STM32L discovery demo is now demonstrating three low power modes - still needs clean up.
Richard Barry
11 years ago
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9001b7b77a
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3d00d47239
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/*
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FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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>>! NOTE: The modification to the GPL is included to allow you to distribute
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>>! a combined work that includes FreeRTOS without being obliged to provide
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>>! kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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*/
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/* Standard includes. */
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#include <limits.h>
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* ST library functions. */
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#include "stm32l1xx.h"
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/*
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* When configCREATE_LOW_POWER_DEMO is set to 1 then the tick interrupt
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* is generated by the wakeup interrupt of the real time clock (RTC). The RTC
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* configuration and handling functions are defined in this file.
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*
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* When configCREATE_LOW_POWER_DEMO is set to 0 the tick interrupt is
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* generated by the standard FreeRTOS Cortex-M port layer, which uses the
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* SysTick timer.
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*/
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#if configCREATE_LOW_POWER_DEMO == 1
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/* The frequency at which TIM2 should run. */
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#define lpCLOCK_INPUT_FREQUENCY ( 1000UL )
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/* Constants required to pend a PendSV interrupt from the tick ISR if the
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preemptive scheduler is being used. These are just standard bits and registers
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within the Cortex-M core itself. */
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define DBGMCU_APB1_FZ ( * ( ( volatile unsigned long * ) 0xE0042008 ) )
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/*-----------------------------------------------------------*/
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/*
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* The tick interrupt is generated by the TIM2 timer. The default interrupt
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* handler cannot be used (even with the TIM2 being handled from the tick hook
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* function) because the default tick interrupt accesses the SysTick registers
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* when configUSE_TICKLESS_IDLE set to 1. TIM2_IRQHandler() is the default name
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* for the TIM2 interrupt handler.
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*/
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void TIM2_IRQHandler( void );
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/*-----------------------------------------------------------*/
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/* Calculate how many clock increments make up a single tick period. */
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static const uint32_t ulReloadValueForOneTick = ( ( lpCLOCK_INPUT_FREQUENCY / configTICK_RATE_HZ ) - 1 );
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/* Holds the maximum number of ticks that can be suppressed - which is
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basically how far into the future an interrupt can be generated. Set during
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initialisation. */
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static portTickType xMaximumPossibleSuppressedTicks = 0;
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/* Flag set from the tick interrupt to allow the sleep processing to know if
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sleep mode was exited because of an RTC interrupt or a different interrupt. */
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static volatile uint32_t ulTickFlag = pdFALSE;
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/* The RTC counter is stopped temporarily each time it is re-programmed. The
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following variable offsets the RTC counter alarm value by the number of RTC
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counts that would typically be missed while the counter was stopped to
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compensate for the lost time. _RB_ Value needs calculating correctly. */
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static uint32_t ulStoppedTimerCompensation = 1;//_RB_ / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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/*-----------------------------------------------------------*/
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/* The tick interrupt handler. This is always the same other than the part that
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clears the interrupt, which is specific to the clock being used to generate the
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tick. */
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void TIM2_IRQHandler( void )
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{
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TIM_ClearITPendingBit( TIM2, TIM_IT_Update );
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TIM_SetAutoreload( TIM2, ( uint16_t ) ulReloadValueForOneTick );
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/* Protect incrementing the tick with an interrupt safe critical section. */
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( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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{
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if( xTaskIncrementTick() != pdFALSE )
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{
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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/* Just completely clear the interrupt mask on exit by passing 0 because
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it is known that this interrupt will only ever execute with the lowest
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possible interrupt priority. */
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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/* The CPU woke because of a tick. */
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ulTickFlag = pdTRUE;
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}
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/*-----------------------------------------------------------*/
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/* Override the default definition of vPortSetupTimerInterrupt() that is weakly
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defined in the FreeRTOS Cortex-M3 port layer with a version that configures the
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wakeup timer of the RTC to generate the tick interrupt. */
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void vPortSetupTimerInterrupt( void )
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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/* Enable the TIM2 clock, which is used to generate long tickless periods
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when the tickless period is finite. */
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RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
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/* Ensure clock stops in debug mode. */
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DBGMCU_APB1_FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP;
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/* Scale the clock so very long tickless periods can be acheived. The
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SysTick is not used as even when its frequency is divided by 8 the maximum
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tickless period with a system clock of 16MHz is only 8.3 seconds. Using
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a prescaled clock on the 16-bit TIM2 allows a tickless period of nearly
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66 seconds, albeit at low resolution. */
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TIM_TimeBaseStructure.TIM_Prescaler = ( uint16_t ) ( SystemCoreClock / lpCLOCK_INPUT_FREQUENCY );
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseStructure.TIM_Period = ( uint16_t ) ( lpCLOCK_INPUT_FREQUENCY / configTICK_RATE_HZ );
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure );
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/* Enable the TIM2 interrupt - used for the tick interrupt when the tickless
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period is finite. */
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NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_LOWEST_INTERRUPT_PRIORITY; /* Must be set to lowest priority. */
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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TIM_ITConfig( TIM2, TIM_IT_Update, ENABLE );
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TIM_SetCounter( TIM2, 0 );
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TIM_Cmd( TIM2, ENABLE );
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/* See the comments where xMaximumPossibleSuppressedTicks is declared. */
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xMaximumPossibleSuppressedTicks = ( ( unsigned long ) USHRT_MAX ) / ulReloadValueForOneTick;
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}
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/*-----------------------------------------------------------*/
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/* Override the default definition of vPortSuppressTicksAndSleep() that is
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weakly defined in the FreeRTOS Cortex-M3 port layer with a version that manages
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the TIM2 interrupt, as the tick is generated from TIM2 compare matches events. */
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void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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{
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uint32_t ulCounterValue, ulCompleteTickPeriods;
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eSleepModeStatus eSleepAction;
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portTickType xModifiableIdleTime;
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const portTickType xRegulatorOffIdleTime = 30;
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/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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/* Make sure the TIM2 reload value does not overflow the counter. */
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if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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{
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xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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}
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/* Calculate the reload value required to wait xExpectedIdleTime tick
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periods. */
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ulCounterValue = ulReloadValueForOneTick * xExpectedIdleTime;
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if( ulCounterValue > ulStoppedTimerCompensation )
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{
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/* Compensate for the fact that TIM2 is going to be stopped
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momentarily. */
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ulCounterValue -= ulStoppedTimerCompensation;
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}
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/* Stop TIM2 momentarily. The time TIM2 is stopped for is accounted for as
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best it can be, but using the tickless mode will inevitably result in some
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tiny drift of the time maintained by the kernel with respect to calendar
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time. */
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TIM_Cmd( TIM2, DISABLE );
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/* Enter a critical section but don't use the taskENTER_CRITICAL() method as
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that will mask interrupts that should exit sleep mode. */
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__asm volatile ( "cpsid i" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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/* The tick flag is set to false before sleeping. If it is true when sleep
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mode is exited then sleep mode was probably exited because the tick was
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suppressed for the entire xExpectedIdleTime period. */
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ulTickFlag = pdFALSE;
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/* If a context switch is pending then abandon the low power entry as
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the context switch might have been pended by an external interrupt that
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requires processing. */
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eSleepAction = eTaskConfirmSleepModeStatus();
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if( eSleepAction == eAbortSleep )
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{
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/* Restart tick. */
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TIM_Cmd( TIM2, ENABLE );
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/* Re-enable interrupts - see comments above the cpsid instruction()
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above. */
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__asm volatile ( "cpsie i" );
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}
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else if( eSleepAction == eNoTasksWaitingTimeout )
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{
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/* There are no running state tasks and no tasks that are blocked with a
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time out. Assuming the application does not care if the tick time slips
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with respect to calendar time then enter a deep sleep that can only be
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woken by (in this demo case) the user button being pushed on the
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STM32L discovery board. */
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configPRE_STOP_PROCESSING();
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PWR_EnterSTOPMode( PWR_Regulator_LowPower, PWR_SLEEPEntry_WFI );
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configPOST_STOP_PROCESSING();
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/* Restart tick. */
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TIM_SetCounter( TIM2, 0 );
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TIM_Cmd( TIM2, ENABLE );
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/* Re-enable interrupts - see comments above the cpsid instruction()
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above. */
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__asm volatile ( "cpsie i" );
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}
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else
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{
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/* Adjust the TIM2 value to take into account that the current time
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slice is already partially complete. */
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configASSERT( ulCounterValue >= TIM_GetCounter( TIM2 ) );
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ulCounterValue -= ( uint32_t ) TIM_GetCounter( TIM2 );
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configASSERT( ulCounterValue < ( uint32_t ) USHRT_MAX );
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configASSERT( ulCounterValue != 0 );
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TIM_SetAutoreload( TIM2, ( uint16_t ) ulCounterValue );
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TIM_SetCounter( TIM2, 0 );
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/* Restart the TIM2. */
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TIM_Cmd( TIM2, ENABLE );
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/* Allow the application to define some pre-sleep processing. */
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xModifiableIdleTime = xExpectedIdleTime;
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configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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means the application defined code has already executed the WAIT
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instruction. */
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if( xModifiableIdleTime > 0 )
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{
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/* The sleep mode used is dependent on the expected idle time
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as the deeper the sleep the longer the wake up time. */
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if( xModifiableIdleTime > xRegulatorOffIdleTime )
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{
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/* A slightly lower power sleep mode with a longer wake up
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time. */
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PWR_EnterSleepMode( PWR_Regulator_LowPower, PWR_SLEEPEntry_WFI );
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}
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else if( pdTRUE )
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{
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/* A slightly higher power sleep mode with a faster wake up
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time. */
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PWR_EnterSleepMode( PWR_Regulator_ON, PWR_SLEEPEntry_WFI );
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}
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}
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/* Allow the application to define some post sleep processing. */
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configPOST_SLEEP_PROCESSING( xModifiableIdleTime );
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/* Stop TIM2. Again, the time the SysTick is stopped for is accounted
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for as best it can be, but using the tickless mode will inevitably
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result in some tiny drift of the time maintained by the kernel with
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respect to calendar time. */
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TIM_Cmd( TIM2, DISABLE );
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/* Re-enable interrupts - see comments above the cpsid instruction()
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above. */
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__asm volatile ( "cpsie i" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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if( ulTickFlag != pdFALSE )
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{
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/* The tick interrupt has already executed, although because this
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function is called with the scheduler suspended the actual tick
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processing will not occur until after this function has exited.
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Reset the reload value with whatever remains of this tick period. */
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configASSERT( ulReloadValueForOneTick >= ( uint32_t ) TIM_GetCounter( TIM2 ) );
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ulCounterValue = ulReloadValueForOneTick - ( uint32_t ) TIM_GetCounter( TIM2 );
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configASSERT( ulCounterValue <= ( uint32_t ) USHRT_MAX );
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configASSERT( ulCounterValue != 0 );
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TIM_SetAutoreload( TIM2, ( uint16_t ) ulCounterValue );
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TIM_SetCounter( TIM2, 0 );
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/* The tick interrupt handler will already have pended the tick
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processing in the kernel. As the pending tick will be processed as
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soon as this function exits, the tick value maintained by the tick
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is stepped forward by one less than the time spent sleeping. The
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actual stepping of the tick appears later in this function. */
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ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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}
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else
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{
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/* Something other than the tick interrupt ended the sleep. How
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many complete tick periods passed while the processor was
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sleeping? */
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ulCompleteTickPeriods = ( ( uint32_t ) TIM_GetCounter( TIM2 ) ) / ulReloadValueForOneTick;
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/* The reload value is set to whatever fraction of a single tick
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period remains. */
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configASSERT( ( ( uint32_t ) TIM_GetCounter( TIM2 ) ) >= ( ulCompleteTickPeriods * ulReloadValueForOneTick ) );
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ulCounterValue = ( ( uint32_t ) TIM_GetCounter( TIM2 ) ) - ( ulCompleteTickPeriods * ulReloadValueForOneTick );
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configASSERT( ulCounterValue <= ( uint32_t ) USHRT_MAX );
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if( ulCounterValue == 0 )
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{
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/* There is no fraction remaining. */
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ulCounterValue = ulReloadValueForOneTick;
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ulCompleteTickPeriods++;
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}
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TIM_SetAutoreload( TIM2, ( uint16_t ) ulCounterValue );
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TIM_SetCounter( TIM2, 0 );
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}
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/* Restart TIM2 so it runs up to the reload value. The reload value
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will get set to the value required to generate exactly one tick period
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the next time the TIM2 interrupt executes. */
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TIM_Cmd( TIM2, ENABLE );
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/* Wind the tick forward by the number of tick periods that the CPU
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remained in a low power state. */
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vTaskStepTick( ulCompleteTickPeriods );
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}
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}
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#endif /* configCREATE_LOW_POWER_DEMO == 1 */
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