@ -12,6 +12,15 @@ static hwtimer_t xKernelTimer;
uint32_t ulPortYieldRequired [ portMAX_CORE_COUNT ] = { pdFALSE } ;
/* When this port was designed, it was assumed that pxCurrentTCBs would always
exist and that it would always be an array containing pointers to the current
TCBs for each core . In v11 , this is not the case ; if we are only running one
core , the symbol is pxCurrentTCB instead . Therefore , this port adds a layer
of indirection - we populate this pointer - to - pointer in the RTOS kernel entry
function below . This makes this port agnostic to whether it is running on SMP
or singlecore RTOS . */
void * * xcorePvtTCBContainer ;
/*-----------------------------------------------------------*/
void vIntercoreInterruptISR ( void )
@ -140,6 +149,28 @@ DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
}
# endif
/* Populate the TCBContainer depending on whether we're singlecore or SMP */
# if ( configNUMBER_OF_CORES == 1 )
{
asm volatile (
" ldaw %0, dp[pxCurrentTCB] \n \t "
: " =r " ( xcorePvtTCBContainer )
: /* no inputs */
: /* no clobbers */
) ;
}
# else
{
asm volatile (
" ldaw %0, dp[pxCurrentTCBs] \n \t "
: " =r " ( xcorePvtTCBContainer )
: /* no inputs */
: /* no clobbers */
) ;
}
# endif
debug_printf ( " FreeRTOS Core %d initialized \n " , xCoreID ) ;
/*
@ -147,8 +178,8 @@ DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
* to run and jump into it .
*/
asm volatile (
" mov r6, %0 \n \t " /* R6 must be the FreeRTOS core ID */
" ld aw r5, dp[pxCurrentTCBs ]\n \t " /* R5 must be the TCB list which is indexed by R6 */
" mov r6, %0 \n \t " /* R6 must be the FreeRTOS core ID . In singlecore this is always 0. */
" ld w r5, dp[xcorePvtTCBContainer ]\n \t " /* R5 must be the TCB list which is indexed by R6 */
" bu _freertos_restore_ctx \n \t "
: /* no outputs */
: " r " ( xCoreID )