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Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC.

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pull/4/head
Richard Barry 8 years ago
parent 0a7a0a79d6
commit 0f85ead175
2 changed files with 6 additions and 6 deletions
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4
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
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@ -254,7 +254,7 @@ uint32_t ulAPSR;
/* Only continue if the CPU is not in User mode. The CPU must be in a /* Only continue if the CPU is not in User mode. The CPU must be in a
Privileged mode for the scheduler to start. */ Privileged mode for the scheduler to start. */
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
ulAPSR &= portAPSR_MODE_BITS_MASK; ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE ); configASSERT( ulAPSR != portAPSR_USER_MODE );
@ -354,7 +354,7 @@ uint32_t ulInitialFPSCR = 0;
ulPortTaskHasFPUContext = pdTRUE; ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */ /* Initialise the floating point status register. */
__asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

8
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
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@ -128,7 +128,7 @@ extern volatile uint32_t ulPortYieldRequired; \
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
#define portYIELD() __asm volatile ( "SWI 0 \n" \ #define portYIELD() __asm volatile ( "SWI 0 \n" \
"ISB " ); "ISB " ::: "memory" );
/*----------------------------------------------------------- /*-----------------------------------------------------------
@ -148,16 +148,16 @@ extern void vPortInstallFreeRTOSVectorTable( void );
globally enable and disable interrupts. */ globally enable and disable interrupts. */
#define portENTER_CRITICAL() vPortEnterCritical(); #define portENTER_CRITICAL() vPortEnterCritical();
#define portEXIT_CRITICAL() vPortExitCritical(); #define portEXIT_CRITICAL() vPortExitCritical();
#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ); #define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ::: "memory" );
#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \ #define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
"DSB \n" \ "DSB \n" \
"ISB " ); "ISB " ::: "memory" );
__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
{ {
volatile uint32_t ulCPSR; volatile uint32_t ulCPSR;
__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) ); __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
ulCPSR &= portINTERRUPT_ENABLE_BIT; ulCPSR &= portINTERRUPT_ENABLE_BIT;
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
return ulCPSR; return ulCPSR;

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