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@ -1,34 +1,76 @@
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/******************************************************************
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***** *****
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***** Ver.: 1.0 *****
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***** Date: 07/05/2001 *****
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***** Auth: Andreas Dannenberg *****
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***** HTWK Leipzig *****
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***** university of applied sciences *****
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***** Germany *****
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***** Func: ethernet packet-driver for use with LAN- *****
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***** controller CS8900 from Crystal/Cirrus Logic *****
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***** *****
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***** Keil: Module modified for use with Philips *****
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***** LPC2378 EMAC Ethernet controller *****
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***** *****
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******************************************************************/
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/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */
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/*
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FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License (version 2) as published
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by the Free Software Foundation and modified by the FreeRTOS exception.
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**NOTE** The exception to the GPL is included to allow you to distribute a
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combined work that includes FreeRTOS.org without being obliged to provide
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the source code for any proprietary components. Alternative commercial
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license and support terms are also available upon request. See the
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licensing section of http://www.FreeRTOS.org for full details.
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FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
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Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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***************************************************************************
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* *
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* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
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* *
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* This is a concise, step by step, 'hands on' guide that describes both *
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* general multitasking concepts and FreeRTOS specifics. It presents and *
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* explains numerous examples that are written using the FreeRTOS API. *
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* Full source code for all the examples is provided in an accompanying *
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* .zip file. *
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* *
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***************************************************************************
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1 tab == 4 spaces!
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Please ensure to read the configuration and relevant port sections of the
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online documentation.
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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/* Kernel includes. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#include "semphr.h"
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/* Hardware specific includes. */
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#include "LPC17xx_defs.h"
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#include "EthDev_LPC17xx.h"
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#define emacPINSEL2_VALUE 0x50150105
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/* Time to wait between each inspection of the link status. */
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#define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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/* Short delay used in several places during the initialisation process. */
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#define emacSHORT_DELAY ( 2 )
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/* Hardware specific bit definitions. */
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#define emacLINK_ESTABLISHED ( 0x0001 )
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#define emacFULL_DUPLEX_ENABLED ( 0x0004 )
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#define emac10BASE_T_MODE ( 0x0002 )
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#define emacPINSEL2_VALUE 0x50150105
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/* If no buffers are available, then wait this long before looking again.... */
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#define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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@ -36,24 +78,63 @@
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/* ...and don't look more than this many times. */
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#define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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/* Index to the Tx descriptor that is always used first for every Tx. The second
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descriptor is then used to re-send in order to speed up the uIP Tx process. */
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#define emacTX_DESC_INDEX ( 0 )
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/* The semaphore used to wake the uIP task when data arives. */
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extern xSemaphoreHandle xEMACSemaphore;
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static unsigned short *rptr;
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static unsigned short *tptr;
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/*-----------------------------------------------------------*/
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/*
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* Configure both the Rx and Tx descriptors during the init process.
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*/
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static void prvInitDescriptors( void );
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/*
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* Setup the IO and peripherals required for Ethernet communication.
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*/
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static void prvSetupEMACHardware( void );
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/*
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* Control the auto negotiate process.
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*/
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static void prvConfigurePHY( void );
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/*
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* Wait for a link to be established, then setup the PHY according to the link
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* parameters.
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*/
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static long prvSetupLinkStatus( void );
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/*
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* Search the pool of buffers to find one that is free. If a buffer is found
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* mark it as in use before returning its address.
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*/
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static unsigned char *prvGetNextBuffer( void );
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/*
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* Return an allocated buffer to the pool of free buffers.
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*/
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static void prvReturnBuffer( unsigned char *pucBuffer );
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/* Each ucBufferInUse index corresponds to a position in the same index in the
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ucMACBuffers array. If the index contains a 1 then the buffer within
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ucMACBuffers is in use, if it contains a 0 then the buffer is free. */
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/*
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* Send lValue to the lPhyReg within the PHY.
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*/
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static long prvWritePHY( long lPhyReg, long lValue );
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/*
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* Read a value from ucPhyReg within the PHY. *plStatus will be set to
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* pdFALSE if there is an error.
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*/
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static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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/*-----------------------------------------------------------*/
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/* The semaphore used to wake the uIP task when data arrives. */
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extern xSemaphoreHandle xEMACSemaphore;
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/* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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If the index contains a 1 then the buffer within pool is in use, if it
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contains a 0 then the buffer is free. */
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static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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/* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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@ -66,64 +147,59 @@ static unsigned short usSendLen = 0;
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/*-----------------------------------------------------------*/
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int write_PHY( long lPhyReg, long lValue )
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long lEMACInit( void )
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{
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const long lMaxTime = 10;
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long x;
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long lReturn = pdPASS;
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volatile unsigned long regv, tout;
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unsigned long ulID1, ulID2;
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MAC_MADR = DP83848C_DEF_ADR | lPhyReg;
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MAC_MWTD = lValue;
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/* Reset peripherals, configure port pins and registers. */
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prvSetupEMACHardware();
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x = 0;
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for( x = 0; x < lMaxTime; x++ )
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{
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if( ( MAC_MIND & MIND_BUSY ) == 0 )
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/* Check the PHY part number is as expected. */
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ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
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{
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/* Operation has finished. */
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break;
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}
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/* Set the Ethernet MAC Address registers */
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MAC_SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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MAC_SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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MAC_SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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vTaskDelay( emacSHORT_DELAY );
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}
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/* Initialize Tx and Rx DMA Descriptors */
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prvInitDescriptors();
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if( x < lMaxTime )
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{
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return pdPASS;
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/* Receive broadcast and perfect match packets */
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MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Setup the PHY. */
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prvConfigurePHY();
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}
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else
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{
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return pdFAIL;
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lReturn = pdFAIL;
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}
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}
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/*-----------------------------------------------------------*/
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unsigned short read_PHY( unsigned char ucPhyReg, long *plStatus )
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{
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long x;
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const long lMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | ucPhyReg;
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MAC_MCMD = MCMD_READ;
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for( x = 0; x < lMaxTime; x++ )
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{
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/* Operation has finished. */
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if( ( MAC_MIND & MIND_BUSY ) == 0 )
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/* Check the link status. */
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if( lReturn == pdPASS )
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{
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break;
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lReturn = prvSetupLinkStatus();
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}
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vTaskDelay( emacSHORT_DELAY );
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}
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if( lReturn == pdPASS )
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{
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/* Initialise uip_buf to ensure it points somewhere valid. */
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uip_buf = prvGetNextBuffer();
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MAC_MCMD = 0;
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/* Reset all interrupts */
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MAC_INTCLEAR = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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if( x >= lMaxTime )
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{
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*plStatus = pdFAIL;
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/* Enable receive and transmit mode of MAC Ethernet core */
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MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
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MAC_MAC1 |= MAC1_REC_EN;
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}
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return( MAC_MRDD );
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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@ -246,14 +322,14 @@ long x, lDummy;
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MAC_SUPP = 0;
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/* Put the PHY in reset mode */
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write_PHY( PHY_REG_BMCR, MCFG_RES_MII );
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write_PHY( PHY_REG_BMCR, MCFG_RES_MII );
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prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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/* Wait for hardware reset to end. */
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for( x = 0; x < 100; x++ )
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{
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vTaskDelay( emacSHORT_DELAY * 5 );
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us = read_PHY( PHY_REG_BMCR, &lDummy );
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us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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if( !( us & MCFG_RES_MII ) )
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{
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/* Reset complete */
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|
@ -269,13 +345,13 @@ unsigned short us;
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long x, lDummy;
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/* Auto negotiate the configuration. */
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if( write_PHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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{
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vTaskDelay( emacSHORT_DELAY * 5 );
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for( x = 0; x < 10; x++ )
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{
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us = read_PHY( PHY_REG_BMSR, &lDummy );
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|
us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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if( us & PHY_AUTO_NEG_COMPLETE )
|
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|
{
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|
|
@ -293,9 +369,10 @@ static long prvSetupLinkStatus( void )
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|
|
long lReturn = pdFAIL, x;
|
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|
|
unsigned short usLinkStatus;
|
|
|
|
|
|
|
|
|
|
/* Wait with timeout for the link to be established. */
|
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|
|
for( x = 0; x < 10; x++ )
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|
{
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|
|
usLinkStatus = read_PHY( PHY_REG_STS, &lReturn );
|
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|
|
usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );
|
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|
|
if( usLinkStatus & emacLINK_ESTABLISHED )
|
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|
{
|
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|
|
/* Link is established. */
|
|
|
|
|
@ -339,62 +416,6 @@ unsigned short usLinkStatus;
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|
|
}
|
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
|
|
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|
|
long Init_EMAC( void )
|
|
|
|
|
{
|
|
|
|
|
long lReturn = pdPASS;
|
|
|
|
|
volatile unsigned long regv, tout;
|
|
|
|
|
unsigned long ulID1, ulID2;
|
|
|
|
|
|
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/* Reset peripherals, configure port pins and registers. */
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prvSetupEMACHardware();
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/* Check if connected to a DP83848C PHY. */
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ulID1 = read_PHY( PHY_REG_IDR1, &lReturn );
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ulID2 = read_PHY( PHY_REG_IDR2, &lReturn );
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if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
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{
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/* Set the Ethernet MAC Address registers */
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MAC_SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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MAC_SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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MAC_SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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/* Initialize Tx and Rx DMA Descriptors */
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prvInitDescriptors();
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/* Receive Broadcast and Perfect Match Packets */
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MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Setup the PHY. */
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prvConfigurePHY();
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}
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else
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{
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lReturn = pdFAIL;
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}
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/* Check the link status. */
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if( lReturn == pdPASS )
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{
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lReturn = prvSetupLinkStatus();
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}
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if( lReturn == pdPASS )
|
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|
|
|
{
|
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|
|
/* Initialise uip_buf to ensure it points somewhere valid. */
|
|
|
|
|
uip_buf = prvGetNextBuffer();
|
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|
|
/* Reset all interrupts */
|
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|
|
MAC_INTCLEAR = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
|
|
|
|
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|
|
|
|
|
/* Enable receive and transmit mode of MAC Ethernet core */
|
|
|
|
|
MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
|
|
|
|
|
MAC_MAC1 |= MAC1_REC_EN;
|
|
|
|
|
}
|
|
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|
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|
|
return lReturn;
|
|
|
|
|
}
|
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
|
|
|
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|
|
static void prvReturnBuffer( unsigned char *pucBuffer )
|
|
|
|
|
{
|
|
|
|
|
unsigned long ul;
|
|
|
|
|
@ -480,10 +501,66 @@ unsigned long ulAttempts = 0UL;
|
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|
|
}
|
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
|
|
|
|
|
|
static long prvWritePHY( long lPhyReg, long lValue )
|
|
|
|
|
{
|
|
|
|
|
const long lMaxTime = 10;
|
|
|
|
|
long x;
|
|
|
|
|
|
|
|
|
|
static char c[ 256 ] = { 0 };
|
|
|
|
|
static int i = 0;
|
|
|
|
|
MAC_MADR = DP83848C_DEF_ADR | lPhyReg;
|
|
|
|
|
MAC_MWTD = lValue;
|
|
|
|
|
|
|
|
|
|
x = 0;
|
|
|
|
|
for( x = 0; x < lMaxTime; x++ )
|
|
|
|
|
{
|
|
|
|
|
if( ( MAC_MIND & MIND_BUSY ) == 0 )
|
|
|
|
|
{
|
|
|
|
|
/* Operation has finished. */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vTaskDelay( emacSHORT_DELAY );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if( x < lMaxTime )
|
|
|
|
|
{
|
|
|
|
|
return pdPASS;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
return pdFAIL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
|
|
|
|
|
|
static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
|
|
|
|
|
{
|
|
|
|
|
long x;
|
|
|
|
|
const long lMaxTime = 10;
|
|
|
|
|
|
|
|
|
|
MAC_MADR = DP83848C_DEF_ADR | ucPhyReg;
|
|
|
|
|
MAC_MCMD = MCMD_READ;
|
|
|
|
|
|
|
|
|
|
for( x = 0; x < lMaxTime; x++ )
|
|
|
|
|
{
|
|
|
|
|
/* Operation has finished. */
|
|
|
|
|
if( ( MAC_MIND & MIND_BUSY ) == 0 )
|
|
|
|
|
{
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vTaskDelay( emacSHORT_DELAY );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
MAC_MCMD = 0;
|
|
|
|
|
|
|
|
|
|
if( x >= lMaxTime )
|
|
|
|
|
{
|
|
|
|
|
*plStatus = pdFAIL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return( MAC_MRDD );
|
|
|
|
|
}
|
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
|
|
|
|
|
|
void vEMAC_ISR( void )
|
|
|
|
|
{
|
|
|
|
|
@ -505,8 +582,6 @@ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
|
|
|
|
|
{
|
|
|
|
|
if( usSendLen > 0 )
|
|
|
|
|
{
|
|
|
|
|
if( i < 255 )
|
|
|
|
|
c[ i++ ] = 1;
|
|
|
|
|
/* Send the data again, using the second descriptor. As there are
|
|
|
|
|
only two descriptors the index is set back to 0. */
|
|
|
|
|
TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
|
|
|
|
|
@ -519,9 +594,6 @@ if( i < 255 )
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if( i < 255 )
|
|
|
|
|
c[ i++ ] = 1;
|
|
|
|
|
|
|
|
|
|
/* The Tx buffer is no longer required. */
|
|
|
|
|
prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
|
|
|
|
|
TX_DESC_PACKET( emacTX_DESC_INDEX ) = NULL;
|
|
|
|
|
|
Richard Barry
16 years ago