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Update the Xilinx UltraScale+ demo project to use the BSP and hardware platform generated by the 2016.1 version of the SDK.

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pull/4/head
Richard Barry 9 years ago
parent 11fe9de0f0
commit 0cb71ee9ce
12 changed files with 140 additions and 225 deletions
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164
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
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<option id="xilinx.gnu.c.linker.option.lscript.1953060494" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
<option id="xilinx.gnu.c.linker.option.lscript.1039423151" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
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<tool id="xilinx.gnu.arm.a53.size.release.1941542703" name="ARM A53 Print Size" superClass="xilinx.gnu.arm.a53.size.release"/>
<tool id="xilinx.gnu.arm.a53.size.release.174718103" name="ARM A53 Print Size" superClass="xilinx.gnu.arm.a53.size.release"/>
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</folderInfo>
</configuration>
@ -165,29 +147,21 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="RTOSDemo_A53.xilinx.gnu.arm.a53.exe.32800772" name="Xilinx ARM A53 Executable" projectType="xilinx.gnu.arm.a53.exe"/>
<project id="RTOSDemo_A53.xilinx.gnu.arm.a53.exe.2053650162" name="Xilinx ARM A53 Executable" projectType="xilinx.gnu.arm.a53.exe"/>
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<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="xilinx.gnu.arm.a53.exe.debug.1895997290;xilinx.gnu.arm.a53.exe.debug.1895997290.">
<scannerConfigBuildInfo instanceId="xilinx.gnu.arm.a53.exe.debug.741188110;xilinx.gnu.arm.a53.exe.debug.741188110.">
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</storageModule>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/RTOSDemo_A53"/>
</configuration>
<configuration configurationName="Release">
<resource resourceType="PROJECT" workspacePath="/RTOSDemo_A53"/>
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</cproject>

96
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project
Unescape Escape View File

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo_A53</name>
<comment>Created by SDK v2015.1. RTOSDemo_A53_bsp - psu_cortexa53_0</comment>
<comment>Created by SDK v2016.1. RTOSDemo_A53_bsp - psu_cortexa53_0</comment>
<projects>
<project>RTOSDemo_A53_bsp</project>
</projects>
@ -42,88 +42,34 @@
</linkedResources>
<filteredResources>
<filter>
<id>1450692515382</id>
<id>1461847194341</id>
<name>src/FreeRTOS_Source</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-event_groups.c</arguments>
</matcher>
</filter>
<filter>
<id>1450692515402</id>
<name>src/FreeRTOS_Source</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-list.c</arguments>
</matcher>
</filter>
<filter>
<id>1450692515422</id>
<name>src/FreeRTOS_Source</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-queue.c</arguments>
</matcher>
</filter>
<filter>
<id>1450692515432</id>
<name>src/FreeRTOS_Source</name>
<type>5</type>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-tasks.c</arguments>
<arguments>1.0-name-matches-false-false-croutine.c</arguments>
</matcher>
</filter>
<filter>
<id>1450692515452</id>
<name>src/FreeRTOS_Source</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-timers.c</arguments>
</matcher>
</filter>
<filter>
<id>1450692515452</id>
<name>src/FreeRTOS_Source</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-include</arguments>
</matcher>
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<id>1450692515462</id>
<name>src/FreeRTOS_Source</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-portable</arguments>
</matcher>
</filter>
<filter>
<id>1450692538900</id>
<id>1461847221751</id>
<name>src/FreeRTOS_Source/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-MemMang</arguments>
<arguments>1.0-name-matches-false-false-GCC</arguments>
</matcher>
</filter>
<filter>
<id>1450692538920</id>
<id>1461847221761</id>
<name>src/FreeRTOS_Source/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-GCC</arguments>
<arguments>1.0-name-matches-false-false-MemMang</arguments>
</matcher>
</filter>
<filter>
<id>1450693252106</id>
<id>1461847438191</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -132,7 +78,7 @@
</matcher>
</filter>
<filter>
<id>1450693252106</id>
<id>1461847438201</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -141,7 +87,7 @@
</matcher>
</filter>
<filter>
<id>1450693252116</id>
<id>1461847438221</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -150,7 +96,7 @@
</matcher>
</filter>
<filter>
<id>1450693252116</id>
<id>1461847438241</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -159,7 +105,7 @@
</matcher>
</filter>
<filter>
<id>1450693252126</id>
<id>1461847438251</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -168,7 +114,7 @@
</matcher>
</filter>
<filter>
<id>1450693252126</id>
<id>1461847438251</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -177,7 +123,7 @@
</matcher>
</filter>
<filter>
<id>1450693252136</id>
<id>1461847438261</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -186,7 +132,7 @@
</matcher>
</filter>
<filter>
<id>1450693252136</id>
<id>1461847438261</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -195,7 +141,7 @@
</matcher>
</filter>
<filter>
<id>1450693252146</id>
<id>1461847438271</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -204,7 +150,7 @@
</matcher>
</filter>
<filter>
<id>1450693252146</id>
<id>1461847438281</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -213,7 +159,7 @@
</matcher>
</filter>
<filter>
<id>1450693252146</id>
<id>1461847438301</id>
<name>src/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -222,7 +168,7 @@
</matcher>
</filter>
<filter>
<id>1450692572845</id>
<id>1461847264041</id>
<name>src/FreeRTOS_Source/portable/GCC</name>
<type>9</type>
<matcher>
@ -231,7 +177,7 @@
</matcher>
</filter>
<filter>
<id>1450692711859</id>
<id>1461847244679</id>
<name>src/FreeRTOS_Source/portable/MemMang</name>
<type>5</type>
<matcher>

79
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld
Unescape Escape View File

@ -22,19 +22,12 @@ _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
MEMORY
{
psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x10000000
psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x80000000
psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000
psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000
psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000
psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000
psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000
psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000
psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000
psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000
}
/* Specify the default entry point to the program */
@ -58,23 +51,23 @@ SECTIONS
*(.glue_7t)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.init (ALIGN(64)) : {
KEEP (*(.init))
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.fini (ALIGN(64)) : {
KEEP (*(.fini))
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.interp : {
KEEP (*(.interp))
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.note-ABI-tag : {
KEEP (*(.note-ABI-tag))
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.rodata : {
. = ALIGN(64);
@ -83,7 +76,7 @@ SECTIONS
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.rodata1 : {
. = ALIGN(64);
@ -91,7 +84,7 @@ SECTIONS
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.sdata2 : {
. = ALIGN(64);
@ -100,7 +93,7 @@ SECTIONS
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.sbss2 : {
. = ALIGN(64);
@ -109,7 +102,7 @@ SECTIONS
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.data : {
. = ALIGN(64);
@ -121,7 +114,7 @@ SECTIONS
*(.got)
*(.got.plt)
__data_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.data1 : {
. = ALIGN(64);
@ -129,19 +122,19 @@ SECTIONS
*(.data1)
*(.data1.*)
__data1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.got : {
*(.got)
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.got1 : {
*(.got1)
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.got2 : {
*(.got2)
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.ctors : {
. = ALIGN(64);
@ -153,7 +146,7 @@ SECTIONS
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.dtors : {
. = ALIGN(64);
@ -165,52 +158,52 @@ SECTIONS
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.mmu_tbl0 (ALIGN(4096)) : {
__mmu_tbl0_start = .;
*(.mmu_tbl0)
__mmu_tbl0_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.mmu_tbl1 (ALIGN(4096)) : {
__mmu_tbl1_start = .;
*(.mmu_tbl1)
__mmu_tbl1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.mmu_tbl2 (ALIGN(4096)) : {
__mmu_tbl2_start = .;
*(.mmu_tbl2)
__mmu_tbl2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.preinit_array : {
. = ALIGN(64);
@ -218,7 +211,7 @@ SECTIONS
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.init_array : {
. = ALIGN(64);
@ -226,7 +219,7 @@ SECTIONS
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.fini_array : {
. = ALIGN(64);
@ -234,13 +227,13 @@ SECTIONS
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.sdata : {
. = ALIGN(64);
@ -249,7 +242,7 @@ SECTIONS
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
. = ALIGN(64);
@ -259,7 +252,7 @@ SECTIONS
*(.gnu.linkonce.sb.*)
. = ALIGN(64);
__sbss_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.tdata : {
. = ALIGN(64);
@ -268,7 +261,7 @@ SECTIONS
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.tbss : {
. = ALIGN(64);
@ -277,7 +270,7 @@ SECTIONS
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
. = ALIGN(64);
@ -288,7 +281,7 @@ SECTIONS
*(COMMON)
. = ALIGN(64);
__bss_end__ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
@ -304,7 +297,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(64);
@ -323,7 +316,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
. += _EL0_STACK_SIZE;
. = ALIGN(64);
__el0_stack = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
} > psu_ddr_0_S_AXI_BASEADDR
_end = .;
}

22
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.c
Unescape Escape View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -18,8 +18,8 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
@ -36,10 +36,12 @@
#include "platform_config.h"
/*
* Uncomment the following line if ps7 init source files are added in the
* source directory for compiling example outside of SDK.
* Uncomment one of the following two lines, depending on the target,
* if ps7/psu init source files are added in the source directory for
* compiling example outside of SDK.
*/
/*#include "ps7_init.h"*/
/*#include "psu_init.h"*/
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
@ -77,9 +79,7 @@ init_uart()
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
#ifdef STDOUT_IS_PS7_UART
/* Bootrom/BSP configures PS7 UART to 115200 bps */
#endif
/* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
}
void
@ -87,11 +87,13 @@ init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment the following line and also #include "ps7_init.h" at the top.
* Make sure that the ps7_init.c and ps7_init.h files are included
* uncomment one of the following two lines and also #include "ps7_init.h"
* or #include "ps7_init.h" at the top, depending on the target.
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
* along with this example source files for compilation.
*/
/* ps7_init();*/
/* psu_init();*/
enable_caches();
init_uart();
}

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.h
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@ -18,8 +18,8 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.tcl → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
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0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/system.hdf → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf
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