Split the LPC18xx FreeRTOS+UDP drivers between those that use the LPCOpen library and those that use the older CMSIS library.
Richard Barry
12 years ago
parent
a1145a1b78
commit
0ca2110982
@ -0,0 +1,310 @@
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/*
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* FreeRTOS+UDP V1.0.0 (C) 2013 Real Time Engineers ltd.
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*
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* This file is part of the FreeRTOS+UDP distribution. The FreeRTOS+UDP license
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* terms are different to the FreeRTOS license terms.
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*
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* FreeRTOS+UDP uses a dual license model that allows the software to be used
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* under a pure GPL open source license (as opposed to the modified GPL license
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* under which FreeRTOS is distributed) or a commercial license. Details of
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* both license options follow:
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*
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* - Open source licensing -
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* FreeRTOS+UDP is a free download and may be used, modified, evaluated and
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* distributed without charge provided the user adheres to version two of the
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* GNU General Public License (GPL) and does not remove the copyright notice or
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* this text. The GPL V2 text is available on the gnu.org web site, and on the
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* following URL: http://www.FreeRTOS.org/gpl-2.0.txt.
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*
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* - Commercial licensing -
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* Businesses and individuals that for commercial or other reasons cannot comply
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* with the terms of the GPL V2 license must obtain a commercial license before
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* incorporating FreeRTOS+UDP into proprietary software for distribution in any
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* form. Commercial licenses can be purchased from http://shop.freertos.org/udp
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* and do not require any source files to be changed.
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*
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* FreeRTOS+UDP is distributed in the hope that it will be useful. You cannot
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* use FreeRTOS+UDP unless you agree that you use the software 'as is'.
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* FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied
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* warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they
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* implied, expressed, or statutory.
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*
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* 1 tab == 4 spaces!
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*
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* http://www.FreeRTOS.org
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* http://www.FreeRTOS.org/udp
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*
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*/
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/* Standard includes. */
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#include <stdint.h>
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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#include "semphr.h"
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/* FreeRTOS+UDP includes. */
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#include "FreeRTOS_UDP_IP.h"
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#include "FreeRTOS_IP_Private.h"
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#include "FreeRTOS_Sockets.h"
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#include "NetworkBufferManagement.h"
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/* Driver includes. */
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#include "lpc18xx_emac.h"
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/* Demo includes. */
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#include "NetworkInterface.h"
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#if configMAC_INTERRUPT_PRIORITY > configMAC_INTERRUPT_PRIORITY
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#error configMAC_INTERRUPT_PRIORITY must be greater than or equal to configMAC_INTERRUPT_PRIORITY (higher numbers mean lower logical priority)
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#endif
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#ifndef configNUM_RX_ETHERNET_DMA_DESCRIPTORS
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#error configNUM_RX_ETHERNET_DMA_DESCRIPTORS must be defined in FreeRTOSConfig.h to set the number of RX DMA descriptors
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#endif
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#ifndef configNUM_TX_ETHERNET_DMA_DESCRIPTORS
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#error configNUM_TX_ETHERNET_DMA_DESCRIPTORS must be defined in FreeRTOSConfig.h to set the number of TX DMA descriptors
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#endif
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/* If a packet cannot be sent immediately then the task performing the send
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operation will be held in the Blocked state (so other tasks can execute) for
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niTX_BUFFER_FREE_WAIT ticks. It will do this a maximum of niMAX_TX_ATTEMPTS
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before giving up. */
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#define niTX_BUFFER_FREE_WAIT ( ( portTickType ) 2UL / portTICK_RATE_MS )
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#define niMAX_TX_ATTEMPTS ( 5 )
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/*-----------------------------------------------------------*/
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/*
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* A deferred interrupt handler task that processes received frames.
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*/
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static void prvEMACDeferredInterruptHandlerTask( void *pvParameters );
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/*-----------------------------------------------------------*/
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/* The queue used to communicate Ethernet events to the IP task. */
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extern xQueueHandle xNetworkEventQueue;
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/* The semaphore used to wake the deferred interrupt handler task when an Rx
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interrupt is received. */
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static xSemaphoreHandle xEMACRxEventSemaphore = NULL;
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceInitialise( void )
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{
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EMAC_CFG_Type Emac_Config;
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portBASE_TYPE xReturn;
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extern uint8_t ucMACAddress[ 6 ];
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Emac_Config.pbEMAC_Addr = ucMACAddress;
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xReturn = EMAC_Init( &Emac_Config );
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if( xReturn == pdPASS )
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{
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LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE;
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/* Create the event semaphore if it has not already been created. */
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if( xEMACRxEventSemaphore == NULL )
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{
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vSemaphoreCreateBinary( xEMACRxEventSemaphore );
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#if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1
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{
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/* If the trace recorder code is included name the semaphore for
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viewing in FreeRTOS+Trace. */
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vTraceSetQueueName( xEMACRxEventSemaphore, "MAC_RX" );
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}
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#endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 */
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}
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configASSERT( xEMACRxEventSemaphore );
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/* The Rx deferred interrupt handler task is created at the highest
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possible priority to ensure the interrupt handler can return directly to
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it no matter which task was running when the interrupt occurred. */
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xTaskCreate( prvEMACDeferredInterruptHandlerTask, /* The function that implements the task. */
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( const signed char * const ) "MACTsk",
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configMINIMAL_STACK_SIZE, /* Stack allocated to the task (defined in words, not bytes). */
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NULL, /* The task parameter is not used. */
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configMAX_PRIORITIES - 1, /* The priority assigned to the task. */
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NULL ); /* The handle is not required, so NULL is passed. */
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/* Enable the interrupt and set its priority as configured. THIS
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DRIVER REQUIRES configMAC_INTERRUPT_PRIORITY TO BE DEFINED, PREFERABLY
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IN FreeRTOSConfig.h. */
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NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY );
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NVIC_EnableIRQ( ETHERNET_IRQn );
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
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{
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portBASE_TYPE xReturn = pdFAIL;
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int32_t x;
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/* Attempt to obtain access to a Tx descriptor. */
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for( x = 0; x < niMAX_TX_ATTEMPTS; x++ )
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{
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if( EMAC_CheckTransmitIndex() == TRUE )
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{
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/* Assign the buffer being transmitted to the Tx descriptor. */
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EMAC_SetNextPacketToSend( pxNetworkBuffer->pucEthernetBuffer );
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/* The EMAC now owns the buffer and will free it when it has been
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transmitted. Set pucBuffer to NULL to ensure the buffer is not
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freed when the network buffer structure is returned to the pool
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of network buffers. */
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pxNetworkBuffer->pucEthernetBuffer = NULL;
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/* Initiate the Tx. */
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EMAC_StartTransmitNextBuffer( pxNetworkBuffer->xDataLength );
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iptraceNETWORK_INTERFACE_TRANSMIT();
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/* The Tx has been initiated. */
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xReturn = pdPASS;
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break;
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}
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else
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{
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iptraceWAITING_FOR_TX_DMA_DESCRIPTOR();
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vTaskDelay( niTX_BUFFER_FREE_WAIT );
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}
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}
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/* Finished with the network buffer. */
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vNetworkBufferRelease( pxNetworkBuffer );
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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void ETH_IRQHandler( void )
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{
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uint32_t ulInterruptCause;
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ulInterruptCause = LPC_ETHERNET->DMA_STAT ;
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/* Clear the interrupt. */
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LPC_ETHERNET->DMA_STAT |= ( DMA_INT_NOR_SUM | DMA_INT_RECEIVE );
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/* Clear fatal error conditions. NOTE: The driver does not clear all
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errors, only those actually experienced. For future reference, range
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errors are not actually errors so can be ignored. */
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if( ( ulInterruptCause & ( 1 << 13 ) ) != 0U )
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{
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LPC_ETHERNET->DMA_STAT |= ( 1 << 13 );
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}
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/* Unblock the deferred interrupt handler task if the event was an Rx. */
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if( ( ulInterruptCause & DMA_INT_RECEIVE ) != 0UL )
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{
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xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL );
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}
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/* ulInterruptCause is used for convenience here. A context switch is
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wanted, but coding portEND_SWITCHING_ISR( 1 ) would likely result in a
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compiler warning. */
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portEND_SWITCHING_ISR( ulInterruptCause );
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}
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/*-----------------------------------------------------------*/
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static void prvEMACDeferredInterruptHandlerTask( void *pvParameters )
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{
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xNetworkBufferDescriptor_t *pxNetworkBuffer;
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xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL };
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( void ) pvParameters;
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configASSERT( xEMACRxEventSemaphore );
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for( ;; )
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{
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/* Wait for the EMAC interrupt to indicate that another packet has been
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received. The while() loop is only needed if INCLUDE_vTaskSuspend is
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set to 0 in FreeRTOSConfig.h. If INCLUDE_vTaskSuspend is set to 1
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then portMAX_DELAY would be an indefinite block time and
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xSemaphoreTake() would only return when the semaphore was actually
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obtained. */
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while( xSemaphoreTake( xEMACRxEventSemaphore, portMAX_DELAY ) == pdFALSE );
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/* At least one packet has been received. */
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while( EMAC_CheckReceiveIndex() != FALSE )
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{
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/* The buffer filled by the DMA is going to be passed into the IP
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stack. Allocate another buffer for the DMA descriptor. */
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pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( portTickType ) 0 );
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if( pxNetworkBuffer != NULL )
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{
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/* Swap the buffer just allocated and referenced from the
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pxNetworkBuffer with the buffer that has already been filled by
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the DMA. pxNetworkBuffer will then hold a reference to the
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buffer that already contains the data without any data having
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been copied between buffers. */
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EMAC_NextPacketToRead( pxNetworkBuffer );
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#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 1
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{
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if( pxNetworkBuffer->xDataLength > 0 )
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{
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/* If the frame would not be processed by the IP stack then
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don't even bother sending it to the IP stack. */
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if( eConsiderFrameForProcessing( pxNetworkBuffer->pucEthernetBuffer ) != eProcessBuffer )
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{
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pxNetworkBuffer->xDataLength = 0;
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}
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}
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}
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#endif
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if( pxNetworkBuffer->xDataLength > 0 )
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{
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/* Store a pointer to the network buffer structure in the
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padding space that was left in front of the Ethernet frame.
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The pointer is needed to ensure the network buffer structure
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can be located when it is time for it to be freed if the
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Ethernet frame gets used as a zero copy buffer. */
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*( ( xNetworkBufferDescriptor_t ** ) ( ( pxNetworkBuffer->pucEthernetBuffer - ipBUFFER_PADDING ) ) ) = pxNetworkBuffer;
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/* Data was received and stored. Send it to the IP task
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for processing. */
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xRxEvent.pvData = ( void * ) pxNetworkBuffer;
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if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( portTickType ) 0 ) == pdFALSE )
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{
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/* The buffer could not be sent to the IP task so the
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buffer must be released. */
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vNetworkBufferRelease( pxNetworkBuffer );
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iptraceETHERNET_RX_EVENT_LOST();
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}
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else
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{
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iptraceNETWORK_INTERFACE_RECEIVE();
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}
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}
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else
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{
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/* The buffer does not contain any data so there is no
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point sending it to the IP task. Just release it. */
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vNetworkBufferRelease( pxNetworkBuffer );
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iptraceETHERNET_RX_EVENT_LOST();
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}
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}
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else
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{
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iptraceETHERNET_RX_EVENT_LOST();
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}
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/* Release the descriptor. */
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EMAC_UpdateRxConsumeIndex();
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}
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}
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}
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/*-----------------------------------------------------------*/
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@ -0,0 +1,610 @@
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/**********************************************************************
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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* Heavily modified by Real Time Engineers ltd.
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* FreeRTOS+UDP includes. */
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#include "FreeRTOS_UDP_IP.h"
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#include "FreeRTOS_IP_Private.h"
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#include "NetworkBufferManagement.h"
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/* Library includes. */
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#include "lpc18xx_emac.h"
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#include "lpc18xx_rgu.h"
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#include "lpc18xx_scu.h"
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#include "lpc18xx_gpio.h"
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#define emacTIMEOUT_DELAY ( 2 )
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#define emacNEGOTIATE_DELAY ( 10 / portTICK_RATE_MS )
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#define emacEXPECTED_RX_STATUS_MASK ( RX_FIRST_SEGM | RX_LAST_SEGM )
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/* Rx descriptors and data array. */
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static volatile RX_Desc Rx_Desc[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ];
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static unsigned int RxDescIndex = 0;
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/** Rx Status data array - Must be 8-Byte aligned */
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#if defined ( __CC_ARM )
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static __align(8) RX_Stat Rx_Stat[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ];
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#elif defined ( __ICCARM__ )
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#pragma data_alignment=8
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static RX_Stat Rx_Stat[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ];
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#elif defined ( __GNUC__ )
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static volatile __attribute__ ((aligned (8))) RX_Stat Rx_Stat[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS ];
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#endif
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/* Tx descriptors and status array. */
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static volatile TX_Desc Tx_Desc[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS ];
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static volatile TX_Stat Tx_Stat[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS ];
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static unsigned int TxDescIndex = 0;
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/* Private Functions ---------------------------------------------------------- */
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static void rx_descr_init( void );
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static void tx_descr_init( void );
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static int32_t write_PHY( uint32_t PhyReg, uint16_t Value );
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static int32_t read_PHY( uint32_t PhyReg );
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static void setEmacAddr( uint8_t abStationAddr[] );
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/*********************************************************************//**
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* @brief Initializes the EMAC peripheral according to the specified
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* parameters in the EMAC_ConfigStruct.
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* @param[in] EMAC_ConfigStruct Pointer to a EMAC_CFG_Type structure
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* that contains the configuration information for the
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* specified EMAC peripheral.
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* @return None
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*
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* Note: This function will initialize EMAC module according to procedure below:
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* - Remove the soft reset condition from the MAC
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* - Configure the PHY via the MIIM interface of the MAC
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* - Select RMII mode
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* - Configure the transmit and receive DMA engines, including the descriptor arrays
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* - Configure the host registers (MAC1,MAC2 etc.) in the MAC
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* - Enable the receive and transmit data paths
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* In default state after initializing, only Rx Done and Tx Done interrupt are enabled,
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* all remain interrupts are disabled
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* (Ref. from LPC17xx UM)
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**********************************************************************/
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portBASE_TYPE EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct)
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{
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int32_t id1, id2, regv, phy = 0;
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int32_t phy_linkstatus_reg, phy_linkstatus_mask;
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uint32_t x;
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const uint32_t ulMaxAttempts = 250UL;
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portBASE_TYPE xReturn = pdPASS;
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/* Enable Ethernet Pins (NGX LPC1830 Xplorer. */
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scu_pinmux(0x2 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7);
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scu_pinmux(0x1 ,17 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3);
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scu_pinmux(0x1 ,18 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3);
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scu_pinmux(0x1 ,20 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3);
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scu_pinmux(0x1 ,19 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0);
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scu_pinmux(0x0 ,1 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC6);
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scu_pinmux(0x1 ,15 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3);
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scu_pinmux(0x0 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2);
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scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3);
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scu_pinmux(0xC ,9 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3);
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scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7);
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/* Ethernet RESET Pins */
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scu_pinmux(0x1 ,0 , MD_PUP, FUNC0);
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GPIO_SetDir(0,(1<<4), 1);
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GPIO_SetValue(0,(1<<4));
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#if MII /* Select MII interface */ // check MUXING for new Eagle...
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scu_pinmux(0xC ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD2: PC_6 -> FUNC3
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scu_pinmux(0xC ,7 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD3: PC_7 -> FUNC3
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scu_pinmux(0xC ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXLK: PC_0 -> FUNC3
|
||||
scu_pinmux(0xC ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD2: PC_2 -> FUNC3
|
||||
scu_pinmux(0xC ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD3: PC_3 -> FUNC3
|
||||
scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3
|
||||
scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_COL: P0_1 -> FUNC2
|
||||
#else /* Select RMII interface */
|
||||
LPC_CREG->CREG6 |= RMII_SELECT;
|
||||
#endif
|
||||
|
||||
|
||||
RGU_SoftReset( RGU_SIG_ETHERNET );
|
||||
|
||||
/* Wait for reset. */
|
||||
while( !( LPC_RGU->RESET_ACTIVE_STATUS0 & ( 1 << ETHERNET_RST ) ) )
|
||||
{
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
|
||||
/* Reset all GMAC Subsystem internal registers and logic. */
|
||||
LPC_ETHERNET->DMA_BUS_MODE |= DMA_SOFT_RESET;
|
||||
|
||||
/* Wait for software reset completion. */
|
||||
while( LPC_ETHERNET->DMA_BUS_MODE & DMA_SOFT_RESET )
|
||||
{
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
|
||||
/* Put the PHY in reset mode */
|
||||
write_PHY( PHY_REG_BMCR, PHY_BMCR_RESET );
|
||||
|
||||
/* Wait for hardware reset to end. */
|
||||
for( x = 0; x < ulMaxAttempts; x++ )
|
||||
{
|
||||
regv = read_PHY (PHY_REG_BMCR);
|
||||
if( !( regv & PHY_BMCR_RESET ) )
|
||||
{
|
||||
/* Reset complete */
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
if( x == ulMaxAttempts )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
|
||||
/* Check if this is a DP83848C PHY. */
|
||||
id1 = read_PHY( PHY_REG_IDR1 );
|
||||
id2 = read_PHY( PHY_REG_IDR2 );
|
||||
if( ( ( id1 << 16 ) | ( id2 & 0xFFF0 ) ) == DP83848C_ID )
|
||||
{
|
||||
phy = DP83848C_ID;
|
||||
}
|
||||
else if( ( ( id1 << 16 ) | id2 ) == LAN8720_ID )
|
||||
{
|
||||
phy = LAN8720_ID;
|
||||
}
|
||||
|
||||
if( phy != 0 )
|
||||
{
|
||||
/* Use autonegotiation about the link speed. */
|
||||
write_PHY( PHY_REG_BMCR, PHY_AUTO_NEG );
|
||||
|
||||
/* Wait to complete Auto_Negotiation. */
|
||||
for( x = 0; x < ulMaxAttempts; x++ )
|
||||
{
|
||||
regv = read_PHY( PHY_REG_BMSR );
|
||||
|
||||
if( ( regv & PHY_AUTO_NEG_DONE ) != 0 )
|
||||
{
|
||||
/* Auto negotiation Complete. */
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
vTaskDelay( emacNEGOTIATE_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
if( x == ulMaxAttempts )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xReturn == pdPASS )
|
||||
{
|
||||
/* Default to DP83848C. */
|
||||
phy_linkstatus_reg = PHY_REG_STS;
|
||||
phy_linkstatus_mask = 0x0001;
|
||||
|
||||
if( phy == LAN8720_ID )
|
||||
{
|
||||
phy_linkstatus_reg = PHY_REG_BMSR;
|
||||
phy_linkstatus_mask = 0x0004;
|
||||
}
|
||||
|
||||
/* Check the link status. */
|
||||
for( x = 0; x < ulMaxAttempts; x++ )
|
||||
{
|
||||
regv = read_PHY( phy_linkstatus_reg );
|
||||
|
||||
if( ( regv & phy_linkstatus_mask ) != 0 )
|
||||
{
|
||||
/* Link is on. */
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
vTaskDelay( emacNEGOTIATE_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
if( x == ulMaxAttempts )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
|
||||
regv = read_PHY( PHY_REG_SPCON );
|
||||
regv &= PHY_REG_HCDSPEED_MASK;
|
||||
|
||||
/* Configure 100MBit/10MBit mode and Full/Half Duplex mode. */
|
||||
switch( regv )
|
||||
{
|
||||
case PHY_REG_HCDSPEED_10MB_FULLD:
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE;
|
||||
break;
|
||||
|
||||
case PHY_REG_HCDSPEED_100MB_HALFD:
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS;
|
||||
break;
|
||||
|
||||
case PHY_REG_HCDSPEED_100MB_FULLD:
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE;
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Set the Ethernet MAC Address registers */
|
||||
setEmacAddr( EMAC_ConfigStruct->pbEMAC_Addr );
|
||||
|
||||
/* Initialize Descriptor Lists */
|
||||
rx_descr_init();
|
||||
tx_descr_init();
|
||||
|
||||
/* Configure Filter
|
||||
LPC_ETHERNET->MAC_FRAME_FILTER is left at its default value.
|
||||
MAC_PROMISCUOUS and MAC_RECEIVEALL can be set if required. */
|
||||
|
||||
/* Enable Receiver and Transmitter */
|
||||
LPC_ETHERNET->MAC_CONFIG |= (MAC_TX_ENABLE | MAC_RX_ENABLE);
|
||||
|
||||
/* Enable interrupts */
|
||||
LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE ;
|
||||
|
||||
/* Start Transmission & Receive processes */
|
||||
LPC_ETHERNET->DMA_OP_MODE |= (DMA_SS_TRANSMIT | DMA_SS_RECEIVE );
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
**********************************************************************/
|
||||
portBASE_TYPE EMAC_CheckTransmitIndex( void )
|
||||
{
|
||||
portBASE_TYPE xReturn;
|
||||
|
||||
if( ( Tx_Desc[ TxDescIndex ].Status & OWN_BIT ) == 0 )
|
||||
{
|
||||
xReturn = pdPASS;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief EMAC_SetNextPacketToSend
|
||||
* @param[in] pucBuffer
|
||||
* @return None
|
||||
***********************************************************************/
|
||||
void EMAC_SetNextPacketToSend( uint8_t * pucBuffer )
|
||||
{
|
||||
/* The old packet is now finished with and can be freed. */
|
||||
vEthernetBufferRelease( ( void * ) Tx_Desc[ TxDescIndex ].Packet );
|
||||
|
||||
/* Assign the new packet to the descriptor. */
|
||||
Tx_Desc[ TxDescIndex ].Packet = ( uint32_t ) pucBuffer;
|
||||
}
|
||||
|
||||
void EMAC_StartTransmitNextBuffer( uint32_t ulLength )
|
||||
{
|
||||
Tx_Desc[ TxDescIndex ].Ctrl = ulLength;
|
||||
Tx_Desc[ TxDescIndex ].Status |= OWN_BIT;
|
||||
|
||||
/* Wake Up the DMA if it's in Suspended Mode. */
|
||||
LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1;
|
||||
TxDescIndex++;
|
||||
|
||||
if( TxDescIndex == configNUM_TX_ETHERNET_DMA_DESCRIPTORS )
|
||||
{
|
||||
TxDescIndex = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Get size of current Received data in received buffer (due to
|
||||
* RxConsumeIndex)
|
||||
* @param[in] None
|
||||
* @return Size of received data
|
||||
**********************************************************************/
|
||||
uint32_t EMAC_GetReceiveDataSize(void)
|
||||
{
|
||||
unsigned short RxLen = 0;
|
||||
|
||||
RxLen = ( Rx_Desc[ RxDescIndex ].Status >> 16 ) & 0x03FFF;
|
||||
return RxLen;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Increase the RxConsumeIndex (after reading the Receive buffer
|
||||
* to release the Receive buffer) and wrap-around the index if
|
||||
* it reaches the maximum Receive Number
|
||||
* @param[in] None
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
void EMAC_UpdateRxConsumeIndex( void )
|
||||
{
|
||||
Rx_Desc[ RxDescIndex ].Status = OWN_BIT;
|
||||
RxDescIndex++;
|
||||
|
||||
if( RxDescIndex == configNUM_RX_ETHERNET_DMA_DESCRIPTORS )
|
||||
{
|
||||
RxDescIndex = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Check whether if the current RxConsumeIndex is not equal to the
|
||||
* current RxProduceIndex.
|
||||
* @param[in] None
|
||||
* @return TRUE if they're not equal, otherwise return FALSE
|
||||
*
|
||||
* Note: In case the RxConsumeIndex is not equal to the RxProduceIndex,
|
||||
* it means there're available data has been received. They should be read
|
||||
* out and released the Receive Data Buffer by updating the RxConsumeIndex value.
|
||||
**********************************************************************/
|
||||
portBASE_TYPE EMAC_CheckReceiveIndex(void)
|
||||
{
|
||||
portBASE_TYPE xReturn;
|
||||
|
||||
if( ( Rx_Desc[ RxDescIndex ].Status & OWN_BIT ) == 0 )
|
||||
{
|
||||
xReturn = pdPASS;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer )
|
||||
{
|
||||
uint8_t *pucTemp;
|
||||
|
||||
/* Swap the buffer in the network buffer with the buffer used by the DMA.
|
||||
This allows the data to be passed out without having to perform any copies. */
|
||||
pucTemp = ( uint8_t * ) Rx_Desc[ RxDescIndex ].Packet;
|
||||
Rx_Desc[ RxDescIndex ].Packet = ( uint32_t ) pxNetworkBuffer->pucEthernetBuffer;
|
||||
pxNetworkBuffer->pucEthernetBuffer = pucTemp;
|
||||
|
||||
/* Only supports frames coming in single buffers. If this frame is split
|
||||
across multiple buffers then reject it (and if the frame is needed increase
|
||||
the ipconfigNETWORK_MTU setting). */
|
||||
if( ( Rx_Desc[ RxDescIndex ].Status & emacEXPECTED_RX_STATUS_MASK ) != emacEXPECTED_RX_STATUS_MASK )
|
||||
{
|
||||
pxNetworkBuffer->xDataLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
pxNetworkBuffer->xDataLength = ( size_t ) EMAC_GetReceiveDataSize() - ( ipETHERNET_CRC_BYTES - 1U );;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Initializes RX Descriptor
|
||||
* @param[in] None
|
||||
* @return None
|
||||
***********************************************************************/
|
||||
static void rx_descr_init( void )
|
||||
{
|
||||
uint32_t x;
|
||||
size_t xBufferSize = ipTOTAL_ETHERNET_FRAME_SIZE;
|
||||
|
||||
for( x = 0; x < configNUM_RX_ETHERNET_DMA_DESCRIPTORS; x++ )
|
||||
{
|
||||
/* Obtain the buffer first, as the size of the buffer might be changed
|
||||
within the pucEthernetBufferGet() call. */
|
||||
Rx_Desc[ x ].Packet = ( uint32_t ) pucEthernetBufferGet( &xBufferSize );
|
||||
Rx_Desc[ x ].Status = OWN_BIT;
|
||||
Rx_Desc[ x ].Ctrl = xBufferSize;
|
||||
Rx_Desc[ x ].NextDescripter = ( uint32_t ) &Rx_Desc[ x + 1 ];
|
||||
|
||||
configASSERT( ( ( ( uint32_t ) Rx_Desc[x].Packet ) & 0x07 ) == 0 );
|
||||
}
|
||||
|
||||
/* Last Descriptor */
|
||||
Rx_Desc[ configNUM_RX_ETHERNET_DMA_DESCRIPTORS - 1 ].Ctrl |= RX_END_RING;
|
||||
|
||||
RxDescIndex = 0;
|
||||
|
||||
/* Set Starting address of RX Descriptor list */
|
||||
LPC_ETHERNET->DMA_REC_DES_ADDR = ( uint32_t ) Rx_Desc;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Initializes TX Descriptor
|
||||
* @param[in] None
|
||||
* @return None
|
||||
***********************************************************************/
|
||||
static void tx_descr_init( void )
|
||||
{
|
||||
/* Initialize Transmit Descriptor and Status array. */
|
||||
uint32_t x;
|
||||
|
||||
for( x = 0; x < configNUM_TX_ETHERNET_DMA_DESCRIPTORS; x++ )
|
||||
{
|
||||
Tx_Desc[ x ].Status = TX_LAST_SEGM | TX_FIRST_SEGM;
|
||||
Tx_Desc[ x ].Ctrl = 0;
|
||||
Tx_Desc[ x ].NextDescripter = ( uint32_t ) &Tx_Desc[ x + 1 ];
|
||||
|
||||
/* Packet is assigned when a Tx is initiated. */
|
||||
Tx_Desc[ x ].Packet = ( uint32_t )NULL;
|
||||
}
|
||||
|
||||
/* Last Descriptor? */
|
||||
Tx_Desc[ configNUM_TX_ETHERNET_DMA_DESCRIPTORS-1 ].Status |= TX_END_RING;
|
||||
|
||||
/* Set Starting address of TX Descriptor list */
|
||||
LPC_ETHERNET->DMA_TRANS_DES_ADDR = ( uint32_t ) Tx_Desc;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Write value to PHY device
|
||||
* @param[in] PhyReg: PHY Register address
|
||||
* @param[in] Value: Value to write
|
||||
* @return 0 - if success
|
||||
* 1 - if fail
|
||||
***********************************************************************/
|
||||
static int32_t write_PHY (uint32_t PhyReg, uint16_t Value)
|
||||
{
|
||||
uint32_t x;
|
||||
const uint32_t ulMaxAttempts = 250UL;
|
||||
int32_t lReturn = pdPASS;
|
||||
|
||||
/* Write a data 'Value' to PHY register 'PhyReg'. */
|
||||
x = 0;
|
||||
while( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY )
|
||||
{
|
||||
x++;
|
||||
|
||||
if( x >= ulMaxAttempts )
|
||||
{
|
||||
/* Time out. */
|
||||
lReturn = pdFAIL;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* GMII is busy. */
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
LPC_ETHERNET->MAC_MII_ADDR = ( DP83848C_DEF_ADR << 11 ) | ( PhyReg << 6 ) | GMII_WRITE;
|
||||
LPC_ETHERNET->MAC_MII_DATA = Value;
|
||||
|
||||
/* Start PHY Write Cycle. */
|
||||
LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY;
|
||||
|
||||
/* Wait untl operation completed. */
|
||||
for( x = 0; x < ulMaxAttempts; x++ )
|
||||
{
|
||||
if( ( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY ) == 0 )
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
if( x == ulMaxAttempts )
|
||||
{
|
||||
/* Timeout. */
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
}
|
||||
|
||||
return lReturn;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Read value from PHY device
|
||||
* @param[in] PhyReg: PHY Register address
|
||||
* @return 0 - if success
|
||||
* 1 - if fail
|
||||
***********************************************************************/
|
||||
static int32_t read_PHY( uint32_t PhyReg )
|
||||
{
|
||||
int32_t lValue = 0;
|
||||
uint32_t x;
|
||||
const uint32_t ulMaxAttempts = 250UL;
|
||||
|
||||
/* Write a data 'Value' to PHY register 'PhyReg'. */
|
||||
x = 0;
|
||||
while( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY )
|
||||
{
|
||||
x++;
|
||||
|
||||
if( x >= ulMaxAttempts )
|
||||
{
|
||||
/* Time out. */
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* GMII is busy. */
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
if( x < ulMaxAttempts )
|
||||
{
|
||||
/* Read a PHY register 'PhyReg'. */
|
||||
LPC_ETHERNET->MAC_MII_ADDR = ( DP83848C_DEF_ADR << 11 ) | ( PhyReg << 6 ) | GMII_READ;
|
||||
|
||||
/* Start PHY Read Cycle. */
|
||||
LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY;
|
||||
|
||||
/* Wait until operation completed */
|
||||
for( x = 0; x < ulMaxAttempts; x++ )
|
||||
{
|
||||
if( ( LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY ) == 0 )
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
vTaskDelay( emacTIMEOUT_DELAY );
|
||||
}
|
||||
}
|
||||
|
||||
configASSERT( x != ulMaxAttempts );
|
||||
lValue = LPC_ETHERNET->MAC_MII_DATA;
|
||||
}
|
||||
|
||||
return lValue;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Set Station MAC address for EMAC module
|
||||
* @param[in] abStationAddr Pointer to Station address that contains 6-bytes
|
||||
* of MAC address (should be in order from MAC Address 1 to MAC Address 6)
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
static void setEmacAddr( uint8_t abStationAddr[] )
|
||||
{
|
||||
/* Set the Ethernet MAC Address registers */
|
||||
LPC_ETHERNET->MAC_ADDR0_HIGH = (( uint32_t ) abStationAddr[ 5 ] << 8 ) | ( uint32_t )abStationAddr[ 4 ];
|
||||
LPC_ETHERNET->MAC_ADDR0_LOW = (( uint32_t )abStationAddr[ 3 ] << 24) | (( uint32_t )abStationAddr[ 2 ] << 16) | (( uint32_t )abStationAddr[ 1 ] << 8 ) | ( uint32_t )abStationAddr[ 0 ];
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,238 @@
|
||||
/***********************************************************************//**
|
||||
* @file lpc17xx_emac.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Ethernet MAC firmware library on LPC17xx
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
**************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**************************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup EMAC EMAC
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC18XX_EMAC_H_
|
||||
#define LPC18XX_EMAC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC18xx.h"
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "lpc_types.h"
|
||||
|
||||
/* Configuration */
|
||||
|
||||
/* Interface Selection */
|
||||
#define MII 0 // =0 RMII - =1 MII
|
||||
|
||||
/* End of Configuration */
|
||||
|
||||
/* Descriptors Fields bits */
|
||||
#define OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
|
||||
#define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
|
||||
#define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
|
||||
#define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
|
||||
#define RX_LAST_SEGM (1<<9)
|
||||
#define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
|
||||
#define RX_FIRST_SEGM (1<<8) /* First Segment bit in TDES0 */
|
||||
#define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
|
||||
#define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
|
||||
|
||||
/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
|
||||
#define EMAC_ETH_MAX_FLEN ipETHERNET_FRAME_SIZE_TO_USE
|
||||
|
||||
/* NOTE: EMAC_NUM_RX_FRAG is not used by the example FreeRTOS drivers - use
|
||||
configNUM_RX_ETHERNET_DMA_DESCRIPTORS. */
|
||||
#define EMAC_NUM_RX_FRAG 6 /**< Num.of RX Fragments */
|
||||
|
||||
/* NOTE: EMAC_NUM_TX_FRAG is not used by the example FreeRTOS drivers - use
|
||||
configNUM_TX_ETHERNET_DMA_DESCRIPTORS. */
|
||||
#define EMAC_NUM_TX_FRAG 2 /**< Num.of TX Fragments */
|
||||
|
||||
/* EMAC Control and Status bits */
|
||||
#define MAC_RX_ENABLE (1<<2) /* Receiver Enable in MAC_CONFIG reg */
|
||||
#define MAC_TX_ENABLE (1<<3) /* Transmitter Enable in MAC_CONFIG reg */
|
||||
#define MAC_PADCRC_STRIP (1<<7) /* Automatic Pad-CRC Stripping in MAC_CONFIG reg */
|
||||
#define MAC_DUPMODE (1<<11) /* Duplex Mode in MAC_CONFIG reg */
|
||||
#define MAC_100MPS (1<<14) /* Speed is 100Mbps in MAC_CONFIG reg */
|
||||
#define MAC_PROMISCUOUS (1U<<0) /* Promiscuous Mode bit in MAC_FRAME_FILTER reg */
|
||||
#define MAC_DIS_BROAD (1U<<5) /* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */
|
||||
#define MAC_RECEIVEALL (1U<<31) /* Receive All bit in MAC_FRAME_FILTER reg */
|
||||
#define DMA_SOFT_RESET 0x01 /* Software Reset bit in DMA_BUS_MODE reg */
|
||||
#define DMA_SS_RECEIVE (1<<1) /* Start/Stop Receive bit in DMA_OP_MODE reg */
|
||||
#define DMA_SS_TRANSMIT (1<<13) /* Start/Stop Transmission bit in DMA_OP_MODE reg */
|
||||
#define DMA_INT_TRANSMIT (1<<0) /* Transmit Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_OVERFLOW (1<<4) /* Overflow Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_UNDERFLW (1<<5) /* Underflow Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_RECEIVE (1<<6) /* Receive Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_ABN_SUM (1<<15) /* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_NOR_SUM (1<<16) /* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */
|
||||
|
||||
/* MII Management Command Register */
|
||||
#define GMII_READ (0<<1) /* GMII Read PHY */
|
||||
#define GMII_WRITE (1<<1) /* GMII Write PHY */
|
||||
#define GMII_BUSY 0x00000001 /* GMII is Busy / Start Read/Write */
|
||||
#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
|
||||
#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
|
||||
|
||||
/* MII Management Address Register */
|
||||
#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
|
||||
|
||||
/* LAN8720 PHY Registers */
|
||||
#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
|
||||
#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
|
||||
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
|
||||
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
|
||||
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
|
||||
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
|
||||
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
|
||||
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
|
||||
|
||||
/* LAN8720 PHY Speed identify */
|
||||
#define PHY_REG_SPCON 0x1f /* Speed indication Register */
|
||||
#define PHY_REG_HCDSPEED_MASK 0x1c /* Speed indication Register mask*/
|
||||
#define PHY_REG_HCDSPEED_10MB_HALFD 0x04 /* Speed is 10Mbps HALF-duplex */
|
||||
#define PHY_REG_HCDSPEED_10MB_FULLD 0x14 /* Speed is 10Mbps FULL-duplex */
|
||||
#define PHY_REG_HCDSPEED_100MB_HALFD 0x08 /* Speed is 100Mbps HALF-duplex */
|
||||
#define PHY_REG_HCDSPEED_100MB_FULLD 0x18 /* Speed is 100Mbps FULL-duplex */
|
||||
|
||||
|
||||
/* PHY Extended Registers */
|
||||
#define PHY_REG_STS 0x10 /* Status Register */
|
||||
#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
|
||||
#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
|
||||
#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
|
||||
#define PHY_REG_RECR 0x15 /* Receive Error Counter */
|
||||
#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
|
||||
#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
|
||||
#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
|
||||
#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
|
||||
#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
|
||||
#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
|
||||
#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
|
||||
|
||||
/* PHY Control and Status bits */
|
||||
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
|
||||
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
|
||||
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
|
||||
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
|
||||
#define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
|
||||
#define PHY_AUTO_NEG_DONE 0x0020 /* AutoNegotiation Complete in BMSR PHY reg */
|
||||
#define PHY_BMCR_RESET 0x8000 /* Reset bit at BMCR PHY reg */
|
||||
#define LINK_VALID_STS 0x0001 /* Link Valid Status at REG_STS PHY reg */
|
||||
#define FULL_DUP_STS 0x0004 /* Full Duplex Status at REG_STS PHY reg */
|
||||
#define SPEED_10M_STS 0x0002 /* 10Mbps Status at REG_STS PHY reg */
|
||||
|
||||
#define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
|
||||
#define DP83848C_ID 0x20005C90 /* PHY Identifier (without Rev. info */
|
||||
#define LAN8720_ID 0x0007C0F1 /* PHY Identifier for SMSC PHY */
|
||||
|
||||
/* Misc */
|
||||
#define ETHERNET_RST 22 /* Reset Output for EMAC at RGU */
|
||||
#define RMII_SELECT 0x04 /* Select RMII in EMACCFG */
|
||||
|
||||
|
||||
/**
|
||||
* @brief EMAC configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
|
||||
- EMAC_MODE_AUTO
|
||||
- EMAC_MODE_10M_FULL
|
||||
- EMAC_MODE_10M_HALF
|
||||
- EMAC_MODE_100M_FULL
|
||||
- EMAC_MODE_100M_HALF
|
||||
*/
|
||||
uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
|
||||
of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
|
||||
*/
|
||||
} EMAC_CFG_Type;
|
||||
|
||||
/* Descriptor and status formats ---------------------------------------------- */
|
||||
/**
|
||||
* @brief RX Descriptor structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Status; /**< Receive Status Descriptor */
|
||||
uint32_t Ctrl; /**< Receive Control Descriptor */
|
||||
uint32_t Packet; /**< Receive Packet Descriptor */
|
||||
uint32_t NextDescripter;/**< Receive Next Descriptor Address */
|
||||
} RX_Desc;
|
||||
|
||||
/**
|
||||
* @brief RX Status structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Info; /**< Receive Information Status */
|
||||
uint32_t HashCRC; /**< Receive Hash CRC Status */
|
||||
} RX_Stat;
|
||||
|
||||
/**
|
||||
* @brief TX Descriptor structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Status; /**< Transmit Status Descriptor */
|
||||
uint32_t Ctrl; /**< Transmit Control Descriptor */
|
||||
uint32_t Packet; /**< Transmit Packet Descriptor */
|
||||
uint32_t NextDescripter; /**< Transmit Next Descriptor Address */
|
||||
} TX_Desc;
|
||||
|
||||
/**
|
||||
* @brief TX Status structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Info; /**< Transmit Information Status */
|
||||
} TX_Stat;
|
||||
|
||||
|
||||
/**
|
||||
* @brief TX Data Buffer structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ulDataLen; /**< Data length */
|
||||
uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
|
||||
} EMAC_PACKETBUF_Type;
|
||||
|
||||
|
||||
|
||||
/* Prototypes */
|
||||
portBASE_TYPE EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
|
||||
int32_t EMAC_UpdatePHYStatus(void);
|
||||
uint32_t EMAC_GetReceiveDataSize(void);
|
||||
void EMAC_StartTransmitNextBuffer( uint32_t ulLength );
|
||||
void EMAC_SetNextPacketToSend( uint8_t * pucBuffer );
|
||||
void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer );
|
||||
void EMAC_UpdateRxConsumeIndex(void);
|
||||
portBASE_TYPE EMAC_CheckReceiveIndex(void);
|
||||
portBASE_TYPE EMAC_CheckTransmitIndex(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPC18XX_EMAC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
Loading…
Reference in New Issue