Add two Cortex-M4F demo applications.
Richard Barry
13 years ago
parent
e7a1222c5f
commit
08ddd1d00d
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This version supports only the cortex-M4F core. Future versions will also support the Cortex-M0 core.
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/*
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FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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#include "LPC43xx.h"
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#include "core_cm4.h"
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*
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* See http://www.freertos.org/a00110.html.
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*----------------------------------------------------------*/
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 1
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#define configUSE_TICK_HOOK 1
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#define configCPU_CLOCK_HZ ( 120000000UL )
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#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 75 * 1024 ) )
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#define configMAX_TASK_NAME_LEN ( 10 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 1
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#define configUSE_MUTEXES 1
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#define configQUEUE_REGISTRY_SIZE 8
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#define configUSE_RECURSIVE_MUTEXES 1
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#define configUSE_MALLOC_FAILED_HOOK 1
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#define configUSE_APPLICATION_TASK_TAG 0
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configGENERATE_RUN_TIME_STATS 0
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Software timer definitions. This example uses I2C to write to the LEDs. As
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this takes a finite time, and because a timer callback writes to an LED, the
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priority of the timer task is kept to a minimum to ensure it does not disrupt
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test tasks that check their own execution times. */
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#define configUSE_TIMERS 1
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#define configTIMER_TASK_PRIORITY ( 0 )
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#define configTIMER_QUEUE_LENGTH 5
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#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskCleanUpResources 1
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#define INCLUDE_vTaskSuspend 1
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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/* Cortex-M specific definitions. */
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#ifdef __NVIC_PRIO_BITS
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/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#else
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#define configPRIO_BITS 5 /* 32 priority levels */
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#endif
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/* The lowest interrupt priority that can be used in a call to a "set priority"
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function. */
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1f
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/* The highest interrupt priority that can be used by any interrupt service
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routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
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INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
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PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
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/* Interrupt priorities used by the kernel port layer itself. These are generic
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to all Cortex-M ports, and do not rely on any particular library functions. */
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#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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/* Normal assert() semantics without relying on the provision of an assert.h
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header file. */
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#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
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/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
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standard names. */
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#define vPortSVCHandler SVC_Handler
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#define xPortPendSVHandler PendSV_Handler
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#define xPortSysTickHandler SysTick_Handler
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#endif /* FREERTOS_CONFIG_H */
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@ -0,0 +1,166 @@
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/******************************************************************************/
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/* LPC43XX-FLASH-DEBUG.INI: External Memory Interface initialization for */
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/* LPC43xx first revision (Sept 2011). */
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/* The purpose is to be able to debug a program */
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/* located in the external flash. */
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/******************************************************************************/
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FUNC void Pre_Setup (void) {
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/* configure M0 for infinite loop */
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_WDWORD(0x10080000,0x00001F00); /* dummy stack pointer */
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_WDWORD(0x10080004,0x000000D5); /* reset handler */
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_WDWORD(0x100800D4,0xE7FEE7FE); /* jump to itself instruction for M0a */
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_WDWORD(0x40043404,0x10080000); /* M0 shadow pointer. */
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/* release M0 from reset to allow Jtag access */
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_WDWORD(0x40053104,(~(_RDWORD(0x40053154))) & (~(1<<24)));
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// u32Val = (~(u32REG) & (~(1 << 24))); // clear the control bit
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// LPC_RGU->RESET_CTRL1 = (~( LPC_RGU->RESET_ACTIVE_STATUS1 )) & (0 << 24); //Release M0
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}
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FUNC void Setup (void)
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{
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// With the values used here, the program had to be linked to CS0 memory
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// located at 0x1C000000 in the LPC43xx.
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/* This would be used in case there is a 16-byte header in the image */
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/*
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SP = _RDWORD(0x1c000100); // Setup Stack Pointer
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PC = _RDWORD(0x1C000104); // Setup Program Counter
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_WDWORD(0xE000ED08, 0x1C000100); // Setup Vector Table Offset Register
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*/
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/* This is used for plain images, without a 16-byte header */
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SP = _RDWORD(0x1C000000); // Setup Stack Pointer
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PC = _RDWORD(0x1C000004); // Setup Program Counter
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_WDWORD(0xE000ED08, 0x1C000000); // Setup Vector Table Offset Register
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}
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FUNC void emc_setup (void)
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{
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// bus signals for external memory
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_WDWORD(0x4008609C, 0x000000F3); /* P1_7: D0 (function 3) */
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_WDWORD(0x400860A0, 0x000000F3); /* P1_8: D1 (function 3) */
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_WDWORD(0x400860A4, 0x000000F3); /* P1_9: D2 (function 3) */
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_WDWORD(0x400860A8, 0x000000F3); /* P1_10: D3 (function 3) */
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_WDWORD(0x400860AC, 0x000000F3); /* P1_11: D4 (function 3) */
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_WDWORD(0x400860B0, 0x000000F3); /* P1_12: D5 (function 3) */
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_WDWORD(0x400860B4, 0x000000F3); /* P1_13: D6 (function 3) */
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_WDWORD(0x400860B8, 0x000000F3); /* P1_14: D7 (function 3) */
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_WDWORD(0x40086280, 0x000000F2); /* P5_0: D12 (function 2) */
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_WDWORD(0x40086284, 0x000000F2); /* P5_1: D13 (function 2) */
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_WDWORD(0x40086288, 0x000000F2); /* P5_2: D14 (function 2) */
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_WDWORD(0x4008628C, 0x000000F2); /* P5_3: D15 (function 2) */
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_WDWORD(0x40086290, 0x000000F2); /* P5_4: D8 (function 2) */
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_WDWORD(0x40086294, 0x000000F2); /* P5_5: D9 (function 2) */
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_WDWORD(0x40086298, 0x000000F2); /* P5_6: D10 (function 2) */
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_WDWORD(0x4008629C, 0x000000F2); /* P5_7: D11 (function 2) */
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_WDWORD(0x40086688, 0x000000F2); /* PD_2: D16 (function 2) */
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_WDWORD(0x4008668C, 0x000000F2); /* PD_3: D17 (function 2) */
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_WDWORD(0x40086690, 0x000000F2); /* PD_4: D18 (function 2) */
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_WDWORD(0x40086694, 0x000000F2); /* PD_5: D19 (function 2) */
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_WDWORD(0x40086698, 0x000000F2); /* PD_6: D20 (function 2) */
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_WDWORD(0x4008669C, 0x000000F2); /* PD_7: D21 (function 2) */
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_WDWORD(0x400866A0, 0x000000F2); /* PD_8: D22 (function 2) */
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_WDWORD(0x400866A4, 0x000000F2); /* PD_9: D23 (function 2) */
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_WDWORD(0x40086714, 0x000000F3); /* PE_5: D24 (function 3) */
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_WDWORD(0x40086718, 0x000000F3); /* PE_6: D25 (function 3) */
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_WDWORD(0x4008671C, 0x000000F3); /* PE_7: D26 (function 3) */
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_WDWORD(0x40086720, 0x000000F3); /* PE_8: D27 (function 3) */
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_WDWORD(0x40086724, 0x000000F3); /* PE_9: D28 (function 3) */
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_WDWORD(0x40086728, 0x000000F3); /* PE_10: D29 (function 3) */
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_WDWORD(0x4008672C, 0x000000F3); /* PE_11: D30 (function 3) */
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_WDWORD(0x40086730, 0x000000F3); /* PE_12: D31 (function 3) */
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_WDWORD(0x40086124, 0x000000F3); /* P2_9: A0 (function 3) */
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_WDWORD(0x40086128, 0x000000F3); /* P2_10: A1 (function 3) */
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_WDWORD(0x4008612C, 0x000000F3); /* P2_11: A2 (function 3) */
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_WDWORD(0x40086130, 0x000000F3); /* P2_12: A3 (function 3) */
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_WDWORD(0x40086134, 0x000000F3); /* P2_13: A4 (function 3) */
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_WDWORD(0x40086080, 0x000000F2); /* P1_0: A5 (function 2) */
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_WDWORD(0x40086084, 0x000000F2); /* P1_1: A6 (function 2) */
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_WDWORD(0x40086088, 0x000000F2); /* P1_2: A7 (function 2) */
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_WDWORD(0x40086120, 0x000000F3); /* P2_8: A8 (function 3) */
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_WDWORD(0x4008611C, 0x000000F3); /* P2_7: A9 (function 3) */
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_WDWORD(0x40086118, 0x000000F2); /* P2_6: A10 (function 2) */
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_WDWORD(0x40086108, 0x000000F2); /* P2_2: A11 (function 2) */
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_WDWORD(0x40086104, 0x000000F2); /* P2_1: A12 (function 2) */
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_WDWORD(0x40086100, 0x000000F2); /* P2_0: A13 (function 2) */
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_WDWORD(0x40086320, 0x000000F1); /* P6_8: A14 (function 1) */
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_WDWORD(0x4008631C, 0x000000F1); /* P6_7: A15 (function 1) */
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_WDWORD(0x400866C0, 0x000000F2); /* PD_16: A16 (function 2) */
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_WDWORD(0x400866BC, 0x000000F2); /* PD_15: A17 (function 2) */
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_WDWORD(0x40086700, 0x000000F3); /* PE_0: A18 (function 3) */
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_WDWORD(0x40086704, 0x000000F3); /* PE_1: A19 (function 3) */
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_WDWORD(0x40086708, 0x000000F3); /* PE_2: A20 (function 3) */
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_WDWORD(0x4008670C, 0x000000F3); /* PE_3: A21 (function 3) */
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_WDWORD(0x40086710, 0x000000F3); /* PE_4: A22 (function 3) */
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// control signals for static memory
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_WDWORD(0x40086094, 0x000000F3); /* P1_5: CS0 (function 3) */
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_WDWORD(0x400866B0, 0x000000F2); /* PD_12: CS2 (function 2) */
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_WDWORD(0x40086098, 0x000000F3); /* P1_6: WE (function 3) */
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_WDWORD(0x4008608C, 0x000000F3); /* P1_3: OE (function 3) */
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_WDWORD(0x40086090, 0x000000F3); /* P1_4: BLS0 (function 3) */
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_WDWORD(0x40086318, 0x000000F1); /* P6_6: BLS1 (function 1) */
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// configure EMC static memory registers
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_WDWORD(0x40005000, 0x00000001); /* Enable the EMC block */
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_WDWORD(0x40005200, 0x00000081); /* CS0: 16 bit, WE */
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_WDWORD(0x40005208, 0x00000000); /* CS0: WAITOEN = 0 */
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_WDWORD(0x4000520C, 0x00000008); /* CS0: WAITRD = 8 @120MHz for 70ns flash */
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_WDWORD(0x40005240, 0x00000081); /* CS2: 16 bit, WE */
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_WDWORD(0x40005248, 0x00000000); /* CS2: WAITOEN = 0 */
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_WDWORD(0x4000524C, 0x00000007); /* CS2: WAITRD = 7 */
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}
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/******************************************************************************/
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/* */
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/* */
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/* */
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/******************************************************************************/
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_sleep_(100);
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//Pre_setup();
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// Just set up the memory interface to enable the correct access to the external
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// flash memory on CS0.
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emc_setup();
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// Download the image. This is not a physical download as the image is
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// (already) in the flash.
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// If working with ULINK devices an alternative is to check the checkbox "Load Application at Startup" in the
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// debug settings of µVision (comment the LOAD instruction out).
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// This mechanism is not used here, because somehow it does not work with the JLINK devices.
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LOAD Flash\LPC43xx_M4_FLASH.axf INCREMENTAL
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// Setup for running from a specific memory location
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Setup();
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@ -0,0 +1,110 @@
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/******************************************************************************/
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/* LPC43XX-FLASH-PROGRAM.INI: External Memory Interface initialization for */
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/* LPC43xx first revision (Sept 2011). */
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/* The purpose is to be able to program the */
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/* external flash using the KEIL µVision utility. */
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/******************************************************************************/
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FUNC void emc_setup (void)
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{
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// bus signals for external memory
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_WDWORD(0x4008609C, 0x000000F3); /* P1_7: D0 (function 3) */
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_WDWORD(0x400860A0, 0x000000F3); /* P1_8: D1 (function 3) */
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_WDWORD(0x400860A4, 0x000000F3); /* P1_9: D2 (function 3) */
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_WDWORD(0x400860A8, 0x000000F3); /* P1_10: D3 (function 3) */
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_WDWORD(0x400860AC, 0x000000F3); /* P1_11: D4 (function 3) */
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_WDWORD(0x400860B0, 0x000000F3); /* P1_12: D5 (function 3) */
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_WDWORD(0x400860B4, 0x000000F3); /* P1_13: D6 (function 3) */
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_WDWORD(0x400860B8, 0x000000F3); /* P1_14: D7 (function 3) */
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_WDWORD(0x40086280, 0x000000F2); /* P5_0: D12 (function 2) */
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_WDWORD(0x40086284, 0x000000F2); /* P5_1: D13 (function 2) */
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_WDWORD(0x40086288, 0x000000F2); /* P5_2: D14 (function 2) */
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_WDWORD(0x4008628C, 0x000000F2); /* P5_3: D15 (function 2) */
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_WDWORD(0x40086290, 0x000000F2); /* P5_4: D8 (function 2) */
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_WDWORD(0x40086294, 0x000000F2); /* P5_5: D9 (function 2) */
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_WDWORD(0x40086298, 0x000000F2); /* P5_6: D10 (function 2) */
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_WDWORD(0x4008629C, 0x000000F2); /* P5_7: D11 (function 2) */
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_WDWORD(0x40086688, 0x000000F2); /* PD_2: D16 (function 2) */
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_WDWORD(0x4008668C, 0x000000F2); /* PD_3: D17 (function 2) */
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_WDWORD(0x40086690, 0x000000F2); /* PD_4: D18 (function 2) */
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_WDWORD(0x40086694, 0x000000F2); /* PD_5: D19 (function 2) */
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_WDWORD(0x40086698, 0x000000F2); /* PD_6: D20 (function 2) */
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_WDWORD(0x4008669C, 0x000000F2); /* PD_7: D21 (function 2) */
|
||||
_WDWORD(0x400866A0, 0x000000F2); /* PD_8: D22 (function 2) */
|
||||
_WDWORD(0x400866A4, 0x000000F2); /* PD_9: D23 (function 2) */
|
||||
_WDWORD(0x40086714, 0x000000F3); /* PE_5: D24 (function 3) */
|
||||
_WDWORD(0x40086718, 0x000000F3); /* PE_6: D25 (function 3) */
|
||||
_WDWORD(0x4008671C, 0x000000F3); /* PE_7: D26 (function 3) */
|
||||
_WDWORD(0x40086720, 0x000000F3); /* PE_8: D27 (function 3) */
|
||||
_WDWORD(0x40086724, 0x000000F3); /* PE_9: D28 (function 3) */
|
||||
_WDWORD(0x40086728, 0x000000F3); /* PE_10: D29 (function 3) */
|
||||
_WDWORD(0x4008672C, 0x000000F3); /* PE_11: D30 (function 3) */
|
||||
_WDWORD(0x40086730, 0x000000F3); /* PE_12: D31 (function 3) */
|
||||
|
||||
_WDWORD(0x40086124, 0x000000F3); /* P2_9: A0 (function 3) */
|
||||
_WDWORD(0x40086128, 0x000000F3); /* P2_10: A1 (function 3) */
|
||||
_WDWORD(0x4008612C, 0x000000F3); /* P2_11: A2 (function 3) */
|
||||
_WDWORD(0x40086130, 0x000000F3); /* P2_12: A3 (function 3) */
|
||||
_WDWORD(0x40086134, 0x000000F3); /* P2_13: A4 (function 3) */
|
||||
_WDWORD(0x40086080, 0x000000F2); /* P1_0: A5 (function 2) */
|
||||
_WDWORD(0x40086084, 0x000000F2); /* P1_1: A6 (function 2) */
|
||||
_WDWORD(0x40086088, 0x000000F2); /* P1_2: A7 (function 2) */
|
||||
_WDWORD(0x40086120, 0x000000F3); /* P2_8: A8 (function 3) */
|
||||
_WDWORD(0x4008611C, 0x000000F3); /* P2_7: A9 (function 3) */
|
||||
_WDWORD(0x40086118, 0x000000F2); /* P2_6: A10 (function 2) */
|
||||
_WDWORD(0x40086108, 0x000000F2); /* P2_2: A11 (function 2) */
|
||||
_WDWORD(0x40086104, 0x000000F2); /* P2_1: A12 (function 2) */
|
||||
_WDWORD(0x40086100, 0x000000F2); /* P2_0: A13 (function 2) */
|
||||
_WDWORD(0x40086320, 0x000000F1); /* P6_8: A14 (function 1) */
|
||||
_WDWORD(0x4008631C, 0x000000F1); /* P6_7: A15 (function 1) */
|
||||
_WDWORD(0x400866C0, 0x000000F2); /* PD_16: A16 (function 2) */
|
||||
_WDWORD(0x400866BC, 0x000000F2); /* PD_15: A17 (function 2) */
|
||||
_WDWORD(0x40086700, 0x000000F3); /* PE_0: A18 (function 3) */
|
||||
_WDWORD(0x40086704, 0x000000F3); /* PE_1: A19 (function 3) */
|
||||
_WDWORD(0x40086708, 0x000000F3); /* PE_2: A20 (function 3) */
|
||||
_WDWORD(0x4008670C, 0x000000F3); /* PE_3: A21 (function 3) */
|
||||
_WDWORD(0x40086710, 0x000000F3); /* PE_4: A22 (function 3) */
|
||||
|
||||
// signals for static memory
|
||||
_WDWORD(0x40086094, 0x000000F3); /* P1_5: CS0 (function 3) */
|
||||
_WDWORD(0x400866B0, 0x000000F2); /* PD_12: CS2 (function 2) */
|
||||
_WDWORD(0x40086098, 0x000000F3); /* P1_6: WE (function 3) */
|
||||
_WDWORD(0x4008608C, 0x000000F3); /* P1_3: OE (function 3) */
|
||||
_WDWORD(0x40086090, 0x000000F3); /* P1_4: BLS0 (function 3) */
|
||||
_WDWORD(0x40086318, 0x000000F1); /* P6_6: BLS1 (function 1) */
|
||||
|
||||
|
||||
// configure EMC static memory registers
|
||||
_WDWORD(0x40005000, 0x00000001); /* Enable */
|
||||
|
||||
_WDWORD(0x40005200, 0x00000081); /* CS0: 16 bit, WE */
|
||||
_WDWORD(0x40005208, 0x00000000); /* CS0: WAITOEN = 0 */
|
||||
_WDWORD(0x4000520C, 0x00000008); /* CS0: WAITRD = 8 */
|
||||
|
||||
_WDWORD(0x40005240, 0x00000081); /* CS2: 16 bit, WE */
|
||||
_WDWORD(0x40005248, 0x00000000); /* CS2: WAITOEN = 0 */
|
||||
_WDWORD(0x4000524C, 0x00000007); /* CS2: WAITRD = 7 */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
_sleep_(100);
|
||||
|
||||
|
||||
// Just set up the memory interface to enable the correct access to the external
|
||||
// flash memory on CS0.
|
||||
emc_setup();
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,672 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>LPC43xx_M4_FLASH</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>0</BeepAtEnd>
|
||||
<RunSim>1</RunSim>
|
||||
<RunTarget>0</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\FLASH\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DllOpt>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDllName>DLM.DLL</SimDlgDllName>
|
||||
<SimDlgDllArguments>-pEMBER</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDllName>TLM.DLL</TargetDlgDllName>
|
||||
<TargetDlgDllArguments></TargetDlgDllArguments>
|
||||
</DllOpt>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>0</tRwatch>
|
||||
<tRmem>0</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>0</tRbox>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>1</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>.\LPC43XX-M4-FLASH-DEBUG.ini</tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV1115SAE -O968 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO2 -TC120000000 -TP21 -TDS801F -TDT0 -TDC1F -TIE1 -TIP8 -FO23 -FD10000000 -FC8000 -FN1 -FF0SST39VF3201B_LPC4300 -FS01C000000 -FL0400000</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=914,153,1280,699,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=1046,243,1280,780,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ULP2CM3</Key>
|
||||
<Name>-UP1012135 -O718 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC3800 -FN1 -FF0SST39VF3201B_LPC1800A -FS01C000000 -FL0400000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>1</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>System Code</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>164</TopLine>
|
||||
<CurrentLine>164</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\platform\startup_LPC43xx.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_LPC43xx.s</FilenameWithoutPath>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\system\system_LPC43xx.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_LPC43xx.c</FilenameWithoutPath>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\system\core_cm4.c</PathWithFileName>
|
||||
<FilenameWithoutPath>core_cm4.c</FilenameWithoutPath>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>31</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\system\emc_LPC43xx.c</PathWithFileName>
|
||||
<FilenameWithoutPath>emc_LPC43xx.c</FilenameWithoutPath>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\system\scu.c</PathWithFileName>
|
||||
<FilenameWithoutPath>scu.c</FilenameWithoutPath>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\system\fpu_init.c</PathWithFileName>
|
||||
<FilenameWithoutPath>fpu_init.c</FilenameWithoutPath>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Platform</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\platform\platform_config.h</PathWithFileName>
|
||||
<FilenameWithoutPath>platform_config.h</FilenameWithoutPath>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>22</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>0</TopLine>
|
||||
<CurrentLine>0</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\platform\platform_config.c</PathWithFileName>
|
||||
<FilenameWithoutPath>platform_config.c</FilenameWithoutPath>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Application_Source</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>9</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
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</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DLM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pEMBER</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TLM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments></TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>0</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>0</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>0</RestoreToolbox>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>1</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile>.\LPC43XX-M4-FLASH-DEBUG.ini</InitializationFile>
|
||||
<Driver>BIN\UL2CM3.DLL</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4>.\LPC43XX-M4-FLASH-PROGRAM.ini</Flash4>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>0</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>0</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<VariousControls>
|
||||
<MiscControls>--no_allow_fpreg_for_nonfpdata</MiscControls>
|
||||
<Define>CORE_M4</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\system;..\platform;..\..\Common\include;..\M4;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\platform\M4_PeripheralLibraryFiles</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>1</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>NO_CRP EXT_FLASH</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x10000000</TextAddressRange>
|
||||
<DataAddressRange>0x10004000</DataAddressRange>
|
||||
<ScatterFile>..\platform\M4_Flash.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--debug --pad=0xFF</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings>6312</DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>System Code</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_LPC43xx.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\platform\startup_LPC43xx.s</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>system_LPC43xx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\system\system_LPC43xx.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>core_cm4.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\system\core_cm4.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>emc_LPC43xx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\system\emc_LPC43xx.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>scu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\system\scu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fpu_init.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\system\fpu_init.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Platform</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>platform_config.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\platform\platform_config.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>platform_config.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\platform\platform_config.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Application_Source</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ParTest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\ParTest.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>RegTest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\RegTest.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>FreeRTOS_Source</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>port.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>heap_2.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\portable\MemMang\heap_2.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>timers.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\timers.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>list.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\list.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tasks.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\tasks.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Common_Demo_Source</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>sp_flop.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\sp_flop.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>BlockQ.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\BlockQ.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>blocktim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\blocktim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>countsem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\countsem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>death.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\death.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>dynamic.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\dynamic.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\flash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>GenQTest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\GenQTest.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>integer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\integer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>PollQ.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\PollQ.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>recmutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\recmutex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>semtest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\semtest.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Peripheral_Library</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>lpc43xx_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\platform\M4_PeripheralLibraryFiles\lpc43xx_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>lpc43xx_cgu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\platform\M4_PeripheralLibraryFiles\lpc43xx_cgu.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
@ -0,0 +1,188 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Normally, a demo application would define ParTest (parallel port test)
|
||||
* functions to write to an LED. In this case, four '*' symbols that are
|
||||
* output to the debug printf() port are used to simulate LED outputs.
|
||||
*-----------------------------------------------------------*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
/* Library includes. */
|
||||
#include "lpc43xx_i2c.h"
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "queue.h"
|
||||
|
||||
/* Standard demo include. */
|
||||
#include "partest.h"
|
||||
|
||||
/* The number of LED outputs. */
|
||||
#define partstMAX_LEDS 4
|
||||
|
||||
/* Commands written to the PCA9502. */
|
||||
#define partstIO_WRITE_COMMAND ( ( unsigned char ) ( 0x0BU << 3U ) )
|
||||
#define partstIO_DIR_COMMAND ( ( unsigned char ) ( 0x0AU << 3U ) )
|
||||
#define partstSLAVE_ADDRESS ( ( unsigned char ) ( 0x9AU >> 1U ) )
|
||||
|
||||
/* Just defines the length of the queue used to pass toggle commands to the I2C
|
||||
gatekeeper task. */
|
||||
#define partstLED_COMMAND_QUEUE_LENGTH ( 6 )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The LEDs are connected to an I2C port expander. Therefore, writing to an
|
||||
* LED takes longer than might be expected if the LED was connected directly
|
||||
* to a GPIO pin. As several tasks, and a timer, toggle LEDs, it is convenient
|
||||
* to use a gatekeeper task to ensure access is both mutually exclusive and
|
||||
* serialised. Tasks other than this gatekeeper task must not access the I2C
|
||||
* port directly.
|
||||
*/
|
||||
static void prvI2CGateKeeperTask( void *pvParameters );
|
||||
|
||||
/* The queue used to communicate toggle commands with the I2C gatekeeper
|
||||
task. */
|
||||
static xQueueHandle xI2CCommandQueue = NULL;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestInitialise( void )
|
||||
{
|
||||
unsigned char ucBuffer[ 2 ];
|
||||
I2C_M_SETUP_Type xI2CMessage;
|
||||
|
||||
/* The LEDs are on an I2C IO expander. Initialise the I2C interface. */
|
||||
I2C_Init( LPC_I2C0, 300000 );
|
||||
I2C_Cmd( LPC_I2C0, ENABLE );
|
||||
|
||||
/* GPIO0-GPIO2 to output. */
|
||||
ucBuffer[ 0 ] = partstIO_DIR_COMMAND;
|
||||
ucBuffer[ 1 ] = 0x0f;
|
||||
xI2CMessage.sl_addr7bit = partstSLAVE_ADDRESS;
|
||||
xI2CMessage.tx_data = ucBuffer ;
|
||||
xI2CMessage.tx_length = sizeof( ucBuffer );
|
||||
xI2CMessage.rx_data = NULL;
|
||||
xI2CMessage.rx_length = 0;
|
||||
xI2CMessage.retransmissions_max = 3;
|
||||
I2C_MasterTransferData( LPC_I2C0, &xI2CMessage, I2C_TRANSFER_POLLING );
|
||||
|
||||
/* Create the mutex used to guard access to the I2C bus. */
|
||||
xI2CCommandQueue = xQueueCreate( partstLED_COMMAND_QUEUE_LENGTH, sizeof( unsigned char ) );
|
||||
configASSERT( xI2CCommandQueue );
|
||||
|
||||
/* Create the I2C gatekeeper task itself. */
|
||||
xTaskCreate( prvI2CGateKeeperTask, ( signed char * ) "I2C", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestToggleLED( unsigned long ulLED )
|
||||
{
|
||||
unsigned char ucLED = ( unsigned char ) ulLED;
|
||||
|
||||
/* Only the gatekeeper task will actually access the I2C port, so send the
|
||||
toggle request to the gatekeeper task. A block time of zero is used as
|
||||
this function is called by a software timer callback. */
|
||||
xQueueSend( xI2CCommandQueue, &ucLED, 0UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvI2CGateKeeperTask( void *pvParameters )
|
||||
{
|
||||
unsigned char ucBuffer[ 2 ], ucLED;
|
||||
static unsigned char ucLEDState = 0xffU;
|
||||
static I2C_M_SETUP_Type xI2CMessage; /* Static so it is not on the stack as this is called from task code. */
|
||||
|
||||
/* Just to remove compiler warnings. */
|
||||
( void ) pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait for the next command. */
|
||||
xQueueReceive( xI2CCommandQueue, &ucLED, portMAX_DELAY );
|
||||
|
||||
/* Only this task is allowed to touch the I2C port, so there is no need
|
||||
for additional mutual exclusion. */
|
||||
if( ucLED < partstMAX_LEDS )
|
||||
{
|
||||
/* Which bit is being manipulated? */
|
||||
ucLED = 0x01 << ucLED;
|
||||
|
||||
/* Is the bit currently set or clear? */
|
||||
if( ( ucLEDState & ucLED ) == 0U )
|
||||
{
|
||||
ucLEDState |= ucLED;
|
||||
}
|
||||
else
|
||||
{
|
||||
ucLEDState &= ~ucLED;
|
||||
}
|
||||
|
||||
ucBuffer[ 0 ] = partstIO_WRITE_COMMAND;
|
||||
ucBuffer[ 1 ] = ucLEDState;
|
||||
|
||||
xI2CMessage.sl_addr7bit = partstSLAVE_ADDRESS;
|
||||
xI2CMessage.tx_data = ucBuffer ;
|
||||
xI2CMessage.tx_length = sizeof( ucBuffer );
|
||||
xI2CMessage.rx_data = NULL;
|
||||
xI2CMessage.rx_length = 0;
|
||||
xI2CMessage.retransmissions_max = 3;
|
||||
I2C_MasterTransferData( LPC_I2C0, &xI2CMessage, I2C_TRANSFER_POLLING );
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -0,0 +1,502 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
__asm vRegTest1Task( void )
|
||||
{
|
||||
PRESERVE8
|
||||
IMPORT ulRegTest1LoopCounter
|
||||
|
||||
/* Fill the core registers with known values. */
|
||||
mov r0, #100
|
||||
mov r1, #101
|
||||
mov r2, #102
|
||||
mov r3, #103
|
||||
mov r4, #104
|
||||
mov r5, #105
|
||||
mov r6, #106
|
||||
mov r7, #107
|
||||
mov r8, #108
|
||||
mov r9, #109
|
||||
mov r10, #110
|
||||
mov r11, #111
|
||||
mov r12, #112
|
||||
|
||||
/* Fill the VFP registers with known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg1_loop
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg1_loopf_pass
|
||||
|
||||
reg1_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg1_error_loopf
|
||||
|
||||
reg1_loopf_pass
|
||||
|
||||
cmp r0, #100
|
||||
bne reg1_error_loop
|
||||
cmp r1, #101
|
||||
bne reg1_error_loop
|
||||
cmp r2, #102
|
||||
bne reg1_error_loop
|
||||
cmp r3, #103
|
||||
bne reg1_error_loop
|
||||
cmp r4, #104
|
||||
bne reg1_error_loop
|
||||
cmp r5, #105
|
||||
bne reg1_error_loop
|
||||
cmp r6, #106
|
||||
bne reg1_error_loop
|
||||
cmp r7, #107
|
||||
bne reg1_error_loop
|
||||
cmp r8, #108
|
||||
bne reg1_error_loop
|
||||
cmp r9, #109
|
||||
bne reg1_error_loop
|
||||
cmp r10, #110
|
||||
bne reg1_error_loop
|
||||
cmp r11, #111
|
||||
bne reg1_error_loop
|
||||
cmp r12, #112
|
||||
bne reg1_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest1LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg1_loop
|
||||
|
||||
reg1_error_loop
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg1_error_loop
|
||||
nop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm vRegTest2Task( void )
|
||||
{
|
||||
PRESERVE8
|
||||
IMPORT ulRegTest2LoopCounter
|
||||
|
||||
/* Set all the core registers to known values. */
|
||||
mov r0, #-1
|
||||
mov r1, #1
|
||||
mov r2, #2
|
||||
mov r3, #3
|
||||
mov r4, #4
|
||||
mov r5, #5
|
||||
mov r6, #6
|
||||
mov r7, #7
|
||||
mov r8, #8
|
||||
mov r9, #9
|
||||
mov r10, #10
|
||||
mov r11, #11
|
||||
mov r12, #12
|
||||
|
||||
/* Set all the VFP to known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg2_loop
|
||||
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg2_loopf_pass
|
||||
|
||||
reg2_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg2_error_loopf
|
||||
|
||||
reg2_loopf_pass
|
||||
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loop
|
||||
cmp r1, #1
|
||||
bne reg2_error_loop
|
||||
cmp r2, #2
|
||||
bne reg2_error_loop
|
||||
cmp r3, #3
|
||||
bne reg2_error_loop
|
||||
cmp r4, #4
|
||||
bne reg2_error_loop
|
||||
cmp r5, #5
|
||||
bne reg2_error_loop
|
||||
cmp r6, #6
|
||||
bne reg2_error_loop
|
||||
cmp r7, #7
|
||||
bne reg2_error_loop
|
||||
cmp r8, #8
|
||||
bne reg2_error_loop
|
||||
cmp r9, #9
|
||||
bne reg2_error_loop
|
||||
cmp r10, #10
|
||||
bne reg2_error_loop
|
||||
cmp r11, #11
|
||||
bne reg2_error_loop
|
||||
cmp r12, #12
|
||||
bne reg2_error_loop
|
||||
|
||||
/* Increment the loop counter to indicate this test is still functioning
|
||||
correctly. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest2LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg2_loop
|
||||
|
||||
reg2_error_loop
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
This loop ensures the loop counter variable stops incrementing. */
|
||||
b reg2_error_loop
|
||||
nop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
|
||||
{
|
||||
PRESERVE8
|
||||
|
||||
/* Clobber the auto saved registers. */
|
||||
vmov d0, r0, r0
|
||||
vmov d1, r0, r0
|
||||
vmov d2, r0, r0
|
||||
vmov d3, r0, r0
|
||||
vmov d4, r0, r0
|
||||
vmov d5, r0, r0
|
||||
vmov d6, r0, r0
|
||||
vmov d7, r0, r0
|
||||
bx lr
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
|
||||
{
|
||||
PRESERVE8
|
||||
|
||||
vmov r1, s0
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s1
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s2
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s3
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s4
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s5
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s6
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s7
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s8
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s9
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s10
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s11
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s12
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s13
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s14
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s15
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
|
||||
return_pass
|
||||
mov r0, #1
|
||||
bx lr
|
||||
|
||||
return_error
|
||||
mov r0, #0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,442 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* >>>>>> NOTE 1: <<<<<<
|
||||
*
|
||||
* main() can be configured to create either a very simple LED flasher demo, or
|
||||
* a more comprehensive test/demo application.
|
||||
*
|
||||
* To create a very simple LED flasher example, set the
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant (defined below) to 1. When
|
||||
* this is done, only the standard demo flash tasks are created. The standard
|
||||
* demo flash example creates three tasks, each of which toggle an LED at a
|
||||
* fixed but different frequency.
|
||||
*
|
||||
* To create a more comprehensive test and demo application, set
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0.
|
||||
******************************************************************************
|
||||
*
|
||||
* main() creates all the demo application tasks and software timers, then starts
|
||||
* the scheduler. The web documentation provides more details of the standard
|
||||
* demo application tasks, which provide no particular functionality, but do
|
||||
* provide a good example of how to use the FreeRTOS API.
|
||||
*
|
||||
* In addition to the standard demo tasks, the following tasks and tests are
|
||||
* defined and/or created within this file:
|
||||
*
|
||||
* "Reg test" tasks - These fill both the core and floating point registers with
|
||||
* known values, then check that each register maintains its expected value for
|
||||
* the lifetime of the task. Each task uses a different set of values. The reg
|
||||
* test tasks execute with a very low priority, so get preempted very
|
||||
* frequently. A register containing an unexpected value is indicative of an
|
||||
* error in the context switching mechanism.
|
||||
*
|
||||
* "Check" timer - The check software timer period is initially set to three
|
||||
* seconds. The callback function associated with the check software timer
|
||||
* checks that all the standard demo tasks, and the register check tasks, are
|
||||
* not only still executing, but are executing without reporting any errors. If
|
||||
* the check software timer discovers that a task has either stalled, or
|
||||
* reported an error, then it changes its own execution period from the initial
|
||||
* three seconds, to just 200ms. The check software timer callback function
|
||||
* also toggles an LED each time it is called. This provides a visual
|
||||
* indication of the system status: If the LED toggles every three seconds,
|
||||
* then no issues have been discovered. If the LED toggles every 200ms, then
|
||||
* an issue has been discovered with at least one task.
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "timers.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Demo application includes. */
|
||||
#include "partest.h"
|
||||
#include "flash.h"
|
||||
#include "flop.h"
|
||||
#include "integer.h"
|
||||
#include "PollQ.h"
|
||||
#include "semtest.h"
|
||||
#include "dynamic.h"
|
||||
#include "BlockQ.h"
|
||||
#include "blocktim.h"
|
||||
#include "countsem.h"
|
||||
#include "GenQTest.h"
|
||||
#include "recmutex.h"
|
||||
#include "death.h"
|
||||
|
||||
/* Hardware includes. */
|
||||
#include "platform_config.h"
|
||||
|
||||
/* Priorities for the demo application tasks. */
|
||||
#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL )
|
||||
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
|
||||
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
|
||||
|
||||
/* The LED used by the check timer. */
|
||||
#define mainCHECK_LED ( 3UL )
|
||||
|
||||
/* A block time of zero simply means "don't block". */
|
||||
#define mainDONT_BLOCK ( 0UL )
|
||||
|
||||
/* The period after which the check timer will expire, in ms, provided no errors
|
||||
have been reported by any of the standard demo tasks. ms are converted to the
|
||||
equivalent in ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
|
||||
|
||||
/* The period at which the check timer will expire, in ms, if an error has been
|
||||
reported in one of the standard demo tasks. ms are converted to the equivalent
|
||||
in ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
|
||||
|
||||
/* Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 1 to create a simple demo.
|
||||
Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more
|
||||
comprehensive test application. See the comments at the top of this file, and
|
||||
the documentation page on the http://www.FreeRTOS.org web site for more
|
||||
information. */
|
||||
#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Set up the hardware ready to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*
|
||||
* The check timer callback function, as described at the top of this file.
|
||||
*/
|
||||
static void prvCheckTimerCallback( xTimerHandle xTimer );
|
||||
|
||||
/*
|
||||
* Register check tasks, and the tasks used to write over and check the contents
|
||||
* of the FPU registers, as described at the top of this file. The nature of
|
||||
* these files necessitates that they are written in an assembly file.
|
||||
*/
|
||||
extern void vRegTest1Task( void *pvParameters );
|
||||
extern void vRegTest2Task( void *pvParameters );
|
||||
extern void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue );
|
||||
extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue );
|
||||
|
||||
/*
|
||||
* This file can be used to create either a simple LED flasher example, or a
|
||||
* comprehensive test/demo application - depending on the setting of the
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant defined above. If
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 1, then the following
|
||||
* function will create a lot of additional tasks and a software timer. If
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0, then the following
|
||||
* function will do nothing.
|
||||
*/
|
||||
static void prvOptionallyCreateComprehensveTestApplication( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The following two variables are used to communicate the status of the
|
||||
register check tasks to the check software timer. If the variables keep
|
||||
incrementing, then the register check tasks has not discovered any errors. If
|
||||
a variable stops incrementing, then an error has been found. */
|
||||
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* Configure the hardware ready to run the test. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* Start standard demo/test application flash tasks. See the comments at
|
||||
the top of this file. The LED flash tasks are always created. The other
|
||||
tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to
|
||||
0 (at the top of this file). See the comments at the top of this file for
|
||||
more information. */
|
||||
vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
|
||||
|
||||
/* The following function will only create more tasks and timers if
|
||||
mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this
|
||||
file). See the comments at the top of this file for more information. */
|
||||
prvOptionallyCreateComprehensveTestApplication();
|
||||
|
||||
/* Start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Infinite loop */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckTimerCallback( xTimerHandle xTimer )
|
||||
{
|
||||
static long lChangedTimerPeriodAlready = pdFALSE;
|
||||
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
|
||||
unsigned long ulErrorFound = pdFALSE;
|
||||
|
||||
/* Check all the demo tasks (other than the flash tasks) to ensure
|
||||
that they are all still running, and that none have detected an error. */
|
||||
|
||||
if( xAreMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 0UL;
|
||||
}
|
||||
|
||||
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 1UL;
|
||||
}
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 2UL;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 3UL;
|
||||
}
|
||||
|
||||
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 4UL;
|
||||
}
|
||||
|
||||
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 5UL;
|
||||
}
|
||||
|
||||
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 6UL;
|
||||
}
|
||||
|
||||
if( xIsCreateTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 7UL;
|
||||
}
|
||||
|
||||
if( xArePollingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 8UL;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 9UL;
|
||||
}
|
||||
|
||||
/* Check that the register test 1 task is still running. */
|
||||
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 10UL;
|
||||
}
|
||||
ulLastRegTest1Value = ulRegTest1LoopCounter;
|
||||
|
||||
/* Check that the register test 2 task is still running. */
|
||||
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
|
||||
{
|
||||
ulErrorFound |= 0x01UL << 11UL;
|
||||
}
|
||||
ulLastRegTest2Value = ulRegTest2LoopCounter;
|
||||
|
||||
/* Toggle the check LED to give an indication of the system status. If
|
||||
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
|
||||
everything is ok. A faster toggle indicates an error. */
|
||||
vParTestToggleLED( mainCHECK_LED );
|
||||
|
||||
/* Have any errors been latch in ulErrorFound? If so, shorten the
|
||||
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
|
||||
This will result in an increase in the rate at which mainCHECK_LED
|
||||
toggles. */
|
||||
if( ulErrorFound != pdFALSE )
|
||||
{
|
||||
if( lChangedTimerPeriodAlready == pdFALSE )
|
||||
{
|
||||
lChangedTimerPeriodAlready = pdTRUE;
|
||||
|
||||
/* This call to xTimerChangePeriod() uses a zero block time.
|
||||
Functions called from inside of a timer callback function must
|
||||
*never* attempt to block. */
|
||||
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
/* Setup system (clock, PLL and Flash configuration) */
|
||||
platformInit();
|
||||
|
||||
/* Ensure all priority bits are assigned as preemption priority bits. */
|
||||
NVIC_SetPriorityGrouping( 0 );
|
||||
|
||||
/* Setup the LED outputs. */
|
||||
vParTestInitialise();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvOptionallyCreateComprehensveTestApplication( void )
|
||||
{
|
||||
#if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )
|
||||
{
|
||||
xTimerHandle xCheckTimer = NULL;
|
||||
|
||||
/* Start all the other standard demo/test tasks. */
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vCreateBlockTimeTasks();
|
||||
vStartCountingSemaphoreTasks();
|
||||
vStartGenericQueueTasks( tskIDLE_PRIORITY );
|
||||
vStartRecursiveMutexTasks();
|
||||
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
|
||||
/* Most importantly, start the tasks that use the FPU. */
|
||||
vStartMathTasks( mainFLOP_TASK_PRIORITY );
|
||||
|
||||
/* Create the register check tasks, as described at the top of this
|
||||
file */
|
||||
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
|
||||
/* Create the software timer that performs the 'check' functionality,
|
||||
as described at the top of this file. */
|
||||
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
|
||||
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
|
||||
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
|
||||
( void * ) 0, /* The ID is not used, so can be set to anything. */
|
||||
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
|
||||
);
|
||||
|
||||
if( xCheckTimer != NULL )
|
||||
{
|
||||
xTimerStart( xCheckTimer, mainDONT_BLOCK );
|
||||
}
|
||||
|
||||
/* This task has to be created last as it keeps account of the number of
|
||||
tasks it expects to see running. */
|
||||
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
|
||||
}
|
||||
#else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */
|
||||
{
|
||||
/* Just to prevent compiler warnings when the configuration options are
|
||||
set such that these static functions are not used. */
|
||||
( void ) vRegTest1Task;
|
||||
( void ) vRegTest2Task;
|
||||
( void ) prvCheckTimerCallback;
|
||||
( void ) prvSetupNestedFPUInterruptsTest;
|
||||
}
|
||||
#endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook( void )
|
||||
{
|
||||
/* vApplicationMallocFailedHook() will only be called if
|
||||
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
|
||||
function that will get called if a call to pvPortMalloc() fails.
|
||||
pvPortMalloc() is called internally by the kernel whenever a task, queue,
|
||||
timer or semaphore is created. It is also called by various parts of the
|
||||
demo application. If heap_1.c or heap_2.c are used, then the size of the
|
||||
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
|
||||
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
|
||||
to query the size of free heap space that remains (although it does not
|
||||
provide information on how the remaining heap might be fragmented). */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
|
||||
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
|
||||
task. It is essential that code added to this hook function never attempts
|
||||
to block in any way (for example, call xQueueReceive() with a block time
|
||||
specified, or call vTaskDelay()). If the application makes use of the
|
||||
vTaskDelete() API function (as this demo application does) then it is also
|
||||
important that vApplicationIdleHook() is permitted to return to its calling
|
||||
function, because it is the responsibility of the idle task to clean up
|
||||
memory allocated by the kernel to any task that has since been deleted. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
|
||||
{
|
||||
( void ) pcTaskName;
|
||||
( void ) pxTask;
|
||||
|
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
/* This function will be called by each tick interrupt if
|
||||
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
|
||||
added here, but the tick hook is called from an interrupt context, so
|
||||
code must not attempt to block, and only the interrupt safe FreeRTOS API
|
||||
functions can be used (those that end in FromISR()). */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
@ -0,0 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<WorkspaceName>WorkSpace</WorkspaceName>
|
||||
|
||||
<project>
|
||||
<PathAndName>.\M4\M4.uvproj</PathAndName>
|
||||
<NodeIsActive>1</NodeIsActive>
|
||||
<NodeIsExpanded>1</NodeIsExpanded>
|
||||
</project>
|
||||
|
||||
</ProjectWorkspace>
|
||||
@ -0,0 +1,53 @@
|
||||
IPC demo program based on mailbox
|
||||
-----------------------------------------
|
||||
|
||||
- within the file platform_config.h the user needs to specify the system configuration.
|
||||
|
||||
|
||||
The user can specifiy:
|
||||
|
||||
* which mailboxes are required (host, slave, or both)
|
||||
|
||||
* if the M0 memory has to be initialized to a specific value before download
|
||||
|
||||
* the usage of an optional 32-bit parameter for the mailboxes
|
||||
|
||||
* the availability of a callback function for the mailboxes
|
||||
|
||||
* the priority of the interrupt associated with the IPC communication
|
||||
|
||||
* the memory locations of the M0 code/data, buffers for M0 and M4, location of the mailboxes
|
||||
|
||||
* if the M4 shall download the M0 and start it via INITIALIZE_M0_IMAGE (YES/NO)
|
||||
|
||||
The linker scatter file needs to be consistent with the provided ROM/RAM addresses in case of changes.
|
||||
|
||||
Set it to NO if you want to debug the M0 application separately.
|
||||
|
||||
Set to YES means the M4 will reset, download, and release the M0. In this case, the debug connection could be lost.
|
||||
|
||||
For debugging, in this scenario the .ini file shall be modified, not to download the application but just to connect to the processor.
|
||||
|
||||
|
||||
- according to the number of mailbox desired, if callbacks are enabled, the user has to provide a callback table within the Mx_usr_mbx_callbacks.c file.
|
||||
|
||||
In Mx_usr_mbx_callbacks.h file the mailbox numbering is defined. Within the callback table, each callback gets associated to the related mailbox number.
|
||||
|
||||
The order in the table is not important, since the callback function addresses are plugged-in at runtime by the IPC initialization routines.
|
||||
|
||||
|
||||
- The mailbox table defined in ipc_buffer.c needs also to be updated accordingly to accomodate the desired number of mailboxes. There can be
|
||||
|
||||
|
||||
- since the callbacks are executed within the ISR, their usage is meant for quick operations that need to be performed in reaction to the mailbox event
|
||||
|
||||
For normal application processing, message pending flags are provided and shall rather be used, to avoid increasing unnecessarily interrupt latency
|
||||
|
||||
|
||||
- the type of logical messages for the mailboxes are defined within the Mx_ipc_msg.h file
|
||||
|
||||
|
||||
- the application runs completely from RAM and exchanges messages between the processors, showing how to post and read from the mailboxes.
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,46 @@
|
||||
; memory map assignment
|
||||
; check with platform_config.h header
|
||||
; check the ranges
|
||||
|
||||
; #define M4_ROM_START 0x1C000000
|
||||
; #define M4_ROM_LEN 0x400000 /* 4 Mbytes */
|
||||
LR_IROM1 0x1C000000 0x400000 { ; load region size_region
|
||||
|
||||
ER_IROM1 0x1C000000 0x400000 { ; load address = execution address
|
||||
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; #define M4_RAM_START 0x10000000 /* 96 Kbytes */
|
||||
; #define M4_RAM_LEN 0x18000
|
||||
|
||||
; this region includes just the relocated vector table
|
||||
; not used by anything else
|
||||
ER_RELOCIRQ 0x10000000 0xC0 {
|
||||
}
|
||||
|
||||
RW_IRAM1 +0 (0x18000 - 0xC0) { ; RW data
|
||||
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
; #define M4_BUF_START 0x20000000
|
||||
; #define M4_BUF_LEN 0x4000
|
||||
RW_IRAM_BUFFERS 0x20000000 0x4000 { ; rw buffers
|
||||
|
||||
}
|
||||
|
||||
; #define M4_MBX_START 0x20008000
|
||||
; #define M4_MBX_LEN 0x2000
|
||||
RW_IRAM_MBX 0x20008000 0x2000 {
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,916 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_cgu.c 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_cgu.c
|
||||
* @brief Contains all functions support for Clock Generation and Control
|
||||
* firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @addtogroup CGU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
|
||||
/** This define used to fix mistake when run with IAR compiler */
|
||||
#ifdef __ICCARM__
|
||||
#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001
|
||||
#else
|
||||
#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01
|
||||
#endif
|
||||
|
||||
/*TODO List:
|
||||
* SET PLL0
|
||||
* UPDATE Clock from PLL0
|
||||
* SetDIV uncheck value
|
||||
* GetBaseStatus BASE_SAFE
|
||||
* */
|
||||
/* Local definition */
|
||||
#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))
|
||||
|
||||
/* Local Variable */
|
||||
const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {
|
||||
-1, //CGU_CLKSRC_32KHZ_OSC,
|
||||
-1, //CGU_CLKSRC_IRC,
|
||||
-1, //CGU_CLKSRC_ENET_RX_CLK,
|
||||
-1, //CGU_CLKSRC_ENET_TX_CLK,
|
||||
-1, //CGU_CLKSRC_GP_CLKIN,
|
||||
-1, //CGU_CLKSRC_TCK,
|
||||
0x18, //CGU_CLKSRC_XTAL_OSC,
|
||||
0x20, //CGU_CLKSRC_PLL0,
|
||||
0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**
|
||||
0x44, //CGU_CLKSRC_PLL1,
|
||||
-1, //CGU_CLKSRC_RESERVE,
|
||||
-1, //CGU_CLKSRC_RESERVE,
|
||||
0x48, //CGU_CLKSRC_IDIVA,,
|
||||
0x4C, //CGU_CLKSRC_IDIVB,
|
||||
0x50, //CGU_CLKSRC_IDIVC,
|
||||
0x54, //CGU_CLKSRC_IDIVD,
|
||||
0x58, //CGU_CLKSRC_IDIVE,
|
||||
|
||||
0x5C, //CGU_BASE_SAFE,
|
||||
0x60, //CGU_BASE_USB0,
|
||||
-1, //CGU_BASE_RESERVE,
|
||||
0x68, //CGU_BASE_USB1,
|
||||
0x6C, //CGU_BASE_M3,
|
||||
0x70, //CGU_BASE_SPIFI,
|
||||
-1, //CGU_BASE_RESERVE,
|
||||
0x78, //CGU_BASE_PHY_RX,
|
||||
0x7C, //CGU_BASE_PHY_TX,
|
||||
0x80, //CGU_BASE_APB1,
|
||||
0x84, //CGU_BASE_APB3,
|
||||
0x88, //CGU_BASE_LCD,
|
||||
0X8C, //CGU_BASE_ENET_CSR, **REV A**
|
||||
0x90, //CGU_BASE_SDIO,
|
||||
0x94, //CGU_BASE_SSP0,
|
||||
0x98, //CGU_BASE_SSP1,
|
||||
0x9C, //CGU_BASE_UART0,
|
||||
0xA0, //CGU_BASE_UART1,
|
||||
0xA4, //CGU_BASE_UART2,
|
||||
0xA8, //CGU_BASE_UART3,
|
||||
0xAC, //CGU_BASE_CLKOUT
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
0xC0, //CGU_BASE_APLL
|
||||
0xC4, //CGU_BASE_OUT0
|
||||
0xC8 //CGU_BASE_OUT1
|
||||
};
|
||||
|
||||
const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {
|
||||
// 3 I E E G T X P P P x x D D D D D S U x U M S x P P A A L E S S S U U U U C x x x x A O O
|
||||
// 2 R R T P C T L L L I I I I I A S S 3 P H H P P C N D S S R R R R O P U U
|
||||
// C X X I K A 0 A 1 A B C D E F B B F RxTx1 3 D T I 0 1 0 1 2 3 L T T
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_32KHZ_OSC = 0,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IRC,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_RX_CLK,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_TX_CLK,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_GP_CLKIN,*/
|
||||
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0},/*CGU_CLKSRC_TCK,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_XTAL_OSC,*/
|
||||
{0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1},/*CGU_CLKSRC_PLL0,*/
|
||||
{0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL0_AUDIO,*/
|
||||
{0,0,0,0,0,0,0,1,1,0,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL1,*/
|
||||
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
|
||||
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVB,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVC,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVD,*/
|
||||
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1}/*CGU_CLKSRC_IDIVE,*/
|
||||
};
|
||||
|
||||
const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {
|
||||
/* Register Clock | Peripheral Clock
|
||||
| BASE | BRANCH | BASE | BRANCH */
|
||||
{CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,
|
||||
{CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,
|
||||
{CGU_BASE_M3, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,
|
||||
//// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
|
||||
{CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,
|
||||
{CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,
|
||||
{CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,
|
||||
{CGU_BASE_M3, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,
|
||||
{CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,
|
||||
{CGU_BASE_M3, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,
|
||||
{CGU_BASE_M3, 0x1430, CGU_BASE_M3, 0x1478, 0},//CGU_PERIPHERAL_EMC,
|
||||
{CGU_BASE_M3, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,
|
||||
{CGU_ENTITY_NONE,0x0000, CGU_BASE_PHY_TX, 0x0000, 0},//CGU_PERIPHERAL_ETHERNET_TX
|
||||
{CGU_BASE_M3, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,
|
||||
{CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,
|
||||
{CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,
|
||||
{CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,
|
||||
{CGU_BASE_M3, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,
|
||||
{CGU_BASE_M3, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,
|
||||
{CGU_BASE_M3, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,
|
||||
{CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,
|
||||
{CGU_BASE_M3, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,
|
||||
{CGU_BASE_M3, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,
|
||||
{CGU_BASE_M3, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,
|
||||
{CGU_BASE_M3, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,
|
||||
{CGU_BASE_M3, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,
|
||||
{CGU_BASE_M3, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,
|
||||
{CGU_BASE_M3, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,
|
||||
{CGU_BASE_M3, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,
|
||||
{CGU_BASE_M3, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,
|
||||
{CGU_BASE_M3, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,
|
||||
{CGU_BASE_M3, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,
|
||||
{CGU_BASE_M3, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,
|
||||
{CGU_BASE_M3, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,
|
||||
{CGU_BASE_M3, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,
|
||||
{CGU_BASE_M3, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,
|
||||
{CGU_BASE_M3, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,
|
||||
{CGU_BASE_M3, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,
|
||||
{CGU_BASE_M3, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,
|
||||
{CGU_BASE_M3, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,
|
||||
};
|
||||
|
||||
uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0,12000000,0,0,0,0, 0, 480000000,0,0,0,0,0,0,0,0,0};
|
||||
|
||||
#define CGU_CGU_ADDR ((uint32_t)LPC_CGU)
|
||||
#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))
|
||||
#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))
|
||||
#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
|
||||
|
||||
#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))
|
||||
#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))
|
||||
#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Initialize default clock for LPC4300 Eval board
|
||||
* @param[in] None
|
||||
* @return Initialize status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - Other: error
|
||||
**********************************************************************/
|
||||
uint32_t CGU_Init(void){
|
||||
CGU_SetXTALOSC(12000000);
|
||||
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
|
||||
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
|
||||
// Disable PLL1 CPU hang???
|
||||
//CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);
|
||||
CGU_SetPLL1(6);
|
||||
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
|
||||
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
|
||||
CGU_UpdateClock();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Configure power for individual peripheral
|
||||
* @param[in] PPType peripheral type, should be:
|
||||
* - CGU_PERIPHERAL_ADC0 :ADC0
|
||||
* - CGU_PERIPHERAL_ADC1 :ADC1
|
||||
* - CGU_PERIPHERAL_AES :AES
|
||||
* - CGU_PERIPHERAL_APB1_BUS :APB1 bus
|
||||
* - CGU_PERIPHERAL_APB3_BUS :APB3 bus
|
||||
* - CGU_PERIPHERAL_CAN :CAN
|
||||
* - CGU_PERIPHERAL_CREG :CREG
|
||||
* - CGU_PERIPHERAL_DAC :DAC
|
||||
* - CGU_PERIPHERAL_DMA :DMA
|
||||
* - CGU_PERIPHERAL_EMC :EMC
|
||||
* - CGU_PERIPHERAL_ETHERNET :ETHERNET
|
||||
* - CGU_PERIPHERAL_GPIO :GPIO
|
||||
* - CGU_PERIPHERAL_I2C0 :I2C0
|
||||
* - CGU_PERIPHERAL_I2C1 :I2C1
|
||||
* - CGU_PERIPHERAL_I2S :I2S
|
||||
* - CGU_PERIPHERAL_LCD :LCD
|
||||
* - CGU_PERIPHERAL_M3CORE :M3 core
|
||||
* - CGU_PERIPHERAL_M3_BUS :M3 bus
|
||||
* - CGU_PERIPHERAL_MOTOCON :Motor control
|
||||
* - CGU_PERIPHERAL_QEI :QEI
|
||||
* - CGU_PERIPHERAL_RITIMER :RIT timer
|
||||
* - CGU_PERIPHERAL_SCT :SCT
|
||||
* - CGU_PERIPHERAL_SCU :SCU
|
||||
* - CGU_PERIPHERAL_SDIO :SDIO
|
||||
* - CGU_PERIPHERAL_SPIFI :SPIFI
|
||||
* - CGU_PERIPHERAL_SSP0 :SSP0
|
||||
* - CGU_PERIPHERAL_SSP1 :SSP1
|
||||
* - CGU_PERIPHERAL_TIMER0 :TIMER0
|
||||
* - CGU_PERIPHERAL_TIMER1 :TIMER1
|
||||
* - CGU_PERIPHERAL_TIMER2 :TIMER2
|
||||
* - CGU_PERIPHERAL_TIMER3 :TIMER3
|
||||
* - CGU_PERIPHERAL_UART0 :UART0
|
||||
* - CGU_PERIPHERAL_UART1 :UART1
|
||||
* - CGU_PERIPHERAL_UART2 :UART2
|
||||
* - CGU_PERIPHERAL_UART3 :UART3
|
||||
* - CGU_PERIPHERAL_USB0 :USB0
|
||||
* - CGU_PERIPHERAL_USB1 :USB1
|
||||
* - CGU_PERIPHERAL_WWDT :WWDT
|
||||
* @param[in] en status, should be:
|
||||
* - ENABLE: Enable power
|
||||
* - DISABLE: Disable power
|
||||
* @return Configure status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - Other: error
|
||||
**********************************************************************/
|
||||
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en){
|
||||
if(PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0)
|
||||
return CGU_ERROR_INVALID_PARAM;
|
||||
if(en == DISABLE){/* Going to disable clock */
|
||||
/*Get Reg branch status */
|
||||
if(CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0 &&
|
||||
CGU_REG_BRANCH_STATUS(PPType) & 1){
|
||||
CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
|
||||
while(CGU_REG_BRANCH_STATUS(PPType) & 1);
|
||||
}
|
||||
/* GetBase Status*/
|
||||
if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) &&
|
||||
CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0){
|
||||
/* Disable Base */
|
||||
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity,0);
|
||||
}
|
||||
|
||||
/* Same for Peripheral */
|
||||
if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
|
||||
CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
|
||||
while(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);
|
||||
}
|
||||
/* GetBase Status*/
|
||||
if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity!=CGU_ENTITY_NONE) &&
|
||||
CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0){
|
||||
/* Disable Base */
|
||||
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity,0);
|
||||
}
|
||||
}else{
|
||||
/* enable */
|
||||
/* GetBase Status*/
|
||||
if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK){
|
||||
/* Enable Base */
|
||||
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);
|
||||
}
|
||||
/*Get Reg branch status */
|
||||
if((CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
|
||||
CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
|
||||
while(!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
|
||||
}
|
||||
|
||||
/* Same for Peripheral */
|
||||
/* GetBase Status*/
|
||||
if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
|
||||
(CGU_PER_BASE_CTRL(PPType) & 1)){
|
||||
/* Enable Base */
|
||||
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);
|
||||
}
|
||||
/*Get Reg branch status */
|
||||
if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
|
||||
CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
|
||||
while(!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(CGU_PERIPHERAL_Info[PPType].next){
|
||||
return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);
|
||||
}
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Get peripheral clock frequency
|
||||
* @param[in] Clock Peripheral type, should be:
|
||||
* - CGU_PERIPHERAL_ADC0 :ADC0
|
||||
* - CGU_PERIPHERAL_ADC1 :ADC1
|
||||
* - CGU_PERIPHERAL_AES :AES
|
||||
* - CGU_PERIPHERAL_APB1_BUS :APB1 bus
|
||||
* - CGU_PERIPHERAL_APB3_BUS :APB3 bus
|
||||
* - CGU_PERIPHERAL_CAN :CAN
|
||||
* - CGU_PERIPHERAL_CREG :CREG
|
||||
* - CGU_PERIPHERAL_DAC :DAC
|
||||
* - CGU_PERIPHERAL_DMA :DMA
|
||||
* - CGU_PERIPHERAL_EMC :EMC
|
||||
* - CGU_PERIPHERAL_ETHERNET :ETHERNET
|
||||
* - CGU_PERIPHERAL_GPIO :GPIO
|
||||
* - CGU_PERIPHERAL_I2C0 :I2C0
|
||||
* - CGU_PERIPHERAL_I2C1 :I2C1
|
||||
* - CGU_PERIPHERAL_I2S :I2S
|
||||
* - CGU_PERIPHERAL_LCD :LCD
|
||||
* - CGU_PERIPHERAL_M3CORE :M3 core
|
||||
* - CGU_PERIPHERAL_M3_BUS :M3 bus
|
||||
* - CGU_PERIPHERAL_MOTOCON :Motor control
|
||||
* - CGU_PERIPHERAL_QEI :QEI
|
||||
* - CGU_PERIPHERAL_RITIMER :RIT timer
|
||||
* - CGU_PERIPHERAL_SCT :SCT
|
||||
* - CGU_PERIPHERAL_SCU :SCU
|
||||
* - CGU_PERIPHERAL_SDIO :SDIO
|
||||
* - CGU_PERIPHERAL_SPIFI :SPIFI
|
||||
* - CGU_PERIPHERAL_SSP0 :SSP0
|
||||
* - CGU_PERIPHERAL_SSP1 :SSP1
|
||||
* - CGU_PERIPHERAL_TIMER0 :TIMER0
|
||||
* - CGU_PERIPHERAL_TIMER1 :TIMER1
|
||||
* - CGU_PERIPHERAL_TIMER2 :TIMER2
|
||||
* - CGU_PERIPHERAL_TIMER3 :TIMER3
|
||||
* - CGU_PERIPHERAL_UART0 :UART0
|
||||
* - CGU_PERIPHERAL_UART1 :UART1
|
||||
* - CGU_PERIPHERAL_UART2 :UART2
|
||||
* - CGU_PERIPHERAL_UART3 :UART3
|
||||
* - CGU_PERIPHERAL_USB0 :USB0
|
||||
* - CGU_PERIPHERAL_USB1 :USB1
|
||||
* - CGU_PERIPHERAL_WWDT :WWDT
|
||||
* @return Return frequently value
|
||||
**********************************************************************/
|
||||
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock){
|
||||
uint32_t ClkSrc;
|
||||
if(Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0)
|
||||
return CGU_ERROR_INVALID_PARAM;
|
||||
|
||||
if(CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE){
|
||||
/* Get Base Clock Source */
|
||||
ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
|
||||
/* GetBase Status*/
|
||||
if(CGU_PER_BASE_CTRL(Clock) & 1)
|
||||
return 0;
|
||||
/* check Branch if it is enabled */
|
||||
if((CGU_PERIPHERAL_Info[Clock].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;
|
||||
}else{
|
||||
if(CGU_REG_BASE_CTRL(Clock) & 1) return 0;
|
||||
ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
|
||||
/* check Branch if it is enabled */
|
||||
if((CGU_PERIPHERAL_Info[Clock].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;
|
||||
}
|
||||
return CGU_ClockSourceFrequency[ClkSrc];
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Update clock
|
||||
* @param[in] None
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
void CGU_UpdateClock(void){
|
||||
uint32_t ClkSrc;
|
||||
uint32_t div;
|
||||
uint32_t divisor;
|
||||
int32_t RegOffset;
|
||||
/* 32OSC */
|
||||
if(ISBITSET(LPC_CREG->CREG0,1) && ISBITCLR(LPC_CREG->CREG0,3))
|
||||
CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;
|
||||
else
|
||||
CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;
|
||||
/*PLL0*/
|
||||
/* PLL1 */
|
||||
if(ISBITCLR(LPC_CGU->PLL1_CTRL,1) /* Enabled */
|
||||
&& (LPC_CGU->PLL1_STAT&1)){ /* Locked? */
|
||||
ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;
|
||||
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *
|
||||
(((LPC_CGU->PLL1_CTRL>>16)&0xFF)+1);
|
||||
}else
|
||||
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;
|
||||
|
||||
/* DIV */
|
||||
for(div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++){
|
||||
RegOffset = CGU_Entity_ControlReg_Offset[div];
|
||||
if(ISBITCLR(CGU_ADDRESS32(LPC_CGU,RegOffset),1)){
|
||||
ClkSrc = (CGU_ADDRESS32(LPC_CGU,RegOffset) & CGU_CTRL_SRC_MASK) >> 24;
|
||||
divisor = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>2) & 0xFF;
|
||||
divisor ++;
|
||||
CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;
|
||||
}else
|
||||
CGU_ClockSourceFrequency[div] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Set XTAL oscillator value
|
||||
* @param[in] ClockFrequency XTAL Frequency value
|
||||
* @return Setting status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range
|
||||
**********************************************************************/
|
||||
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency){
|
||||
if(ClockFrequency < 15000000){
|
||||
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2);
|
||||
}else if(ClockFrequency < 25000000){
|
||||
LPC_CGU->XTAL_OSC_CTRL |= (1<<2);
|
||||
}else
|
||||
return CGU_ERROR_FREQ_OUTOF_RANGE;
|
||||
|
||||
CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Set clock divider
|
||||
* @param[in] SelectDivider Clock source, should be:
|
||||
* - CGU_CLKSRC_IDIVA :Integer divider register A
|
||||
* - CGU_CLKSRC_IDIVB :Integer divider register B
|
||||
* - CGU_CLKSRC_IDIVC :Integer divider register C
|
||||
* - CGU_CLKSRC_IDIVD :Integer divider register D
|
||||
* - CGU_CLKSRC_IDIVE :Integer divider register E
|
||||
* @param[in] divisor Divisor value, should be: 0..255
|
||||
* @return Setting status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - CGU_ERROR_INVALID_ENTITY: Invalid entity
|
||||
**********************************************************************/
|
||||
/* divisor number must >=1*/
|
||||
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor){
|
||||
int32_t RegOffset;
|
||||
uint32_t tempReg;
|
||||
if(SelectDivider>=CGU_CLKSRC_IDIVA && SelectDivider<=CGU_CLKSRC_IDIVE){
|
||||
RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];
|
||||
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
|
||||
tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);
|
||||
tempReg &= ~(0xFF<<2);
|
||||
tempReg |= ((divisor-1)&0xFF)<<2;
|
||||
CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}
|
||||
return CGU_ERROR_INVALID_ENTITY;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Enable clock entity
|
||||
* @param[in] ClockEntity Clock entity, should be:
|
||||
* - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
|
||||
* - CGU_CLKSRC_IRC :IRC clock
|
||||
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
|
||||
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
|
||||
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
|
||||
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
|
||||
* - CGU_CLKSRC_PLL0 :PLL0 clock
|
||||
* - CGU_CLKSRC_PLL1 :PLL1 clock
|
||||
* - CGU_CLKSRC_IDIVA :Integer divider register A
|
||||
* - CGU_CLKSRC_IDIVB :Integer divider register B
|
||||
* - CGU_CLKSRC_IDIVC :Integer divider register C
|
||||
* - CGU_CLKSRC_IDIVD :Integer divider register D
|
||||
* - CGU_CLKSRC_IDIVE :Integer divider register E
|
||||
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
|
||||
* - CGU_BASE_USB0 :Base clock for USB0
|
||||
* - CGU_BASE_USB1 :Base clock for USB1
|
||||
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
|
||||
* and APB peripheral blocks #0 and #2
|
||||
* - CGU_BASE_SPIFI :Base clock for SPIFI
|
||||
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
|
||||
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
|
||||
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
|
||||
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
|
||||
* - CGU_BASE_LCD :Base clock for LCD
|
||||
* - CGU_BASE_SDIO :Base clock for SDIO card reader
|
||||
* - CGU_BASE_SSP0 :Base clock for SSP0
|
||||
* - CGU_BASE_SSP1 :Base clock for SSP1
|
||||
* - CGU_BASE_UART0 :Base clock for UART0
|
||||
* - CGU_BASE_UART1 :Base clock for UART1
|
||||
* - CGU_BASE_UART2 :Base clock for UART2
|
||||
* - CGU_BASE_UART3 :Base clock for UART3
|
||||
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
|
||||
* @param[in] en status, should be:
|
||||
* - ENABLE: Enable power
|
||||
* - DISABLE: Disable power
|
||||
* @return Setting status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - CGU_ERROR_INVALID_ENTITY: Invalid entity
|
||||
**********************************************************************/
|
||||
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en){
|
||||
int32_t RegOffset;
|
||||
int32_t i;
|
||||
if(ClockEntity == CGU_CLKSRC_32KHZ_OSC){
|
||||
if(en){
|
||||
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2));
|
||||
LPC_CREG->CREG0 |= (1<<1)|(1<<0);
|
||||
}else{
|
||||
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0));
|
||||
LPC_CREG->CREG0 |= (1<<3);
|
||||
}
|
||||
for(i = 0;i<1000000;i++);
|
||||
|
||||
}else if(ClockEntity == CGU_CLKSRC_ENET_RX_CLK){
|
||||
scu_pinmux(0xC ,0 , MD_PLN, FUNC3);
|
||||
|
||||
}else if(ClockEntity == CGU_CLKSRC_ENET_TX_CLK){
|
||||
scu_pinmux(0x1 ,19 , MD_PLN, FUNC0);
|
||||
|
||||
}else if(ClockEntity == CGU_CLKSRC_GP_CLKIN){
|
||||
|
||||
}else if(ClockEntity == CGU_CLKSRC_TCK){
|
||||
|
||||
}else if(ClockEntity == CGU_CLKSRC_XTAL_OSC){
|
||||
if(!en)
|
||||
LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;
|
||||
else
|
||||
LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;
|
||||
/*Delay for stable clock*/
|
||||
for(i = 0;i<1000000;i++);
|
||||
|
||||
}else{
|
||||
RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
|
||||
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
|
||||
if(!en){
|
||||
CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) |= CGU_CTRL_EN_MASK;
|
||||
}else{
|
||||
CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) &= ~CGU_CTRL_EN_MASK;
|
||||
/*if PLL is selected check if it is locked */
|
||||
if(ClockEntity == CGU_CLKSRC_PLL0){
|
||||
while((LPC_CGU->PLL0USB_STAT&1) == 0x0);
|
||||
}
|
||||
if(ClockEntity == CGU_CLKSRC_PLL1){
|
||||
while((LPC_CGU->PLL1_STAT&1) == 0x0);
|
||||
/*post check lock status */
|
||||
if(!(LPC_CGU->PLL1_STAT&1))
|
||||
while(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Connect entity clock source
|
||||
* @param[in] ClockSource Clock source, should be:
|
||||
* - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
|
||||
* - CGU_CLKSRC_IRC :IRC clock
|
||||
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
|
||||
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
|
||||
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
|
||||
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
|
||||
* - CGU_CLKSRC_PLL0 :PLL0 clock
|
||||
* - CGU_CLKSRC_PLL1 :PLL1 clock
|
||||
* - CGU_CLKSRC_IDIVA :Integer divider register A
|
||||
* - CGU_CLKSRC_IDIVB :Integer divider register B
|
||||
* - CGU_CLKSRC_IDIVC :Integer divider register C
|
||||
* - CGU_CLKSRC_IDIVD :Integer divider register D
|
||||
* - CGU_CLKSRC_IDIVE :Integer divider register E
|
||||
* @param[in] ClockEntity Clock entity, should be:
|
||||
* - CGU_CLKSRC_PLL0 :PLL0 clock
|
||||
* - CGU_CLKSRC_PLL1 :PLL1 clock
|
||||
* - CGU_CLKSRC_IDIVA :Integer divider register A
|
||||
* - CGU_CLKSRC_IDIVB :Integer divider register B
|
||||
* - CGU_CLKSRC_IDIVC :Integer divider register C
|
||||
* - CGU_CLKSRC_IDIVD :Integer divider register D
|
||||
* - CGU_CLKSRC_IDIVE :Integer divider register E
|
||||
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
|
||||
* - CGU_BASE_USB0 :Base clock for USB0
|
||||
* - CGU_BASE_USB1 :Base clock for USB1
|
||||
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
|
||||
* and APB peripheral blocks #0 and #2
|
||||
* - CGU_BASE_SPIFI :Base clock for SPIFI
|
||||
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
|
||||
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
|
||||
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
|
||||
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
|
||||
* - CGU_BASE_LCD :Base clock for LCD
|
||||
* - CGU_BASE_SDIO :Base clock for SDIO card reader
|
||||
* - CGU_BASE_SSP0 :Base clock for SSP0
|
||||
* - CGU_BASE_SSP1 :Base clock for SSP1
|
||||
* - CGU_BASE_UART0 :Base clock for UART0
|
||||
* - CGU_BASE_UART1 :Base clock for UART1
|
||||
* - CGU_BASE_UART2 :Base clock for UART2
|
||||
* - CGU_BASE_UART3 :Base clock for UART3
|
||||
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
|
||||
* @return Setting status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together
|
||||
* - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error
|
||||
* - CGU_ERROR_INVALID_ENTITY: Invalid entity error
|
||||
**********************************************************************/
|
||||
/* Connect one entity into clock source */
|
||||
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity){
|
||||
int32_t RegOffset;
|
||||
uint32_t tempReg;
|
||||
|
||||
if(ClockSource > CGU_CLKSRC_IDIVE)
|
||||
return CGU_ERROR_INVALID_CLOCK_SOURCE;
|
||||
|
||||
if(ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT){
|
||||
if(CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]){
|
||||
RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];
|
||||
if(RegOffset != -1){
|
||||
if(ClockEntity<=CGU_CLKSRC_IDIVE &&
|
||||
ClockEntity>=CGU_CLKSRC_PLL0)
|
||||
{
|
||||
//RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;
|
||||
if(((CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)& 0xF) == ClockEntity)
|
||||
return CGU_ERROR_CONNECT_TOGETHER;
|
||||
}
|
||||
}
|
||||
RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
|
||||
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
|
||||
tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);
|
||||
tempReg &= ~CGU_CTRL_SRC_MASK;
|
||||
tempReg |= ClockSource<<24 | CGU_CTRL_AUTOBLOCK_MASK;
|
||||
CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}else
|
||||
return CGU_ERROR_INVALID_CLOCK_SOURCE;
|
||||
}else
|
||||
return CGU_ERROR_INVALID_ENTITY;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Get current USB PLL clock from XTAL
|
||||
* @param[in] None
|
||||
* @return Returned clock value
|
||||
**********************************************************************/
|
||||
uint32_t CGU_SetPLL0(void){
|
||||
// Setup PLL550 to generate 480MHz from 12 MHz crystal
|
||||
LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL
|
||||
// P N
|
||||
LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);
|
||||
// SELP SELI SELR MDEC
|
||||
LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);
|
||||
LPC_CGU->PLL0USB_CTRL =(CGU_CLKSRC_XTAL_OSC<<24) | (0x3<<2) | (1<<4);
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Setting PLL1
|
||||
* @param[in] mult Multiple value
|
||||
* @return Setting status, could be:
|
||||
* - CGU_ERROR_SUCCESS: successful
|
||||
* - CGU_ERROR_INVALID_PARAM: Invalid parameter error
|
||||
**********************************************************************/
|
||||
uint32_t CGU_SetPLL1(uint32_t mult){
|
||||
uint32_t msel=0, nsel=0, psel=0, pval=1;
|
||||
uint32_t freq;
|
||||
uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;
|
||||
freq = CGU_ClockSourceFrequency[ClkSrc];
|
||||
freq *= mult;
|
||||
msel = mult-1;
|
||||
|
||||
LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |
|
||||
CGU_PLL1_BYPASS_MASK |
|
||||
CGU_PLL1_DIRECT_MASK |
|
||||
(0x03<<8) | (0xFF<<16) | (0x03<<12));
|
||||
|
||||
if(freq<156000000){
|
||||
//psel is encoded such that 0=1, 1=2, 2=4, 3=8
|
||||
while(2*(pval)*freq < 156000000) {
|
||||
psel++;
|
||||
pval*=2;
|
||||
}
|
||||
// if(2*(pval)*freq > 320000000) {
|
||||
// //THIS IS OUT OF RANGE!!!
|
||||
// //HOW DO WE ASSERT IN SAMPLE CODE?
|
||||
// //__breakpoint(0);
|
||||
// return CGU_ERROR_INVALID_PARAM;
|
||||
// }
|
||||
LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) | CGU_PLL1_FBSEL_MASK;
|
||||
}else if(freq<320000000){
|
||||
LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) |CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;
|
||||
}else
|
||||
return CGU_ERROR_INVALID_PARAM;
|
||||
|
||||
return CGU_ERROR_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Get current base status
|
||||
* @param[in] Base Base type, should be:
|
||||
* - CGU_BASE_USB0 :Base clock for USB0
|
||||
* - CGU_BASE_USB1 :Base clock for USB1
|
||||
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
|
||||
* and APB peripheral blocks #0 and #2
|
||||
* - CGU_BASE_SPIFI :Base clock for SPIFI
|
||||
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
|
||||
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
|
||||
* - CGU_BASE_SDIO :Base clock for SDIO card reader
|
||||
* - CGU_BASE_SSP0 :Base clock for SSP0
|
||||
* - CGU_BASE_SSP1 :Base clock for SSP1
|
||||
* - CGU_BASE_UART0 :Base clock for UART0
|
||||
* - CGU_BASE_UART1 :Base clock for UART1
|
||||
* - CGU_BASE_UART2 :Base clock for UART2
|
||||
* - CGU_BASE_UART3 :Base clock for UART3
|
||||
* @return Always return 0
|
||||
**********************************************************************/
|
||||
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base){
|
||||
switch(Base){
|
||||
/*CCU1*/
|
||||
case CGU_BASE_APB3:
|
||||
return LPC_CCU1->BASE_STAT & 1;
|
||||
|
||||
case CGU_BASE_APB1:
|
||||
return (LPC_CCU1->BASE_STAT>>1) & 1;
|
||||
|
||||
case CGU_BASE_SPIFI:
|
||||
return (LPC_CCU1->BASE_STAT>>2) & 1;
|
||||
|
||||
case CGU_BASE_M3:
|
||||
return (LPC_CCU1->BASE_STAT>>3) & 1;
|
||||
|
||||
case CGU_BASE_USB0:
|
||||
return (LPC_CCU1->BASE_STAT>>7) & 1;
|
||||
|
||||
case CGU_BASE_USB1:
|
||||
return (LPC_CCU1->BASE_STAT>>8) & 1;
|
||||
|
||||
/*CCU2*/
|
||||
case CGU_BASE_UART3:
|
||||
return (LPC_CCU2->BASE_STAT>>1) & 1;
|
||||
|
||||
case CGU_BASE_UART2:
|
||||
return (LPC_CCU2->BASE_STAT>>2) & 1;
|
||||
|
||||
case CGU_BASE_UART1:
|
||||
return (LPC_CCU2->BASE_STAT>>3) & 1;
|
||||
|
||||
case CGU_BASE_UART0:
|
||||
return (LPC_CCU2->BASE_STAT>>4) & 1;
|
||||
|
||||
case CGU_BASE_SSP1:
|
||||
return (LPC_CCU2->BASE_STAT>>5) & 1;
|
||||
|
||||
case CGU_BASE_SSP0:
|
||||
return (LPC_CCU2->BASE_STAT>>6) & 1;
|
||||
|
||||
case CGU_BASE_SDIO:
|
||||
return (LPC_CCU2->BASE_STAT>>7) & 1;
|
||||
|
||||
/*BASE SAFE is used by WWDT and RGU*/
|
||||
case CGU_BASE_SAFE:
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Compare one source clock to IRC clock
|
||||
* @param[in] Clock Clock entity that will be compared to IRC, should be:
|
||||
* - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
|
||||
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
|
||||
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
|
||||
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
|
||||
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
|
||||
* - CGU_CLKSRC_PLL0 :PLL0 clock
|
||||
* - CGU_CLKSRC_PLL1 :PLL1 clock
|
||||
* - CGU_CLKSRC_IDIVA :Integer divider register A
|
||||
* - CGU_CLKSRC_IDIVB :Integer divider register B
|
||||
* - CGU_CLKSRC_IDIVC :Integer divider register C
|
||||
* - CGU_CLKSRC_IDIVD :Integer divider register D
|
||||
* - CGU_CLKSRC_IDIVE :Integer divider register E
|
||||
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
|
||||
* - CGU_BASE_USB0 :Base clock for USB0
|
||||
* - CGU_BASE_USB1 :Base clock for USB1
|
||||
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
|
||||
* and APB peripheral blocks #0 and #2
|
||||
* - CGU_BASE_SPIFI :Base clock for SPIFI
|
||||
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
|
||||
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
|
||||
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
|
||||
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
|
||||
* - CGU_BASE_LCD :Base clock for LCD
|
||||
* - CGU_BASE_SDIO :Base clock for SDIO card reader
|
||||
* - CGU_BASE_SSP0 :Base clock for SSP0
|
||||
* - CGU_BASE_SSP1 :Base clock for SSP1
|
||||
* - CGU_BASE_UART0 :Base clock for UART0
|
||||
* - CGU_BASE_UART1 :Base clock for UART1
|
||||
* - CGU_BASE_UART2 :Base clock for UART2
|
||||
* - CGU_BASE_UART3 :Base clock for UART3
|
||||
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
|
||||
* @param[in] m Multiple value pointer
|
||||
* @param[in] d Divider value pointer
|
||||
* @return Compare status, could be:
|
||||
* - (-1): fail
|
||||
* - 0: successful
|
||||
* @note Formula used to compare:
|
||||
* FClock = F_IRC* m / d
|
||||
**********************************************************************/
|
||||
int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d){
|
||||
uint32_t n,c,temp;
|
||||
int i;
|
||||
|
||||
/* Maximum allow RCOUNT number */
|
||||
c= 511;
|
||||
/* Check Source Clock Freq is larger or smaller */
|
||||
LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;
|
||||
while(LPC_CGU->FREQ_MON & (1 <<23));
|
||||
for(i=0;i<10000;i++);
|
||||
temp = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;
|
||||
|
||||
if(temp == 0) /* too low F < 12000000/511*/
|
||||
return -1;
|
||||
if(temp > 511){ /* larger */
|
||||
|
||||
c = 511 - (LPC_CGU->FREQ_MON&0x1FF);
|
||||
}else{
|
||||
do{
|
||||
c--;
|
||||
LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;
|
||||
while(LPC_CGU->FREQ_MON & (1 <<23));
|
||||
for(i=0;i<10000;i++);
|
||||
n = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;
|
||||
}while(n==temp);
|
||||
c++;
|
||||
}
|
||||
*m = temp;
|
||||
*d = c;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Compare one source clock to another source clock
|
||||
* @param[in] Clock Clock entity that will be compared to second source, should be:
|
||||
* - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
|
||||
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
|
||||
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
|
||||
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
|
||||
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
|
||||
* - CGU_CLKSRC_PLL0 :PLL0 clock
|
||||
* - CGU_CLKSRC_PLL1 :PLL1 clock
|
||||
* - CGU_CLKSRC_IDIVA :Integer divider register A
|
||||
* - CGU_CLKSRC_IDIVB :Integer divider register B
|
||||
* - CGU_CLKSRC_IDIVC :Integer divider register C
|
||||
* - CGU_CLKSRC_IDIVD :Integer divider register D
|
||||
* - CGU_CLKSRC_IDIVE :Integer divider register E
|
||||
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
|
||||
* - CGU_BASE_USB0 :Base clock for USB0
|
||||
* - CGU_BASE_USB1 :Base clock for USB1
|
||||
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
|
||||
* and APB peripheral blocks #0 and #2
|
||||
* - CGU_BASE_SPIFI :Base clock for SPIFI
|
||||
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
|
||||
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
|
||||
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
|
||||
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
|
||||
* - CGU_BASE_LCD :Base clock for LCD
|
||||
* - CGU_BASE_SDIO :Base clock for SDIO card reader
|
||||
* - CGU_BASE_SSP0 :Base clock for SSP0
|
||||
* - CGU_BASE_SSP1 :Base clock for SSP1
|
||||
* - CGU_BASE_UART0 :Base clock for UART0
|
||||
* - CGU_BASE_UART1 :Base clock for UART1
|
||||
* - CGU_BASE_UART2 :Base clock for UART2
|
||||
* - CGU_BASE_UART3 :Base clock for UART3
|
||||
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
|
||||
* @param[in] CompareToClock Clock source that to be compared to first source, should be different
|
||||
* to first source.
|
||||
* @param[in] m Multiple value pointer
|
||||
* @param[in] d Divider value pointer
|
||||
* @return Compare status, could be:
|
||||
* - (-1): fail
|
||||
* - 0: successful
|
||||
* @note Formula used to compare:
|
||||
* FClock = m*FCompareToClock/d
|
||||
**********************************************************************/
|
||||
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d){
|
||||
uint32_t m1,m2,d1,d2;
|
||||
/* Check Parameter */
|
||||
if((Clock>CGU_CLKSRC_IDIVE) || (CompareToClock>CGU_CLKSRC_IDIVE))
|
||||
return CGU_ERROR_INVALID_PARAM;
|
||||
/* Check for Clock Enable - Not yet implement
|
||||
* The Comparator will hang if Clock has not been set*/
|
||||
CGU_FrequencyMonitor(Clock, &m1, &d1);
|
||||
CGU_FrequencyMonitor(CompareToClock, &m2, &d2);
|
||||
*m= m1*d2;
|
||||
*d= d1*m2;
|
||||
return 0;
|
||||
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,271 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_cgu.h 2011-06-02
|
||||
*//**
|
||||
* @file llpc43xx_cgu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Clock Generation and Clock Control firmware
|
||||
* library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CGU CGU (Clock Generation Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_CGU_H_
|
||||
#define lpc43xx_CGU_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "lpc43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private Macros -------------------------------------------------------------- */
|
||||
/** @defgroup CGU_Private_Macros CGU Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Branch clocks from CGU_BASE_SAFE */
|
||||
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
|
||||
|
||||
/** Check bit at specific position is clear or not */
|
||||
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
|
||||
/** Check bit at specific position is set or not */
|
||||
#define ISBITSET(x,bit) (x&(1<<bit))
|
||||
/** Set mask */
|
||||
#define ISMASKSET(x,mask) (x&mask)
|
||||
|
||||
/** CGU number of clock source */
|
||||
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CGU control mask bit definitions
|
||||
**********************************************************************/
|
||||
/** CGU control enable mask bit */
|
||||
#define CGU_CTRL_EN_MASK 1
|
||||
/** CGU control clock-source mask bit */
|
||||
#define CGU_CTRL_SRC_MASK (0xF<<24)
|
||||
/** CGU control auto block mask bit */
|
||||
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CGU PLL1 mask bit definitions
|
||||
**********************************************************************/
|
||||
/** CGU PLL1 feedback select mask bit */
|
||||
#define CGU_PLL1_FBSEL_MASK (1<<6)
|
||||
/** CGU PLL1 Input clock bypass control mask bit */
|
||||
#define CGU_PLL1_BYPASS_MASK (1<<1)
|
||||
/** CGU PLL1 direct CCO output mask bit */
|
||||
#define CGU_PLL1_DIRECT_MASK (1<<7)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup CGU_Public_Types CGU Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief CGU enumeration
|
||||
**********************************************************************/
|
||||
/*
|
||||
* @brief CGU clock source enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
/* Clock Source */
|
||||
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
|
||||
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
|
||||
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
|
||||
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
|
||||
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
|
||||
CGU_CLKSRC_TCK, /**< TCK clock source */
|
||||
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
|
||||
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
|
||||
CGU_CLKSRC_PLL0_AUDIO,
|
||||
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
|
||||
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
|
||||
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
|
||||
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
|
||||
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
|
||||
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
|
||||
|
||||
/* Base */
|
||||
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
|
||||
CGU_BASE_USB0, /**< USB0 base clock */
|
||||
CGU_BASE_USB1 = CGU_BASE_USB0 + 2, /**< USB1 base clock */
|
||||
CGU_BASE_M3, /**< ARM Cortex-M3 Core base clock */
|
||||
CGU_BASE_SPIFI, /**< SPIFI base clock */
|
||||
//CGU_BASE_SPI,
|
||||
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
|
||||
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
|
||||
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
|
||||
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
|
||||
CGU_BASE_LCD, /**< LCD base clock */
|
||||
CGU_BASE_ENET_CSR,
|
||||
CGU_BASE_SDIO, /**< SDIO base clock */
|
||||
CGU_BASE_SSP0, /**< SSP0 base clock */
|
||||
CGU_BASE_SSP1, /**< SSP1 base clock */
|
||||
CGU_BASE_UART0, /**< UART0 base clock */
|
||||
CGU_BASE_UART1, /**< UART1 base clock */
|
||||
CGU_BASE_UART2, /**< UART2 base clock */
|
||||
CGU_BASE_UART3, /**< UART3 base clock */
|
||||
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
|
||||
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
|
||||
CGU_BASE_OUT0,
|
||||
CGU_BASE_OUT1,
|
||||
CGU_ENTITY_NUM /**< Number or clock source entity */
|
||||
} CGU_ENTITY_T;
|
||||
|
||||
/*
|
||||
* @brief CGU PPL0 mode enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_PLL0_MODE_1d = 0,
|
||||
CGU_PLL0_MODE_1c,
|
||||
CGU_PLL0_MODE_1b,
|
||||
CGU_PLL0_MODE_1a
|
||||
}CGU_PLL0_MODE;
|
||||
|
||||
/*
|
||||
* @brief CGU peripheral enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
|
||||
CGU_PERIPHERAL_ADC1, /**< ADC1 */
|
||||
CGU_PERIPHERAL_AES, /**< AES */
|
||||
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
|
||||
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
|
||||
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
|
||||
CGU_PERIPHERAL_CAN, /**< CAN */
|
||||
CGU_PERIPHERAL_CREG, /**< CREG */
|
||||
CGU_PERIPHERAL_DAC, /**< DAC */
|
||||
CGU_PERIPHERAL_DMA, /**< DMA */
|
||||
CGU_PERIPHERAL_EMC, /**< EMC */
|
||||
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
|
||||
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
|
||||
CGU_PERIPHERAL_GPIO, /**< GPIO */
|
||||
CGU_PERIPHERAL_I2C0, /**< I2C0 */
|
||||
CGU_PERIPHERAL_I2C1, /**< I2C1 */
|
||||
CGU_PERIPHERAL_I2S, /**< I2S */
|
||||
CGU_PERIPHERAL_LCD, /**< LCD */
|
||||
CGU_PERIPHERAL_M3CORE, /**< ARM Cortex-M3 Core */
|
||||
CGU_PERIPHERAL_M3_BUS, /**< ARM Cortex-M3 Bus */
|
||||
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
|
||||
CGU_PERIPHERAL_QEI, /**< QEI */
|
||||
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
|
||||
CGU_PERIPHERAL_SCT, /**< SCT */
|
||||
CGU_PERIPHERAL_SCU, /**< SCU */
|
||||
CGU_PERIPHERAL_SDIO, /**< SDIO */
|
||||
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
|
||||
CGU_PERIPHERAL_SSP0, /**< SSP0 */
|
||||
CGU_PERIPHERAL_SSP1, /**< SSP1 */
|
||||
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
|
||||
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
|
||||
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
|
||||
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
|
||||
CGU_PERIPHERAL_UART0, /**< UART0 */
|
||||
CGU_PERIPHERAL_UART1, /**< UART1 */
|
||||
CGU_PERIPHERAL_UART2, /**< UART2 */
|
||||
CGU_PERIPHERAL_UART3, /**< UART3 */
|
||||
CGU_PERIPHERAL_USB0, /**< USB0 */
|
||||
CGU_PERIPHERAL_USB1, /**< USB1 */
|
||||
CGU_PERIPHERAL_WWDT, /**< WWDT */
|
||||
CGU_PERIPHERAL_NUM
|
||||
} CGU_PERIPHERAL_T;
|
||||
|
||||
/**
|
||||
* @brief CGU error status enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_ERROR_SUCCESS = 0,
|
||||
CGU_ERROR_CONNECT_TOGETHER,
|
||||
CGU_ERROR_INVALID_ENTITY,
|
||||
CGU_ERROR_INVALID_CLOCK_SOURCE,
|
||||
CGU_ERROR_INVALID_PARAM,
|
||||
CGU_ERROR_FREQ_OUTOF_RANGE
|
||||
} CGU_ERROR;
|
||||
|
||||
/********************************************************************//**
|
||||
* @brief CGU structure definitions
|
||||
**********************************************************************/
|
||||
/*
|
||||
* @brief CGU peripheral clock structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t RegBaseEntity; /**< Base register address */
|
||||
uint16_t RegBranchOffset; /**< Branch register offset */
|
||||
uint8_t PerBaseEntity; /**< Base peripheral address */
|
||||
uint16_t PerBranchOffset; /**< Base peripheral offset */
|
||||
uint8_t next; /**< Pointer to next structure */
|
||||
} CGU_PERIPHERAL_S;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CGU_Public_Functions CGU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Clock generate initialize/de-initialize */
|
||||
uint32_t CGU_Init(void);
|
||||
uint32_t CGU_DeInit(void);
|
||||
|
||||
/** Clock Generator and Clock Control */
|
||||
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
|
||||
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
|
||||
|
||||
/** Clock Source and Base Clock operation */
|
||||
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
|
||||
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
|
||||
uint32_t CGU_SetPLL0(void);
|
||||
uint32_t CGU_SetPLL1(uint32_t mult);
|
||||
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
|
||||
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
|
||||
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
|
||||
void CGU_UpdateClock(void);
|
||||
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_CGU_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,383 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_i2c.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_i2c.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for I2C firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup I2C I2C (Inter-Integrated Circuit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_I2C_H_
|
||||
#define lpc43xx_I2C_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "lpc43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*******************************************************************//**
|
||||
* I2C Control Set register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
|
||||
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
|
||||
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
|
||||
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
|
||||
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
|
||||
|
||||
/*******************************************************************//**
|
||||
* I2C Control Clear register description
|
||||
*********************************************************************/
|
||||
/** Assert acknowledge Clear bit */
|
||||
#define I2C_I2CONCLR_AAC ((1<<2))
|
||||
/** I2C interrupt Clear bit */
|
||||
#define I2C_I2CONCLR_SIC ((1<<3))
|
||||
/** START flag Clear bit */
|
||||
#define I2C_I2CONCLR_STAC ((1<<5))
|
||||
/** I2C interface Disable bit */
|
||||
#define I2C_I2CONCLR_I2ENC ((1<<6))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Status Code definition (I2C Status register)
|
||||
*********************************************************************/
|
||||
/* Return Code in I2C status register */
|
||||
#define I2C_STAT_CODE_BITMASK ((0xF8))
|
||||
|
||||
/* I2C return status code definitions ----------------------------- */
|
||||
|
||||
/** No relevant information */
|
||||
#define I2C_I2STAT_NO_INF ((0xF8))
|
||||
|
||||
/* Master transmit mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_START ((0x08))
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_RESTART ((0x10))
|
||||
/** SLA+W has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
|
||||
/** SLA+W has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
|
||||
/** Arbitration lost in SLA+R/W or Data bytes */
|
||||
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
|
||||
|
||||
/* Master receive mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_START ((0x08))
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_RESTART ((0x10))
|
||||
/** Arbitration lost */
|
||||
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
|
||||
/** SLA+R has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
|
||||
/** SLA+R has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
|
||||
/** Data has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
|
||||
/** Data has been received, NACK has been return */
|
||||
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
|
||||
|
||||
/* Slave receive mode -------------------------------------------- */
|
||||
/** Own slave address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
|
||||
/** Own SLA+W has been received, ACK returned */
|
||||
//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
|
||||
|
||||
/** General call address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
|
||||
|
||||
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
|
||||
/** General call address has been received, ACK has been returned */
|
||||
//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
|
||||
|
||||
/** Previously addressed with own SLV address;
|
||||
* Data has been received, ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
|
||||
/** Previously addressed with own SLA;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
|
||||
/** A STOP condition or repeated START condition has
|
||||
* been received while still addressed as SLV/REC
|
||||
* (Slave Receive) or SLV/TRX (Slave Transmit) */
|
||||
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
|
||||
|
||||
/** Slave transmit mode */
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
|
||||
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
|
||||
/** Last data byte in I2DAT has been transmitted (AA = 0);
|
||||
ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
|
||||
|
||||
/** Time out in case of using I2C slave mode */
|
||||
#define I2C_SLAVE_TIME_OUT 0x10000UL
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data register definition
|
||||
*********************************************************************/
|
||||
/** Mask for I2DAT register*/
|
||||
#define I2C_I2DAT_BITMASK ((0xFF))
|
||||
|
||||
/** Idle data value will be send out in slave mode in case of the actual
|
||||
* expecting data requested from the master is greater than its sending data
|
||||
* length that can be supported */
|
||||
#define I2C_I2DAT_IDLE_CHAR (0xFF)
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Monitor mode control register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
|
||||
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
|
||||
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
|
||||
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data buffer register description
|
||||
*********************************************************************/
|
||||
/** I2C Data buffer register bit mask */
|
||||
#define I2DATA_BUFFER_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Slave Address registers definition
|
||||
*********************************************************************/
|
||||
/** General Call enable bit */
|
||||
#define I2C_I2ADR_GC ((1<<0))
|
||||
/** I2C Slave Address registers bit mask */
|
||||
#define I2C_I2ADR_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Mask Register definition
|
||||
*********************************************************************/
|
||||
/** I2C Mask Register mask field */
|
||||
#define I2C_I2MASK_MASK(n) ((n&0xFE))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL HIGH duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL HIGH duty cycle Register bit mask */
|
||||
#define I2C_I2SCLH_BITMASK ((0xFFFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL LOW duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL LOW duty cycle Register bit mask */
|
||||
#define I2C_I2SCLL_BITMASK ((0xFFFF))
|
||||
|
||||
/* I2C status values */
|
||||
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
|
||||
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
|
||||
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
|
||||
|
||||
/*********************************************************************//**
|
||||
* I2C monitor control configuration defines
|
||||
**********************************************************************/
|
||||
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
|
||||
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
|
||||
|
||||
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
|
||||
/* Macros check I2C slave address */
|
||||
#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
|
||||
|
||||
/** Macro to determine if it is valid SSP port number */
|
||||
#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
|
||||
|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
|
||||
|
||||
/* Macros check I2C monitor configuration type */
|
||||
#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Types I2C Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Own slave address setting structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
|
||||
should be in range from 0..3
|
||||
*/
|
||||
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
|
||||
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
|
||||
when I2C control being in Slave mode, should be:
|
||||
- ENABLE: Enable General Call function.
|
||||
- DISABLE: Disable General Call function.
|
||||
*/
|
||||
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
|
||||
which is set to '1' will cause an automatic compare on
|
||||
the corresponding bit of the received address when it
|
||||
is compared to the SlaveAddr_7bit value associated with this
|
||||
mask register. In other words, bits in SlaveAddr_7bit value
|
||||
which are masked are not taken into account in determining
|
||||
an address match
|
||||
*/
|
||||
} I2C_OWNSLAVEADDR_CFG_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Master transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
|
||||
uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
|
||||
is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
|
||||
is not used*/
|
||||
uint32_t tx_count; /**< Current Transmit data counter */
|
||||
uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
|
||||
is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is
|
||||
not used */
|
||||
uint32_t rx_count; /**< Current Receive data counter */
|
||||
uint32_t retransmissions_max; /**< Max Re-Transmission value */
|
||||
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
|
||||
uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to Call back function when transmission complete
|
||||
used in interrupt transfer mode */
|
||||
} I2C_M_SETUP_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Slave transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */
|
||||
uint32_t tx_count; /**< Current transmit data counter */
|
||||
uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */
|
||||
uint32_t rx_count; /**< Current receive data counter */
|
||||
uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to call-back function when transmission complete
|
||||
used by interrupt transfer mode */
|
||||
} I2C_S_SETUP_Type;
|
||||
|
||||
/**
|
||||
* @brief Transfer option type definitions
|
||||
*/
|
||||
typedef enum {
|
||||
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
|
||||
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
|
||||
} I2C_TRANSFER_OPT_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Functions I2C Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I2C Init/DeInit functions ---------- */
|
||||
void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
|
||||
void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
|
||||
//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
|
||||
void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* I2C transfer data functions -------- */
|
||||
Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
|
||||
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
|
||||
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
|
||||
uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
|
||||
|
||||
|
||||
void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
|
||||
uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
|
||||
|
||||
/* I2C Monitor functions ---------------*/
|
||||
void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
|
||||
void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
|
||||
BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
|
||||
|
||||
/* I2C Interrupt handler functions ------*/
|
||||
void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
|
||||
void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
|
||||
void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_I2C_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,186 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_libcfg_default.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_libcfg_default.h
|
||||
* @brief Default Library configuration header file
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Library Configuration group ----------------------------------------------------------- */
|
||||
/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_LIBCFG_DEFAULT_H_
|
||||
#define lpc43xx_LIBCFG_DEFAULT_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************** DEBUG MODE DEFINITIONS *********************************/
|
||||
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
|
||||
the "CHECK_PARAM" macro in the FW library code */
|
||||
|
||||
//#define DEBUG
|
||||
|
||||
|
||||
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
|
||||
|
||||
/* Comment the line below to disable the specific peripheral inclusion */
|
||||
|
||||
/* GPIO ------------------------------- */
|
||||
#define _GPIO
|
||||
|
||||
/* EXTI ------------------------------- */
|
||||
#define _EXTI
|
||||
|
||||
/* UART ------------------------------- */
|
||||
#define _UART
|
||||
#define _UART0
|
||||
#define _UART1
|
||||
#define _UART2
|
||||
#define _UART3
|
||||
|
||||
/* SPI ------------------------------- */
|
||||
#define _SPI
|
||||
|
||||
/* SYSTICK --------------------------- */
|
||||
#define _SYSTICK
|
||||
|
||||
/* SSP ------------------------------- */
|
||||
#define _SSP
|
||||
#define _SSP0
|
||||
#define _SSP1
|
||||
|
||||
|
||||
/* I2C ------------------------------- */
|
||||
#define _I2C
|
||||
#define _I2C0
|
||||
#define _I2C1
|
||||
#define _I2C2
|
||||
|
||||
/* TIMER ------------------------------- */
|
||||
#define _TIM
|
||||
|
||||
/* WWDT ------------------------------- */
|
||||
#define _WWDT
|
||||
|
||||
|
||||
/* GPDMA ------------------------------- */
|
||||
#define _GPDMA
|
||||
|
||||
|
||||
/* DAC ------------------------------- */
|
||||
#define _DAC
|
||||
|
||||
/* DAC ------------------------------- */
|
||||
#define _ADC
|
||||
|
||||
|
||||
/* PWM ------------------------------- */
|
||||
#define _PWM
|
||||
#define _PWM1
|
||||
|
||||
/* RTC ------------------------------- */
|
||||
#define _RTC
|
||||
|
||||
/* I2S ------------------------------- */
|
||||
#define _I2S
|
||||
|
||||
/* USB device ------------------------------- */
|
||||
#define _USBDEV
|
||||
#define _USB_DMA
|
||||
|
||||
/* QEI ------------------------------- */
|
||||
#define _QEI
|
||||
|
||||
/* MCPWM ------------------------------- */
|
||||
#define _MCPWM
|
||||
|
||||
/* CAN--------------------------------*/
|
||||
#define _C_CAN
|
||||
|
||||
/* RIT ------------------------------- */
|
||||
#define _RIT
|
||||
|
||||
/* EMAC ------------------------------ */
|
||||
#define _EMAC
|
||||
|
||||
/* SCT ------------------------------ */
|
||||
#define _SCT
|
||||
|
||||
/* LCD ------------------------------ */
|
||||
#define _LCD
|
||||
|
||||
/* ATIMER ------------------------------ */
|
||||
#define _ATIMER
|
||||
|
||||
/* RGU ------------------------------ */
|
||||
#define _RGU
|
||||
|
||||
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
|
||||
|
||||
#ifdef DEBUG
|
||||
/*******************************************************************************
|
||||
* @brief The CHECK_PARAM macro is used for function's parameters check.
|
||||
* It is used only if the library is compiled in DEBUG mode.
|
||||
* @param[in] expr - If expr is false, it calls check_failed() function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* - If expr is true, it returns no value.
|
||||
* @return None
|
||||
*******************************************************************************/
|
||||
#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
|
||||
#else
|
||||
#define CHECK_PARAM(expr)
|
||||
#endif /* DEBUG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef DEBUG
|
||||
void check_failed(uint8_t *file, uint32_t line);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* lpc43xx_LIBCFG_DEFAULT_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,98 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_scu.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_scu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for SCU firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SCU SCU (System Control Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __SCU_H
|
||||
#define __SCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup SCT_Private_Macros SCT Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Port offset definition */
|
||||
#define PORT_OFFSET 0x80
|
||||
/** Pin offset definition */
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin modes */
|
||||
#define MD_PUP (0x0<<3)
|
||||
#define MD_BUK (0x1<<3)
|
||||
#define MD_PLN (0x2<<3)
|
||||
#define MD_PDN (0x3<<3)
|
||||
#define MD_EHS (0x1<<5)
|
||||
#define MD_EZI (0x1<<6)
|
||||
#define MD_ZI (0x1<<7)
|
||||
#define MD_EHD0 (0x1<<8)
|
||||
#define MD_EHD1 (0x1<<8)
|
||||
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
|
||||
// 0xF0
|
||||
|
||||
/* Pin function */
|
||||
#define FUNC0 0x0 /** Function 0 */
|
||||
#define FUNC1 0x1 /** Function 1 */
|
||||
#define FUNC2 0x2 /** Function 2 */
|
||||
#define FUNC3 0x3 /** Function 3 */
|
||||
#define FUNC4 0x4
|
||||
#define FUNC5 0x5
|
||||
#define FUNC6 0x6
|
||||
#define FUNC7 0x7
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SCU_Public_Functions SCU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end __SCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,211 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_types.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_types.h
|
||||
* @brief Contains the NXP ABL typedefs for C standard types.
|
||||
* It is intended to be used in ISO C conforming development
|
||||
* environments and checks for this insofar as it is possible
|
||||
* to do so.
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
/* Type group ----------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types LPC_Types
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC_TYPES_H
|
||||
#define LPC_TYPES_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Boolean Type definition
|
||||
*/
|
||||
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
|
||||
|
||||
/**
|
||||
* @brief Flag Status and Interrupt Flag Status type definition
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
|
||||
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
|
||||
|
||||
/**
|
||||
* @brief Functional State Definition
|
||||
*/
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
|
||||
|
||||
/**
|
||||
* @ Status type definition
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
|
||||
|
||||
|
||||
/**
|
||||
* Read/Write transfer type mode (Block or non-block)
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NONE_BLOCKING = 0, /**< None Blocking type */
|
||||
BLOCKING, /**< Blocking type */
|
||||
} TRANSFER_BLOCK_Type;
|
||||
|
||||
|
||||
/** Pointer to Function returning Void (any number of parameters) */
|
||||
typedef void (*PFV)();
|
||||
|
||||
/** Pointer to Function returning int32_t (any number of parameters) */
|
||||
typedef int32_t(*PFI)();
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* _BIT(n) sets the bit at position "n"
|
||||
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
|
||||
* e.g., "(_BIT(3) | _BIT(7))".
|
||||
*/
|
||||
#undef _BIT
|
||||
/* Set bit macro */
|
||||
#define _BIT(n) (1<<(n))
|
||||
|
||||
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
|
||||
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
|
||||
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
|
||||
*/
|
||||
#undef _SBF
|
||||
/* Set bit field macro */
|
||||
#define _SBF(f,v) ((v)<<(f))
|
||||
|
||||
/* _BITMASK constructs a symbol with 'field_width' least significant
|
||||
* bits set.
|
||||
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
|
||||
* The symbol is intended to be used to limit the bit field width
|
||||
* thusly:
|
||||
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
|
||||
* If "any_expression" results in a value that is larger than can be
|
||||
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
|
||||
* used with the _SBF example above, the example would be written:
|
||||
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
|
||||
* This ensures that the value written to a_reg is no wider than
|
||||
* 16 bits, and makes the code easier to read and understand.
|
||||
*/
|
||||
#undef _BITMASK
|
||||
/* Bitmask creation macro */
|
||||
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
|
||||
|
||||
/* NULL pointer */
|
||||
#ifndef NULL
|
||||
#define NULL ((void*) 0)
|
||||
#endif
|
||||
|
||||
/* Number of elements in an array */
|
||||
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
|
||||
|
||||
/* Static data/function define */
|
||||
#define STATIC static
|
||||
/* External data/function define */
|
||||
#define EXTERN extern
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Old Type Definition compatibility ------------------------------------------ */
|
||||
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** SMA type for character type */
|
||||
typedef char CHAR;
|
||||
|
||||
/** SMA type for 8 bit unsigned value */
|
||||
typedef uint8_t UNS_8;
|
||||
|
||||
/** SMA type for 8 bit signed value */
|
||||
typedef int8_t INT_8;
|
||||
|
||||
/** SMA type for 16 bit unsigned value */
|
||||
typedef uint16_t UNS_16;
|
||||
|
||||
/** SMA type for 16 bit signed value */
|
||||
typedef int16_t INT_16;
|
||||
|
||||
/** SMA type for 32 bit unsigned value */
|
||||
typedef uint32_t UNS_32;
|
||||
|
||||
/** SMA type for 32 bit signed value */
|
||||
typedef int32_t INT_32;
|
||||
|
||||
/** SMA type for 64 bit signed value */
|
||||
typedef int64_t INT_64;
|
||||
|
||||
/** SMA type for 64 bit unsigned value */
|
||||
typedef uint64_t UNS_64;
|
||||
|
||||
/** 32 bit boolean type */
|
||||
typedef Bool BOOL_32;
|
||||
|
||||
/** 16 bit boolean type */
|
||||
typedef Bool BOOL_16;
|
||||
|
||||
/** 8 bit boolean type */
|
||||
typedef Bool BOOL_8;
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#define INLINE __inline
|
||||
#else
|
||||
#define INLINE inline
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* LPC_TYPES_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@ -0,0 +1,140 @@
|
||||
#ifndef __PLATFORM_CHECK_H
|
||||
#define __PLATFORM_CHECK_H
|
||||
|
||||
#warning "************ PLATFORM CONFIG ************"
|
||||
|
||||
/* this is used to check the build platform */
|
||||
#if (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
#warning "*** Building for NXP VALIDATION BOARD ***"
|
||||
#elif (PLATFORM == HITEX_A2_BOARD)
|
||||
#warning "Building for HITEX LPC4350EVA-2 platform"
|
||||
#else
|
||||
#error "Platform not supported, check platform_config.h"
|
||||
#endif
|
||||
|
||||
/* this is to ensure memory ranges are defined */
|
||||
#ifndef M4_ROM_START
|
||||
#error "M4_ROM_START not defined, check platform_config.h"
|
||||
#endif
|
||||
#ifndef M4_ROM_LEN
|
||||
#error "M4_ROM_LEN not defined, check platform_config.h"
|
||||
#endif
|
||||
#ifndef M4_RAM_START
|
||||
#error "M4_RAM_START not defined, check platform_config.h"
|
||||
#endif
|
||||
#ifndef M4_RAM_LEN
|
||||
#error "M4_RAM_LEN not defined, check platform_config.h"
|
||||
#endif
|
||||
|
||||
#ifndef M0_ROM_START
|
||||
#error "M0_ROM_START not defined, check platform_config.h"
|
||||
#endif
|
||||
#ifndef M0_ROM_LEN
|
||||
#error "M0_ROM_LEN not defined, check platform_config.h"
|
||||
#endif
|
||||
#ifndef M0_RAM_START
|
||||
#error "M0_RAM_START not defined, check platform_config.h"
|
||||
#endif
|
||||
#ifndef M0_RAM_LEN
|
||||
#error "M0_RAM_LEN not defined, check platform_config.h"
|
||||
#endif
|
||||
|
||||
/* feedback for mailboxes usage */
|
||||
|
||||
/* configuration checks for M0 */
|
||||
#ifdef CORE_M4
|
||||
|
||||
#if (USE_M4_MAILBOX == YES)
|
||||
|
||||
#warning "*** M4 mailbox: YES ***"
|
||||
|
||||
#if (USE_MAILBOX_PARAMETER == YES)
|
||||
#warning "*** M4 mailbox parameter: YES ***"
|
||||
#elif (USE_MAILBOX_PARAMETER == NO)
|
||||
#warning "*** M4 mailbox parameter: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M4 mailbox parameter is required (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
#if (USE_MAILBOX_CALLBACK == YES)
|
||||
#warning "*** M4 mailbox callback: YES ***"
|
||||
#elif (USE_MAILBOX_CALLBACK == NO)
|
||||
#warning "*** M4 mailbox callback: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M4 mailbox callback is required (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
#elif (USE_M4_MAILBOX == NO)
|
||||
#warning "*** M4 mailbox: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M4 mailbox is required (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
#if (INITIALIZE_M0_IMAGE == YES)
|
||||
#warning "*** M4 should download the M0 image: YES ***"
|
||||
#elif (INITIALIZE_M0_IMAGE == NO)
|
||||
#warning "*** M4 should download the M0 image: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M4 should initialize the M0 image (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
/* check the build rules */
|
||||
#if (USE_EXT_FLASH == YES)
|
||||
#warning "*** Building with external flash support: YES ***"
|
||||
#elif (USE_EXT_FLASH == NO)
|
||||
#warning "*** Building with external flash support: NO ***"
|
||||
#endif
|
||||
|
||||
#if (USE_EXT_STATIC_MEM == YES)
|
||||
#warning "*** Building with external static memory support: YES ***"
|
||||
#elif (USE_EXT_STATIC_MEM == NO)
|
||||
#warning "*** Building with external static memory support: NO ***"
|
||||
#endif
|
||||
|
||||
#if (USE_EXT_DYNAMIC_MEM == YES)
|
||||
#warning "*** Building for external dynamic memory support: YES ***"
|
||||
#elif (USE_EXT_DYNAMIC_MEM == NO)
|
||||
#warning "*** Building for external dynamic memory support: NO ***"
|
||||
#endif
|
||||
|
||||
#endif /* CORE_M4 */
|
||||
|
||||
/* configuration checks for M0 */
|
||||
#ifdef CORE_M0
|
||||
|
||||
#if (USE_M0_MAILBOX == YES)
|
||||
|
||||
#warning "*** M0 mailbox: YES ***"
|
||||
|
||||
#if (USE_MAILBOX_PARAMETER == YES)
|
||||
#warning "*** M0 mailbox parameter: YES ***"
|
||||
#elif (USE_MAILBOX_PARAMETER == NO)
|
||||
#warning "*** M0 mailbox parameter: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M0 mailbox parameter is required (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
#if (USE_MAILBOX_CALLBACK == YES)
|
||||
#warning "*** M0 mailbox callback: YES ***"
|
||||
#elif (USE_MAILBOX_CALLBACK == NO)
|
||||
#warning "*** M0 mailbox callback: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M0 mailbox callback is required (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
#elif (USE_M0_MAILBOX == NO)
|
||||
#warning "*** M0 mailbox: NO ***"
|
||||
#else
|
||||
#error "*** Specify if M0 mailbox is required (YES/NO) ***"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /* CORE_M0 */
|
||||
|
||||
#warning "************ PLATFORM CONFIG ************"
|
||||
|
||||
#endif /* platform check */
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,81 @@
|
||||
#include "LPC43xx.h"
|
||||
#include "platform_config.h"
|
||||
|
||||
#include "scu.h"
|
||||
#include "type.h"
|
||||
#include "emc_LPC43xx.h"
|
||||
#include "fpu_init.h"
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
** Function prototypes
|
||||
**********************************************************************/
|
||||
void vIOInit(void);
|
||||
void clockInit(void);
|
||||
|
||||
|
||||
|
||||
/* this function initializes the platform with system level settings */
|
||||
void platformInit(void) {
|
||||
|
||||
SystemInit();
|
||||
|
||||
fpuInit();
|
||||
|
||||
clockInit();
|
||||
|
||||
vIOInit();
|
||||
|
||||
#if (USE_EXT_STATIC_MEM == YES) || (USE_EXT_DYNAMIC_MEM == YES)
|
||||
|
||||
EMC_Init();
|
||||
|
||||
#endif
|
||||
|
||||
#if (USE_EXT_FLASH == YES)
|
||||
|
||||
// relocate vector table to internal ram
|
||||
// updates also VTOR
|
||||
relocIrqTable();
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Initialize board specific IO
|
||||
*----------------------------------------------------------------------------*/
|
||||
void vIOInit(void)
|
||||
{
|
||||
#if (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
// P9.2 : GPIO4_14: LD11 (LED)
|
||||
scu_pinmux(0x9 ,2 , PDN_ENABLE, FUNC0);
|
||||
LPC_GPIO4->DIR |= (1UL << 14);
|
||||
#endif
|
||||
#if (PLATFORM == HITEX_A2_BOARD)
|
||||
// P9.3 : GPIO4_15
|
||||
scu_pinmux(0x9 , 3 , PDN_ENABLE, FUNC0);
|
||||
LPC_GPIO4->DIR |= (1UL << 15);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Initialize clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
void clockInit(void)
|
||||
{
|
||||
/* Set PL160M @ 10*12=120 MHz */
|
||||
SetPL160M(SRC_XTAL, 10);
|
||||
/* Run base M4 clock from PL160M, no division */
|
||||
SetClock(BASE_M4_CLK, SRC_PL160M_0, DIV1);
|
||||
/* Show base out clock on output */
|
||||
SetClock(BASE_OUT_CLK, SRC_XTAL, DIV1);
|
||||
|
||||
// clock to UART 1
|
||||
SetClock(BASE_UART1_CLK, SRC_PL160M_0, DIV1);
|
||||
|
||||
// clock to CAN1 > 15 MHz
|
||||
// SetClock(BASE_VPB1_CLK, SRC_PL160M_0, DIV8);
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,230 @@
|
||||
#ifndef __PLATFORM_CONFIG_H
|
||||
#define __PLATFORM_CONFIG_H
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
/****************************************************/
|
||||
/* supported platforms list */
|
||||
/* DO NOT CHANGE THESE DEFINITIONS */
|
||||
#define NXP_VALIDATION_BOARD (1)
|
||||
#define HITEX_A2_BOARD (3)
|
||||
/****************************************************/
|
||||
|
||||
/****************************************************/
|
||||
/* used for the configuration checks */
|
||||
/* DO NOT CHANGE THESE DEFINITIONS */
|
||||
/****************************************************/
|
||||
#define YES (1)
|
||||
#define NO (2)
|
||||
|
||||
/****************************************************/
|
||||
/* USER CONFIGURATION SECTION */
|
||||
/****************************************************/
|
||||
|
||||
/* choose the platform you want to build against */
|
||||
// #define PLATFORM NXP_VALIDATION_BOARD
|
||||
#define PLATFORM HITEX_A2_BOARD
|
||||
|
||||
/* these definitions are being taken from the build rule */
|
||||
#ifdef EXT_FLASH
|
||||
#define USE_EXT_FLASH (YES)
|
||||
#else
|
||||
#define USE_EXT_FLASH (NO)
|
||||
#endif
|
||||
|
||||
#ifdef EXT_STAT_MEM
|
||||
#define USE_EXT_STATIC_MEM (YES)
|
||||
#else
|
||||
#define USE_EXT_STATIC_MEM (NO)
|
||||
#endif
|
||||
|
||||
#ifdef EXT_DYN_MEM
|
||||
#define USE_EXT_DYNAMIC_MEM (YES)
|
||||
#else
|
||||
#define USE_EXT_DYNAMIC_MEM (NO)
|
||||
#endif
|
||||
|
||||
/* define if the M4 should download and start the M0 application */
|
||||
/* set to YES if M4 should initialize M0 application */
|
||||
/* set to NO if the debugger is downloading the M0 image, used for */
|
||||
/* dual core debugging sessions */
|
||||
#define INITIALIZE_M0_IMAGE (NO)
|
||||
|
||||
/* specify if need to prefill the M0 memory before download */
|
||||
#define FILL_ROM_BEFORE_DOWNLOAD (NO)
|
||||
#define FILL_RAM_BEFORE_DOWNLOAD (NO)
|
||||
|
||||
/* define if the M4 provides a mailbox system to the M0 */
|
||||
/* M0 ---> M4 */
|
||||
#define USE_M4_MAILBOX (NO)
|
||||
/* configure which priority the mailbox interrupt should have on the M4 side */
|
||||
/* cmsis definition, priority from 0 to 7 */
|
||||
#define M4_MAILBOX_PRIORITY (0)
|
||||
|
||||
/* define if the M0 provides a mailbox system to the M4 */
|
||||
/* M4 ---> M0 */
|
||||
#define USE_M0_MAILBOX (NO)
|
||||
/* configure which priority the mailbox interrupt should have on the M0 side */
|
||||
/* cmsis definition, priority from 0 to 3 */
|
||||
#define M0_MAILBOX_PRIORITY (0)
|
||||
|
||||
|
||||
/* define if the system needs to exchange a parameter */
|
||||
#define USE_MAILBOX_PARAMETER (NO)
|
||||
|
||||
/* define if the system needs to hook a callback, or just notify */
|
||||
#define USE_MAILBOX_CALLBACK (NO)
|
||||
|
||||
|
||||
/* memory map for the application */
|
||||
/* !!! needs to be consistent with the scatter file !!! */
|
||||
#ifdef EXT_FLASH
|
||||
|
||||
/************************************/
|
||||
/* this is for the FLASH version */
|
||||
/************************************/
|
||||
/* 0x1C000000 M4 ROM 4Mbytes */
|
||||
/* 0x1C3FFFFF */
|
||||
/* 0x10000000 M4 RAM 96K */
|
||||
/* 0x10017FFF */
|
||||
#define M4_ROM_START 0x1C000000
|
||||
#define M4_ROM_LEN 0x400000 /* 4 Mbytes */
|
||||
|
||||
#define M4_RAM_START 0x10000000 /* 96 Kbytes */
|
||||
#define M4_RAM_LEN 0x18000
|
||||
|
||||
/* 0x10080000 M0 ROM 32K */
|
||||
/* 0x10087FFF */
|
||||
/* 0x10088000 M0 RAM 8K */
|
||||
/* 0x10089FFF */
|
||||
#define M0_ROM_START 0x10080000
|
||||
#define M0_ROM_LEN 0x8000
|
||||
|
||||
#define M0_RAM_START 0x10088000
|
||||
#define M0_RAM_LEN 0x2000
|
||||
|
||||
/* 0x20000000 M4 BUF 16K */
|
||||
/* 0x20003FFF */
|
||||
/* 0x20004000 M0 BUF 16K */
|
||||
/* 0x20007FFF */
|
||||
#define M4_BUF_START 0x20000000
|
||||
#define M4_BUF_LEN 0x4000
|
||||
|
||||
#define M0_BUF_START 0x20004000
|
||||
#define M0_BUF_LEN 0x4000
|
||||
|
||||
/* 0x20008000 M4 MBX 8K */
|
||||
/* 0x20009FFF */
|
||||
/* 0x2000A000 M0 MBX 8K */
|
||||
/* 0x2000BFFF */
|
||||
#define M4_MBX_START 0x20008000
|
||||
#define M4_MBX_LEN 0x2000
|
||||
|
||||
#define M0_MBX_START 0x2000A000
|
||||
#define M0_MBX_LEN 0x2000
|
||||
|
||||
#else
|
||||
|
||||
/*******************************/
|
||||
/* this is for the ram version */
|
||||
/*******************************/
|
||||
/* 0x10000000 M4 ROM 64K */
|
||||
/* 0x1000FFFF */
|
||||
/* 0x10010000 M4 RAM 32K */
|
||||
/* 0x10017FFF */
|
||||
#define M4_ROM_START 0x10000000
|
||||
#define M4_ROM_LEN 0x10000
|
||||
|
||||
#define M4_RAM_START 0x10010000
|
||||
#define M4_RAM_LEN 0x8000
|
||||
|
||||
/* 0x10080000 M0 ROM 32K */
|
||||
/* 0x10087FFF */
|
||||
/* 0x10088000 M0 RAM 8K */
|
||||
/* 0x10089FFF */
|
||||
#define M0_ROM_START 0x10080000
|
||||
#define M0_ROM_LEN 0x8000
|
||||
|
||||
#define M0_RAM_START 0x10088000
|
||||
#define M0_RAM_LEN 0x2000
|
||||
|
||||
/* 0x20000000 M4 BUF 16K */
|
||||
/* 0x20003FFF */
|
||||
/* 0x20004000 M0 BUF 16K */
|
||||
/* 0x20007FFF */
|
||||
#define M4_BUF_START 0x20000000
|
||||
#define M4_BUF_LEN 0x4000
|
||||
|
||||
#define M0_BUF_START 0x20004000
|
||||
#define M0_BUF_LEN 0x4000
|
||||
|
||||
/* 0x20008000 M4 MBX 8K */
|
||||
/* 0x20009FFF */
|
||||
/* 0x2000A000 M0 MBX 8K */
|
||||
/* 0x2000BFFF */
|
||||
#define M4_MBX_START 0x20008000
|
||||
#define M4_MBX_LEN 0x2000
|
||||
|
||||
#define M0_MBX_START 0x2000A000
|
||||
#define M0_MBX_LEN 0x2000
|
||||
|
||||
#endif /* ifdef EXT_FLASH */
|
||||
|
||||
/****************************************************/
|
||||
/* END OF USER CONFIGURATION */
|
||||
/* DO NOT EDIT BELOW THIS LINE */
|
||||
/****************************************************/
|
||||
|
||||
#define M4_IPC_TABLE M4_MBX_START
|
||||
#define M0_IPC_TABLE M0_MBX_START
|
||||
|
||||
/* configure defines for local mailbox */
|
||||
#if defined (CORE_M0) && (USE_M0_MAILBOX == YES)
|
||||
#define PROVIDE_M0_LOCAL_MBX (1)
|
||||
#endif
|
||||
|
||||
#if defined (CORE_M4) && (USE_M4_MAILBOX == YES)
|
||||
#define PROVIDE_M4_LOCAL_MBX (1)
|
||||
#endif
|
||||
|
||||
#if defined PROVIDE_M0_LOCAL_MBX || PROVIDE_M4_LOCAL_MBX
|
||||
#define LOCAL_MAILBOX_ENABLED (1)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (CORE_M0) && (USE_M4_MAILBOX == YES)
|
||||
#define PROVIDE_M0_REMOTE_MBX (1)
|
||||
#endif
|
||||
|
||||
#if defined (CORE_M4) && (USE_M0_MAILBOX == YES)
|
||||
#define PROVIDE_M4_REMOTE_MBX (1)
|
||||
#endif
|
||||
|
||||
#if defined PROVIDE_M0_REMOTE_MBX || PROVIDE_M4_REMOTE_MBX
|
||||
#define REMOTE_MAILBOX_ENABLED (1)
|
||||
#endif
|
||||
|
||||
|
||||
#if(USE_MAILBOX_PARAMETER == YES)
|
||||
#define MBX_PARAM_DEFAULT ,0x0
|
||||
#else
|
||||
#define MBX_PARAM_DEFAULT
|
||||
#endif
|
||||
|
||||
#define DUMMY_CALLBACK ,(mbxCallback_t) &dummyCallback
|
||||
|
||||
#if (USE_MAILBOX_CALLBACK == YES)
|
||||
#define MBX_CALLBACK_DEFAULT DUMMY_CALLBACK
|
||||
#else
|
||||
#define MBX_CALLBACK_DEFAULT
|
||||
#endif
|
||||
|
||||
/****************************************************/
|
||||
/* platform wise initialization functions */
|
||||
/****************************************************/
|
||||
void platformInit(void);
|
||||
|
||||
|
||||
|
||||
#endif /* __PLATFORM_CONFIG_H */
|
||||
|
||||
@ -0,0 +1,416 @@
|
||||
;/***********************************************************************
|
||||
; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
; *
|
||||
; * Project: LPC43xx CMSIS Package
|
||||
; *
|
||||
; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx
|
||||
; * Device Series.
|
||||
; *
|
||||
; * Copyright(C) 2011, NXP Semiconductor
|
||||
; * All rights reserved.
|
||||
; *
|
||||
; ***********************************************************************
|
||||
; * Software that is described herein is for illustrative purposes only
|
||||
; * which provides customers with programming information regarding the
|
||||
; * products. This software is supplied "AS IS" without any warranties.
|
||||
; * NXP Semiconductors assumes no responsibility or liability for the
|
||||
; * use of the software, conveys no license or title under any patent,
|
||||
; * copyright, or mask work right to the product. NXP Semiconductors
|
||||
; * reserves the right to make changes in the software without
|
||||
; * notification. NXP Semiconductors also make no representation or
|
||||
; * warranty that such application will be suitable for the specified
|
||||
; * use without further testing or modification.
|
||||
; **********************************************************************/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __endVectors
|
||||
|
||||
Sign_Value EQU 0x5A5A5A5A
|
||||
|
||||
; this might be meaningful only for images which require a header
|
||||
; IF :DEF:EXT_FLASH
|
||||
;
|
||||
;Signature_Size EQU 0x10
|
||||
; DCD 0x000200DA
|
||||
; DCD 0x00000000
|
||||
; DCD 0x00000000
|
||||
; DCD 0x00000000
|
||||
; SPACE Signature_Size
|
||||
; DCD __initial_sp
|
||||
; DCD Reset_Handler ; 1 Reset Handler
|
||||
; FILL 256 - 8 - 16
|
||||
; ENDIF
|
||||
|
||||
|
||||
__Vectors DCD __initial_sp ; 0 Top of Stack
|
||||
DCD Reset_Handler ; 1 Reset Handler
|
||||
DCD NMI_Handler ; 2 NMI Handler
|
||||
DCD HardFault_Handler ; 3 Hard Fault Handler
|
||||
DCD MemManage_Handler ; 4 MPU Fault Handler
|
||||
DCD BusFault_Handler ; 5 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; 6 Usage Fault Handler
|
||||
DCD Sign_Value ; 7 Reserved
|
||||
DCD 0 ; 8 Reserved
|
||||
DCD 0 ; 9 Reserved
|
||||
DCD 0 ; 10 Reserved
|
||||
DCD SVC_Handler ; 11 SVCall Handler
|
||||
DCD DebugMon_Handler ; 12 Debug Monitor Handler
|
||||
DCD 0 ; 13 Reserved
|
||||
DCD PendSV_Handler ; 14 PendSV Handler
|
||||
DCD SysTick_Handler ; 15 SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DAC_IRQHandler ; 16 D/A Converter
|
||||
DCD M0_IRQHandler ; 17 M0
|
||||
DCD DMA_IRQHandler ; 18 General Purpose DMA
|
||||
DCD 0 ; 19 Reserved
|
||||
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
|
||||
DCD ETH_IRQHandler ; 21 Ethernet
|
||||
DCD SDIO_IRQHandler ; 22 SD/MMC
|
||||
DCD LCD_IRQHandler ; 23 LCD
|
||||
DCD USB0_IRQHandler ; 24 USB0
|
||||
DCD USB1_IRQHandler ; 25 USB1
|
||||
DCD SCT_IRQHandler ; 26 State Configurable Timer
|
||||
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
|
||||
DCD TIMER0_IRQHandler ; 28 Timer0
|
||||
DCD TIMER1_IRQHandler ; 29 Timer1
|
||||
DCD TIMER2_IRQHandler ; 30 Timer2
|
||||
DCD TIMER3_IRQHandler ; 31 Timer3
|
||||
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
|
||||
DCD ADC0_IRQHandler ; 33 A/D Converter 0
|
||||
DCD I2C0_IRQHandler ; 34 I2C0
|
||||
DCD I2C1_IRQHandler ; 35 I2C1
|
||||
DCD SPI_IRQHandler ; 36 SPI
|
||||
DCD ADC1_IRQHandler ; 37 A/D Converter 1
|
||||
DCD SSP0_IRQHandler ; 38 SSP0
|
||||
DCD SSP1_IRQHandler ; 39 SSP1
|
||||
DCD UART0_IRQHandler ; 40 UART0
|
||||
DCD UART1_IRQHandler ; 41 UART1
|
||||
DCD UART2_IRQHandler ; 42 UART2
|
||||
DCD UART3_IRQHandler ; 43 UART3
|
||||
DCD I2S0_IRQHandler ; 44 I2S0
|
||||
DCD I2S1_IRQHandler ; 45 I2S1
|
||||
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
|
||||
DCD SGPIO_IRQHandler ; 47 SGPIO
|
||||
DCD GPIO0_IRQHandler ; 48 GPIO0
|
||||
DCD GPIO1_IRQHandler ; 49 GPIO1
|
||||
DCD GPIO2_IRQHandler ; 50 GPIO2
|
||||
DCD GPIO3_IRQHandler ; 51 GPIO3
|
||||
DCD GPIO4_IRQHandler ; 52 GPIO4
|
||||
DCD GPIO5_IRQHandler ; 53 GPIO5
|
||||
DCD GPIO6_IRQHandler ; 54 GPIO6
|
||||
DCD GPIO7_IRQHandler ; 55 GPIO7
|
||||
DCD GINT0_IRQHandler ; 56 GINT0
|
||||
DCD GINT1_IRQHandler ; 57 GINT1
|
||||
DCD EVRT_IRQHandler ; 58 Event Router
|
||||
DCD CAN1_IRQHandler ; 59 C_CAN1
|
||||
DCD 0 ; 60 Reserved
|
||||
DCD VADC_IRQHandler ; 61 VADC
|
||||
DCD ATIMER_IRQHandler ; 62 ATIMER
|
||||
DCD RTC_IRQHandler ; 63 RTC
|
||||
DCD 0 ; 64 Reserved
|
||||
DCD WDT_IRQHandler ; 65 WDT
|
||||
DCD 0 ; 66 Reserved
|
||||
DCD CAN0_IRQHandler ; 67 C_CAN0
|
||||
DCD QEI_IRQHandler ; 68 QEI
|
||||
|
||||
__endVectors
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
|
||||
IF :DEF:EXT_FLASH
|
||||
|
||||
; Extend the address bus, as the bootloader configured only [A13:0]
|
||||
; *(uint32_t*)(0x40086320) = 0x000000F1;
|
||||
; P6_8: A14 (function 1)
|
||||
LDR R0, =0x40086320
|
||||
LDR R1, =0x000000F1
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x4008631C) = 0x000000F1;
|
||||
; P6_7: A15 (function 1)
|
||||
LDR R0, =0x4008631C
|
||||
LDR R1, =0x000000F1
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x400866C0) = 0x000000F2;
|
||||
; PD_16: A16 (function 2)
|
||||
LDR R0, =0x400866C0
|
||||
LDR R1, =0x000000F2
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x400866BC) = 0x000000F2;
|
||||
; PD_15: A17 (function 2)
|
||||
LDR R0, =0x400866BC
|
||||
LDR R1, =0x000000F2
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086700) = 0x000000F3;
|
||||
; PE_0: A18 (function 3)
|
||||
LDR R0, =0x40086700
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086704) = 0x000000F3;
|
||||
; PE_1: A19 (function 3)
|
||||
LDR R0, =0x40086704
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086708) = 0x000000F3;
|
||||
; PE_2: A20 (function 3)
|
||||
LDR R0, =0x40086708
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x4008670C) = 0x000000F3;
|
||||
; PE_3: A21 (function 3)
|
||||
LDR R0, =0x4008670C
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086710) = 0x000000F3;
|
||||
; PE_4: A22 (function 3)
|
||||
LDR R0, =0x40086710
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
|
||||
ENDIF
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
; FreeRTOS handler
|
||||
vPortSVCHandler\
|
||||
PROC
|
||||
EXPORT vPortSVCHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
; FreeRTOS handler
|
||||
xPortPendSVHandler\
|
||||
PROC
|
||||
EXPORT xPortPendSVHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
; FreeRTOS handler
|
||||
xPortSysTickHandler\
|
||||
PROC
|
||||
EXPORT xPortSysTickHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT M0_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USB1_IRQHandler [WEAK]
|
||||
EXPORT SCT_IRQHandler [WEAK]
|
||||
EXPORT RIT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT I2S1_IRQHandler [WEAK]
|
||||
EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SGPIO_IRQHandler [WEAK]
|
||||
EXPORT GPIO0_IRQHandler [WEAK]
|
||||
EXPORT GPIO1_IRQHandler [WEAK]
|
||||
EXPORT GPIO2_IRQHandler [WEAK]
|
||||
EXPORT GPIO3_IRQHandler [WEAK]
|
||||
EXPORT GPIO4_IRQHandler [WEAK]
|
||||
EXPORT GPIO5_IRQHandler [WEAK]
|
||||
EXPORT GPIO6_IRQHandler [WEAK]
|
||||
EXPORT GPIO7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT EVRT_IRQHandler [WEAK]
|
||||
EXPORT CAN1_IRQHandler [WEAK]
|
||||
EXPORT VADC_IRQHandler [WEAK]
|
||||
EXPORT ATIMER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
|
||||
|
||||
|
||||
|
||||
DAC_IRQHandler
|
||||
M0_IRQHandler
|
||||
DMA_IRQHandler
|
||||
FLASH_EEPROM_IRQHandler
|
||||
ETH_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
LCD_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USB1_IRQHandler
|
||||
SCT_IRQHandler
|
||||
RIT_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
I2S1_IRQHandler
|
||||
SPIFI_IRQHandler
|
||||
SGPIO_IRQHandler
|
||||
GPIO0_IRQHandler
|
||||
GPIO1_IRQHandler
|
||||
GPIO2_IRQHandler
|
||||
GPIO3_IRQHandler
|
||||
GPIO4_IRQHandler
|
||||
GPIO5_IRQHandler
|
||||
GPIO6_IRQHandler
|
||||
GPIO7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
EVRT_IRQHandler
|
||||
CAN1_IRQHandler
|
||||
VADC_IRQHandler
|
||||
ATIMER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
QEI_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,59 @@
|
||||
/*****************************************************************************
|
||||
* config.h: Header file for NXP LPC43xx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2011.6.22 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
|
||||
#define IRC_TRIM_VAL 0x34A /* IRC trim value for 12MHz output */
|
||||
#define XTAL_FREQ (12000000UL) /* Frequency of external xtal */
|
||||
#define EXT_FREQ (12000000UL) /* Frequency of external clock on EXT_TCK, ENET_RX_CLK or ENET_TX_CLK */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Retarget selection
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
typedef enum {
|
||||
RETARGET_USART0 = 0,
|
||||
RETARGET_UART1 = 1,
|
||||
RETARGET_USART2 = 2,
|
||||
RETARGET_USART3 = 3
|
||||
} RETARGET_Type;
|
||||
|
||||
#define RETARGET_UART_BUFSIZE 0x40
|
||||
extern volatile uint32_t UART0Count;
|
||||
extern volatile uint8_t UART0Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern volatile uint32_t UART1Count;
|
||||
extern volatile uint8_t UART1Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern volatile uint32_t UART2Count;
|
||||
extern volatile uint8_t UART2Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern volatile uint32_t UART3Count;
|
||||
extern volatile uint8_t UART3Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern void RetargetInit(RETARGET_Type retarget, uint32_t baudrate);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Board selection
|
||||
*----------------------------------------------------------------------------*/
|
||||
//NXP LPC4300 validation board
|
||||
//#define NXP_VALIDATION_BOARD
|
||||
|
||||
//Hitex LPC4350 evaluation board
|
||||
//#define USE_HITEX_LPC4350_EVAL
|
||||
|
||||
#endif /* end __CONFIG_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@ -0,0 +1,53 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm4.c
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,844 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H__
|
||||
#define __CORE_CMFUNC_H__
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_CONTROL(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_CONTROL(uint32_t control);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_IPSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_APSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_xPSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_PSP(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_PSP(uint32_t topOfProcStack);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_MSP(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_MSP(uint32_t topOfMainStack);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_PRIMASK(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_PRIMASK(uint32_t priMask);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_BASEPRI(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_BASEPRI(uint32_t basePri);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_FAULTMASK(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_FAULTMASK(uint32_t faultMask);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & 1);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#include <intrinsics.h> /* IAR Intrinsics */
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_irq __enable_interrupt
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_irq __disable_interrupt
|
||||
|
||||
|
||||
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
static uint32_t __get_IPSR(void)
|
||||
{
|
||||
__ASM("mrs r0, ipsr");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
static uint32_t __get_APSR(void)
|
||||
{
|
||||
__ASM("mrs r0, apsr");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
static uint32_t __get_xPSR(void)
|
||||
{
|
||||
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
static uint32_t __get_PSP(void)
|
||||
{
|
||||
__ASM("mrs r0, psp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
static void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM("msr psp, r0");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
static uint32_t __get_MSP(void)
|
||||
{
|
||||
__ASM("mrs r0, msp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
static void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM("msr msp, r0");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
static __INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
static __INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
|
||||
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM("vmrs r0, fpscr");
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM("vmsr fpscr, r0");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H__ */
|
||||
@ -0,0 +1,775 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H__
|
||||
#define __CORE_CMINSTR_H__
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
extern uint32_t __REV16(uint32_t value);
|
||||
#else /* (__ARMCC_VERSION >= 400677) */
|
||||
static __INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
extern int32_t __REVSH(int32_t value);
|
||||
#else /* (__ARMCC_VERSION >= 400677) */
|
||||
static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __CLREX(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
#define __CLREX __clrex
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <intrinsics.h> /* IAR Intrinsics */
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __no_operation
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
static __INLINE void __WFI(void)
|
||||
{
|
||||
__ASM ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
static __INLINE void __WFE(void)
|
||||
{
|
||||
__ASM ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
static __INLINE void __SEV(void)
|
||||
{
|
||||
__ASM ("sev");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic void __ISB(void) (see intrinsics.h) */
|
||||
/* intrinsic void __DSB(void) (see intrinsics.h) */
|
||||
/* intrinsic void __DMB(void) (see intrinsics.h) */
|
||||
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
|
||||
/* intrinsic __SSAT (see intrinsics.h) */
|
||||
/* intrinsic __USAT (see intrinsics.h) */
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
__ASM("rev16 r0, r0");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
__ASM("rbit r0, r0");
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
static uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("ldrexb r0, [r0]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
static uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("ldrexh r0, [r0]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
|
||||
static uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("ldrex r0, [r0]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("strexb r0, r0, [r1]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("strexh r0, r0, [r1]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
|
||||
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("strex r0, r0, [r1]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
static __INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM ("clrex");
|
||||
}
|
||||
|
||||
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H__ */
|
||||
@ -0,0 +1,46 @@
|
||||
/***********************************************************************
|
||||
* $Id: dma.h 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Validation
|
||||
*
|
||||
* Description: DMA Test
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
#ifndef __DMA_H
|
||||
#define __DMA_H
|
||||
|
||||
#define DMA_SIZE 0x1000
|
||||
|
||||
#define M2M 0x00
|
||||
#define M2P 0x01
|
||||
#define P2M 0x02
|
||||
#define P2P 0x03
|
||||
|
||||
extern void DMA_IRQHandler (void);
|
||||
extern uint32_t DMA_Init_Matrix( uint32_t u32SrcAddr );
|
||||
|
||||
typedef struct _LinkedList {
|
||||
DWORD SRC;
|
||||
DWORD DST;
|
||||
DWORD LLI;
|
||||
DWORD CTRL;
|
||||
}LinkedList;
|
||||
|
||||
#endif /* end __DMA_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
****************************************************************************/
|
||||
@ -0,0 +1,421 @@
|
||||
/***********************************************************************
|
||||
* $Id: emc_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC43xx.c
|
||||
*
|
||||
* Project: NXP LPC43xx Common
|
||||
*
|
||||
* Description: Initialisation of the external memory interface and
|
||||
* configuration for the specific memories connected to
|
||||
* the LPC43xx
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "system_LPC43xx.h"
|
||||
#include "scu.h"
|
||||
#include "config.h"
|
||||
#include "platform_config.h"
|
||||
|
||||
#include "emc_LPC43xx.h"
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
** Function prototypes
|
||||
**********************************************************************/
|
||||
#define DELAY_1usFreq (1000000) // 1MHz equivalent to 1usec
|
||||
static uint32_t delayBase1us; // calculated depending on M4/EMI frequency
|
||||
static void vDelay(uint32_t u32Delay); // delay function
|
||||
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Call the required memory setup functions from here
|
||||
*
|
||||
*
|
||||
****************************************************************************************/
|
||||
void EMC_Init( void )
|
||||
{
|
||||
// The address/data pins for the memory interface are required for the static and for
|
||||
// dynamic memories
|
||||
EMC_Config_Pinmux();
|
||||
|
||||
// Initialise the control signals for static memories
|
||||
#if (USE_EXT_STATIC_MEM == YES)
|
||||
|
||||
// Initialise the control signals for static memories
|
||||
EMC_Config_Static();
|
||||
|
||||
// #if (USE_EXT_DYNAMIC_MEM == NO)
|
||||
// LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
|
||||
// LPC_EMC->CONFIG = 0;
|
||||
// // Buffers for the static memories are enabled as well. If there is SDRAM as well,
|
||||
// // then this is done after the initialisation for the dynamic memory interface.
|
||||
// LPC_EMC->STATICCONFIG0 = 0x00080081;
|
||||
// #endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (USE_EXT_DYNAMIC_MEM == YES)
|
||||
|
||||
// The setup for dynamic memories (SDRAM)
|
||||
EMC_Init_SRDRAM(SDRAM_BASE, PART_WIDTH, PART_SIZE, EXT_WIDTH, COL_ADDR_BITS);
|
||||
|
||||
#elif (USE_EXT_DYNAMIC_MEM == NO)
|
||||
|
||||
LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
|
||||
LPC_EMC->CONFIG = 0;
|
||||
|
||||
#endif
|
||||
|
||||
// Buffers for the static memories can now be enabled as well. In a system with static and dynamic memory
|
||||
// this should only been done after the SDRAM initialisation --> here
|
||||
LPC_EMC->STATICCONFIG0 = 0x00080081;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Set up the address/data pins for external memory interface in LP43xx
|
||||
*
|
||||
* Modify this function in case not all of the address/data pins are needed.
|
||||
****************************************************************************************/
|
||||
void EMC_Config_Pinmux(void)
|
||||
{
|
||||
|
||||
// Disable the external memory controller before changing pin control configuration
|
||||
LPC_EMC->CONTROL = 0x00000000;
|
||||
|
||||
// EMC_OUT (PUP_CLEAR | SLEWRATE_FAST | FILTER_DISABLE)
|
||||
// EMC_IO (PUP_CLEAR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
// Data line configuration
|
||||
scu_pinmux(0x1, 7, EMC_IO, FUNC3); // P1_7: D0
|
||||
scu_pinmux(0x1, 8, EMC_IO, FUNC3); // P1_8: D1
|
||||
scu_pinmux(0x1, 9, EMC_IO, FUNC3); // P1_9: D2
|
||||
scu_pinmux(0x1, 10, EMC_IO, FUNC3); // P1_10: D3
|
||||
scu_pinmux(0x1, 11, EMC_IO, FUNC3); // P1_11: D4
|
||||
scu_pinmux(0x1, 12, EMC_IO, FUNC3); // P1_12: D5
|
||||
scu_pinmux(0x1, 13, EMC_IO, FUNC3); // P1_13: D6
|
||||
scu_pinmux(0x1, 14, EMC_IO, FUNC3); // P1_14: D7
|
||||
scu_pinmux(0x5, 4, EMC_IO, FUNC2); // P5_4: D8
|
||||
scu_pinmux(0x5, 5, EMC_IO, FUNC2); // P5_5: D9
|
||||
scu_pinmux(0x5, 6, EMC_IO, FUNC2); // P5_6: D10
|
||||
scu_pinmux(0x5, 7, EMC_IO, FUNC2); // P5_7: D11
|
||||
scu_pinmux(0x5, 0, EMC_IO, FUNC2); // P5_0: D12
|
||||
scu_pinmux(0x5, 1, EMC_IO, FUNC2); // P5_1: D13
|
||||
scu_pinmux(0x5, 2, EMC_IO, FUNC2); // P5_2: D14
|
||||
scu_pinmux(0x5, 3, EMC_IO, FUNC2); // P5_3: D15
|
||||
scu_pinmux(0xD, 2, EMC_IO, FUNC2); // PD_2: D16
|
||||
scu_pinmux(0xD, 3, EMC_IO, FUNC2); // PD_3: D17
|
||||
scu_pinmux(0xD, 4, EMC_IO, FUNC2); // PD_4: D18
|
||||
scu_pinmux(0xD, 5, EMC_IO, FUNC2); // PD_5: D19
|
||||
scu_pinmux(0xD, 6, EMC_IO, FUNC2); // PD_6: D20
|
||||
scu_pinmux(0xD, 7, EMC_IO, FUNC2); // PD_7: D21
|
||||
scu_pinmux(0xD, 8, EMC_IO, FUNC2); // PD_8: D22
|
||||
scu_pinmux(0xD, 9, EMC_IO, FUNC2); // PD_9: D23
|
||||
scu_pinmux(0xE, 5, EMC_IO, FUNC3); // PE_5: D24
|
||||
scu_pinmux(0xE, 6, EMC_IO, FUNC3); // PE_6: D25
|
||||
scu_pinmux(0xE, 7, EMC_IO, FUNC3); // PE_7: D26
|
||||
scu_pinmux(0xE, 8, EMC_IO, FUNC3); // PE_8: D27
|
||||
scu_pinmux(0xE, 9, EMC_IO, FUNC3); // PE_9: D28
|
||||
scu_pinmux(0xE, 10, EMC_IO, FUNC3); // PE_10: D29
|
||||
scu_pinmux(0xE, 11, EMC_IO, FUNC3); // PE_11: D30
|
||||
scu_pinmux(0xE, 12, EMC_IO, FUNC3); // PE_12: D31
|
||||
|
||||
// Address line configuration
|
||||
scu_pinmux(0x2, 9, EMC_IO, FUNC3); // P2_9: A0
|
||||
scu_pinmux(0x2, 10, EMC_IO, FUNC3); // P2_10: A1
|
||||
scu_pinmux(0x2, 11, EMC_IO, FUNC3); // P2_11: A2
|
||||
scu_pinmux(0x2, 12, EMC_IO, FUNC3); // P2_12: A3
|
||||
scu_pinmux(0x2, 13, EMC_IO, FUNC3); // P2_13: A4
|
||||
scu_pinmux(0x1, 0, EMC_IO, FUNC2); // P1_0: A5
|
||||
scu_pinmux(0x1, 1, EMC_IO, FUNC2); // P1_1: A6
|
||||
scu_pinmux(0x1, 2, EMC_IO, FUNC2); // P1_2: A7
|
||||
scu_pinmux(0x2, 8, EMC_IO, FUNC3); // P2_8: A8
|
||||
scu_pinmux(0x2, 7, EMC_IO, FUNC3); // P2_7: A9
|
||||
scu_pinmux(0x2, 6, EMC_IO, FUNC2); // P2_6: A10
|
||||
scu_pinmux(0x2, 2, EMC_IO, FUNC2); // P2_2: A11
|
||||
scu_pinmux(0x2, 1, EMC_IO, FUNC2); // P2_0: A12
|
||||
scu_pinmux(0x2, 0, EMC_IO, FUNC2); // P2_0: A13
|
||||
scu_pinmux(0x6, 8, EMC_IO, FUNC1); // P6_8: A14
|
||||
scu_pinmux(0x6, 7, EMC_IO, FUNC1); // P6_7: A15
|
||||
scu_pinmux(0xD, 16, EMC_IO, FUNC2); // PD_16: A16
|
||||
scu_pinmux(0xD, 15, EMC_IO, FUNC2); // PD_15: A17
|
||||
scu_pinmux(0xE, 0, EMC_IO, FUNC3); // PE_0: A18
|
||||
scu_pinmux(0xE, 1, EMC_IO, FUNC3); // PE_1: A19
|
||||
scu_pinmux(0xE, 2, EMC_IO, FUNC3); // PE_2: A20
|
||||
scu_pinmux(0xE, 3, EMC_IO, FUNC3); // PE_3: A21
|
||||
scu_pinmux(0xE, 4, EMC_IO, FUNC3); // PE_4: A22
|
||||
|
||||
// Control signals for static memory
|
||||
scu_pinmux(0x1, 6, EMC_IO, FUNC3); // P1_6: WE
|
||||
scu_pinmux(0x1, 5, EMC_IO, FUNC3); // P1_5: CS0
|
||||
scu_pinmux(0x1, 3, EMC_IO, FUNC3); // P1_6: OE
|
||||
scu_pinmux(0x1, 4, EMC_IO, FUNC3); // P1_5: BLS0
|
||||
scu_pinmux(0x6, 6, EMC_IO, FUNC1); // P1_6: BLS1
|
||||
scu_pinmux(0xD, 12, EMC_IO, FUNC2); // PD_12: CS2
|
||||
|
||||
#if (USE_EXT_DYNAMIC_MEM == YES)
|
||||
// Control signals for dynamic memory
|
||||
scu_pinmux(0x6, 9, EMC_IO, FUNC3); // P6_9: DYCS0
|
||||
scu_pinmux(0x6, 4, EMC_IO, FUNC3); // P6_4: CAS
|
||||
scu_pinmux(0x6, 5, EMC_IO, FUNC3); // P6_5: RAS
|
||||
scu_pinmux(0x6, 11, EMC_IO, FUNC3); // P6_11: CKEOUT0
|
||||
scu_pinmux(0x6, 12, EMC_IO, FUNC3); // P6_12: DQMOUT0
|
||||
scu_pinmux(0x6, 10, EMC_IO, FUNC3); // P6_10: DQMOUT1
|
||||
|
||||
LPC_SCU_CLK(0) = 0 + EMC_IO; // EMC_CLK0 signal on pin CLK0 (needed for SDRAM)
|
||||
LPC_SCU_CLK(1) = 0 + EMC_IO;
|
||||
LPC_SCU_CLK(2) = 0 + EMC_IO;
|
||||
LPC_SCU_CLK(3) = 0 + EMC_IO;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Configure CS0 for 70ns 16-bit flash memory on the Hitex board
|
||||
* Configure CS2 for 55ns 16-bit SRAM on the Hitex board
|
||||
*
|
||||
****************************************************************************************/
|
||||
void EMC_Config_Static(void)
|
||||
{
|
||||
|
||||
// Configure CS0 for flash memory
|
||||
// @120MHz there should be 8 or 9 waitstates for the 70ns flash, apparently it works with 7
|
||||
LPC_EMC->STATICCONFIG0 = 0x00000081; // CS0: 16 bit = WE
|
||||
LPC_EMC->STATICWAITOEN0 = 0; // CS0: WAITOEN = 0
|
||||
|
||||
#if (PLATFORM == HITEX_A2_BOARD)
|
||||
|
||||
LPC_EMC->STATICWAITRD0 = 7; // CS0: WAITRD = 7
|
||||
|
||||
// The Hitex board has external SRAM on CS2
|
||||
// @120MHz there should be 7 waitstates for the 55ns SRAM, it should work with 6
|
||||
LPC_EMC->STATICCONFIG0 = 0x00000081; // CS2: 16 bit = WE
|
||||
LPC_EMC->STATICWAITOEN2 = 0; // CS2: WAITOEN = 0
|
||||
LPC_EMC->STATICWAITRD2 = 7; // CS2: WAITRD = 6
|
||||
|
||||
#elif (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
LPC_EMC->STATICWAITRD0 = check 9; // CS0: WAITRD = 8
|
||||
// to be added
|
||||
|
||||
LPC_EMC->STATICCONFIG0 = check 0x00000081; // CS2: 16 bit = WE
|
||||
LPC_EMC->STATICWAITOEN2 = check 0; // CS2: WAITOEN = 0
|
||||
LPC_EMC->STATICWAITRD2 = check 7; // CS2: WAITRD = 6
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
// Defines for EMC signal delay settings
|
||||
#define EMC_B_ENABLE (1 << 19)
|
||||
#define EMC_ENABLE (1 << 0)
|
||||
#define EMC_CE_ENABLE (1 << 0)
|
||||
#define EMC_CS_ENABLE (1 << 1)
|
||||
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
|
||||
#define EMC_INIT(i) ((i) << 7)
|
||||
#define EMC_NORMAL (0)
|
||||
#define EMC_MODE (1)
|
||||
#define EMC_PRECHARGE_ALL (2)
|
||||
#define EMC_NOP (3)
|
||||
|
||||
/****************************************************************************************
|
||||
* Configure the delays for the SDRAM
|
||||
*
|
||||
* - on the Hitex board (IS42S16400D-7TL)
|
||||
* - on the NXP evaluation board (MT48LC4M32B2)
|
||||
* - on the NXP validation board (MT48LC4M32B2)
|
||||
*
|
||||
****************************************************************************************/
|
||||
#if (PLATFORM == HITEX_A2_BOARD) || (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
// Defines for SDRAM devices
|
||||
#define DOUT_DELAY 0
|
||||
#define CLK0_DELAY 5
|
||||
#define CLKE0_DELAY 5
|
||||
#define RAS_DELAY 0
|
||||
#define CAS_DELAY 0
|
||||
#define WE_DELAY 0
|
||||
#define DYCS0_DELAY 0
|
||||
#define DQM0_DELAY 0
|
||||
#define FBCLK0_DELAY 0
|
||||
#define CCLK_DELAY 0
|
||||
#define ADDR_DELAY 0
|
||||
#define DIN_DELAY 0
|
||||
#define DEN_DELAY 0
|
||||
|
||||
#endif
|
||||
|
||||
void initEmiDelays(void)
|
||||
{
|
||||
// eventually configure delays, defaults are zero
|
||||
|
||||
// CLK & CLKE0 delay
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD00) = ((CLK0_DELAY << 16) | (CLKE0_DELAY << 0) );
|
||||
|
||||
// EMCCTRLDELAY, address 0x4008 6D04
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD04) = ((WE_DELAY << 12)| (CAS_DELAY << 4) | (RAS_DELAY << 0) );
|
||||
|
||||
// DYCS0_DELAY, address 0x4008 6D08
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD08) = ((DYCS0_DELAY << 0));
|
||||
|
||||
// data out delay for D0 to D31 EMCDOUTDELAY
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD0C) = ((DOUT_DELAY << 28) | (DOUT_DELAY << 24) | (DOUT_DELAY << 20) | (DOUT_DELAY << 16)|(DQM0_DELAY << 12) | (DQM0_DELAY << 8) | (DQM0_DELAY << 4) | (DQM0_DELAY << 0)) ;
|
||||
|
||||
// EMCFBCLKDELAY, address 0x4008 6D10
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD10) = ((CCLK_DELAY << 16)|(FBCLK0_DELAY << 12) | (FBCLK0_DELAY << 8) | (FBCLK0_DELAY << 4) | (FBCLK0_DELAY << 0)) ;
|
||||
|
||||
// EMCADDRDELAY, address 0x4008 6D14, 0x4008 6D18, 0x4008 6D1C)
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD14) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD18) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD1C) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
|
||||
|
||||
// data in delay for D0 to D31 EMCDINDELAY
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD24) = ((DEN_DELAY << 28)|(DEN_DELAY << 24)|(DEN_DELAY << 20)|(DEN_DELAY << 16)|(DIN_DELAY << 12)|(DIN_DELAY << 8)|(DIN_DELAY << 4)|(DIN_DELAY << 0));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Configure the EMI for the SDRAM
|
||||
*
|
||||
* - on the Hitex board (IS42S16400D-7TL)
|
||||
* - on the NXP validation board (MT48LC4M32B2)
|
||||
*
|
||||
****************************************************************************************/
|
||||
void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
|
||||
{
|
||||
|
||||
// calculate a 1 usec delay base
|
||||
delayBase1us = M4Frequency / DELAY_1usFreq;
|
||||
|
||||
// eventually adjust the CCU delays for EMI (default to zero)
|
||||
initEmiDelays();
|
||||
|
||||
// Initialize EMC to interface with SDRAM. The EMC needs to run for this.
|
||||
LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller
|
||||
LPC_EMC->CONFIG = 0;
|
||||
|
||||
#if (PLATFORM == HITEX_A2_BOARD)
|
||||
|
||||
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.
|
||||
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0.
|
||||
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.
|
||||
LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period
|
||||
LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period
|
||||
LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time
|
||||
LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time
|
||||
LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.
|
||||
LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time
|
||||
LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period
|
||||
LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period
|
||||
LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time
|
||||
LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency
|
||||
LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
|
||||
|
||||
// Write configuration data to SDRAM device
|
||||
if(u32DataBus == 0) // 16-bit data bus, the EMC enforces a burst size 8
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
|
||||
}
|
||||
else // burst size 4 (which is not an option for 16-bit data bus anyway)
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
|
||||
}
|
||||
#endif // HITEX_BOARD
|
||||
|
||||
|
||||
#if (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));
|
||||
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8);
|
||||
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
|
||||
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
|
||||
LPC_EMC->DYNAMICRAS = 2;
|
||||
LPC_EMC->DYNAMICSREX = 5;
|
||||
LPC_EMC->DYNAMICAPR = 0;
|
||||
LPC_EMC->DYNAMICDAL = 4;
|
||||
LPC_EMC->DYNAMICWR = 1;
|
||||
LPC_EMC->DYNAMICRC = 5;
|
||||
LPC_EMC->DYNAMICRFC = 5;
|
||||
LPC_EMC->DYNAMICXSR = 5;
|
||||
LPC_EMC->DYNAMICRRD = 0;
|
||||
LPC_EMC->DYNAMICMRD = 0;
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 2;
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 83;
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
|
||||
|
||||
// Write configuration data to SDRAM device
|
||||
if(u32DataBus == 0) // burst size 8
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
|
||||
}
|
||||
else // burst size 4
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
|
||||
}
|
||||
#endif // Validation board
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = 0;
|
||||
LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
** Function name:
|
||||
**
|
||||
** Description:
|
||||
**
|
||||
** Parameters:
|
||||
**
|
||||
** Returned value:
|
||||
**********************************************************************/
|
||||
static void vDelay(uint32_t u32Delay)
|
||||
{
|
||||
volatile uint32_t i;
|
||||
|
||||
for(i = 0; i < (u32Delay * delayBase1us); i++);
|
||||
}
|
||||
|
||||
@ -0,0 +1,89 @@
|
||||
//BF: take over the whole file
|
||||
|
||||
/***********************************************************************
|
||||
* $Id: emc_LPC43xx.h 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC18xx_43xx.h
|
||||
*
|
||||
* Project: NXP LPC18xx/LPC43xx Common
|
||||
*
|
||||
* Description: Header file for emc_LPC18xx_43xx.c
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef EMC_LPC43XX_H_
|
||||
#define EMC_LPC43XX_H_
|
||||
|
||||
|
||||
enum {
|
||||
PART_WIDTH_8 = 0,
|
||||
PART_WIDTH_16 = 1,
|
||||
PART_WIDTH_32 = 2
|
||||
};
|
||||
|
||||
enum {
|
||||
PART_SIZE_16 = 0,
|
||||
PART_SIZE_64 = 1,
|
||||
PART_SIZE_128 = 2,
|
||||
PART_SIZE_256 = 3,
|
||||
PART_SIZE_512 = 4
|
||||
};
|
||||
|
||||
enum {
|
||||
EXT_WIDTH_16 = 0,
|
||||
EXT_WIDTH_32 = 1
|
||||
};
|
||||
|
||||
|
||||
#if (PLATFORM == HITEX_A2_BOARD) //defined USE_HITEX_A2
|
||||
|
||||
#define SDRAM_SIZE 0x00800000 // 8 MByte SDRAM IS42S16400D-7TL
|
||||
#define SDRAM_BASE 0x28000000 // base address for DYCS0
|
||||
|
||||
// We have 16 data lines connected to the SDRAM
|
||||
#define PART_WIDTH (PART_WIDTH_16) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.
|
||||
#define PART_SIZE (PART_SIZE_64)
|
||||
#define EXT_WIDTH (EXT_WIDTH_16) // external memory bus width
|
||||
#define COL_ADDR_BITS (8) // for calculating how to write mode bits
|
||||
|
||||
#endif
|
||||
|
||||
#if (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
#define SDRAM_SIZE 0x01000000 // 16 MByte SDRAM MT48LC4M32
|
||||
#define SDRAM_BASE 0x28000000 // base address for DYCS0
|
||||
|
||||
// We have 32 data lines connected to the SDRAM
|
||||
#define PART_WIDTH (PART_WIDTH_32) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.
|
||||
#define PART_SIZE (PART_SIZE_128)
|
||||
#define EXT_WIDTH (EXT_WIDTH_32) // external memory bus width
|
||||
#define COL_ADDR_BITS (8) // for calculating how to write mode bits
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Function prototypes
|
||||
void EMC_Init( void );
|
||||
void EMC_Config_Pinmux( void );
|
||||
void EMC_Config_Static( void );
|
||||
void initEmiDelays( void );
|
||||
void EMC_Init_SRDRAM( uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits );
|
||||
|
||||
|
||||
#endif /* EMC_LPC43XX_H_ */
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,69 @@
|
||||
/***********************************************************************
|
||||
* $Id: fpu_init.c
|
||||
*
|
||||
* Project: LPC43xx
|
||||
*
|
||||
* Description: fpu initialization routine
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#define LPC_CPACR 0xE000ED88
|
||||
|
||||
#define SCB_MVFR0 0xE000EF40
|
||||
#define SCB_MVFR0_RESET 0x10110021
|
||||
|
||||
#define SCB_MVFR1 0xE000EF44
|
||||
#define SCB_MVFR1_RESET 0x11000011
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
void fpuInit(void)
|
||||
{
|
||||
// from arm trm manual:
|
||||
// ; CPACR is located at address 0xE000ED88
|
||||
// LDR.W R0, =0xE000ED88
|
||||
// ; Read CPACR
|
||||
// LDR R1, [R0]
|
||||
// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||
// ORR R1, R1, #(0xF << 20)
|
||||
// ; Write back the modified value to the CPACR
|
||||
// STR R1, [R0]
|
||||
|
||||
|
||||
volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
|
||||
volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
|
||||
volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
|
||||
volatile uint32_t Cpacr;
|
||||
volatile uint32_t Mvfr0;
|
||||
volatile uint32_t Mvfr1;
|
||||
char vfpPresent = 0;
|
||||
|
||||
Mvfr0 = *regMvfr0;
|
||||
Mvfr1 = *regMvfr1;
|
||||
|
||||
vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
|
||||
|
||||
if(vfpPresent)
|
||||
{
|
||||
Cpacr = *regCpacr;
|
||||
Cpacr |= (0xF << 20);
|
||||
*regCpacr = Cpacr; // enable CP10 and CP11 for full access
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,29 @@
|
||||
/***********************************************************************
|
||||
* $Id: fpu_init.h
|
||||
*
|
||||
* Project: LPC43xx
|
||||
*
|
||||
* Description: fpu initialization routine header
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __FPU_INIT_H
|
||||
#define __FPU_INIT_H
|
||||
|
||||
void fpuInit(void);
|
||||
|
||||
#endif /* __FPU_INIT_H */
|
||||
@ -0,0 +1,37 @@
|
||||
/***********************************************************************
|
||||
* $Id: scu.c 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* This file contains code to configure the PINMUX
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#if defined CORE_M4
|
||||
#include "LPC43xx.h" /* LPC43xx definitions */
|
||||
#endif
|
||||
|
||||
#ifdef CORE_M0
|
||||
#include "LPC43xx_M0.h" /* LPC43xx definitions */
|
||||
#endif
|
||||
|
||||
#include "type.h"
|
||||
#include "scu.h"
|
||||
|
||||
void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func)
|
||||
{
|
||||
volatile unsigned int * const scu_base=(unsigned int*)(LPC_SCU_BASE);
|
||||
scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func;
|
||||
} /* scu_pinmux */
|
||||
@ -0,0 +1,125 @@
|
||||
/***********************************************************************
|
||||
* $Id: scu.h 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* Header file for PINMUX configuration
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
#ifndef __SCU_H
|
||||
#define __SCU_H
|
||||
|
||||
#define PORT_OFFSET 0x80
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin modes */
|
||||
//#define MD_PUP (0x0<<3)
|
||||
//#define MD_BUK (0x1<<3)
|
||||
//#define MD_PLN (0x2<<3)
|
||||
//#define MD_PDN (0x3<<3)
|
||||
//#define MD_EHS (0x1<<5)
|
||||
//#define MD_EZI (0x1<<6)
|
||||
//#define MD_ZI (0x1<<7)
|
||||
//#define MD_EHD0 (0x1<<8)
|
||||
//#define MD_EHD1 (0x1<<8)
|
||||
|
||||
/* Pin modes
|
||||
* =========
|
||||
* The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip
|
||||
* pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the
|
||||
* selection of the repeater mode.
|
||||
* The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
|
||||
* pull-up/pull-down. The default value is pull-up enabled.
|
||||
*
|
||||
* The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
|
||||
* the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
|
||||
* known state if it is configured as an input and is not driven externally. Repeater mode may
|
||||
* typically be used to prevent a pin from floating (and potentially using significant power if it
|
||||
* floats to an indeterminate state) if it is temporarily not driven.
|
||||
*
|
||||
* To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
|
||||
* the pin configuration registers. By default, the input buffer is disabled.
|
||||
* For pads that support both a digital and an analog function, the input buffer must be
|
||||
* disabled before enabling the analog function
|
||||
*
|
||||
* All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
|
||||
* off. By default, the glitch filter is on. The glitch filter should be disabled for
|
||||
* clocking signals with frequencies higher than 30 MHz.
|
||||
*
|
||||
* Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
|
||||
* between lower noise and low speed or higher noise and high speed . The typical
|
||||
* frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for
|
||||
* high-speed pins.
|
||||
*/
|
||||
|
||||
/* these definitions allow to set or clear single configuration bits */
|
||||
#define PDN_SET (1 << 3)
|
||||
#define PDN_CLR (0)
|
||||
#define PUP_SET (0)
|
||||
#define PUP_CLR (1 << 4)
|
||||
|
||||
/* these definitions allow to configure the port in one specific mode */
|
||||
/* within scu_pinmux() function */
|
||||
#define PDN_ENABLE (0x3 << 3) /* pull down */
|
||||
#define PUP_ENABLE (0x0 << 3) /* pull up */
|
||||
#define REPEATER_ENABLE (0x1 << 3) /* repeater */
|
||||
#define PLAIN_ENABLE (0x2 << 3) /* no pull up, no pull down (plain) */
|
||||
|
||||
#define SLEWRATE_SLOW (0)
|
||||
#define SLEWRATE_FAST (1 << 5)
|
||||
|
||||
/* enable / disable the input buffer */
|
||||
#define INBUF_ENABLE (1 << 6)
|
||||
#define INBUF_DISABLE (0)
|
||||
|
||||
/* enable / disable the filter */
|
||||
#define FILTER_ENABLE (0)
|
||||
#define FILTER_DISABLE (1 << 7)
|
||||
|
||||
/* define the drive strenght */
|
||||
#define DRIVE_8MA (0x1 << 8) // Drive strength of 8mA
|
||||
#define DRIVE_14MA (0x1 << 9) // Drive strength of 14mA
|
||||
#define DRIVE_20MA (0x3 << 8) // Drive strength of 20mA
|
||||
|
||||
|
||||
|
||||
// Configuration examples for external memory bus pins
|
||||
#define EMC_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE)
|
||||
#define EMC_IO (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
// Configuration examples
|
||||
#define CLK_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE)
|
||||
#define CLK_IN (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
/* Pin functions */
|
||||
#define FUNC0 0x0
|
||||
#define FUNC1 0x1
|
||||
#define FUNC2 0x2
|
||||
#define FUNC3 0x3
|
||||
#define FUNC4 0x4
|
||||
#define FUNC5 0x5
|
||||
#define FUNC6 0x6
|
||||
#define FUNC7 0x7
|
||||
|
||||
extern void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func);
|
||||
|
||||
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
|
||||
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
|
||||
|
||||
|
||||
#endif /* end __SCU_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@ -0,0 +1,422 @@
|
||||
;/***********************************************************************
|
||||
; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
; *
|
||||
; * Project: LPC43xx CMSIS Package
|
||||
; *
|
||||
; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx
|
||||
; * Device Series.
|
||||
; *
|
||||
; * Copyright(C) 2011, NXP Semiconductor
|
||||
; * All rights reserved.
|
||||
; *
|
||||
; ***********************************************************************
|
||||
; * Software that is described herein is for illustrative purposes only
|
||||
; * which provides customers with programming information regarding the
|
||||
; * products. This software is supplied "AS IS" without any warranties.
|
||||
; * NXP Semiconductors assumes no responsibility or liability for the
|
||||
; * use of the software, conveys no license or title under any patent,
|
||||
; * copyright, or mask work right to the product. NXP Semiconductors
|
||||
; * reserves the right to make changes in the software without
|
||||
; * notification. NXP Semiconductors also make no representation or
|
||||
; * warranty that such application will be suitable for the specified
|
||||
; * use without further testing or modification.
|
||||
; **********************************************************************/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __endVectors
|
||||
|
||||
Sign_Value EQU 0x5A5A5A5A
|
||||
|
||||
; IF :DEF:EXT_FLASH
|
||||
;
|
||||
;Signature_Size EQU 0x10
|
||||
; DCD 0x000200DA
|
||||
; DCD 0x00000000
|
||||
; DCD 0x00000000
|
||||
; DCD 0x00000000
|
||||
; SPACE Signature_Size
|
||||
; DCD __initial_sp
|
||||
; DCD Reset_Handler ; 1 Reset Handler
|
||||
; FILL 256 - 8 - 16
|
||||
; ENDIF
|
||||
|
||||
|
||||
__Vectors DCD __initial_sp ; 0 Top of Stack
|
||||
DCD Reset_Handler ; 1 Reset Handler
|
||||
DCD NMI_Handler ; 2 NMI Handler
|
||||
DCD HardFault_Handler ; 3 Hard Fault Handler
|
||||
DCD MemManage_Handler ; 4 MPU Fault Handler
|
||||
DCD BusFault_Handler ; 5 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; 6 Usage Fault Handler
|
||||
DCD Sign_Value ; 7 Reserved
|
||||
DCD 0 ; 8 Reserved
|
||||
DCD 0 ; 9 Reserved
|
||||
DCD 0 ; 10 Reserved
|
||||
DCD SVC_Handler ; 11 SVCall Handler
|
||||
DCD DebugMon_Handler ; 12 Debug Monitor Handler
|
||||
DCD 0 ; 13 Reserved
|
||||
DCD PendSV_Handler ; 14 PendSV Handler
|
||||
DCD SysTick_Handler ; 15 SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DAC_IRQHandler ; 16 D/A Converter
|
||||
DCD M0_IRQHandler ; 17 M0
|
||||
DCD DMA_IRQHandler ; 18 General Purpose DMA
|
||||
DCD 0 ; 19 Reserved
|
||||
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
|
||||
DCD ETH_IRQHandler ; 21 Ethernet
|
||||
DCD SDIO_IRQHandler ; 22 SD/MMC
|
||||
DCD LCD_IRQHandler ; 23 LCD
|
||||
DCD USB0_IRQHandler ; 24 USB0
|
||||
DCD USB1_IRQHandler ; 25 USB1
|
||||
DCD SCT_IRQHandler ; 26 State Configurable Timer
|
||||
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
|
||||
DCD TIMER0_IRQHandler ; 28 Timer0
|
||||
DCD TIMER1_IRQHandler ; 29 Timer1
|
||||
DCD TIMER2_IRQHandler ; 30 Timer2
|
||||
DCD TIMER3_IRQHandler ; 31 Timer3
|
||||
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
|
||||
DCD ADC0_IRQHandler ; 33 A/D Converter 0
|
||||
DCD I2C0_IRQHandler ; 34 I2C0
|
||||
DCD I2C1_IRQHandler ; 35 I2C1
|
||||
DCD SPI_IRQHandler ; 36 SPI
|
||||
DCD ADC1_IRQHandler ; 37 A/D Converter 1
|
||||
DCD SSP0_IRQHandler ; 38 SSP0
|
||||
DCD SSP1_IRQHandler ; 39 SSP1
|
||||
DCD UART0_IRQHandler ; 40 UART0
|
||||
DCD UART1_IRQHandler ; 41 UART1
|
||||
DCD UART2_IRQHandler ; 42 UART2
|
||||
DCD UART3_IRQHandler ; 43 UART3
|
||||
DCD I2S0_IRQHandler ; 44 I2S0
|
||||
DCD I2S1_IRQHandler ; 45 I2S1
|
||||
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
|
||||
DCD SGPIO_IRQHandler ; 47 SGPIO
|
||||
DCD GPIO0_IRQHandler ; 48 GPIO0
|
||||
DCD GPIO1_IRQHandler ; 49 GPIO1
|
||||
DCD GPIO2_IRQHandler ; 50 GPIO2
|
||||
DCD GPIO3_IRQHandler ; 51 GPIO3
|
||||
DCD GPIO4_IRQHandler ; 52 GPIO4
|
||||
DCD GPIO5_IRQHandler ; 53 GPIO5
|
||||
DCD GPIO6_IRQHandler ; 54 GPIO6
|
||||
DCD GPIO7_IRQHandler ; 55 GPIO7
|
||||
DCD GINT0_IRQHandler ; 56 GINT0
|
||||
DCD GINT1_IRQHandler ; 57 GINT1
|
||||
DCD EVRT_IRQHandler ; 58 Event Router
|
||||
DCD CAN1_IRQHandler ; 59 C_CAN1
|
||||
DCD 0 ; 60 Reserved
|
||||
DCD VADC_IRQHandler ; 61 VADC
|
||||
DCD ATIMER_IRQHandler ; 62 ATIMER
|
||||
DCD RTC_IRQHandler ; 63 RTC
|
||||
DCD 0 ; 64 Reserved
|
||||
DCD WDT_IRQHandler ; 65 WDT
|
||||
DCD 0 ; 66 Reserved
|
||||
DCD CAN0_IRQHandler ; 67 C_CAN0
|
||||
DCD QEI_IRQHandler ; 68 QEI
|
||||
|
||||
__endVectors
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
|
||||
IF :DEF:EXT_FLASH
|
||||
|
||||
; Extend the address bus, as the bootloader configured only [A13:0]
|
||||
; *(uint32_t*)(0x40086320) = 0x000000F1;
|
||||
; P6_8: A14 (function 1)
|
||||
LDR R0, =0x40086320
|
||||
LDR R1, =0x000000F1
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x4008631C) = 0x000000F1;
|
||||
; P6_7: A15 (function 1)
|
||||
LDR R0, =0x4008631C
|
||||
LDR R1, =0x000000F1
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x400866C0) = 0x000000F2;
|
||||
; PD_16: A16 (function 2)
|
||||
LDR R0, =0x400866C0
|
||||
LDR R1, =0x000000F2
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x400866BC) = 0x000000F2;
|
||||
; PD_15: A17 (function 2)
|
||||
LDR R0, =0x400866BC
|
||||
LDR R1, =0x000000F2
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086700) = 0x000000F3;
|
||||
; PE_0: A18 (function 3)
|
||||
LDR R0, =0x40086700
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086704) = 0x000000F3;
|
||||
; PE_1: A19 (function 3)
|
||||
LDR R0, =0x40086704
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086708) = 0x000000F3;
|
||||
; PE_2: A20 (function 3)
|
||||
LDR R0, =0x40086708
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x4008670C) = 0x000000F3;
|
||||
; PE_3: A21 (function 3)
|
||||
LDR R0, =0x4008670C
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086710) = 0x000000F3;
|
||||
; PE_4: A22 (function 3)
|
||||
LDR R0, =0x40086710
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
|
||||
; IMPORT _startup_configureFlash
|
||||
; LDR R0, =_startup_configureFlash
|
||||
; NOP
|
||||
; NOP
|
||||
; NOP
|
||||
; BLX R0
|
||||
|
||||
ENDIF
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
; FreeRTOS handler
|
||||
vPortSVCHandler\
|
||||
PROC
|
||||
EXPORT vPortSVCHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
; FreeRTOS handler
|
||||
xPortPendSVHandler\
|
||||
PROC
|
||||
EXPORT xPortPendSVHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
; FreeRTOS handler
|
||||
xPortSysTickHandler\
|
||||
PROC
|
||||
EXPORT xPortSysTickHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT M0_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USB1_IRQHandler [WEAK]
|
||||
EXPORT SCT_IRQHandler [WEAK]
|
||||
EXPORT RIT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT I2S1_IRQHandler [WEAK]
|
||||
EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SGPIO_IRQHandler [WEAK]
|
||||
EXPORT GPIO0_IRQHandler [WEAK]
|
||||
EXPORT GPIO1_IRQHandler [WEAK]
|
||||
EXPORT GPIO2_IRQHandler [WEAK]
|
||||
EXPORT GPIO3_IRQHandler [WEAK]
|
||||
EXPORT GPIO4_IRQHandler [WEAK]
|
||||
EXPORT GPIO5_IRQHandler [WEAK]
|
||||
EXPORT GPIO6_IRQHandler [WEAK]
|
||||
EXPORT GPIO7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT EVRT_IRQHandler [WEAK]
|
||||
EXPORT CAN1_IRQHandler [WEAK]
|
||||
EXPORT VADC_IRQHandler [WEAK]
|
||||
EXPORT ATIMER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
|
||||
|
||||
|
||||
|
||||
DAC_IRQHandler
|
||||
M0_IRQHandler
|
||||
DMA_IRQHandler
|
||||
FLASH_EEPROM_IRQHandler
|
||||
ETH_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
LCD_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USB1_IRQHandler
|
||||
SCT_IRQHandler
|
||||
RIT_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
I2S1_IRQHandler
|
||||
SPIFI_IRQHandler
|
||||
SGPIO_IRQHandler
|
||||
GPIO0_IRQHandler
|
||||
GPIO1_IRQHandler
|
||||
GPIO2_IRQHandler
|
||||
GPIO3_IRQHandler
|
||||
GPIO4_IRQHandler
|
||||
GPIO5_IRQHandler
|
||||
GPIO6_IRQHandler
|
||||
GPIO7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
EVRT_IRQHandler
|
||||
CAN1_IRQHandler
|
||||
VADC_IRQHandler
|
||||
ATIMER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
QEI_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,590 @@
|
||||
/***********************************************************************
|
||||
* $Id: system_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* CMSIS Cortex-M4 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC43xx Device Series
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined CORE_M4
|
||||
#include "LPC43xx.h" /* LPC18xx definitions */
|
||||
#endif
|
||||
|
||||
#ifdef CORE_M0
|
||||
#include "LPC43xx_M0.h" /* LPC18xx definitions */
|
||||
#endif
|
||||
|
||||
#include "scu.h"
|
||||
#include "type.h"
|
||||
#include "config.h"
|
||||
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------*/
|
||||
//#define OTP
|
||||
#define FLASH_SETUP 0
|
||||
#define FLASHCFG_Val 0x0000303A
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
|
||||
#error "SCS: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
|
||||
#error "CLKSRCSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
|
||||
#error "PLL0CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
|
||||
#error "PLL1CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
|
||||
#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
||||
#error "USBCLKCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
||||
#error "PCLKSEL0: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
||||
#error "PCLKSEL1: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
||||
#error "PCONP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
||||
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
/* Flash Accelerator Configuration -------------------------------------------*/
|
||||
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
|
||||
#error "FLASHCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t XtalFrequency = 0;
|
||||
uint32_t PL160M_0Frequency = 0;
|
||||
uint32_t PL160M_1Frequency = 0;
|
||||
uint32_t PL160M_2Frequency = 0;
|
||||
uint32_t PL550Frequency = 0;
|
||||
uint32_t PL550FracFrequency = 0; //New in Falcon
|
||||
uint32_t IDIVAFrequency = 0;
|
||||
uint32_t IDIVBFrequency = 0;
|
||||
uint32_t IDIVCFrequency = 0;
|
||||
uint32_t IDIVDFrequency = 0;
|
||||
uint32_t IDIVEFrequency = 0;
|
||||
uint32_t USB1Frequency = 0;
|
||||
uint32_t M4Frequency = 0;
|
||||
uint32_t SPIFIFrequency = 0;
|
||||
uint32_t SPIFrequency = 0;
|
||||
uint32_t EnetRxFrequency = 0;
|
||||
uint32_t EnetTxFrequency = 0;
|
||||
uint32_t EXTFrequency = 0;
|
||||
uint32_t VPB1Frequency = 0;
|
||||
uint32_t VPB3Frequency = 0;
|
||||
uint32_t LCDFrequency = 0;
|
||||
uint32_t SCIFrequency = 0;
|
||||
uint32_t VADCFrequency = 0;
|
||||
uint32_t SDIOFrequency = 0;
|
||||
uint32_t SSP0Frequency = 0;
|
||||
uint32_t SSP1Frequency = 0;
|
||||
uint32_t UART0Frequency = 0;
|
||||
uint32_t UART1Frequency = 0;
|
||||
uint32_t UART2Frequency = 0;
|
||||
uint32_t UART3Frequency = 0;
|
||||
uint32_t OUTFrequency = 0;
|
||||
uint32_t AOTESTFrequency = 0;
|
||||
uint32_t ISOFrequency = 0;
|
||||
uint32_t BSRFrequency = 0;
|
||||
uint32_t CLK_TESTFrequency = 0;
|
||||
uint32_t APLLFrequency = 0;
|
||||
uint32_t SPARE0Frequency = 0;
|
||||
uint32_t SPARE1Frequency = 0;
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#ifdef OTP
|
||||
// Set IRC trim if OTP is not programmed.
|
||||
if( *(uint32_t *)LPC_OTP_CTRL_BASE == 0x00FF ||
|
||||
*(uint32_t *)(LPC_OTP_CTRL_BASE+4) == 0x0000)
|
||||
{
|
||||
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
|
||||
}
|
||||
#else
|
||||
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
|
||||
#endif
|
||||
|
||||
// Set all GPIO as input.
|
||||
LPC_GPIO0->DIR = 0x0000;
|
||||
LPC_GPIO1->DIR = 0x0000;
|
||||
LPC_GPIO2->DIR = 0x0000;
|
||||
LPC_GPIO3->DIR = 0x0000;
|
||||
LPC_GPIO4->DIR = 0x0000;
|
||||
LPC_GPIO5->DIR = 0x0000;
|
||||
LPC_GPIO6->DIR = 0x0000;
|
||||
LPC_GPIO7->DIR = 0x0000;
|
||||
|
||||
// M4 runs on IRC by default
|
||||
M4Frequency = IRC_OSC;
|
||||
XtalFrequency = XTAL_FREQ;
|
||||
EXTFrequency = EXT_FREQ;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set Clock
|
||||
*
|
||||
* @param target PLL, source clock, division
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup a clock
|
||||
*/
|
||||
void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div)
|
||||
{
|
||||
volatile uint32_t target_clk_adr;
|
||||
volatile uint8_t auto_block=TRUE;
|
||||
uint32_t src_freq;
|
||||
|
||||
EnableSourceClk(src_clk);
|
||||
|
||||
switch(div)
|
||||
{
|
||||
case(DIV1): // Divide by 1 == no division
|
||||
break;
|
||||
case(DIV2):
|
||||
LPC_CGU->IDIVA_CTRL = (src_clk<<24) | (1<<2) | AUTO_BLOCK;
|
||||
IDIVAFrequency = GetClockFrequency(src_clk)/2;
|
||||
src_clk = SRC_IDIV_0; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV4):
|
||||
LPC_CGU->IDIVB_CTRL = (src_clk<<24) | (3<<2) |AUTO_BLOCK;
|
||||
IDIVBFrequency = GetClockFrequency(src_clk)/4;
|
||||
src_clk = SRC_IDIV_1; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV8):
|
||||
LPC_CGU->IDIVC_CTRL = (src_clk<<24) | (7<<2) |AUTO_BLOCK;
|
||||
IDIVCFrequency = GetClockFrequency(src_clk)/8;
|
||||
src_clk = SRC_IDIV_2; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV16):
|
||||
LPC_CGU->IDIVD_CTRL = (src_clk<<24) | (15<<2) |AUTO_BLOCK;
|
||||
IDIVDFrequency = GetClockFrequency(src_clk)/16;
|
||||
src_clk = SRC_IDIV_3; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV256):
|
||||
LPC_CGU->IDIVE_CTRL = (src_clk<<24) | (255<<2) |AUTO_BLOCK; // MAX 128? IDIV bit 2:9 = 7 bits = 127 max
|
||||
IDIVEFrequency = GetClockFrequency(src_clk)/256;
|
||||
src_clk = SRC_IDIV_4; // Set new src_clk for target_clk
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
src_freq = GetClockFrequency(src_clk);
|
||||
|
||||
switch(target_clk)
|
||||
{
|
||||
case(BASE_OUT_CLK):
|
||||
{
|
||||
LPC_SCU->SFSCLK_0 = 1; // function 1; CGU clk out, diable pull down, disable pull-up
|
||||
auto_block = FALSE;
|
||||
break;
|
||||
}
|
||||
case(XTAL):
|
||||
{
|
||||
XtalFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
|
||||
break;
|
||||
}
|
||||
case(ENET_RX):
|
||||
{
|
||||
EnetRxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
|
||||
break;
|
||||
}
|
||||
case(ENET_TX):
|
||||
{
|
||||
EnetTxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
|
||||
break;
|
||||
}
|
||||
case(BASE_USB1_CLK):
|
||||
{
|
||||
USB1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_M4_CLK):
|
||||
{
|
||||
M4Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPIFI_CLK):
|
||||
{
|
||||
SPIFIFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPI_CLK):
|
||||
{
|
||||
SPIFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_PHY_RX_CLK):
|
||||
{
|
||||
EnetRxFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_PHY_TX_CLK):
|
||||
{
|
||||
EnetTxFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_VPB1_CLK):
|
||||
{
|
||||
VPB1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_VPB3_CLK):
|
||||
{
|
||||
VPB3Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_LCD_CLK):
|
||||
{
|
||||
LCDFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case (BASE_VADC_CLK) :
|
||||
{
|
||||
VADCFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SDIO_CLK):
|
||||
{
|
||||
SDIOFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SSP0_CLK):
|
||||
{
|
||||
SSP0Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SSP1_CLK):
|
||||
{
|
||||
SSP1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART0_CLK):
|
||||
{
|
||||
UART0Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART1_CLK):
|
||||
{
|
||||
UART1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART2_CLK):
|
||||
{
|
||||
UART2Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART3_CLK):
|
||||
{
|
||||
UART3Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_AOTEST_CLK):
|
||||
{
|
||||
AOTESTFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_ISO_TCK):
|
||||
{
|
||||
ISOFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_BSR_TCK):
|
||||
{
|
||||
BSRFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_CLK_TEST):
|
||||
{
|
||||
CLK_TESTFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_APLL_CLK): //New in Falcon
|
||||
{
|
||||
APLLFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPARE0_CLK): //New in Falcon
|
||||
{
|
||||
SPARE0Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPARE1_CLK): //New in Falcon
|
||||
{
|
||||
SPARE1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if(target_clk<200)
|
||||
{
|
||||
target_clk_adr = (uint32_t) &LPC_CGU->IDIVA_CTRL + (target_clk-2)*4;
|
||||
*(uint32_t *)target_clk_adr = (src_clk<<24) | (auto_block<<11);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Get Clock Frequency
|
||||
*
|
||||
* @param source clock
|
||||
* @return frequency
|
||||
*
|
||||
* @brief returns the current frequency of a base clock
|
||||
*/
|
||||
uint32_t GetClockFrequency(CLKSRC_Type src_clk)
|
||||
{
|
||||
switch(src_clk)
|
||||
{
|
||||
case(SRC_OSC32K):
|
||||
return RTC_CLK;
|
||||
case(SRC_IRC):
|
||||
return IRC_OSC;
|
||||
case(SRC_ENET_RX_CLK):
|
||||
return EnetRxFrequency;
|
||||
case(SRC_ENET_TX_CLK):
|
||||
return EnetTxFrequency;
|
||||
case(SRC_EXT_TCK):
|
||||
return EXTFrequency;
|
||||
case(SRC_XTAL):
|
||||
return XtalFrequency;
|
||||
case(SRC_PL550M_0):
|
||||
return PL550Frequency;
|
||||
case(SRC_PL550M_FRAC): //New in Falcon
|
||||
return PL550FracFrequency;
|
||||
case(SRC_PL160M_0):
|
||||
return PL160M_0Frequency;
|
||||
case(SRC_PL160M_1):
|
||||
return PL160M_1Frequency;
|
||||
case(SRC_PL160M_2):
|
||||
return PL160M_2Frequency;
|
||||
case(SRC_IDIV_0):
|
||||
return IDIVAFrequency;
|
||||
case(SRC_IDIV_1):
|
||||
return IDIVBFrequency;
|
||||
case(SRC_IDIV_2):
|
||||
return IDIVCFrequency;
|
||||
case(SRC_IDIV_3):
|
||||
return IDIVDFrequency;
|
||||
case(SRC_IDIV_4):
|
||||
return IDIVEFrequency;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set PL160M
|
||||
*
|
||||
* @param source clock, desired frequency
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the PL160M PLL
|
||||
* If frequency equals 0 then disable PLL
|
||||
* Integer mode only (fbsel=1, direct=0)
|
||||
* Fclkout = M * Fclkin/N
|
||||
* Fcc0 = 2 * P * Fclkout = 2 * P * M * Fclkin/N
|
||||
* msel+1 = feedback-divider value M (1 to 2^15)
|
||||
* nsel+1 = pre-divider value N (1 to 2^8)
|
||||
* psel+1 = post-divider value P(x2) (1 to 2^5)
|
||||
*/
|
||||
void SetPL160M(CLKSRC_Type src_clk, uint32_t mult)
|
||||
{
|
||||
uint32_t msel=0, nsel=0, psel=0, pval=1;
|
||||
|
||||
// EnableSourceClk(src_clk);
|
||||
|
||||
if(mult==0)
|
||||
{
|
||||
LPC_CGU->PLL1_CTRL |= PD_ENABLE; // Power down PLL
|
||||
DisableSourceClk(src_clk);
|
||||
}
|
||||
else
|
||||
{
|
||||
EnableSourceClk(src_clk);
|
||||
|
||||
switch(src_clk)
|
||||
{
|
||||
case(SRC_OSC32K):
|
||||
PL160M_0Frequency = mult * RTC_CLK;
|
||||
break;
|
||||
case(SRC_IRC):
|
||||
PL160M_0Frequency = mult * IRC_OSC;
|
||||
break;
|
||||
case(SRC_ENET_RX_CLK):
|
||||
PL160M_0Frequency = mult * EnetRxFrequency;
|
||||
break;
|
||||
case(SRC_ENET_TX_CLK):
|
||||
PL160M_0Frequency = mult * EnetTxFrequency;
|
||||
break;
|
||||
case(SRC_EXT_TCK):
|
||||
PL160M_0Frequency = mult * EXTFrequency;
|
||||
break;
|
||||
case(SRC_XTAL):
|
||||
PL160M_0Frequency = mult * XtalFrequency;
|
||||
break;
|
||||
default:
|
||||
PL160M_0Frequency = mult * IRC_OSC;
|
||||
break;
|
||||
}
|
||||
|
||||
// CCO must be in range of 156 - 320 MHz
|
||||
// Increase P if FCCO is too low.
|
||||
msel = mult-1;
|
||||
//psel is encoded such that 0=1, 1=2, 2=4, 3=8
|
||||
while(2*(pval)*PL160M_0Frequency < 156000000) {
|
||||
psel++;
|
||||
pval*=2;
|
||||
}
|
||||
// if(2*(pval)*PL160M_0Frequency > 320000000) {
|
||||
// THIS IS OUT OF RANGE!!!
|
||||
// HOW DO WE ASSERT IN SAMPLE CODE?
|
||||
// __breakpoint(0);
|
||||
// }
|
||||
LPC_CGU->PLL1_CTRL = (src_clk<<24) | (msel<<16) | (nsel<<12) | (psel<<8) | FBSEL;
|
||||
while((LPC_CGU->PLL1_STAT&1) == 0x0); // Wait for PLL lock
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set PLL USB (PL550M)
|
||||
*
|
||||
* @param enable
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the USB PLL to 480 MHz
|
||||
* If enable equals 0 then disable PLL
|
||||
* Only clock sources IRC and XTAL are valid
|
||||
* Mode1a only: Normal operating mode without post- and pre-divider
|
||||
* Fclkout = 2 * M * Fclkin
|
||||
* msel+1 = feedback-divider value M (1 to 2^15)
|
||||
*/
|
||||
void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable)
|
||||
{
|
||||
if(!enable)
|
||||
{
|
||||
LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL
|
||||
}
|
||||
else
|
||||
{
|
||||
// Setup PLL550 to generate 480MHz from 12 MHz crystal
|
||||
LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL
|
||||
// P N
|
||||
LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);
|
||||
// SELP SELI SELR MDEC
|
||||
LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);
|
||||
LPC_CGU->PLL0USB_CTRL =(SRC_XTAL<<24) | (0x3<<2) | CLKEN;
|
||||
|
||||
// Set the USB0 clock source to PLL550 (480MHz)
|
||||
LPC_CGU->BASE_USB0_CLK = (0<<0) | (1<<11) | (SRC_PL550M_0<<24);
|
||||
|
||||
while((LPC_CGU->PLL0USB_STAT&1) == 0x0); // Wait for PLL lock
|
||||
}
|
||||
|
||||
PL550Frequency = 480000000UL;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable source clock pheripheral
|
||||
*
|
||||
* @param clock source
|
||||
* @return none
|
||||
*
|
||||
* @brief Enable clock specific peripherals
|
||||
*/
|
||||
void EnableSourceClk(CLKSRC_Type src_clk)
|
||||
{
|
||||
uint32_t i=0;
|
||||
|
||||
if(src_clk == SRC_OSC32K)
|
||||
{
|
||||
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset
|
||||
LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k
|
||||
}
|
||||
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC3); // enet_rx_clk on PC_0 func 3
|
||||
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC0); // enet_tx_clk on P1_19 func 0
|
||||
if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1))
|
||||
{
|
||||
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M
|
||||
for(i=0;i<0xFFFF;i++);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable source clock pheripheral
|
||||
*
|
||||
* @param clock source
|
||||
* @return none
|
||||
*
|
||||
* @brief Disable clock specific peripherals
|
||||
*/
|
||||
void DisableSourceClk(CLKSRC_Type src_clk)
|
||||
{
|
||||
uint32_t i=0;
|
||||
|
||||
if(src_clk == SRC_OSC32K)
|
||||
{
|
||||
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k
|
||||
LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode
|
||||
}
|
||||
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC0); // nc on PC_0 func 0
|
||||
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC2); // nc on P1_19 func 2
|
||||
if(src_clk == SRC_XTAL)
|
||||
{
|
||||
LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M
|
||||
for(i=0;i<0xFFFF;i++);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,186 @@
|
||||
/***********************************************************************
|
||||
* $Id: system_LPC43xx.h 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* CMSIS Cortex-M4 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC43xx Device Series
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC18xx_H
|
||||
#define __SYSTEM_LPC18xx_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "scu.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BUTTON0 !((LPC_GPIO3->PIN>>6)&1) // P6.10
|
||||
#define BUTTON1 !((LPC_GPIO2->PIN>>0)&1) // P4.0
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
DO NOT SET MANUALLY, SET WITH SetClock AND SetPL160M
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t XtalFrequency;
|
||||
extern uint32_t PL160M_0Frequency;
|
||||
extern uint32_t PL160M_1Frequency;
|
||||
extern uint32_t PL160M_2Frequency;
|
||||
extern uint32_t PL550Frequency;
|
||||
extern uint32_t PL550FracFrequency; //New in Falcon
|
||||
extern uint32_t IDIVAFrequency;
|
||||
extern uint32_t IDIVBFrequency;
|
||||
extern uint32_t IDIVCFrequency;
|
||||
extern uint32_t IDIVDFrequency;
|
||||
extern uint32_t IDIVEFrequency;
|
||||
extern uint32_t M0Frequency;
|
||||
extern uint32_t USB1Frequency;
|
||||
extern uint32_t M4Frequency;
|
||||
extern uint32_t SPIFIFrequency;
|
||||
extern uint32_t SPIFrequency;
|
||||
extern uint32_t EnetRxFrequency;
|
||||
extern uint32_t EnetTxFrequency;
|
||||
extern uint32_t EXTFrequency;
|
||||
extern uint32_t VPB1Frequency;
|
||||
extern uint32_t VPB3Frequency;
|
||||
extern uint32_t LCDFrequency;
|
||||
extern uint32_t SCIFrequency;
|
||||
extern uint32_t SDIOFrequency;
|
||||
extern uint32_t SSP0Frequency;
|
||||
extern uint32_t SSP1Frequency;
|
||||
extern uint32_t UART0Frequency;
|
||||
extern uint32_t UART1Frequency;
|
||||
extern uint32_t UART2Frequency;
|
||||
extern uint32_t UART3Frequency;
|
||||
extern uint32_t OUTFrequency;
|
||||
extern uint32_t AOTESTFrequency;
|
||||
extern uint32_t ISOFrequency;
|
||||
extern uint32_t BSRFrequency;
|
||||
extern uint32_t CLK_TESTFrequency;
|
||||
extern uint32_t APLLFrequency;
|
||||
extern uint32_t SPARE0Frequency;
|
||||
extern uint32_t SPARE1Frequency;
|
||||
|
||||
|
||||
typedef enum CLKDIV
|
||||
{
|
||||
DIV1 = 1,
|
||||
DIV2 = 2,
|
||||
DIV4 = 4,
|
||||
DIV8 = 8,
|
||||
DIV16 = 16,
|
||||
DIV256 = 256,
|
||||
} CLKDIV_Type;
|
||||
|
||||
typedef enum CLKSRC
|
||||
{
|
||||
SRC_OSC32K = 0,
|
||||
SRC_IRC = 1,
|
||||
SRC_ENET_RX_CLK = 2,
|
||||
SRC_ENET_TX_CLK = 3,
|
||||
SRC_EXT_TCK = 4,
|
||||
RESERVED = 5, // Do NOT use
|
||||
SRC_XTAL = 6,
|
||||
SRC_PL550M_0 = 7,
|
||||
SRC_PL550M_FRAC = 8, //New in Falcon
|
||||
SRC_PL160M_0 = 9,
|
||||
SRC_PL160M_1 = 10,
|
||||
SRC_PL160M_2 = 11,
|
||||
SRC_IDIV_0 = 12,
|
||||
SRC_IDIV_1 = 13,
|
||||
SRC_IDIV_2 = 14,
|
||||
SRC_IDIV_3 = 15,
|
||||
SRC_IDIV_4 = 16,
|
||||
NOT_DEFINED = 0xFFFFFFF, // Force a signed int enum, so every possible frequency can be entered
|
||||
} CLKSRC_Type;
|
||||
|
||||
typedef enum CLKBASE
|
||||
{
|
||||
PL550M = 0, //PL550Frac is new, should be added???
|
||||
PL160M = 1,
|
||||
IDIVA_4 = 2,
|
||||
IDIVB_16 = 3,
|
||||
IDIVC_16 = 4,
|
||||
IDIVD_16 = 5,
|
||||
IDIVE_256 = 6,
|
||||
BASE_SAFE_CLK = 7,
|
||||
BASE_USB0_CLK = 8,
|
||||
BASE_M0_CLK = 9,
|
||||
BASE_USB1_CLK = 10,
|
||||
BASE_M4_CLK = 11,
|
||||
BASE_SPIFI_CLK = 12,
|
||||
BASE_SPI_CLK = 13,
|
||||
BASE_PHY_RX_CLK = 14,
|
||||
BASE_PHY_TX_CLK = 15,
|
||||
BASE_VPB1_CLK = 16,
|
||||
BASE_VPB3_CLK = 17,
|
||||
BASE_LCD_CLK = 18,
|
||||
BASE_VADC_CLK = 19, //New
|
||||
BASE_SDIO_CLK = 20,
|
||||
BASE_SSP0_CLK = 21,
|
||||
BASE_SSP1_CLK = 22,
|
||||
BASE_UART0_CLK = 23,
|
||||
BASE_UART1_CLK = 24,
|
||||
BASE_UART2_CLK = 25,
|
||||
BASE_UART3_CLK = 26,
|
||||
BASE_OUT_CLK = 27,
|
||||
BASE_AOTEST_CLK = 28,
|
||||
BASE_ISO_TCK = 29,
|
||||
BASE_BSR_TCK = 30,
|
||||
BASE_CLK_TEST = 31,
|
||||
BASE_APLL_CLK = 32, //New in Falcon
|
||||
BASE_SPARE0_CLK = 33, //New in Falcon
|
||||
BASE_SPARE1_CLK = 34, //New in Falcon
|
||||
XTAL = 253,
|
||||
ENET_RX = 254,
|
||||
ENET_TX = 255,
|
||||
}CLKBASE_Type;
|
||||
|
||||
// PL550M
|
||||
#define MODE1A (0x3<<2) // Normal operating mode without post-divider and without pre-divider
|
||||
#define MODE1B (0x2<<2) // Normal operating mode with post-divider and without pre-divider
|
||||
#define MODE1C (0x1<<2) // Normal operating mode without post-divider and with pre-divider
|
||||
#define MODE1D (0x0<<2) // Normal operating mode with post-divider and with pre-divider.
|
||||
#define BYPASSOFF (0<<1)
|
||||
#define CLKEN (1<<4)
|
||||
|
||||
// PL160M
|
||||
#define FBSEL (1<<6)
|
||||
#define MSEL_FBDIV(n) (n<<16) // MSEL = feedback-divider value 2*M (1 to 2^15)
|
||||
#define NSEL_PREDIV(n) (n<<12) // NSEL = pre-divider value N (1 to 2^8)
|
||||
#define PSEL_POSTDIV(n) (n<<8) // PSEL = post-divider value P*2 (1 to 2^5)
|
||||
|
||||
// Generic clock properties
|
||||
#define AUTO_BLOCK (1<<11)
|
||||
#define PD_ENABLE (1<<0)
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div);
|
||||
extern void SetPL160M(CLKSRC_Type src_clk, uint32_t mult);
|
||||
extern void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable);
|
||||
extern void EnableSourceClk(CLKSRC_Type src_clk);
|
||||
extern void DisableSourceClk(CLKSRC_Type src_clk);
|
||||
extern void IOInit(void);
|
||||
extern uint32_t GetClockFrequency(CLKSRC_Type src_clk);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC43xx_H */
|
||||
@ -0,0 +1,78 @@
|
||||
/***********************************************************************
|
||||
* $Id: type.h 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* Type definition Header file for NXP LPC4300 Family
|
||||
* Microprocessors
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __TYPE_H__
|
||||
#define __TYPE_H__
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
#define ABS(value) (value<0 ? -value : value)
|
||||
|
||||
/**
|
||||
* @brief Flag Status and Interrupt Flag Status type definition
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
|
||||
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
|
||||
|
||||
/**
|
||||
* @brief Functional State Definition
|
||||
*/
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
|
||||
|
||||
/**
|
||||
* @ Status type definition
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
|
||||
|
||||
typedef unsigned char BYTE;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned long DWORD;
|
||||
typedef unsigned int BOOL;
|
||||
|
||||
typedef union _BITS
|
||||
{
|
||||
unsigned char value;
|
||||
struct _bits
|
||||
{
|
||||
unsigned char bit0:1;
|
||||
unsigned char bit1:1;
|
||||
unsigned char bit2:1;
|
||||
unsigned char bit3:1;
|
||||
unsigned char bit4:1;
|
||||
unsigned char bit5:1;
|
||||
unsigned char bit6:1;
|
||||
unsigned char bit7:1;
|
||||
}bits;
|
||||
}BITS;
|
||||
|
||||
#endif /* __TYPE_H__ */
|
||||
@ -0,0 +1,151 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Ensure stdint is only used by the compiler, and not the assembler. */
|
||||
#ifdef __ICCARM__
|
||||
#include <stdint.h>
|
||||
extern uint32_t SystemCoreClock;
|
||||
#endif
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 1
|
||||
#define configCPU_CLOCK_HZ ( SystemCoreClock )
|
||||
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
|
||||
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 75 * 1024 ) )
|
||||
#define configMAX_TASK_NAME_LEN ( 10 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 8
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_MALLOC_FAILED_HOOK 1
|
||||
#define configUSE_APPLICATION_TASK_TAG 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Software timer definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY ( 2 )
|
||||
#define configTIMER_QUEUE_LENGTH 10
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 1
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
|
||||
/* Cortex-M specific definitions. */
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4 /* 15 priority levels */
|
||||
#endif
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority"
|
||||
function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
standard names. */
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,99 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F4XX_H
|
||||
#define __SYSTEM_STM32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F4XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because one or more lines are too long
@ -0,0 +1,629 @@
|
||||
;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f4xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.0.0
|
||||
;* Date : 30-September-2011
|
||||
;* Description : STM32F4xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock and the external SRAM mounted on
|
||||
;* STM324xG-EVAL board to be used as data memory (optional,
|
||||
;* to be enabled by user)
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
;*******************************************************************************/
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD CRYP_IRQHandler ; CRYP crypto
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PVD_IRQHandler
|
||||
B PVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TAMP_STAMP_IRQHandler
|
||||
B TAMP_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream0_IRQHandler
|
||||
B DMA1_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream1_IRQHandler
|
||||
B DMA1_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream2_IRQHandler
|
||||
B DMA1_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream3_IRQHandler
|
||||
B DMA1_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream4_IRQHandler
|
||||
B DMA1_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream5_IRQHandler
|
||||
B DMA1_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream6_IRQHandler
|
||||
B DMA1_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_SCE_IRQHandler
|
||||
B CAN1_SCE_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_TIM9_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
B TIM1_BRK_TIM9_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM10_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
B TIM1_UP_TIM10_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
B TIM1_TRG_COM_TIM11_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
B OTG_FS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_TIM12_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
B TIM8_BRK_TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_TIM13_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
B TIM8_UP_TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
B TIM8_TRG_COM_TIM14_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream7_IRQHandler
|
||||
B DMA1_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK FSMC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
FSMC_IRQHandler
|
||||
B FSMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_DAC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM6_DAC_IRQHandler
|
||||
B TIM6_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream0_IRQHandler
|
||||
B DMA2_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream1_IRQHandler
|
||||
B DMA2_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream2_IRQHandler
|
||||
B DMA2_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream3_IRQHandler
|
||||
B DMA2_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream4_IRQHandler
|
||||
B DMA2_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK ETH_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ETH_WKUP_IRQHandler
|
||||
B ETH_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_TX_IRQHandler
|
||||
B CAN2_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_RX0_IRQHandler
|
||||
B CAN2_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_RX1_IRQHandler
|
||||
B CAN2_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_SCE_IRQHandler
|
||||
B CAN2_SCE_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream5_IRQHandler
|
||||
B DMA2_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream6_IRQHandler
|
||||
B DMA2_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream7_IRQHandler
|
||||
B DMA2_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
B OTG_HS_EP1_OUT_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_IN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
B OTG_HS_EP1_IN_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
B OTG_HS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_IRQHandler
|
||||
B OTG_HS_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DCMI_IRQHandler
|
||||
B DCMI_IRQHandler
|
||||
|
||||
PUBWEAK CRYP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CRYP_IRQHandler
|
||||
B CRYP_IRQHandler
|
||||
|
||||
PUBWEAK HASH_RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HASH_RNG_IRQHandler
|
||||
B HASH_RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
END
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,553 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F4xx devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f4xx_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*=============================================================================
|
||||
* Supported STM32F4xx device revision | Rev A
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 168000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 168000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 25000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 25
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 336
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* I2S input clock | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD(V) | 3.3
|
||||
*-----------------------------------------------------------------------------
|
||||
* Main regulator output voltage | Scale1 mode
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 5
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | OFF
|
||||
*-----------------------------------------------------------------------------
|
||||
* Instruction cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Data cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Enabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM mounted
|
||||
on STM324xG_EVAL board as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/************************* PLL Parameters *************************************/
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
|
||||
#define PLL_M 25
|
||||
#define PLL_N 336
|
||||
|
||||
/* SYSCLK = PLL_VCO / PLL_P */
|
||||
#define PLL_P 2
|
||||
|
||||
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
|
||||
#define PLL_Q 7
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 168000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @Note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM324xG_EVAL board
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/*
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
+ SRAM pins assignment +
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
|
||||
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
|
||||
| PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
|
||||
| PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
|
||||
| PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
|
||||
| PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
|
||||
| PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
|
||||
| PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
|
||||
| PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
|
||||
| PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
|
||||
| PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
|
||||
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
|
||||
| | PE15 <-> FSMC_D12 |
|
||||
+-------------------+--------------------+
|
||||
*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR = 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00cc00cc;
|
||||
GPIOD->AFR[1] = 0xcc0ccccc;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xaaaa0a0a;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xffff0f0f;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xc00cc0cc;
|
||||
GPIOE->AFR[1] = 0xcccccccc;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xaaaa828a;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xffffc3cf;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR = 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001015;
|
||||
FSMC_Bank1->BTCR[3] = 0x00010603;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 3;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 6;
|
||||
p.FSMC_BusTurnAroundDuration = 1;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because one or more lines are too long
@ -0,0 +1,172 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be an enumerator of @ref IRQn_Type
|
||||
enumeration (For the complete STM32 Devices IRQ Channels
|
||||
list, please refer to stm32f4xx.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,643 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_ADC_H
|
||||
#define __STM32F4xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
|
||||
This parameter can be a value of @ref ADC_resolution */
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
|
||||
is performed in Scan (multichannels)
|
||||
or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
|
||||
is performed in Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
|
||||
enable the trigger of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
|
||||
the start of conversion of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
|
||||
is left or right. This parameter can be
|
||||
a value of @ref ADC_data_align */
|
||||
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
|
||||
that will be done using the sequencer for
|
||||
regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Common Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
|
||||
independent or multi mode.
|
||||
This parameter can be a value of @ref ADC_Common_mode */
|
||||
uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
|
||||
to the ADC. The clock is common for all the ADCs.
|
||||
This parameter can be a value of @ref ADC_Prescaler */
|
||||
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
|
||||
mode for multi ADC mode.
|
||||
This parameter can be a value of
|
||||
@ref ADC_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value of
|
||||
@ref ADC_delay_between_2_sampling_phases */
|
||||
|
||||
}ADC_CommonInitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
/** @defgroup ADC_Common_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
|
||||
#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
|
||||
#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
|
||||
#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
|
||||
#define ADC_DualMode_Interl ((uint32_t)0x00000007)
|
||||
#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
|
||||
#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
|
||||
#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
|
||||
#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
|
||||
#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
|
||||
#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
|
||||
#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
|
||||
((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_DualMode_InjecSimult) || \
|
||||
((MODE) == ADC_DualMode_RegSimult) || \
|
||||
((MODE) == ADC_DualMode_Interl) || \
|
||||
((MODE) == ADC_DualMode_AlterTrig) || \
|
||||
((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
|
||||
((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_TripleMode_InjecSimult) || \
|
||||
((MODE) == ADC_TripleMode_RegSimult) || \
|
||||
((MODE) == ADC_TripleMode_Interl) || \
|
||||
((MODE) == ADC_TripleMode_AlterTrig))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
|
||||
#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
|
||||
#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
|
||||
#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
|
||||
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div4) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div6) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
|
||||
#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
|
||||
#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
|
||||
#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
|
||||
((MODE) == ADC_DMAAccessMode_1) || \
|
||||
((MODE) == ADC_DMAAccessMode_2) || \
|
||||
((MODE) == ADC_DMAAccessMode_3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_delay_between_2_sampling_phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
|
||||
#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
|
||||
#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
|
||||
#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
|
||||
#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
|
||||
#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
|
||||
#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
|
||||
#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
|
||||
#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
|
||||
#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
|
||||
#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
|
||||
#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
|
||||
#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
|
||||
#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
|
||||
#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
|
||||
#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
|
||||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
|
||||
((DELAY) == ADC_TwoSamplingDelay_20Cycles))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000)
|
||||
#define ADC_Resolution_10b ((uint32_t)0x01000000)
|
||||
#define ADC_Resolution_8b ((uint32_t)0x02000000)
|
||||
#define ADC_Resolution_6b ((uint32_t)0x03000000)
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
|
||||
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
|
||||
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
|
||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
|
||||
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
|
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
|
||||
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
|
||||
#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
|
||||
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
|
||||
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
|
||||
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
|
||||
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
#define ADC_Channel_18 ((uint8_t)0x12)
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
|
||||
((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || \
|
||||
((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || \
|
||||
((CHANNEL) == ADC_Channel_17) || \
|
||||
((CHANNEL) == ADC_Channel_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_sampling_times
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
|
||||
((TIME) == ADC_SampleTime_15Cycles) || \
|
||||
((TIME) == ADC_SampleTime_28Cycles) || \
|
||||
((TIME) == ADC_SampleTime_56Cycles) || \
|
||||
((TIME) == ADC_SampleTime_84Cycles) || \
|
||||
((TIME) == ADC_SampleTime_112Cycles) || \
|
||||
((TIME) == ADC_SampleTime_144Cycles) || \
|
||||
((TIME) == ADC_SampleTime_480Cycles))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
|
||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
|
||||
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
|
||||
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_IT_EOC ((uint16_t)0x0205)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0106)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0407)
|
||||
#define ADC_IT_OVR ((uint16_t)0x201A)
|
||||
#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
#define ADC_FLAG_OVR ((uint8_t)0x20)
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
|
||||
((FLAG) == ADC_FLAG_EOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOC) || \
|
||||
((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT) || \
|
||||
((FLAG)== ADC_FLAG_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
|
||||
/* Temperature Sensor, Vrefint and VBAT management functions ******************/
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||
void ADC_VBATCmd(FunctionalState NewState);
|
||||
|
||||
/* Regular Channels Configuration functions ***********************************/
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetMultiModeConversionValue(void);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
|
||||
|
||||
/* Injected channels Configuration functions **********************************/
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
|
||||
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,638 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CAN_H
|
||||
#define __STM32F4xx_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
|
||||
((PERIPH) == CAN2))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode_status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
|
||||
an empty mailbox */
|
||||
/* Legacy defines */
|
||||
#define CANTXFAILED CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* CAN Frames Transmission functions ******************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* CAN Frames Reception functions *********************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* CAN Bus Error management functions *****************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_CAN_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,77 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CRC_H
|
||||
#define __STM32F4xx_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void CRC_ResetDR(void);
|
||||
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
void CRC_SetIDRegister(uint8_t IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_CRC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,338 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the Cryptographic
|
||||
* processor(CRYP) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CRYP_H
|
||||
#define __STM32F4xx_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a
|
||||
value of @ref CRYP_Algorithm_Direction */
|
||||
uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB,
|
||||
AES-CBC, AES-CTR, AES-Key. This parameter can be
|
||||
a value of @ref CRYP_Algorithm_Mode */
|
||||
uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit
|
||||
key length. This parameter can be a value of
|
||||
@ref CRYP_Key_Size_for_AES_only */
|
||||
}CRYP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRYP Key(s) structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CRYP_Key0Left; /*!< Key 0 Left */
|
||||
uint32_t CRYP_Key0Right; /*!< Key 0 Right */
|
||||
uint32_t CRYP_Key1Left; /*!< Key 1 left */
|
||||
uint32_t CRYP_Key1Right; /*!< Key 1 Right */
|
||||
uint32_t CRYP_Key2Left; /*!< Key 2 left */
|
||||
uint32_t CRYP_Key2Right; /*!< Key 2 Right */
|
||||
uint32_t CRYP_Key3Left; /*!< Key 3 left */
|
||||
uint32_t CRYP_Key3Right; /*!< Key 3 Right */
|
||||
}CRYP_KeyInitTypeDef;
|
||||
/**
|
||||
* @brief CRYP Initialization Vectors (IV) structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */
|
||||
uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
|
||||
uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */
|
||||
uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
|
||||
}CRYP_IVInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRYP context swapping structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*!< Configuration */
|
||||
uint32_t CR_bits9to2;
|
||||
/*!< KEY */
|
||||
uint32_t CRYP_IV0LR;
|
||||
uint32_t CRYP_IV0RR;
|
||||
uint32_t CRYP_IV1LR;
|
||||
uint32_t CRYP_IV1RR;
|
||||
/*!< IV */
|
||||
uint32_t CRYP_K0LR;
|
||||
uint32_t CRYP_K0RR;
|
||||
uint32_t CRYP_K1LR;
|
||||
uint32_t CRYP_K1RR;
|
||||
uint32_t CRYP_K2LR;
|
||||
uint32_t CRYP_K2RR;
|
||||
uint32_t CRYP_K3LR;
|
||||
uint32_t CRYP_K3RR;
|
||||
}CRYP_Context;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Direction
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)
|
||||
#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)
|
||||
#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
|
||||
((ALGODIR) == CRYP_AlgoDir_Decrypt))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< TDES Modes */
|
||||
#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000)
|
||||
#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008)
|
||||
|
||||
/*!< DES Modes */
|
||||
#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010)
|
||||
#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018)
|
||||
|
||||
/*!< AES Modes */
|
||||
#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020)
|
||||
#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028)
|
||||
#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030)
|
||||
#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038)
|
||||
|
||||
#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
|
||||
((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
|
||||
((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \
|
||||
((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
|
||||
((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
|
||||
((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
|
||||
((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
|
||||
((ALGOMODE) == CRYP_AlgoMode_AES_Key))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DataType_32b ((uint16_t)0x0000)
|
||||
#define CRYP_DataType_16b ((uint16_t)0x0040)
|
||||
#define CRYP_DataType_8b ((uint16_t)0x0080)
|
||||
#define CRYP_DataType_1b ((uint16_t)0x00C0)
|
||||
#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
|
||||
((DATATYPE) == CRYP_DataType_16b)|| \
|
||||
((DATATYPE) == CRYP_DataType_8b)|| \
|
||||
((DATATYPE) == CRYP_DataType_1b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size_for_AES_only
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_KeySize_128b ((uint16_t)0x0000)
|
||||
#define CRYP_KeySize_192b ((uint16_t)0x0100)
|
||||
#define CRYP_KeySize_256b ((uint16_t)0x0200)
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
|
||||
((KEYSIZE) == CRYP_KeySize_192b)|| \
|
||||
((KEYSIZE) == CRYP_KeySize_256b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently
|
||||
processing a block of data
|
||||
or a key preparation (for
|
||||
AES decryption). */
|
||||
#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */
|
||||
#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */
|
||||
#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */
|
||||
#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw
|
||||
interrupt status */
|
||||
#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */
|
||||
#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw
|
||||
interrupt status */
|
||||
|
||||
#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \
|
||||
((FLAG) == CRYP_FLAG_IFNF) || \
|
||||
((FLAG) == CRYP_FLAG_OFNE) || \
|
||||
((FLAG) == CRYP_FLAG_OFFU) || \
|
||||
((FLAG) == CRYP_FLAG_BUSY) || \
|
||||
((FLAG) == CRYP_FLAG_OUTRIS)|| \
|
||||
((FLAG) == CRYP_FLAG_INRIS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */
|
||||
#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
|
||||
#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Encryption_Decryption_modes_definition
|
||||
* @{
|
||||
*/
|
||||
#define MODE_ENCRYPT ((uint8_t)0x01)
|
||||
#define MODE_DECRYPT ((uint8_t)0x00)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DMAReq_DataIN ((uint8_t)0x01)
|
||||
#define CRYP_DMAReq_DataOUT ((uint8_t)0x02)
|
||||
#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the CRYP configuration to the default reset state ****/
|
||||
void CRYP_DeInit(void);
|
||||
|
||||
/* CRYP Initialization and Configuration functions ****************************/
|
||||
void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
|
||||
void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
|
||||
void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
|
||||
void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
|
||||
void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
|
||||
void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
|
||||
void CRYP_Cmd(FunctionalState NewState);
|
||||
|
||||
/* CRYP Data processing functions *********************************************/
|
||||
void CRYP_DataIn(uint32_t Data);
|
||||
uint32_t CRYP_DataOut(void);
|
||||
void CRYP_FIFOFlush(void);
|
||||
|
||||
/* CRYP Context swapping functions ********************************************/
|
||||
ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
|
||||
CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
|
||||
void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
|
||||
|
||||
/* CRYP's DMA interface function **********************************************/
|
||||
void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
|
||||
ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
|
||||
FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
|
||||
|
||||
/* High Level AES functions **************************************************/
|
||||
ErrorStatus CRYP_AES_ECB(uint8_t Mode,
|
||||
uint8_t *Key, uint16_t Keysize,
|
||||
uint8_t *Input, uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
ErrorStatus CRYP_AES_CBC(uint8_t Mode,
|
||||
uint8_t InitVectors[16],
|
||||
uint8_t *Key, uint16_t Keysize,
|
||||
uint8_t *Input, uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
ErrorStatus CRYP_AES_CTR(uint8_t Mode,
|
||||
uint8_t InitVectors[16],
|
||||
uint8_t *Key, uint16_t Keysize,
|
||||
uint8_t *Input, uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
/* High Level TDES functions **************************************************/
|
||||
ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
|
||||
uint8_t Key[24],
|
||||
uint8_t *Input, uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
|
||||
uint8_t Key[24],
|
||||
uint8_t InitVectors[8],
|
||||
uint8_t *Input, uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
/* High Level DES functions **************************************************/
|
||||
ErrorStatus CRYP_DES_ECB(uint8_t Mode,
|
||||
uint8_t Key[8],
|
||||
uint8_t *Input, uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
ErrorStatus CRYP_DES_CBC(uint8_t Mode,
|
||||
uint8_t Key[8],
|
||||
uint8_t InitVectors[8],
|
||||
uint8_t *Input,uint32_t Ilength,
|
||||
uint8_t *Output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_CRYP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,298 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_DAC_H
|
||||
#define __STM32F4xx_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(void);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,103 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_DBGMCU_H
|
||||
#define __STM32F4xx_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
|
||||
#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)
|
||||
#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)
|
||||
#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)
|
||||
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
||||
#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
|
||||
#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)
|
||||
#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)
|
||||
#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)
|
||||
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_DBGMCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,306 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the DCMI firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_DCMI_H
|
||||
#define __STM32F4xx_DCMI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief DCMI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot.
|
||||
This parameter can be a value of @ref DCMI_Capture_Mode */
|
||||
|
||||
uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
||||
This parameter can be a value of @ref DCMI_Synchronization_Mode */
|
||||
|
||||
uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
||||
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
|
||||
|
||||
uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
|
||||
|
||||
uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
|
||||
|
||||
uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
|
||||
This parameter can be a value of @ref DCMI_Capture_Rate */
|
||||
|
||||
uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
|
||||
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
|
||||
} DCMI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI CROP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture
|
||||
will start. This parameter can be a value between 0x00 and 0x1FFF */
|
||||
|
||||
uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture.
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
|
||||
uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point.
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
|
||||
uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting
|
||||
point on the same line.
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
} DCMI_CROPInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */
|
||||
uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */
|
||||
uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
|
||||
} DCMI_CodesInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously
|
||||
into the destination memory through the DMA */
|
||||
#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of
|
||||
frame and then transfers a single frame through the DMA */
|
||||
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
|
||||
((MODE) == DCMI_CaptureMode_SnapShot))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_Synchronization_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
is synchronized with the HSYNC/VSYNC signals */
|
||||
#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with
|
||||
synchronization codes embedded in the data flow */
|
||||
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
|
||||
((MODE) == DCMI_SynchroMode_Embedded))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_PIXCK_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
|
||||
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
|
||||
((POLARITY) == DCMI_PCKPolarity_Rising))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_VSYNC_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */
|
||||
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
|
||||
((POLARITY) == DCMI_VSPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_HSYNC_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
|
||||
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
|
||||
((POLARITY) == DCMI_HSPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_Capture_Rate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */
|
||||
#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */
|
||||
#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
|
||||
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
|
||||
((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
|
||||
((RATE) == DCMI_CaptureRate_1of4_Frame))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_Extended_Data_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
|
||||
#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
|
||||
#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
|
||||
((DATA) == DCMI_ExtendedDataMode_10b) ||\
|
||||
((DATA) == DCMI_ExtendedDataMode_12b) ||\
|
||||
((DATA) == DCMI_ExtendedDataMode_14b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_IT_FRAME ((uint16_t)0x0001)
|
||||
#define DCMI_IT_OVF ((uint16_t)0x0002)
|
||||
#define DCMI_IT_ERR ((uint16_t)0x0004)
|
||||
#define DCMI_IT_VSYNC ((uint16_t)0x0008)
|
||||
#define DCMI_IT_LINE ((uint16_t)0x0010)
|
||||
#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
|
||||
#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
|
||||
((IT) == DCMI_IT_OVF) || \
|
||||
((IT) == DCMI_IT_ERR) || \
|
||||
((IT) == DCMI_IT_VSYNC) || \
|
||||
((IT) == DCMI_IT_LINE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMI_Flags
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DCMI SR register
|
||||
*/
|
||||
#define DCMI_FLAG_HSYNC ((uint16_t)0x2001)
|
||||
#define DCMI_FLAG_VSYNC ((uint16_t)0x2002)
|
||||
#define DCMI_FLAG_FNE ((uint16_t)0x2004)
|
||||
/**
|
||||
* @brief DCMI RISR register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)
|
||||
#define DCMI_FLAG_OVFRI ((uint16_t)0x0002)
|
||||
#define DCMI_FLAG_ERRRI ((uint16_t)0x0004)
|
||||
#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)
|
||||
#define DCMI_FLAG_LINERI ((uint16_t)0x0010)
|
||||
/**
|
||||
* @brief DCMI MISR register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)
|
||||
#define DCMI_FLAG_OVFMI ((uint16_t)0x1002)
|
||||
#define DCMI_FLAG_ERRMI ((uint16_t)0x1004)
|
||||
#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)
|
||||
#define DCMI_FLAG_LINEMI ((uint16_t)0x1010)
|
||||
#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
|
||||
((FLAG) == DCMI_FLAG_VSYNC) || \
|
||||
((FLAG) == DCMI_FLAG_FNE) || \
|
||||
((FLAG) == DCMI_FLAG_FRAMERI) || \
|
||||
((FLAG) == DCMI_FLAG_OVFRI) || \
|
||||
((FLAG) == DCMI_FLAG_ERRRI) || \
|
||||
((FLAG) == DCMI_FLAG_VSYNCRI) || \
|
||||
((FLAG) == DCMI_FLAG_LINERI) || \
|
||||
((FLAG) == DCMI_FLAG_FRAMEMI) || \
|
||||
((FLAG) == DCMI_FLAG_OVFMI) || \
|
||||
((FLAG) == DCMI_FLAG_ERRMI) || \
|
||||
((FLAG) == DCMI_FLAG_VSYNCMI) || \
|
||||
((FLAG) == DCMI_FLAG_LINEMI))
|
||||
|
||||
#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DCMI configuration to the default reset state ****/
|
||||
void DCMI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
|
||||
void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
|
||||
void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
|
||||
void DCMI_CROPCmd(FunctionalState NewState);
|
||||
void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
|
||||
void DCMI_JPEGCmd(FunctionalState NewState);
|
||||
|
||||
/* Image capture functions ****************************************************/
|
||||
void DCMI_Cmd(FunctionalState NewState);
|
||||
void DCMI_CaptureCmd(FunctionalState NewState);
|
||||
uint32_t DCMI_ReadData(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
|
||||
FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
|
||||
void DCMI_ClearFlag(uint16_t DCMI_FLAG);
|
||||
ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
|
||||
void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_DCMI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,603 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_DMA_H
|
||||
#define __STM32F4xx_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_channel */
|
||||
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
|
||||
|
||||
uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
|
||||
This memory is the default memory used when double buffer mode is
|
||||
not enabled. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
|
||||
This parameter can be a value of @ref DMA_fifo_direct_mode
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_fifo_threshold_level */
|
||||
|
||||
uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptable
|
||||
transaction. This parameter can be a value of @ref DMA_memory_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
|
||||
uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptable
|
||||
transaction. This parameter can be a value of @ref DMA_peripheral_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
|
||||
((PERIPH) == DMA1_Stream1) || \
|
||||
((PERIPH) == DMA1_Stream2) || \
|
||||
((PERIPH) == DMA1_Stream3) || \
|
||||
((PERIPH) == DMA1_Stream4) || \
|
||||
((PERIPH) == DMA1_Stream5) || \
|
||||
((PERIPH) == DMA1_Stream6) || \
|
||||
((PERIPH) == DMA1_Stream7) || \
|
||||
((PERIPH) == DMA2_Stream0) || \
|
||||
((PERIPH) == DMA2_Stream1) || \
|
||||
((PERIPH) == DMA2_Stream2) || \
|
||||
((PERIPH) == DMA2_Stream3) || \
|
||||
((PERIPH) == DMA2_Stream4) || \
|
||||
((PERIPH) == DMA2_Stream5) || \
|
||||
((PERIPH) == DMA2_Stream6) || \
|
||||
((PERIPH) == DMA2_Stream7))
|
||||
|
||||
#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
|
||||
((CONTROLLER) == DMA2))
|
||||
|
||||
/** @defgroup DMA_channel
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Channel_0 ((uint32_t)0x00000000)
|
||||
#define DMA_Channel_1 ((uint32_t)0x02000000)
|
||||
#define DMA_Channel_2 ((uint32_t)0x04000000)
|
||||
#define DMA_Channel_3 ((uint32_t)0x06000000)
|
||||
#define DMA_Channel_4 ((uint32_t)0x08000000)
|
||||
#define DMA_Channel_5 ((uint32_t)0x0A000000)
|
||||
#define DMA_Channel_6 ((uint32_t)0x0C000000)
|
||||
#define DMA_Channel_7 ((uint32_t)0x0E000000)
|
||||
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
|
||||
((CHANNEL) == DMA_Channel_1) || \
|
||||
((CHANNEL) == DMA_Channel_2) || \
|
||||
((CHANNEL) == DMA_Channel_3) || \
|
||||
((CHANNEL) == DMA_Channel_4) || \
|
||||
((CHANNEL) == DMA_Channel_5) || \
|
||||
((CHANNEL) == DMA_Channel_6) || \
|
||||
((CHANNEL) == DMA_Channel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
|
||||
#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
|
||||
#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
|
||||
((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
|
||||
((DIRECTION) == DMA_DIR_MemoryToMemory))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_data_buffer_size
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||
((STATE) == DMA_PeripheralInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||
((STATE) == DMA_MemoryInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000100)
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
|
||||
((MODE) == DMA_Mode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00010000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00020000)
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_VeryHigh))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_fifo_direct_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
|
||||
|
||||
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
|
||||
((STATE) == DMA_FIFOMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_fifo_threshold_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
|
||||
#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
|
||||
#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
|
||||
#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
|
||||
|
||||
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
|
||||
((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
|
||||
((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
|
||||
((THRESHOLD) == DMA_FIFOThreshold_Full))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
|
||||
#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
|
||||
#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
|
||||
|
||||
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
|
||||
((BURST) == DMA_MemoryBurst_INC4) || \
|
||||
((BURST) == DMA_MemoryBurst_INC8) || \
|
||||
((BURST) == DMA_MemoryBurst_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
|
||||
#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
|
||||
#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
|
||||
((BURST) == DMA_PeripheralBurst_INC4) || \
|
||||
((BURST) == DMA_PeripheralBurst_INC8) || \
|
||||
((BURST) == DMA_PeripheralBurst_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
|
||||
#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
|
||||
#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
|
||||
#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
|
||||
#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
|
||||
#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
|
||||
|
||||
#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
|
||||
((STATUS) == DMA_FIFOStatus_HalfFull) || \
|
||||
((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
|
||||
((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
|
||||
((STATUS) == DMA_FIFOStatus_Full) || \
|
||||
((STATUS) == DMA_FIFOStatus_Empty))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
|
||||
#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
|
||||
#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
|
||||
#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
|
||||
#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
|
||||
#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
|
||||
#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
|
||||
#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
|
||||
#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
|
||||
#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
|
||||
#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
|
||||
#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
|
||||
#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
|
||||
#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
|
||||
#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
|
||||
#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
|
||||
#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
|
||||
#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
|
||||
#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
|
||||
#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
|
||||
#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
|
||||
#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
|
||||
#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
|
||||
#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
|
||||
#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
|
||||
#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
|
||||
#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
|
||||
#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
|
||||
#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
|
||||
#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
|
||||
#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
|
||||
#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
|
||||
#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
|
||||
#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
|
||||
#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
|
||||
#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
|
||||
#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
|
||||
#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
|
||||
#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
|
||||
#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
|
||||
(((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
|
||||
((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
|
||||
((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
|
||||
((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
|
||||
((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
|
||||
((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
|
||||
((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
|
||||
((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
|
||||
((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
|
||||
((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
|
||||
((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
|
||||
((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
|
||||
((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
|
||||
((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
|
||||
((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
|
||||
((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)0x00000010)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000008)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000004)
|
||||
#define DMA_IT_DME ((uint32_t)0x00000002)
|
||||
#define DMA_IT_FE ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupts_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_FEIF0 ((uint32_t)0x90000001)
|
||||
#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
|
||||
#define DMA_IT_TEIF0 ((uint32_t)0x10002008)
|
||||
#define DMA_IT_HTIF0 ((uint32_t)0x10004010)
|
||||
#define DMA_IT_TCIF0 ((uint32_t)0x10008020)
|
||||
#define DMA_IT_FEIF1 ((uint32_t)0x90000040)
|
||||
#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
|
||||
#define DMA_IT_TEIF1 ((uint32_t)0x10002200)
|
||||
#define DMA_IT_HTIF1 ((uint32_t)0x10004400)
|
||||
#define DMA_IT_TCIF1 ((uint32_t)0x10008800)
|
||||
#define DMA_IT_FEIF2 ((uint32_t)0x90010000)
|
||||
#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
|
||||
#define DMA_IT_TEIF2 ((uint32_t)0x10082000)
|
||||
#define DMA_IT_HTIF2 ((uint32_t)0x10104000)
|
||||
#define DMA_IT_TCIF2 ((uint32_t)0x10208000)
|
||||
#define DMA_IT_FEIF3 ((uint32_t)0x90400000)
|
||||
#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
|
||||
#define DMA_IT_TEIF3 ((uint32_t)0x12002000)
|
||||
#define DMA_IT_HTIF3 ((uint32_t)0x14004000)
|
||||
#define DMA_IT_TCIF3 ((uint32_t)0x18008000)
|
||||
#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
|
||||
#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
|
||||
#define DMA_IT_TEIF4 ((uint32_t)0x20002008)
|
||||
#define DMA_IT_HTIF4 ((uint32_t)0x20004010)
|
||||
#define DMA_IT_TCIF4 ((uint32_t)0x20008020)
|
||||
#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
|
||||
#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
|
||||
#define DMA_IT_TEIF5 ((uint32_t)0x20002200)
|
||||
#define DMA_IT_HTIF5 ((uint32_t)0x20004400)
|
||||
#define DMA_IT_TCIF5 ((uint32_t)0x20008800)
|
||||
#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
|
||||
#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
|
||||
#define DMA_IT_TEIF6 ((uint32_t)0x20082000)
|
||||
#define DMA_IT_HTIF6 ((uint32_t)0x20104000)
|
||||
#define DMA_IT_TCIF6 ((uint32_t)0x20208000)
|
||||
#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
|
||||
#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
|
||||
#define DMA_IT_TEIF7 ((uint32_t)0x22002000)
|
||||
#define DMA_IT_HTIF7 ((uint32_t)0x24004000)
|
||||
#define DMA_IT_TCIF7 ((uint32_t)0x28008000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
|
||||
(((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
|
||||
(((IT) & 0x40820082) == 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
|
||||
((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
|
||||
((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
|
||||
((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
|
||||
((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
|
||||
((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
|
||||
((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
|
||||
((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
|
||||
((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
|
||||
((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
|
||||
((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
|
||||
((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
|
||||
((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
|
||||
((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
|
||||
((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
|
||||
((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
|
||||
((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
|
||||
((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
|
||||
((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
|
||||
((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_increment_offset
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINCOS_Psize ((uint32_t)0x00000000)
|
||||
#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
|
||||
|
||||
#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
|
||||
((SIZE) == DMA_PINCOS_WordAligned))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_flow_controller_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
|
||||
#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
|
||||
|
||||
#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
|
||||
((CTRL) == DMA_FlowCtrl_Peripheral))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_targets_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Memory_0 ((uint32_t)0x00000000)
|
||||
#define DMA_Memory_1 ((uint32_t)0x00080000)
|
||||
|
||||
#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state *****/
|
||||
void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
||||
|
||||
/* Optional Configuration functions *******************************************/
|
||||
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
|
||||
void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
|
||||
|
||||
/* Data Counter functions *****************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
|
||||
/* Double Buffer mode functions ***********************************************/
|
||||
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
|
||||
uint32_t DMA_CurrentMemory);
|
||||
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
||||
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
|
||||
uint32_t DMA_MemoryTarget);
|
||||
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
|
||||
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
|
||||
void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
|
||||
void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,177 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_EXTI_H
|
||||
#define __STM32F4xx_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination value of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||
#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
|
||||
#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
|
||||
((LINE) == EXTI_Line22))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_EXTI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,334 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_FLASH_H
|
||||
#define __STM32F4xx_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PGS,
|
||||
FLASH_ERROR_PGP,
|
||||
FLASH_ERROR_PGA,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_ERROR_OPERATION,
|
||||
FLASH_COMPLETE
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2) || \
|
||||
((LATENCY) == FLASH_Latency_3) || \
|
||||
((LATENCY) == FLASH_Latency_4) || \
|
||||
((LATENCY) == FLASH_Latency_5) || \
|
||||
((LATENCY) == FLASH_Latency_6) || \
|
||||
((LATENCY) == FLASH_Latency_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Voltage_Range
|
||||
* @{
|
||||
*/
|
||||
#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
|
||||
#define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
|
||||
#define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
|
||||
#define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
|
||||
|
||||
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
|
||||
((RANGE) == VoltageRange_2) || \
|
||||
((RANGE) == VoltageRange_3) || \
|
||||
((RANGE) == VoltageRange_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Sectors
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
|
||||
#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
|
||||
#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
|
||||
#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
|
||||
#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
|
||||
#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
|
||||
#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
|
||||
#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
|
||||
#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
|
||||
#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
|
||||
#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
|
||||
#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
|
||||
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
|
||||
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
|
||||
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
|
||||
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
|
||||
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
|
||||
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
|
||||
#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
|
||||
#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
|
||||
#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
|
||||
#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0x55)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_BOR_Reset_Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
|
||||
#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
|
||||
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
|
||||
#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
|
||||
#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
|
||||
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
|
||||
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
|
||||
#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
|
||||
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
|
||||
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
|
||||
((FLAG) == FLASH_FLAG_BSY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Program_Parallelism
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
|
||||
#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
|
||||
#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
|
||||
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
|
||||
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys
|
||||
* @{
|
||||
*/
|
||||
#define RDP_KEY ((uint16_t)0x00A5)
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
|
||||
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
|
||||
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ACR register byte 0 (Bits[8:0]) base address
|
||||
*/
|
||||
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
|
||||
/**
|
||||
* @brief OPTCR register byte 3 (Bits[24:16]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
|
||||
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
|
||||
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
void FLASH_InstructionCacheCmd(FunctionalState NewState);
|
||||
void FLASH_DataCacheCmd(FunctionalState NewState);
|
||||
void FLASH_InstructionCacheReset(void);
|
||||
void FLASH_DataCacheReset(void);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
|
||||
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
|
||||
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
|
||||
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
void FLASH_OB_BORConfig(uint8_t OB_BOR);
|
||||
FLASH_Status FLASH_OB_Launch(void);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint16_t FLASH_OB_GetWRP(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
uint8_t FLASH_OB_GetBOR(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,669 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_FSMC_H
|
||||
#define __STM32F4xx_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note This parameter is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note This parameter is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 0 and 0xFF.
|
||||
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note This parameter is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF.
|
||||
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The parameter value depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
}FSMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
}FSMC_NORSRAMInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For FSMC NAND and PCCARD Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 0xFF.*/
|
||||
|
||||
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command deassertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NAND Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */
|
||||
|
||||
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
}FSMC_NANDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
|
||||
}FSMC_PCCARDInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_PCCARD_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM4))
|
||||
|
||||
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND))
|
||||
|
||||
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
/** @defgroup FSMC_NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FSMC_DataAddressMux_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FSMC_MemoryType_NOR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FSMC_MemoryDataWidth_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FSMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FSMC_AsynchronousWait_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
|
||||
((MODE) == FSMC_WrapMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FSMC_WriteOperation_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FSMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FSMC_ExtendedMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||||
((BURST) == FSMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||||
((MODE) == FSMC_AccessMode_B) || \
|
||||
((MODE) == FSMC_AccessMode_C) || \
|
||||
((MODE) == FSMC_AccessMode_D))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
|
||||
((FEATURE) == FSMC_Waitfeature_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FSMC_ECC
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
|
||||
((STATE) == FSMC_ECC_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_8192Bytes))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||
#define FSMC_IT_Level ((uint32_t)0x00000010)
|
||||
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
|
||||
((IT) == FSMC_IT_Level) || \
|
||||
((IT) == FSMC_IT_FallingEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Flags
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
|
||||
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_Level) || \
|
||||
((FLAG) == FSMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* NOR/SRAM Controller functions **********************************************/
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
|
||||
/* NAND Controller functions **************************************************/
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||
|
||||
/* PCCARD Controller functions ************************************************/
|
||||
void FSMC_PCCARDDeInit(void);
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_FSMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,406 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_GPIO_H
|
||||
#define __STM32F4xx_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG) || \
|
||||
((PERIPH) == GPIOH) || \
|
||||
((PERIPH) == GPIOI))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration Mode enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Output type enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Output Maximum frequency enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_2MHz = 0x00, /*!< Low speed */
|
||||
GPIO_Speed_25MHz = 0x01, /*!< Medium speed */
|
||||
GPIO_Speed_50MHz = 0x02, /*!< Fast speed */
|
||||
GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
|
||||
}GPIOSpeed_TypeDef;
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
|
||||
((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration PullUp PullDown enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternat_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
|
||||
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
|
||||
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \
|
||||
((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \
|
||||
((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Mode_AIN GPIO_Mode_AN
|
||||
|
||||
#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
|
||||
#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
|
||||
#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the GPIO configuration to the default reset state ****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Alternate functions configuration function ****************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_GPIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,244 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the HASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HASH_H
|
||||
#define __STM32F4xx_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HASH Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value
|
||||
of @ref HASH_Algo_Selection */
|
||||
uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value
|
||||
of @ref HASH_processor_Algorithm_Mode */
|
||||
uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or
|
||||
bit-string. This parameter can be a value of
|
||||
@ref HASH_Data_Type */
|
||||
uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter
|
||||
can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
|
||||
}HASH_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HASH message digest result structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or
|
||||
4x 32bit words for MD5 */
|
||||
} HASH_MsgDigest;
|
||||
|
||||
/**
|
||||
* @brief HASH context swapping structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HASH_IMR;
|
||||
uint32_t HASH_STR;
|
||||
uint32_t HASH_CR;
|
||||
uint32_t HASH_CSR[51];
|
||||
}HASH_Context;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Algo_Selection
|
||||
* @{
|
||||
*/
|
||||
#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */
|
||||
#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */
|
||||
|
||||
#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
|
||||
((ALGOSELECTION) == HASH_AlgoSelection_MD5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_processor_Algorithm_Mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */
|
||||
#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */
|
||||
|
||||
#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
|
||||
((ALGOMODE) == HASH_AlgoMode_HMAC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Data_Type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_DataType_32b ((uint16_t)0x0000)
|
||||
#define HASH_DataType_16b ((uint16_t)0x0010)
|
||||
#define HASH_DataType_8b ((uint16_t)0x0020)
|
||||
#define HASH_DataType_1b ((uint16_t)0x0030)
|
||||
|
||||
#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
|
||||
((DATATYPE) == HASH_DataType_16b)|| \
|
||||
((DATATYPE) == HASH_DataType_8b)|| \
|
||||
((DATATYPE) == HASH_DataType_1b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
|
||||
#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */
|
||||
|
||||
#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
|
||||
((KEYTYPE) == HASH_HMACKeyType_LongKey))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Number_of_valid_bits_in_last_word_of_the_message
|
||||
* @{
|
||||
*/
|
||||
#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/
|
||||
#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */
|
||||
|
||||
#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/
|
||||
#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */
|
||||
#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
|
||||
#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */
|
||||
#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */
|
||||
|
||||
#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
|
||||
((FLAG) == HASH_FLAG_DCIS) || \
|
||||
((FLAG) == HASH_FLAG_DMAS) || \
|
||||
((FLAG) == HASH_FLAG_BUSY) || \
|
||||
((FLAG) == HASH_FLAG_DINNE))
|
||||
|
||||
#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
|
||||
((FLAG) == HASH_FLAG_DCIS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the HASH configuration to the default reset state ****/
|
||||
void HASH_DeInit(void);
|
||||
|
||||
/* HASH Configuration function ************************************************/
|
||||
void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
|
||||
void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
|
||||
void HASH_Reset(void);
|
||||
|
||||
/* HASH Message Digest generation functions ***********************************/
|
||||
void HASH_DataIn(uint32_t Data);
|
||||
uint8_t HASH_GetInFIFOWordsNbr(void);
|
||||
void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
|
||||
void HASH_StartDigest(void);
|
||||
void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
|
||||
|
||||
/* HASH Context swapping functions ********************************************/
|
||||
void HASH_SaveContext(HASH_Context* HASH_ContextSave);
|
||||
void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
|
||||
|
||||
/* HASH's DMA interface function **********************************************/
|
||||
void HASH_DMACmd(FunctionalState NewState);
|
||||
|
||||
/* HASH Interrupts and flags management functions *****************************/
|
||||
void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);
|
||||
FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);
|
||||
void HASH_ClearFlag(uint16_t HASH_FLAG);
|
||||
ITStatus HASH_GetITStatus(uint8_t HASH_IT);
|
||||
void HASH_ClearITPendingBit(uint8_t HASH_IT);
|
||||
|
||||
/* High Level SHA1 functions **************************************************/
|
||||
ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
|
||||
ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
|
||||
uint8_t *Input, uint32_t Ilen,
|
||||
uint8_t Output[20]);
|
||||
|
||||
/* High Level MD5 functions ***************************************************/
|
||||
ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
|
||||
ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
|
||||
uint8_t *Input, uint32_t Ilen,
|
||||
uint8_t Output[16]);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_HASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,692 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_I2C_H
|
||||
#define __STM32F4xx_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2) || \
|
||||
((PERIPH) == I2C3))
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
|
||||
((CYCLE) == I2C_DutyCycle_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
|
||||
((STATE) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DR ((uint8_t)0x10)
|
||||
#define I2C_Register_SR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_SR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CCR ((uint8_t)0x1C)
|
||||
#define I2C_Register_TRISE ((uint8_t)0x20)
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_DR) || \
|
||||
((REGISTER) == I2C_Register_SR1) || \
|
||||
((REGISTER) == I2C_Register_SR2) || \
|
||||
((REGISTER) == I2C_Register_CCR) || \
|
||||
((REGISTER) == I2C_Register_TRISE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NACK_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
|
||||
((POSITION) == I2C_NACKPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_SMBus_alert_pin_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
|
||||
((ALERT) == I2C_SMBusAlert_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_PEC_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
|
||||
((POSITION) == I2C_PECPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
|
||||
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
|
||||
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
|
||||
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SR2 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/**
|
||||
* @brief SR1 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
|
||||
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
|
||||
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
|
||||
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
|
||||
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
|
||||
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
|
||||
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
|
||||
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Events
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
===============================================================================
|
||||
I2C Master Events (Events grouped in order of communication)
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Communication start
|
||||
*
|
||||
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||
*
|
||||
*/
|
||||
/* --EV5 */
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/**
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set:
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus. Then master should send the second part of
|
||||
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
|
||||
* should wait for event EV6.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV6 */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/* --EV9 */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_ReceiveData() function).
|
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2.
|
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EV8 is sufficient for the application.
|
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation).
|
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/
|
||||
/* --EV8 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* --EV8_2 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
|
||||
/**
|
||||
===============================================================================
|
||||
I2C Slave Events (Events grouped in order of communication)
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Communication start events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||
* condition on the bus (if the acknowledge feature is enabled through function
|
||||
* I2C_AcknowledgeConfig()) and the events listed above are set :
|
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* 2) Case of Dual address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* 3) Case of General Call enabled for the slave */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked and:
|
||||
*
|
||||
* - Slave RECEIVER mode:
|
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
||||
* used when the user software doesn't guarantee the EV3 is managed before the
|
||||
* current byte end of transfer.
|
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||
* data bytes and expect a Stop condition on the bus.
|
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* --EV4 */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/
|
||||
/* --EV3 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/* --EV3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
/*
|
||||
===============================================================================
|
||||
End of Events Description
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_clock_speed
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the I2C configuration to the default reset state *****/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* PEC management functions ***************************************************/
|
||||
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Interrupts, events and flags management functions **************************/
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
|
||||
/*
|
||||
===============================================================================
|
||||
I2C State Monitoring Functions
|
||||
===============================================================================
|
||||
This I2C driver provides three different ways for I2C state monitoring
|
||||
depending on the application requirements and constraints:
|
||||
|
||||
|
||||
1. Basic state monitoring (Using I2C_CheckEvent() function)
|
||||
-----------------------------------------------------------
|
||||
It compares the status registers (SR1 and SR2) content to a given event
|
||||
(can be the combination of one or more flags).
|
||||
It returns SUCCESS if the current status includes the given flags
|
||||
and returns ERROR if one or more flags are missing in the current status.
|
||||
|
||||
- When to use
|
||||
- This function is suitable for most applications as well as for startup
|
||||
activity since the events are fully described in the product reference
|
||||
manual (RM0090).
|
||||
- It is also suitable for users who need to define their own events.
|
||||
|
||||
- Limitations
|
||||
- If an error occurs (ie. error flags are set besides to the monitored
|
||||
flags), the I2C_CheckEvent() function may return SUCCESS despite
|
||||
the communication hold or corrupted real state.
|
||||
In this case, it is advised to use error interrupts to monitor
|
||||
the error events and handle them in the interrupt IRQ handler.
|
||||
|
||||
Note
|
||||
For error management, it is advised to use the following functions:
|
||||
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||||
- I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||||
Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
|
||||
I2Cx_ER_IRQHandler() function in order to determine which error occurred.
|
||||
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||||
and/or I2C_GenerateStop() in order to clear the error flag and source
|
||||
and return to correct communication status.
|
||||
|
||||
|
||||
2. Advanced state monitoring (Using the function I2C_GetLastEvent())
|
||||
--------------------------------------------------------------------
|
||||
Using the function I2C_GetLastEvent() which returns the image of both status
|
||||
registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||
by 16 bits and concatenated to Status Register 1).
|
||||
|
||||
- When to use
|
||||
- This function is suitable for the same applications above but it
|
||||
allows to overcome the mentioned limitation of I2C_GetFlagStatus()
|
||||
function.
|
||||
- The returned value could be compared to events already defined in
|
||||
this file or to custom values defined by user.
|
||||
This function is suitable when multiple flags are monitored at the
|
||||
same time.
|
||||
- At the opposite of I2C_CheckEvent() function, this function allows
|
||||
user to choose when an event is accepted (when all events flags are
|
||||
set and no other flags are set or just when the needed flags are set
|
||||
like I2C_CheckEvent() function.
|
||||
|
||||
- Limitations
|
||||
- User may need to define his own events.
|
||||
- Same remark concerning the error management is applicable for this
|
||||
function if user decides to check only regular communication flags
|
||||
(and ignores error flags).
|
||||
|
||||
|
||||
3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||
one single flag (ie. I2C_FLAG_RXNE ...).
|
||||
|
||||
- When to use
|
||||
- This function could be used for specific applications or in debug
|
||||
phase.
|
||||
- It is suitable when only one flag checking is needed (most I2C
|
||||
events are monitored through multiple flags).
|
||||
- Limitations:
|
||||
- When calling this function, the Status register is accessed.
|
||||
Some flags are cleared when the status register is accessed.
|
||||
So checking the status of one Flag, may clear other ones.
|
||||
- Function may need to be called twice or more in order to monitor
|
||||
one single event.
|
||||
*/
|
||||
|
||||
/*
|
||||
===============================================================================
|
||||
1. Basic state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||
/*
|
||||
===============================================================================
|
||||
2. Advanced state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/*
|
||||
===============================================================================
|
||||
3. Flag-based state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,125 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_IWDG_H
|
||||
#define __STM32F4xx_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
/* Flag management function ***************************************************/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_IWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,179 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_PWR_H
|
||||
#define __STM32F4xx_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower PWR_CR_LPDS
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/** @defgroup PWR_Regulator_Voltage_Scale
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000)
|
||||
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000)
|
||||
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_BRR PWR_CSR_BRR
|
||||
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
|
||||
|
||||
/** @defgroup PWR_Flag_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
|
||||
((FLAG) == PWR_FLAG_VOSRDY))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the PWR configuration to the default reset state ******/
|
||||
void PWR_DeInit(void);
|
||||
|
||||
/* Backup Domain Access function **********************************************/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||
|
||||
/* PVD configuration functions ************************************************/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||
|
||||
/* Main and Backup Regulators configuration functions *************************/
|
||||
void PWR_BackupRegulatorCmd(FunctionalState NewState);
|
||||
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
|
||||
|
||||
/* FLASH Power Down configuration functions ***********************************/
|
||||
void PWR_FlashPowerDownCmd(FunctionalState NewState);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Flags management functions *************************************************/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_PWR_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,510 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_RCC_H
|
||||
#define __STM32F4xx_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE))
|
||||
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
|
||||
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||
((IT) == RCC_IT_PLLI2SRDY))
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
|
||||
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
|
||||
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
|
||||
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
|
||||
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
|
||||
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
|
||||
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
|
||||
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
|
||||
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
|
||||
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
|
||||
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
|
||||
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
|
||||
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
|
||||
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
|
||||
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
|
||||
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
|
||||
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
|
||||
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
|
||||
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
|
||||
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
|
||||
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
|
||||
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
|
||||
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
|
||||
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
|
||||
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
|
||||
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
|
||||
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
|
||||
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
|
||||
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
|
||||
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
|
||||
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
|
||||
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
|
||||
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
|
||||
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
|
||||
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
|
||||
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
|
||||
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
|
||||
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
|
||||
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
|
||||
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
|
||||
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
|
||||
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
|
||||
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
|
||||
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
|
||||
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
|
||||
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
|
||||
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
|
||||
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
|
||||
((DIV) == RCC_MCO1Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
|
||||
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
|
||||
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
|
||||
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
|
||||
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
|
||||
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
|
||||
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
|
||||
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
|
||||
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
|
||||
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
|
||||
((DIV) == RCC_MCO2Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_BORRST ((uint8_t)0x79)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_PLLI2SRDY))
|
||||
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
|
||||
void RCC_PLLI2SCmd(FunctionalState NewState);
|
||||
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
|
||||
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
|
||||
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,114 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the Random
|
||||
* Number Generator(RNG) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_RNG_H
|
||||
#define __STM32F4xx_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */
|
||||
#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */
|
||||
#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */
|
||||
|
||||
#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
|
||||
((RNG_FLAG) == RNG_FLAG_CECS) || \
|
||||
((RNG_FLAG) == RNG_FLAG_SECS))
|
||||
#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
|
||||
((RNG_FLAG) == RNG_FLAG_SECS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */
|
||||
#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */
|
||||
|
||||
#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the RNG configuration to the default reset state *****/
|
||||
void RNG_DeInit(void);
|
||||
|
||||
/* Configuration function *****************************************************/
|
||||
void RNG_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Get 32 bit Random number function ******************************************/
|
||||
uint32_t RNG_GetRandomNumber(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RNG_ITConfig(FunctionalState NewState);
|
||||
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
|
||||
void RNG_ClearFlag(uint8_t RNG_FLAG);
|
||||
ITStatus RNG_GetITStatus(uint8_t RNG_IT);
|
||||
void RNG_ClearITPendingBit(uint8_t RNG_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_RNG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,875 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_RTC_H
|
||||
#define __STM32F4xx_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7F */
|
||||
|
||||
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7FFF */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be set to a value in the 0-12 range
|
||||
if the RTC_HourFormat_12 is selected or 0-23 range if
|
||||
the RTC_HourFormat_24 is selected. */
|
||||
|
||||
uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t RTC_Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be set to a value in the 1-31 range. */
|
||||
|
||||
uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be set to a value in the 0-99 range. */
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
|
||||
|
||||
uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter
|
||||
must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this
|
||||
parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HourFormat_24 ((uint32_t)0x00000000)
|
||||
#define RTC_HourFormat_12 ((uint32_t)0x00000040)
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
|
||||
((FORMAT) == RTC_HourFormat_24))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_H12_AM ((uint8_t)0x00)
|
||||
#define RTC_H12_PM ((uint8_t)0x40)
|
||||
#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_Month_January ((uint8_t)0x01)
|
||||
#define RTC_Month_February ((uint8_t)0x02)
|
||||
#define RTC_Month_March ((uint8_t)0x03)
|
||||
#define RTC_Month_April ((uint8_t)0x04)
|
||||
#define RTC_Month_May ((uint8_t)0x05)
|
||||
#define RTC_Month_June ((uint8_t)0x06)
|
||||
#define RTC_Month_July ((uint8_t)0x07)
|
||||
#define RTC_Month_August ((uint8_t)0x08)
|
||||
#define RTC_Month_September ((uint8_t)0x09)
|
||||
#define RTC_Month_October ((uint8_t)0x10)
|
||||
#define RTC_Month_November ((uint8_t)0x11)
|
||||
#define RTC_Month_December ((uint8_t)0x12)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_Weekday_Monday ((uint8_t)0x01)
|
||||
#define RTC_Weekday_Tuesday ((uint8_t)0x02)
|
||||
#define RTC_Weekday_Wednesday ((uint8_t)0x03)
|
||||
#define RTC_Weekday_Thursday ((uint8_t)0x04)
|
||||
#define RTC_Weekday_Friday ((uint8_t)0x05)
|
||||
#define RTC_Weekday_Saturday ((uint8_t)0x06)
|
||||
#define RTC_Weekday_Sunday ((uint8_t)0x07)
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
|
||||
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmMask_None ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
|
||||
#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
|
||||
#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
|
||||
#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
|
||||
#define RTC_AlarmMask_All ((uint32_t)0x80808080)
|
||||
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Alarm_A ((uint32_t)0x00000100)
|
||||
#define RTC_Alarm_B ((uint32_t)0x00000200)
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
|
||||
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Wakeup_Timer_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
|
||||
#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
|
||||
#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
|
||||
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
|
||||
#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
|
||||
#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
|
||||
((EDGE) == RTC_TimeStampEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Output_Disable ((uint32_t)0x00000000)
|
||||
#define RTC_Output_AlarmA ((uint32_t)0x00200000)
|
||||
#define RTC_Output_AlarmB ((uint32_t)0x00400000)
|
||||
#define RTC_Output_WakeUp ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
|
||||
((OUTPUT) == RTC_Output_AlarmA) || \
|
||||
((OUTPUT) == RTC_Output_AlarmB) || \
|
||||
((OUTPUT) == RTC_Output_WakeUp))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
|
||||
#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
|
||||
((POL) == RTC_OutputPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Digital_Calibration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
|
||||
#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
|
||||
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
|
||||
((SIGN) == RTC_CalibSign_Negative))
|
||||
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
|
||||
#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
|
||||
((OUTPUT) == RTC_CalibOutput_1Hz))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0].
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0]. */
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
|
||||
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
|
||||
((SAVE) == RTC_DayLightSaving_ADD1H))
|
||||
|
||||
#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
|
||||
((OPERATION) == RTC_StoreOperation_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Trigger_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
|
||||
#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
|
||||
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_HighLevel))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Filter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
|
||||
|
||||
#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
|
||||
consecutive samples at the active leve. */
|
||||
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
|
||||
((FILTER) == RTC_TamperFilter_2Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_4Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_8Sample))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
|
||||
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
|
||||
#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pin_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)
|
||||
#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)
|
||||
#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
|
||||
((PIN) == RTC_TamperPin_PI8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_TimeStamp_Pin_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)
|
||||
#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
|
||||
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
|
||||
((PIN) == RTC_TimeStampPin_PI8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
|
||||
#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
|
||||
((TYPE) == RTC_OutputType_PushPull))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
|
||||
((SEL) == RTC_ShiftAdd1S_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Backup_Registers_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
|
||||
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
|
||||
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
|
||||
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
|
||||
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
|
||||
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
|
||||
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
|
||||
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
|
||||
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
|
||||
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
|
||||
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
|
||||
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
|
||||
#define RTC_BKP_DR16 ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_DR17 ((uint32_t)0x00000011)
|
||||
#define RTC_BKP_DR18 ((uint32_t)0x00000012)
|
||||
#define RTC_BKP_DR19 ((uint32_t)0x00000013)
|
||||
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
|
||||
((BKP) == RTC_BKP_DR1) || \
|
||||
((BKP) == RTC_BKP_DR2) || \
|
||||
((BKP) == RTC_BKP_DR3) || \
|
||||
((BKP) == RTC_BKP_DR4) || \
|
||||
((BKP) == RTC_BKP_DR5) || \
|
||||
((BKP) == RTC_BKP_DR6) || \
|
||||
((BKP) == RTC_BKP_DR7) || \
|
||||
((BKP) == RTC_BKP_DR8) || \
|
||||
((BKP) == RTC_BKP_DR9) || \
|
||||
((BKP) == RTC_BKP_DR10) || \
|
||||
((BKP) == RTC_BKP_DR11) || \
|
||||
((BKP) == RTC_BKP_DR12) || \
|
||||
((BKP) == RTC_BKP_DR13) || \
|
||||
((BKP) == RTC_BKP_DR14) || \
|
||||
((BKP) == RTC_BKP_DR15) || \
|
||||
((BKP) == RTC_BKP_DR16) || \
|
||||
((BKP) == RTC_BKP_DR17) || \
|
||||
((BKP) == RTC_BKP_DR18) || \
|
||||
((BKP) == RTC_BKP_DR19))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Format_BIN ((uint32_t)0x000000000)
|
||||
#define RTC_Format_BCD ((uint32_t)0x000000001)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
|
||||
((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
|
||||
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
|
||||
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
|
||||
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
|
||||
((FLAG) == RTC_FLAG_SHPF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_IT_WUT ((uint32_t)0x00004000)
|
||||
#define RTC_IT_ALRB ((uint32_t)0x00002000)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
|
||||
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
|
||||
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
|
||||
((IT) == RTC_IT_TAMP1))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
|
||||
#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_WriteProtectionCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
|
||||
void RTC_BypassShadowCmd(FunctionalState NewState);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
uint32_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
|
||||
/* Alarms (Alarm A and Alarm B) configuration functions **********************/
|
||||
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
|
||||
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
|
||||
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
|
||||
|
||||
/* WakeUp Timer configuration functions ***************************************/
|
||||
void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
|
||||
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
|
||||
uint32_t RTC_GetWakeUpCounter(void);
|
||||
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
|
||||
uint32_t RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
|
||||
|
||||
/* Digital Calibration configuration functions *********************************/
|
||||
ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
|
||||
ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
|
||||
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
|
||||
uint32_t RTC_SmoothCalibPlusPulses,
|
||||
uint32_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* TimeStamp configuration functions ******************************************/
|
||||
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
|
||||
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
|
||||
RTC_DateTypeDef* RTC_StampDateStruct);
|
||||
uint32_t RTC_GetTimeStampSubSecond(void);
|
||||
|
||||
/* Tampers configuration functions ********************************************/
|
||||
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
|
||||
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
|
||||
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
|
||||
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
|
||||
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
|
||||
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
|
||||
void RTC_TamperPullUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Backup Data Registers configuration functions ******************************/
|
||||
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
|
||||
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
|
||||
|
||||
/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
|
||||
functions ******************************************************************/
|
||||
void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
|
||||
void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
|
||||
void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
|
||||
|
||||
/* RTC_Shift_control_synchonisation_functions *********************************/
|
||||
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
|
||||
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint32_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint32_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint32_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_RTC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,530 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_sdio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the SDIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_SDIO_H
|
||||
#define __STM32F4xx_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||
|
||||
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
|
||||
enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||
|
||||
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
|
||||
disabled when the bus is idle.
|
||||
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||
|
||||
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
|
||||
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||
|
||||
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||
|
||||
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a value between 0x00 and 0xFF. */
|
||||
|
||||
} SDIO_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
|
||||
to a card as part of a command message. If a command
|
||||
contains an argument, it must be loaded into this register
|
||||
before writing the command to the command register */
|
||||
|
||||
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
|
||||
|
||||
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
|
||||
This parameter can be a value of @ref SDIO_Response_Type */
|
||||
|
||||
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||
|
||||
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||
} SDIO_CmdInitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
|
||||
|
||||
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
|
||||
|
||||
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
|
||||
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||
|
||||
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
|
||||
is a read or write.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||
|
||||
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||
|
||||
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||
} SDIO_DataInitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Edge
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
|
||||
((EDGE) == SDIO_ClockEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Bypass
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
|
||||
((BYPASS) == SDIO_ClockBypass_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Power_Save
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
|
||||
((SAVE) == SDIO_ClockPowerSave_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Bus_Wide
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
|
||||
((WIDE) == SDIO_BusWide_8b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
|
||||
((CONTROL) == SDIO_HardwareFlowControl_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Power_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SDIO_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Command_Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
|
||||
((RESPONSE) == SDIO_Response_Short) || \
|
||||
((RESPONSE) == SDIO_Response_Long))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Wait_Interrupt_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
|
||||
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
|
||||
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
|
||||
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
|
||||
((WAIT) == SDIO_Wait_Pend))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_CPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
|
||||
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Block_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_32b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_64b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_128b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_256b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_512b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_1024b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2048b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4096b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8192b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16384b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
|
||||
((DIR) == SDIO_TransferDir_ToSDIO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
|
||||
((MODE) == SDIO_TransferMode_Block))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_DPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_TXUNDERR) || \
|
||||
((FLAG) == SDIO_FLAG_RXOVERR) || \
|
||||
((FLAG) == SDIO_FLAG_CMDREND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDSENT) || \
|
||||
((FLAG) == SDIO_FLAG_DATAEND) || \
|
||||
((FLAG) == SDIO_FLAG_STBITERR) || \
|
||||
((FLAG) == SDIO_FLAG_DBCKEND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXACT) || \
|
||||
((FLAG) == SDIO_FLAG_RXACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_TXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_RXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_SDIOIT) || \
|
||||
((FLAG) == SDIO_FLAG_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
||||
|
||||
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
|
||||
((IT) == SDIO_IT_DCRCFAIL) || \
|
||||
((IT) == SDIO_IT_CTIMEOUT) || \
|
||||
((IT) == SDIO_IT_DTIMEOUT) || \
|
||||
((IT) == SDIO_IT_TXUNDERR) || \
|
||||
((IT) == SDIO_IT_RXOVERR) || \
|
||||
((IT) == SDIO_IT_CMDREND) || \
|
||||
((IT) == SDIO_IT_CMDSENT) || \
|
||||
((IT) == SDIO_IT_DATAEND) || \
|
||||
((IT) == SDIO_IT_STBITERR) || \
|
||||
((IT) == SDIO_IT_DBCKEND) || \
|
||||
((IT) == SDIO_IT_CMDACT) || \
|
||||
((IT) == SDIO_IT_TXACT) || \
|
||||
((IT) == SDIO_IT_RXACT) || \
|
||||
((IT) == SDIO_IT_TXFIFOHE) || \
|
||||
((IT) == SDIO_IT_RXFIFOHF) || \
|
||||
((IT) == SDIO_IT_TXFIFOF) || \
|
||||
((IT) == SDIO_IT_RXFIFOF) || \
|
||||
((IT) == SDIO_IT_TXFIFOE) || \
|
||||
((IT) == SDIO_IT_RXFIFOE) || \
|
||||
((IT) == SDIO_IT_TXDAVL) || \
|
||||
((IT) == SDIO_IT_RXDAVL) || \
|
||||
((IT) == SDIO_IT_SDIOIT) || \
|
||||
((IT) == SDIO_IT_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Read_Wait_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
|
||||
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
|
||||
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
|
||||
((MODE) == SDIO_ReadWaitMode_DATA2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Function used to set the SDIO configuration to the default reset state ****/
|
||||
void SDIO_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ClockCmd(FunctionalState NewState);
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||
uint32_t SDIO_GetPowerState(void);
|
||||
|
||||
/* Command path state machine (CPSM) management functions *********************/
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||
uint8_t SDIO_GetCommandResponse(void);
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||
|
||||
/* Data path state machine (DPSM) management functions ************************/
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
uint32_t SDIO_GetDataCounter(void);
|
||||
uint32_t SDIO_ReadData(void);
|
||||
void SDIO_WriteData(uint32_t Data);
|
||||
uint32_t SDIO_GetFIFOCount(void);
|
||||
|
||||
/* SDIO IO Cards mode management functions ************************************/
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||
|
||||
/* CE-ATA mode management functions *******************************************/
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SDIO_DMACmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_SDIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,537 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the SPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_SPI_H
|
||||
#define __STM32F4xx_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
|
||||
((DATASIZE) == SPI_DataSize_8b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx)|| \
|
||||
((MODE) == I2S_Mode_MasterRx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)
|
||||
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||
|
||||
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
|
||||
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
|
||||
((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
|
||||
((IT) == SPI_I2S_IT_TIFRFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)
|
||||
|
||||
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
|
||||
((FLAG) == SPI_I2S_FLAG_TIFRFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
|
||||
#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
|
||||
#define SPI_IT_TXE SPI_I2S_IT_TXE
|
||||
#define SPI_IT_RXNE SPI_I2S_IT_RXNE
|
||||
#define SPI_IT_ERR SPI_I2S_IT_ERR
|
||||
#define SPI_IT_OVR SPI_I2S_IT_OVR
|
||||
#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
|
||||
#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
|
||||
#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
|
||||
#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
|
||||
#define SPI_DeInit SPI_I2S_DeInit
|
||||
#define SPI_ITConfig SPI_I2S_ITConfig
|
||||
#define SPI_DMACmd SPI_I2S_DMACmd
|
||||
#define SPI_SendData SPI_I2S_SendData
|
||||
#define SPI_ReceiveData SPI_I2S_ReceiveData
|
||||
#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
|
||||
#define SPI_ClearFlag SPI_I2S_ClearFlag
|
||||
#define SPI_GetITStatus SPI_I2S_GetITStatus
|
||||
#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the SPI configuration to the default reset state *****/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
|
||||
void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,173 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_SYSCFG_H
|
||||
#define __STM32F4xx_SYSCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
|
||||
#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
|
||||
#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
|
||||
#define EXTI_PortSourceGPIOI ((uint8_t)0x08)
|
||||
|
||||
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Pin_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PinSource0 ((uint8_t)0x00)
|
||||
#define EXTI_PinSource1 ((uint8_t)0x01)
|
||||
#define EXTI_PinSource2 ((uint8_t)0x02)
|
||||
#define EXTI_PinSource3 ((uint8_t)0x03)
|
||||
#define EXTI_PinSource4 ((uint8_t)0x04)
|
||||
#define EXTI_PinSource5 ((uint8_t)0x05)
|
||||
#define EXTI_PinSource6 ((uint8_t)0x06)
|
||||
#define EXTI_PinSource7 ((uint8_t)0x07)
|
||||
#define EXTI_PinSource8 ((uint8_t)0x08)
|
||||
#define EXTI_PinSource9 ((uint8_t)0x09)
|
||||
#define EXTI_PinSource10 ((uint8_t)0x0A)
|
||||
#define EXTI_PinSource11 ((uint8_t)0x0B)
|
||||
#define EXTI_PinSource12 ((uint8_t)0x0C)
|
||||
#define EXTI_PinSource13 ((uint8_t)0x0D)
|
||||
#define EXTI_PinSource14 ((uint8_t)0x0E)
|
||||
#define EXTI_PinSource15 ((uint8_t)0x0F)
|
||||
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
|
||||
((PINSOURCE) == EXTI_PinSource1) || \
|
||||
((PINSOURCE) == EXTI_PinSource2) || \
|
||||
((PINSOURCE) == EXTI_PinSource3) || \
|
||||
((PINSOURCE) == EXTI_PinSource4) || \
|
||||
((PINSOURCE) == EXTI_PinSource5) || \
|
||||
((PINSOURCE) == EXTI_PinSource6) || \
|
||||
((PINSOURCE) == EXTI_PinSource7) || \
|
||||
((PINSOURCE) == EXTI_PinSource8) || \
|
||||
((PINSOURCE) == EXTI_PinSource9) || \
|
||||
((PINSOURCE) == EXTI_PinSource10) || \
|
||||
((PINSOURCE) == EXTI_PinSource11) || \
|
||||
((PINSOURCE) == EXTI_PinSource12) || \
|
||||
((PINSOURCE) == EXTI_PinSource13) || \
|
||||
((PINSOURCE) == EXTI_PinSource14) || \
|
||||
((PINSOURCE) == EXTI_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_Memory_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
|
||||
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
|
||||
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_FSMC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_ETHERNET_Media_Interface
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
|
||||
#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
|
||||
|
||||
#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
|
||||
((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void SYSCFG_DeInit(void);
|
||||
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
|
||||
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
|
||||
void SYSCFG_CompensationCellCmd(FunctionalState NewState);
|
||||
FlagStatus SYSCFG_GetCompensationCellStatus(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,423 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_USART_H
|
||||
#define __STM32F4xx_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
|
||||
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
|
||||
|
||||
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5) || \
|
||||
((PERIPH) == USART6))
|
||||
|
||||
#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == USART6))
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_0_5) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
|
||||
/** @defgroup USART_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define USART_IT_ORE USART_IT_ORE_ER
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
|
||||
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the USART configuration to the default reset state ***/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,105 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file contains all the functions prototypes for the WWDG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_WWDG_H
|
||||
#define __STM32F4xx_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the WWDG configuration to the default reset state ****/
|
||||
void WWDG_DeInit(void);
|
||||
|
||||
/* Prescaler, Refresh window and Counter configuration functions **************/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation function ***************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,243 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to configure Interrupts using driver
|
||||
* ===================================================================
|
||||
*
|
||||
* This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
* The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
*
|
||||
* 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
|
||||
* function according to the following table.
|
||||
|
||||
* The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
* to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
* ==========================================================================================================================
|
||||
* NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
* ==========================================================================================================================
|
||||
* NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
* | | | 4 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
* | | | 3 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
* | | | 2 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
* | | | 1 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
* | | | 0 bits for subpriority
|
||||
* ==========================================================================================================================
|
||||
*
|
||||
* 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
|
||||
*
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
*
|
||||
* @note IRQ priority order (sorted by highest to lowest priority):
|
||||
* - Lowest pre-emption priority
|
||||
* - Lowest subpriority
|
||||
* - Lowest hardware priority (IRQ number)
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
|
||||
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
|
||||
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
|
||||
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
|
||||
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,306 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* - Initialization and Configuration
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* EXTI features
|
||||
* ===================================================================
|
||||
*
|
||||
* External interrupt/event lines are mapped as following:
|
||||
* 1- All available GPIO pins are connected to the 16 external
|
||||
* interrupt/event lines from EXTI0 to EXTI15.
|
||||
* 2- EXTI line 16 is connected to the PVD Output
|
||||
* 3- EXTI line 17 is connected to the RTC Alarm event
|
||||
* 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
|
||||
* 5- EXTI line 19 is connected to the Ethernet Wakeup event
|
||||
* 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
|
||||
* 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events
|
||||
* 8- EXTI line 22 is connected to the RTC Wakeup event
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
*
|
||||
* In order to use an I/O pin as an external interrupt source, follow
|
||||
* steps below:
|
||||
* 1- Configure the I/O in input mode using GPIO_Init()
|
||||
* 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
|
||||
* 3- Select the mode(interrupt, event) and configure the trigger
|
||||
* selection (Rising, falling or both) using EXTI_Init()
|
||||
* 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
|
||||
*
|
||||
* @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
|
||||
* registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_exti.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x00000000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x007FFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
|
||||
* will be generated.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group2 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be EXTI_Linex where x can be(0..22)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be EXTI_Linex where x can be(0..22)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,561 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* - Initialization and Configuration
|
||||
* - GPIO Read and Write
|
||||
* - GPIO Alternate functions configuration
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Enable the GPIO AHB clock using the following function
|
||||
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
|
||||
*
|
||||
* 2. Configure the GPIO pin(s) using GPIO_Init()
|
||||
* Four possible configuration are available for each pin:
|
||||
* - Input: Floating, Pull-up, Pull-down.
|
||||
* - Output: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
* Open Drain (Pull-up, Pull-down or no Pull).
|
||||
* In output mode, the speed is configurable: 2 MHz, 25 MHz,
|
||||
* 50 MHz or 100 MHz.
|
||||
* - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
* Open Drain (Pull-up, Pull-down or no Pull).
|
||||
* - Analog: required mode when a pin is to be used as ADC channel
|
||||
* or DAC output.
|
||||
*
|
||||
* 3- Peripherals alternate function:
|
||||
* - For ADC and DAC, configure the desired pin in analog mode using
|
||||
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
|
||||
* - For other peripherals (TIM, USART...):
|
||||
* - Connect the pin to the desired peripherals' Alternate
|
||||
* Function (AF) using GPIO_PinAFConfig() function
|
||||
* - Configure the desired pin in alternate function mode using
|
||||
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
* - Select the type, pull-up/pull-down and output speed via
|
||||
* GPIO_PuPd, GPIO_OType and GPIO_Speed members
|
||||
* - Call GPIO_Init() function
|
||||
*
|
||||
* 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
*
|
||||
* 5. To set/reset the level of a pin configured in output mode use
|
||||
* GPIO_SetBits()/GPIO_ResetBits()
|
||||
*
|
||||
* 6. During and just after reset, the alternate functions are not
|
||||
* active and the GPIO pins are configured in input floating mode
|
||||
* (except JTAG pins).
|
||||
*
|
||||
* 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
|
||||
* general-purpose (PC14 and PC15, respectively) when the LSE
|
||||
* oscillator is off. The LSE has priority over the GPIO function.
|
||||
*
|
||||
* 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
* general-purpose PH0 and PH1, respectively, when the HSE
|
||||
* oscillator is off. The HSE has priority over the GPIO function.
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOH)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOI)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/* -------------------------Configure the port pins---------------- */
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
GPIO Read and Write
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRH = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins..
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
|
||||
* @brief GPIO Alternate functions configuration function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
GPIO Alternate functions configuration function
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AFSelection: selects the pin to used as Alternate function.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
|
||||
* @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
|
||||
* @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
|
||||
* @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
|
||||
* @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
|
||||
* @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
|
||||
* @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
|
||||
* @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
|
||||
* @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
|
||||
* @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
|
||||
* @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
|
||||
* @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
|
||||
* @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
|
||||
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
|
||||
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
|
||||
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
|
||||
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
|
||||
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
|
||||
* @arg GPIO_AF_USART2: Connect USART2 pins to AF7
|
||||
* @arg GPIO_AF_USART3: Connect USART3 pins to AF7
|
||||
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8
|
||||
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8
|
||||
* @arg GPIO_AF_USART6: Connect USART6 pins to AF8
|
||||
* @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
|
||||
* @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
|
||||
* @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
|
||||
* @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
|
||||
* @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
|
||||
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
|
||||
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
|
||||
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
|
||||
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
|
||||
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
|
||||
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
|
||||
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
|
||||
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,197 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_syscfg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
*
|
||||
* This driver provides functions for:
|
||||
*
|
||||
* 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
|
||||
*
|
||||
* 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
|
||||
*
|
||||
* 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
|
||||
*
|
||||
* @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
|
||||
* using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_syscfg.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG
|
||||
* @brief SYSCFG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* ------------ RCC registers bit address in the alias region ----------- */
|
||||
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
|
||||
/* --- PMC Register ---*/
|
||||
/* Alias word address of MII_RMII_SEL bit */
|
||||
#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
|
||||
#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
|
||||
#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
|
||||
|
||||
/* --- CMPCR Register ---*/
|
||||
/* Alias word address of CMP_PD bit */
|
||||
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
|
||||
#define CMP_PD_BitNumber ((uint8_t)0x00)
|
||||
#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
|
||||
* registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_DeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param SYSCFG_Memory: selects the memory remapping.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
|
||||
|
||||
SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
|
||||
* EXTI lines where x can be (A..I).
|
||||
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
|
||||
* This parameter can be EXTI_PinSourcex where x can be (0..15, except
|
||||
* for EXTI_PortSourceGPIOI x can be (0..11).
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
|
||||
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the ETHERNET media interface
|
||||
* @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
|
||||
* @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
|
||||
{
|
||||
assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
|
||||
/* Configure MII_RMII selection bit */
|
||||
*(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @param NewState: new state of the I/O Compensation Cell.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ENABLE: I/O compensation cell enabled
|
||||
* @arg DISABLE: I/O compensation cell power-down mode
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_CompensationCellCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the I/O Compensation Cell ready flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
|
||||
*/
|
||||
FlagStatus SYSCFG_GetCompensationCellStatus(void)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,113 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Simple GPIO (parallel port) IO routines.
|
||||
*-----------------------------------------------------------*/
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Standard demo include. */
|
||||
#include "partest.h"
|
||||
|
||||
/* Starter kit includes. */
|
||||
#include "iar_stm32f407zg_sk.h"
|
||||
|
||||
/* Only the LEDs on one of the two seven segment displays are used. */
|
||||
#define partstMAX_LEDS 4
|
||||
|
||||
static const Led_TypeDef xLEDs[ partstMAX_LEDS ] = { LED1, LED2, LED3, LED4 };
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestInitialise( void )
|
||||
{
|
||||
/* Initialise all four LEDs that are built onto the starter kit. */
|
||||
STM_EVAL_LEDInit( LED1 );
|
||||
STM_EVAL_LEDInit( LED2 );
|
||||
STM_EVAL_LEDInit( LED3 );
|
||||
STM_EVAL_LEDInit( LED4 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )
|
||||
{
|
||||
if( ulLED < partstMAX_LEDS )
|
||||
{
|
||||
if( xValue == pdTRUE )
|
||||
{
|
||||
STM_EVAL_LEDOn( xLEDs[ ulLED ] );
|
||||
}
|
||||
else
|
||||
{
|
||||
STM_EVAL_LEDOff( xLEDs[ ulLED ] );
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestToggleLED( unsigned long ulLED )
|
||||
{
|
||||
if( ulLED < partstMAX_LEDS )
|
||||
{
|
||||
taskENTER_CRITICAL();
|
||||
{
|
||||
STM_EVAL_LEDToggle( xLEDs[ ulLED ] );
|
||||
}
|
||||
taskEXIT_CRITICAL();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -0,0 +1,961 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<project>
|
||||
<fileVersion>2</fileVersion>
|
||||
<configuration>
|
||||
<name>Flash Debug</name>
|
||||
<toolchain>
|
||||
<name>ARM</name>
|
||||
</toolchain>
|
||||
<debug>1</debug>
|
||||
<settings>
|
||||
<name>C-SPY</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>23</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CInput</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CEndian</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCVariant</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacFile</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MemOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32f4xxx.ddf</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToName</name>
|
||||
<state>main</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CExtraOptionsCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CExtraOptions</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CFpuProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDDFArgumentProducer</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDownloadSuppressDownload</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDownloadVerifyAll</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCProductVersion</name>
|
||||
<state>5.30.0.51236</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDynDriverList</name>
|
||||
<state>JLINK_ID</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCLastSavedByProductVersion</name>
|
||||
<state>6.30.3.53229</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDownloadAttachToProgram</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UseFlashLoader</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CLowLevel</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCBE8Slave</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacFile2</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CDevice</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoadersV3</name>
|
||||
<state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F4xxx.board</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck1</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesPath1</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck2</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesPath2</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesSuppressCheck3</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesPath3</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OverrideDefFlashBoard</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesOffset1</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesOffset2</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesOffset3</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesUse1</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesUse2</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCImagesUse3</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDeviceConfigMacroFile</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>ARMSIM_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>1</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCSimDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCSimEnablePSP</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCSimPspOverrideConfig</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCSimPspConfigFile</name>
|
||||
<state></state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>ANGEL_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CCAngelHeartbeat</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CAngelCommunication</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CAngelCommBaud</name>
|
||||
<version>0</version>
|
||||
<state>3</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CAngelCommPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ANGELTCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoAngelLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AngelLogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>GDBSERVER_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>TCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>LogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJTagBreakpointRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJTagDoUpdateBreakpoints</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJTagUpdateBreakpoints</name>
|
||||
<state>main</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>IARROM_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>1</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CRomLogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomLogFileEditB</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomCommPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomCommBaud</name>
|
||||
<version>0</version>
|
||||
<state>7</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>JLINK_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>14</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>JLinkSpeed</name>
|
||||
<state>32</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkDoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkLogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkHWResetDelay</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>JLinkInitialSpeed</name>
|
||||
<state>32</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDoJlinkMultiTarget</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCScanChainNonARMDevices</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkMultiTarget</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkIRLength</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkCommRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkTCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkSpeedRadioV2</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCUSBDevice</name>
|
||||
<version>1</version>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchUndef</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchSWI</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchData</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchPrefetch</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchIRQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchFIQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkBreakpointRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkDoUpdateBreakpoints</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkUpdateBreakpoints</name>
|
||||
<state>main</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkInterfaceRadio</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCJLinkAttachSlave</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkResetList</name>
|
||||
<version>6</version>
|
||||
<state>7</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkInterfaceCmdLine</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchCORERESET</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchMMERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchNOCPERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchCHRERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchSTATERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchBUSERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchINTERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchHARDERR</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCatchDummy</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCJLinkScriptFile</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkUsbSerialNo</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCTcpIpAlt</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkTcpIpSerialNo</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCpuClockEdit</name>
|
||||
<state>120.0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockAuto</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockEdit</name>
|
||||
<state>2000</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCJLinkTraceSource</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCJLinkTraceSourceDummy</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>LMIFTDI_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>2</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>LmiftdiSpeed</name>
|
||||
<state>500</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLmiftdiDoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLmiftdiLogFile</name>
|
||||
<state>$PROJ_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLmiFtdiInterfaceRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLmiFtdiInterfaceCmdLine</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>MACRAIGOR_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>3</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>jtag</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>EmuSpeed</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>TCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>LogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoEmuMultiTarget</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>EmuMultiTarget</name>
|
||||
<state>0@ARM7TDMI</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>EmuHWReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CEmuCommBaud</name>
|
||||
<version>0</version>
|
||||
<state>4</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CEmuCommPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>jtago</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UnusedAddr</name>
|
||||
<state>0x00800000</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCMacraigorHWResetDelay</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJTagBreakpointRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJTagDoUpdateBreakpoints</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJTagUpdateBreakpoints</name>
|
||||
<state>main</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCMacraigorInterfaceRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCMacraigorInterfaceCmdLine</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>PEMICRO_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCPEMicroAttachSlave</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroInterfaceList</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroResetDelay</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroJtagSpeed</name>
|
||||
<state>#UNINITIALIZED#</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJPEMicroShowSettings</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>LogFile</name>
|
||||
<state>$PROJ_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroUSBDevice</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroSerialPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJPEMicroTCPIPAutoScanNetwork</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroTCPIP</name>
|
||||
<state>10.0.0.1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPEMicroCommCmdLineProducer</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>RDI_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>2</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CRDIDriverDll</name>
|
||||
<state>Browse to your RDI driver</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRDILogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRDILogFileEdit</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDIHWReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchUndef</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchSWI</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchData</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchPrefetch</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchIRQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchFIQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>RDIJTAGJET_ID</name>
|
||||
<archiveVersion>0</archiveVersion>
|
||||
<data>
|
||||
<version>1</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CRDILogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRDILogFileEdit</name>
|
||||
<state>$PROJ_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDIHWReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchUndef</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchSWI</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchData</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchPrefetch</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchIRQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchFIQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>JTAGjetConfigure</name>
|
||||
<state></state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>STLINK_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>2</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSTLinkInterfaceRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSTLinkInterfaceCmdLine</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSTLinkResetList</name>
|
||||
<version>1</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCpuClockEdit</name>
|
||||
<state>120.0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockAuto</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSwoClockEdit</name>
|
||||
<state>2000</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>THIRDPARTY_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CThirdPartyDriverDll</name>
|
||||
<state>Browse to your third-party driver</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CThirdPartyLogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CThirdPartyLogFileEditB</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>XDS100_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCXDS100AttachSlave</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<debuggerPlugins>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
|
||||
<loadFlag>1</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
|
||||
<loadFlag>1</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
|
||||
<loadFlag>1</loadFlag>
|
||||
</plugin>
|
||||
</debuggerPlugins>
|
||||
</configuration>
|
||||
</project>
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,18 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\RTOSDemo.ewp</path>
|
||||
</project>
|
||||
<batchBuild>
|
||||
<batchDefinition>
|
||||
<name>All</name>
|
||||
<member>
|
||||
<project>RTOSDemo</project>
|
||||
<configuration>Flash Debug</configuration>
|
||||
</member>
|
||||
</batchDefinition>
|
||||
</batchBuild>
|
||||
</workspace>
|
||||
|
||||
|
||||
@ -0,0 +1,506 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
#include <FreeRTOSConfig.h>
|
||||
|
||||
|
||||
RSEG CODE:CODE(2)
|
||||
thumb
|
||||
|
||||
EXTERN ulRegTest1LoopCounter
|
||||
EXTERN ulRegTest2LoopCounter
|
||||
|
||||
PUBLIC vRegTest1Task
|
||||
PUBLIC vRegTest2Task
|
||||
PUBLIC vRegTestClearFlopRegistersToParameterValue
|
||||
PUBLIC ulRegTestCheckFlopRegistersContainParameterValue
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vRegTest1Task
|
||||
|
||||
/* Fill the core registers with known values. */
|
||||
mov r0, #100
|
||||
mov r1, #101
|
||||
mov r2, #102
|
||||
mov r3, #103
|
||||
mov r4, #104
|
||||
mov r5, #105
|
||||
mov r6, #106
|
||||
mov r7, #107
|
||||
mov r8, #108
|
||||
mov r9, #109
|
||||
mov r10, #110
|
||||
mov r11, #111
|
||||
mov r12, #112
|
||||
|
||||
/* Fill the VFP registers with known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg1_loop:
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg1_loopf_pass
|
||||
|
||||
reg1_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg1_error_loopf
|
||||
|
||||
reg1_loopf_pass
|
||||
|
||||
cmp r0, #100
|
||||
bne reg1_error_loop
|
||||
cmp r1, #101
|
||||
bne reg1_error_loop
|
||||
cmp r2, #102
|
||||
bne reg1_error_loop
|
||||
cmp r3, #103
|
||||
bne reg1_error_loop
|
||||
cmp r4, #104
|
||||
bne reg1_error_loop
|
||||
cmp r5, #105
|
||||
bne reg1_error_loop
|
||||
cmp r6, #106
|
||||
bne reg1_error_loop
|
||||
cmp r7, #107
|
||||
bne reg1_error_loop
|
||||
cmp r8, #108
|
||||
bne reg1_error_loop
|
||||
cmp r9, #109
|
||||
bne reg1_error_loop
|
||||
cmp r10, #110
|
||||
bne reg1_error_loop
|
||||
cmp r11, #111
|
||||
bne reg1_error_loop
|
||||
cmp r12, #112
|
||||
bne reg1_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest1LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg1_loop
|
||||
|
||||
reg1_error_loop:
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg1_error_loop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
vRegTest2Task
|
||||
|
||||
/* Set all the core registers to known values. */
|
||||
mov r0, #-1
|
||||
mov r1, #1
|
||||
mov r2, #2
|
||||
mov r3, #3
|
||||
mov r4, #4
|
||||
mov r5, #5
|
||||
mov r6, #6
|
||||
mov r7, #7
|
||||
mov r8, #8
|
||||
mov r9, #9
|
||||
mov r10, #10
|
||||
mov r11, #11
|
||||
mov r12, #12
|
||||
|
||||
/* Set all the VFP to known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg2_loop:
|
||||
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg2_loopf_pass
|
||||
|
||||
reg2_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg2_error_loopf
|
||||
|
||||
reg2_loopf_pass
|
||||
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loop
|
||||
cmp r1, #1
|
||||
bne reg2_error_loop
|
||||
cmp r2, #2
|
||||
bne reg2_error_loop
|
||||
cmp r3, #3
|
||||
bne reg2_error_loop
|
||||
cmp r4, #4
|
||||
bne reg2_error_loop
|
||||
cmp r5, #5
|
||||
bne reg2_error_loop
|
||||
cmp r6, #6
|
||||
bne reg2_error_loop
|
||||
cmp r7, #7
|
||||
bne reg2_error_loop
|
||||
cmp r8, #8
|
||||
bne reg2_error_loop
|
||||
cmp r9, #9
|
||||
bne reg2_error_loop
|
||||
cmp r10, #10
|
||||
bne reg2_error_loop
|
||||
cmp r11, #11
|
||||
bne reg2_error_loop
|
||||
cmp r12, #12
|
||||
bne reg2_error_loop
|
||||
|
||||
/* Increment the loop counter to indicate this test is still functioning
|
||||
correctly. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest2LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg2_loop
|
||||
|
||||
reg2_error_loop:
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
This loop ensures the loop counter variable stops incrementing. */
|
||||
b reg2_error_loop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vRegTestClearFlopRegistersToParameterValue
|
||||
|
||||
/* Clobber the auto saved registers. */
|
||||
vmov d0, r0, r0
|
||||
vmov d1, r0, r0
|
||||
vmov d2, r0, r0
|
||||
vmov d3, r0, r0
|
||||
vmov d4, r0, r0
|
||||
vmov d5, r0, r0
|
||||
vmov d6, r0, r0
|
||||
vmov d7, r0, r0
|
||||
bx lr
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
ulRegTestCheckFlopRegistersContainParameterValue
|
||||
|
||||
vmov r1, s0
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s1
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s2
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s3
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s4
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s5
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s6
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s7
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s8
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s9
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s10
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s11
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s12
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s13
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s14
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s15
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
|
||||
return_pass
|
||||
mov r0, #1
|
||||
bx lr
|
||||
|
||||
return_error
|
||||
mov r0, #0
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
||||
@ -0,0 +1,172 @@
|
||||
/***************************************************************************
|
||||
**
|
||||
** Common definition for IAR EW ARM
|
||||
**
|
||||
** Used with ARM IAR C/C++ Compiler and Assembler.
|
||||
**
|
||||
** (c) Copyright IAR Systems 2006
|
||||
**
|
||||
** $Revision: 48478 $
|
||||
**
|
||||
***************************************************************************/
|
||||
#include <intrinsics.h>
|
||||
|
||||
#ifndef __ARM_COMM_DEF_H
|
||||
#define __ARM_COMM_DEF_H
|
||||
|
||||
#define MHZ *1000000l
|
||||
#define KHZ *1000l
|
||||
#define HZ *1l
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (1 == 0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1 == 1)
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void*)0)
|
||||
#endif
|
||||
|
||||
typedef double Flo64; // Double precision floating point
|
||||
typedef double * pFlo64;
|
||||
typedef float Flo32; // Single precision floating point
|
||||
typedef float * pFlo32;
|
||||
typedef signed long long Int64S; // Signed 64 bit quantity
|
||||
typedef signed long long * pInt64S;
|
||||
typedef unsigned long long Int64U; // Unsigned 64 bit quantity
|
||||
typedef unsigned long long * pInt64U;
|
||||
typedef signed int Int32S; // Signed 32 bit quantity
|
||||
typedef signed int * pInt32S;
|
||||
typedef unsigned int Int32U; // Unsigned 32 bit quantity
|
||||
typedef unsigned int * pInt32U;
|
||||
typedef signed short Int16S; // Signed 16 bit quantity
|
||||
typedef signed short * pInt16S;
|
||||
typedef unsigned short Int16U; // Unsigned 16 bit quantity
|
||||
typedef unsigned short * pInt16U;
|
||||
typedef signed char Int8S; // Signed 8 bit quantity
|
||||
typedef signed char * pInt8S;
|
||||
typedef unsigned char Int8U; // Unsigned 8 bit quantity
|
||||
typedef unsigned char * pInt8U;
|
||||
typedef unsigned int Boolean; // Boolean
|
||||
typedef unsigned int * pBoolean;
|
||||
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#define _2BL(a) (Int8U)(a),(Int8U)(a>>8)
|
||||
#define _2BB(a) (Int8U)(a>>8),(Int8U)(a),
|
||||
#define _3BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16)
|
||||
#define _3BB(a) (Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)
|
||||
#define _4BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16),(Int8U)(a>>24)
|
||||
#define _4BB(a) (Int8U)(a>>24),(Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)
|
||||
|
||||
typedef void * (*CommUserFpnt_t)(void *);
|
||||
typedef void (*VoidFpnt_t)(void);
|
||||
|
||||
// Atomic exchange of data between a memory cell and a register
|
||||
// return value of the memory cell
|
||||
#if __CORE__ < 7
|
||||
inline __arm Int32U AtomicExchange (Int32U State, pInt32U Flag)
|
||||
{
|
||||
asm("swp r0, r0, [r1]");
|
||||
return(State);
|
||||
}
|
||||
|
||||
#define IRQ_FLAG 0x80
|
||||
#define FIQ_FLAG 0x40
|
||||
|
||||
inline __arm Int32U EntrCritSection(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
tmp = __get_CPSR();
|
||||
__set_CPSR(tmp | IRQ_FLAG);
|
||||
return(tmp);
|
||||
}
|
||||
|
||||
inline __arm void ExtCritSection(Int32U Save)
|
||||
{
|
||||
unsigned long tmp;
|
||||
tmp = __get_CPSR();
|
||||
__set_CPSR(tmp & (Save | ~IRQ_FLAG));
|
||||
}
|
||||
|
||||
inline __arm Int32U EntrCritSectionFiq(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
tmp = __get_CPSR();
|
||||
__set_CPSR(tmp | (IRQ_FLAG | FIQ_FLAG));
|
||||
return(tmp);
|
||||
}
|
||||
|
||||
inline __arm void ExtCritSectionFiq(Int32U Save)
|
||||
{
|
||||
unsigned long tmp;
|
||||
tmp = __get_CPSR();
|
||||
__set_CPSR(tmp & (Save | ~(IRQ_FLAG | FIQ_FLAG)));
|
||||
}
|
||||
|
||||
#define ENTR_CRT_SECTION(Save) Save = EntrCritSection()
|
||||
#define EXT_CRT_SECTION(Save) ExtCritSection(Save)
|
||||
|
||||
#define ENTR_CRT_SECTION_F(Save) Save = EntrCritSectionFiq()
|
||||
#define EXT_CRT_SECTION_F(Save) ExtCritSectionFiq(Save)
|
||||
|
||||
#elif ((__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) || (__CORE__ == __ARM7M__) || (__CORE__ == __ARM7EM__))
|
||||
|
||||
extern Int32U CriticalSecCntr;
|
||||
|
||||
inline void EntrCritSection(void)
|
||||
{
|
||||
if(CriticalSecCntr == 0)
|
||||
{
|
||||
asm("CPSID i");
|
||||
}
|
||||
// avoid lost of one count in case of simultaneously calling from both places
|
||||
++CriticalSecCntr;
|
||||
}
|
||||
|
||||
inline void ExtCritSection(void)
|
||||
{
|
||||
if(--CriticalSecCntr == 0)
|
||||
{
|
||||
asm("CPSIE i");
|
||||
}
|
||||
}
|
||||
|
||||
inline Int32U AtomicExchange (Int32U State, pInt32U Flag)
|
||||
{
|
||||
Int32U Hold;
|
||||
EntrCritSection();
|
||||
Hold = *Flag;
|
||||
*Flag = State;
|
||||
ExtCritSection();
|
||||
return(Hold);
|
||||
}
|
||||
|
||||
#define ENTR_CRT_SECTION() EntrCritSection()
|
||||
#define EXT_CRT_SECTION() ExtCritSection()
|
||||
#endif
|
||||
|
||||
#define LongToBin(n) (((n >> 21) & 0x80) | \
|
||||
((n >> 18) & 0x40) | \
|
||||
((n >> 15) & 0x20) | \
|
||||
((n >> 12) & 0x10) | \
|
||||
((n >> 9) & 0x08) | \
|
||||
((n >> 6) & 0x04) | \
|
||||
((n >> 3) & 0x02) | \
|
||||
((n ) & 0x01))
|
||||
|
||||
#define __BIN(n) LongToBin(0x##n##l)
|
||||
|
||||
#define BIN8(n) __BIN(n)
|
||||
#define BIN(n) __BIN(n)
|
||||
#define BIN16(b1,b2) (( __BIN(b1) << 8UL) + \
|
||||
__BIN(b2))
|
||||
#define BIN32(b1,b2,b3,b4) ((((Int32U)__BIN(b1)) << 24UL) + \
|
||||
(((Int32U)__BIN(b2)) << 16UL) + \
|
||||
(((Int32U)__BIN(b3)) << 8UL) + \
|
||||
(Int32U)__BIN(b4))
|
||||
|
||||
#endif // __ARM_COMM_DEF_H
|
||||
@ -0,0 +1,330 @@
|
||||
/**/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "iar_stm32f407zg_sk.h"
|
||||
|
||||
/**
|
||||
* @{
|
||||
*/
|
||||
GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
|
||||
LED4_GPIO_PORT};
|
||||
const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
|
||||
LED4_PIN};
|
||||
const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
|
||||
LED4_GPIO_CLK};
|
||||
|
||||
GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
|
||||
USER_BUTTON_GPIO_PORT,RIGHT_BUTTON_GPIO_PORT, LEFT_BUTTON_GPIO_PORT,
|
||||
UP_BUTTON_GPIO_PORT,DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
|
||||
|
||||
const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
|
||||
USER_BUTTON_PIN,RIGHT_BUTTON_PIN, LEFT_BUTTON_PIN,
|
||||
UP_BUTTON_PIN,DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
|
||||
|
||||
const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
|
||||
USER_BUTTON_GPIO_CLK,RIGHT_BUTTON_GPIO_CLK, LEFT_BUTTON_GPIO_CLK,
|
||||
UP_BUTTON_GPIO_CLK,DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
|
||||
|
||||
const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
|
||||
TAMPER_BUTTON_EXTI_LINE,
|
||||
USER_BUTTON_EXTI_LINE,
|
||||
RIGHT_BUTTON_EXTI_LINE,
|
||||
LEFT_BUTTON_EXTI_LINE,
|
||||
UP_BUTTON_EXTI_LINE,
|
||||
DOWN_BUTTON_EXTI_LINE,
|
||||
SEL_BUTTON_EXTI_LINE};
|
||||
|
||||
const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
|
||||
TAMPER_BUTTON_EXTI_PORT_SOURCE,
|
||||
USER_BUTTON_EXTI_PORT_SOURCE,
|
||||
RIGHT_BUTTON_EXTI_PORT_SOURCE,
|
||||
LEFT_BUTTON_EXTI_PORT_SOURCE,
|
||||
UP_BUTTON_EXTI_PORT_SOURCE,
|
||||
DOWN_BUTTON_EXTI_PORT_SOURCE,
|
||||
SEL_BUTTON_EXTI_PORT_SOURCE};
|
||||
|
||||
const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
|
||||
TAMPER_BUTTON_EXTI_PIN_SOURCE,
|
||||
USER_BUTTON_EXTI_PIN_SOURCE,
|
||||
RIGHT_BUTTON_EXTI_PIN_SOURCE,
|
||||
LEFT_BUTTON_EXTI_PIN_SOURCE,
|
||||
UP_BUTTON_EXTI_PIN_SOURCE,
|
||||
DOWN_BUTTON_EXTI_PIN_SOURCE,
|
||||
SEL_BUTTON_EXTI_PIN_SOURCE};
|
||||
const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
|
||||
USER_BUTTON_EXTI_IRQn,RIGHT_BUTTON_EXTI_IRQn,
|
||||
LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
|
||||
DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
|
||||
|
||||
USART_TypeDef* COM_USART[COMn] = {EVAL_COM1,EVAL_COM2};
|
||||
|
||||
GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
|
||||
|
||||
GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT,EVAL_COM2_RX_GPIO_PORT};
|
||||
|
||||
const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK,EVAL_COM2_CLK};
|
||||
|
||||
const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK,EVAL_COM2_TX_GPIO_CLK};
|
||||
|
||||
const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
|
||||
|
||||
const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
|
||||
|
||||
const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
|
||||
|
||||
const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};
|
||||
|
||||
const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM1_RX_SOURCE};
|
||||
|
||||
const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};
|
||||
|
||||
const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};
|
||||
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
void STM_EVAL_GPIOReset(void)
|
||||
{
|
||||
GPIO_DeInit(GPIOA);
|
||||
GPIO_DeInit(GPIOB);
|
||||
GPIO_DeInit(GPIOC);
|
||||
GPIO_DeInit(GPIOD);
|
||||
GPIO_DeInit(GPIOE);
|
||||
GPIO_DeInit(GPIOF);
|
||||
GPIO_DeInit(GPIOG);
|
||||
GPIO_DeInit(GPIOH);
|
||||
GPIO_DeInit(GPIOI);
|
||||
}
|
||||
/**
|
||||
* @brief Configures LED GPIO.
|
||||
* @param Led: Specifies the Led to be configured.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDInit(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable the GPIO_LED Clock */
|
||||
RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE);
|
||||
|
||||
|
||||
/* Configure the GPIO_LED pin */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED On.
|
||||
* @param Led: Specifies the Led to be set on.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDOn(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED Off.
|
||||
* @param Led: Specifies the Led to be set off.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDOff(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the selected LED.
|
||||
* @param Led: Specifies the Led to be toggled.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDToggle(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures Button GPIO and EXTI Line.
|
||||
* @param Button: Specifies the Button to be configured.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg BUTTON_WAKEUP: Wakeup Push Button
|
||||
* @arg BUTTON_TAMPER: Tamper Push Button
|
||||
* @arg BUTTON_KEY: Key Push Button
|
||||
* @arg BUTTON_RIGHT: Joystick Right Push Button
|
||||
* @arg BUTTON_LEFT: Joystick Left Push Button
|
||||
* @arg BUTTON_UP: Joystick Up Push Button
|
||||
* @arg BUTTON_DOWN: Joystick Down Push Button
|
||||
* @arg BUTTON_SEL: Joystick Sel Push Button
|
||||
* @param Button_Mode: Specifies Button mode.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg BUTTON_MODE_GPIO: Button will be used as simple IO
|
||||
* @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
|
||||
* generation capability
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
EXTI_InitTypeDef EXTI_InitStructure;
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
|
||||
/* Enable the BUTTON Clock */
|
||||
RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
/* Configure Button pin as input */
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
|
||||
GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
|
||||
|
||||
|
||||
if (Button_Mode == BUTTON_MODE_EXTI)
|
||||
{
|
||||
/* Connect Button EXTI Line to Button GPIO Pin */
|
||||
SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
|
||||
|
||||
/* Configure Button EXTI line */
|
||||
EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
|
||||
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
|
||||
if(Button != BUTTON_WAKEUP)
|
||||
{
|
||||
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
|
||||
}
|
||||
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||||
EXTI_Init(&EXTI_InitStructure);
|
||||
|
||||
/* Enable and set Button EXTI Interrupt to the lowest priority */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the selected Button state.
|
||||
* @param Button: Specifies the Button to be checked.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg BUTTON_WAKEUP: Wakeup Push Button
|
||||
* @arg BUTTON_TAMPER: Tamper Push Button
|
||||
* @arg BUTTON_KEY: Key Push Button
|
||||
* @arg BUTTON_RIGHT: Joystick Right Push Button
|
||||
* @arg BUTTON_LEFT: Joystick Left Push Button
|
||||
* @arg BUTTON_UP: Joystick Up Push Button
|
||||
* @arg BUTTON_DOWN: Joystick Down Push Button
|
||||
* @arg BUTTON_SEL: Joystick Sel Push Button
|
||||
* @retval The Button GPIO pin value.
|
||||
*/
|
||||
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
|
||||
{
|
||||
return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures COM port.
|
||||
* @param COM: Specifies the COM port to be configured.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg COM1
|
||||
* @arg COM2
|
||||
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure that
|
||||
* contains the configuration information for the specified USART peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable GPIO clock */
|
||||
RCC_AHB1PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
|
||||
|
||||
if (COM == COM1)
|
||||
{
|
||||
/* Enable UART clock */
|
||||
RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
|
||||
}
|
||||
|
||||
/* Connect PXx to USARTx_Tx*/
|
||||
GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
|
||||
|
||||
/* Connect PXx to USARTx_Rx*/
|
||||
GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
|
||||
|
||||
/* Configure USART Tx as alternate function */
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
|
||||
|
||||
/* Configure USART Rx as alternate function */
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
|
||||
GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
|
||||
|
||||
/* USART configuration */
|
||||
USART_Init(COM_USART[COM], USART_InitStruct);
|
||||
|
||||
/* Enable USART */
|
||||
USART_Cmd(COM_USART[COM], ENABLE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,430 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file iar_stm32f407zg_sk.h
|
||||
* @brief This file contains definitions for Leds, push-buttons
|
||||
* and COM ports hardware resources.
|
||||
******************************************************************************
|
||||
* @copy
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __IAR_STM32F407ZG_SK_H
|
||||
#define __IAR_STM32F407ZG_SK_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
LED1 = 0,
|
||||
LED2 = 1,
|
||||
LED3 = 2,
|
||||
LED4 = 3
|
||||
} Led_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_WAKEUP = 0,
|
||||
BUTTON_TAMPER = 1,
|
||||
BUTTON_USER = 2,
|
||||
BUTTON_RIGHT = 3,
|
||||
BUTTON_LEFT = 4,
|
||||
BUTTON_UP = 5,
|
||||
BUTTON_DOWN = 6,
|
||||
BUTTON_SEL = 7
|
||||
} Button_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_MODE_GPIO = 0,
|
||||
BUTTON_MODE_EXTI = 1
|
||||
} ButtonMode_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
COM1 = 0,
|
||||
COM2 = 1
|
||||
} COM_TypeDef;
|
||||
|
||||
#define LEDn 4
|
||||
|
||||
#define LED1_PIN GPIO_Pin_6
|
||||
#define LED1_GPIO_PORT GPIOF
|
||||
#define LED1_GPIO_CLK RCC_AHB1Periph_GPIOF
|
||||
|
||||
#define LED2_PIN GPIO_Pin_7
|
||||
#define LED2_GPIO_PORT GPIOF
|
||||
#define LED2_GPIO_CLK RCC_AHB1Periph_GPIOF
|
||||
|
||||
#define LED3_PIN GPIO_Pin_8
|
||||
#define LED3_GPIO_PORT GPIOF
|
||||
#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOF
|
||||
|
||||
#define LED4_PIN GPIO_Pin_9
|
||||
#define LED4_GPIO_PORT GPIOF
|
||||
#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOF
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IAR_STM32F407ZG_SK_LOW_LEVEL_BUTTON
|
||||
* @{
|
||||
*/
|
||||
#define BUTTONn 8 /**/
|
||||
|
||||
/**
|
||||
* @brief Wakeup push-button
|
||||
*/
|
||||
#define WAKEUP_BUTTON_PIN GPIO_Pin_0
|
||||
#define WAKEUP_BUTTON_GPIO_PORT GPIOA
|
||||
#define WAKEUP_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA
|
||||
#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
|
||||
#define WAKEUP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
|
||||
#define WAKEUP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
|
||||
#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
|
||||
|
||||
/**
|
||||
* @brief Tamper push-button
|
||||
*/
|
||||
#define TAMPER_BUTTON_PIN GPIO_Pin_13
|
||||
#define TAMPER_BUTTON_GPIO_PORT GPIOC
|
||||
#define TAMPER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOC
|
||||
#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13
|
||||
#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC
|
||||
#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13
|
||||
#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
|
||||
|
||||
/**
|
||||
* @brief Key push-button
|
||||
*/
|
||||
#define USER_BUTTON_PIN GPIO_Pin_6
|
||||
#define USER_BUTTON_GPIO_PORT GPIOG
|
||||
#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG
|
||||
#define USER_BUTTON_EXTI_LINE EXTI_Line6
|
||||
#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
|
||||
#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource6
|
||||
#define USER_BUTTON_EXTI_IRQn EXTI9_5_IRQn
|
||||
/**
|
||||
* @brief Joystick Right
|
||||
*/
|
||||
#define RIGHT_BUTTON_PIN GPIO_Pin_3
|
||||
#define RIGHT_BUTTON_GPIO_PORT GPIOC
|
||||
#define RIGHT_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOC
|
||||
#define RIGHT_BUTTON_EXTI_LINE EXTI_Line3
|
||||
#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC
|
||||
#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource3
|
||||
#define RIGHT_BUTTON_EXTI_IRQn EXTI3_IRQn
|
||||
/**
|
||||
* @brief Joystick Left
|
||||
*/
|
||||
#define LEFT_BUTTON_PIN GPIO_Pin_11
|
||||
#define LEFT_BUTTON_GPIO_PORT GPIOG
|
||||
#define LEFT_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG
|
||||
#define LEFT_BUTTON_EXTI_LINE EXTI_Line11
|
||||
#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
|
||||
#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11
|
||||
#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
|
||||
/**
|
||||
* @brief Joystick Up
|
||||
*/
|
||||
#define UP_BUTTON_PIN GPIO_Pin_7
|
||||
#define UP_BUTTON_GPIO_PORT GPIOG
|
||||
#define UP_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG
|
||||
#define UP_BUTTON_EXTI_LINE EXTI_Line7
|
||||
#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
|
||||
#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource7
|
||||
#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
|
||||
/**
|
||||
* @brief Joystick Down
|
||||
*/
|
||||
#define DOWN_BUTTON_PIN GPIO_Pin_8
|
||||
#define DOWN_BUTTON_GPIO_PORT GPIOG
|
||||
#define DOWN_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG
|
||||
#define DOWN_BUTTON_EXTI_LINE EXTI_Line8
|
||||
#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
|
||||
#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8
|
||||
#define DOWN_BUTTON_EXTI_IRQn EXTI9_5_IRQn
|
||||
/**
|
||||
* @brief Joystick Sel
|
||||
*/
|
||||
#define SEL_BUTTON_PIN GPIO_Pin_15
|
||||
#define SEL_BUTTON_GPIO_PORT GPIOG
|
||||
#define SEL_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG
|
||||
#define SEL_BUTTON_EXTI_LINE EXTI_Line15
|
||||
#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
|
||||
#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource15
|
||||
#define SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IAR_STM32F407ZG_SK_LOW_LEVEL_COM
|
||||
* @{
|
||||
*/
|
||||
#define COMn 2
|
||||
|
||||
/**
|
||||
* @brief Definition for COM port1, connected to USART6
|
||||
*/
|
||||
#define EVAL_COM1 USART6
|
||||
#define EVAL_COM1_CLK RCC_APB2Periph_USART6
|
||||
#define EVAL_COM1_TX_PIN GPIO_Pin_6
|
||||
#define EVAL_COM1_TX_GPIO_PORT GPIOC
|
||||
#define EVAL_COM1_TX_GPIO_CLK RCC_AHB1Periph_GPIOC
|
||||
#define EVAL_COM1_TX_SOURCE GPIO_PinSource6
|
||||
#define EVAL_COM1_TX_AF GPIO_AF_USART6
|
||||
#define EVAL_COM1_RX_PIN GPIO_Pin_9
|
||||
#define EVAL_COM1_RX_GPIO_PORT GPIOG
|
||||
#define EVAL_COM1_RX_GPIO_CLK RCC_AHB1Periph_GPIOG
|
||||
#define EVAL_COM1_RX_SOURCE GPIO_PinSource9
|
||||
#define EVAL_COM1_RX_AF GPIO_AF_USART6
|
||||
#define EVAL_COM1_IRQn USART6_IRQn
|
||||
|
||||
/**
|
||||
* @brief Definition for COM port2, connected to USART3
|
||||
*/
|
||||
#define EVAL_COM2 USART3
|
||||
#define EVAL_COM2_CLK RCC_APB1Periph_USART3
|
||||
#define EVAL_COM2_TX_PIN GPIO_Pin_8
|
||||
#define EVAL_COM2_TX_GPIO_PORT GPIOD
|
||||
#define EVAL_COM2_TX_GPIO_CLK RCC_AHB1Periph_GPIOD
|
||||
#define EVAL_COM2_TX_SOURCE GPIO_PinSource8
|
||||
#define EVAL_COM2_TX_AF GPIO_AF_USART3
|
||||
#define EVAL_COM2_RX_PIN GPIO_Pin_9
|
||||
#define EVAL_COM2_RX_GPIO_PORT GPIOD
|
||||
#define EVAL_COM2_RX_GPIO_CLK RCC_AHB1Periph_GPIOD
|
||||
#define EVAL_COM2_RX_SOURCE GPIO_PinSource9
|
||||
#define EVAL_COM2_RX_AF GPIO_AF_USART3
|
||||
#define EVAL_COM2_RTS_PIN GPIO_Pin_12
|
||||
#define EVAL_COM2_RTS_GPIO_PORT GPIOD
|
||||
#define EVAL_COM2_RTS_GPIO_CLK RCC_AHB1Periph_GPIOD
|
||||
#define EVAL_COM2_RTS_SOURCE GPIO_PinSource12
|
||||
#define EVAL_COM2_RTS_AF GPIO_AF_USART3
|
||||
#define EVAL_COM2_CTS_PIN GPIO_Pin_11
|
||||
#define EVAL_COM2_CTS_GPIO_PORT GPIOD
|
||||
#define EVAL_COM2_CTS_GPIO_CLK RCC_AHB1Periph_GPIOD
|
||||
#define EVAL_COM2_CTS_SOURCE GPIO_PinSource11
|
||||
#define EVAL_COM2_CTS_AF GPIO_AF_USART3
|
||||
#define EVAL_COM2_IRQn USART3_IRQn
|
||||
|
||||
/**
|
||||
* @BUZZER
|
||||
*/
|
||||
#define BUZZER_GPIO_PIN GPIO_Pin_10
|
||||
#define BUZZER_GPIO_PORT GPIOA
|
||||
#define BUZZER_GPIO_CLK RCC_AHB1Periph_GPIOA
|
||||
#define BUZZER_PIN_SOURCE GPIO_PinSource10
|
||||
#define BUZZER_TIM TIM1
|
||||
#define RCC_APB2PERIPH_BUZZER_TIM RCC_APB2Periph_TIM1
|
||||
#define BUZZER_PIN_AF GPIO_AF_TIM1
|
||||
|
||||
/**
|
||||
* @USB OTG
|
||||
*/
|
||||
#define OTG_FS_VBUS_PIN GPIO_Pin_9
|
||||
#define OTG_FS_VBUS_PORT GPIOA
|
||||
#define OTG_FS_VBUS_CLK RCC_AHB1Periph_GPIOA
|
||||
#define OTG_FS_VBUS_SOURCE GPIO_PinSource9
|
||||
|
||||
#define USB_FS_VBUSON_PIN GPIO_Pin_2
|
||||
#define USB_FS_VBUSON_PORT GPIOC
|
||||
#define USB_FS_VBUSON_CLK RCC_AHB1Periph_GPIOC
|
||||
#define USB_FS_VBUSON_SOURCE GPIO_PinSource2
|
||||
|
||||
#define USB_FS_FAULT_PIN GPIO_Pin_10
|
||||
#define USB_FS_FAULT_PORT GPIOB
|
||||
#define USB_FS_FAULT_CLK RCC_AHB1Periph_GPIOB
|
||||
#define USB_FS_FAULT_SOURCE GPIO_PinSource10
|
||||
|
||||
/**
|
||||
* @USB HOST
|
||||
*/
|
||||
#define OTG_HS_VBUS_PIN GPIO_Pin_13
|
||||
#define OTG_HS_VBUS_PORT GPIOB
|
||||
#define OTG_HS_VBUS_CLK RCC_AHB1Periph_GPIOB
|
||||
#define OTG_HS_VBUS_SOURCE GPIO_PinSource13
|
||||
|
||||
#define USB_HS_VBUSON_PIN GPIO_Pin_3
|
||||
#define USB_HS_VBUSON_PORT GPIOE
|
||||
#define USB_HS_VBUSON_CLK RCC_AHB1Periph_GPIOE
|
||||
#define USB_HS_VBUSON_SOURCE GPIO_PinSource3
|
||||
|
||||
#define USB_HS_FAULT_PIN GPIO_Pin_13
|
||||
#define USB_HS_FAULT_PORT GPIOD
|
||||
#define USB_HS_FAULT_CLK RCC_AHB1Periph_GPIOD
|
||||
#define USB_HS_FAULT_SOURCE GPIO_PinSource13
|
||||
|
||||
#define OTG_HS_ID_PIN GPIO_Pin_12
|
||||
#define OTG_HS_ID_PORT GPIOB
|
||||
#define OTG_HS_ID_CLK RCC_AHB1Periph_GPIOB
|
||||
#define OTG_HS_ID_SOURCE GPIO_PinSource12
|
||||
|
||||
/**
|
||||
* @TRIMER
|
||||
*/
|
||||
#define TRIMER_PIN GPIO_Pin_0
|
||||
#define TRIMER_PORT GPIOC
|
||||
#define TRIMER_CLK RCC_AHB1Periph_GPIOC
|
||||
#define TRIMER_SOURCE GPIO_PinSource0
|
||||
#define TRIMER_CHANNEL ADC_Channel_10
|
||||
|
||||
/** @addtogroup IAR_STM32F407ZG_SK_LOW_LEVEL_SD_FLASH
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @SD
|
||||
*/
|
||||
#define SD_CP_PIN GPIO_Pin_3
|
||||
#define SD_CP_PORT GPIOD
|
||||
#define SD_CP_CLK RCC_AHB1Periph_GPIOD
|
||||
#define SD_CP_SOURCE GPIO_PinSource3
|
||||
|
||||
#define SD_WP_PIN GPIO_Pin_4
|
||||
#define SD_WP_PORT GPIOE
|
||||
#define SD_WP_CLK RCC_AHB1Periph_GPIOE
|
||||
#define SD_WP_SOURCE GPIO_PinSource4
|
||||
|
||||
#define SD_CMD_PIN GPIO_Pin_2
|
||||
#define SD_CMD_PORT GPIOD
|
||||
#define SD_CMD_CLK RCC_AHB1Periph_GPIOD
|
||||
#define SD_CMD_SOURCE GPIO_PinSource2
|
||||
|
||||
#define SD_D0_PIN GPIO_Pin_8
|
||||
#define SD_D0_PORT GPIOC
|
||||
#define SD_D0_CLK RCC_AHB1Periph_GPIOC
|
||||
#define SD_D0_SOURCE GPIO_PinSource8
|
||||
|
||||
#define SD_D1_PIN GPIO_Pin_9
|
||||
#define SD_D1_PORT GPIOC
|
||||
#define SD_D1_CLK RCC_AHB1Periph_GPIOC
|
||||
#define SD_D1_SOURCE GPIO_PinSource9
|
||||
|
||||
#define SD_D2_PIN GPIO_Pin_10
|
||||
#define SD_D2_PORT GPIOC
|
||||
#define SD_D2_CLK RCC_AHB1Periph_GPIOC
|
||||
#define SD_D2_SOURCE GPIO_PinSource10
|
||||
|
||||
#define SD_D3_PIN GPIO_Pin_11
|
||||
#define SD_D3_PORT GPIOC
|
||||
#define SD_D3_CLK RCC_AHB1Periph_GPIOC
|
||||
#define SD_D3_SOURCE GPIO_PinSource11
|
||||
|
||||
#define SD_CLK_PIN GPIO_Pin_12
|
||||
#define SD_CLK_PORT GPIOC
|
||||
#define SD_CLK_CLK RCC_AHB1Periph_GPIOC
|
||||
#define SD_CLK_SOURCE GPIO_PinSource12
|
||||
/**
|
||||
* @brief SD FLASH SDIO Interface
|
||||
*/
|
||||
#define SD_SDIO_DMA_STREAM3 3
|
||||
//#define SD_SDIO_DMA_STREAM6 6
|
||||
|
||||
#ifdef SD_SDIO_DMA_STREAM3
|
||||
#define SD_SDIO_DMA_STREAM DMA2_Stream3
|
||||
#define SD_SDIO_DMA_CHANNEL DMA_Channel_4
|
||||
#define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3
|
||||
#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3
|
||||
#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3
|
||||
#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3
|
||||
#define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3
|
||||
#elif defined SD_SDIO_DMA_STREAM6
|
||||
#define SD_SDIO_DMA_STREAM DMA2_Stream6
|
||||
#define SD_SDIO_DMA_CHANNEL DMA_Channel_4
|
||||
#define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF6
|
||||
#define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6
|
||||
#define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6
|
||||
#define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6
|
||||
#define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6
|
||||
#endif /* SD_SDIO_DMA_STREAM3 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @CAN
|
||||
*/
|
||||
#define CAN_TX_PIN GPIO_Pin_9
|
||||
#define CAN_TX_PORT GPIOB
|
||||
#define CAN_TX_CLK RCC_AHB1Periph_GPIOB
|
||||
#define CAN_TX_AF GPIO_AF_CAN1
|
||||
#define CAN_TX_SOURCE GPIO_PinSource9
|
||||
|
||||
#define CAN_RX_PIN GPIO_Pin_8
|
||||
#define CAN_RX_PORT GPIOB
|
||||
#define CAN_RX_CLK RCC_AHB1Periph_GPIOB
|
||||
#define CAN_RX_AF GPIO_AF_CAN1
|
||||
#define CAN_RX_SOURCE GPIO_PinSource8
|
||||
|
||||
#define CAN_CTRL_PIN GPIO_Pin_6
|
||||
#define CAN_CTRL_PORT GPIOD
|
||||
#define CAN_CTRL_CLK RCC_AHB1Periph_GPIOD
|
||||
#define CAN_CTRL_SOURCE GPIO_PinSource6
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IAR_STM32F407ZG_SK_LOW_LEVEL_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup IAR_STM32F407ZG_SK_LOW_LEVEL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void STM_EVAL_LEDInit(Led_TypeDef Led);
|
||||
void STM_EVAL_LEDOn(Led_TypeDef Led);
|
||||
void STM_EVAL_LEDOff(Led_TypeDef Led);
|
||||
void STM_EVAL_LEDToggle(Led_TypeDef Led);
|
||||
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
|
||||
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
|
||||
void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IAR_STM32F407ZG_SK_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,34 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,652 @@
|
||||
/*
|
||||
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* >>>>>> NOTE 1: <<<<<<
|
||||
*
|
||||
* main() can be configured to create either a very simple LED flasher demo, or
|
||||
* a more comprehensive test/demo application.
|
||||
*
|
||||
* To create a very simple LED flasher example, set the
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant (defined below) to 1. When
|
||||
* this is done, only the standard demo flash tasks are created. The standard
|
||||
* demo flash example creates three tasks, each of which toggle an LED at a
|
||||
* fixed but different frequency.
|
||||
*
|
||||
* To create a more comprehensive test and demo application, set
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0.
|
||||
*
|
||||
* >>>>>> NOTE 2: <<<<<<
|
||||
*
|
||||
* In addition to the normal set of standard demo tasks, the comprehensive test
|
||||
* makes heavy use of the floating point unit, and forces floating point
|
||||
* instructions to be used from interrupts that nest three deep. The nesting
|
||||
* starts from the tick hook function, resulting is an abnormally long context
|
||||
* switch time. This is done purely to stress test the FPU context switching
|
||||
* implementation, and that part of the test can be removed by setting
|
||||
* configUSE_TICK_HOOK to 0 in FreeRTOSConfig.h.
|
||||
******************************************************************************
|
||||
*
|
||||
* main() creates all the demo application tasks and software timers, then starts
|
||||
* the scheduler. The web documentation provides more details of the standard
|
||||
* demo application tasks, which provide no particular functionality, but do
|
||||
* provide a good example of how to use the FreeRTOS API.
|
||||
*
|
||||
* In addition to the standard demo tasks, the following tasks and tests are
|
||||
* defined and/or created within this file:
|
||||
*
|
||||
* "Reg test" tasks - These fill both the core and floating point registers with
|
||||
* known values, then check that each register maintains its expected value for
|
||||
* the lifetime of the task. Each task uses a different set of values. The reg
|
||||
* test tasks execute with a very low priority, so get preempted very
|
||||
* frequently. A register containing an unexpected value is indicative of an
|
||||
* error in the context switching mechanism.
|
||||
*
|
||||
* "Check" timer - The check software timer period is initially set to three
|
||||
* seconds. The callback function associated with the check software timer
|
||||
* checks that all the standard demo tasks, and the register check tasks, are
|
||||
* not only still executing, but are executing without reporting any errors. If
|
||||
* the check software timer discovers that a task has either stalled, or
|
||||
* reported an error, then it changes its own execution period from the initial
|
||||
* three seconds, to just 200ms. The check software timer callback function
|
||||
* also toggles an LED each time it is called. This provides a visual
|
||||
* indication of the system status: If the LED toggles every three seconds,
|
||||
* then no issues have been discovered. If the LED toggles every 200ms, then
|
||||
* an issue has been discovered with at least one task.
|
||||
*
|
||||
* Tick hook - The application tick hook is called from the schedulers tick
|
||||
* interrupt service routine when configUSE_TICK_HOOK is set to 1 in
|
||||
* FreeRTOSConfig.h. In this example, the tick hook is used to test the kernels
|
||||
* handling of the floating point units (FPU) context, both at the task level
|
||||
* and when nesting interrupts access the floating point unit registers. The
|
||||
* tick hook function first fills the FPU registers with a known value, it
|
||||
* then triggers a medium priority interrupt. The medium priority interrupt
|
||||
* fills the FPU registers with a different value, and triggers a high priority
|
||||
* interrupt. The high priority interrupt once again fills the the FPU
|
||||
* registers with a known value before returning to the medium priority
|
||||
* interrupt. The medium priority interrupt checks that the FPU registers
|
||||
* contain the values that it wrote to them, then returns to the tick hook
|
||||
* function. Finally, the tick hook function checks that the FPU registers
|
||||
* contain the values that it wrote to them, before it too returns.
|
||||
*
|
||||
* Button interrupt - The button marked "USER" on the starter kit is used to
|
||||
* demonstrate how to write an interrupt service routine, and how to synchronise
|
||||
* a task with an interrupt. A task is created that blocks on a test semaphore.
|
||||
* When the USER button is pressed, the button interrupt handler gives the
|
||||
* semaphore, causing the task to unblock. When the task unblocks, it simply
|
||||
* increments an execution count variable, then returns to block on the
|
||||
* semaphore again.
|
||||
*/
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "timers.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Demo application includes. */
|
||||
#include "partest.h"
|
||||
#include "flash.h"
|
||||
#include "flop.h"
|
||||
#include "integer.h"
|
||||
#include "PollQ.h"
|
||||
#include "semtest.h"
|
||||
#include "dynamic.h"
|
||||
#include "BlockQ.h"
|
||||
#include "blocktim.h"
|
||||
#include "countsem.h"
|
||||
#include "GenQTest.h"
|
||||
#include "recmutex.h"
|
||||
#include "death.h"
|
||||
|
||||
/* Hardware and starter kit includes. */
|
||||
#include "arm_comm.h"
|
||||
#include "iar_stm32f407zg_sk.h"
|
||||
#include "stm32f4xx.h"
|
||||
#include "stm32f4xx_conf.h"
|
||||
|
||||
/* Priorities for the demo application tasks. */
|
||||
#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL )
|
||||
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
|
||||
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
|
||||
|
||||
/* The LED used by the check timer. */
|
||||
#define mainCHECK_LED ( 3UL )
|
||||
|
||||
/* A block time of zero simply means "don't block". */
|
||||
#define mainDONT_BLOCK ( 0UL )
|
||||
|
||||
/* The period after which the check timer will expire, in ms, provided no errors
|
||||
have been reported by any of the standard demo tasks. ms are converted to the
|
||||
equivalent in ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
|
||||
|
||||
/* The period at which the check timer will expire, in ms, if an error has been
|
||||
reported in one of the standard demo tasks. ms are converted to the equivalent
|
||||
in ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
|
||||
|
||||
/* Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 1 to create a simple demo.
|
||||
Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more
|
||||
comprehensive test application. See the comments at the top of this file, and
|
||||
the documentation page on the http://www.FreeRTOS.org web site for more
|
||||
information. */
|
||||
#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Set up the hardware ready to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*
|
||||
* The check timer callback function, as described at the top of this file.
|
||||
*/
|
||||
static void prvCheckTimerCallback( xTimerHandle xTimer );
|
||||
|
||||
/*
|
||||
* Configure the interrupts used to test the interrupt nesting depth as
|
||||
* described at the top of this file.
|
||||
*/
|
||||
static void prvSetupNestedFPUInterruptsTest( void );
|
||||
|
||||
/*
|
||||
* Register check tasks, and the tasks used to write over and check the contents
|
||||
* of the FPU registers, as described at the top of this file. The nature of
|
||||
* these files necessitates that they are written in an assembly file.
|
||||
*/
|
||||
extern void vRegTest1Task( void *pvParameters );
|
||||
extern void vRegTest2Task( void *pvParameters );
|
||||
extern void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue );
|
||||
extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue );
|
||||
|
||||
/*
|
||||
* The task that is synchronised with the button interrupt. This is done just
|
||||
* to demonstrate how to write interrupt service routines, and how to
|
||||
* synchronise a task with an interrupt.
|
||||
*/
|
||||
static void prvButtonTestTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* This file can be used to create either a simple LED flasher example, or a
|
||||
* comprehensive test/demo application - depending on the setting of the
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant defined above. If
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 1, then the following
|
||||
* function will create a lot of additional tasks and a software timer. If
|
||||
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0, then the following
|
||||
* function will do nothing.
|
||||
*/
|
||||
static void prvOptionallyCreateComprehensveTestApplication( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The following two variables are used to communicate the status of the
|
||||
register check tasks to the check software timer. If the variables keep
|
||||
incrementing, then the register check tasks has not discovered any errors. If
|
||||
a variable stops incrementing, then an error has been found. */
|
||||
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
|
||||
|
||||
/* The following variables are used to verify that the interrupt nesting depth
|
||||
is as intended. ulFPUInterruptNesting is incremented on entry to an interrupt
|
||||
that uses the FPU, and decremented on exit of the same interrupt.
|
||||
ulMaxFPUInterruptNesting latches the highest value reached by
|
||||
ulFPUInterruptNesting. These variables have no other purpose. */
|
||||
volatile unsigned long ulFPUInterruptNesting = 0UL, ulMaxFPUInterruptNesting = 0UL;
|
||||
|
||||
/* The semaphore used to demonstrate a task being synchronised with an
|
||||
interrupt. */
|
||||
static xSemaphoreHandle xTestSemaphore = NULL;
|
||||
|
||||
/* The variable that is incremented by the task synchronised with the button
|
||||
interrupt. */
|
||||
volatile unsigned long ulButtonPressCounts = 0UL;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* Configure the hardware ready to run the test. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* Start standard demo/test application flash tasks. See the comments at
|
||||
the top of this file. The LED flash tasks are always created. The other
|
||||
tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to
|
||||
0 (at the top of this file). See the comments at the top of this file for
|
||||
more information. */
|
||||
vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
|
||||
|
||||
/* The following function will only create more tasks and timers if
|
||||
mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this
|
||||
file). See the comments at the top of this file for more information. */
|
||||
prvOptionallyCreateComprehensveTestApplication();
|
||||
|
||||
/* Start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Infinite loop */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckTimerCallback( xTimerHandle xTimer )
|
||||
{
|
||||
static long lChangedTimerPeriodAlready = pdFALSE;
|
||||
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
|
||||
long lErrorFound = pdFALSE;
|
||||
|
||||
/* Check all the demo tasks (other than the flash tasks) to ensure
|
||||
that they are all still running, and that none have detected an error. */
|
||||
|
||||
if( xAreMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xIsCreateTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xArePollingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
/* Check that the register test 1 task is still running. */
|
||||
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
ulLastRegTest1Value = ulRegTest1LoopCounter;
|
||||
|
||||
/* Check that the register test 2 task is still running. */
|
||||
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
|
||||
{
|
||||
lErrorFound = pdTRUE;
|
||||
}
|
||||
ulLastRegTest2Value = ulRegTest2LoopCounter;
|
||||
|
||||
/* Toggle the check LED to give an indication of the system status. If
|
||||
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
|
||||
everything is ok. A faster toggle indicates an error. */
|
||||
vParTestToggleLED( mainCHECK_LED );
|
||||
|
||||
/* Have any errors been latch in lErrorFound? If so, shorten the
|
||||
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
|
||||
This will result in an increase in the rate at which mainCHECK_LED
|
||||
toggles. */
|
||||
if( lErrorFound != pdFALSE )
|
||||
{
|
||||
if( lChangedTimerPeriodAlready == pdFALSE )
|
||||
{
|
||||
lChangedTimerPeriodAlready = pdTRUE;
|
||||
|
||||
/* This call to xTimerChangePeriod() uses a zero block time.
|
||||
Functions called from inside of a timer callback function must
|
||||
*never* attempt to block. */
|
||||
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvButtonTestTask( void *pvParameters )
|
||||
{
|
||||
configASSERT( xTestSemaphore );
|
||||
|
||||
/* This is the task used as an example of how to synchronise a task with
|
||||
an interrupt. Each time the button interrupt gives the semaphore, this task
|
||||
will unblock, increment its execution counter, then return to block
|
||||
again. */
|
||||
|
||||
/* Take the semaphore before started to ensure it is in the correct
|
||||
state. */
|
||||
xSemaphoreTake( xTestSemaphore, mainDONT_BLOCK );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
xSemaphoreTake( xTestSemaphore, portMAX_DELAY );
|
||||
ulButtonPressCounts++;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
/* Setup STM32 system (clock, PLL and Flash configuration) */
|
||||
SystemInit();
|
||||
|
||||
/* Ensure all priority bits are assigned as preemption priority bits. */
|
||||
NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );
|
||||
|
||||
/* Setup the LED outputs. */
|
||||
vParTestInitialise();
|
||||
|
||||
/* Configure the button input. This configures the interrupt to use the
|
||||
lowest interrupt priority, so it is ok to use the ISR safe FreeRTOS API
|
||||
from the button interrupt handler. */
|
||||
STM_EVAL_PBInit( BUTTON_USER, BUTTON_MODE_EXTI );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
#if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )
|
||||
{
|
||||
/* Just to verify that the interrupt nesting behaves as expected,
|
||||
increment ulFPUInterruptNesting on entry, and decrement it on exit. */
|
||||
ulFPUInterruptNesting++;
|
||||
|
||||
/* Fill the FPU registers with 0. */
|
||||
vRegTestClearFlopRegistersToParameterValue( 0UL );
|
||||
|
||||
/* Trigger a timer 2 interrupt, which will fill the registers with a
|
||||
different value and itself trigger a timer 3 interrupt. Note that the
|
||||
timers are not actually used. The timer 2 and 3 interrupt vectors are
|
||||
just used for convenience. */
|
||||
NVIC_SetPendingIRQ( TIM2_IRQn );
|
||||
|
||||
/* Ensure that, after returning from the nested interrupts, all the FPU
|
||||
registers contain the value to which they were set by the tick hook
|
||||
function. */
|
||||
configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 0UL ) );
|
||||
|
||||
ulFPUInterruptNesting--;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupNestedFPUInterruptsTest( void )
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
/* Enable the TIM2 interrupt in the NVIC. The timer itself is not used,
|
||||
just its interrupt vector to force nesting from software. TIM2 must have
|
||||
a lower priority than TIM3, and both must have priorities above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init( &NVIC_InitStructure );
|
||||
|
||||
/* Enable the TIM3 interrupt in the NVIC. The timer itself is not used,
|
||||
just its interrupt vector to force nesting from software. TIM2 must have
|
||||
a lower priority than TIM3, and both must have priorities above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 2;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init( &NVIC_InitStructure );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void TIM3_IRQHandler( void )
|
||||
{
|
||||
/* Just to verify that the interrupt nesting behaves as expected, increment
|
||||
ulFPUInterruptNesting on entry, and decrement it on exit. */
|
||||
ulFPUInterruptNesting++;
|
||||
|
||||
/* This is the highest priority interrupt in the chain of forced nesting
|
||||
interrupts, so latch the maximum value reached by ulFPUInterruptNesting.
|
||||
This is done purely to allow verification that the nesting depth reaches
|
||||
that intended. */
|
||||
if( ulFPUInterruptNesting > ulMaxFPUInterruptNesting )
|
||||
{
|
||||
ulMaxFPUInterruptNesting = ulFPUInterruptNesting;
|
||||
}
|
||||
|
||||
/* Fill the FPU registers with 99 to overwrite the values written by
|
||||
TIM2_IRQHandler(). */
|
||||
vRegTestClearFlopRegistersToParameterValue( 99UL );
|
||||
|
||||
ulFPUInterruptNesting--;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void TIM2_IRQHandler( void )
|
||||
{
|
||||
/* Just to verify that the interrupt nesting behaves as expected, increment
|
||||
ulFPUInterruptNesting on entry, and decrement it on exit. */
|
||||
ulFPUInterruptNesting++;
|
||||
|
||||
/* Fill the FPU registers with 1. */
|
||||
vRegTestClearFlopRegistersToParameterValue( 1UL );
|
||||
|
||||
/* Trigger a timer 3 interrupt, which will fill the registers with a
|
||||
different value. */
|
||||
NVIC_SetPendingIRQ( TIM3_IRQn );
|
||||
|
||||
/* Ensure that, after returning from the nesting interrupt, all the FPU
|
||||
registers contain the value to which they were set by this interrupt
|
||||
function. */
|
||||
configASSERT( ulRegTestCheckFlopRegistersContainParameterValue( 1UL ) );
|
||||
|
||||
ulFPUInterruptNesting--;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvOptionallyCreateComprehensveTestApplication( void )
|
||||
{
|
||||
#if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )
|
||||
{
|
||||
xTimerHandle xCheckTimer = NULL;
|
||||
|
||||
/* Configure the interrupts used to test FPU registers being used from
|
||||
nested interrupts. */
|
||||
prvSetupNestedFPUInterruptsTest();
|
||||
|
||||
/* Start all the other standard demo/test tasks. */
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vCreateBlockTimeTasks();
|
||||
vStartCountingSemaphoreTasks();
|
||||
vStartGenericQueueTasks( tskIDLE_PRIORITY );
|
||||
vStartRecursiveMutexTasks();
|
||||
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
|
||||
/* Most importantly, start the tasks that use the FPU. */
|
||||
vStartMathTasks( mainFLOP_TASK_PRIORITY );
|
||||
|
||||
/* Create the register check tasks, as described at the top of this
|
||||
file */
|
||||
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
|
||||
/* Create the semaphore that is used to demonstrate a task being
|
||||
synchronised with an interrupt. */
|
||||
vSemaphoreCreateBinary( xTestSemaphore );
|
||||
|
||||
/* Create the task that is unblocked by the demonstration interrupt. */
|
||||
xTaskCreate( prvButtonTestTask, ( signed char * ) "BtnTest", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
|
||||
/* Create the software timer that performs the 'check' functionality,
|
||||
as described at the top of this file. */
|
||||
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
|
||||
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
|
||||
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
|
||||
( void * ) 0, /* The ID is not used, so can be set to anything. */
|
||||
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
|
||||
);
|
||||
|
||||
if( xCheckTimer != NULL )
|
||||
{
|
||||
xTimerStart( xCheckTimer, mainDONT_BLOCK );
|
||||
}
|
||||
|
||||
/* This task has to be created last as it keeps account of the number of
|
||||
tasks it expects to see running. */
|
||||
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
|
||||
}
|
||||
#else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */
|
||||
{
|
||||
/* Just to prevent compiler warnings when the configuration options are
|
||||
set such that these static functions are not used. */
|
||||
( void ) vRegTest1Task;
|
||||
( void ) vRegTest2Task;
|
||||
( void ) prvCheckTimerCallback;
|
||||
( void ) prvSetupNestedFPUInterruptsTest;
|
||||
}
|
||||
#endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void EXTI9_5_IRQHandler(void)
|
||||
{
|
||||
long lHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
/* Only line 6 is enabled, so there is no need to test which line generated
|
||||
the interrupt. */
|
||||
EXTI_ClearITPendingBit( EXTI_Line6 );
|
||||
|
||||
/* This interrupt does nothing more than demonstrate how to synchronise a
|
||||
task with an interrupt. First the handler releases a semaphore.
|
||||
lHigherPriorityTaskWoken has been initialised to zero. */
|
||||
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
|
||||
|
||||
/* If there was a task that was blocked on the semaphore, and giving the
|
||||
semaphore caused the task to unblock, and the unblocked task has a priority
|
||||
higher than the currently executing task (the task that this interrupt
|
||||
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE.
|
||||
Passing pdTRUE into the following macro call will cause this interrupt to
|
||||
return directly to the unblocked, higher priority, task. */
|
||||
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook( void )
|
||||
{
|
||||
/* vApplicationMallocFailedHook() will only be called if
|
||||
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
|
||||
function that will get called if a call to pvPortMalloc() fails.
|
||||
pvPortMalloc() is called internally by the kernel whenever a task, queue,
|
||||
timer or semaphore is created. It is also called by various parts of the
|
||||
demo application. If heap_1.c or heap_2.c are used, then the size of the
|
||||
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
|
||||
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
|
||||
to query the size of free heap space that remains (although it does not
|
||||
provide information on how the remaining heap might be fragmented). */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
|
||||
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
|
||||
task. It is essential that code added to this hook function never attempts
|
||||
to block in any way (for example, call xQueueReceive() with a block time
|
||||
specified, or call vTaskDelay()). If the application makes use of the
|
||||
vTaskDelete() API function (as this demo application does) then it is also
|
||||
important that vApplicationIdleHook() is permitted to return to its calling
|
||||
function, because it is the responsibility of the idle task to clean up
|
||||
memory allocated by the kernel to any task that has since been deleted. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
|
||||
{
|
||||
( void ) pcTaskName;
|
||||
( void ) pxTask;
|
||||
|
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
@ -0,0 +1,15 @@
|
||||
@REM This batch file has been generated by the IAR Embedded Workbench
|
||||
@REM C-SPY Debugger, as an aid to preparing a command line for running
|
||||
@REM the cspybat command line utility using the appropriate settings.
|
||||
@REM
|
||||
@REM You can launch cspybat by typing the name of this batch file followed
|
||||
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
|
||||
@REM Note that this file is generated every time a new debug session
|
||||
@REM is initialized, so you may want to move or rename the file before
|
||||
@REM making changes.
|
||||
@REM
|
||||
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32F4xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M4" "--fpu=VFPv4" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32f4xxx.ddf" "--drv_verify_download" "--semihosting" "--device=STM32F4xxx" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=120000000,1,2000000"
|
||||
|
||||
|
||||
@ -0,0 +1,92 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<Project>
|
||||
<Desktop>
|
||||
<Static>
|
||||
<Debug-Log>
|
||||
|
||||
|
||||
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>
|
||||
<Build>
|
||||
|
||||
|
||||
|
||||
|
||||
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>
|
||||
<Workspace>
|
||||
<ColumnWidths>
|
||||
|
||||
|
||||
|
||||
|
||||
<Column0>273</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
|
||||
</Workspace>
|
||||
<Disassembly>
|
||||
<col-names>
|
||||
|
||||
|
||||
<item>Disassembly</item><item>_I0</item></col-names>
|
||||
<col-widths>
|
||||
|
||||
|
||||
<item>500</item><item>20</item></col-widths>
|
||||
<DisasmHistory/>
|
||||
<PreferedWindows>
|
||||
|
||||
|
||||
|
||||
|
||||
<Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>
|
||||
|
||||
|
||||
<ShowCodeCoverage>0</ShowCodeCoverage><ShowInstrProfiling>0</ShowInstrProfiling></Disassembly>
|
||||
<Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><WATCH_1><expressions><item>enablestatus</item><item/></expressions><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>160</item><item>150</item><item>100</item><item>174</item></col-widths><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></WATCH_1><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Breakpoint</item><item>_I0</item></col-names><col-widths><item>500</item><item>35</item></col-widths></Breakpoints><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>100</item><item>150</item><item>100</item><item>100</item></col-widths><QWatchHistory/></QuickWatch></Static>
|
||||
<Windows>
|
||||
|
||||
|
||||
<Wnd2>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-1555-27928</Identity>
|
||||
<TabName>Debug Log</TabName>
|
||||
<Factory>Debug-Log</Factory>
|
||||
<Session/>
|
||||
</Tab>
|
||||
<Tab>
|
||||
<Identity>TabID-1033-27938</Identity>
|
||||
<TabName>Build</TabName>
|
||||
<Factory>Build</Factory>
|
||||
<Session/>
|
||||
</Tab>
|
||||
</Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-12304-27932</Identity>
|
||||
<TabName>Workspace</TabName>
|
||||
<Factory>Workspace</Factory>
|
||||
<Session>
|
||||
|
||||
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source/Portable</ExpandedNode></NodeDict></Session>
|
||||
</Tab>
|
||||
</Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd3></Windows>
|
||||
<Editor>
|
||||
|
||||
|
||||
|
||||
|
||||
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>239</YPos><SelStart>12512</SelStart><SelEnd>12512</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\tasks.c</Filename><XPos>0</XPos><YPos>140</YPos><SelStart>7168</SelStart><SelEnd>7175</SelEnd></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
|
||||
<Positions>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<Top><Row0><Sizes><Toolbar-013492f8><key>iaridepm.enu1</key></Toolbar-013492f8></Sizes></Row0><Row1><Sizes><Toolbar-04c71520><key>debuggergui.enu1</key></Toolbar-04c71520><Toolbar-04d32498><key>armjlink.enu1</key></Toolbar-04d32498></Sizes></Row1></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>716</Bottom><Right>347</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>207738</sizeVertCX><sizeVertCY>731161</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd2></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
|
||||
</Desktop>
|
||||
</Project>
|
||||
|
||||
|
||||
@ -0,0 +1,123 @@
|
||||
[Stack]
|
||||
FillEnabled=0
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnLogOnly=1
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[DebugChecksum]
|
||||
Checksum=1889324230
|
||||
[Exceptions]
|
||||
StopOnUncaught=_ 0
|
||||
StopOnThrow=_ 0
|
||||
[CallStack]
|
||||
ShowArgs=0
|
||||
[Disassembly]
|
||||
MixedMode=1
|
||||
[StackPlugin]
|
||||
Enabled=1
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnHow=0
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[SWOTraceHWSettings]
|
||||
OverrideDefaultClocks=0
|
||||
CpuClock=120000000
|
||||
ClockAutoDetect=1
|
||||
ClockWanted=4500000
|
||||
JtagSpeed=2250000
|
||||
Prescaler=53
|
||||
TimeStampPrescIndex=0
|
||||
TimeStampPrescData=0
|
||||
PcSampCYCTAP=1
|
||||
PcSampPOSTCNT=15
|
||||
PcSampIndex=0
|
||||
DataLogMode=0
|
||||
ITMportsEnable=0
|
||||
ITMportsTermIO=0
|
||||
ITMportsLogFile=0
|
||||
ITMlogFile=$PROJ_DIR$\ITM.log
|
||||
[watch_formats]
|
||||
Fmt0={W}0:ultemp 4 0
|
||||
[PowerLog]
|
||||
LogEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=0
|
||||
Title0=I0
|
||||
Setup0=0 1 0 500 2 0 4 0 0
|
||||
LiveEnabled=0
|
||||
LiveFile=PowerLogLive.log
|
||||
[DataLog]
|
||||
LogEnabled=0
|
||||
SumEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=1
|
||||
[EventLog]
|
||||
LogEnabled=0
|
||||
SumEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=1
|
||||
Title0=ITM1
|
||||
Setup0=1 1 1 1
|
||||
Title1=ITM2
|
||||
Setup1=1 1 1 1
|
||||
Title2=ITM3
|
||||
Setup2=1 1 1 1
|
||||
Title3=ITM4
|
||||
Setup3=1 1 1 1
|
||||
SumSortOrder=0
|
||||
[InterruptLog]
|
||||
LogEnabled=0
|
||||
SumEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=1
|
||||
SumSortOrder=0
|
||||
[Log file]
|
||||
LoggingEnabled=_ 0
|
||||
LogFile=_ ""
|
||||
Category=_ 0
|
||||
[TermIOLog]
|
||||
LoggingEnabled=_ 0
|
||||
LogFile=_ ""
|
||||
[Trace2]
|
||||
Enabled=0
|
||||
[SWOTraceWindow]
|
||||
PcSampling=0
|
||||
InterruptLogs=0
|
||||
ForcedTimeStamps=0
|
||||
EventCPI=0
|
||||
EventEXC=0
|
||||
EventFOLD=0
|
||||
EventLSU=0
|
||||
EventSLEEP=0
|
||||
[PowerProbe]
|
||||
Frequency=10000
|
||||
Probe0=I0
|
||||
ProbeSetup0=2 1 1 2 0 0
|
||||
[CallStackLog]
|
||||
Enabled=0
|
||||
[DriverProfiling]
|
||||
Enabled=0
|
||||
Mode=3
|
||||
Graph=0
|
||||
Symbiont=0
|
||||
Exclusions=
|
||||
[Disassemble mode]
|
||||
mode=0
|
||||
[Breakpoints2]
|
||||
Bp0=_ 1 "EMUL_CODE" "{$PROJ_DIR$\..\..\Source\tasks.c}.1090.7" 0 0 1 "" 0 "" 0
|
||||
Count=1
|
||||
[Aliases]
|
||||
Count=0
|
||||
SuppressDialog=0
|
||||
@ -0,0 +1,66 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<Workspace>
|
||||
<ConfigDictionary>
|
||||
|
||||
<CurrentConfigs><Project>RTOSDemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
|
||||
<Desktop>
|
||||
<Static>
|
||||
<Workspace>
|
||||
<ColumnWidths>
|
||||
|
||||
|
||||
|
||||
|
||||
<Column0>292</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
|
||||
</Workspace>
|
||||
<Build>
|
||||
|
||||
|
||||
|
||||
|
||||
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>
|
||||
<TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log></Static>
|
||||
<Windows>
|
||||
|
||||
|
||||
<Wnd0>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-21337-25041</Identity>
|
||||
<TabName>Workspace</TabName>
|
||||
<Factory>Workspace</Factory>
|
||||
<Session>
|
||||
|
||||
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Common Demo Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/STM32F4xx_StdPeriph_Driver</ExpandedNode><ExpandedNode>RTOSDemo/modules</ExpandedNode></NodeDict></Session>
|
||||
</Tab>
|
||||
</Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd0><Wnd1>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-25290-25172</Identity>
|
||||
<TabName>Build</TabName>
|
||||
<Factory>Build</Factory>
|
||||
<Session/>
|
||||
</Tab>
|
||||
<Tab><Identity>TabID-22929-15481</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd1></Windows>
|
||||
<Editor>
|
||||
|
||||
|
||||
|
||||
|
||||
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>46</YPos><SelStart>12512</SelStart><SelEnd>12512</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
|
||||
<Positions>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<Top><Row0><Sizes><Toolbar-013492f8><key>iaridepm.enu1</key></Toolbar-013492f8></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>625</Bottom><Right>366</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>219048</sizeVertCX><sizeVertCY>638493</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>313</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>315</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>320774</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
|
||||
</Desktop>
|
||||
</Workspace>
|
||||
|
||||
|
||||
@ -0,0 +1,15 @@
|
||||
@REM This batch file has been generated by the IAR Embedded Workbench
|
||||
@REM C-SPY Debugger, as an aid to preparing a command line for running
|
||||
@REM the cspybat command line utility using the appropriate settings.
|
||||
@REM
|
||||
@REM You can launch cspybat by typing the name of this batch file followed
|
||||
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
|
||||
@REM Note that this file is generated every time a new debug session
|
||||
@REM is initialized, so you may want to move or rename the file before
|
||||
@REM making changes.
|
||||
@REM
|
||||
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32F4xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M4" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32f4xxx.ddf" "--drv_verify_download" "--semihosting" "--device=STM32F4xxx" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=120000000,1,2000000"
|
||||
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<Project/>
|
||||
|
||||
|
||||
@ -0,0 +1,120 @@
|
||||
[DebugChecksum]
|
||||
Checksum=1459121027
|
||||
[Exceptions]
|
||||
StopOnUncaught=_ 0
|
||||
StopOnThrow=_ 0
|
||||
[PowerLog]
|
||||
LogEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=0
|
||||
Title0=I0
|
||||
Setup0=0 1 0 500 2 0 4 0 0
|
||||
LiveEnabled=0
|
||||
LiveFile=PowerLogLive.log
|
||||
[DataLog]
|
||||
LogEnabled=0
|
||||
SumEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=1
|
||||
[EventLog]
|
||||
LogEnabled=0
|
||||
SumEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=1
|
||||
SumSortOrder=0
|
||||
Title0=ITM1
|
||||
Setup0=1 1 1 1
|
||||
Title1=ITM2
|
||||
Setup1=1 1 1 1
|
||||
Title2=ITM3
|
||||
Setup2=1 1 1 1
|
||||
Title3=ITM4
|
||||
Setup3=1 1 1 1
|
||||
[InterruptLog]
|
||||
LogEnabled=0
|
||||
SumEnabled=0
|
||||
GraphEnabled=0
|
||||
ShowTimeLog=1
|
||||
ShowTimeSum=1
|
||||
SumSortOrder=0
|
||||
[Stack]
|
||||
FillEnabled=0
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnLogOnly=1
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[Log file]
|
||||
LoggingEnabled=_ 0
|
||||
LogFile=_ ""
|
||||
Category=_ 0
|
||||
[TermIOLog]
|
||||
LoggingEnabled=_ 0
|
||||
LogFile=_ ""
|
||||
[CallStack]
|
||||
ShowArgs=0
|
||||
[Disassembly]
|
||||
MixedMode=1
|
||||
[StackPlugin]
|
||||
Enabled=1
|
||||
OverflowWarningsEnabled=1
|
||||
WarningThreshold=90
|
||||
SpWarningsEnabled=1
|
||||
WarnHow=0
|
||||
UseTrigger=1
|
||||
TriggerName=main
|
||||
LimitSize=0
|
||||
ByteLimit=50
|
||||
[Trace2]
|
||||
Enabled=0
|
||||
[SWOTraceWindow]
|
||||
PcSampling=0
|
||||
InterruptLogs=0
|
||||
ForcedTimeStamps=0
|
||||
EventCPI=0
|
||||
EventEXC=0
|
||||
EventFOLD=0
|
||||
EventLSU=0
|
||||
EventSLEEP=0
|
||||
[SWOTraceHWSettings]
|
||||
OverrideDefaultClocks=0
|
||||
CpuClock=120000000
|
||||
ClockAutoDetect=1
|
||||
ClockWanted=4500000
|
||||
JtagSpeed=2250000
|
||||
Prescaler=53
|
||||
TimeStampPrescIndex=0
|
||||
TimeStampPrescData=0
|
||||
PcSampCYCTAP=1
|
||||
PcSampPOSTCNT=15
|
||||
PcSampIndex=0
|
||||
DataLogMode=0
|
||||
ITMportsEnable=0
|
||||
ITMportsTermIO=0
|
||||
ITMportsLogFile=0
|
||||
ITMlogFile=$PROJ_DIR$\ITM.log
|
||||
[PowerProbe]
|
||||
Frequency=10000
|
||||
Probe0=I0
|
||||
ProbeSetup0=2 1 1 2 0 0
|
||||
[CallStackLog]
|
||||
Enabled=0
|
||||
[DriverProfiling]
|
||||
Enabled=0
|
||||
Mode=3
|
||||
Graph=0
|
||||
Symbiont=0
|
||||
Exclusions=
|
||||
[Disassemble mode]
|
||||
mode=0
|
||||
[Breakpoints2]
|
||||
Count=0
|
||||
[Aliases]
|
||||
Count=0
|
||||
SuppressDialog=0
|
||||
@ -0,0 +1,66 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<Workspace>
|
||||
<ConfigDictionary>
|
||||
|
||||
<CurrentConfigs><Project>Test/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
|
||||
<Desktop>
|
||||
<Static>
|
||||
<Workspace>
|
||||
<ColumnWidths>
|
||||
|
||||
|
||||
|
||||
|
||||
<Column0>299</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
|
||||
</Workspace>
|
||||
<Build>
|
||||
|
||||
|
||||
|
||||
|
||||
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>
|
||||
</Static>
|
||||
<Windows>
|
||||
|
||||
|
||||
<Wnd2>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-24013-20283</Identity>
|
||||
<TabName>Workspace</TabName>
|
||||
<Factory>Workspace</Factory>
|
||||
<Session>
|
||||
|
||||
<NodeDict><ExpandedNode>Test</ExpandedNode></NodeDict></Session>
|
||||
</Tab>
|
||||
</Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
|
||||
<Tabs>
|
||||
<Tab>
|
||||
<Identity>TabID-21922-20322</Identity>
|
||||
<TabName>Build</TabName>
|
||||
<Factory>Build</Factory>
|
||||
<Session/>
|
||||
</Tab>
|
||||
</Tabs>
|
||||
|
||||
<SelectedTab>0</SelectedTab></Wnd3></Windows>
|
||||
<Editor>
|
||||
|
||||
|
||||
|
||||
|
||||
<Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
|
||||
<Positions>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<Top><Row0><Sizes><Toolbar-01349408><key>iaridepm.enu1</key></Toolbar-01349408></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>373</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>223214</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
|
||||
</Desktop>
|
||||
</Workspace>
|
||||
|
||||
|
||||
@ -0,0 +1,31 @@
|
||||
[BREAKPOINTS]
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 0
|
||||
Device="AD7160"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
@ -0,0 +1,629 @@
|
||||
;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f4xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.0.0
|
||||
;* Date : 30-September-2011
|
||||
;* Description : STM32F4xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock and the external SRAM mounted on
|
||||
;* STM324xG-EVAL board to be used as data memory (optional,
|
||||
;* to be enabled by user)
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
;*******************************************************************************/
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD CRYP_IRQHandler ; CRYP crypto
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PVD_IRQHandler
|
||||
B PVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TAMP_STAMP_IRQHandler
|
||||
B TAMP_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream0_IRQHandler
|
||||
B DMA1_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream1_IRQHandler
|
||||
B DMA1_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream2_IRQHandler
|
||||
B DMA1_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream3_IRQHandler
|
||||
B DMA1_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream4_IRQHandler
|
||||
B DMA1_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream5_IRQHandler
|
||||
B DMA1_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream6_IRQHandler
|
||||
B DMA1_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN1_SCE_IRQHandler
|
||||
B CAN1_SCE_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_TIM9_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
B TIM1_BRK_TIM9_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM10_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
B TIM1_UP_TIM10_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
B TIM1_TRG_COM_TIM11_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
B OTG_FS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_TIM12_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
B TIM8_BRK_TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_TIM13_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
B TIM8_UP_TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
B TIM8_TRG_COM_TIM14_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA1_Stream7_IRQHandler
|
||||
B DMA1_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK FSMC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
FSMC_IRQHandler
|
||||
B FSMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_DAC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM6_DAC_IRQHandler
|
||||
B TIM6_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream0_IRQHandler
|
||||
B DMA2_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream1_IRQHandler
|
||||
B DMA2_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream2_IRQHandler
|
||||
B DMA2_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream3_IRQHandler
|
||||
B DMA2_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream4_IRQHandler
|
||||
B DMA2_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK ETH_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ETH_WKUP_IRQHandler
|
||||
B ETH_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_TX_IRQHandler
|
||||
B CAN2_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_RX0_IRQHandler
|
||||
B CAN2_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_RX1_IRQHandler
|
||||
B CAN2_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN2_SCE_IRQHandler
|
||||
B CAN2_SCE_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream5_IRQHandler
|
||||
B DMA2_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream6_IRQHandler
|
||||
B DMA2_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA2_Stream7_IRQHandler
|
||||
B DMA2_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
B OTG_HS_EP1_OUT_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_IN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
B OTG_HS_EP1_IN_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
B OTG_HS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
OTG_HS_IRQHandler
|
||||
B OTG_HS_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DCMI_IRQHandler
|
||||
B DCMI_IRQHandler
|
||||
|
||||
PUBWEAK CRYP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CRYP_IRQHandler
|
||||
B CRYP_IRQHandler
|
||||
|
||||
PUBWEAK HASH_RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HASH_RNG_IRQHandler
|
||||
B HASH_RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
END
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,552 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 24-October-2011
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F4xx devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f4xx_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*=============================================================================
|
||||
* Supported STM32F4xx device revision | Rev A
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 150000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 150000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 25000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 25
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 300
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* I2S input clock | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD(V) | 3.3
|
||||
*-----------------------------------------------------------------------------
|
||||
* Main regulator output voltage | Scale1 mode
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | OFF
|
||||
*-----------------------------------------------------------------------------
|
||||
* Instruction cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Data cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM mounted
|
||||
on STM324xG_EVAL board as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/************************* PLL Parameters *************************************/
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
|
||||
#define PLL_M 25
|
||||
#define PLL_N 300
|
||||
|
||||
/* SYSCLK = PLL_VCO / PLL_P */
|
||||
#define PLL_P 2
|
||||
|
||||
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
|
||||
#define PLL_Q 7
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 150000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @Note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_4WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM324xG_EVAL board
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/*
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
+ SRAM pins assignment +
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
|
||||
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
|
||||
| PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
|
||||
| PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
|
||||
| PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
|
||||
| PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
|
||||
| PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
|
||||
| PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
|
||||
| PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
|
||||
| PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
|
||||
| PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
|
||||
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
|
||||
| | PE15 <-> FSMC_D12 |
|
||||
+-------------------+--------------------+
|
||||
*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR = 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00cc00cc;
|
||||
GPIOD->AFR[1] = 0xcc0ccccc;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xaaaa0a0a;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xffff0f0f;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xc00cc0cc;
|
||||
GPIOE->AFR[1] = 0xcccccccc;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xaaaa828a;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xffffc3cf;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR = 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001015;
|
||||
FSMC_Bank1->BTCR[3] = 0x00010603;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 3;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 6;
|
||||
p.FSMC_BusTurnAroundDuration = 1;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@ -0,0 +1,88 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 30-September-2011
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CONF_H
|
||||
#define __STM32F4xx_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment the line below to enable peripheral header file inclusion */
|
||||
#include "stm32f4xx_adc.h"
|
||||
#include "stm32f4xx_can.h"
|
||||
#include "stm32f4xx_crc.h"
|
||||
#include "stm32f4xx_cryp.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_dbgmcu.h"
|
||||
#include "stm32f4xx_dcmi.h"
|
||||
#include "stm32f4xx_dma.h"
|
||||
#include "stm32f4xx_exti.h"
|
||||
#include "stm32f4xx_flash.h"
|
||||
#include "stm32f4xx_fsmc.h"
|
||||
#include "stm32f4xx_hash.h"
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_i2c.h"
|
||||
#include "stm32f4xx_iwdg.h"
|
||||
#include "stm32f4xx_pwr.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_rtc.h"
|
||||
#include "stm32f4xx_sdio.h"
|
||||
#include "stm32f4xx_spi.h"
|
||||
#include "stm32f4xx_syscfg.h"
|
||||
#include "stm32f4xx_tim.h"
|
||||
#include "stm32f4xx_usart.h"
|
||||
#include "stm32f4xx_wwdg.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* If an external clock source is used, then the value of the following define
|
||||
should be set to the value of the external clock source, else, if no external
|
||||
clock is used, keep this define commented */
|
||||
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
|
||||
|
||||
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F4xx_CONF_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
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Reference in New Issue