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RZ RVDS and IAR projects.

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pull/4/head
Richard Barry 12 years ago
parent 5013baa2cd
commit 018f0f602a
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113
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.cproject
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245
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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.settings/org.eclipse.core.resources.prefs
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#Sun Jun 16 20:16:37 BST 2013
eclipse.preferences.version=1
encoding//Source/RenesasFiles/handler/reset_handler.s=UTF-8
encoding//Source/RenesasFiles/include/iodefine.h=UTF-8

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/LowLevelInitialise.c
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/*************************************************************************
*
* Used with ICCARM and AARM.
*
* (c) Copyright IAR Systems 2013
*
* File name : main.c
* Description : main module
**************************************************************************/
/*
* Called from Cstart.s to configure the chip and board specific IO before
* main() is called.
*/
/** include files **/
#include <Renesas/ior7s721000.h>
#include <intrinsics.h>
#include <stdint.h>
#include "armv7a_cp15_drv.h"
#include "devdrv_common.h"
/* Renesas include files. */
#include "stb_init.h"
#include "port_init.h"
#include "devdrv_intc.h"
/** external data **/
#pragma section = ".intvec"
extern void Peripheral_BasicInit( void );
void LowLevelInitialisation(void);
unsigned long __write(int fildes, const void *buf, unsigned long nbytes);
/* Called from cstartup.s before the kernel is started. */
void LowLevelInitialisation(void)
{
/* Chip configuration functions from IAR. ********************************/
/* Disable MMU, enable ICache */
CP15_Mmu(FALSE);
CP15_ICache(FALSE);
CP15_SetVectorBase( (uint32_t )__section_begin( ".intvec" ) );
/* Set Low vectors mode in CP15 Control Register */
CP15_SetHighVectors(FALSE);
/* Chip and board specific configuration functions from Renesas. *********/
Peripheral_BasicInit();
STB_Init();
PORT_Init();
R_BSC_Init( ( uint8_t ) ( BSC_AREA_CS2 | BSC_AREA_CS3 ) );
R_INTC_Init();
CP15_ICache(TRUE);
/* Start with interrupts enabled. */
__enable_irq();
__enable_fiq();
}
/* Keep the linker happy. */
unsigned long __write(int fildes, const void *buf, unsigned long nbytes)
{
return 0;
}

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.ewp
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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.eww
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo.ewp</path>
</project>
<batchBuild>
<batchDefinition>
<name>All</name>
<member>
<project>RTOSDemo</project>
<configuration>NOR Debug</configuration>
</member>
<member>
<project>RTOSDemo</project>
<configuration>RAM Debug</configuration>
</member>
<member>
<project>RTOSDemo</project>
<configuration>SerialFlash Debug</configuration>
</member>
<member>
<project>RTOSDemo</project>
<configuration>SerialFlash for Bootloader</configuration>
</member>
<member>
<project>Bootloader</project>
<configuration>SerialFlash Bootloader</configuration>
</member>
</batchDefinition>
</batchBuild>
</workspace>

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/board/arm_comm.h
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/***************************************************************************
**
** Common definition for IAR EW ARM
**
** Used with ARM IAR C/C++ Compiler and Assembler.
**
** (c) Copyright IAR Systems 2006
**
** $Revision: 52705 $
**
***************************************************************************/
#include <intrinsics.h>
#ifndef __ARM_COMM_DEF_H
#define __ARM_COMM_DEF_H
#define MHZ *1000000l
#define KHZ *1000l
#define HZ *1l
#ifndef FALSE
#define FALSE (1 == 0)
#endif
#ifndef TRUE
#define TRUE (1 == 1)
#endif
#ifndef NULL
#define NULL ((void*)0)
#endif
typedef double Flo64; // Double precision floating point
typedef double * pFlo64;
typedef float Flo32; // Single precision floating point
typedef float * pFlo32;
typedef signed long long Int64S; // Signed 64 bit quantity
typedef signed long long * pInt64S;
typedef unsigned long long Int64U; // Unsigned 64 bit quantity
typedef unsigned long long * pInt64U;
typedef signed int Int32S; // Signed 32 bit quantity
typedef signed int * pInt32S;
typedef unsigned int Int32U; // Unsigned 32 bit quantity
typedef unsigned int * pInt32U;
typedef signed short Int16S; // Signed 16 bit quantity
typedef signed short * pInt16S;
typedef unsigned short Int16U; // Unsigned 16 bit quantity
typedef unsigned short * pInt16U;
typedef signed char Int8S; // Signed 8 bit quantity
typedef signed char * pInt8S;
typedef unsigned char Int8U; // Unsigned 8 bit quantity
typedef unsigned char * pInt8U;
typedef unsigned int Boolean; // Boolean
typedef unsigned int * pBoolean;
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#define _2BL(a) (Int8U)(a),(Int8U)(a>>8)
#define _2BB(a) (Int8U)(a>>8),(Int8U)(a),
#define _3BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16)
#define _3BB(a) (Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)
#define _4BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16),(Int8U)(a>>24)
#define _4BB(a) (Int8U)(a>>24),(Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)
typedef void * (*CommUserFpnt_t)(void *);
typedef void (*VoidFpnt_t)(void);
// Atomic exchange of data between a memory cell and a register
// return value of the memory cell
#if __CORE__ < 7
inline __arm Int32U AtomicExchange (Int32U State, pInt32U Flag)
{
asm("swp r0, r0, [r1]");
return(State);
}
#define IRQ_FLAG 0x80
#define FIQ_FLAG 0x40
inline __arm Int32U EntrCritSection(void)
{
unsigned long tmp;
tmp = __get_CPSR();
__set_CPSR(tmp | IRQ_FLAG);
return(tmp);
}
inline __arm void ExtCritSection(Int32U Save)
{
unsigned long tmp;
tmp = __get_CPSR();
__set_CPSR(tmp & (Save | ~IRQ_FLAG));
}
inline __arm Int32U EntrCritSectionFiq(void)
{
unsigned long tmp;
tmp = __get_CPSR();
__set_CPSR(tmp | (IRQ_FLAG | FIQ_FLAG));
return(tmp);
}
inline __arm void ExtCritSectionFiq(Int32U Save)
{
unsigned long tmp;
tmp = __get_CPSR();
__set_CPSR(tmp & (Save | ~(IRQ_FLAG | FIQ_FLAG)));
}
#define ENTR_CRT_SECTION(Save) Save = EntrCritSection()
#define EXT_CRT_SECTION(Save) ExtCritSection(Save)
#define ENTR_CRT_SECTION_F(Save) Save = EntrCritSectionFiq()
#define EXT_CRT_SECTION_F(Save) ExtCritSectionFiq(Save)
#elif __CORE__ == 7
extern Int32U CriticalSecCntr;
inline void EntrCritSection(void)
{
if(CriticalSecCntr == 0)
{
asm("CPSID i");
}
// avoid lost of one count in case of simultaneously calling from both places
++CriticalSecCntr;
}
inline void ExtCritSection(void)
{
if(--CriticalSecCntr == 0)
{
asm("CPSIE i");
}
}
inline Int32U AtomicExchange (Int32U State, pInt32U Flag)
{
Int32U Hold;
EntrCritSection();
Hold = *Flag;
*Flag = State;
ExtCritSection();
return(Hold);
}
#define ENTR_CRT_SECTION() EntrCritSection()
#define EXT_CRT_SECTION() ExtCritSection()
#endif
#define LongToBin(n) (((n >> 21) & 0x80) | \
((n >> 18) & 0x40) | \
((n >> 15) & 0x20) | \
((n >> 12) & 0x10) | \
((n >> 9) & 0x08) | \
((n >> 6) & 0x04) | \
((n >> 3) & 0x02) | \
((n ) & 0x01))
#define __BIN(n) LongToBin(0x##n##l)
#define BIN8(n) __BIN(n)
#define BIN(n) __BIN(n)
#define BIN16(b1,b2) (( __BIN(b1) << 8UL) + \
__BIN(b2))
#define BIN32(b1,b2,b3,b4) ((((Int32U)__BIN(b1)) << 24UL) + \
(((Int32U)__BIN(b2)) << 16UL) + \
(((Int32U)__BIN(b3)) << 8UL) + \
(Int32U)__BIN(b4))
#endif // __ARM_COMM_DEF_H

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000040;
define symbol __ICFEDIT_region_ROM_end__ = 0x07FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x8000;
define symbol __ICFEDIT_size_svcstack__ = 0x40;
define symbol __ICFEDIT_size_irqstack__ = 0x40;
define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/
define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section MMU_TT };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
place in RetRAM_region { section .retram };
place in MirrorRAM_region { section .mirrorram };
place in MirrorRetRAM_region { section .mirrorretram };

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.mac
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setup()
{
__var Reg;
// Enable I Cache
// Disable MMU and enable ICache
Reg = __jtagCP15ReadReg(1, 0, 0, 0);
Reg &= 0xFFFFFFFA;
Reg |= 1<<12;
__jtagCP15WriteReg(1, 0, 0, 0, Reg);
__writeMemory16(0x0000FF41, 0xFCFE721C, "Memory"); // set PIPC7.6 direction controlled by alt.WE0
__writeMemory16(0x0000FF41, 0xFCFE341C, "Memory"); // set PMC7.6 to be alt.WE0
__writeMemory16(0x0000FFFF, 0xFCFE7220, "Memory"); // set PIPC8 direction controlled by alt.A8-A23
__writeMemory16(0x0000FFFF, 0xFCFE3420, "Memory"); // set PMC8 to be alt.A8-A23
__writeMemory16(0x00000003, 0xFCFE7224, "Memory"); // set PIPC9 direction controlled by alt.A24-A25
__writeMemory16(0x00000003, 0xFCFE3424, "Memory"); // set PMC9 to be alt.A24-A25
__writeMemory16(0x00000080, 0xFCFE720C, "Memory"); // set PIPC3 direction controlled by alt.CS1
__writeMemory16(0x00000080, 0xFCFE340C, "Memory"); // set PMC3 to be alt.CS1
__writeMemory16(0x00000080, 0xFCFE360C, "Memory"); // set PFCE3 to be alt.CS1
__writeMemory16(0x00000080, 0xFCFE3A0C, "Memory"); // set PFCAE3 to be alt.CS1
}
execUserPreload()
{
__message "----- Prepare hardware for debug -----\n";
__hwReset(0);
setup();
}

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x18000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x18000040;
define symbol __ICFEDIT_region_ROM_end__ = 0x1807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x8000;
define symbol __ICFEDIT_size_svcstack__ = 0x40;
define symbol __ICFEDIT_size_irqstack__ = 0x40;
define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/
define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section MMU_TT };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
place in RetRAM_region { section .retram };
place in MirrorRAM_region { section .mirrorram };
place in MirrorRetRAM_region { section .mirrorretram };

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.mac
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setup()
{
__var Reg;
// Enable I Cache
// Disable MMU and enable ICache
Reg = __jtagCP15ReadReg(1, 0, 0, 0);
Reg &= 0xFFFFFFFA;
Reg |= 1<<12;
__jtagCP15WriteReg(1, 0, 0, 0, Reg);
//__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR
//__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2
// Turn on clock for SPI
__writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9
// Configure PORTS for SPI (serial flash 1)
__writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode
__writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode
__writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode
// Configure PORTS for SPI (serial flash 2)
__writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode
__writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode
__writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode
__writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode
// Configure SPI for EXTREAD mode
__writeMemory32(0x01AA4020, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 1-memory, CPHA=0, CPOL=0, SFDE=1
// Configure SPI registers
__writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13
__writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1
__writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst
__writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range
// Set Bit Rate
__writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3
// Flush Read Cache
Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR_0
Reg |= 0x00000200; // Set RCF bit
__writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR_0
}
execUserPreload()
{
__message "----- Prepare hardware for debug -----\n";
__hwReset(0);
setup();
}
execUserReset()
{
setup();
}

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x18080000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x18080040;
define symbol __ICFEDIT_region_ROM_end__ = 0x1BFFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x8000;
define symbol __ICFEDIT_size_svcstack__ = 0x40;
define symbol __ICFEDIT_size_irqstack__ = 0x40;
define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x8000;
/**** End of ICF editor section. ###ICF###*/
define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section MMU_TT };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
place in RetRAM_region { section .retram };
place in MirrorRAM_region { section .mirrorram };
place in MirrorRetRAM_region { section .mirrorretram };

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.mac
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setup()
{
__var Reg;
// Enable I Cache
// Disable MMU and enable ICache
Reg = __jtagCP15ReadReg(1, 0, 0, 0);
Reg &= 0xFFFFFFFA;
Reg |= 1<<12;
__jtagCP15WriteReg(1, 0, 0, 0, Reg);
//__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR
//__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2
// Turn on clock for SPI
__writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9
// Configure PORTS for SPI (serial flash 1)
__writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode
__writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode
__writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode
// Configure PORTS for SPI (serial flash 2)
__writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode
__writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode
__writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode
__writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode
// Configure SPI for EXTREAD mode
__writeMemory32(0x01AA4021, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 2-memory, CPHAT=0, CPHAR=1, CPOL=0, SFDE=1
// Configure SPIBSC 32-bit addressing
__writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13
__writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1
__writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst
__writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range
// Set Bit Rate
__writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3
// Flush Read Cache
Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR
Reg |= 0x00000200; // Set RCF bit
__writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR
}
execUserPreload()
{
__message "----- Prepare hardware for debug -----\n";
__hwReset(0);
setup();
}
execUserReset()
{
setup();
}

173
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/cstartup.s
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
;; Copyright 2007 IAR Systems. All rights reserved.
;;
;; $Revision: 49919 $
;;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
;
; The module in this file are included in the libraries, and may be
; replaced by any user-defined modules that define the PUBLIC symbol
; __iar_program_start or a user defined start symbol.
;
; To override the cstartup defined in the library, simply add your
; modified version to the workbench project.
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector
PUBLIC __iar_program_start
EXTERN Undefined_Handler
EXTERN SWI_Handler
EXTERN Prefetch_Handler
EXTERN Abort_Handler
EXTERN IRQ_Handler
EXTERN FIQ_Handler
EXTERN LowLevelInitialisation
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
__vector: ; Make this a DATA label, so that stack usage
; analysis doesn't consider it an uncalled fun
ARM
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR PC,Reset_Addr ; Reset
LDR PC,Undefined_Addr ; Undefined instructions
LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
LDR PC,Prefetch_Addr ; Prefetch abort
LDR PC,Abort_Addr ; Data abort
DCD 0 ; RESERVED
LDR PC,IRQ_Addr ; IRQ
LDR PC,FIQ_Addr ; FIQ
DATA
Reset_Addr: DCD __iar_program_start
Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
IRQ_Addr: DCD IRQ_Handler
FIQ_Addr: DCD FIQ_Handler
; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reset execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;
SECTION .text:CODE:NOROOT(2)
EXTERN __cmain
REQUIRE __vector
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
ARM
__iar_program_start:
?cstartup:
;
; Add initialization needed before setup of stackpointers here.
;
;
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
;
; --------------------
; Mode, correspords to bits 0-5 in CPSR
#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR
#define USR_MODE 0x10 ; User mode
#define FIQ_MODE 0x11 ; Fast Interrupt Request mode
#define IRQ_MODE 0x12 ; Interrupt Request mode
#define SVC_MODE 0x13 ; Supervisor mode
#define ABT_MODE 0x17 ; Abort mode
#define UND_MODE 0x1B ; Undefined Instruction mode
#define SYS_MODE 0x1F ; System mode
MRS r0, cpsr ; Original PSR value
;; Set up the interrupt stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the fast interrupt stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the normal SVC pointer.
;; FreeRTOS Note:
;; FreeRTOS does not need a System/User mode stack as only tasks run in
;; System/User mode, and their stack is allocated when the task is created.
;; Therefore the CSTACK allocated in the linker script is instead given to
;; Supervisor mode, and main() is called from Supervisor mode.
BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
ORR r0 ,r0, #SVC_MODE ; Set System mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(CSTACK) ; End of CSTACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Turn on core features assumed to be enabled.
FUNCALL __iar_program_start, __iar_init_core
BL __iar_init_core
;; Initialize VFP (if needed).
FUNCALL __iar_program_start, __iar_init_vfp
BL __iar_init_vfp
;; Chip and board specific configuration
BL LowLevelInitialisation
;;;
;;; Add more initialization here
;;;
;;; Continue to __cmain for C-level initialization.
FUNCALL __iar_program_start, __cmain
B __cmain
END

768
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.c
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/*************************************************************************
*
* Used with ICCARM and AARM.
*
* (c) Copyright IAR Systems 2012
*
* File name : armv7a_cp15_drv.c
* Description : Driver for the CP15 of ARMv7-A
*
* History :
* 1. Date : September, 8 2006
* Author : Stanimir Bonev
* Description : Driver for the ARM926EJ's CP15
*
* 2. Date : October, 2008
* Author : Stoyan Choynev
* Description : Port for ARM1136JF. The driver is backwards compatible
* with ARMv5 or earlier processors.
*
* 3. Date : March, 2012
* Author : Atanas Uzunov
* Description : Port for ARMv7-A architecture.
* Added cache maintenance functions.
*
* $Revision: 52705 $
**************************************************************************/
#include "armv7a_cp15_drv.h"
/*************************************************************************
* Function Name: CP15_GetID
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the ID register
*
*************************************************************************/
__arm Int32U CP15_GetID (void)
{
return(__MRC(15,0,CP15_ID,0,0));
}
/*************************************************************************
* Function Name: CP15_GetCacheType
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the Cache type
*
*************************************************************************/
__arm Int32U CP15_GetCacheType (void)
{
return(__MRC(15,0,CP15_ID,0,1));
}
/*************************************************************************
* Function Name: CP15_GetTCM_Status
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the TCM status
*
*************************************************************************/
__arm Int32U CP15_GetTCM_Status (void)
{
return(__MRC(15,0,CP15_ID,0,2));
}
/*************************************************************************
* Function Name: CP15_GetTtb0
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the TTB0 register
*
*************************************************************************/
__arm Int32U CP15_GetTtb0 (void)
{
return(__MRC(15,0,CP15_TTB_ADDR,0,0));
}
/*************************************************************************
* Function Name: CP15_GetTtb1
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the TTB1 register
*
*************************************************************************/
__arm Int32U CP15_GetTtb1 (void)
{
return(__MRC(15,0,CP15_TTB_ADDR,0,1));
}
/*************************************************************************
* Function Name: CP15_GetStatus
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the MMU control register
*
*************************************************************************/
__arm Int32U CP15_GetStatus (void)
{
return(__MRC(15,0,CP15_CTRL,0,0));
}
/*************************************************************************
* Function Name: CP15_GetDomain
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the MMU domain access register
*
*************************************************************************/
__arm Int32U CP15_GetDomain (void)
{
return(__MRC(15,0,CP15_DA_CTRL,0,0));
}
/*************************************************************************
* Function Name: CP15_SetDomains
* Parameters: Int32U DomainAccess
*
* Return: Int32U
*
* Description: Function set the MMU domain access register
*
*************************************************************************/
__arm void CP15_SetDomains (Int32U DomainAccess)
{
register Int32U Val = DomainAccess;
__MCR(15,0,Val,CP15_DA_CTRL,0,0);
}
/*************************************************************************
* Function Name: log2_n_up
* Parameters: Int32U n
*
* Return: Int32S
*
* Description: Logarithm at base 2 , rounded up
*
*************************************************************************/
Int32S log2_up(Int32U n)
{
Int32S log = -1;
Int32U t = n;
while(t)
{
log++; t >>=1;
}
/* if n not power of 2 -> round up*/
if ( n & (n - 1) ) log++;
return log;
}
/*************************************************************************
* Function Name: CP15_MaintainDCacheSetWay
* Parameters: Int32U level - level of cache,
* Int32U maint - maintenance type
*
* Return: none
*
* Description: Maintain data cache line by Set/Way
*
*************************************************************************/
__arm void CP15_MaintainDCacheSetWay(Int32U level, Int32U maint)
{
register volatile Int32U Dummy;
register volatile Int32U ccsidr;
Int32U num_sets;
Int32U num_ways;
Int32U shift_way;
Int32U log2_linesize;
Int32U log2_num_ways;
Dummy = level << 1;
/* set csselr, select ccsidr register */
__MCR(15,2,Dummy,0,0,0);
/* get current ccsidr register */
ccsidr = __MRC(15,1,0,0,0);
num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1;
num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1;
log2_linesize = (ccsidr & 0x00000007) + 2 + 2;
log2_num_ways = log2_up(num_ways);
shift_way = 32 - log2_num_ways;
for(int way = num_ways-1; way >= 0; way--)
for(int set = num_sets-1; set >= 0; set--)
{
Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way);
switch (maint)
{
case DCACHE_CLEAN_AND_INVALIDATE:
__MCR(15,0,Dummy,7,14,2);
break;
case DCACHE_INVALIDATE:
__MCR(15,0,Dummy,7,6,2);
break;
}
}
__DMB();
}
/*************************************************************************
* Function Name: CP15_MaintAllDCache
* Parameters: Int32U oper - type of maintenance, one of:
* DCACHE_CLEAN_AND_INVALIDATE
* DCACHE_INVALIDATE
*
* Return: none
*
* Description: Maintenance of all data cache
*
*************************************************************************/
__arm void CP15_MaintainAllDCache(Int32U oper)
{
register volatile Int32U clidr;
Int32U cache_type;
clidr = __MRC(15,1,0,0,1);
for(Int32U i = 0; i<7; i++)
{
cache_type = (clidr >> i*3) & 0x7UL;
if ((cache_type >= 2) && (cache_type <= 4))
{
CP15_MaintainDCacheSetWay(i,oper);
}
}
}
/*************************************************************************
* Function Name: CP15_InvalInstrCache
* Parameters: none
*
* Return: none
*
* Description: Invalidate instruction cache
*
*************************************************************************/
__arm void CP15_InvalInstrCache(void)
{
register volatile Int32U Dummy;
__MCR(15,0,Dummy,CP15_CACHE_OPR,5,0);
CP15_InvalPredictArray();
__DSB();
__ISB();
}
/*************************************************************************
* Function Name: CP15_InvalPredictArray
* Parameters: none
*
* Return: none
*
* Description: Invalidate prediction array
*
*************************************************************************/
__arm void CP15_InvalPredictArray(void)
{
register volatile Int32U Dummy;
__MCR(15,0,Dummy,CP15_CACHE_OPR,5,6); __ISB();
}
/*************************************************************************
* Function Name: CP15_InvalAllTbl
* Parameters: none
*
* Return: none
*
* Description: Invalidate TLB
*
*************************************************************************/
__arm void CP15_InvalAllTbl (void)
{
register volatile Int32U Dummy;
/* Invalidate entire unified TLB*/
__MCR(15,0,Dummy,CP15_TBL_OPR,7,0);
/* Invalidate entire data TLB*/
__MCR(15,0,Dummy,CP15_TBL_OPR,6,0);
/* Invalidate entire instruction TLB*/
__MCR(15,0,Dummy,CP15_TBL_OPR,5,0);
__DSB();
__ISB();
}
/*************************************************************************
* Function Name: CP15_SetStatus
* Parameters: Int32U Ctrl
*
* Return: none
*
* Description: Set CP15 CTR (control) register
*
*************************************************************************/
__arm void CP15_SetStatus (Int32U Ctrl)
{
register volatile Int32U Val = Ctrl;
__MCR(15,0,Val,CP15_CTRL,0,0);
}
/*************************************************************************
* Function Name: CP15_SetTtb0
* Parameters: pInt32U pTtb
*
* Return: none
*
* Description: Set CP15 TTB0 base address register
*
*************************************************************************/
__arm void CP15_SetTtb0 (pInt32U pTtb)
{
register volatile Int32U Val = (Int32U)pTtb;
__MCR(15,0,Val,CP15_TTB_ADDR,0,0);
}
/*************************************************************************
* Function Name: CP15_SetTtb1
* Parameters: pInt32U pTtb
*
* Return: none
*
* Description: Set CP15 TTB1 base address register
*
*************************************************************************/
__arm void CP15_SetTtb1 (pInt32U pTtb)
{
register volatile Int32U Val = (Int32U)pTtb;
__MCR(15,0,Val,CP15_TTB_ADDR,0,1);
}
/*************************************************************************
* Function Name: CP15_SetDac
* Parameters: Int32U da
*
* Return: none
*
* Description: Set CP15 domain access register
*
*************************************************************************/
__arm void CP15_SetDac (Int32U da)
{
register volatile Int32U Val = da;
__MCR(15,0,Val,CP15_DA_CTRL,0,0);
}
/*************************************************************************
* Function Name: CP15_WriteBuffFlush
* Parameters: none
*
* Return: none
*
* Description: Flush the write buffer and wait for completion
* of the flush.
*
*************************************************************************/
__arm void CP15_WriteBuffFlush (void)
{
register volatile Int32U Val;
__MCR(15,0,Val,CP15_CACHE_OPR,10,4);
}
/*************************************************************************
* Function Name: CP15_GetFaultStat
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the MMU fault status register
*
*************************************************************************/
__arm Int32U CP15_GetFaultStat (void)
{
return(__MRC(15,0,CP15_FAULT_STAT,0,0));
}
/*************************************************************************
* Function Name: CP15_GetFaultAddr
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the MMU fault address register
*
*************************************************************************/
__arm Int32U CP15_GetFaultAddr (void)
{
return(__MRC(15,0,CP15_FAULT_ADDR,0,0));
}
/*************************************************************************
* Function Name: CP15_GetFcsePid
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the MMU Process identifier
* FCSE PID register
*
*************************************************************************/
__arm Int32U CP15_GetFcsePid (void)
{
return(__MRC(15,0,CP15_PROCESS_IDNF,0,0));
}
/*************************************************************************
* Function Name: CP15_GetPraceProcId
* Parameters: none
*
* Return: Int32U
*
* Description: Function returns the MMU Trace Process identifier
* register
*
*************************************************************************/
__arm Int32U CP15_GetPraceProcId (void)
{
return(__MRC(15,0,CP15_PROCESS_IDNF,0,1));
}
/*************************************************************************
* Function Name: CP15_SetFcsePid
* Parameters: Int32U FcsePid
*
* Return: none
*
* Description: Function set the MMU Process identifier
* FCSE PID register
*
*************************************************************************/
__arm void CP15_SetFcsePid (Int32U FcsePid)
{
register Int32U Val = FcsePid;
__MCR(15,0,Val,CP15_PROCESS_IDNF,0,0);
}
/*************************************************************************
* Function Name: CP15_GetPraceProcId
* Parameters: Int32U
*
* Return: none
*
* Description: Function set the MMU Trace Process identifier
* register
*
*************************************************************************/
__arm void CP15_SetPraceProcId(Int32U Trace)
{
register Int32U Val = Trace;
__MCR(15,0,Val,CP15_PROCESS_IDNF,0,1);
}
/*************************************************************************
* Function Name: CP15_InitMmuTtb
* Parameters: pTtSectionBlock_t pTtSB, pTtTableBlock_t pTtTB
*
* Return: Boolean
*
* Returns error if MMU is enabled or if target
* Translation Table address is not 16K aligned. Clear the
* Translation Table area. Build the Translation Table from the
* initialization data in the Section Block array. Return no error.
*
* Description: Initializes the MMU tables.
*
*
*************************************************************************/
Boolean CP15_InitMmuTtb(const TtSectionBlock_t * pTtSB,
const TtTableBlock_t * pTtTB)
{
Int32U i, pa, pa_inc, va_ind;
pInt32U pTtb;
TableType_t TableType;
while(1)
{
TableType = pTtTB->TableType;
switch(TableType)
{
case TableL1:
pTtb = pTtTB->TableAddr;
if((Int32U)pTtb & L1_ENTRIES_NUMB-1)
{
return(FALSE);
}
pa_inc = 0x100000;
pa = L1_ENTRIES_NUMB;
break;
case TableL2_PageTable:
pTtb = pTtTB->TableAddr;
if((Int32U)pTtb & L2_CP_ENTRIES_NUMB-1)
{
return(FALSE);
}
pa_inc = 0x1000;
pa = L2_CP_ENTRIES_NUMB;
break;
default:
return(TRUE);
}
// Clear the entire Translation Table This results in LxD_TYPE_FAULT
// being the default for any uninitialized entries.
for(i = 0; i < pa; ++i)
{
*(pTtb+i) = TT_ENTRY_INVALID;
}
// Build the translation table from user provided pTtSectionBlock_t array
while(pTtSB->NubrOfSections != 0)
{
Int32U Entrys = pTtSB->NubrOfSections;
Int32U Data = pTtSB->Entry.Data;
pa = pTtSB->PhysAddr;
switch(TableType)
{
case TableL1:
va_ind = (pTtSB->VirtAddr >> 20) & (L1_ENTRIES_NUMB-1);
if((va_ind + Entrys) > L1_ENTRIES_NUMB)
{
return(FALSE);
}
break;
case TableL2_PageTable:
va_ind = (pTtSB->VirtAddr >> 12) & (L2_CP_ENTRIES_NUMB-1);
if((va_ind + Entrys) > L2_CP_ENTRIES_NUMB)
{
return(FALSE);
}
break;
}
for(i = 0; i < Entrys; ++i, ++va_ind)
{
switch(TableType)
{
case TableL1:
switch(pTtSB->Entry.Type)
{
case TtL1PageTable:
*(pTtb+va_ind) |= Data | (pa & TTL1_PT_PADDR_MASK);
break;
case TtL1Section:
*(pTtb+va_ind) |= Data | (pa & TTL1_SECTION_PADDR_MASK);
break;
case TtL1SuperSection:
*(pTtb+va_ind) |= Data | (pa & TTL1_S_SECTION_PADDR_MASK);
break;
default:
return(FALSE);
}
break;
case TableL2_PageTable:
switch(pTtSB->Entry.Type)
{
case TtL2LargePage:
*(pTtb+va_ind) |= Data | (pa & TTL2_LP_PADDR_MASK);
break;
case TtL2SmallPage:
*(pTtb+va_ind) |= Data | (pa & TTL2_SP_PADDR_MASK);
break;
default:
return(FALSE);
}
break;
}
pa += pa_inc;
}
++pTtSB;
}
++pTtSB;
++pTtTB;
}
}
/*************************************************************************
* Function Name: CP15_Mmu
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable MMU
*
*************************************************************************/
void CP15_Mmu(Boolean Enable)
{
Int32U Val = CP15_GetStatus();
if(Enable)
{
CP15_InvalAllTbl();
Val |= CP15_CTRL_M;
}
else
{
Val &= ~(CP15_CTRL_M | CP15_CTRL_C);
}
CP15_SetStatus(Val);
}
/*************************************************************************
* Function Name: CP15_Cache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable Both Cache
*
*************************************************************************/
void CP15_Cache(Boolean Enable)
{
Int32U Val = CP15_GetStatus();
if(Enable)
{
Val |= CP15_CTRL_M | CP15_CTRL_C | CP15_CTRL_I;
}
else
{
Val &= ~CP15_CTRL_C;
}
CP15_SetStatus(Val);
}
/*************************************************************************
* Function Name: CP15_InvalidateCache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Invalidate Cache
*
*************************************************************************/
void CP15_InvalidateCache()
{
CP15_MaintainAllDCache(DCACHE_INVALIDATE);
__DSB();
CP15_InvalInstrCache(); /* includes invalidation of branch predictor */
__DSB();
__ISB();
}
/*************************************************************************
* Function Name: CP15_ICache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable I cache
*
*************************************************************************/
void CP15_ICache (Boolean Enable)
{
Int32U Val = CP15_GetStatus();
if(Enable)
{
Val |= CP15_CTRL_I;
}
else
{
Val &= ~CP15_CTRL_I;
}
CP15_SetStatus(Val);
}
/*************************************************************************
* Function Name: CP15_DCache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable D cache
*
*************************************************************************/
void CP15_DCache (Boolean Enable)
{
Int32U Val = CP15_GetStatus();
if(Enable)
{
Val |= CP15_CTRL_M | CP15_CTRL_C;
}
else
{
Val &= ~CP15_CTRL_C;
}
CP15_SetStatus(Val);
}
/*************************************************************************
* Function Name: CP15_ProgFlowPrediction
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable program flow prediction.
*
*************************************************************************/
void CP15_ProgFlowPrediction (Boolean Enable)
{
Int32U Val = CP15_GetStatus();
if(Enable)
{
CP15_InvalPredictArray();
Val |= CP15_CTRL_Z;
}
else
{
Val &= ~CP15_CTRL_Z;
}
CP15_SetStatus(Val);
}
/*************************************************************************
* Function Name: CP15_GetVectorBase
* Parameters: none
*
* Return: Int32U
*
* Description: Get Vector Base Register (VBAR)
*
*************************************************************************/
__arm Int32U CP15_GetVectorBase(void)
{
return(__MRC(15,0,CP15_VBAR,0,0));
}
/*************************************************************************
* Function Name: CP15_SetVectorBase
* Parameters: Int32U
*
* Return: none
*
* Description: Set Vector Base Register (VBAR)
*
*************************************************************************/
__arm void CP15_SetVectorBase(Int32U vector)
{
register volatile Int32U Val = vector;
__MCR(15,0,Val,CP15_VBAR,0,0);
}
/*************************************************************************
* Function Name: CP15_SetHighVectors
* Parameters: Boolean
*
* Return: none
*
* Description: Select High or Low vectors base in CP15 control register
*
*************************************************************************/
__arm void CP15_SetHighVectors(Boolean Enable)
{
Int32U Val = CP15_GetStatus();
if(Enable)
{
Val |= CP15_CTRL_V;
}
else
{
Val &= ~CP15_CTRL_V;
}
CP15_SetStatus(Val);
}

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.h
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/*************************************************************************
*
* Used with ICCARM and AARM.
*
* (c) Copyright IAR Systems 2012
*
* File name : armv7a_cp15_drv.h
* Description : Definitions of a driver for the CP15 of ARMv7-A
*
* History :
* 1. Date : September, 8 2006
* Author : Stanimir Bonev
* Description : Create
*
* 2. Date : October, 2008
* Author : Stoyan Choynev
* Description : Port for ARM1136JF. The driver is backwards compatible with ARMv5 or earlier
* processors
*
* 3. Date : March, 2012
* Author : Atanas Uzunov
* Description : Port for ARMv7-A architecture.
* Added cache maintenance functions.
*
* $Revision: 52705 $
**************************************************************************/
#include <intrinsics.h>
#include "arm_comm.h"
#ifndef __ARMV7A_CP15_DRV_H
#define __ARMV7A_CP15_DRV_H
#define NON_CACHABLE_ADDR 0xFFFFFFFC
#define L1_ENTRIES_NUMB 4096
#define L2_CP_ENTRIES_NUMB 256
#define DCACHE_CLEAN_AND_INVALIDATE 1
#define DCACHE_INVALIDATE 2
#define TSB_INVALID { 0, 0, 0, 0 }
#define TTB_INVALID { 0, TableInvalid }
#define L1_PAGE_TABLE_ENTRY(Numb, VirtAddr ,PhAddr, Domain, NS) \
{ Numb, VirtAddr, PhAddr, \
((Domain << 5) | (NS << 3) | \
TtL1PageTable)}
#define L1_SECTION_ENTRY(Numb, VirtAddr ,PhAddr, NS, nG, S, AP2, TEX, AP01, Domain, XN, C, B) \
{ Numb, VirtAddr, PhAddr, \
((NS << 19) | (nG << 17) | (S << 16) | (AP2 << 15) | (TEX << 12) | (AP01 << 10) | (Domain << 5) | (XN << 4) | (C << 3) | (B << 2) | \
TtL1Section)}
#define L1_SUPERSECTION_ENTRY(Numb, VirtAddr, PhAddr, ExtBaseAddr, NS, nG, S, AP2, TEX, AP01, Domain, XN, C, B) \
{ Numb*16, VirtAddr, PhAddr, \
(((ExtBaseAddr&0x0FUL) << 20) | (((ExtBaseAddr&0xF0UL)>>4) << 5) | (NS << 19) | (nG << 17) | (S << 16) | (AP2 << 15) | (TEX << 12) | (AP01 << 10) | (Domain << 5) | (XN << 4) | (C << 3) | (B << 2) | \
TtL1SuperSection)}
#define L2_LARGE_PAGE_ENTRY(Numb, VirtAddr ,PhAddr, XN, TEX, nG, S, AP2, AP01, C, B) \
{ Numb*16, VirtAddr, PhAddr, \
((XN << 15) | (TEX << 12) | (nG << 11) | (S << 10) | (AP2 << 9) | (AP01 << 4) | (C << 3) | (B << 2) | \
TtL2LargePage)}
#define L2_SMALL_PAGE_ENTRY(Numb, VirtAddr ,PhAddr, XN, TEX, nG, S, AP2, AP01, C, B) \
{ Numb, VirtAddr, PhAddr, \
((nG << 11) | (S << 10) | (AP2 << 9) | (TEX<<6) | (AP01 << 4) | (C << 3) | (B << 2) | (XN << 0) | \
TtL2SmallPage)}
// CP15 Registers
// ID register
#define CP15_ID 0
// Control register
#define CP15_CTRL 1
// CP15 Control register bits
#define CP15_CTRL_M (1UL << 0) // MMU enable/disable
#define CP15_CTRL_A (1UL << 1) // Alignment fault enable/disable
#define CP15_CTRL_C (1UL << 2) // DCache enable/disable
#define CP15_CTRL_Z (1UL << 11) // Program flow prediction
#define CP15_CTRL_I (1UL << 12) // ICache enable/disable
#define CP15_CTRL_V (1UL << 13) // Location of exception vectors
#define CP15_CTRL_EE (1UL << 25) // CPSR E bit on exception
#define CP15_CTRL_NMFI (1UL << 27) // FIQ enable bit (1 - FIQ cannot be masked) READ-ONLY
#define CP15_CTRL_TRE (1UL << 28) // TEX remap functionality bit. (TEX enabled/disabled)
#define CP15_CTRL_AFE (1UL << 29) // Access Flag Enable bit.
#define CP15_CTRL_TE (1UL << 30) // Thumb Exception enable bit.
// Translation table base address (alignment 4KB)
#define CP15_TTB_ADDR 2
// Domain access control register
#define CP15_DA_CTRL 3
#define CP15_DA_CTRL_D0(Val) ((Val & 0x3) << 0)
#define CP15_DA_CTRL_D1(Val) ((Val & 0x3) << 2)
#define CP15_DA_CTRL_D2(Val) ((Val & 0x3) << 4)
#define CP15_DA_CTRL_D3(Val) ((Val & 0x3) << 6)
#define CP15_DA_CTRL_D4(Val) ((Val & 0x3) << 8)
#define CP15_DA_CTRL_D5(Val) ((Val & 0x3) << 10)
#define CP15_DA_CTRL_D6(Val) ((Val & 0x3) << 12)
#define CP15_DA_CTRL_D7(Val) ((Val & 0x3) << 14)
#define CP15_DA_CTRL_D8(Val) ((Val & 0x3) << 16)
#define CP15_DA_CTRL_D9(Val) ((Val & 0x3) << 18)
#define CP15_DA_CTRL_D10(Val) ((Val & 0x3) << 20)
#define CP15_DA_CTRL_D11(Val) ((Val & 0x3) << 22)
#define CP15_DA_CTRL_D12(Val) ((Val & 0x3) << 24)
#define CP15_DA_CTRL_D13(Val) ((Val & 0x3) << 25)
#define CP15_DA_CTRL_D14(Val) ((Val & 0x3) << 28)
#define CP15_DA_CTRL_D15(Val) ((Val & 0x3) << 30)
// CP15 fault status register
#define CP15_FAULT_STAT 5
// CP15 fault address register
#define CP15_FAULT_ADDR 6
// CP15 Cache operations
#define CP15_CACHE_OPR 7
// CP15 TLB operation
#define CP15_TBL_OPR 8
// CP15 Cache lockdown
#define CP15_C_LD 9
// CP15 TBL lockdown
#define CP15_TBL_LD 10
// CP15 VBAR
#define CP15_VBAR 12
// CP15 Process identifier register
#define CP15_PROCESS_IDNF 13
// CP15 Test
#define CP15_TEST 15
typedef enum {
DomainNoAccess = 0, DomainClient, DomainManager = 3,
} MmuDomainType_t;
typedef enum
{
TtL1Invalid = 0, TtL1PageTable, TtL1Section, TtL1SuperSection = 0x40002,
} TtL1EntryType_t;
typedef enum
{
TtL2Invalid = 0, TtL2LargePage, TtL2SmallPage,
} TtL2EntryType_t;
typedef enum
{
TableInvalid = 0, TableL1, TableL2_PageTable,
} TableType_t;
typedef enum
{
PC15_FASTBUS_MODE = 0, PC15_SYNC_MODE, PC15_ASYNC_MODE = 3
} ClkMode_t;
typedef union _TtEntry_t
{
Int32U Data;
struct
{
Int32U Type : 2;
Int32U : 3;
Int32U Domain : 4;
Int32U :23;
};
} TtEntry_t, *pTtEntry_t;
typedef struct _TtSectionBlock_t
{
Int32U NubrOfSections;
Int32U VirtAddr;
Int32U PhysAddr;
TtEntry_t Entry;
} TtSectionBlock_t, * pTtSectionBlock_t;
typedef struct _TtTableBlock_t
{
pInt32U TableAddr;
TableType_t TableType;
} TtTableBlock_t, * pTtTableBlock_t;
#define TT_ENTRY_INVALID 0
#define TTL1_SECTION_PADDR_MASK 0xFFF00000
#define TTL1_S_SECTION_PADDR_MASK 0xFF000000
#define TTL1_S_SECTION_EXT35_32_PADDR_MASK 0x00F00000
#define TTL1_S_SECTION_EXT39_36_PADDR_MASK 0x000001E0
#define TTL1_PT_PADDR_MASK 0xFFFFFC00
#define TTL2_LP_PADDR_MASK 0xFFFF0000
#define TTL2_SP_PADDR_MASK 0xFFFFF000
/*************************************************************************
* Function Name: CP15_GetTtb0
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the TTB0 register
*
*************************************************************************/
__arm Int32U CP15_GetTtb0 (void);
/*************************************************************************
* Function Name: CP15_GetTtb1
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the TTB1 register
*
*************************************************************************/
__arm Int32U CP15_GetTtb1 (void);
/*************************************************************************
* Function Name: CP15_GetStatus
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the MMU control register
*
*************************************************************************/
__arm Int32U CP15_GetStatus (void);
/*************************************************************************
* Function Name: CP15_GetDomain
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the MMU domain access register
*
*************************************************************************/
__arm Int32U CP15_GetDomain (void);
/*************************************************************************
* Function Name: CP15_SetDomains
* Parameters: Int32U DomainAccess
*
* Return: Int32U
*
* Description: Function set the MMU domain access register
*
*************************************************************************/
__arm void CP15_SetDomains (Int32U DomainAccess);
/*************************************************************************
* Function Name: CP15_MaintainDCacheSetWay
* Parameters: Int32U level - level of cache,
* Int32U maint - maintenance type
*
* Return: none
*
* Description: Maintain data cache line by Set/Way
*
*************************************************************************/
__arm void CP15_MaintainDCacheSetWay(Int32U level, Int32U maint);
/*************************************************************************
* Function Name: CP15_MaintAllDCache
* Parameters: Int32U oper - type of maintenance, one of:
* DCACHE_CLEAN_AND_INVALIDATE
* DCACHE_INVALIDATE
*
* Return: none
*
* Description: Maintenance of all data cache
*
*************************************************************************/
__arm void CP15_MaintainAllDCache(Int32U oper);
/*************************************************************************
* Function Name: CP15_InvalInstrCache
* Parameters: none
*
* Return: none
*
* Description: Invalidate instruction cache
*
*************************************************************************/
__arm void CP15_InvalInstrCache(void);
/*************************************************************************
* Function Name: CP15_InvalPredictArray
* Parameters: none
*
* Return: none
*
* Description: Invalidate prediction array
*
*************************************************************************/
__arm void CP15_InvalPredictArray(void);
/*************************************************************************
* Function Name: CP15_InvalAllTbl
* Parameters: none
*
* Return: none
*
* Description: Invalidate TLB
*
*************************************************************************/
__arm void CP15_InvalAllTbl (void);
/*************************************************************************
* Function Name: CP15_SetStatus
* Parameters: Int32U Ctrl
*
* Return: none
*
* Description: Set CP15 CTR (control) register
*
*************************************************************************/
__arm void CP15_SetStatus (Int32U Ctrl);
/*************************************************************************
* Function Name: CP15_SetMmu
* Parameters: Int32U Ctrl
*
* Return: none
*
* Description: Set CP15 control register
*
*************************************************************************/
__arm void CP15_SetMmu (Int32U Ctrl);
/*************************************************************************
* Function Name: CP15_SetTtb0
* Parameters: pInt32U pTtb
*
* Return: none
*
* Description: Set CP15 TTB0 base address register
*
*************************************************************************/
__arm void CP15_SetTtb0 (pInt32U pTtb);
/*************************************************************************
* Function Name: CP15_SetTtb1
* Parameters: pInt32U pTtb
*
* Return: none
*
* Description: Set CP15 TTB1 base address register
*
*************************************************************************/
__arm void CP15_SetTtb1 (pInt32U pTtb);
/*************************************************************************
* Function Name: CP15_SetDac
* Parameters: Int32U da
*
* Return: none
*
* Description: Set CP15 domain access register
*
*************************************************************************/
__arm void CP15_SetDac (Int32U da);
/*************************************************************************
* Function Name: CP15_WriteBuffFlush
* Parameters: none
*
* Return: none
*
* Description: Flush the write buffer and wait for completion
* of the flush.
*
*************************************************************************/
__arm void CP15_WriteBuffFlush (void);
/*************************************************************************
* Function Name: CP15_GetFaultStat
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the MMU fault status register
*
*************************************************************************/
__arm Int32U CP15_GetFaultStat (void);
/*************************************************************************
* Function Name: CP15_GetFaultAddr
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the MMU fault address register
*
*************************************************************************/
__arm Int32U CP15_GetFaultAddr (void);
/*************************************************************************
* Function Name: CP15_GetFcsePid
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the MMU Process identifier
* FCSE PID register
*
*************************************************************************/
__arm Int32U CP15_GetFcsePid (void);
/*************************************************************************
* Function Name: CP15_GetPraceProcId
* Parameters: none
*
* Return: Int32U
*
* Description: Function returning the MMU Trace Process identifier
* register
*
*************************************************************************/
__arm Int32U CP15_GetPraceProcId (void);
/*************************************************************************
* Function Name: CP15_SetFcsePid
* Parameters: Int32U FcsePid
*
* Return: none
*
* Description: Function set the MMU Process identifier
* FCSE PID register
*
*************************************************************************/
__arm void CP15_SetFcsePid (Int32U FcsePid);
/*************************************************************************
* Function Name: CP15_SetPraceProcId
* Parameters: Int32U
*
* Return: none
*
* Description: Function set the MMU Trace Process identifier
* register
*
*************************************************************************/
__arm void CP15_SetPraceProcId (Int32U Trace);
/*************************************************************************
* Function Name: CP15_WriteBuffFlush
* Parameters: pTtSectionBlock_t pTtSB, pTtTableBlock_t pTtTB
*
* Return: Boolean
*
* Return error if MMU is enabled. Return error if target
* Translation Table address is not 16K aligned. Clear the
* Translation Table area. Build the Translation Table from the
* initialization data in the Section Block array. Return no error.
*
* Description: Initializes the MMU tables.
*
*
*************************************************************************/
Boolean CP15_InitMmuTtb(const TtSectionBlock_t * pTtSB,
const TtTableBlock_t * pTtTB);
/*************************************************************************
* Function Name: CP15_Mmu
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable MMU
*
*************************************************************************/
void CP15_Mmu (Boolean Enable);
/*************************************************************************
* Function Name: CP15_Cache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable Cache
*
*************************************************************************/
void CP15_Cache (Boolean Enable);
/*************************************************************************
* Function Name: CP15_InvalidateCache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Invalidate Cache
*
*************************************************************************/
void CP15_InvalidateCache();
/*************************************************************************
* Function Name: CP15_ICache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable I cache
*
*************************************************************************/
void CP15_ICache (Boolean Enable);
/*************************************************************************
* Function Name: CP15_DCache
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable D cache
*
*************************************************************************/
void CP15_DCache (Boolean Enable);
/*************************************************************************
* Function Name: CP15_ProgFlowPredictioin
* Parameters: Boolean Enable
*
* Return: none
*
* Description: Enable/Disable program flow prediction
*
*************************************************************************/
void CP15_ProgFlowPrediction (Boolean Enable);
/*************************************************************************
* Function Name: CP15_GetVectorBase
* Parameters: none
*
* Return: Int32U
*
* Description: Get Vector Base Register (VBAR)
*
*************************************************************************/
__arm Int32U CP15_GetVectorBase(void);
/*************************************************************************
* Function Name: CP15_SetVectorBase
* Parameters: Int32U
*
* Return: none
*
* Description: Set Vector Base Register (VBAR)
*
*************************************************************************/
__arm void CP15_SetVectorBase(Int32U vector);
/*************************************************************************
* Function Name: CP15_SetHighVectors
* Parameters: Boolean
*
* Return: none
*
* Description: Select High or Low Vectors base in CP15 control register
*
*************************************************************************/
__arm void CP15_SetHighVectors(Boolean Enable);
#endif // __ARMV7A_CP15_DRV_H

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/r7s721000.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x20020000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
define symbol __ICFEDIT_region_ROM_end__ = 0x0;
define symbol __ICFEDIT_region_RAM_start__ = 0x20020040;
define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_svcstack__ = 0x800;
define symbol __ICFEDIT_size_irqstack__ = 0x800;
define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x8;
/**** End of ICF editor section. ###ICF###*/
define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
define memory mem with size = 4G;
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section MMU_TT };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in RAM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
place in RetRAM_region { section .retram };
place in MirrorRAM_region { section .mirrorram };
place in MirrorRetRAM_region { section .mirrorretram };

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.cspy.bat
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@REM This batch file has been generated by the IAR Embedded Workbench
@REM C-SPY Debugger, as an aid to preparing a command line for running
@REM the cspybat command line utility using the appropriate settings.
@REM
@REM Note that this file is generated every time a new debug session
@REM is initialized, so you may want to move or rename the file before
@REM making changes.
@REM
@REM You can launch cspybat by typing the name of this batch file followed
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
@REM
@REM Read about available command line parameters in the C-SPY Debugging
@REM Guide. Hints about additional command line parameters that may be
@REM useful in specific cases:
@REM --download_only Downloads a code image without starting a debug
@REM session afterwards.
@REM --silent Omits the sign-on message.
@REM --timeout Limits the maximum allowed execution time.
@REM
"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armsim2.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --backend -B "--endian=little" "--cpu=Cortex-A9" "--fpu=VFPv3Neon" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Renesas\R7S721000.ddf" "--semihosting=none" "--device=R7S721000"

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dbgdt
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<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Debug-Log>
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>
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<Workspace>
<ColumnWidths>
<Column0>228</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<col-names>
<item>Disassembly</item><item>_I0</item></col-names>
<col-widths>
<item>500</item><item>20</item></col-widths>
<DisasmHistory/>
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<Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>WATCH_1</Factory></Window></Windows></PreferedWindows></Register><WATCH_1><expressions><item/></expressions><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>236</item><item>150</item><item>100</item><item>100</item></col-widths><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></WATCH_1><Auto><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>100</item><item>150</item><item>100</item><item>100</item></col-widths><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Auto><Find-in-Files><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-in-Files><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Breakpoint</item><item>_I0</item></col-names><col-widths><item>500</item><item>35</item></col-widths></Breakpoints></Static>
<Windows>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-6824-27546</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-17050-27559</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
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</Tab>
<Tab><Identity>TabID-11794-23690</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs>
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<TabName>Workspace</TabName>
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<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Blinky-Demo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source/portable</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source/portable/IAR</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS-Source/portable/IAR/ARM_CA9</ExpandedNode></NodeDict></Session>
</Tab>
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121
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dni
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[Stack]
FillEnabled=0
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=0
WarnLogOnly=1
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[JLinkDriver]
WatchCond=_ 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
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[DebugChecksum]
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[Exceptions]
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[CallStack]
ShowArgs=0
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SamplingDivider=8192
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CpuClock=0
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ItmPortsEnabled=63
ItmTermIOPorts=1
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Title0=ITrgPwr
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Frequency=10000
Probe0=ITrgPwr
ProbeSetup0=2 1 1 2 0 0
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78
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.wsdt
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<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>RTOSDemo/RAM Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>306</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
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<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>
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<Wnd2>
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<Identity>TabID-16877-7786</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
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</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
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<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
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<Tab>
<Identity>TabID-13343-8671</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
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</Tab>
<Tab><Identity>TabID-959-438</Identity><TabName>Ambiguous Definitions</TabName><Factory>Select-Ambiguous-Definitions</Factory><Session/></Tab><Tab><Identity>TabID-21579-10611</Identity><TabName>Find All Declarations</TabName><Factory>Find-All-Declarations</Factory><Session/></Tab></Tabs>
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34
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo_RAM Debug.jlink
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[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Unspecified"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

241
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Blinky-Demo/main_blinky.c
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles an LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Standard demo includes. */
#include "partest.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* The LED toggled by the Rx task. */
#define mainTASK_LED ( 0 )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* Called by main() to create the simply blinky style application if
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
*/
void main_blinky( void );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static xQueueHandle xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
const unsigned long ulExpectedValue = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
vParTestToggleLED( mainTASK_LED );
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

210
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOSConfig.h
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/*
* The FreeRTOS Cortex-A port implements a full interrupt nesting model.
*
* Interrupts that are assigned a priority at or below
* configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM
* generic interrupt controller [GIC] means a priority that has a numerical
* value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API
* functions and will nest.
*
* Interrupts that are assigned a priority above
* configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical
* value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS
* API functions, will nest, and will not be masked by FreeRTOS critical
* sections (although it is necessary for interrupts to be globally disabled
* extremely briefly as the interrupt mask is updated in the GIC).
*
* FreeRTOS functions that can be called from an interrupt are those that end in
* "FromISR". FreeRTOS maintains a separate interrupt safe API to enable
* interrupt entry to be shorter, faster, simpler and smaller.
*
* The Renesas RZ implements 32 unique interrupt priorities. For the purpose of
* setting configMAX_API_CALL_INTERRUPT_PRIORITY 31 represents the lowest
* priority.
*/
#define configMAX_API_CALL_INTERRUPT_PRIORITY 25
#define configCPU_CLOCK_HZ 100000000UL
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_TICKLESS_IDLE 0
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configPERIPHERAL_CLOCK_HZ ( 33333000UL )
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 160 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38912 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Prevent C code being included in assembly files when the IAR compiler is
used. */
#ifndef __IASMARM__
/* Run time stats gathering definitions. */
unsigned long ulGetRunTimeCounterValue( void );
void vInitialiseRunTimeStats( void );
#define configGENERATE_RUN_TIME_STATS 1
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats()
#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
/* The size of the global output buffer that is available for use when there
are multiple command interpreters running at once (for example, one on a UART
and one on TCP/IP). This is done to prevent an output buffer being defined by
each implementation - which would waste RAM. In this case, there is only one
command interpreter running. */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
void vAssertCalled( const char * pcFile, unsigned long ulLine );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );
/****** Hardware specific settings. *******************************************/
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Renesas RZ MPU. FreeRTOS_Tick_Handler() must
* be installed as the peripheral's interrupt handler.
*/
void vConfigureTickInterrupt( void );
#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
#endif /* __ICCARM__ */
/* The following constants describe the hardware, and are correct for the
Renesas RZ MPU. */
#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0xE8201000
#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000
#define configUNIQUE_INTERRUPT_PRIORITIES 32
/* Map the FreeRTOS IRQ and SVC/SWI handlers to the names used in the C startup
code (which is where the vector table is defined). */
#define FreeRTOS_IRQ_Handler IRQ_Handler
#define FreeRTOS_SWI_Handler SWI_Handler
#endif /* FREERTOS_CONFIG_H */

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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "Task.h"
/* Renesas driver includes. */
#include "stdint.h"
#include "dev_drv.h"
#include "devdrv_ostm.h"
#include "devdrv_intc.h"
#include "iodefine.h"
#define runtimeCLOCK_SCALE_SHIFT ( 9UL )
#define runtimeOVERFLOW_BIT ( 1UL << ( 32UL - runtimeCLOCK_SCALE_SHIFT ) )
/* To make casting to the ISR prototype expected by the Renesas GIC drivers. */
typedef void (*ISR_FUNCTION)( uint32_t );
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Renesas RZ MPU.
*/
void vConfigureTickInterrupt( void )
{
/* Stop the counter. */
OSTM0.OSTMnTT.BIT.OSTMnTT = 1;
/* Work in interval mode. */
OSTM0.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_INTERVAL;
/* Use interrupts after counting starts. */
OSTM0.OSTMnCTL.BIT.OSTMnMD0 = 1;
/* Start value for down counter. */
OSTM0.OSTMnCMP = configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ;
/* Configure the interrupt controller. */
R_INTC_RegistIntFunc( INTC_ID_OSTMI0, ( ISR_FUNCTION ) FreeRTOS_Tick_Handler );
/* Tick must be assigned the lowest interrupt priority. */
R_INTC_SetPriority( INTC_ID_OSTMI0, portLOWEST_USABLE_INTERRUPT_PRIORITY );
INTC.ICCBPR.BIT.Binarypoint = 0;
R_INTC_Enable( INTC_ID_OSTMI0 );
R_OSTM_Open( DEVDRV_CH_0 );
}
/*-----------------------------------------------------------*/
/*
* Crude implementation of a run time counter used to measure how much time
* each task spends in the Running state.
*/
unsigned long ulGetRunTimeCounterValue( void )
{
static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
unsigned long ulValueNow;
ulValueNow = OSTM1.OSTMnCNT;
/* Has the value overflowed since it was last read. */
if( ulValueNow < ulLastCounterValue )
{
ulOverflows++;
}
ulLastCounterValue = ulValueNow;
/* There is no prescale on the counter, so simulate in software. */
ulValueNow >>= runtimeCLOCK_SCALE_SHIFT + ( runtimeOVERFLOW_BIT * ulOverflows );
return ulValueNow;
}
/*-----------------------------------------------------------*/
void vInitialiseRunTimeStats( void )
{
/* OSTM1 is used as the run time stats counter. */
/* Stop the counter. */
OSTM1.OSTMnTT.BIT.OSTMnTT = 1;
/* Work in compare mode mode. */
OSTM1.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_COMPARE;
/* Don't use interrupts. */
OSTM1.OSTMnCTL.BIT.OSTMnMD0 = 0;
/* Compare is just set to 0. */
OSTM1.OSTMnCMP = 0;
R_OSTM_Open( DEVDRV_CH_1 );
}

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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not itcan be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Standard includes. */
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/* FreeRTOS+CLI includes. */
#include "FreeRTOS_CLI.h"
/* File system includes. */
#include "fat_sl.h"
#include "api_mdriver_ram.h"
#ifdef _WINDOWS_
#define snprintf _snprintf
#endif
#define cliNEW_LINE "\r\n"
/*******************************************************************************
* See the URL in the comments within main.c for the location of the online
* documentation.
******************************************************************************/
/*
* Print out information on a single file.
*/
static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct );
/*
* Copies an existing file into a newly created file.
*/
static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,
int32_t lSourceFileLength,
int8_t *pcDestinationFile,
int8_t *pxWriteBuffer,
size_t xWriteBufferLen );
/*
* Implements the DIR command.
*/
static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the CD command.
*/
static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the DEL command.
*/
static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the TYPE command.
*/
static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the COPY command.
*/
static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Registers the CLI commands that are specific to the files system with the
* FreeRTOS+CLI command interpreter.
*/
void vRegisterFileSystemCLICommands( void );
/* Structure that defines the DIR command line command, which lists all the
files in the current directory. */
static const CLI_Command_Definition_t xDIR =
{
"dir", /* The command string to type. */
"\r\ndir:\r\n Lists the files in the current directory\r\n",
prvDIRCommand, /* The function to run. */
0 /* No parameters are expected. */
};
/* Structure that defines the CD command line command, which changes the
working directory. */
static const CLI_Command_Definition_t xCD =
{
"cd", /* The command string to type. */
"\r\ncd <dir name>:\r\n Changes the working directory\r\n",
prvCDCommand, /* The function to run. */
1 /* One parameter is expected. */
};
/* Structure that defines the TYPE command line command, which prints the
contents of a file to the console. */
static const CLI_Command_Definition_t xTYPE =
{
"type", /* The command string to type. */
"\r\ntype <filename>:\r\n Prints file contents to the terminal\r\n",
prvTYPECommand, /* The function to run. */
1 /* One parameter is expected. */
};
/* Structure that defines the DEL command line command, which deletes a file. */
static const CLI_Command_Definition_t xDEL =
{
"del", /* The command string to type. */
"\r\ndel <filename>:\r\n deletes a file or directory\r\n",
prvDELCommand, /* The function to run. */
1 /* One parameter is expected. */
};
/* Structure that defines the COPY command line command, which deletes a file. */
static const CLI_Command_Definition_t xCOPY =
{
"copy", /* The command string to type. */
"\r\ncopy <source file> <dest file>:\r\n Copies <source file> to <dest file>\r\n",
prvCOPYCommand, /* The function to run. */
2 /* Two parameters are expected. */
};
/*-----------------------------------------------------------*/
void vRegisterFileSystemCLICommands( void )
{
/* Register all the command line commands defined immediately above. */
FreeRTOS_CLIRegisterCommand( &xDIR );
FreeRTOS_CLIRegisterCommand( &xCD );
FreeRTOS_CLIRegisterCommand( &xTYPE );
FreeRTOS_CLIRegisterCommand( &xDEL );
FreeRTOS_CLIRegisterCommand( &xCOPY );
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcParameter;
portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;
static F_FILE *pxFile = NULL;
int iChar;
size_t xByte;
size_t xColumns = 50U;
/* Ensure there is always a null terminator after each character written. */
memset( pcWriteBuffer, 0x00, xWriteBufferLen );
/* Ensure the buffer leaves space for the \r\n. */
configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
xWriteBufferLen -= strlen( cliNEW_LINE );
if( xWriteBufferLen < xColumns )
{
/* Ensure the loop that uses xColumns as an end condition does not
write off the end of the buffer. */
xColumns = xWriteBufferLen;
}
if( pxFile == NULL )
{
/* The file has not been opened yet. Find the file name. */
pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
1, /* Return the first parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcParameter );
/* Attempt to open the requested file. */
pxFile = f_open( ( const char * ) pcParameter, "r" );
}
if( pxFile != NULL )
{
/* Read the next chunk of data from the file. */
for( xByte = 0; xByte < xColumns; xByte++ )
{
iChar = f_getc( pxFile );
if( iChar == -1 )
{
/* No more characters to return. */
f_close( pxFile );
pxFile = NULL;
break;
}
else
{
pcWriteBuffer[ xByte ] = ( int8_t ) iChar;
}
}
}
if( pxFile == NULL )
{
/* Either the file was not opened, or all the data from the file has
been returned and the file is now closed. */
xReturn = pdFALSE;
}
strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
return xReturn;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcParameter;
portBASE_TYPE xParameterStringLength;
unsigned char ucReturned;
size_t xStringLength;
/* Obtain the parameter string. */
pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
1, /* Return the first parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcParameter );
/* Attempt to move to the requested directory. */
ucReturned = f_chdir( ( char * ) pcParameter );
if( ucReturned == F_NO_ERROR )
{
sprintf( ( char * ) pcWriteBuffer, "In: " );
xStringLength = strlen( ( const char * ) pcWriteBuffer );
f_getcwd( ( char * ) &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );
}
else
{
sprintf( ( char * ) pcWriteBuffer, "Error" );
}
strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
return pdFALSE;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
static F_FIND *pxFindStruct = NULL;
unsigned char ucReturned;
portBASE_TYPE xReturn = pdFALSE;
/* This assumes pcWriteBuffer is long enough. */
( void ) pcCommandString;
/* Ensure the buffer leaves space for the \r\n. */
configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
xWriteBufferLen -= strlen( cliNEW_LINE );
if( pxFindStruct == NULL )
{
/* This is the first time this function has been executed since the Dir
command was run. Create the find structure. */
pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );
if( pxFindStruct != NULL )
{
ucReturned = f_findfirst( "*.*", pxFindStruct );
if( ucReturned == F_NO_ERROR )
{
prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
xReturn = pdPASS;
}
else
{
snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );
}
}
else
{
snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );
}
}
else
{
/* The find struct has already been created. Find the next file in
the directory. */
ucReturned = f_findnext( pxFindStruct );
if( ucReturned == F_NO_ERROR )
{
prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
xReturn = pdPASS;
}
else
{
/* There are no more files. Free the find structure. */
vPortFree( pxFindStruct );
pxFindStruct = NULL;
/* No string to return. */
pcWriteBuffer[ 0 ] = 0x00;
}
}
strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
return xReturn;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcParameter;
portBASE_TYPE xParameterStringLength;
unsigned char ucReturned;
/* This function assumes xWriteBufferLen is large enough! */
( void ) xWriteBufferLen;
/* Obtain the parameter string. */
pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
1, /* Return the first parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcParameter );
/* Attempt to delete the file. */
ucReturned = f_delete( ( const char * ) pcParameter );
if( ucReturned == F_NO_ERROR )
{
sprintf( ( char * ) pcWriteBuffer, "%s was deleted", pcParameter );
}
else
{
sprintf( ( char * ) pcWriteBuffer, "Error" );
}
strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
return pdFALSE;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcSourceFile, *pcDestinationFile;
portBASE_TYPE xParameterStringLength;
long lSourceLength, lDestinationLength = 0;
/* Obtain the name of the destination file. */
pcDestinationFile = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
2, /* Return the second parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcDestinationFile );
/* Obtain the name of the source file. */
pcSourceFile = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
1, /* Return the first parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcSourceFile );
/* Terminate the string. */
pcSourceFile[ xParameterStringLength ] = 0x00;
/* See if the source file exists, obtain its length if it does. */
lSourceLength = f_filelength( ( const char * ) pcSourceFile );
if( lSourceLength == 0 )
{
sprintf( ( char * ) pcWriteBuffer, "Source file does not exist" );
}
else
{
/* See if the destination file exists. */
lDestinationLength = f_filelength( ( const char * ) pcDestinationFile );
if( lDestinationLength != 0 )
{
sprintf( ( char * ) pcWriteBuffer, "Error: Destination file already exists" );
}
}
/* Continue only if the source file exists and the destination file does
not exist. */
if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )
{
if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )
{
sprintf( ( char * ) pcWriteBuffer, "Copy made" );
}
else
{
sprintf( ( char * ) pcWriteBuffer, "Error during copy" );
}
}
strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
return pdFALSE;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,
int32_t lSourceFileLength,
int8_t *pcDestinationFile,
int8_t *pxWriteBuffer,
size_t xWriteBufferLen )
{
int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;
F_FILE *pxFile;
portBASE_TYPE xReturn = pdPASS;
/* NOTE: Error handling has been omitted for clarity. */
while( lBytesRead < lSourceFileLength )
{
/* How many bytes are left? */
lBytesRemaining = lSourceFileLength - lBytesRead;
/* How many bytes should be read this time around the loop. Can't
read more bytes than will fit into the buffer. */
if( lBytesRemaining > ( long ) xWriteBufferLen )
{
lBytesToRead = ( long ) xWriteBufferLen;
}
else
{
lBytesToRead = lBytesRemaining;
}
/* Open the source file, seek past the data that has already been
read from the file, read the next block of data, then close the
file again so the destination file can be opened. */
pxFile = f_open( ( const char * ) pcSourceFile, "r" );
if( pxFile != NULL )
{
f_seek( pxFile, lBytesRead, F_SEEK_SET );
f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );
f_close( pxFile );
}
else
{
xReturn = pdFAIL;
break;
}
/* Open the destination file and write the block of data to the end of
the file. */
pxFile = f_open( ( const char * ) pcDestinationFile, "a" );
if( pxFile != NULL )
{
f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );
f_close( pxFile );
}
else
{
xReturn = pdFAIL;
break;
}
lBytesRead += lBytesToRead;
}
return xReturn;
}
/*-----------------------------------------------------------*/
static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct )
{
const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";
const char * pcAttrib;
/* Point pcAttrib to a string that describes the file. */
if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )
{
pcAttrib = pcDirectory;
}
else if( pxFindStruct->attr & F_ATTR_READONLY )
{
pcAttrib = pcReadOnlyFile;
}
else
{
pcAttrib = pcWritableFile;
}
/* Create a string that includes the file name, the file size and the
attributes string. */
sprintf( ( char * ) pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, pxFindStruct->filesize );
}

384
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not itcan be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/*******************************************************************************
* See the URL in the comments within main.c for the location of the online
* documentation.
******************************************************************************/
/* Standard includes. */
#include <stdio.h>
#include <string.h>
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
/* File system includes. */
#include "fat_sl.h"
#include "api_mdriver_ram.h"
/* 8.3 format, plus null terminator. */
#define fsMAX_FILE_NAME_LEN 13
/* The number of bytes read/written to the example files at a time. */
#define fsRAM_BUFFER_SIZE 200
/* The number of bytes written to the file that uses f_putc() and f_getc(). */
#define fsPUTC_FILE_SIZE 100
/* The number of files created in root. */
#define fsROOT_FILES 5
/*-----------------------------------------------------------*/
/*
* Creates and verifies different files on the volume, demonstrating the use of
* various different API functions.
*/
void vCreateAndVerifySampleFiles( void );
/*
* Create a set of example files in the root directory of the volume using
* f_write().
*/
static void prvCreateDemoFilesUsing_f_write( void );
/*
* Use f_read() to read back and verify the files that were created by
* prvCreateDemoFilesUsing_f_write().
*/
static void prvVerifyDemoFileUsing_f_read( void );
/*
* Create an example file in a sub-directory using f_putc().
*/
static void prvCreateDemoFileUsing_f_putc( void );
/*
* Use f_getc() to read back and verify the file that was created by
* prvCreateDemoFileUsing_f_putc().
*/
static void prvVerifyDemoFileUsing_f_getc( void );
/*-----------------------------------------------------------*/
/* A buffer used to both create content to write to disk, and read content back
from a disk. Note there is no mutual exclusion on this buffer. */
static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];
/* Names of directories that are created. */
static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";
/*-----------------------------------------------------------*/
void vCreateAndVerifySampleFiles( void )
{
unsigned char ucStatus;
/* First create the volume. */
ucStatus = f_initvolume( ram_initfunc );
/* It is expected that the volume is not formatted. */
if( ucStatus == F_ERR_NOTFORMATTED )
{
/* Format the created volume. */
ucStatus = f_format( F_FAT12_MEDIA );
}
if( ucStatus == F_NO_ERROR )
{
/* Create a set of files using f_write(). */
prvCreateDemoFilesUsing_f_write();
/* Read back and verify the files that were created using f_write(). */
prvVerifyDemoFileUsing_f_read();
/* Create sub directories two deep then create a file using putc. */
prvCreateDemoFileUsing_f_putc();
/* Read back and verify the file created by
prvCreateDemoFileUsing_f_putc(). */
prvVerifyDemoFileUsing_f_getc();
}
}
/*-----------------------------------------------------------*/
static void prvCreateDemoFilesUsing_f_write( void )
{
portBASE_TYPE xFileNumber, xWriteNumber;
char cFileName[ fsMAX_FILE_NAME_LEN ];
long lItemsWritten;
F_FILE *pxFile;
/* Create fsROOT_FILES files. Each created file will be
( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled
with a different repeating character. */
for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )
{
/* Generate a file name. */
sprintf( cFileName, "root%03d.txt", xFileNumber );
/* Obtain the current working directory and print out the file name and
the directory into which the file is being written. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "Creating file %s in %s\r\n", cFileName, cRAMBuffer );
/* Open the file, creating the file if it does not already exist. */
pxFile = f_open( cFileName, "w" );
configASSERT( pxFile );
/* Fill the RAM buffer with data that will be written to the file. This
is just a repeating ascii character that indicates the file number. */
memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );
/* Write the RAM buffer to the opened file a number of times. The
number of times the RAM buffer is written to the file depends on the
file number, so the length of each created file will be different. */
for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )
{
lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
configASSERT( lItemsWritten == 1 );
}
/* Close the file so another file can be created. */
f_close( pxFile );
}
}
/*-----------------------------------------------------------*/
static void prvVerifyDemoFileUsing_f_read( void )
{
portBASE_TYPE xFileNumber, xReadNumber;
char cFileName[ fsMAX_FILE_NAME_LEN ];
long lItemsRead, lChar;
F_FILE *pxFile;
/* Read back the files that were created by
prvCreateDemoFilesUsing_f_write(). */
for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )
{
/* Generate the file name. */
sprintf( cFileName, "root%03d.txt", xFileNumber );
/* Obtain the current working directory and print out the file name and
the directory from which the file is being read. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "Reading file %s from %s\r\n", cFileName, cRAMBuffer );
/* Open the file for reading. */
pxFile = f_open( cFileName, "r" );
configASSERT( pxFile );
/* Read the file into the RAM buffer, checking the file contents are as
expected. The size of the file depends on the file number. */
for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )
{
/* Start with the RAM buffer clear. */
memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );
lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
configASSERT( lItemsRead == 1 );
/* Check the RAM buffer is filled with the expected data. Each
file contains a different repeating ascii character that indicates
the number of the file. */
for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )
{
configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );
}
}
/* Close the file. */
f_close( pxFile );
}
}
/*-----------------------------------------------------------*/
static void prvCreateDemoFileUsing_f_putc( void )
{
unsigned char ucReturn;
int iByte, iReturned;
F_FILE *pxFile;
char cFileName[ fsMAX_FILE_NAME_LEN ];
/* Obtain and print out the working directory. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "In directory %s\r\n", cRAMBuffer );
/* Create a sub directory. */
ucReturn = f_mkdir( pcDirectory1 );
configASSERT( ucReturn == F_NO_ERROR );
/* Move into the created sub-directory. */
ucReturn = f_chdir( pcDirectory1 );
configASSERT( ucReturn == F_NO_ERROR );
/* Obtain and print out the working directory. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "In directory %s\r\n", cRAMBuffer );
/* Create a subdirectory in the new directory. */
ucReturn = f_mkdir( pcDirectory2 );
configASSERT( ucReturn == F_NO_ERROR );
/* Move into the directory just created - now two directories down from
the root. */
ucReturn = f_chdir( pcDirectory2 );
configASSERT( ucReturn == F_NO_ERROR );
/* Obtain and print out the working directory. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "In directory %s\r\n", cRAMBuffer );
configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );
/* Generate the file name. */
sprintf( cFileName, "%s.txt", pcDirectory2 );
/* Print out the file name and the directory into which the file is being
written. */
printf( "Writing file %s in %s\r\n", cFileName, cRAMBuffer );
pxFile = f_open( cFileName, "w" );
/* Create a file 1 byte at a time. The file is filled with incrementing
ascii characters starting from '0'. */
for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
{
iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );
configASSERT( iReturned == ( ( int ) '0' + iByte ) );
}
/* Finished so close the file. */
f_close( pxFile );
/* Move back to the root directory. */
ucReturn = f_chdir( "../.." );
configASSERT( ucReturn == F_NO_ERROR );
/* Obtain and print out the working directory. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "Back in root directory %s\r\n", cRAMBuffer );
configASSERT( strcmp( ( const char * ) cRAMBuffer, pcRoot ) == 0 );
}
/*-----------------------------------------------------------*/
static void prvVerifyDemoFileUsing_f_getc( void )
{
unsigned char ucReturn;
int iByte, iReturned;
F_FILE *pxFile;
char cFileName[ fsMAX_FILE_NAME_LEN ];
/* Move into the directory in which the file was created. */
ucReturn = f_chdir( pcFullPath );
configASSERT( ucReturn == F_NO_ERROR );
/* Obtain and print out the working directory. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "Back in directory %s\r\n", cRAMBuffer );
configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );
/* Generate the file name. */
sprintf( cFileName, "%s.txt", pcDirectory2 );
/* Print out the file name and the directory from which the file is being
read. */
printf( "Reading file %s in %s\r\n", cFileName, cRAMBuffer );
/* This time the file is opened for reading. */
pxFile = f_open( cFileName, "r" );
/* Read the file 1 byte at a time. */
for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
{
iReturned = f_getc( pxFile );
configASSERT( iReturned == ( ( int ) '0' + iByte ) );
}
/* Finished so close the file. */
f_close( pxFile );
/* Move back to the root directory. */
ucReturn = f_chdir( "../.." );
configASSERT( ucReturn == F_NO_ERROR );
/* Obtain and print out the working directory. */
f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
printf( "Back in root directory %s\r\n", cRAMBuffer );
}

432
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/Sample-CLI-commands.c
Unescape Escape View File

@ -0,0 +1,432 @@
/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not itcan be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/******************************************************************************
*
* See the following URL for information on the commands defined in this file:
* http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
*
******************************************************************************/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Standard includes. */
#include <stdint.h>
#include <stdio.h>
#include <string.h>
/* FreeRTOS+CLI includes. */
#include "FreeRTOS_CLI.h"
#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS
#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
#endif
/*
* Implements the run-time-stats command.
*/
static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the task-stats command.
*/
static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the echo-three-parameters command.
*/
static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Implements the echo-parameters command.
*/
static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
/*
* Registers the CLI commands defined within this file with the FreeRTOS+CLI
* command line interface.
*/
void vRegisterSampleCLICommands( void );
/*
* Implements the "trace start" and "trace stop" commands;
*/
#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
#endif
/* Structure that defines the "run-time-stats" command line command. This
generates a table that shows how much run time each task has */
static const CLI_Command_Definition_t xRunTimeStats =
{
"run-time-stats", /* The command string to type. */
"\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",
prvRunTimeStatsCommand, /* The function to run. */
0 /* No parameters are expected. */
};
/* Structure that defines the "task-stats" command line command. This generates
a table that gives information on each task in the system. */
static const CLI_Command_Definition_t xTaskStats =
{
"task-stats", /* The command string to type. */
"\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",
prvTaskStatsCommand, /* The function to run. */
0 /* No parameters are expected. */
};
/* Structure that defines the "echo_3_parameters" command line command. This
takes exactly three parameters that the command simply echos back one at a
time. */
static const CLI_Command_Definition_t xThreeParameterEcho =
{
"echo-3-parameters",
"\r\necho-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n",
prvThreeParameterEchoCommand, /* The function to run. */
3 /* Three parameters are expected, which can take any value. */
};
/* Structure that defines the "echo_parameters" command line command. This
takes a variable number of parameters that the command simply echos back one at
a time. */
static const CLI_Command_Definition_t xParameterEcho =
{
"echo-parameters",
"\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",
prvParameterEchoCommand, /* The function to run. */
-1 /* The user can enter any number of commands. */
};
#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
/* Structure that defines the "trace" command line command. This takes a single
parameter, which can be either "start" or "stop". */
static const CLI_Command_Definition_t xStartStopTrace =
{
"trace",
"\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",
prvStartStopTraceCommand, /* The function to run. */
1 /* One parameter is expected. Valid values are "start" and "stop". */
};
#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
/*-----------------------------------------------------------*/
void vRegisterSampleCLICommands( void )
{
/* Register all the command line commands defined immediately above. */
FreeRTOS_CLIRegisterCommand( &xTaskStats );
FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
FreeRTOS_CLIRegisterCommand( &xParameterEcho );
#if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )
{
FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
}
#endif
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
const int8_t *const pcHeader = ( int8_t * ) "Task State Priority Stack #\r\n************************************************\r\n";
/* Remove compile time warnings about unused parameters, and check the
write buffer is not NULL. NOTE - for simplicity, this example assumes the
write buffer length is adequate, so does not check for buffer overflows. */
( void ) pcCommandString;
( void ) xWriteBufferLen;
configASSERT( pcWriteBuffer );
/* Generate a table of task stats. */
strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
/* There is no more data to return after this single string, so return
pdFALSE. */
return pdFALSE;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
const int8_t * const pcHeader = ( int8_t * ) "Task Abs Time % Time\r\n****************************************\r\n";
/* Remove compile time warnings about unused parameters, and check the
write buffer is not NULL. NOTE - for simplicity, this example assumes the
write buffer length is adequate, so does not check for buffer overflows. */
( void ) pcCommandString;
( void ) xWriteBufferLen;
configASSERT( pcWriteBuffer );
/* Generate a table of task stats. */
strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
/* There is no more data to return after this single string, so return
pdFALSE. */
return pdFALSE;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcParameter;
portBASE_TYPE xParameterStringLength, xReturn;
static portBASE_TYPE lParameterNumber = 0;
/* Remove compile time warnings about unused parameters, and check the
write buffer is not NULL. NOTE - for simplicity, this example assumes the
write buffer length is adequate, so does not check for buffer overflows. */
( void ) pcCommandString;
( void ) xWriteBufferLen;
configASSERT( pcWriteBuffer );
if( lParameterNumber == 0 )
{
/* The first time the function is called after the command has been
entered just a header string is returned. */
sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );
/* Next time the function is called the first parameter will be echoed
back. */
lParameterNumber = 1L;
/* There is more data to be returned as no parameters have been echoed
back yet. */
xReturn = pdPASS;
}
else
{
/* Obtain the parameter string. */
pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
lParameterNumber, /* Return the next parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcParameter );
/* Return the parameter string. */
memset( pcWriteBuffer, 0x00, xWriteBufferLen );
sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
/* If this is the last of the three parameters then there are no more
strings to return after this one. */
if( lParameterNumber == 3L )
{
/* If this is the last of the three parameters then there are no more
strings to return after this one. */
xReturn = pdFALSE;
lParameterNumber = 0L;
}
else
{
/* There are more parameters to return after this one. */
xReturn = pdTRUE;
lParameterNumber++;
}
}
return xReturn;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcParameter;
portBASE_TYPE xParameterStringLength, xReturn;
static portBASE_TYPE lParameterNumber = 0;
/* Remove compile time warnings about unused parameters, and check the
write buffer is not NULL. NOTE - for simplicity, this example assumes the
write buffer length is adequate, so does not check for buffer overflows. */
( void ) pcCommandString;
( void ) xWriteBufferLen;
configASSERT( pcWriteBuffer );
if( lParameterNumber == 0 )
{
/* The first time the function is called after the command has been
entered just a header string is returned. */
sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );
/* Next time the function is called the first parameter will be echoed
back. */
lParameterNumber = 1L;
/* There is more data to be returned as no parameters have been echoed
back yet. */
xReturn = pdPASS;
}
else
{
/* Obtain the parameter string. */
pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
lParameterNumber, /* Return the next parameter. */
&xParameterStringLength /* Store the parameter string length. */
);
if( pcParameter != NULL )
{
/* Return the parameter string. */
memset( pcWriteBuffer, 0x00, xWriteBufferLen );
sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
/* There might be more parameters to return after this one. */
xReturn = pdTRUE;
lParameterNumber++;
}
else
{
/* No more parameters were found. Make sure the write buffer does
not contain a valid string. */
pcWriteBuffer[ 0 ] = 0x00;
/* No more data to return. */
xReturn = pdFALSE;
/* Start over the next time this command is executed. */
lParameterNumber = 0;
}
}
return xReturn;
}
/*-----------------------------------------------------------*/
#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
{
int8_t *pcParameter;
portBASE_TYPE lParameterStringLength;
/* Remove compile time warnings about unused parameters, and check the
write buffer is not NULL. NOTE - for simplicity, this example assumes the
write buffer length is adequate, so does not check for buffer overflows. */
( void ) pcCommandString;
( void ) xWriteBufferLen;
configASSERT( pcWriteBuffer );
/* Obtain the parameter string. */
pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
(
pcCommandString, /* The command string itself. */
1, /* Return the first parameter. */
&lParameterStringLength /* Store the parameter string length. */
);
/* Sanity check something was returned. */
configASSERT( pcParameter );
/* There are only two valid parameter values. */
if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )
{
/* Start or restart the trace. */
vTraceStop();
vTraceClear();
vTraceStart();
sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );
}
else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )
{
/* End the trace, if one is running. */
vTraceStop();
sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );
}
else
{
sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
}
/* There is no more data to return after this single string, so return
pdFALSE. */
return pdFALSE;
}
#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */

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/*
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Standard includes. */
#include "string.h"
#include "stdio.h"
#include "stdint.h"
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Common demo includes. */
#include "serial.h"
/* Example includes. */
#include "FreeRTOS_CLI.h"
#include "UARTCommandConsole.h"
/* Dimensions the buffer into which input characters are placed. */
#define cmdMAX_INPUT_SIZE 50
/* The maximum time in ticks to wait for the UART access mutex. */
#define cmdMAX_MUTEX_WAIT ( 200 / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* The task that implements the command console processing.
*/
static void prvUARTCommandConsoleTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* Const messages output by the command console. */
static const signed char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
static const signed char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";
static const signed char * const pcNewLine = "\r\n";
/*-----------------------------------------------------------*/
void vUARTCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority )
{
/* Create that task that handles the console itself. */
xTaskCreate( prvUARTCommandConsoleTask, /* The task that implements the command console. */
"CLI", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */
usStackSize, /* The size of the stack allocated to the task. */
NULL, /* The parameter is not used, so NULL is passed. */
uxPriority, /* The priority allocated to the task. */
NULL ); /* A handle is not required, so just pass NULL. */
}
/*-----------------------------------------------------------*/
static void prvUARTCommandConsoleTask( void *pvParameters )
{
int8_t cRxedChar, cInputIndex = 0, *pcOutputString;
static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
portBASE_TYPE xReturned;
( void ) pvParameters;
/* Obtain the address of the output buffer. Note there is no mutual
exclusion on this buffer as it is assumed only one command console
interface will be used at any one time. */
pcOutputString = FreeRTOS_CLIGetOutputBuffer();
/* Send the welcome message. */
vSerialPutString( NULL, pcWelcomeMessage, strlen( ( char * ) pcWelcomeMessage ) );
for( ;; )
{
/* Only interested in reading one character at a time. */
while( xSerialGetChar( NULL, &cRxedChar, portMAX_DELAY ) == pdFALSE );
/* Echo the character back. */
xSerialPutChar( NULL, cRxedChar, portMAX_DELAY );
/* Was it the end of the line? */
if( cRxedChar == '\n' || cRxedChar == '\r' )
{
/* Just to space the output from the input. */
vSerialPutString( NULL, pcNewLine, strlen( ( char * ) pcNewLine ) );
/* See if the command is empty, indicating that the last command is
to be executed again. */
if( cInputIndex == 0 )
{
/* Copy the last command back into the input string. */
strcpy( ( char * ) cInputString, ( char * ) cLastInputString );
}
/* Pass the received command to the command interpreter. The
command interpreter is called repeatedly until it returns pdFALSE
(indicating there is no more output) as it might generate more than
one string. */
do
{
/* Get the next output string from the command interpreter. */
xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
/* Write the generated string to the UART. */
vSerialPutString( NULL, pcOutputString, strlen( ( char * ) pcOutputString ) );
} while( xReturned != pdFALSE );
/* All the strings generated by the input command have been sent.
Clear the input string ready to receive the next command. Remember
the command that was just processed first in case it is to be
processed again. */
strcpy( ( char * ) cLastInputString, ( char * ) cInputString );
cInputIndex = 0;
memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
vSerialPutString( NULL, pcEndOfOutputMessage, strlen( ( char * ) pcEndOfOutputMessage ) );
}
else
{
if( cRxedChar == '\r' )
{
/* Ignore the character. */
}
else if( cRxedChar == '\b' )
{
/* Backspace was pressed. Erase the last character in the
string - if any. */
if( cInputIndex > 0 )
{
cInputIndex--;
cInputString[ cInputIndex ] = '\0';
}
}
else
{
/* A character was entered. Add it to the string
entered so far. When a \n is entered the complete
string will be passed to the command interpreter. */
if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
{
if( cInputIndex < cmdMAX_INPUT_SIZE )
{
cInputString[ cInputIndex ] = cRxedChar;
cInputIndex++;
}
}
}
}
}
}
/*-----------------------------------------------------------*/

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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
#ifndef UART_COMMAND_CONSOLE_H
#define UART_COMMAND_CONSOLE_H
/*
* Create the task that implements a command console using the USB virtual com
* port driver for intput and output.
*/
void vUARTCommandConsoleStart( unsigned short usStackSize, unsigned portBASE_TYPE uxPriority );
#endif /* UART_COMMAND_CONSOLE_H */

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/*
* FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded
*
* FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
* Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
* the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
* and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
* license model, information on which is provided below:
*
* - Open source licensing -
* FreeRTOS+FAT SL is a free download and may be used, modified and distributed
* without charge provided the user adheres to version two of the GNU General
* Public license (GPL) and does not remove the copyright notice or this text.
* The GPL V2 text is available on the gnu.org web site, and on the following
* URL: http://www.FreeRTOS.org/gpl-2.0.txt
*
* - Commercial licensing -
* Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
* proprietary software for redistribution in any form must first obtain a
* commercial license - and in-so-doing support the maintenance, support and
* further development of the FreeRTOS+FAT SL product. Commercial licenses can
* be obtained from http://shop.freertos.org and do not require any source files
* to be changed.
*
* FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
* cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
* is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
* implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
* PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
* conditions and terms, be they implied, expressed, or statutory.
*
* http://www.FreeRTOS.org
* http://www.FreeRTOS.org/FreeRTOS-Plus
*
*/
#ifndef _CONFIG_FAT_SL_H
#define _CONFIG_FAT_SL_H
#include "../version/ver_fat_sl.h"
#if VER_FAT_SL_MAJOR != 3 || VER_FAT_SL_MINOR != 2
#error Incompatible FAT_SL version number!
#endif
#include "../api/api_mdriver.h"
#ifdef __cplusplus
extern "C" {
#endif
/**************************************************************************
**
** FAT SL user settings
**
**************************************************************************/
#define F_SECTOR_SIZE 512u /* Disk sector size. */
#define F_FS_THREAD_AWARE 0 /* Set to one if the file system will be access from more than one task. */
#define F_MAXPATH 64 /* Maximum length a file name (including its full path) can be. */
#define F_MAX_LOCK_WAIT_TICKS 20 /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */
#ifdef __cplusplus
}
#endif
#endif /* _CONFIG_FAT_SL_H */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_mdriver_ram.h
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/*
* FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded
*
* FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
* Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
* the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
* and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
* license model, information on which is provided below:
*
* - Open source licensing -
* FreeRTOS+FAT SL is a free download and may be used, modified and distributed
* without charge provided the user adheres to version two of the GNU General
* Public license (GPL) and does not remove the copyright notice or this text.
* The GPL V2 text is available on the gnu.org web site, and on the following
* URL: http://www.FreeRTOS.org/gpl-2.0.txt
*
* - Commercial licensing -
* Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
* proprietary software for redistribution in any form must first obtain a
* commercial license - and in-so-doing support the maintenance, support and
* further development of the FreeRTOS+FAT SL product. Commercial licenses can
* be obtained from http://shop.freertos.org and do not require any source files
* to be changed.
*
* FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
* cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
* is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
* implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
* PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
* conditions and terms, be they implied, expressed, or statutory.
*
* http://www.FreeRTOS.org
* http://www.FreeRTOS.org/FreeRTOS-Plus
*
*/
#ifndef _CONFIG_MDRIVER_RAM_H_
#define _CONFIG_MDRIVER_RAM_H_
#include "../version/ver_mdriver_ram.h"
#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2
#error Incompatible MDRIVER_RAM version number!
#endif
#define MDRIVER_RAM_SECTOR_SIZE 512 /* Sector size */
#define MDRIVER_RAM_VOLUME0_SIZE (64 * 1024) /* defintion for size of ramdrive0 */
#define MDRIVER_MEM_LONG_ACCESS 1 /* set this value to 1 if 32bit access available */
#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */

518
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the comprehensive test and demo version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
* NOTE 3: If mainINCLUDE_FAT_SL_DEMO is set to 1 then the UART is used to
* interface to the FreeRTOS+CLI command line interface. If
* mainINCLUDE_FAT_SL_DEMO is set to 0 then the UART is used to run the standard
* COM test tasks and a loopback connector must be fitted to the UART port
* because the test expects to receive every character that is transmitted. A
* simple loopback connector can be created by linking pins 2 and 3 of the 9 way
* UART connector.
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* FreeRTOS+CLI command console. The command console is access through UART2
* using 115200 baud if mainINCLUDE_FAT_SL_DEMO is set to 1. For reasons of
* robustness testing the UART driver is deliberately written to be inefficient
* and should not be used as a template for a production driver. Type "help" to
* see a list of registered commands. The FreeRTOS+CLI license is different to
* the FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage
* details.
*
* FreeRTOS+FAT SL. FreeRTOS+FAT SL is demonstrated using a RAM disk if
* mainINCLUDE_FAT_SL_DEMO is set to 1. [At the time of writing] The
* functionality of the file system demo is identical to the functionality of
* the FreeRTOS Win32 simulator file system demo, with the command console being
* accessed via the UART (as described above) instead of a network terminal.
* The FreeRTOS+FAT SL license is different to the FreeRTOS license, see
* http://www.FreeRTOS.org/fat_sl for license and usage details, and a
* description of the file system demo functionality.
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" task - The check task period is initially set to three seconds. The
* task checks that all the standard demo tasks, and the register check tasks,
* are not only still executing, but are executing without reporting any errors.
* If the check task discovers that a task has either stalled, or reported an
* error, then it changes its own execution period from the initial three
* seconds, to just 200ms. The check task also toggles an LED each time it is
* called. This provides a visual indication of the system status: If the LED
* toggles every three seconds, then no issues have been discovered. If the LED
* toggles every 200ms, then an issue has been discovered with at least one
* task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "semtest.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "death.h"
#include "partest.h"
#include "comtest2.h"
#include "serial.h"
#include "TimerDemo.h"
/* FreeRTOS+CLI and FreeRTOS+FAT SL includes. */
#include "UARTCommandConsole.h"
/* Either the FreeRTOS+FAT SL demo or the COM test demo can be build into the
project, not both (because they use the same UART). Set
configINCLUDE_FAT_SL_DEMO to 1 to include the FreeRTOS+FAT SL (and therefore
also FreeRTOS+CLI) demo in the build. Set configINCLUDE_FAT_SL_DEMO to 0 to
include the COM test tasks. The COM test tasks require a loop back connector
to be fitted to the UART port. */
#define mainINCLUDE_FAT_SL_DEMO 0
/* Priorities for the demo application tasks. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
/* The priority used by the UART command console task. */
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/* The LED used by the check timer. */
#define mainCHECK_LED ( 0 )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* In this example the baud rate is hard coded and there is no LED for use by
the COM test tasks, so just set both to invalid values. */
#define mainCOM_TEST_LED ( 100 )
#define mainBAUD_RATE ( 0 )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_RATE_MS constant. */
#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_RATE_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_RATE_MS constant. */
#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_RATE_MS )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
/* The length of queues used to pass characters into and out of the UART
interrupt. Note the comments above about the UART driver being implemented in
this way to test the kernel robustness rather than to provide a template for an
efficient production driver. */
#define mainUART_QUEUE_LENGTHS 10
/*-----------------------------------------------------------*/
/*
* Called by main() to run the full demo (as opposed to the blinky demo) when
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
void main_full( void );
/*
* The check task, as described at the top of this file.
*/
static void prvCheckTask( void *pvParameters );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file, but the
* entry points are kept in the C file for the convenience of checking the task
* parameter.
*/
static void prvRegTestTaskEntry1( void *pvParameters );
extern void vRegTest1Implementation( void );
static void prvRegTestTaskEntry2( void *pvParameters );
extern void vRegTest2Implementation( void );
/*
* Register commands that can be used with FreeRTOS+CLI. The commands are
* defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
*/
extern void vRegisterSampleCLICommands( void );
extern void vRegisterFileSystemCLICommands( void );
/*
* Creates and verifies different files on the volume, demonstrating the use of
* various different API functions.
*/
extern void vCreateAndVerifySampleFiles( void );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check software timer. If the variables keep
incrementing, then the register check tasks has not discovered any errors. If
a variable stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
void main_full( void )
{
/* The baud rate setting here has no effect, hence it is set to 0 to
make that obvious. */
xSerialPortInitMinimal( 0, mainUART_QUEUE_LENGTHS );
/* If the file system is only going to be accessed from one task then
F_FS_THREAD_AWARE can be set to 0 and the set of example files are created
before the RTOS scheduler is started. If the file system is going to be
access from more than one task then F_FS_THREAD_AWARE must be set to 1 and
the set of sample files are created from the idle task hook function
vApplicationIdleHook() - which is defined in this file. */
#if ( mainINCLUDE_FAT_SL_DEMO == 1 )&& ( F_FS_THREAD_AWARE == 0 )
{
/* Initialise the drive and file system, then create a few example
files. The output from this function just goes to the stdout window,
allowing the output to be viewed when the UDP command console is not
connected. */
vCreateAndVerifySampleFiles();
}
#endif
/* Start all the other standard demo/test tasks. The have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
#if mainINCLUDE_FAT_SL_DEMO == 1
{
/* Start the tasks that implements the command console on the UART, as
described above. */
vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );
/* Register both the standard and file system related CLI commands. */
vRegisterSampleCLICommands();
vRegisterFileSystemCLICommands();
}
#else
{
/* The COM test tasks can use the UART if the CLI is not used by the
FAT SL demo. The COM test tasks require a UART connector to be fitted
to the UART port. */
vAltStartComTestTasks( mainCOM_TEST_TASK_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );
}
#endif
/* Create the register check tasks, as described at the top of this
file */
xTaskCreate( prvRegTestTaskEntry1, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTestTaskEntry2, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
xTaskCreate( prvCheckTask, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* The set of tasks created by the following function call have to be
created last as they keep account of the number of tasks they expect to see
running. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
portTickType xLastExecutionTime;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The onboard LED is toggled on each iteration.
If an error is detected then the delay period is decreased from
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
effect of increasing the rate at which the onboard LED toggles, and in so
doing gives visual feedback of the system status. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreTimerDemoTasksStillRunning( ( portTickType ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )
{
ulErrorFound = pdTRUE;
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
#if mainINCLUDE_FAT_SL_DEMO == 0
{
if( xAreComTestTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
}
#endif
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
everything is ok. A faster toggle indicates an error. */
vParTestToggleLED( mainCHECK_LED );
if( ulErrorFound != pdFALSE )
{
/* An error has been detected in one of the tasks - flash the LED
at a higher frequency to give visible feedback that something has
gone wrong (it might just be that the loop back connector required
by the comtest tasks has not been fitted). */
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
}
}
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry1( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
{
/* The reg test task also tests the floating point registers. Tasks
that use the floating point unit must call vPortTaskUsesFPU() before
any floating point instructions are executed. */
vPortTaskUsesFPU();
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check timer will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry2( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
{
/* The reg test task also tests the floating point registers. Tasks
that use the floating point unit must call vPortTaskUsesFPU() before
any floating point instructions are executed. */
vPortTaskUsesFPU();
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check timer will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/

670
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/reg_test.s
Unescape Escape View File

@ -0,0 +1,670 @@
;/*
; FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
;
; FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
; http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
;
; ***************************************************************************
; * *
; * FreeRTOS tutorial books are available in pdf and paperback. *
; * Complete, revised, and edited pdf reference manuals are also *
; * available. *
; * *
; * Purchasing FreeRTOS documentation will not only help you, by *
; * ensuring you get running as quickly as possible and with an *
; * in-depth knowledge of how to use FreeRTOS, it will also help *
; * the FreeRTOS project to continue with its mission of providing *
; * professional grade, cross platform, de facto standard solutions *
; * for microcontrollers - completely free of charge! *
; * *
; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
; * *
; * Thank you for using FreeRTOS, and thank you for your support! *
; * *
; ***************************************************************************
;
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
;
; >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
; distribute a combined work that includes FreeRTOS without being obliged to
; provide the source code for proprietary components outside of the FreeRTOS
; kernel.
;
; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
; FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
; details. You should have received a copy of the GNU General Public License
; and the FreeRTOS license exception along with FreeRTOS; if not itcan be
; viewed here: http://www.freertos.org/a00114.html and also obtained by
; writing to Real Time Engineers Ltd., contact details for whom are available
; on the FreeRTOS WEB site.
;
; 1 tab == 4 spaces!
;
; ***************************************************************************
; * *
; * Having a problem? Start by reading the FAQ "My application does *
; * not run, what could be wrong?" *
; * *
; * http://www.FreeRTOS.org/FAQHelp.html *
; * *
; ***************************************************************************
;
;
; http://www.FreeRTOS.org - Documentation, books, training, latest versions,
; license and Real Time Engineers Ltd. contact details.
;
; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
; including FreeRTOS+Trace - an indispensable productivity tool, and our new
; fully thread aware and reentrant UDP/IP stack.
;
; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
; Integrity Systems, who sell the code with commercial support,
; indemnification and middleware, under the OpenRTOS brand.
;
; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
; engineered and independently SIL3 certified version for use in safety and
; mission critical applications that require provable dependability.
;*/
EXPORT vRegTest1Implementation
EXPORT vRegTest2Implementation
; This file is built with IAR and ARM compilers. When the ARM compiler
; is used the compiler options must define __IASMARM__ as 0 using the
; --predefine "__IASMARM__ SETA 0" command line option. When compiling
; with IAR __IASMARM__ is automatically set to 1 so no additional assembler
; options are required.
if __IASMARM__ == 1
; Syntax for IAR compiler.
SECTION .text:CODE:ROOT(2)
else
; Syntax for ARM compiler.
AREA RegTest, CODE, READONLY
endif
ARM
; This function is explained in the comments at the top of main-full.c.
vRegTest1Implementation
PRESERVE8
IMPORT ulRegTest1LoopCounter
; Fill each general purpose register with a known value.
mov r0, #0xFF
mov r1, #0x11
mov r2, #0x22
mov r3, #0x33
mov r4, #0x44
mov r5, #0x55
mov r6, #0x66
mov r7, #0x77
mov r8, #0x88
mov r9, #0x99
mov r10, #0xAA
mov r11, #0xBB
mov r12, #0xCC
mov r14, #0xEE
; Fill each FPU register with a known value.
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
vmov d16, r0, r1
vmov d17, r2, r3
vmov d18, r4, r5
vmov d19, r6, r7
vmov d20, r8, r9
vmov d21, r10, r11
vmov d22, r0, r1
vmov d23, r2, r3
vmov d24, r4, r5
vmov d25, r6, r7
vmov d26, r8, r9
vmov d27, r10, r11
vmov d28, r0, r1
vmov d29, r2, r3
vmov d30, r4, r5
vmov d31, r6, r7
; Loop, checking each itteration that each register still contains the
; expected value.
reg1_loop
; Yield to increase test coverage
svc 0
; Check all the VFP registers still contain the values set above.
; First save registers that are clobbered by the test.
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #0xFF
bne reg1_error_loopf
cmp r1, #0x11
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #0x22
bne reg1_error_loopf
cmp r1, #0x33
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #0x44
bne reg1_error_loopf
cmp r1, #0x55
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #0x66
bne reg1_error_loopf
cmp r1, #0x77
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #0x88
bne reg1_error_loopf
cmp r1, #0x99
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #0xAA
bne reg1_error_loopf
cmp r1, #0xBB
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #0xFF
bne reg1_error_loopf
cmp r1, #0x11
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #0x22
bne reg1_error_loopf
cmp r1, #0x33
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #0x44
bne reg1_error_loopf
cmp r1, #0x55
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #0x66
bne reg1_error_loopf
cmp r1, #0x77
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #0x88
bne reg1_error_loopf
cmp r1, #0x99
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #0xAA
bne reg1_error_loopf
cmp r1, #0xBB
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #0xFF
bne reg1_error_loopf
cmp r1, #0x11
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #0x22
bne reg1_error_loopf
cmp r1, #0x33
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #0x44
bne reg1_error_loopf
cmp r1, #0x55
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #0x66
bne reg1_error_loopf
cmp r1, #0x77
bne reg1_error_loopf
vmov r0, r1, d16
cmp r0, #0xFF
bne reg1_error_loopf
cmp r1, #0x11
bne reg1_error_loopf
vmov r0, r1, d17
cmp r0, #0x22
bne reg1_error_loopf
cmp r1, #0x33
bne reg1_error_loopf
vmov r0, r1, d18
cmp r0, #0x44
bne reg1_error_loopf
cmp r1, #0x55
bne reg1_error_loopf
vmov r0, r1, d19
cmp r0, #0x66
bne reg1_error_loopf
cmp r1, #0x77
bne reg1_error_loopf
vmov r0, r1, d20
cmp r0, #0x88
bne reg1_error_loopf
cmp r1, #0x99
bne reg1_error_loopf
vmov r0, r1, d21
cmp r0, #0xAA
bne reg1_error_loopf
cmp r1, #0xBB
bne reg1_error_loopf
vmov r0, r1, d22
cmp r0, #0xFF
bne reg1_error_loopf
cmp r1, #0x11
bne reg1_error_loopf
vmov r0, r1, d23
cmp r0, #0x22
bne reg1_error_loopf
cmp r1, #0x33
bne reg1_error_loopf
vmov r0, r1, d24
cmp r0, #0x44
bne reg1_error_loopf
cmp r1, #0x55
bne reg1_error_loopf
vmov r0, r1, d25
cmp r0, #0x66
bne reg1_error_loopf
cmp r1, #0x77
bne reg1_error_loopf
vmov r0, r1, d26
cmp r0, #0x88
bne reg1_error_loopf
cmp r1, #0x99
bne reg1_error_loopf
vmov r0, r1, d27
cmp r0, #0xAA
bne reg1_error_loopf
cmp r1, #0xBB
bne reg1_error_loopf
vmov r0, r1, d28
cmp r0, #0xFF
bne reg1_error_loopf
cmp r1, #0x11
bne reg1_error_loopf
vmov r0, r1, d29
cmp r0, #0x22
bne reg1_error_loopf
cmp r1, #0x33
bne reg1_error_loopf
vmov r0, r1, d30
cmp r0, #0x44
bne reg1_error_loopf
cmp r1, #0x55
bne reg1_error_loopf
vmov r0, r1, d31
cmp r0, #0x66
bne reg1_error_loopf
cmp r1, #0x77
bne reg1_error_loopf
; Restore the registers that were clobbered by the test.
pop {r0-r1}
; VFP register test passed. Jump to the core register test.
b reg1_loopf_pass
reg1_error_loopf
; If this line is hit then a VFP register value was found to be
; incorrect.
b reg1_error_loopf
reg1_loopf_pass
; Test each general purpose register to check that it still contains the
; expected known value, jumping to reg1_error_loop if any register contains
; an unexpected value.
cmp r0, #0xFF
bne reg1_error_loop
cmp r1, #0x11
bne reg1_error_loop
cmp r2, #0x22
bne reg1_error_loop
cmp r3, #0x33
bne reg1_error_loop
cmp r4, #0x44
bne reg1_error_loop
cmp r5, #0x55
bne reg1_error_loop
cmp r6, #0x66
bne reg1_error_loop
cmp r7, #0x77
bne reg1_error_loop
cmp r8, #0x88
bne reg1_error_loop
cmp r9, #0x99
bne reg1_error_loop
cmp r10, #0xAA
bne reg1_error_loop
cmp r11, #0xBB
bne reg1_error_loop
cmp r12, #0xCC
bne reg1_error_loop
cmp r14, #0xEE
bne reg1_error_loop
; Everything passed, increment the loop counter.
push { r0-r1 }
ldr r0, =ulRegTest1LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
; Start again.
b reg1_loop
reg1_error_loop
; If this line is hit then there was an error in a core register value.
; The loop ensures the loop counter stops incrementing.
b reg1_error_loop
nop
;/*-----------------------------------------------------------*/
vRegTest2Implementation
PRESERVE8
IMPORT ulRegTest2LoopCounter
; Put a known value in each register.
mov r0, #0xFF000000
mov r1, #0x11000000
mov r2, #0x22000000
mov r3, #0x33000000
mov r4, #0x44000000
mov r5, #0x55000000
mov r6, #0x66000000
mov r7, #0x77000000
mov r8, #0x88000000
mov r9, #0x99000000
mov r10, #0xAA000000
mov r11, #0xBB000000
mov r12, #0xCC000000
mov r14, #0xEE000000
; Likewise the floating point registers
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
vmov d16, r0, r1
vmov d17, r2, r3
vmov d18, r4, r5
vmov d19, r6, r7
vmov d20, r8, r9
vmov d21, r10, r11
vmov d22, r0, r1
vmov d23, r2, r3
vmov d24, r4, r5
vmov d25, r6, r7
vmov d26, r8, r9
vmov d27, r10, r11
vmov d28, r0, r1
vmov d29, r2, r3
vmov d30, r4, r5
vmov d31, r6, r7
; Loop, checking each itteration that each register still contains the
; expected value.
reg2_loop
; Check all the VFP registers still contain the values set above.
; First save registers that are clobbered by the test.
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #0xFF000000
bne reg2_error_loopf
cmp r1, #0x11000000
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #0x22000000
bne reg2_error_loopf
cmp r1, #0x33000000
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #0x44000000
bne reg2_error_loopf
cmp r1, #0x55000000
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #0x66000000
bne reg2_error_loopf
cmp r1, #0x77000000
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #0x88000000
bne reg2_error_loopf
cmp r1, #0x99000000
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #0xAA000000
bne reg2_error_loopf
cmp r1, #0xBB000000
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #0xFF000000
bne reg2_error_loopf
cmp r1, #0x11000000
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #0x22000000
bne reg2_error_loopf
cmp r1, #0x33000000
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #0x44000000
bne reg2_error_loopf
cmp r1, #0x55000000
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #0x66000000
bne reg2_error_loopf
cmp r1, #0x77000000
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #0x88000000
bne reg2_error_loopf
cmp r1, #0x99000000
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #0xAA000000
bne reg2_error_loopf
cmp r1, #0xBB000000
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #0xFF000000
bne reg2_error_loopf
cmp r1, #0x11000000
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #0x22000000
bne reg2_error_loopf
cmp r1, #0x33000000
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #0x44000000
bne reg2_error_loopf
cmp r1, #0x55000000
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #0x66000000
bne reg2_error_loopf
cmp r1, #0x77000000
bne reg2_error_loopf
vmov r0, r1, d16
cmp r0, #0xFF000000
bne reg2_error_loopf
cmp r1, #0x11000000
bne reg2_error_loopf
vmov r0, r1, d17
cmp r0, #0x22000000
bne reg2_error_loopf
cmp r1, #0x33000000
bne reg2_error_loopf
vmov r0, r1, d18
cmp r0, #0x44000000
bne reg2_error_loopf
cmp r1, #0x55000000
bne reg2_error_loopf
vmov r0, r1, d19
cmp r0, #0x66000000
bne reg2_error_loopf
cmp r1, #0x77000000
bne reg2_error_loopf
vmov r0, r1, d20
cmp r0, #0x88000000
bne reg2_error_loopf
cmp r1, #0x99000000
bne reg2_error_loopf
vmov r0, r1, d21
cmp r0, #0xAA000000
bne reg2_error_loopf
cmp r1, #0xBB000000
bne reg2_error_loopf
vmov r0, r1, d22
cmp r0, #0xFF000000
bne reg2_error_loopf
cmp r1, #0x11000000
bne reg2_error_loopf
vmov r0, r1, d23
cmp r0, #0x22000000
bne reg2_error_loopf
cmp r1, #0x33000000
bne reg2_error_loopf
vmov r0, r1, d24
cmp r0, #0x44000000
bne reg2_error_loopf
cmp r1, #0x55000000
bne reg2_error_loopf
vmov r0, r1, d25
cmp r0, #0x66000000
bne reg2_error_loopf
cmp r1, #0x77000000
bne reg2_error_loopf
vmov r0, r1, d26
cmp r0, #0x88000000
bne reg2_error_loopf
cmp r1, #0x99000000
bne reg2_error_loopf
vmov r0, r1, d27
cmp r0, #0xAA000000
bne reg2_error_loopf
cmp r1, #0xBB000000
bne reg2_error_loopf
vmov r0, r1, d28
cmp r0, #0xFF000000
bne reg2_error_loopf
cmp r1, #0x11000000
bne reg2_error_loopf
vmov r0, r1, d29
cmp r0, #0x22000000
bne reg2_error_loopf
cmp r1, #0x33000000
bne reg2_error_loopf
vmov r0, r1, d30
cmp r0, #0x44000000
bne reg2_error_loopf
cmp r1, #0x55000000
bne reg2_error_loopf
vmov r0, r1, d31
cmp r0, #0x66000000
bne reg2_error_loopf
cmp r1, #0x77000000
bne reg2_error_loopf
; Restore the registers that were clobbered by the test.
pop {r0-r1}
; VFP register test passed. Jump to the core register test.
b reg2_loopf_pass
reg2_error_loopf
; If this line is hit then a VFP register value was found to be
; incorrect.
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #0xFF000000
bne reg2_error_loop
cmp r1, #0x11000000
bne reg2_error_loop
cmp r2, #0x22000000
bne reg2_error_loop
cmp r3, #0x33000000
bne reg2_error_loop
cmp r4, #0x44000000
bne reg2_error_loop
cmp r5, #0x55000000
bne reg2_error_loop
cmp r6, #0x66000000
bne reg2_error_loop
cmp r7, #0x77000000
bne reg2_error_loop
cmp r8, #0x88000000
bne reg2_error_loop
cmp r9, #0x99000000
bne reg2_error_loop
cmp r10, #0xAA000000
bne reg2_error_loop
cmp r11, #0xBB000000
bne reg2_error_loop
cmp r12, #0xCC000000
bne reg2_error_loop
cmp r14, #0xEE000000
bne reg2_error_loop
; Everything passed, increment the loop counter.
push { r0-r1 }
ldr r0, =ulRegTest2LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
; Start again.
b reg2_loop
reg2_error_loop
; If this line is hit then there was an error in a core register value.
; The loop ensures the loop counter stops incrementing.
b reg2_error_loop
nop
END

301
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/serial.c
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART2.
***Note*** This example uses queues to send each character into an interrupt
service routine and out of an interrupt service routine individually. This
is done to demonstrate queues being used in an interrupt, and to deliberately
load the system to test the FreeRTOS port. It is *NOT* meant to be an
example of an efficient implementation. An efficient implementation should
use the DMA, and only use FreeRTOS API functions when enough has been
received to warrant a task being unblocked to process the data.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
#include "comtest2.h"
/* Driver includes. */
#include "r_typedefs.h"
#include "dev_drv.h"
#include "devdrv_scif_uart.h"
#include "sio_char.h"
#include "iodefine.h"
#include "devdrv_intc.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Misc defines. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Handlers for the Rx and Tx interrupts respectively. */
static void prvRXI_Handler( uint32_t ulUnusedParameter );
static void prvTXI_Handler( uint32_t ulUnusedParameter );
/*-----------------------------------------------------------*/
/* The queue used to hold received characters. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
/* Baud is set in IoInitScif2(), called in prvSetupHardware() in main.c. */
( void ) ulWantedBaud;
/* Create the queues used to hold Rx/Tx characters. Note the comments at
the top of this file regarding the use of queues in this manner. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
/* Register RXI and TXI handlers. */
R_INTC_RegistIntFunc( INTC_ID_RXI2, prvRXI_Handler );
R_INTC_RegistIntFunc( INTC_ID_TXI2, prvTXI_Handler );
/* Set both interrupts such that they can interrupt the tick. Also
set the Rx interrupt above the Tx interrupt in the hope that (for test
purposes) the Tx interrupt will interrupt the Rx interrupt. */
R_INTC_SetPriority( INTC_ID_RXI2, configMAX_API_CALL_INTERRUPT_PRIORITY );
R_INTC_SetPriority( INTC_ID_TXI2, ( configMAX_API_CALL_INTERRUPT_PRIORITY + 1 ) );
/* This driver is intended to test interrupt interactions, and not
intended to be efficient. Therefore set the RX trigger level to 1. */
SCIF2.SCFCR.BIT.RTRG = 0;
SCIF2.SCFCR.BIT.TTRG = 3;
/* Enable Rx interrupt. Tx interrupt will be enabled when a Tx is
performed. */
SCIF2.SCSCR.BIT.RIE = 1;
R_INTC_Enable( INTC_ID_RXI2 );
R_INTC_Enable( INTC_ID_TXI2 );
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return ( xComPortHandle ) 0;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports one port. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned portSHORT usStringLength )
{
signed char *pxNext;
/* A couple of parameters that this port does not use. */
( void ) usStringLength;
( void ) pxPort;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, portMAX_DELAY );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;
/* Note the comments at the top of this file regarding the use of queues in
this manner. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
{
xReturn = pdPASS;
/* Enable the interrupt which will remove the character from the
queue. */
SCIF2.SCSCR.BIT.TIE = 1;
}
else
{
xReturn = pdFAIL;
}
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/
static void prvRXI_Handler( uint32_t ulUnusedParameter )
{
unsigned char ucRxedByte;
long lHigherPriorityTaskWoken = pdFALSE;
/* The parameter is not used. It is only present because Renesas drivers
are used to install the interrupt handlers, and the drivers expect the
parameter to be present. */
( void ) ulUnusedParameter;
/* Note the comments at the top of this file regarding the use of queues in
this manner. */
while( ( SCIF2.SCFDR.WORD & 0x1F ) != 0 )
{
ucRxedByte = SCIF2.SCFRDR.BYTE;
xQueueSendFromISR( xRxedChars, &ucRxedByte, &lHigherPriorityTaskWoken );
}
SCIF2.SCFSR.BIT.RDF = 0;
/* If sending to the queue has caused a task to unblock, and the unblocked
task has a priority equal to or higher than the currently running task (the
task this ISR interrupted), then lHigherPriorityTaskWoken will have
automatically been set to pdTRUE within the queue send function.
portYIELD_FROM_ISR() will then ensure that this ISR returns directly to the
higher priority unblocked task. */
portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void prvTXI_Handler( uint32_t ulUnusedParameter )
{
unsigned char ucByte;
long lHigherPriorityTaskWoken = pdFALSE;
/* The parameter is not used. It is only present because Renesas drivers
are used to install the interrupt handlers, and the drivers expect the
parameter to be present. */
( void ) ulUnusedParameter;
/* Note the comments at the top of this file regarding the use of queues in
this manner. */
if( xQueueReceiveFromISR( xCharsForTx, &ucByte, &lHigherPriorityTaskWoken ) == pdPASS )
{
SCIF2.SCFTDR.BYTE = ucByte;
/* Clear TDRE and TEND flag */
SCIF2.SCFSR.WORD &= ~0x0060;
}
else
{
/* No more characters. Disable the interrupt. */
SCIF2.SCSCR.BIT.TIE = 0;
}
/* If receiving from the queue has caused a task to unblock, and the
unblocked task has a priority equal to or higher than the currently running
task (the task this ISR interrupted), then lHigherPriorityTaskWoken will
have automatically been set to pdTRUE within the queue receive function.
portYIELD_FROM_ISR() will then ensure that this ISR returns directly to the
higher priority unblocked task. */
portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/

145
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/LEDs.c
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/*-----------------------------------------------------------
* Simple IO routines to control the LEDs.
*-----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo includes. */
#include "partest.h"
/* Hardware specifics. */
#include "iodefine.h"
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* Initialise P4_10 for LED1. */
PORT4.PMCn.BIT.PMCn10 = 0;
PORT4.Pn.BIT.Pn10 = 1;
PORT4.PMn.BIT.PMn10 = 0;
PORT4.PIPCn.BIT.PIPCn10 = 0;
/* Initialise P4_11 for LED2. */
PORT4.PMCn.BIT.PMCn11 = 0;
PORT4.Pn.BIT.Pn11 = 1;
PORT4.PMn.BIT.PMn11 = 0;
PORT4.PIPCn.BIT.PIPCn11 = 0;
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned long ulLED, signed long xValue )
{
/* A high value turns the LED off. */
xValue = !xValue;
taskENTER_CRITICAL();
{
if( ulLED == 0 )
{
PORT4.Pn.BIT.Pn10 = xValue;
}
if( ulLED == 1 )
{
PORT4.Pn.BIT.Pn11 = xValue;
}
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned long ulLED )
{
taskENTER_CRITICAL();
{
if( ulLED == 0 )
{
PORT4.Pn.BIT.Pn10 = !PORT4.Pn.BIT.Pn10;
}
if( ulLED == 1 )
{
PORT4.Pn.BIT.Pn11 = !PORT4.Pn.BIT.Pn11;
}
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/

207
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/peripheral_init_basic.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : peripheral_init_basic.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Initialize peripheral function sample
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "devdrv_common.h" /* Common Driver Header */
#include "iodefine.h"
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_BASIC_SETUP"
#pragma arm section rodata = "CONST_BASIC_SETUP"
#pragma arm section rwdata = "DATA_BASIC_SETUP"
#pragma arm section zidata = "BSS_BASIC_SETUP"
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
void Peripheral_BasicInit(void);
/******************************************************************************
Private global variables and functions
******************************************************************************/
static void CPG_Init(void);
static void CS0_PORTInit(void);
/******************************************************************************
* Function Name: PeripheralBasicInit
* Description :
* :
* :
* Arguments : none
* Return Value : none
******************************************************************************/
void Peripheral_BasicInit(void)
{
/* ==== Clock Pulse Generator (CPG) setting ====*/
CPG_Init();
/* ==== Port setting ==== */
CS0_PORTInit();
/* ==== Bus State Controller (BSC) setting ==== */
R_BSC_Init((uint8_t)(BSC_AREA_CS0 | BSC_AREA_CS1));
}
/******************************************************************************
* Function Name: CPG_Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
static void CPG_Init(void)
{
volatile uint32_t dummy_buf_32b;
volatile uint8_t dummy_buf_8b;
*(volatile uint32_t *)(0x3fffff80) = 0x00000001;
dummy_buf_32b = *(volatile uint32_t *)(0x3fffff80);
/* ==== CPG Settings ==== */
CPG.FRQCR.WORD = 0x1035u; /* PLL(x30), I:G:B:P1:P0 = 30:20:10:5:5/2 */
CPG.FRQCR2.WORD = 0x0001u; /* CKIO:Output at time usually, */
/* Output when bus right is opened, */
/* output at standby"L" */
/* Clockin = 13.33MHz, CKIO = 66.67MHz, */
/* I Clock = 400.00MHz, */
/* G Clock = 266.67MHz, */
/* B Clock = 133.33MHz, */
/* P1 Clock = 66.67MHz, */
/* P0 Clock = 33.33MHz */
/* ---- Writing to On-Chip Data-Retention RAM is enabled. ---- */
CPG.SYSCR3.BYTE = 0x0Fu;
dummy_buf_8b = CPG.SYSCR3.BYTE;
}
/******************************************************************************
* Function Name: CS0_PORTInit
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
static void CS0_PORTInit(void)
{
/* ==== BSC settings ==== */
/* ---- P9_1 : A25 ---- */
PORT9.PMCn.BIT.PMCn1 = 1;
PORT9.PFCAEn.BIT.PFCAEn1 = 0;
PORT9.PFCEn.BIT.PFCEn1 = 0;
PORT9.PFCn.BIT.PFCn1 = 0;
PORT9.PIPCn.BIT.PIPCn1 = 1;
/* ---- P9_0 : A24 ---- */
PORT9.PMCn.BIT.PMCn0 = 1;
PORT9.PFCAEn.BIT.PFCAEn0 = 0;
PORT9.PFCEn.BIT.PFCEn0 = 0;
PORT9.PFCn.BIT.PFCn0 = 0;
PORT9.PIPCn.BIT.PIPCn0 = 1;
/* ---- P8_15 : A23 ---- */
PORT8.PMCn.BIT.PMCn15 = 1;
PORT8.PFCAEn.BIT.PFCAEn15 = 0;
PORT8.PFCEn.BIT.PFCEn15 = 0;
PORT8.PFCn.BIT.PFCn15 = 0;
PORT8.PIPCn.BIT.PIPCn15 = 1;
/* ---- P8_14 : A22 ---- */
PORT8.PMCn.BIT.PMCn14 = 1;
PORT8.PFCAEn.BIT.PFCAEn14 = 0;
PORT8.PFCEn.BIT.PFCEn14 = 0;
PORT8.PFCn.BIT.PFCn14 = 0;
PORT8.PIPCn.BIT.PIPCn14 = 1;
/* ---- P8_13 : A21 ---- */
PORT8.PMCn.BIT.PMCn13 = 1;
PORT8.PFCAEn.BIT.PFCAEn13 = 0;
PORT8.PFCEn.BIT.PFCEn13 = 0;
PORT8.PFCn.BIT.PFCn13 = 0;
PORT8.PIPCn.BIT.PIPCn13 = 1;
/* ---- P7_6 : WE0# / DQMLL# ---- */
PORT7.PMCn.BIT.PMCn6 = 1;
PORT7.PFCAEn.BIT.PFCAEn6 = 0;
PORT7.PFCEn.BIT.PFCEn6 = 0;
PORT7.PFCn.BIT.PFCn6 = 0;
PORT7.PIPCn.BIT.PIPCn6 = 1;
/* ---- P7_8 : RD ---- */
PORT7.PMCn.BIT.PMCn8 = 1;
PORT7.PFCAEn.BIT.PFCAEn8 = 0;
PORT7.PFCEn.BIT.PFCEn8 = 0;
PORT7.PFCn.BIT.PFCn8 = 0;
PORT7.PIPCn.BIT.PIPCn8 = 1;
/* ---- P7_0 : CS0 ---- */
PORT7.PMCn.BIT.PMCn0 = 1;
PORT7.PFCAEn.BIT.PFCAEn0 = 0;
PORT7.PFCEn.BIT.PFCEn0 = 0;
PORT7.PFCn.BIT.PFCn0 = 0;
PORT7.PIPCn.BIT.PIPCn0 = 1;
/* ---- P3_7 : CS1 ---- */
PORT3.PMCn.BIT.PMCn7 = 1;
PORT3.PFCAEn.BIT.PFCAEn7 = 1;
PORT3.PFCEn.BIT.PFCEn7 = 1;
PORT3.PFCn.BIT.PFCn7 = 0;
PORT3.PIPCn.BIT.PIPCn7 = 1;
}
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/port_init.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : port_init.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Initialize peripheral function sample
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "devdrv_common.h" /* Common Driver Header */
#include "port_init.h"
#include "iodefine.h"
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_RESET"
#pragma arm section rodata = "CONST_RESET"
#pragma arm section rwdata = "DATA_RESET"
#pragma arm section zidata = "BSS_RESET"
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: PORT_Init
* Description :
* :
* :
* Arguments : none
* Return Value : none
******************************************************************************/
void PORT_Init(void)
{
/* ==== BSC settings ==== */
/* ---- P7_2 : RAS# ---- */
PORT7.PMCn.BIT.PMCn2 = 1;
PORT7.PFCAEn.BIT.PFCAEn2 = 0;
PORT7.PFCEn.BIT.PFCEn2 = 0;
PORT7.PFCn.BIT.PFCn2 = 0;
PORT7.PIPCn.BIT.PIPCn2 = 1;
/* ---- P7_3 : CAS# ---- */
PORT7.PMCn.BIT.PMCn3 = 1;
PORT7.PFCAEn.BIT.PFCAEn3 = 0;
PORT7.PFCEn.BIT.PFCEn3 = 0;
PORT7.PFCn.BIT.PFCn3 = 0;
PORT7.PIPCn.BIT.PIPCn3 = 1;
/* ---- P7_4 : CKE ---- */
PORT7.PMCn.BIT.PMCn4 = 1;
PORT7.PFCAEn.BIT.PFCAEn4 = 0;
PORT7.PFCEn.BIT.PFCEn4 = 0;
PORT7.PFCn.BIT.PFCn4 = 0;
PORT7.PIPCn.BIT.PIPCn4 = 1;
/* ---- P7_5 : RD/WR# ---- */
PORT7.PMCn.BIT.PMCn5 = 1;
PORT7.PFCAEn.BIT.PFCAEn5 = 0;
PORT7.PFCEn.BIT.PFCEn5 = 0;
PORT7.PFCn.BIT.PFCn5 = 0;
PORT7.PIPCn.BIT.PIPCn5 = 1;
/* ---- P7_7 : DQMLU# ---- */
PORT7.PMCn.BIT.PMCn7 = 1;
PORT7.PFCAEn.BIT.PFCAEn7 = 0;
PORT7.PFCEn.BIT.PFCEn7 = 0;
PORT7.PFCn.BIT.PFCn7 = 0;
PORT7.PIPCn.BIT.PIPCn7 = 1;
/* ---- P5_8 : CS2 ---- */
PORT5.PMCn.BIT.PMCn8 = 1;
PORT5.PFCAEn.BIT.PFCAEn8 = 1;
PORT5.PFCEn.BIT.PFCEn8 = 0;
PORT5.PFCn.BIT.PFCn8 = 1;
PORT5.PIPCn.BIT.PIPCn8 = 1;
/* ---- P7_1 : CS3 ---- */
PORT7.PMCn.BIT.PMCn1 = 1;
PORT7.PFCAEn.BIT.PFCAEn1 = 0;
PORT7.PFCEn.BIT.PFCEn1 = 0;
PORT7.PFCn.BIT.PFCn1 = 0;
PORT7.PIPCn.BIT.PIPCn1 = 1;
}
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/siochar.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : siochar.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Serial I/O character R/W (SCIF 2-ch process)
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_scif_uart.h" /* UART Driver header */
#include "sio_char.h"
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: IoInitScif2
* Description : This function initializes SCIF channel 2 as UART mode.
* : The transmit and the receive of SCIF channel 2 are enabled.
* Arguments : none
* Return Value : none
******************************************************************************/
void IoInitScif2(void)
{
/* P1=66.67MHz CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps */
R_SCIF_UART_Init(DEVDRV_CH_2, SCIF_UART_MODE_RW, 0, 17);
/* === PORT ==== */
/* ---- P3_0 : TxD2 ---- */
PORT3.PMCn.BIT.PMCn0 = 1;
PORT3.PFCAEn.BIT.PFCAEn0 = 1;
PORT3.PFCEn.BIT.PFCEn0 = 0;
PORT3.PFCn.BIT.PFCn0 = 1;
PORT3.PIPCn.BIT.PIPCn0 = 1;
/* ---- P3_2 : RxD2 ---- */
PORT3.PMCn.BIT.PMCn2 = 1;
PORT3.PFCAEn.BIT.PFCAEn2 = 0;
PORT3.PFCEn.BIT.PFCEn2 = 1;
PORT3.PFCn.BIT.PFCn2 = 1;
PORT3.PIPCn.BIT.PIPCn2 = 1;
/* ---- Serial control register (SCSCRi) setting ---- */
SCIF2.SCSCR.WORD = 0x0030;
/* SCIF2 transmitting and receiving operations are enabled */
}
/******************************************************************************
* Function Name: IoGetchar
* Description : One character is received from SCIF2, and it's data is returned.
* : This function keeps waiting until it can obtain the receiving data.
* Arguments : none
* Return Value : Character to receive (Byte).
******************************************************************************/
char_t IoGetchar(void)
{
char_t data;
/* Confirming receive error(ER,DR,BRK) */
if (SCIF2.SCFSR.WORD & 0x09C)
{
/* Detect receive error */
SCIF2.SCSCR.BIT.RE = 0; /* Disable reception */
SCIF2.SCFCR.BIT.RFRST = 1; /* Reset receiving FIFO */
SCIF2.SCFCR.BIT.RFRST = 0; /* Clearing FIFO reception reset */
SCIF2.SCFSR.WORD &= ~0x9C; /* Error bit clear */
SCIF2.SCSCR.BIT.RE = 1; /* Enable reception */
return 0;
}
/* Is there receive FIFO data? */
while (0 == SCIF2.SCFSR.BIT.RDF)
{
/* WAIT */
}
/* Read receive data */
data = SCIF2.SCFRDR.BYTE;
/* Clear RDF */
SCIF2.SCFSR.BIT.RDF = 0;
/* Is it overflowed? */
if (1 == SCIF2.SCLSR.BIT.ORER)
{
SCIF2.SCLSR.BIT.ORER = 0; /* ORER clear */
}
return data;
}
/******************************************************************************
* Function Name: IoPutchar
* Description : Character "buffer" is output to SCIF2.
* : This function keeps waiting until it becomes the transmission
* : enabled state.
* Arguments : char_t buffer : character to output
* Return Value : None
******************************************************************************/
void IoPutchar(char_t buffer)
{
/* Check if it is possible to transmit (TDFE flag) */
while (0 == SCIF2.SCFSR.BIT.TDFE)
{
/* Wait */
}
/* Write the receiving data in TDR */
SCIF2.SCFTDR.BYTE = buffer;
/* Clear TDRE and TEND flag */
SCIF2.SCFSR.WORD &= ~0x0060;
}
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/stb_init.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : stb_init.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Initialize peripheral function sample
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "devdrv_common.h" /* Common Driver Header */
#include "stb_init.h"
#include "iodefine.h"
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_RESET"
#pragma arm section rodata = "CONST_RESET"
#pragma arm section rwdata = "DATA_RESET"
#pragma arm section zidata = "BSS_RESET"
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: StbInit
* Description :
* :
* Arguments : none
* Return Value : none
******************************************************************************/
void STB_Init(void)
{
volatile uint8_t dummy_buf;
/* ---- The clock of all modules is permitted. ---- */
CPG.STBCR2.BYTE = 0x6Au; /* Port level is keep in standby mode, [1], [1], [0], */
/* [1], [0], [1], CoreSight */
dummy_buf = CPG.STBCR2.BYTE; /* (Dummy read) */
CPG.STBCR3.BYTE = 0x00u; /* IEBus, IrDA, LIN0, LIN1, MTU2, RSCAN2, [0], PWM */
dummy_buf = CPG.STBCR3.BYTE; /* (Dummy read) */
CPG.STBCR4.BYTE = 0x00u; /* SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 */
dummy_buf = CPG.STBCR4.BYTE; /* (Dummy read) */
CPG.STBCR5.BYTE = 0x00u; /* SCIM0, SCIM1, SDG0, SDG1, SDG2, SDG3, OSTM0, OSTM1 */
dummy_buf = CPG.STBCR5.BYTE; /* (Dummy read) */
CPG.STBCR6.BYTE = 0x00u; /* A/D, CEU, DISCOM0, DISCOM1, DRC0, DRC1, JCU, RTClock */
dummy_buf = CPG.STBCR6.BYTE; /* (Dummy read) */
CPG.STBCR7.BYTE = 0x24u; /* DVDEC0, DVDEC1, [1], ETHER, FLCTL, [1], USB0, USB1 */
dummy_buf = CPG.STBCR7.BYTE; /* (Dummy read) */
CPG.STBCR8.BYTE = 0x05u; /* IMR-LS20, IMR-LS21, IMR-LSD, MMCIF, MOST50, [1], SCUX, [1] */
dummy_buf = CPG.STBCR8.BYTE; /* (Dummy read) */
CPG.STBCR9.BYTE = 0x00u; /* I2C0, I2C1, I2C2, I2C3, SPIBSC0, SPIBSC1, VDC50, VDC51 */
dummy_buf = CPG.STBCR9.BYTE; /* (Dummy read) */
CPG.STBCR10.BYTE = 0x00u; /* RSPI0, RSPI1, RSPI2, RSPI3, RSPI4, CD-ROMDEC, RSPDIF, RGPVG */
dummy_buf = CPG.STBCR10.BYTE; /* (Dummy read) */
CPG.STBCR11.BYTE = 0xC0u; /* [1], [1], SSIF0, SSIF1, SSIF2, SSIF3, SSIF4, SSIF5 */
dummy_buf = CPG.STBCR11.BYTE; /* (Dummy read) */
CPG.STBCR12.BYTE = 0xF0u; /* [1], [1], [1], [1], SDHI00, SDHI01, SDHI10, SDHI11 */
dummy_buf = CPG.STBCR12.BYTE; /* (Dummy read) */
}
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/ttb_init.s
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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : ttb_init.s
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.8
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program - TTB initialize
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
; ---- Parameter setting to level1 descriptor (bits 19:0) ----
; setting for Strongly-ordered memory
TTB_PARA_STRGLY EQU 2_00000000000000000000110111100010
; setting for Outer and inner not cache normal memory
TTB_PARA_NORMAL_NOT_CACHE EQU 2_00000000000000000001110111100010
; setting for Outer and inner write back, write allocate normal memory (Cacheable)
TTB_PARA_NORMAL_CACHE EQU 2_00000000000000000001110111101110
; setting for Outer and inner write back, write allocate normal memory (Cacheable)
;TTB_PARA_NORMAL_CACHE EQU 2_00000000000000000101110111100110
; ---- Memory area size (MB) ----
M_SIZE_NOR EQU 128 ; [Area00] CS0, CS1 area (for NOR flash)
M_SIZE_SDRAM EQU 128 ; [Area01] CS2, CS3 area (for SDRAM)
M_SIZE_CS45 EQU 128 ; [Area02] CS4, CS5 area
M_SIZE_SPI EQU 128 ; [Area03] SPI, SP2 area (for Serial flash)
M_SIZE_RAM EQU 10 ; [Area04] Internal RAM
M_SIZE_IO_1 EQU 502 ; [Area05] I/O area 1
M_SIZE_NOR_M EQU 128 ; [Area06] CS0, CS1 area (for NOR flash) (mirror)
M_SIZE_SDRAM_M EQU 128 ; [Area07] CS2, CS3 area (for SDRAM) (mirror)
M_SIZE_CS45_M EQU 128 ; [Area08] CS4, CS5 area (mirror)
M_SIZE_SPI_M EQU 128 ; [Area09] SPI, SP2 area (for Serial flash) (mirror)
M_SIZE_RAM_M EQU 10 ; [Area10] Internal RAM (mirror)
M_SIZE_IO_2 EQU 2550 ; [Area11] I/O area 2
;==================================================================
; This code provides basic global enable for Cortex-A9 cache.
; It also enables branch prediction
; This code must be run from a privileged mode
;==================================================================
AREA INIT_TTB, CODE, READONLY
IMPORT ||Image$$TTB$$ZI$$Base|| ;;; From scatter file
EXPORT init_TTB
init_TTB FUNCTION
;===================================================================
; Cortex-A9 MMU Configuration
; Set translation table base
;===================================================================
;;; Cortex-A9 supports two translation tables
;;; Configure translation table base (TTB) control register cp15,c2
;;; to a value of all zeros, indicates we are using TTB register 0.
MOV r0,#0x0
MCR p15, 0, r0, c2, c0, 2 ;;; TTBCR
;;; write the address of our page table base to TTB register 0
LDR r0,=||Image$$TTB$$ZI$$Base||
MOV r1, #0x08 ;;; RGN=b01 (outer cacheable write-back cached, write allocate)
;;; S=0 (translation table walk to non-shared memory)
ORR r1,r1,#0x40 ;;; IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate)
ORR r0,r0,r1
MCR p15, 0, r0, c2, c0, 0 ;;; TTBR0
;===================================================================
; PAGE TABLE generation
; Generate the page tables
; Build a flat translation table for the whole address space.
; ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx
; 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0
; |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0|
;
; Bits[31:20] - Top 12 bits of VA is pointer into table
; nG[17]=0 - Non global, enables matching against ASID in the TLB when set.
; S[16]=0 - Indicates normal memory is shared when set.
; AP2[15]=0
; AP[11:10]=11 - Configure for full read/write access in all modes
; TEX[14:12]=000
; CB[3:2]= 00 - Set attributes to Strongly-ordered memory.
; (except for the descriptor where code segment is based, see below)
; IMPP[9]=0 - Ignored
; Domain[5:8]=1111 - Set all pages to use domain 15
; XN[4]=0 - Execute never disabled
; Bits[1:0]=10 - Indicate entry is a 1MB section
;===================================================================
LDR r0,=||Image$$TTB$$ZI$$Base||
LDR r1,=0xFFF
LDR r2,=11
LDR r3,=0
LDR r4,=0
LDR r5,=0
;;; r0 contains the address of the translation table base
;;; r1 is loop counter
;;; r2 is target area counter (Initialize value = Last area No.)
;;; r3 is loop counter by area
;;; use loop counter to create 4096 individual table entries.
;;; this writes from address 'Image$$TTB$$ZI$$Base' +
;;; offset 0x3FFC down to offset 0x0 in word steps (4 bytes)
set_mem_accsess
CMP r2, #11
BEQ setting_area11
CMP r2, #10
BEQ setting_area10
CMP r2, #9
BEQ setting_area9
CMP r2, #8
BEQ setting_area8
CMP r2, #7
BEQ setting_area7
CMP r2, #6
BEQ setting_area6
CMP r2, #5
BEQ setting_area5
CMP r2, #4
BEQ setting_area4
CMP r2, #3
BEQ setting_area3
CMP r2, #2
BEQ setting_area2
CMP r2, #1
BEQ setting_area1
CMP r2, #0
BEQ setting_area0
setting_area11 ;;; [area11] I/O area 2
LDR r3, =M_SIZE_IO_2
LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
BAL init_counter
setting_area10 ;;; [area10] Internal RAM (mirror)
LDR r3, =M_SIZE_RAM_M
LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
BAL init_counter
setting_area9 ;;; [area09] SPI, SP2 area (for Serial flash) (mirror)
LDR r3, =M_SIZE_SPI_M
LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
BAL init_counter
setting_area8 ;;; [area08] CS4, CS5 area (mirror)
LDR r3, =M_SIZE_CS45_M
LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
BAL init_counter
setting_area7 ;;; [area07] CS2, CS3 area (for SDRAM) (mirror)
LDR r3, =M_SIZE_SDRAM_M
LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
BAL init_counter
setting_area6 ;;; [area06] CS0, CS1 area (for NOR flash) (mirror)
LDR r3, =M_SIZE_NOR_M
LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
BAL init_counter
setting_area5 ;;; [area05] I/O area 1
LDR r3, =M_SIZE_IO_1
LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
BAL init_counter
setting_area4 ;;; [area04] Internal RAM
LDR r3, =M_SIZE_RAM
LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
BAL init_counter
setting_area3 ;;; [area03] SPI, SP2 area (for Serial flash)
LDR r3, =M_SIZE_SPI
LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
BAL init_counter
setting_area2 ;;; [area02] CS4, CS5 area
LDR r3, =M_SIZE_CS45
LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
BAL init_counter
setting_area1 ;;; [area01] CS2, CS3 area (for SDRAM)
LDR r3, =M_SIZE_SDRAM
LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
BAL init_counter
setting_area0 ;;; [area00] CS0, CS1 area (for NOR flash)
LDR r3, =M_SIZE_NOR
LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
BAL init_counter
init_counter
SUBS r3, r3, #1 ;;; memory size -> loop counter value
write_ttb
ORR r5, r4, r1, LSL#20 ;;; R5 now contains full level1 descriptor to write
STR r5, [r0, r1, LSL#2] ;;; Str table entry at TTB base + loopcount*4
SUB r1, r1, #1 ;;; Decrement loop counter
SUBS r3, r3, #1 ;;; Decrement loop counter by area
BPL write_ttb
SUBS r2, r2, #1 ;;; target area counter
BPL set_mem_accsess ;;; To the next area
BX lr
ENDFUNC
END

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/l1_cache_init.s
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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : l1_cache_init.s
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.8
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program vecotr.s
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
;==================================================================
; This code provides basic global enable for Cortex-A9 cache.
; It also enables branch prediction
; This code must be run from a privileged mode
;==================================================================
AREA INITCA9CACHE, CODE, READONLY
EXPORT L1CacheInit
L1CacheInit FUNCTION
;==================================================================
; Enable caches
; Caches are controlled by the System Control Register:
;==================================================================
;;; I-cache is controlled by bit 12
;;; D-cache is controlled by bit 2
MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 register 1
ORR r0, r0, #(0x1 << 12) ;;; Enable I Cache
ORR r0, r0, #(0x1 << 2) ;;; Enable D Cache
MCR p15, 0, r0, c1, c0, 0 ;;; Write CP15 register 1
;==================================================================
; Enable Program Flow Prediction
;
; Branch prediction is controlled by the System Control Register:
; Set Bit 11 to enable branch prediction and return
;==================================================================
;;; Turning on branch prediction requires a general enable
;;; CP15, c1. Control Register
;;; Bit 11 [Z] bit Program flow prediction:
;;; 0 = Program flow prediction disabled
;;; 1 = Program flow prediction enabled.
MRC p15, 0, r0, c1, c0, 0 ;;; Read System Control Register
ORR r0, r0, #(0x1 << 11)
MCR p15, 0, r0, c1, c0, 0 ;;; Write System Control Register
;==================================================================
; Enable D-side prefetch
;==================================================================
;;; Bit 2 [DP] Dside prefetch:
;;; 0 = Dside prefetch disabled
;;; 1 = Dside prefetch enabled.
MRC p15, 0, r0, c1, c0, 1 ;;; Read Auxiliary Control Register
ORR r0, r0, #(0x1 << 2) ;;; Enable Dside prefetch
MCR p15, 0, r0, c1, c0, 1 ;;; Write Auxiliary Control Register
BX lr
ENDFUNC
END

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/resetprg.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : resetprg.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Sub Main
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "devdrv_common.h" /* Common Driver Header */
#include "devdrv_intc.h" /* INTC Driver Header */
#include "resetprg.h"
#include "sio_char.h"
#include "stb_init.h"
#include "port_init.h"
#pragma arm section code = "CODE_RESET"
#pragma arm section rodata = "CONST_RESET"
#pragma arm section rwdata = "DATA_RESET"
#pragma arm section zidata = "BSS_RESET"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
extern void VbarInit(void);
extern void L1CacheInit(void);
extern int32_t $Super$$main(void);
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/*******************************************************************************
* Function Name: $Sub$$main
* Description :
* Arguments : none
* Return Value : none
*******************************************************************************/
void $Sub$$main(void)
{
STB_Init();
/* ==== PORT setting ==== */
PORT_Init();
/* ==== BSC setting ==== */
R_BSC_Init((uint8_t)(BSC_AREA_CS2 | BSC_AREA_CS3));
/* ==== INTC setting ==== */
R_INTC_Init();
/* ==== Cache setting ==== */
// io_init_cache();
/* ==== Writeback Cache ==== */
// io_cache_writeback();
L1CacheInit();
/* ==== Vector base address setting ==== */
VbarInit();
__enable_irq();
__enable_fiq();
/* ==== Function call of main function ==== */
$Super$$main();
}
/* END of File */

67
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/vbar_init.s
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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : vbar_init.s
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.8
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
;==================================================================
; This code provides basic global enable for Cortex-A9 cache.
; It also enables branch prediction
; This code must be run from a privileged mode
;==================================================================
AREA INIT_VBAR, CODE, READONLY
IMPORT ||Image$$VECTOR_MIRROR_TABLE$$Base||
; IMPORT ||Image$$VECTOR_TABLE$$Base||
EXPORT VbarInit
VbarInit FUNCTION
;===================================================================
; Set Vector Base Address Register (VBAR) to point to this application's vector table
;===================================================================
LDR r0, =||Image$$VECTOR_MIRROR_TABLE$$Base||
; LDR r0, =||Image$$VECTOR_TABLE$$Base||
MCR p15, 0, r0, c12, c0, 0
BX lr
ENDFUNC
END

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/common_driver/bsc.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc.c
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - BSC initialize
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_common.h" /* Common Driver Header */
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_RESET"
#pragma arm section rodata = "CONST_RESET"
#pragma arm section rwdata = "DATA_RESET"
#pragma arm section zidata = "BSS_RESET"
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: R_BSC_Init
* Description :
* Arguments : uint8 area
* : B'xxxxxxxx
* : |||||||+--- [0] CS0
* : ||||||+---- [1] CS1
* : |||||+----- [2] CS2
* : ||||+------ [3] CS3
* : |||+------- [4] CS4
* : ||+-------- [5] CS5
* : ++--------- [6-7] n/a
* Return Value : none
******************************************************************************/
void R_BSC_Init(uint8_t area)
{
/* ==== BSC initialize ==== */
if ((area & BSC_AREA_CS0) != 0) /* CS0 */
{
Userdef_BSC_CS0Init();
}
if ((area & BSC_AREA_CS1) != 0) /* CS1 */
{
Userdef_BSC_CS1Init();
}
if ((area & BSC_AREA_CS2) != 0) /* CS2 */
{
Userdef_BSC_CS2Init();
}
if ((area & BSC_AREA_CS3) != 0) /* CS3 */
{
Userdef_BSC_CS3Init();
}
if ((area & BSC_AREA_CS4) != 0) /* CS4 */
{
Userdef_BSC_CS4Init();
}
if ((area & BSC_AREA_CS5) != 0) /* CS5 */
{
Userdef_BSC_CS5Init();
}
}
/* End of File */

240
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/userdef/bsc_userdef.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_userdef.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Common driver (User define function)
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_common.h" /* Common Driver Header */
#include "iodefine.h"
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_RESET"
#pragma arm section rodata = "CONST_RESET"
#pragma arm section rwdata = "DATA_RESET"
#pragma arm section zidata = "BSS_RESET"
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/* The address when writing in a SDRAM mode register */
#define SDRAM_MODE_CS2 (*(volatile uint16_t *)(0x3FFFD040))
#define SDRAM_MODE_CS3 (*(volatile uint16_t *)(0x3FFFE040))
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: Userdef_BSC_CS0Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_BSC_CS0Init(void)
{
/* ---- CS0BCR settings ---- */
BSC.CS0BCR.LONG = 0x10000C00ul;
/* Idle Cycles between Write-read Cycles */
/* and Write-write Cycles : 1 idle cycle */
/* Data Bus Size: 16-bit */
/* ---- CS0WCR settings ---- */
BSC.CS0WCR.NORMAL.LONG = 0x00000B40ul;
/* Number of Delay Cycles from Address, */
/* CS0# Assertion to RD#,WEn Assertion */
/* : 1.5 cycles */
/* Number of Access Wait Cycles: 6 cycles */
/* Delay Cycles from RD,WEn# negation to */
/* Address,CSn# negation: 0.5 cycles */
}
/******************************************************************************
* Function Name: Userdef_BSC_CS1Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_BSC_CS1Init(void)
{
/* ---- CS1BCR settings ---- */
BSC.CS1BCR.LONG = 0x10000C00ul;
/* Idle Cycles between Write-read Cycles */
/* and Write-write Cycles : 1 idle cycle */
/* Data Bus Size: 16-bit */
/* ---- CS1WCR settings ---- */
BSC.CS1WCR.LONG = 0x00000B40ul;
/* Number of Delay Cycles from Address, */
/* CS0# Assertion to RD#,WEn Assertion */
/* : 1.5 cycles */
/* Number of Access Wait Cycles: 6 cycles */
/* Delay Cycles from RD,WEn# negation to */
/* Address,CSn# negation: 0.5 cycles */
}
/******************************************************************************
* Function Name: Userdef_BSC_CS2Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_BSC_CS2Init(void)
{
/* ==== CS2BCR settings ==== */
BSC.CS2BCR.LONG = 0x00004C00ul;
/* Idle Cycles between Write-read Cycles */
/* and Write-write Cycles : 0 idle cycles */
/* Memory type :SDRAM */
/* Data Bus Size : 16-bit */
/* ==== CS2WCR settings ==== */
BSC.CS2WCR.SDRAM.LONG = 0x00000480ul;
/* CAS latency for Area 2 : 2 cycles */
/* ==== Written in SDRAM Mode Register ==== */
SDRAM_MODE_CS2 = 0;
/* The writing data is arbitrary */
/* SDRAM mode register setting CS2 space */
/* Burst read (burst length 1)./Burst write */
}
/******************************************************************************
* Function Name: Userdef_BSC_CS3Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_BSC_CS3Init(void)
{
volatile int32_t cnt;
cnt = 150;
while (cnt-- > 0)
{
/* wait */
}
/* ==== CS3BCR settings ==== */
BSC.CS3BCR.LONG = 0x00004C00ul;
/* Idle Cycles between Write-read Cycles */
/* and Write-write Cycles : 0 idle cycles */
/* Memory type :SDRAM */
/* Data Bus Size : 16-bit */
/* ==== CS3WCR settings ==== */
BSC.CS3WCR.SDRAM.LONG = 0x00002492ul;
/* Precharge completion wait cycles: 1 cycle */
/* Wait cycles between ACTV command */
/* and READ(A)/WRITE(A) command : 1 cycles */
/* CAS latency for Area 3 : 2 cycles */
/* Auto-precharge startup wait cycles : 2 cycles */
/* Idle cycles from REF command/self-refresh */
/* Release to ACTV/REF/MRS command : 5 cycles */
/* ==== SDCR settings ==== */
BSC.SDCR.LONG = 0x00120812ul;
/* Row address for Area 2 : 13-bit */
/* Column Address for Area 2 : 10-bit */
/* Refresh Control :Refresh */
/* RMODE :Auto-refresh is performed */
/* BACTV :Auto-precharge mode */
/* Row address for Area 3 : 13-bit */
/* Column Address for Area 3 : 10-bit */
/* ==== RTCOR settings ==== */
BSC.RTCOR.LONG = 0xA55A0020ul;
/* 7.813usec /240nsec */
/* = 32(0x20)cycles per refresh */
/* ==== RTCSR settings ==== */
BSC.RTCSR.LONG = 0xA55A0010ul;
/* Initialization sequence start */
/* Clock select B-phy/16 */
/* Refresh count :Once */
/* ==== Written in SDRAM Mode Register ==== */
SDRAM_MODE_CS3 = 0;
/* The writing data is arbitrary */
/* SDRAM mode register setting CS3 space */
/* Burst read (burst length 1)./Burst write */
}
/******************************************************************************
* Function Name: Userdef_BSC_CS4Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_BSC_CS4Init(void)
{
}
/******************************************************************************
* Function Name: Userdef_BSC_CS5Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_BSC_CS5Init(void)
{
}
/* End of File */

298
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : intc.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - Interrupt process
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_intc.h" /* INTC Driver Header */
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define INTC_ICDISR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDISR */
#define INTC_ICDICFR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 16) + 1) /* ICDICFR */
#define INTC_ICDIPR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 4) + 1) /* ICDIPR */
#define INTC_ICDIPTR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 4) + 1) /* ICDIPTR */
#define INTC_ICDISER_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDISER */
#define INTC_ICDICER_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDICER */
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/* ==== Global variable ==== */
static uint32_t intc_icdicfrn_table[] =
{
0xAAAAAAAA, /* ICDICFR0 : 15 - 0 */
0x00000055, /* ICDICFR1 : 19 - 16 */
0xFFFD5555, /* ICDICFR2 : 47 - 32 */
0x555FFFFF, /* ICDICFR3 : 63 - 48 */
0x55555555, /* ICDICFR4 : 79 - 64 */
0x55555555, /* ICDICFR5 : 95 - 80 */
0x55555555, /* ICDICFR6 : 111 - 96 */
0x55555555, /* ICDICFR7 : 127 - 112 */
0x5555F555, /* ICDICFR8 : 143 - 128 */
0x55555555, /* ICDICFR9 : 159 - 144 */
0x55555555, /* ICDICFR10 : 175 - 160 */
0xF5555555, /* ICDICFR11 : 191 - 176 */
0xF555F555, /* ICDICFR12 : 207 - 192 */
0x5555F555, /* ICDICFR13 : 223 - 208 */
0x55555555, /* ICDICFR14 : 239 - 224 */
0x55555555, /* ICDICFR15 : 255 - 240 */
0x55555555, /* ICDICFR16 : 271 - 256 */
0xFD555555, /* ICDICFR17 : 287 - 272 */
0x55555557, /* ICDICFR18 : 303 - 288 */
0x55555555, /* ICDICFR19 : 319 - 304 */
0x55555555, /* ICDICFR20 : 335 - 320 */
0x5F555555, /* ICDICFR21 : 351 - 336 */
0xFD55555F, /* ICDICFR22 : 367 - 352 */
0x55555557, /* ICDICFR23 : 383 - 368 */
0x55555555, /* ICDICFR24 : 399 - 384 */
0x55555555, /* ICDICFR25 : 415 - 400 */
0x55555555, /* ICDICFR26 : 431 - 416 */
0x55555555, /* ICDICFR27 : 447 - 432 */
0x55555555, /* ICDICFR28 : 463 - 448 */
0x55555555, /* ICDICFR29 : 479 - 464 */
0x55555555, /* ICDICFR30 : 495 - 480 */
0x55555555, /* ICDICFR31 : 511 - 496 */
0x55555555, /* ICDICFR32 : 527 - 512 */
0x55555555, /* ICDICFR33 : 543 - 528 */
0x55555555, /* ICDICFR34 : 559 - 544 */
0x55555555, /* ICDICFR35 : 575 - 560 */
0x00155555 /* ICDICFR36 : 586 - 576 */
};
/******************************************************************************
* Function Name: R_INTC_RegistIntFunc
* Description :
* Arguments : uint16_t int_id
* : void (* func)(uint32_t)
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense))
{
if (int_id >= INTC_ID_TOTAL)
{
return DEVDRV_ERROR;
}
Userdef_INTC_RegistIntFunc(int_id, func);
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: R_INTC_Init
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void R_INTC_Init(void)
{
uint16_t offset;
volatile uint32_t * addr;
for (offset = 0; offset < INTC_ICDICFR_REG_TOTAL; offset++)
{
INTC.ICDICFR.LONG[offset] = intc_icdicfrn_table[offset];
}
addr = (volatile uint32_t *)&INTC.ICDIPR0.LONG;
for (offset = 0; offset < INTC_ICDIPR_REG_TOTAL; offset++)
{
*(addr + offset) = 0xF8F8F8F8;
}
addr = (volatile uint32_t *)&INTC.ICDIPTR0.LONG;
for (offset = 8; offset < INTC_ICDIPTR_REG_TOTAL; offset++)
{
*(addr + offset) = 0x01010101;
}
for (offset = 0; offset < INTC_ICDICER_REG_TOTAL; offset++)
{
INTC.ICDICER.LONG[offset] = 0xFFFFFFFF;
}
R_INTC_SetMaskLevel(31);
INTC.ICCBPR.BIT.Binarypoint = 0;
INTC.ICCICR.LONG = 3;
/* Distributor Control Register */
INTC.ICDDCR.BIT.Enable = 1;
}
/******************************************************************************
* Function Name: R_INTC_Enable
* Description :
* Arguments : uint16_t int_id
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_INTC_Enable(uint16_t int_id)
{
uint32_t reg_value;
uint32_t mask;
if (int_id >= INTC_ID_TOTAL)
{
return DEVDRV_ERROR;
}
mask = 1;
mask = mask << (int_id % 32);
reg_value = INTC.ICDISER.LONG[int_id / 32];
reg_value |= mask;
INTC.ICDISER.LONG[int_id / 32] = reg_value;
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: R_INTC_Disable
* Description :
* Arguments : uint16_t int_id
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_INTC_Disable(uint16_t int_id)
{
uint32_t reg_value;
uint32_t mask;
if (int_id >= INTC_ID_TOTAL)
{
return DEVDRV_ERROR;
}
mask = 1;
mask = mask << (int_id % 32);
reg_value = INTC.ICDICER.LONG[int_id / 32];
reg_value |= mask;
INTC.ICDICER.LONG[int_id / 32] = reg_value;
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: R_INTC_SetPriority
* Description :
* Arguments : uint16_t int_id
* : uint8_t priority
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_INTC_SetPriority(uint16_t int_id, uint8_t priority)
{
uint32_t icdipr;
uint32_t mask;
volatile uint32_t * addr;
if ((int_id >= INTC_ID_TOTAL) || priority >= 32)
{
return DEVDRV_ERROR;
}
priority = priority << 3;
addr = (volatile uint32_t *)&INTC.ICDIPR0.LONG;
icdipr = *(addr + (int_id / 4));
mask = (uint32_t)0x000000FF;
mask = mask << ((int_id % 4) * 8);
icdipr &= ~mask;
mask = (uint32_t)priority;
mask = mask << ((int_id % 4) * 8);
icdipr |= mask;
*(addr + (int_id / 4)) = icdipr;
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: R_INTC_SetMaskLevel
* Description :
* Arguments : uint8_t mask_level
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_INTC_SetMaskLevel(uint8_t mask_level)
{
if (mask_level >= 32)
{
return DEVDRV_ERROR;
}
mask_level = mask_level << 3;
INTC.ICCPMR.BIT.Priority = mask_level;
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: R_INTC_GetMaskLevel
* Description :
* Arguments : uint8_t * mask_level
* Return Value : none
******************************************************************************/
void R_INTC_GetMaskLevel(uint8_t * mask_level)
{
*mask_level = INTC.ICCPMR.BIT.Priority;
*mask_level = *mask_level >> 3;
}
/* END of File */

88
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc_handler.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : intc_handler.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - Handler process
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "FreeRTOS.h"
#include <stdio.h>
#include "r_typedefs.h"
#include "devdrv_intc.h" /* INTC Driver Header */
#include "iodefine.h"
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_HANDLER"
#pragma arm section rodata = "CONST_HANDLER"
#pragma arm section rwdata = "DATA_HANDLER"
#pragma arm section zidata = "BSS_HANDLER"
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/* ==== Prototype declaration ==== */
__irq void FiqHandler_Interrupt(void);
/******************************************************************************
Private global variables and functions
******************************************************************************/
/*******************************************************************************
* Function Name: FiqHandler_Interrupt
* Description :
* Arguments : none
* Return Value : none
*******************************************************************************/
__irq void FiqHandler_Interrupt(void)
{
Userdef_FIQ_HandlerExe();
}
/* END of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/userdef/intc_userdef.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : intc_userdef.c
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - Interrupt func table
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "devdrv_intc.h" /* INTC Driver Header */
#include "iodefine.h"
/* Do not include the following pragmas when compiling with IAR. */
#ifndef __ICCARM__
#pragma arm section code = "CODE_HANDLER_JMPTBL"
#pragma arm section rodata = "CONST_HANDLER_JMPTBL"
#pragma arm section rwdata = "DATA_HANDLER_JMPTBL"
#pragma arm section zidata = "BSS_HANDLER_JMPTBL"
#else
/* IAR requires intrinsics.h for the __enable_irq() function. */
#include <intrinsics.h>
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/* ==== Prototype function ==== */
static void Userdef_INTC_Dummy_Interrupt(uint32_t int_sense);
/* ==== Global variable ==== */
static void (* intc_func_table[INTC_ID_TOTAL])(uint32_t int_sense) =
{
Userdef_INTC_Dummy_Interrupt, /* 0 : SW0 */
Userdef_INTC_Dummy_Interrupt, /* 1 : SW1 */
Userdef_INTC_Dummy_Interrupt, /* 2 : SW2 */
Userdef_INTC_Dummy_Interrupt, /* 3 : SW3 */
Userdef_INTC_Dummy_Interrupt, /* 4 : SW4 */
Userdef_INTC_Dummy_Interrupt, /* 5 : SW5 */
Userdef_INTC_Dummy_Interrupt, /* 6 : SW6 */
Userdef_INTC_Dummy_Interrupt, /* 7 : SW7 */
Userdef_INTC_Dummy_Interrupt, /* 8 : SW8 */
Userdef_INTC_Dummy_Interrupt, /* 9 : SW9 */
Userdef_INTC_Dummy_Interrupt, /* 10 : SW10 */
Userdef_INTC_Dummy_Interrupt, /* 11 : SW11 */
Userdef_INTC_Dummy_Interrupt, /* 12 : SW12 */
Userdef_INTC_Dummy_Interrupt, /* 13 : SW13 */
Userdef_INTC_Dummy_Interrupt, /* 14 : SW14 */
Userdef_INTC_Dummy_Interrupt, /* 15 : SW15 */
Userdef_INTC_Dummy_Interrupt, /* 16 : PMUIRQ0 */
Userdef_INTC_Dummy_Interrupt, /* 17 : COMMRX0 */
Userdef_INTC_Dummy_Interrupt, /* 18 : COMMTX0 */
Userdef_INTC_Dummy_Interrupt, /* 19 : CTIIRQ0 */
Userdef_INTC_Dummy_Interrupt, /* 20 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 21 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 22 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 23 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 24 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 25 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 26 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 27 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 28 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 29 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 30 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 31 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 32 : IRQ0 */
Userdef_INTC_Dummy_Interrupt, /* 33 : IRQ1 */
Userdef_INTC_Dummy_Interrupt, /* 34 : IRQ2 */
Userdef_INTC_Dummy_Interrupt, /* 35 : IRQ3 */
Userdef_INTC_Dummy_Interrupt, /* 36 : IRQ4 */
Userdef_INTC_Dummy_Interrupt, /* 37 : IRQ5 */
Userdef_INTC_Dummy_Interrupt, /* 38 : IRQ6 */
Userdef_INTC_Dummy_Interrupt, /* 39 : IRQ7 */
Userdef_INTC_Dummy_Interrupt, /* 40 : PL310ERR */
Userdef_INTC_Dummy_Interrupt, /* 41 : DMAINT0 */
Userdef_INTC_Dummy_Interrupt, /* 42 : DMAINT1 */
Userdef_INTC_Dummy_Interrupt, /* 43 : DMAINT2 */
Userdef_INTC_Dummy_Interrupt, /* 44 : DMAINT3 */
Userdef_INTC_Dummy_Interrupt, /* 45 : DMAINT4 */
Userdef_INTC_Dummy_Interrupt, /* 46 : DMAINT5 */
Userdef_INTC_Dummy_Interrupt, /* 47 : DMAINT6 */
Userdef_INTC_Dummy_Interrupt, /* 48 : DMAINT7 */
Userdef_INTC_Dummy_Interrupt, /* 49 : DMAINT8 */
Userdef_INTC_Dummy_Interrupt, /* 50 : DMAINT9 */
Userdef_INTC_Dummy_Interrupt, /* 51 : DMAINT10 */
Userdef_INTC_Dummy_Interrupt, /* 52 : DMAINT11 */
Userdef_INTC_Dummy_Interrupt, /* 53 : DMAINT12 */
Userdef_INTC_Dummy_Interrupt, /* 54 : DMAINT13 */
Userdef_INTC_Dummy_Interrupt, /* 55 : DMAINT14 */
Userdef_INTC_Dummy_Interrupt, /* 56 : DMAINT15 */
Userdef_INTC_Dummy_Interrupt, /* 57 : DMAERR */
Userdef_INTC_Dummy_Interrupt, /* 58 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 59 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 60 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 61 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 62 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 63 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 64 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 65 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 66 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 67 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 68 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 69 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 70 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 71 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 72 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 73 : USBI0 */
Userdef_INTC_Dummy_Interrupt, /* 74 : USBI1 */
Userdef_INTC_Dummy_Interrupt, /* 75 : S0_VI_VSYNC0 */
Userdef_INTC_Dummy_Interrupt, /* 76 : S0_LO_VSYNC0 */
Userdef_INTC_Dummy_Interrupt, /* 77 : S0_VSYNCERR0 */
Userdef_INTC_Dummy_Interrupt, /* 78 : GR3_VLINE0 */
Userdef_INTC_Dummy_Interrupt, /* 79 : S0_VFIELD0 */
Userdef_INTC_Dummy_Interrupt, /* 80 : IV1_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 81 : IV3_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 82 : IV5_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 83 : IV6_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 84 : S0_WLINE0 */
Userdef_INTC_Dummy_Interrupt, /* 85 : S1_VI_VSYNC0 */
Userdef_INTC_Dummy_Interrupt, /* 86 : S1_LO_VSYNC0 */
Userdef_INTC_Dummy_Interrupt, /* 87 : S1_VSYNCERR0 */
Userdef_INTC_Dummy_Interrupt, /* 88 : S1_VFIELD0 */
Userdef_INTC_Dummy_Interrupt, /* 89 : IV2_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 90 : IV4_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 91 : S1_WLINE0 */
Userdef_INTC_Dummy_Interrupt, /* 92 : OIR_VI_VSYNC0 */
Userdef_INTC_Dummy_Interrupt, /* 93 : OIR_LO_VSYNC0 */
Userdef_INTC_Dummy_Interrupt, /* 94 : OIR_VSYNCERR0 */
Userdef_INTC_Dummy_Interrupt, /* 95 : OIR_VFIELD0 */
Userdef_INTC_Dummy_Interrupt, /* 96 : IV7_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 97 : IV8_VBUFERR0 */
Userdef_INTC_Dummy_Interrupt, /* 98 : OIR_WLINE0 */
Userdef_INTC_Dummy_Interrupt, /* 99 : S0_VI_VSYNC1 */
Userdef_INTC_Dummy_Interrupt, /* 100 : S0_LO_VSYNC1 */
Userdef_INTC_Dummy_Interrupt, /* 101 : S0_VSYNCERR1 */
Userdef_INTC_Dummy_Interrupt, /* 102 : GR3_VLINE1 */
Userdef_INTC_Dummy_Interrupt, /* 103 : S0_VFIELD1 */
Userdef_INTC_Dummy_Interrupt, /* 104 : IV1_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 105 : IV3_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 106 : IV5_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 107 : IV6_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 108 : S0_WLINE1 */
Userdef_INTC_Dummy_Interrupt, /* 109 : S1_VI_VSYNC1 */
Userdef_INTC_Dummy_Interrupt, /* 110 : S1_LO_VSYNC1 */
Userdef_INTC_Dummy_Interrupt, /* 111 : S1_VSYNCERR1 */
Userdef_INTC_Dummy_Interrupt, /* 112 : S1_VFIELD1 */
Userdef_INTC_Dummy_Interrupt, /* 113 : IV2_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 114 : IV4_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 115 : S1_WLINE1 */
Userdef_INTC_Dummy_Interrupt, /* 116 : OIR_VI_VSYNC1 */
Userdef_INTC_Dummy_Interrupt, /* 117 : OIR_LO_VSYNC1 */
Userdef_INTC_Dummy_Interrupt, /* 118 : OIR_VLINE1 */
Userdef_INTC_Dummy_Interrupt, /* 119 : OIR_VFIELD1 */
Userdef_INTC_Dummy_Interrupt, /* 120 : IV7_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 121 : IV8_VBUFERR1 */
Userdef_INTC_Dummy_Interrupt, /* 122 : OIR_WLINE1 */
Userdef_INTC_Dummy_Interrupt, /* 123 : IMRDI */
Userdef_INTC_Dummy_Interrupt, /* 124 : IMR2I0 */
Userdef_INTC_Dummy_Interrupt, /* 125 : IMR2I1 */
Userdef_INTC_Dummy_Interrupt, /* 126 : JEDI */
Userdef_INTC_Dummy_Interrupt, /* 127 : JDTI */
Userdef_INTC_Dummy_Interrupt, /* 128 : CMP0 */
Userdef_INTC_Dummy_Interrupt, /* 129 : CMP1 */
Userdef_INTC_Dummy_Interrupt, /* 130 : INT0 */
Userdef_INTC_Dummy_Interrupt, /* 131 : INT1 */
Userdef_INTC_Dummy_Interrupt, /* 132 : INT2 */
Userdef_INTC_Dummy_Interrupt, /* 133 : INT3 */
Userdef_INTC_Dummy_Interrupt, /* 134 : OSTMI0 */
Userdef_INTC_Dummy_Interrupt, /* 135 : OSTMI1 */
Userdef_INTC_Dummy_Interrupt, /* 136 : CMI */
Userdef_INTC_Dummy_Interrupt, /* 137 : WTOUT */
Userdef_INTC_Dummy_Interrupt, /* 138 : ITI */
Userdef_INTC_Dummy_Interrupt, /* 139 : TGI0A */
Userdef_INTC_Dummy_Interrupt, /* 140 : TGI0B */
Userdef_INTC_Dummy_Interrupt, /* 141 : TGI0C */
Userdef_INTC_Dummy_Interrupt, /* 142 : TGI0D */
Userdef_INTC_Dummy_Interrupt, /* 143 : TGI0V */
Userdef_INTC_Dummy_Interrupt, /* 144 : TGI0E */
Userdef_INTC_Dummy_Interrupt, /* 145 : TGI0F */
Userdef_INTC_Dummy_Interrupt, /* 146 : TGI1A */
Userdef_INTC_Dummy_Interrupt, /* 147 : TGI1B */
Userdef_INTC_Dummy_Interrupt, /* 148 : TGI1V */
Userdef_INTC_Dummy_Interrupt, /* 149 : TGI1U */
Userdef_INTC_Dummy_Interrupt, /* 150 : TGI2A */
Userdef_INTC_Dummy_Interrupt, /* 151 : TGI2B */
Userdef_INTC_Dummy_Interrupt, /* 152 : TGI2V */
Userdef_INTC_Dummy_Interrupt, /* 153 : TGI2U */
Userdef_INTC_Dummy_Interrupt, /* 154 : TGI3A */
Userdef_INTC_Dummy_Interrupt, /* 155 : TGI3B */
Userdef_INTC_Dummy_Interrupt, /* 156 : TGI3C */
Userdef_INTC_Dummy_Interrupt, /* 157 : TGI3D */
Userdef_INTC_Dummy_Interrupt, /* 158 : TGI3V */
Userdef_INTC_Dummy_Interrupt, /* 159 : TGI4A */
Userdef_INTC_Dummy_Interrupt, /* 160 : TGI4B */
Userdef_INTC_Dummy_Interrupt, /* 161 : TGI4C */
Userdef_INTC_Dummy_Interrupt, /* 162 : TGI4D */
Userdef_INTC_Dummy_Interrupt, /* 163 : TGI4V */
Userdef_INTC_Dummy_Interrupt, /* 164 : CMI1 */
Userdef_INTC_Dummy_Interrupt, /* 165 : CMI2 */
Userdef_INTC_Dummy_Interrupt, /* 166 : SGDEI0 */
Userdef_INTC_Dummy_Interrupt, /* 167 : SGDEI1 */
Userdef_INTC_Dummy_Interrupt, /* 168 : SGDEI2 */
Userdef_INTC_Dummy_Interrupt, /* 169 : SGDEI3 */
Userdef_INTC_Dummy_Interrupt, /* 170 : ADI */
Userdef_INTC_Dummy_Interrupt, /* 171 : ADWAR */
Userdef_INTC_Dummy_Interrupt, /* 172 : SSII0 */
Userdef_INTC_Dummy_Interrupt, /* 173 : SSIRXI0 */
Userdef_INTC_Dummy_Interrupt, /* 174 : SSITXI0 */
Userdef_INTC_Dummy_Interrupt, /* 175 : SSII1 */
Userdef_INTC_Dummy_Interrupt, /* 176 : SSIRXI1 */
Userdef_INTC_Dummy_Interrupt, /* 177 : SSITXI1 */
Userdef_INTC_Dummy_Interrupt, /* 178 : SSII2 */
Userdef_INTC_Dummy_Interrupt, /* 179 : SSIRTI2 */
Userdef_INTC_Dummy_Interrupt, /* 180 : SSII3 */
Userdef_INTC_Dummy_Interrupt, /* 181 : SSIRXI3 */
Userdef_INTC_Dummy_Interrupt, /* 182 : SSITXI3 */
Userdef_INTC_Dummy_Interrupt, /* 183 : SSII4 */
Userdef_INTC_Dummy_Interrupt, /* 184 : SSIRTI4 */
Userdef_INTC_Dummy_Interrupt, /* 185 : SSII5 */
Userdef_INTC_Dummy_Interrupt, /* 186 : SSIRXI5 */
Userdef_INTC_Dummy_Interrupt, /* 187 : SSITXI5 */
Userdef_INTC_Dummy_Interrupt, /* 188 : SPDIFI */
Userdef_INTC_Dummy_Interrupt, /* 189 : TEI0 */
Userdef_INTC_Dummy_Interrupt, /* 190 : RI0 */
Userdef_INTC_Dummy_Interrupt, /* 191 : TI0 */
Userdef_INTC_Dummy_Interrupt, /* 192 : SPI0 */
Userdef_INTC_Dummy_Interrupt, /* 193 : STI0 */
Userdef_INTC_Dummy_Interrupt, /* 194 : NAKI0 */
Userdef_INTC_Dummy_Interrupt, /* 195 : ALI0 */
Userdef_INTC_Dummy_Interrupt, /* 196 : TMOI0 */
Userdef_INTC_Dummy_Interrupt, /* 197 : TEI1 */
Userdef_INTC_Dummy_Interrupt, /* 198 : RI1 */
Userdef_INTC_Dummy_Interrupt, /* 199 : TI1 */
Userdef_INTC_Dummy_Interrupt, /* 200 : SPI1 */
Userdef_INTC_Dummy_Interrupt, /* 201 : STI1 */
Userdef_INTC_Dummy_Interrupt, /* 202 : NAKI1 */
Userdef_INTC_Dummy_Interrupt, /* 203 : ALI1 */
Userdef_INTC_Dummy_Interrupt, /* 204 : TMOI1 */
Userdef_INTC_Dummy_Interrupt, /* 205 : TEI2 */
Userdef_INTC_Dummy_Interrupt, /* 206 : RI2 */
Userdef_INTC_Dummy_Interrupt, /* 207 : TI2 */
Userdef_INTC_Dummy_Interrupt, /* 208 : SPI2 */
Userdef_INTC_Dummy_Interrupt, /* 209 : STI2 */
Userdef_INTC_Dummy_Interrupt, /* 210 : NAKI2 */
Userdef_INTC_Dummy_Interrupt, /* 211 : ALI2 */
Userdef_INTC_Dummy_Interrupt, /* 212 : TMOI2 */
Userdef_INTC_Dummy_Interrupt, /* 213 : TEI3 */
Userdef_INTC_Dummy_Interrupt, /* 214 : RI3 */
Userdef_INTC_Dummy_Interrupt, /* 215 : TI3 */
Userdef_INTC_Dummy_Interrupt, /* 216 : SPI3 */
Userdef_INTC_Dummy_Interrupt, /* 217 : STI3 */
Userdef_INTC_Dummy_Interrupt, /* 218 : NAKI3 */
Userdef_INTC_Dummy_Interrupt, /* 219 : ALI3 */
Userdef_INTC_Dummy_Interrupt, /* 220 : TMOI3 */
Userdef_INTC_Dummy_Interrupt, /* 221 : BRI0 */
Userdef_INTC_Dummy_Interrupt, /* 222 : ERI0 */
Userdef_INTC_Dummy_Interrupt, /* 223 : RXI0 */
Userdef_INTC_Dummy_Interrupt, /* 224 : TXI0 */
Userdef_INTC_Dummy_Interrupt, /* 225 : BRI1 */
Userdef_INTC_Dummy_Interrupt, /* 226 : ERI1 */
Userdef_INTC_Dummy_Interrupt, /* 227 : RXI1 */
Userdef_INTC_Dummy_Interrupt, /* 228 : TXI1 */
Userdef_INTC_Dummy_Interrupt, /* 229 : BRI2 */
Userdef_INTC_Dummy_Interrupt, /* 230 : ERI2 */
Userdef_INTC_Dummy_Interrupt, /* 231 : RXI2 */
Userdef_INTC_Dummy_Interrupt, /* 232 : TXI2 */
Userdef_INTC_Dummy_Interrupt, /* 233 : BRI3 */
Userdef_INTC_Dummy_Interrupt, /* 234 : ERI3 */
Userdef_INTC_Dummy_Interrupt, /* 235 : RXI3 */
Userdef_INTC_Dummy_Interrupt, /* 236 : TXI3 */
Userdef_INTC_Dummy_Interrupt, /* 237 : BRI4 */
Userdef_INTC_Dummy_Interrupt, /* 238 : ERI4 */
Userdef_INTC_Dummy_Interrupt, /* 239 : RXI4 */
Userdef_INTC_Dummy_Interrupt, /* 240 : TXI4 */
Userdef_INTC_Dummy_Interrupt, /* 241 : BRI5 */
Userdef_INTC_Dummy_Interrupt, /* 242 : ERI5 */
Userdef_INTC_Dummy_Interrupt, /* 243 : RXI5 */
Userdef_INTC_Dummy_Interrupt, /* 244 : TXI5 */
Userdef_INTC_Dummy_Interrupt, /* 245 : BRI6 */
Userdef_INTC_Dummy_Interrupt, /* 246 : ERI6 */
Userdef_INTC_Dummy_Interrupt, /* 247 : RXI6 */
Userdef_INTC_Dummy_Interrupt, /* 248 : TXI6 */
Userdef_INTC_Dummy_Interrupt, /* 249 : BRI7 */
Userdef_INTC_Dummy_Interrupt, /* 250 : ERI7 */
Userdef_INTC_Dummy_Interrupt, /* 251 : RXI7 */
Userdef_INTC_Dummy_Interrupt, /* 252 : TXI7 */
Userdef_INTC_Dummy_Interrupt, /* 253 : GERI */
Userdef_INTC_Dummy_Interrupt, /* 254 : RFI */
Userdef_INTC_Dummy_Interrupt, /* 255 : CFRXI0 */
Userdef_INTC_Dummy_Interrupt, /* 256 : CERI0 */
Userdef_INTC_Dummy_Interrupt, /* 257 : CTXI0 */
Userdef_INTC_Dummy_Interrupt, /* 258 : CFRXI1 */
Userdef_INTC_Dummy_Interrupt, /* 259 : CERI1 */
Userdef_INTC_Dummy_Interrupt, /* 260 : CTXI1 */
Userdef_INTC_Dummy_Interrupt, /* 261 : CFRXI2 */
Userdef_INTC_Dummy_Interrupt, /* 262 : CERI2 */
Userdef_INTC_Dummy_Interrupt, /* 263 : CTXI2 */
Userdef_INTC_Dummy_Interrupt, /* 264 : CFRXI3 */
Userdef_INTC_Dummy_Interrupt, /* 265 : CERI3 */
Userdef_INTC_Dummy_Interrupt, /* 266 : CTXI3 */
Userdef_INTC_Dummy_Interrupt, /* 267 : CFRXI4 */
Userdef_INTC_Dummy_Interrupt, /* 268 : CERI4 */
Userdef_INTC_Dummy_Interrupt, /* 269 : CTXI4 */
Userdef_INTC_Dummy_Interrupt, /* 270 : SPEI0 */
Userdef_INTC_Dummy_Interrupt, /* 271 : SPRI0 */
Userdef_INTC_Dummy_Interrupt, /* 272 : SPTI0 */
Userdef_INTC_Dummy_Interrupt, /* 273 : SPEI1 */
Userdef_INTC_Dummy_Interrupt, /* 274 : SPRI1 */
Userdef_INTC_Dummy_Interrupt, /* 275 : SPTI1 */
Userdef_INTC_Dummy_Interrupt, /* 276 : SPEI2 */
Userdef_INTC_Dummy_Interrupt, /* 277 : SPRI2 */
Userdef_INTC_Dummy_Interrupt, /* 278 : SPTI2 */
Userdef_INTC_Dummy_Interrupt, /* 279 : SPEI3 */
Userdef_INTC_Dummy_Interrupt, /* 280 : SPRI3 */
Userdef_INTC_Dummy_Interrupt, /* 281 : SPTI3 */
Userdef_INTC_Dummy_Interrupt, /* 282 : SPEI4 */
Userdef_INTC_Dummy_Interrupt, /* 283 : SPRI4 */
Userdef_INTC_Dummy_Interrupt, /* 284 : SPTI4 */
Userdef_INTC_Dummy_Interrupt, /* 285 : IEBBTD */
Userdef_INTC_Dummy_Interrupt, /* 286 : IEBBTERR */
Userdef_INTC_Dummy_Interrupt, /* 287 : IEBBTSTA */
Userdef_INTC_Dummy_Interrupt, /* 288 : IEBBTV */
Userdef_INTC_Dummy_Interrupt, /* 289 : ISY */
Userdef_INTC_Dummy_Interrupt, /* 290 : IERR */
Userdef_INTC_Dummy_Interrupt, /* 291 : ITARG */
Userdef_INTC_Dummy_Interrupt, /* 292 : ISEC */
Userdef_INTC_Dummy_Interrupt, /* 293 : IBUF */
Userdef_INTC_Dummy_Interrupt, /* 294 : IREADY */
Userdef_INTC_Dummy_Interrupt, /* 295 : FLSTE */
Userdef_INTC_Dummy_Interrupt, /* 296 : FLTENDI */
Userdef_INTC_Dummy_Interrupt, /* 297 : FLTREQ0I */
Userdef_INTC_Dummy_Interrupt, /* 298 : FLTREQ1I */
Userdef_INTC_Dummy_Interrupt, /* 299 : MMC0 */
Userdef_INTC_Dummy_Interrupt, /* 300 : MMC1 */
Userdef_INTC_Dummy_Interrupt, /* 301 : MMC2 */
Userdef_INTC_Dummy_Interrupt, /* 302 : SDHI0_3 */
Userdef_INTC_Dummy_Interrupt, /* 303 : SDHI0_0 */
Userdef_INTC_Dummy_Interrupt, /* 304 : SDHI0_1 */
Userdef_INTC_Dummy_Interrupt, /* 305 : SDHI1_3 */
Userdef_INTC_Dummy_Interrupt, /* 306 : SDHI1_0 */
Userdef_INTC_Dummy_Interrupt, /* 307 : SDHI1_1 */
Userdef_INTC_Dummy_Interrupt, /* 308 : ARM */
Userdef_INTC_Dummy_Interrupt, /* 309 : PRD */
Userdef_INTC_Dummy_Interrupt, /* 310 : CUP */
Userdef_INTC_Dummy_Interrupt, /* 311 : SCUAI0 */
Userdef_INTC_Dummy_Interrupt, /* 312 : SCUAI1 */
Userdef_INTC_Dummy_Interrupt, /* 313 : SCUFDI0 */
Userdef_INTC_Dummy_Interrupt, /* 314 : SCUFDI1 */
Userdef_INTC_Dummy_Interrupt, /* 315 : SCUFDI2 */
Userdef_INTC_Dummy_Interrupt, /* 316 : SCUFDI3 */
Userdef_INTC_Dummy_Interrupt, /* 317 : SCUFUI0 */
Userdef_INTC_Dummy_Interrupt, /* 318 : SCUFUI1 */
Userdef_INTC_Dummy_Interrupt, /* 319 : SCUFUI2 */
Userdef_INTC_Dummy_Interrupt, /* 320 : SCUFUI3 */
Userdef_INTC_Dummy_Interrupt, /* 321 : SCUDVI0 */
Userdef_INTC_Dummy_Interrupt, /* 322 : SCUDVI1 */
Userdef_INTC_Dummy_Interrupt, /* 323 : SCUDVI2 */
Userdef_INTC_Dummy_Interrupt, /* 324 : SCUDVI3 */
Userdef_INTC_Dummy_Interrupt, /* 325 : MLBCI */
Userdef_INTC_Dummy_Interrupt, /* 326 : MLBSI */
Userdef_INTC_Dummy_Interrupt, /* 327 : DRC0 */
Userdef_INTC_Dummy_Interrupt, /* 328 : DRC1 */
Userdef_INTC_Dummy_Interrupt, /* 329 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 330 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 331 : LINI0_INT_T */
Userdef_INTC_Dummy_Interrupt, /* 332 : LINI0_INT_R */
Userdef_INTC_Dummy_Interrupt, /* 333 : LINI0_INT_S */
Userdef_INTC_Dummy_Interrupt, /* 334 : LINI0_INT_M */
Userdef_INTC_Dummy_Interrupt, /* 335 : LINI1_INT_T */
Userdef_INTC_Dummy_Interrupt, /* 336 : LINI1_INT_R */
Userdef_INTC_Dummy_Interrupt, /* 337 : LINI1_INT_S */
Userdef_INTC_Dummy_Interrupt, /* 338 : LINI1_INT_M */
Userdef_INTC_Dummy_Interrupt, /* 339 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 340 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 341 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 342 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 343 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 344 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 345 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 346 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 347 : ERI0 */
Userdef_INTC_Dummy_Interrupt, /* 348 : RXI0 */
Userdef_INTC_Dummy_Interrupt, /* 349 : TXI0 */
Userdef_INTC_Dummy_Interrupt, /* 350 : TEI0 */
Userdef_INTC_Dummy_Interrupt, /* 351 : ERI1 */
Userdef_INTC_Dummy_Interrupt, /* 352 : RXI1 */
Userdef_INTC_Dummy_Interrupt, /* 353 : TXI1 */
Userdef_INTC_Dummy_Interrupt, /* 354 : TEI1 */
Userdef_INTC_Dummy_Interrupt, /* 355 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 356 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 357 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 358 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 359 : ETHERI */
Userdef_INTC_Dummy_Interrupt, /* 360 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 361 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 362 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 363 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 364 : CEUI */
Userdef_INTC_Dummy_Interrupt, /* 365 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 366 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 367 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 368 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 369 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 370 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 371 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 372 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 373 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 374 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 375 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 376 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 377 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 378 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 379 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 380 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 381 : H2XMLB_ERRINT */
Userdef_INTC_Dummy_Interrupt, /* 382 : H2XIC1_ERRINT */
Userdef_INTC_Dummy_Interrupt, /* 383 : X2HPERI1_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 384 : X2HPERI2_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 385 : X2HPERI34_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 386 : X2HPERI5_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 387 : X2HPERI67_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 388 : X2HDBGR_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 389 : X2HBSC_ERRINT */
Userdef_INTC_Dummy_Interrupt, /* 390 : X2HSPI1_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 391 : X2HSPI2_ERRINT*/
Userdef_INTC_Dummy_Interrupt, /* 392 : PRRI */
Userdef_INTC_Dummy_Interrupt, /* 393 : IFEI0 */
Userdef_INTC_Dummy_Interrupt, /* 394 : OFFI0 */
Userdef_INTC_Dummy_Interrupt, /* 395 : PFVEI0 */
Userdef_INTC_Dummy_Interrupt, /* 396 : IFEI1 */
Userdef_INTC_Dummy_Interrupt, /* 397 : OFFI1 */
Userdef_INTC_Dummy_Interrupt, /* 398 : PFVEI1 */
Userdef_INTC_Dummy_Interrupt, /* 399 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 400 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 401 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 402 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 403 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 404 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 405 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 406 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 407 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 408 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 409 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 410 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 411 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 412 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 413 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 414 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 415 : <reserved> */
Userdef_INTC_Dummy_Interrupt, /* 416 : TINT0 */
Userdef_INTC_Dummy_Interrupt, /* 417 : TINT1 */
Userdef_INTC_Dummy_Interrupt, /* 418 : TINT2 */
Userdef_INTC_Dummy_Interrupt, /* 419 : TINT3 */
Userdef_INTC_Dummy_Interrupt, /* 420 : TINT4 */
Userdef_INTC_Dummy_Interrupt, /* 421 : TINT5 */
Userdef_INTC_Dummy_Interrupt, /* 422 : TINT6 */
Userdef_INTC_Dummy_Interrupt, /* 423 : TINT7 */
Userdef_INTC_Dummy_Interrupt, /* 424 : TINT8 */
Userdef_INTC_Dummy_Interrupt, /* 425 : TINT9 */
Userdef_INTC_Dummy_Interrupt, /* 426 : TINT10 */
Userdef_INTC_Dummy_Interrupt, /* 427 : TINT11 */
Userdef_INTC_Dummy_Interrupt, /* 428 : TINT12 */
Userdef_INTC_Dummy_Interrupt, /* 429 : TINT13 */
Userdef_INTC_Dummy_Interrupt, /* 430 : TINT14 */
Userdef_INTC_Dummy_Interrupt, /* 431 : TINT15 */
Userdef_INTC_Dummy_Interrupt, /* 432 : TINT16 */
Userdef_INTC_Dummy_Interrupt, /* 433 : TINT17 */
Userdef_INTC_Dummy_Interrupt, /* 434 : TINT18 */
Userdef_INTC_Dummy_Interrupt, /* 435 : TINT19 */
Userdef_INTC_Dummy_Interrupt, /* 436 : TINT20 */
Userdef_INTC_Dummy_Interrupt, /* 437 : TINT21 */
Userdef_INTC_Dummy_Interrupt, /* 438 : TINT22 */
Userdef_INTC_Dummy_Interrupt, /* 439 : TINT23 */
Userdef_INTC_Dummy_Interrupt, /* 440 : TINT24 */
Userdef_INTC_Dummy_Interrupt, /* 441 : TINT25 */
Userdef_INTC_Dummy_Interrupt, /* 442 : TINT26 */
Userdef_INTC_Dummy_Interrupt, /* 443 : TINT27 */
Userdef_INTC_Dummy_Interrupt, /* 444 : TINT28 */
Userdef_INTC_Dummy_Interrupt, /* 445 : TINT29 */
Userdef_INTC_Dummy_Interrupt, /* 446 : TINT30 */
Userdef_INTC_Dummy_Interrupt, /* 447 : TINT31 */
Userdef_INTC_Dummy_Interrupt, /* 448 : TINT32 */
Userdef_INTC_Dummy_Interrupt, /* 449 : TINT33 */
Userdef_INTC_Dummy_Interrupt, /* 450 : TINT34 */
Userdef_INTC_Dummy_Interrupt, /* 451 : TINT35 */
Userdef_INTC_Dummy_Interrupt, /* 452 : TINT36 */
Userdef_INTC_Dummy_Interrupt, /* 453 : TINT37 */
Userdef_INTC_Dummy_Interrupt, /* 454 : TINT38 */
Userdef_INTC_Dummy_Interrupt, /* 455 : TINT39 */
Userdef_INTC_Dummy_Interrupt, /* 456 : TINT40 */
Userdef_INTC_Dummy_Interrupt, /* 457 : TINT41 */
Userdef_INTC_Dummy_Interrupt, /* 458 : TINT42 */
Userdef_INTC_Dummy_Interrupt, /* 459 : TINT43 */
Userdef_INTC_Dummy_Interrupt, /* 460 : TINT44 */
Userdef_INTC_Dummy_Interrupt, /* 461 : TINT45 */
Userdef_INTC_Dummy_Interrupt, /* 462 : TINT46 */
Userdef_INTC_Dummy_Interrupt, /* 463 : TINT47 */
Userdef_INTC_Dummy_Interrupt, /* 464 : TINT48 */
Userdef_INTC_Dummy_Interrupt, /* 465 : TINT49 */
Userdef_INTC_Dummy_Interrupt, /* 466 : TINT50 */
Userdef_INTC_Dummy_Interrupt, /* 467 : TINT51 */
Userdef_INTC_Dummy_Interrupt, /* 468 : TINT52 */
Userdef_INTC_Dummy_Interrupt, /* 469 : TINT53 */
Userdef_INTC_Dummy_Interrupt, /* 470 : TINT54 */
Userdef_INTC_Dummy_Interrupt, /* 471 : TINT55 */
Userdef_INTC_Dummy_Interrupt, /* 472 : TINT56 */
Userdef_INTC_Dummy_Interrupt, /* 473 : TINT57 */
Userdef_INTC_Dummy_Interrupt, /* 474 : TINT58 */
Userdef_INTC_Dummy_Interrupt, /* 475 : TINT59 */
Userdef_INTC_Dummy_Interrupt, /* 476 : TINT60 */
Userdef_INTC_Dummy_Interrupt, /* 477 : TINT61 */
Userdef_INTC_Dummy_Interrupt, /* 478 : TINT62 */
Userdef_INTC_Dummy_Interrupt, /* 479 : TINT63 */
Userdef_INTC_Dummy_Interrupt, /* 480 : TINT64 */
Userdef_INTC_Dummy_Interrupt, /* 481 : TINT65 */
Userdef_INTC_Dummy_Interrupt, /* 482 : TINT66 */
Userdef_INTC_Dummy_Interrupt, /* 483 : TINT67 */
Userdef_INTC_Dummy_Interrupt, /* 484 : TINT68 */
Userdef_INTC_Dummy_Interrupt, /* 485 : TINT69 */
Userdef_INTC_Dummy_Interrupt, /* 486 : TINT70 */
Userdef_INTC_Dummy_Interrupt, /* 487 : TINT71 */
Userdef_INTC_Dummy_Interrupt, /* 488 : TINT72 */
Userdef_INTC_Dummy_Interrupt, /* 489 : TINT73 */
Userdef_INTC_Dummy_Interrupt, /* 490 : TINT74 */
Userdef_INTC_Dummy_Interrupt, /* 491 : TINT75 */
Userdef_INTC_Dummy_Interrupt, /* 492 : TINT76 */
Userdef_INTC_Dummy_Interrupt, /* 493 : TINT77 */
Userdef_INTC_Dummy_Interrupt, /* 494 : TINT78 */
Userdef_INTC_Dummy_Interrupt, /* 495 : TINT79 */
Userdef_INTC_Dummy_Interrupt, /* 496 : TINT80 */
Userdef_INTC_Dummy_Interrupt, /* 497 : TINT81 */
Userdef_INTC_Dummy_Interrupt, /* 498 : TINT82 */
Userdef_INTC_Dummy_Interrupt, /* 499 : TINT83 */
Userdef_INTC_Dummy_Interrupt, /* 500 : TINT84 */
Userdef_INTC_Dummy_Interrupt, /* 501 : TINT85 */
Userdef_INTC_Dummy_Interrupt, /* 502 : TINT86 */
Userdef_INTC_Dummy_Interrupt, /* 503 : TINT87 */
Userdef_INTC_Dummy_Interrupt, /* 504 : TINT88 */
Userdef_INTC_Dummy_Interrupt, /* 505 : TINT89 */
Userdef_INTC_Dummy_Interrupt, /* 506 : TINT90 */
Userdef_INTC_Dummy_Interrupt, /* 507 : TINT91 */
Userdef_INTC_Dummy_Interrupt, /* 508 : TINT92 */
Userdef_INTC_Dummy_Interrupt, /* 509 : TINT93 */
Userdef_INTC_Dummy_Interrupt, /* 510 : TINT94 */
Userdef_INTC_Dummy_Interrupt, /* 511 : TINT95 */
Userdef_INTC_Dummy_Interrupt, /* 512 : TINT96 */
Userdef_INTC_Dummy_Interrupt, /* 513 : TINT97 */
Userdef_INTC_Dummy_Interrupt, /* 514 : TINT98 */
Userdef_INTC_Dummy_Interrupt, /* 515 : TINT99 */
Userdef_INTC_Dummy_Interrupt, /* 516 : TINT100 */
Userdef_INTC_Dummy_Interrupt, /* 517 : TINT101 */
Userdef_INTC_Dummy_Interrupt, /* 518 : TINT102 */
Userdef_INTC_Dummy_Interrupt, /* 519 : TINT103 */
Userdef_INTC_Dummy_Interrupt, /* 520 : TINT104 */
Userdef_INTC_Dummy_Interrupt, /* 521 : TINT105 */
Userdef_INTC_Dummy_Interrupt, /* 522 : TINT106 */
Userdef_INTC_Dummy_Interrupt, /* 523 : TINT107 */
Userdef_INTC_Dummy_Interrupt, /* 524 : TINT108 */
Userdef_INTC_Dummy_Interrupt, /* 525 : TINT109 */
Userdef_INTC_Dummy_Interrupt, /* 526 : TINT110 */
Userdef_INTC_Dummy_Interrupt, /* 527 : TINT111 */
Userdef_INTC_Dummy_Interrupt, /* 528 : TINT112 */
Userdef_INTC_Dummy_Interrupt, /* 529 : TINT113 */
Userdef_INTC_Dummy_Interrupt, /* 530 : TINT114 */
Userdef_INTC_Dummy_Interrupt, /* 531 : TINT115 */
Userdef_INTC_Dummy_Interrupt, /* 532 : TINT116 */
Userdef_INTC_Dummy_Interrupt, /* 533 : TINT117 */
Userdef_INTC_Dummy_Interrupt, /* 534 : TINT118 */
Userdef_INTC_Dummy_Interrupt, /* 535 : TINT119 */
Userdef_INTC_Dummy_Interrupt, /* 536 : TINT120 */
Userdef_INTC_Dummy_Interrupt, /* 537 : TINT121 */
Userdef_INTC_Dummy_Interrupt, /* 538 : TINT122 */
Userdef_INTC_Dummy_Interrupt, /* 539 : TINT123 */
Userdef_INTC_Dummy_Interrupt, /* 540 : TINT124 */
Userdef_INTC_Dummy_Interrupt, /* 541 : TINT125 */
Userdef_INTC_Dummy_Interrupt, /* 542 : TINT126 */
Userdef_INTC_Dummy_Interrupt, /* 543 : TINT127 */
Userdef_INTC_Dummy_Interrupt, /* 544 : TINT128 */
Userdef_INTC_Dummy_Interrupt, /* 545 : TINT129 */
Userdef_INTC_Dummy_Interrupt, /* 546 : TINT130 */
Userdef_INTC_Dummy_Interrupt, /* 547 : TINT131 */
Userdef_INTC_Dummy_Interrupt, /* 548 : TINT132 */
Userdef_INTC_Dummy_Interrupt, /* 549 : TINT133 */
Userdef_INTC_Dummy_Interrupt, /* 550 : TINT134 */
Userdef_INTC_Dummy_Interrupt, /* 551 : TINT135 */
Userdef_INTC_Dummy_Interrupt, /* 552 : TINT136 */
Userdef_INTC_Dummy_Interrupt, /* 553 : TINT137 */
Userdef_INTC_Dummy_Interrupt, /* 554 : TINT138 */
Userdef_INTC_Dummy_Interrupt, /* 555 : TINT139 */
Userdef_INTC_Dummy_Interrupt, /* 556 : TINT140 */
Userdef_INTC_Dummy_Interrupt, /* 557 : TINT141 */
Userdef_INTC_Dummy_Interrupt, /* 558 : TINT142 */
Userdef_INTC_Dummy_Interrupt, /* 559 : TINT143 */
Userdef_INTC_Dummy_Interrupt, /* 560 : TINT144 */
Userdef_INTC_Dummy_Interrupt, /* 561 : TINT145 */
Userdef_INTC_Dummy_Interrupt, /* 562 : TINT146 */
Userdef_INTC_Dummy_Interrupt, /* 563 : TINT147 */
Userdef_INTC_Dummy_Interrupt, /* 564 : TINT148 */
Userdef_INTC_Dummy_Interrupt, /* 565 : TINT149 */
Userdef_INTC_Dummy_Interrupt, /* 566 : TINT150 */
Userdef_INTC_Dummy_Interrupt, /* 567 : TINT151 */
Userdef_INTC_Dummy_Interrupt, /* 568 : TINT152 */
Userdef_INTC_Dummy_Interrupt, /* 569 : TINT153 */
Userdef_INTC_Dummy_Interrupt, /* 570 : TINT154 */
Userdef_INTC_Dummy_Interrupt, /* 571 : TINT155 */
Userdef_INTC_Dummy_Interrupt, /* 572 : TINT156 */
Userdef_INTC_Dummy_Interrupt, /* 573 : TINT157 */
Userdef_INTC_Dummy_Interrupt, /* 574 : TINT158 */
Userdef_INTC_Dummy_Interrupt, /* 575 : TINT159 */
Userdef_INTC_Dummy_Interrupt, /* 576 : TINT160 */
Userdef_INTC_Dummy_Interrupt, /* 577 : TINT161 */
Userdef_INTC_Dummy_Interrupt, /* 578 : TINT162 */
Userdef_INTC_Dummy_Interrupt, /* 579 : TINT163 */
Userdef_INTC_Dummy_Interrupt, /* 580 : TINT164 */
Userdef_INTC_Dummy_Interrupt, /* 581 : TINT165 */
Userdef_INTC_Dummy_Interrupt, /* 582 : TINT166 */
Userdef_INTC_Dummy_Interrupt, /* 583 : TINT167 */
Userdef_INTC_Dummy_Interrupt, /* 584 : TINT168 */
Userdef_INTC_Dummy_Interrupt, /* 585 : TINT169 */
Userdef_INTC_Dummy_Interrupt, /* 586 : TINT170 */
};
/******************************************************************************
* Function Name: Userdef_INTC_RegistIntFunc
* Description :
* Arguments : uint16_t int_id
* : void (* func)(uint32_t)
* Return Value : none
******************************************************************************/
void Userdef_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense))
{
intc_func_table[int_id] = func;
}
/******************************************************************************
* Function Name: Userdef_INTC_UndefId
* Description :
* Arguments : uint16_t int_id
* Return Value : none
******************************************************************************/
void Userdef_INTC_UndefId(uint16_t int_id)
{
while (1)
{
/* Do Nothing */
}
}
/******************************************************************************
* Function Name: Userdef_INTC_Dummy_Interrupt
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
static void Userdef_INTC_Dummy_Interrupt(uint32_t int_sense)
{
/* Do Nothing */
}
/******************************************************************************
* Function Name: Userdef_FIQ_HandlerExe
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
void Userdef_FIQ_HandlerExe(void)
{
}
/* The function called by the RTOS port layer after it has managed interrupt
entry. */
void vApplicationIRQHandler( uint32_t ulICCIAR )
{
uint32_t ulInterruptID;
/* Re-enable interrupts. */
__enable_irq();
/* The ID of the interrupt can be obtained by bitwise anding the ICCIAR value
with 0x3FF. */
ulInterruptID = ulICCIAR & 0x3FFUL;
/* Call the function installed in the array of installed handler functions. */
intc_func_table[ ulInterruptID ]( 0 );
}
/* END of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm.c
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - OS timer device driver (Initialize process)
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_ostm.h" /* OSTM Driver header */
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/* ==== OSTM H/W ==== */
#define OSTM_CH_TOTAL (2)
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
static void OSTM_Open(volatile struct st_ostm_n * ostm);
static void OSTM_Close(volatile struct st_ostm_n * ostm, uint32_t * count);
/******************************************************************************
* Function Name: R_OSTM_Init
* Description :
* Arguments : uint32_t channel
* : uint32_t mode
* : uint32_t cycle
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_OSTM_Init(uint32_t channel, uint32_t mode, uint32_t cycle)
{
int32_t ret;
if ((channel >= OSTM_CH_TOTAL) || (mode > OSTM_MODE_COMPARE))
{
return DEVDRV_ERROR;
}
switch (channel)
{
case DEVDRV_CH_0:
ret = Userdef_OSTM0_Init(mode, cycle);
break;
case DEVDRV_CH_1:
ret = Userdef_OSTM1_Init(mode, cycle);
break;
default:
ret = DEVDRV_ERROR;
break;
}
return ret;
}
/******************************************************************************
* Function Name: R_OSTM_Open
* Description :
* Arguments : int32_t channel
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_OSTM_Open(uint32_t channel)
{
if (channel >= OSTM_CH_TOTAL)
{
return DEVDRV_ERROR;
}
switch (channel)
{
case DEVDRV_CH_0:
OSTM_Open(&OSTM0);
break;
case DEVDRV_CH_1:
OSTM_Open(&OSTM1);
break;
default:
break;
}
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: R_OSTM_Close
* Description :
* Arguments : uint32_t channel
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t R_OSTM_Close(uint32_t channel, uint32_t * count)
{
if (channel >= OSTM_CH_TOTAL)
{
return DEVDRV_ERROR;
}
switch (channel)
{
case DEVDRV_CH_0:
OSTM_Close(&OSTM0, count);
break;
case DEVDRV_CH_1:
OSTM_Close(&OSTM1, count);
break;
default:
break;
}
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: int_ostm0_interrupt
* Description :
* Arguments : none
* Return Value : none
******************************************************************************/
int32_t R_OSTM_Interrupt(uint32_t channel)
{
if (channel >= OSTM_CH_TOTAL)
{
return DEVDRV_ERROR;
}
switch (channel)
{
case DEVDRV_CH_0:
Userdef_OSTM0_Int();
break;
case DEVDRV_CH_1:
Userdef_OSTM1_Int();
break;
default:
break;
}
return DEVDRV_SUCCESS;
}
/*******************************************************************************
* Function Name: OSTM_Open
* Description : This function opens OSTM.
* Arguments : volatile struct st_scif_n * ostm
* Return Value : none
*******************************************************************************/
static void OSTM_Open(volatile struct st_ostm_n * ostm)
{
ostm->OSTMnTS.BIT.OSTMnTS = 1;
}
/******************************************************************************
* Function Name: OSTM_Close
* Description : This function closes OSTM.
* Arguments : volatile struct st_scif_n * ostm
* Return Value : none
******************************************************************************/
static void OSTM_Close(volatile struct st_ostm_n * ostm, uint32_t * count)
{
ostm->OSTMnTT.BIT.OSTMnTT = 1;
*count = ostm->OSTMnCNT;
}
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_userdef.c
* $Rev: $
* $Date:: $
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.13
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - OS timer device driver (User define function)
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_ostm.h" /* OSTM Driver header */
#include "devdrv_intc.h" /* INTC Driver Header */
#include "iodefine.h"
#include "main.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define P0_CLOCK_FREQUENCY_kHz (33.333 * 1000) /* 33.333MHz */
#define MAX_CYCLE_msec (0xFFFFFFFF / P0_CLOCK_FREQUENCY_kHz)
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
static volatile uint8_t ostm_int_flg;
/******************************************************************************
* Function Name: Userdef_OSTM0_Init
* Description :
* Arguments : uint32_t mode
* : uint32_t cycle
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t Userdef_OSTM0_Init(uint32_t mode, uint32_t cycle)
{
return DEVDRV_SUCCESS;
}
/******************************************************************************
* Function Name: Userdef_OSTM1_Init
* Description :
* Arguments : uint32_t mode
* : uint32_t cycle
* Return Value : DEVDRV_SUCCESS
* : DEVDRV_ERROR
******************************************************************************/
int32_t Userdef_OSTM1_Init(uint32_t mode, uint32_t cycle)
{
return 0;
}
/******************************************************************************
* Function Name: Userdef_OSTM0_Int
* Description :
* Arguments :
* Return Value : none
******************************************************************************/
void Userdef_OSTM0_Int(void)
{
}
/******************************************************************************
* Function Name: Userdef_OSTM1_Int
* Description :
* Arguments :
* Return Value : none
******************************************************************************/
void Userdef_OSTM1_Int(void)
{
}
/******************************************************************************
* Function Name: Userdef_OSTM0_WaitInt
* Description :
* Arguments :
* Return Value : none
******************************************************************************/
void Userdef_OSTM0_WaitInt(void)
{
}
/******************************************************************************
* Function Name: Userdef_OSTM1_WaitInt
* Description :
* Arguments :
* Return Value : none
******************************************************************************/
void Userdef_OSTM1_WaitInt(void)
{
}
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/scif_uart_driver/scif_uart.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scif_uart_initialize.c
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - SCIF UART device driver (Initialize process)
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_scif_uart.h" /* UART Driver header */
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define SCIF_UART_CH_TOTAL (8)
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: R_SCIF_UART_Init
* Description :
* Arguments : uint32_t channel
* : uint32_t mode
* : : SCIF_UART_MODE_W
* : : SCIF_UART_MODE_R
* : : SCIF_UART_MODE_RW
* : uint16_t cks
* : uint8_t scbrr
* Return Value : DEVDRV_SUCCESS : Success
* : DEVDRV_ERROR : Error
******************************************************************************/
int32_t R_SCIF_UART_Init(uint32_t channel, uint32_t mode, uint16_t cks, uint8_t scbrr)
{
if ((channel >= SCIF_UART_CH_TOTAL) || (mode < SCIF_UART_MODE_W) || (mode > SCIF_UART_MODE_RW) || (cks > 3))
{
return DEVDRV_ERROR;
}
switch (channel)
{
case DEVDRV_CH_2:
Userdef_SCIF2_UART_Init(mode, cks, scbrr);
break;
default:
/* Do Nothing */
break;
}
return DEVDRV_SUCCESS;
}
/* End of File */

143
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/userdef/scif_uart_userdef.c
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scif_uart_userdef.c
* $Rev: $
* $Date:: $
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.13
* : ARM Complier
* OS :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program - SCIF UART device driver (User define function)
* Operation :
* Limitations :
*******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include <stdio.h>
#include "r_typedefs.h"
#include "dev_drv.h" /* Device Driver common header */
#include "devdrv_scif_uart.h" /* UART Driver header */
#include "devdrv_intc.h" /* INTC Driver Header */
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/******************************************************************************
* Function Name: Userdef_SCIF2_UART_Init
* Description :
* Arguments : uint8_t mode
* : uint16_t cks
* : uint8_t scbrr
* Return Value : none
******************************************************************************/
void Userdef_SCIF2_UART_Init(uint8_t mode, uint16_t cks, uint8_t scbrr)
{
/* ==== SCIF initial setting ==== */
/* ---- Serial control register (SCSCR2) setting ---- */
/* SCIF transmitting and receiving operations stop */
SCIF2.SCSCR.WORD = 0x0000;
if (SCIF_UART_MODE_W == (mode & SCIF_UART_MODE_W))
{
/* ---- FIFO control register (SCFCR2) setting ---- */
SCIF2.SCFCR.BIT.TFRST = 1; /* Transmit FIFO reset */
}
if (SCIF_UART_MODE_R == (mode & SCIF_UART_MODE_R))
{
/* ---- FIFO control register (SCFCR2) setting ---- */
/* SCIF transmitting and receiving operations stop */
SCIF2.SCFCR.BIT.RFRST = 1;
/* Receive FIFO data register reset */
}
/* ---- Serial status register(SCFSR2) setting ---- */
/* ER,BRK,DR bit clear */
SCIF2.SCFSR.WORD &= 0xFF6E;
/* ---- Line status register (SCLSR2) setting ---- */
/* ORER bit clear */
SCIF2.SCLSR.BIT.ORER = 0;
/* ---- Serial control register (SCSCR2) setting ---- */
/* B'00 : Internal CLK */
SCIF2.SCSCR.BIT.CKE = 0x0;
/* ---- Serial mode register (SCSMR2) setting ---- */
/* Communication mode 0: Asynchronous mode */
/* Character length 0: 8-bit data */
/* Parity enable 0: Add and check are disabled */
/* Stop bit length 0: 1 stop bit */
/* Clock select cks(argument) */
SCIF2.SCSMR.WORD = cks & 0x0003;
/* ---- Sets the Serial extension mode register (SCEMR2) ---- */
/* Baud rate generator double-speed mode, 0: Normal mode */
/* Base clock select in asynchronous mode, */
/* 0: Base clock is 16 times the bit rate */
SCIF2.SCEMR.WORD = 0x0000;
/* ---- Bit rate register (SCBRR2) setting ---- */
SCIF2.SCBRR.BYTE = scbrr;
/* ---- FIFO control register (SCFCR2) setting ---- */
/* RTS output active trigger :Initial value */
/* Receive FIFO data trigger :1-data */
/* Transmit FIFO data trigger :0-data */
/* Modem control enable :Disabled */
/* Receive FIFO data register reset :Disabled */
/* Loop-back test :Disabled */
SCIF2.SCFCR.WORD = 0x0030;
/* ---- Serial port register (SCSPTR2) setting ---- */
/* Serial port break output(SPB2IO) 1: Enabled */
/* Serial port break data(SPB2DT) 1: High-level */
SCIF2.SCSPTR.WORD |= 0x0003;
}
/* End of File */

64
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/irqfiq_handler.s
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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : irqfiq_handler.s
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.13
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program - IRQ, FIQ handler
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
INTC_ICCIAR_ADDR EQU 0xE820200C
INTC_ICCEOIR_ADDR EQU 0xE8202010
;==================================================================
; Entry point for the FIQ handler
;==================================================================
PRESERVE8
AREA IRQ_FIQ_HANDLER, CODE, READONLY
IMPORT FiqHandler_Interrupt
EXPORT fiq_handler
fiq_handler
BL FiqHandler_Interrupt
fiq_handler_end
B fiq_handler_end
Literals3
LTORG
END

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/reset_handler.s
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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : reset_handler.s
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.8
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program - Reset handler
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
USR_MODE EQU 0x10
FIQ_MODE EQU 0x11
IRQ_MODE EQU 0x12
SVC_MODE EQU 0x13
ABT_MODE EQU 0x17
UND_MODE EQU 0x1b
SYS_MODE EQU 0x1f
Thum_bit EQU 0x20 ; CPSR/SPSR Thumb bit
;==================================================================
; Entry point for the Reset handler
;==================================================================
PRESERVE8
AREA RESET_HANDLER, CODE, READONLY
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
IMPORT ||Image$$IRQ_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
IMPORT ||Image$$FIQ_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
IMPORT ||Image$$SVC_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
IMPORT ||Image$$ABT_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
IMPORT Peripheral_BasicInit
IMPORT init_TTB
IMPORT __main
EXPORT reset_handler
EXPORT undefined_handler
EXPORT svc_handler
EXPORT prefetch_handler
EXPORT abort_handler
EXPORT reserved_handler
;==================================================================
; Reset Handler
;==================================================================
reset_handler FUNCTION {}
;==================================================================
; Disable cache and MMU in case it was left enabled from an earlier run
; This does not need to be done from a cold reset
;==================================================================
MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 System Control register (SCTLR)
BIC r0, r0, #(0x1 << 12) ;;; Clear I bit 12 to disable I Cache
BIC r0, r0, #(0x1 << 2) ;;; Clear C bit 2 to disable D Cache
BIC r0, r0, #0x1 ;;; Clear M bit 0 to disable MMU
MCR p15, 0, r0, c1, c0, 0 ;;; Write value back to CP15 System Control register
;==================================================================
; Setting up Stack Area
;==================================================================
;;; SVC Mode(Default)
LDR sp, =||Image$$SVC_STACK$$ZI$$Limit||
CPS #IRQ_MODE ;;; IRQ Mode
LDR sp, =||Image$$IRQ_STACK$$ZI$$Limit||
CPS #FIQ_MODE ;;; FIQ Mode
LDR sp, =||Image$$FIQ_STACK$$ZI$$Limit||
CPS #ABT_MODE ;;; ABT Mode
LDR sp, =||Image$$ABT_STACK$$ZI$$Limit||
;; FreeRTOS Note:
;; FreeRTOS does not need a System/User mode stack as only tasks run in
;; System/User mode, and their stack is allocated when the task is created.
;; Therefore the CSTACK allocated in the linker script is instead given to
;; Supervisor mode, and main() is called from Supervisor mode.
CPS #SVC_MODE ;;; SVC Mode
;; SVC mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry()
LDR sp, =||Image$$ARM_LIB_STACK$$ZI$$Limit||
;==================================================================
; TLB maintenance, Invalidate Data and Instruction TLBs
;==================================================================
MOV r0,#0
MCR p15, 0, r0, c8, c7, 0 ;;; Cortex-A9 I-TLB and D-TLB invalidation (TLBIALL)
;===================================================================
; Invalidate instruction cache, also flushes BTAC
;===================================================================
MOV r0, #0 ;;; SBZ
MCR p15, 0, r0, c7, c5, 0 ;;; ICIALLU - Invalidate entire I Cache, and flushes branch target cache
;==================================================================
; Cache Invalidation code for Cortex-A9
;==================================================================
;;; Invalidate L1 Instruction Cache
MRC p15, 1, r0, c0, c0, 1 ;;; Read Cache Level ID Register (CLIDR)
TST r0, #0x3 ;;; Harvard Cache?
MOV r0, #0
MCRNE p15, 0, r0, c7, c5, 0 ;;; Invalidate Instruction Cache
;;; Invalidate Data/Unified Caches
MRC p15, 1, r0, c0, c0, 1 ;;; Read CLIDR
ANDS r3, r0, #0x07000000 ;;; Extract coherency level
MOV r3, r3, LSR #23 ;;; Total cache levels << 1
BEQ Finished ;;; If 0, no need to clean
MOV r10, #0 ;;; R10 holds current cache level << 1
Loop1
ADD r2, r10, r10, LSR #1 ;;; R2 holds cache "Set" position
MOV r1, r0, LSR r2 ;;; Bottom 3 bits are the Cache-type for this level
AND r1, r1, #7 ;;; Isolate those lower 3 bits
CMP r1, #2
BLT Skip ;;; No cache or only instruction cache at this level
MCR p15, 2, r10, c0, c0, 0 ;;; Write the Cache Size selection register (CSSELR)
ISB ;;; ISB to sync the change to the CacheSizeID reg
MRC p15, 1, r1, c0, c0, 0 ;;; Reads current Cache Size ID register (CCSIDR)
AND r2, r1, #7 ;;; Extract the line length field
ADD r2, r2, #4 ;;; Add 4 for the line length offset (log2 16 bytes)
LDR r4, =0x3FF
ANDS r4, r4, r1, LSR #3 ;;; R4 is the max number on the way size (right aligned)
CLZ r5, r4 ;;; R5 is the bit position of the way size increment
LDR r7, =0x7FFF
ANDS r7, r7, r1, LSR #13 ;;; R7 is the max number of the index size (right aligned)
Loop2
MOV r9, r4 ;;; R9 working copy of the max way size (right aligned)
Loop3
ORR r11, r10, r9, LSL r5 ;;; Factor in the Way number and cache number into R11
ORR r11, r11, r7, LSL r2 ;;; Factor in the Set number
MCR p15, 0, r11, c7, c6, 2 ;;; Invalidate by Set/Way (DCISW)
SUBS r9, r9, #1 ;;; Decrement the Way number
BGE Loop3
SUBS r7, r7, #1 ;;; Decrement the Set number
BGE Loop2
Skip
ADD r10, r10, #2 ;;; increment the cache number
CMP r3, r10
BGT Loop1
Finished
;==================================================================
; TTB initialize
;==================================================================
BL init_TTB ;;; Initialize TTB
;===================================================================
; Setup domain control register - Enable all domains to client mode
;===================================================================
MRC p15, 0, r0, c3, c0, 0 ;;; Read Domain Access Control Register (DACR)
LDR r0, =0x55555555 ;;; Initialize every domain entry to b01 (client)
MCR p15, 0, r0, c3, c0, 0 ;;; Write Domain Access Control Register
IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP}
;==================================================================
; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
; Enables Full Access i.e. in both privileged and non privileged modes
;==================================================================
MRC p15, 0, r0, c1, c0, 2 ;;; Read Coprocessor Access Control Register (CPACR)
ORR r0, r0, #(0xF << 20) ;;; Enable access to CP 10 & 11
MCR p15, 0, r0, c1, c0, 2 ;;; Write Coprocessor Access Control Register (CPACR)
ISB
;=================================================================
; Switch on the VFP and NEON hardware
;=================================================================
MOV r0, #0x40000000
VMSR FPEXC, r0 ;;; Write FPEXC register, EN bit set
ENDIF
;===================================================================
; Enable MMU
; Leaving the caches disabled until after scatter loading(__main).
;===================================================================
MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 System Control register (SCTLR)
BIC r0, r0, #(0x1 << 12) ;;; Clear I bit 12 to disable I Cache
BIC r0, r0, #(0x1 << 2) ;;; Clear C bit 2 to disable D Cache
BIC r0, r0, #0x2 ;;; Clear A bit 1 to disable strict alignment fault checking
ORR r0, r0, #0x1 ;;; Set M bit 0 to enable MMU before scatter loading
MCR p15, 0, r0, c1, c0, 0 ;;; Write CP15 System Control register
;==================================================================
; Hardware initialize
; Initialize CPG, BSC for CS0 and CS1, and enable On-Chip Data-Retention RAM
;==================================================================
LDR r12,=Peripheral_BasicInit ;;; Save this in register for possible long jump
BLX r12 ;;; Hardware Initialize
;===================================================================
; Branch to __main
;===================================================================
LDR r12,=__main ;;; Save this in register for possible long jump
BX r12 ;;; Branch to __main C library entry point
ENDFUNC
Literals2
LTORG
;==================================================================
; Other Handler
;==================================================================
undefined_handler
B undefined_handler ;;; Ž©”Ô’nƒ‹<C692>[ƒv
svc_handler
B svc_handler ;;; Ž©”Ô’nƒ‹<C692>[ƒv
prefetch_handler
B prefetch_handler ;;; Ž©”Ô’nƒ‹<C692>[ƒv
abort_handler
B abort_handler ;;; Ž©”Ô’nƒ‹<C692>[ƒv
reserved_handler
B reserved_handler ;;; Ž©”Ô’nƒ‹<C692>[ƒv
END

69
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/command.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : command.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - Command header
******************************************************************************/
#ifndef _COMMAND_H_
#define _COMMAND_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
typedef struct command_list
{
char_t *cmd_str;
int32_t (*cmdexe)(int32_t, char_t **);
int32_t (*helpexe)(void);
} command_list_t;
/******************************************************************************
Macro definitions
******************************************************************************/
/* Maximum number of characters for arguments */
#define COMMAND_MAX_ARGLENGTH (256)
#define COMMAND_EXIT (-100)
#define COMMAND_SUCCESS (0)
#define COMMAND_ERROR (-1)
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
int32_t CommandExe(char_t * buff);
void CommandSetCmdList(const command_list_t * cmd);
#endif /* _COMMAND_H_ */
/* End of File */

80
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/dev_drv.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : dev_drv.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - Device driver header
******************************************************************************/
#ifndef _DEV_DRV_H_
#define _DEV_DRV_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define DEVDRV_SUCCESS (0) /* Success */
#define DEVDRV_ERROR (-1) /* Failure */
#define DEVDRV_FLAG_OFF (0) /* Flag OFF */
#define DEVDRV_FLAG_ON (1) /* Flag ON */
typedef enum devdrv_ch
{
DEVDRV_CH_0, /* Channel 0 */
DEVDRV_CH_1, /* Channel 1 */
DEVDRV_CH_2, /* Channel 2 */
DEVDRV_CH_3, /* Channel 3 */
DEVDRV_CH_4, /* Channel 4 */
DEVDRV_CH_5, /* Channel 5 */
DEVDRV_CH_6, /* Channel 6 */
DEVDRV_CH_7, /* Channel 7 */
DEVDRV_CH_8, /* Channel 8 */
DEVDRV_CH_9, /* Channel 9 */
DEVDRV_CH_10, /* Channel 10 */
DEVDRV_CH_11, /* Channel 11 */
DEVDRV_CH_12, /* Channel 12 */
DEVDRV_CH_13, /* Channel 13 */
DEVDRV_CH_14, /* Channel 14 */
DEVDRV_CH_15 /* Channel 15 */
} devdrv_ch_t;
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
#endif /* _DEV_DRV_H_ */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : devdrv_common.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - Common driver header
******************************************************************************/
#ifndef _DEVDRV_COMMON_H_
#define _DEVDRV_COMMON_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define BSC_AREA_CS0 (0x01) /* CS0 */
#define BSC_AREA_CS1 (0x02) /* CS1 */
#define BSC_AREA_CS2 (0x04) /* CS2 */
#define BSC_AREA_CS3 (0x08) /* CS3 */
#define BSC_AREA_CS4 (0x10) /* CS4 */
#define BSC_AREA_CS5 (0x20) /* CS5 */
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void R_BSC_Init(uint8_t area);
void Userdef_BSC_CS0Init(void);
void Userdef_BSC_CS1Init(void);
void Userdef_BSC_CS2Init(void);
void Userdef_BSC_CS3Init(void);
void Userdef_BSC_CS4Init(void);
void Userdef_BSC_CS5Init(void);
#endif /* _DEVDRV_COMMON_H_ */
/* End of File */

585
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_intc.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : devdrv_intc.h
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - INTC device driver header
******************************************************************************/
#ifndef _DEVDRV_INTC_H_
#define _DEVDRV_INTC_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define INTC_ID_TOTAL (587)
#define INTC_ID_SW0 (0)
#define INTC_ID_SW1 (1) /* */
#define INTC_ID_SW2 (2) /* */
#define INTC_ID_SW3 (3) /* */
#define INTC_ID_SW4 (4) /* */
#define INTC_ID_SW5 (5) /* */
#define INTC_ID_SW6 (6) /* */
#define INTC_ID_SW7 (7) /* */
#define INTC_ID_SW8 (8) /* */
#define INTC_ID_SW9 (9) /* */
#define INTC_ID_SW10 (10) /* */
#define INTC_ID_SW11 (11) /* */
#define INTC_ID_SW12 (12) /* */
#define INTC_ID_SW13 (13) /* */
#define INTC_ID_SW14 (14) /* */
#define INTC_ID_SW15 (15) /* */
#define INTC_ID_PMUIRQ0 (16) /* CPU */
#define INTC_ID_COMMRX0 (17) /* */
#define INTC_ID_COMMTX0 (18) /* */
#define INTC_ID_CTIIRQ0 (19) /* */
#define INTC_ID_IRQ0 (32) /* IRQ */
#define INTC_ID_IRQ1 (33) /* */
#define INTC_ID_IRQ2 (34) /* */
#define INTC_ID_IRQ3 (35) /* */
#define INTC_ID_IRQ4 (36) /* */
#define INTC_ID_IRQ5 (37) /* */
#define INTC_ID_IRQ6 (38) /* */
#define INTC_ID_IRQ7 (39) /* */
#define INTC_ID_PL310ERR (40)
#define INTC_ID_DMAINT0 (41)
#define INTC_ID_DMAINT1 (42) /* */
#define INTC_ID_DMAINT2 (43) /* */
#define INTC_ID_DMAINT3 (44) /* */
#define INTC_ID_DMAINT4 (45) /* */
#define INTC_ID_DMAINT5 (46) /* */
#define INTC_ID_DMAINT6 (47) /* */
#define INTC_ID_DMAINT7 (48) /* */
#define INTC_ID_DMAINT8 (49) /* */
#define INTC_ID_DMAINT9 (50) /* */
#define INTC_ID_DMAINT10 (51) /* */
#define INTC_ID_DMAINT11 (52) /* */
#define INTC_ID_DMAINT12 (53) /* */
#define INTC_ID_DMAINT13 (54) /* */
#define INTC_ID_DMAINT14 (55) /* */
#define INTC_ID_DMAINT15 (56) /* */
#define INTC_ID_DMAERR (57) /* */
#define INTC_ID_USBI0 (73)
#define INTC_ID_USBI1 (74) /* */
#define INTC_ID_S0_VI_VSYNC0 (75)
#define INTC_ID_S0_LO_VSYNC0 (76) /* */
#define INTC_ID_S0_VSYNCERR0 (77) /* */
#define INTC_ID_GR3_VLINE0 (78) /* */
#define INTC_ID_S0_VFIELD0 (79) /* */
#define INTC_ID_IV1_VBUFERR0 (80) /* */
#define INTC_ID_IV3_VBUFERR0 (81) /* */
#define INTC_ID_IV5_VBUFERR0 (82) /* */
#define INTC_ID_IV6_VBUFERR0 (83) /* */
#define INTC_ID_S0_WLINE0 (84) /* */
#define INTC_ID_S1_VI_VSYNC0 (85) /* */
#define INTC_ID_S1_LO_VSYNC0 (86) /* */
#define INTC_ID_S1_VSYNCERR0 (87) /* */
#define INTC_ID_S1_VFIELD0 (88) /* */
#define INTC_ID_IV2_VBUFERR0 (89) /* */
#define INTC_ID_IV4_VBUFERR0 (90) /* */
#define INTC_ID_S1_WLINE0 (91) /* */
#define INTC_ID_OIR_VI_VSYNC0 (92) /* */
#define INTC_ID_OIR_LO_VSYNC0 (93) /* */
#define INTC_ID_OIR_VSYNCERR0 (94) /* */
#define INTC_ID_OIR_VFIELD0 (95) /* */
#define INTC_ID_IV7_VBUFERR0 (96) /* */
#define INTC_ID_IV8_VBUFERR0 (97) /* */
#define INTC_ID_OIR_WLINE0 (98) /* */
#define INTC_ID_S0_VI_VSYNC1 (99) /* */
#define INTC_ID_S0_LO_VSYNC1 (100) /* */
#define INTC_ID_S0_VSYNCERR1 (101) /* */
#define INTC_ID_GR3_VLINE1 (102) /* */
#define INTC_ID_S0_VFIELD1 (103) /* */
#define INTC_ID_IV1_VBUFERR1 (104) /* */
#define INTC_ID_IV3_VBUFERR1 (105) /* */
#define INTC_ID_IV5_VBUFERR1 (106) /* */
#define INTC_ID_IV6_VBUFERR1 (107) /* */
#define INTC_ID_S0_WLINE1 (108) /* */
#define INTC_ID_S1_VI_VSYNC1 (109) /* */
#define INTC_ID_S1_LO_VSYNC1 (110) /* */
#define INTC_ID_S1_VSYNCERR1 (111) /* */
#define INTC_ID_S1_VFIELD1 (112) /* */
#define INTC_ID_IV2_VBUFERR1 (113) /* */
#define INTC_ID_IV4_VBUFERR1 (114) /* */
#define INTC_ID_S1_WLINE1 (115) /* */
#define INTC_ID_OIR_VI_VSYNC1 (116) /* */
#define INTC_ID_OIR_LO_VSYNC1 (117) /* */
#define INTC_ID_OIR_VLINE1 (118) /* */
#define INTC_ID_OIR_VFIELD1 (119) /* */
#define INTC_ID_IV7_VBUFERR1 (120) /* */
#define INTC_ID_IV8_VBUFERR1 (121) /* */
#define INTC_ID_OIR_WLINE1 (122) /* */
#define INTC_ID_IMRDI (123)
#define INTC_ID_IMR2I0 (124) /* */
#define INTC_ID_IMR2I1 (125) /* */
#define INTC_ID_JEDI (126)
#define INTC_ID_JDTI (127) /* */
#define INTC_ID_CMP0 (128)
#define INTC_ID_CMP1 (129) /* */
#define INTC_ID_INT0 (130)
#define INTC_ID_INT1 (131) /* */
#define INTC_ID_INT2 (132) /* */
#define INTC_ID_INT3 (133) /* */
#define INTC_ID_OSTMI0 (134)
#define INTC_ID_OSTMI1 (135) /* */
#define INTC_ID_CMI (136)
#define INTC_ID_WTOUT (137) /* */
#define INTC_ID_ITI (138)
#define INTC_ID_TGI0A (139)
#define INTC_ID_TGI0B (140) /* */
#define INTC_ID_TGI0C (141) /* */
#define INTC_ID_TGI0D (142) /* */
#define INTC_ID_TGI0V (143) /* */
#define INTC_ID_TGI0E (144) /* */
#define INTC_ID_TGI0F (145) /* */
#define INTC_ID_TGI1A (146) /* */
#define INTC_ID_TGI1B (147) /* */
#define INTC_ID_TGI1V (148) /* */
#define INTC_ID_TGI1U (149) /* */
#define INTC_ID_TGI2A (150) /* */
#define INTC_ID_TGI2B (151) /* */
#define INTC_ID_TGI2V (152) /* */
#define INTC_ID_TGI2U (153) /* */
#define INTC_ID_TGI3A (154) /* */
#define INTC_ID_TGI3B (155) /* */
#define INTC_ID_TGI3C (156) /* */
#define INTC_ID_TGI3D (157) /* */
#define INTC_ID_TGI3V (158) /* */
#define INTC_ID_TGI4A (159) /* */
#define INTC_ID_TGI4B (160) /* */
#define INTC_ID_TGI4C (161) /* */
#define INTC_ID_TGI4D (162) /* */
#define INTC_ID_TGI4V (163) /* */
#define INTC_ID_CMI1 (164)
#define INTC_ID_CMI2 (165) /* */
#define INTC_ID_SGDEI0 (166)
#define INTC_ID_SGDEI1 (167) /* */
#define INTC_ID_SGDEI2 (168) /* */
#define INTC_ID_SGDEI3 (169) /* */
#define INTC_ID_ADI (170)
#define INTC_ID_ADWAR (171) /* */
#define INTC_ID_SSII0 (172)
#define INTC_ID_SSIRXI0 (173) /* */
#define INTC_ID_SSITXI0 (174) /* */
#define INTC_ID_SSII1 (175) /* */
#define INTC_ID_SSIRXI1 (176) /* */
#define INTC_ID_SSITXI1 (177) /* */
#define INTC_ID_SSII2 (178) /* */
#define INTC_ID_SSIRTI2 (179) /* */
#define INTC_ID_SSII3 (180) /* */
#define INTC_ID_SSIRXI3 (181) /* */
#define INTC_ID_SSITXI3 (182) /* */
#define INTC_ID_SSII4 (183) /* */
#define INTC_ID_SSIRTI4 (184) /* */
#define INTC_ID_SSII5 (185) /* */
#define INTC_ID_SSIRXI5 (186) /* */
#define INTC_ID_SSITXI5 (187) /* */
#define INTC_ID_SPDIFI (188)
#define INTC_ID_TEI0 (189)
#define INTC_ID_RI0 (190) /* */
#define INTC_ID_TI0 (191) /* */
#define INTC_ID_SPI0 (192) /* */
#define INTC_ID_STI0 (193) /* */
#define INTC_ID_NAKI0 (194) /* */
#define INTC_ID_ALI0 (195) /* */
#define INTC_ID_TMOI0 (196) /* */
#define INTC_ID_TEI1 (197) /* */
#define INTC_ID_RI1 (198) /* */
#define INTC_ID_TI1 (199) /* */
#define INTC_ID_SPI1 (200) /* */
#define INTC_ID_STI1 (201) /* */
#define INTC_ID_NAKI1 (202) /* */
#define INTC_ID_ALI1 (203) /* */
#define INTC_ID_TMOI1 (204) /* */
#define INTC_ID_TEI2 (205) /* */
#define INTC_ID_RI2 (206) /* */
#define INTC_ID_TI2 (207) /* */
#define INTC_ID_SPI2 (208) /* */
#define INTC_ID_STI2 (209) /* */
#define INTC_ID_NAKI2 (210) /* */
#define INTC_ID_ALI2 (211) /* */
#define INTC_ID_TMOI2 (212) /* */
#define INTC_ID_TEI3 (213) /* */
#define INTC_ID_RI3 (214) /* */
#define INTC_ID_TI3 (215) /* */
#define INTC_ID_SPI3 (216) /* */
#define INTC_ID_STI3 (217) /* */
#define INTC_ID_NAKI3 (218) /* */
#define INTC_ID_ALI3 (219) /* */
#define INTC_ID_TMOI3 (220) /* */
#define INTC_ID_BRI0 (221)
#define INTC_ID_ERI0 (222) /* */
#define INTC_ID_RXI0 (223) /* */
#define INTC_ID_TXI0 (224) /* */
#define INTC_ID_BRI1 (225) /* */
#define INTC_ID_ERI1 (226) /* */
#define INTC_ID_RXI1 (227) /* */
#define INTC_ID_TXI1 (228) /* */
#define INTC_ID_BRI2 (229) /* */
#define INTC_ID_ERI2 (230) /* */
#define INTC_ID_RXI2 (231) /* */
#define INTC_ID_TXI2 (232) /* */
#define INTC_ID_BRI3 (233) /* */
#define INTC_ID_ERI3 (234) /* */
#define INTC_ID_RXI3 (235) /* */
#define INTC_ID_TXI3 (236) /* */
#define INTC_ID_BRI4 (237) /* */
#define INTC_ID_ERI4 (238) /* */
#define INTC_ID_RXI4 (239) /* */
#define INTC_ID_TXI4 (240) /* */
#define INTC_ID_BRI5 (241) /* */
#define INTC_ID_ERI5 (242) /* */
#define INTC_ID_RXI5 (243) /* */
#define INTC_ID_TXI5 (244) /* */
#define INTC_ID_BRI6 (245) /* */
#define INTC_ID_ERI6 (246) /* */
#define INTC_ID_RXI6 (247) /* */
#define INTC_ID_TXI6 (248) /* */
#define INTC_ID_BRI7 (249) /* */
#define INTC_ID_ERI7 (250) /* */
#define INTC_ID_RXI7 (251) /* */
#define INTC_ID_TXI7 (252) /* */
#define INTC_ID_GERI (253)
#define INTC_ID_RFI (254) /* */
#define INTC_ID_CFRXI0 (255) /* */
#define INTC_ID_CERI0 (256) /* */
#define INTC_ID_CTXI0 (257) /* */
#define INTC_ID_CFRXI1 (258) /* */
#define INTC_ID_CERI1 (259) /* */
#define INTC_ID_CTXI1 (260) /* */
#define INTC_ID_CFRXI2 (261) /* */
#define INTC_ID_CERI2 (262) /* */
#define INTC_ID_CTXI2 (263) /* */
#define INTC_ID_CFRXI3 (264) /* */
#define INTC_ID_CERI3 (265) /* */
#define INTC_ID_CTXI3 (266) /* */
#define INTC_ID_CFRXI4 (267) /* */
#define INTC_ID_CERI4 (268) /* */
#define INTC_ID_CTXI4 (269) /* */
#define INTC_ID_SPEI0 (270)
#define INTC_ID_SPRI0 (271) /* */
#define INTC_ID_SPTI0 (272) /* */
#define INTC_ID_SPEI1 (273) /* */
#define INTC_ID_SPRI1 (274) /* */
#define INTC_ID_SPTI1 (275) /* */
#define INTC_ID_SPEI2 (276) /* */
#define INTC_ID_SPRI2 (277) /* */
#define INTC_ID_SPTI2 (278) /* */
#define INTC_ID_SPEI3 (279) /* */
#define INTC_ID_SPRI3 (280) /* */
#define INTC_ID_SPTI3 (281) /* */
#define INTC_ID_SPEI4 (282) /* */
#define INTC_ID_SPRI4 (283) /* */
#define INTC_ID_SPTI4 (284) /* */
#define INTC_ID_IEBBTD (285)
#define INTC_ID_IEBBTERR (286) /* */
#define INTC_ID_IEBBTSTA (287) /* */
#define INTC_ID_IEBBTV (288) /* */
#define INTC_ID_ISY (289)
#define INTC_ID_IERR (290) /* */
#define INTC_ID_ITARG (291) /* */
#define INTC_ID_ISEC (292) /* */
#define INTC_ID_IBUF (293) /* */
#define INTC_ID_IREADY (294) /* */
#define INTC_ID_FLSTE (295)
#define INTC_ID_FLTENDI (296) /* */
#define INTC_ID_FLTREQ0I (297) /* */
#define INTC_ID_FLTREQ1I (298) /* */
#define INTC_ID_MMC0 (299)
#define INTC_ID_MMC1 (300) /* */
#define INTC_ID_MMC2 (301) /* */
#define INTC_ID_SDHI0_3 (302)
#define INTC_ID_SDHI0_0 (303) /* */
#define INTC_ID_SDHI0_1 (304) /* */
#define INTC_ID_SDHI1_3 (305) /* */
#define INTC_ID_SDHI1_0 (306) /* */
#define INTC_ID_SDHI1_1 (307) /* */
#define INTC_ID_ARM (308)
#define INTC_ID_PRD (309) /* */
#define INTC_ID_CUP (310) /* */
#define INTC_ID_SCUAI0 (311) /* SCUX */
#define INTC_ID_SCUAI1 (312) /* */
#define INTC_ID_SCUFDI0 (313) /* */
#define INTC_ID_SCUFDI1 (314) /* */
#define INTC_ID_SCUFDI2 (315) /* */
#define INTC_ID_SCUFDI3 (316) /* */
#define INTC_ID_SCUFUI0 (317) /* */
#define INTC_ID_SCUFUI1 (318) /* */
#define INTC_ID_SCUFUI2 (319) /* */
#define INTC_ID_SCUFUI3 (320) /* */
#define INTC_ID_SCUDVI0 (321) /* */
#define INTC_ID_SCUDVI1 (322) /* */
#define INTC_ID_SCUDVI2 (323) /* */
#define INTC_ID_SCUDVI3 (324) /* */
#define INTC_ID_MLBCI (325)
#define INTC_ID_MLBSI (326) /* */
#define INTC_ID_DRC0 (327)
#define INTC_ID_DRC1 (328) /* */
#define INTC_ID_LINI0_INT_T (331) /* Renesas LIN3 */
#define INTC_ID_LINI0_INT_R (332) /* */
#define INTC_ID_LINI0_INT_S (333) /* */
#define INTC_ID_LINI0_INT_M (334) /* */
#define INTC_ID_LINI1_INT_T (335) /* */
#define INTC_ID_LINI1_INT_R (336) /* */
#define INTC_ID_LINI1_INT_S (337) /* */
#define INTC_ID_LINI1_INT_M (338) /* */
#define INTC_ID_SCI_ERI0 (347)
#define INTC_ID_SCI_RXI0 (348) /* */
#define INTC_ID_SCI_TXI0 (349) /* */
#define INTC_ID_SCI_TEI0 (350) /* */
#define INTC_ID_SCI_ERI1 (351) /* */
#define INTC_ID_SCI_RXI1 (352) /* */
#define INTC_ID_SCI_TXI1 (353) /* */
#define INTC_ID_SCI_TEI1 (354) /* */
#define INTC_ID_ETHERI (359)
#define INTC_ID_CEUI (364)
#define INTC_ID_H2XMLB_ERRINT (381)
#define INTC_ID_H2XIC1_ERRINT (382) /* */
#define INTC_ID_X2HPERI1_ERRINT (383) /* */
#define INTC_ID_X2HPERI2_ERRINT (384) /* */
#define INTC_ID_X2HPERI34_ERRINT (385) /* */
#define INTC_ID_X2HPERI5_ERRINT (386) /* */
#define INTC_ID_X2HPERI67_ERRINT (387) /* */
#define INTC_ID_X2HDBGR_ERRINT (388) /* */
#define INTC_ID_X2HBSC_ERRINT (389) /* */
#define INTC_ID_X2HSPI1_ERRINT (390) /* */
#define INTC_ID_X2HSPI2_ERRINT (391) /* */
#define INTC_ID_PRRI (392) /* */
#define INTC_ID_IFEI0 (393)
#define INTC_ID_OFFI0 (394) /* */
#define INTC_ID_PFVEI0 (395) /* */
#define INTC_ID_IFEI1 (396) /* */
#define INTC_ID_OFFI1 (397) /* */
#define INTC_ID_PFVEI1 (398) /* */
#define INTC_ID_TINT0 (416)
#define INTC_ID_TINT1 (417) /* */
#define INTC_ID_TINT2 (418) /* */
#define INTC_ID_TINT3 (419) /* */
#define INTC_ID_TINT4 (420) /* */
#define INTC_ID_TINT5 (421) /* */
#define INTC_ID_TINT6 (422) /* */
#define INTC_ID_TINT7 (423) /* */
#define INTC_ID_TINT8 (424) /* */
#define INTC_ID_TINT9 (425) /* */
#define INTC_ID_TINT10 (426) /* */
#define INTC_ID_TINT11 (427) /* */
#define INTC_ID_TINT12 (428) /* */
#define INTC_ID_TINT13 (429) /* */
#define INTC_ID_TINT14 (430) /* */
#define INTC_ID_TINT15 (431) /* */
#define INTC_ID_TINT16 (432) /* */
#define INTC_ID_TINT17 (433) /* */
#define INTC_ID_TINT18 (434) /* */
#define INTC_ID_TINT19 (435) /* */
#define INTC_ID_TINT20 (436) /* */
#define INTC_ID_TINT21 (437) /* */
#define INTC_ID_TINT22 (438) /* */
#define INTC_ID_TINT23 (439) /* */
#define INTC_ID_TINT24 (440) /* */
#define INTC_ID_TINT25 (441) /* */
#define INTC_ID_TINT26 (442) /* */
#define INTC_ID_TINT27 (443) /* */
#define INTC_ID_TINT28 (444) /* */
#define INTC_ID_TINT29 (445) /* */
#define INTC_ID_TINT30 (446) /* */
#define INTC_ID_TINT31 (447) /* */
#define INTC_ID_TINT32 (448) /* */
#define INTC_ID_TINT33 (449) /* */
#define INTC_ID_TINT34 (450) /* */
#define INTC_ID_TINT35 (451) /* */
#define INTC_ID_TINT36 (452) /* */
#define INTC_ID_TINT37 (453) /* */
#define INTC_ID_TINT38 (454) /* */
#define INTC_ID_TINT39 (455) /* */
#define INTC_ID_TINT40 (456) /* */
#define INTC_ID_TINT41 (457) /* */
#define INTC_ID_TINT42 (458) /* */
#define INTC_ID_TINT43 (459) /* */
#define INTC_ID_TINT44 (460) /* */
#define INTC_ID_TINT45 (461) /* */
#define INTC_ID_TINT46 (462) /* */
#define INTC_ID_TINT47 (463) /* */
#define INTC_ID_TINT48 (464) /* */
#define INTC_ID_TINT49 (465) /* */
#define INTC_ID_TINT50 (466) /* */
#define INTC_ID_TINT51 (467) /* */
#define INTC_ID_TINT52 (468) /* */
#define INTC_ID_TINT53 (469) /* */
#define INTC_ID_TINT54 (470) /* */
#define INTC_ID_TINT55 (471) /* */
#define INTC_ID_TINT56 (472) /* */
#define INTC_ID_TINT57 (473) /* */
#define INTC_ID_TINT58 (474) /* */
#define INTC_ID_TINT59 (475) /* */
#define INTC_ID_TINT60 (476) /* */
#define INTC_ID_TINT61 (477) /* */
#define INTC_ID_TINT62 (478) /* */
#define INTC_ID_TINT63 (479) /* */
#define INTC_ID_TINT64 (480) /* */
#define INTC_ID_TINT65 (481) /* */
#define INTC_ID_TINT66 (482) /* */
#define INTC_ID_TINT67 (483) /* */
#define INTC_ID_TINT68 (484) /* */
#define INTC_ID_TINT69 (485) /* */
#define INTC_ID_TINT70 (486) /* */
#define INTC_ID_TINT71 (487) /* */
#define INTC_ID_TINT72 (488) /* */
#define INTC_ID_TINT73 (489) /* */
#define INTC_ID_TINT74 (490) /* */
#define INTC_ID_TINT75 (491) /* */
#define INTC_ID_TINT76 (492) /* */
#define INTC_ID_TINT77 (493) /* */
#define INTC_ID_TINT78 (494) /* */
#define INTC_ID_TINT79 (495) /* */
#define INTC_ID_TINT80 (496) /* */
#define INTC_ID_TINT81 (497) /* */
#define INTC_ID_TINT82 (498) /* */
#define INTC_ID_TINT83 (499) /* */
#define INTC_ID_TINT84 (500) /* */
#define INTC_ID_TINT85 (501) /* */
#define INTC_ID_TINT86 (502) /* */
#define INTC_ID_TINT87 (503) /* */
#define INTC_ID_TINT88 (504) /* */
#define INTC_ID_TINT89 (505) /* */
#define INTC_ID_TINT90 (506) /* */
#define INTC_ID_TINT91 (507) /* */
#define INTC_ID_TINT92 (508) /* */
#define INTC_ID_TINT93 (509) /* */
#define INTC_ID_TINT94 (510) /* */
#define INTC_ID_TINT95 (511) /* */
#define INTC_ID_TINT96 (512) /* */
#define INTC_ID_TINT97 (513) /* */
#define INTC_ID_TINT98 (514) /* */
#define INTC_ID_TINT99 (515) /* */
#define INTC_ID_TINT100 (516) /* */
#define INTC_ID_TINT101 (517) /* */
#define INTC_ID_TINT102 (518) /* */
#define INTC_ID_TINT103 (519) /* */
#define INTC_ID_TINT104 (520) /* */
#define INTC_ID_TINT105 (521) /* */
#define INTC_ID_TINT106 (522) /* */
#define INTC_ID_TINT107 (523) /* */
#define INTC_ID_TINT108 (524) /* */
#define INTC_ID_TINT109 (525) /* */
#define INTC_ID_TINT110 (526) /* */
#define INTC_ID_TINT111 (527) /* */
#define INTC_ID_TINT112 (528) /* */
#define INTC_ID_TINT113 (529) /* */
#define INTC_ID_TINT114 (530) /* */
#define INTC_ID_TINT115 (531) /* */
#define INTC_ID_TINT116 (532) /* */
#define INTC_ID_TINT117 (533) /* */
#define INTC_ID_TINT118 (534) /* */
#define INTC_ID_TINT119 (535) /* */
#define INTC_ID_TINT120 (536) /* */
#define INTC_ID_TINT121 (537) /* */
#define INTC_ID_TINT122 (538) /* */
#define INTC_ID_TINT123 (539) /* */
#define INTC_ID_TINT124 (540) /* */
#define INTC_ID_TINT125 (541) /* */
#define INTC_ID_TINT126 (542) /* */
#define INTC_ID_TINT127 (543) /* */
#define INTC_ID_TINT128 (544) /* */
#define INTC_ID_TINT129 (545) /* */
#define INTC_ID_TINT130 (546) /* */
#define INTC_ID_TINT131 (547) /* */
#define INTC_ID_TINT132 (548) /* */
#define INTC_ID_TINT133 (549) /* */
#define INTC_ID_TINT134 (550) /* */
#define INTC_ID_TINT135 (551) /* */
#define INTC_ID_TINT136 (552) /* */
#define INTC_ID_TINT137 (553) /* */
#define INTC_ID_TINT138 (554) /* */
#define INTC_ID_TINT139 (555) /* */
#define INTC_ID_TINT140 (556) /* */
#define INTC_ID_TINT141 (557) /* */
#define INTC_ID_TINT142 (558) /* */
#define INTC_ID_TINT143 (559) /* */
#define INTC_ID_TINT144 (560) /* */
#define INTC_ID_TINT145 (561) /* */
#define INTC_ID_TINT146 (562) /* */
#define INTC_ID_TINT147 (563) /* */
#define INTC_ID_TINT148 (564) /* */
#define INTC_ID_TINT149 (565) /* */
#define INTC_ID_TINT150 (566) /* */
#define INTC_ID_TINT151 (567) /* */
#define INTC_ID_TINT152 (568) /* */
#define INTC_ID_TINT153 (569) /* */
#define INTC_ID_TINT154 (570) /* */
#define INTC_ID_TINT155 (571) /* */
#define INTC_ID_TINT156 (572) /* */
#define INTC_ID_TINT157 (573) /* */
#define INTC_ID_TINT158 (574) /* */
#define INTC_ID_TINT159 (575) /* */
#define INTC_ID_TINT160 (576) /* */
#define INTC_ID_TINT161 (577) /* */
#define INTC_ID_TINT162 (578) /* */
#define INTC_ID_TINT163 (579) /* */
#define INTC_ID_TINT164 (580) /* */
#define INTC_ID_TINT165 (581) /* */
#define INTC_ID_TINT166 (582) /* */
#define INTC_ID_TINT167 (583) /* */
#define INTC_ID_TINT168 (584) /* */
#define INTC_ID_TINT169 (585) /* */
#define INTC_ID_TINT170 (586) /* */
#define INTC_LEVEL_SENSITIVE (0)
#define INTC_EDGE_TRIGGER (1)
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
int32_t R_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense));
void R_INTC_Init(void);
int32_t R_INTC_Enable(uint16_t int_id);
int32_t R_INTC_Disable(uint16_t int_id);
int32_t R_INTC_SetPriority(uint16_t int_id, uint8_t priority);
int32_t R_INTC_SetMaskLevel(uint8_t mask_level);
void R_INTC_GetMaskLevel(uint8_t * mask_level);
void Userdef_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense));
void Userdef_INTC_UndefId(uint16_t int_id);
void Userdef_INTC_HandlerExe(uint16_t int_id, uint32_t int_sense);
void Userdef_FIQ_HandlerExe(void);
#endif /* _DEVDRV_INTC_H_ */
/* End of File */

69
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_ostm.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : devdrv_ostm.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - OS timer device driver header
******************************************************************************/
#ifndef _DEVDRV_OSTM_H_
#define _DEVDRV_OSTM_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define OSTM_MODE_INTERVAL (0)
#define OSTM_MODE_COMPARE (1)
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
int32_t R_OSTM_Init(uint32_t channel, uint32_t mode, uint32_t cycle);
int32_t R_OSTM_Open(uint32_t channel);
int32_t R_OSTM_Close(uint32_t channel, uint32_t * count);
int32_t R_OSTM_Interrupt(uint32_t channel);
int32_t Userdef_OSTM0_Init(uint32_t mode, uint32_t cycle);
int32_t Userdef_OSTM1_Init(uint32_t mode, uint32_t cycle);
void Userdef_OSTM0_Int(void);
void Userdef_OSTM1_Int(void);
void Userdef_OSTM0_WaitInt(void);
void Userdef_OSTM1_WaitInt(void);
#endif /* _DEVDRV_OSTM_H_ */
/* End of File */

70
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_scif_uart.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : scif_uart.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - SCIF UART device driver header
******************************************************************************/
#ifndef _DEVDRV_SCIF_UART_H_
#define _DEVDRV_SCIF_UART_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "iodefine.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define SCIF_UART_MODE_W (1)
#define SCIF_UART_MODE_R (2)
#define SCIF_UART_MODE_RW (3)
typedef enum scif_cks_division
{
SCIF_CKS_DIVISION_1,
SCIF_CKS_DIVISION_4,
SCIF_CKS_DIVISION_16,
SCIF_CKS_DIVISION_64
} scif_cks_division_t;
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
int32_t R_SCIF_UART_Init(uint32_t channel, uint32_t mode, uint16_t cks, uint8_t scbrr);
void Userdef_SCIF2_UART_Init(uint8_t mode, uint16_t cks, uint8_t scbrr);
#endif /* _DEVDRV_SCIF_UART_H_ */
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefine.h
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324
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/bsc_iodefine.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_iodefine.h
* Version : 0.01
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* ARM Complier
* :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program vecotr.s
*******************************************************************************/
/*******************************************************************************
* History : DD.MM.YYYY Version Description
* : 27.07.2012 0.01 参考資料：sec08_BSC_20120615.doc !!!TOSCORnに仕様書にないビット名あり!!!
*******************************************************************************/
#ifndef __BSC_IODEFINE_H__
#define __BSC_IODEFINE_H__
#include "typedefine.h"
typedef union { /* CSnBCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :9; /* */
_UDWORD BSZ:2; /* BSZ */
_UDWORD :1; /* */
_UDWORD TYPE:3; /* TYPE */
_UDWORD :1; /* */
_UDWORD IWRRS:3; /* IWRRS */
_UDWORD IWRRD:3; /* IWRRD */
_UDWORD IWRWS:3; /* IWRWS */
_UDWORD IWRWD:3; /* IWRWD */
_UDWORD IWW:3; /* IWW */
_UDWORD :1; /* */
} BIT; /* */
} CSnBCR; /* */
typedef union { /* TOSCORn */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD xxx:16; /* xxx */ /* !!!ビット名決定次第、定義する!!! */
_UDWORD :16; /* */
} BIT; /* */
} TOSCORn; /* */
struct st_bsc { /* struct BSC */
union { /* CMNCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD HIZCNT:1; /* HIZCNT */
_UDWORD HIZMEM:1; /* HIZMEM */
_UDWORD :7; /* */
_UDWORD DPRTY:2; /* DPRTY */
_UDWORD :13; /* */
_UDWORD AL0:1; /* AL0 */
_UDWORD :3; /* */
_UDWORD TL0:1; /* TL0 */
_UDWORD :3; /* */
} BIT; /* */
} CMNCR; /* */
CSnBCR CS0BCR; /* CS0BCR */
CSnBCR CS1BCR; /* CS1BCR */
CSnBCR CS2BCR; /* CS2BCR */
CSnBCR CS3BCR; /* CS3BCR */
CSnBCR CS4BCR; /* CS4BCR */
CSnBCR CS5BCR; /* CS5BCR */
_UBYTE wk0[12]; /* */
union { /* CS0WCR */
union { /* CS0WCR(NORMAL) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD HW:2; /* HW */
_UDWORD :4; /* */
_UDWORD WM:1; /* WM */
_UDWORD WR:4; /* WR */
_UDWORD SW:2; /* SW */
_UDWORD :7; /* */
_UDWORD BAS:1; /* BAS */
_UDWORD :11; /* */
} BIT; /* */
} NORMAL; /* */
union { /* CS0WCR(BROM_ASY) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :6; /* */
_UDWORD WM:1; /* WM */
_UDWORD W:4; /* W */
_UDWORD :5; /* */
_UDWORD BW:2; /* BW */
_UDWORD :2; /* */
_UDWORD BST:2; /* BST */
_UDWORD :10; /* */
} BIT; /* */
} BROM_ASY; /* */
union { /* CS0WCR(BROM_SY) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :6; /* */
_UDWORD WM:1; /* WM */
_UDWORD W:4; /* W */
_UDWORD :5; /* */
_UDWORD BW:2; /* BW */
_UDWORD :14; /* */
} BIT; /* */
} BROM_SY; /* */
} CS0WCR; /* */
union { /* CS1WCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD HW:2; /* HW */
_UDWORD :4; /* */
_UDWORD WM:1; /* WM */
_UDWORD WR:4; /* WR */
_UDWORD SW:2; /* SW */
_UDWORD :3; /* */
_UDWORD WW:3; /* WW */
_UDWORD :1; /* */
_UDWORD BAS:1; /* BAS */
_UDWORD :11; /* */
} BIT; /* */
} CS1WCR; /* */
union { /* CS2WCR */
union { /* CS2WCR(NORMAL) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :6; /* */
_UDWORD WM:1; /* WM */
_UDWORD WR:4; /* WR */
_UDWORD :9; /* */
_UDWORD BAS:1; /* BAS */
_UDWORD :11; /* */
} BIT; /* */
} NORMAL; /* */
union { /* CS2WCR(SDRAM) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :7; /* */
_UDWORD A2CL:2; /* A2CL */
_UDWORD :23; /* */
} BIT; /* */
} SDRAM; /* */
} CS2WCR; /* */
union { /* CS3WCR */
union { /* CS3WCR(NORMAL) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :6; /* */
_UDWORD WM:1; /* WM */
_UDWORD WR:4; /* WR */
_UDWORD :9; /* */
_UDWORD BAS:1; /* BAS */
_UDWORD :11; /* */
} BIT; /* */
} NORMAL; /* */
union { /* CS3WCR(SDRAM) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD WTRC:2; /* WTRC */
_UDWORD :1; /* */
_UDWORD TRWL:2; /* TRWL */
_UDWORD :2; /* */
_UDWORD A3CL:2; /* A3CL */
_UDWORD :1; /* */
_UDWORD WTRCD:2; /* WTRCD */
_UDWORD :1; /* */
_UDWORD WTRP:2; /* WTRP */
_UDWORD :17; /* */
} BIT; /* */
} SDRAM; /* */
} CS3WCR; /* */
union { /* CS4WCR */
union { /* CS4WCR(NORMAL) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD HW:2; /* HW */
_UDWORD :4; /* */
_UDWORD WM:1; /* WM */
_UDWORD WR:4; /* WR */
_UDWORD SW:2; /* SW */
_UDWORD :3; /* */
_UDWORD WW:3; /* WW */
_UDWORD :1; /* */
_UDWORD BAS:1; /* BAS */
_UDWORD :11; /* */
} BIT; /* */
} NORMAL; /* */
union { /* CS4WCR(BROM_ASY) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD HW:2; /* HW */
_UDWORD :4; /* */
_UDWORD WM:1; /* WM */
_UDWORD W:4; /* W */
_UDWORD SW:2; /* SW */
_UDWORD :3; /* */
_UDWORD BW:2; /* BW */
_UDWORD :2; /* */
_UDWORD BST:2; /* BST */
_UDWORD :10; /* */
} BIT; /* */
} BROM_ASY; /* */
} CS4WCR; /* */
union { /* CS5WCR */
union { /* CS5WCR(NORMAL) */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD HW:2; /* HW */
_UDWORD :4; /* */
_UDWORD WM:1; /* WM */
_UDWORD WR:4; /* WR */
_UDWORD SW:2; /* SW */
_UDWORD :3; /* */
_UDWORD WW:3; /* WW */
_UDWORD :1; /* */
_UDWORD MPXWBAS:1; /* MPXW/BAS */
_UDWORD SZSEL:1; /* SZSEL */
_UDWORD :10; /* */
} BIT; /* */
} NORMAL; /* */
} CS5WCR; /* */
_UBYTE wk1[12]; /* */
union { /* SDCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD A3COL:2; /* A3COL */
_UDWORD :1; /* */
_UDWORD A3ROW:2; /* A3ROW */
_UDWORD :3; /* */
_UDWORD BACTV:1; /* BACTV */
_UDWORD PDOWN:1; /* PDOWN */
_UDWORD RMODE:1; /* RMODE */
_UDWORD RFSH:1; /* RFSH */
_UDWORD :1; /* */
_UDWORD DEEP:1; /* DEEP */
_UDWORD :2; /* */
_UDWORD A2COL:2; /* A2COL */
_UDWORD :1; /* */
_UDWORD A2ROW:2; /* A2ROW */
_UDWORD :11; /* */
} BIT; /* */
} SDCR; /* */
union { /* RTCSR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD RRC:3; /* RRC */
_UDWORD CKS:3; /* CKS */
_UDWORD CMIE:1; /* CMIE */
_UDWORD CMF:1; /* CMF */
_UDWORD :24; /* */
} BIT; /* */
} RTCSR; /* */
union { /* RTCNT */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD D:32; /* D */
} BIT; /* */
} RTCNT; /* */
union { /* RTCOR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD D:32; /* D */
} BIT; /* */
} RTCOR; /* */
_UBYTE wk2[4]; /* */
TOSCORn TOSCOR0; /* TOSCOR0 */
TOSCORn TOSCOR1; /* TOSCOR1 */
TOSCORn TOSCOR2; /* TOSCOR2 */
TOSCORn TOSCOR3; /* TOSCOR3 */
TOSCORn TOSCOR4; /* TOSCOR4 */
TOSCORn TOSCOR5; /* TOSCOR5 */
_UBYTE wk3[8]; /* */
union { /* TOSTR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CS0TOSTF:1; /* CS0TOSTF */
_UDWORD CS1TOSTF:1; /* CS1TOSTF */
_UDWORD CS2TOSTF:1; /* CS2TOSTF */
_UDWORD CS3TOSTF:1; /* CS3TOSTF */
_UDWORD CS4TOSTF:1; /* CS4TOSTF */
_UDWORD CS5TOSTF:1; /* CS5TOSTF */
_UDWORD :26; /* */
} BIT; /* */
} TOSTR; /* */
union { /* TOENR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CS0TOEN:1; /* CS0TOEN */
_UDWORD CS1TOEN:1; /* CS1TOEN */
_UDWORD CS2TOEN:1; /* CS2TOEN */
_UDWORD CS3TOEN:1; /* CS3TOEN */
_UDWORD CS4TOEN:1; /* CS4TOEN */
_UDWORD CS5TOEN:1; /* CS5TOEN */
_UDWORD :26; /* */
} BIT; /* */
} TOENR; /* */
}; /* */
#define BSC (*(volatile struct st_bsc *)0x3FFFC000) /* BSC Address */
#endif /* __BSC_IODEFINE_H__ */
/* End of File */

463
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/cpg_iodefine.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : cpg_iodefine.h
* Version : 0.01
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* ARM Complier
* :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program vecotr.s
*******************************************************************************/
/*******************************************************************************
* History : DD.MM.YYYY Version Description
* : 27.07.2012 0.01 ŽQ<EFBFBD>lŽ‘—¿<EFBFBD>FRZ_A1H_05J_121010_11.pdf
*******************************************************************************/
#ifndef __CPG_IODEFINE_H__
#define __CPG_IODEFINE_H__
#include "typedefine.h"
struct st_cpg { /* struct CPG */
union { /* FRQCR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD :8; /* */
_UWORD IFC:2; /* IFC */
_UWORD :2; /* */
_UWORD CKOEN:2; /* CKOEN */
_UWORD CKOEN2:1; /* CKOEN2 */
_UWORD :1; /* */
} BIT; /* */
} FRQCR; /* */
_UBYTE wk0[2]; /* */
union { /* FRQCR2 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD GFC:2; /* GFC */
_UWORD :14; /* */
} BIT; /* */
} FRQCR2; /* */
_UBYTE wk1[2]; /* */
union { /* CPUSTS */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :4; /* */
_UBYTE ISBUSY0:1; /* ISBUSY0 */
_UBYTE :3; /* */
} BIT; /* */
} CPUSTS; /* */
_UBYTE wk2[7]; /* */
union { /* STBCR1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :6; /* */
_UBYTE DEEP:1; /* DEEP */
_UBYTE STBY:1; /* STBY */
} BIT; /* */
} STBCR1; /* */
_UBYTE wk3[3]; /* */
union { /* STBCR2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP20:1; /* MSTP20 */
_UBYTE :6; /* */
_UBYTE HIZ:1; /* HIZ */
} BIT; /* */
} STBCR2; /* */
_UBYTE wk4[11]; /* */
union { /* STBREQ1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE STBRQ10:1; /* STBRQ10 */
_UBYTE :2; /* */
_UBYTE STBRQ13:1; /* STBRQ13 */
_UBYTE :1; /* */
_UBYTE STBRQ15:1; /* STBRQ15 */
_UBYTE :2; /* */
} BIT; /* */
} STBREQ1; /* */
_UBYTE wk5[3]; /* */
union { /* STBREQ2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE STBRQ20:1; /* STBRQ20 */
_UBYTE STBRQ21:1; /* STBRQ21 */
_UBYTE STBRQ22:1; /* STBRQ22 */
_UBYTE STBRQ23:1; /* STBRQ23 */
_UBYTE STBRQ24:1; /* STBRQ24 */
_UBYTE STBRQ25:1; /* STBRQ25 */
_UBYTE STBRQ26:1; /* STBRQ26 */
_UBYTE STBRQ27:1; /* STBRQ27 */
} BIT; /* */
} STBREQ2; /* */
_UBYTE wk6[11]; /* */
union { /* STBACK1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE STBAK10:1; /* STBAK10 */
_UBYTE :2; /* */
_UBYTE STBAK13:1; /* STBAK13 */
_UBYTE :1; /* */
_UBYTE STBAK15:1; /* STBAK15 */
_UBYTE :2; /* */
} BIT; /* */
} STBACK1; /* */
_UBYTE wk7[3]; /* */
union { /* STBACK2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE STBAK20:1; /* STBAK20 */
_UBYTE STBAK21:1; /* STBAK21 */
_UBYTE STBAK22:1; /* STBAK22 */
_UBYTE STBAK23:1; /* STBAK23 */
_UBYTE STBAK24:1; /* STBAK24 */
_UBYTE STBAK25:1; /* STBAK25 */
_UBYTE STBAK26:1; /* STBAK26 */
_UBYTE STBAK27:1; /* STBAK27 */
} BIT; /* */
} STBACK2; /* */
_UBYTE wk8[955]; /* */
union { /* SYSCR1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE VRAME0:1; /* VRAME0 */
_UBYTE VRAME1:1; /* VRAME1 */
_UBYTE VRAME2:1; /* VRAME2 */
_UBYTE VRAME3:1; /* VRAME3 */
_UBYTE VRAME4:1; /* VRAME4 */
_UBYTE :3; /* */
} BIT; /* */
} SYSCR1; /* */
_UBYTE wk9[3]; /* */
union { /* SYSCR2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE VRAMWE0:1; /* VRAMWE0 */
_UBYTE VRAMWE1:1; /* VRAMWE1 */
_UBYTE VRAMWE2:1; /* VRAMWE2 */
_UBYTE VRAMWE3:1; /* VRAMWE3 */
_UBYTE VRAMWE4:1; /* VRAMWE4 */
_UBYTE :3; /* */
} BIT; /* */
} SYSCR2; /* */
_UBYTE wk10[3]; /* */
union { /* SYSCR3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE RRAMWE0:1; /* RRAMWE0 */
_UBYTE RRAMWE1:1; /* RRAMWE1 */
_UBYTE RRAMWE2:1; /* RRAMWE2 */
_UBYTE RRAMWE3:1; /* RRAMWE3 */
_UBYTE :4; /* */
} BIT; /* */
} SYSCR3; /* */
_UBYTE wk11[23]; /* */
union { /* STBCR3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP30:1; /* MSTP30 */
_UBYTE :1; /* */
_UBYTE MSTP32:1; /* MSTP32 */
_UBYTE MSTP33:1; /* MSTP33 */
_UBYTE MSTP34:1; /* MSTP34 */
_UBYTE MSTP35:1; /* MSTP35 */
_UBYTE MSTP36:1; /* MSTP36 */
_UBYTE MSTP37:1; /* MSTP37 */
} BIT; /* */
} STBCR3; /* */
_UBYTE wk12[3]; /* */
union { /* STBCR4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP40:1; /* MSTP40 */
_UBYTE MSTP41:1; /* MSTP41 */
_UBYTE MSTP42:1; /* MSTP42 */
_UBYTE MSTP43:1; /* MSTP43 */
_UBYTE MSTP44:1; /* MSTP44 */
_UBYTE MSTP45:1; /* MSTP45 */
_UBYTE MSTP46:1; /* MSTP46 */
_UBYTE MSTP47:1; /* MSTP47 */
} BIT; /* */
} STBCR4; /* */
_UBYTE wk13[3]; /* */
union { /* STBCR5 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP50:1; /* MSTP50 */
_UBYTE MSTP51:1; /* MSTP51 */
_UBYTE MSTP52:1; /* MSTP52 */
_UBYTE MSTP53:1; /* MSTP53 */
_UBYTE MSTP54:1; /* MSTP54 */
_UBYTE MSTP55:1; /* MSTP55 */
_UBYTE MSTP56:1; /* MSTP56 */
_UBYTE MSTP57:1; /* MSTP57 */
} BIT; /* */
} STBCR5; /* */
_UBYTE wk14[3]; /* */
union { /* STBCR6 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP60:1; /* MSTP60 */
_UBYTE MSTP61:1; /* MSTP61 */
_UBYTE MSTP62:1; /* MSTP62 */
_UBYTE MSTP63:1; /* MSTP63 */
_UBYTE MSTP64:1; /* MSTP64 */
_UBYTE MSTP65:1; /* MSTP65 */
_UBYTE MSTP66:1; /* MSTP66 */
_UBYTE MSTP67:1; /* MSTP67 */
} BIT; /* */
} STBCR6; /* */
_UBYTE wk15[3]; /* */
union { /* STBCR7 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP70:1; /* MSTP70 */
_UBYTE MSTP71:1; /* MSTP71 */
_UBYTE :1; /* */
_UBYTE MSTP73:1; /* MSTP73 */
_UBYTE MSTP74:1; /* MSTP74 */
_UBYTE :1; /* */
_UBYTE MSTP76:1; /* MSTP76 */
_UBYTE MSTP77:1; /* MSTP77 */
} BIT; /* */
} STBCR7; /* */
_UBYTE wk16[3]; /* */
union { /* STBCR8 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :1; /* */
_UBYTE MSTP81:1; /* MSTP81 */
_UBYTE :1; /* */
_UBYTE MSTP83:1; /* MSTP83 */
_UBYTE MSTP84:1; /* MSTP84 */
_UBYTE MSTP85:1; /* MSTP85 */
_UBYTE MSTP86:1; /* MSTP86 */
_UBYTE MSTP87:1; /* MSTP87 */
} BIT; /* */
} STBCR8; /* */
_UBYTE wk17[3]; /* */
union { /* STBCR9 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP90:1; /* MSTP60 */
_UBYTE MSTP91:1; /* MSTP61 */
_UBYTE MSTP92:1; /* MSTP62 */
_UBYTE MSTP93:1; /* MSTP63 */
_UBYTE MSTP94:1; /* MSTP64 */
_UBYTE MSTP95:1; /* MSTP65 */
_UBYTE MSTP96:1; /* MSTP66 */
_UBYTE MSTP97:1; /* MSTP67 */
} BIT; /* */
} STBCR9; /* */
_UBYTE wk18[3]; /* */
union { /* STBCR10 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP100:1; /* MSTP100 */
_UBYTE MSTP101:1; /* MSTP101 */
_UBYTE MSTP102:1; /* MSTP102 */
_UBYTE MSTP103:1; /* MSTP103 */
_UBYTE MSTP104:1; /* MSTP104 */
_UBYTE MSTP105:1; /* MSTP105 */
_UBYTE MSTP106:1; /* MSTP106 */
_UBYTE MSTP107:1; /* MSTP107 */
} BIT; /* */
} STBCR10; /* */
_UBYTE wk19[3]; /* */
union { /* STBCR11 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP110:1; /* MSTP110 */
_UBYTE MSTP111:1; /* MSTP111 */
_UBYTE MSTP112:1; /* MSTP112 */
_UBYTE MSTP113:1; /* MSTP113 */
_UBYTE MSTP114:1; /* MSTP114 */
_UBYTE MSTP115:1; /* MSTP115 */
_UBYTE :2; /* */
} BIT; /* */
} STBCR11; /* */
_UBYTE wk20[3]; /* */
union { /* STBCR12 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MSTP120:1; /* MSTP120 */
_UBYTE MSTP121:1; /* MSTP121 */
_UBYTE MSTP122:1; /* MSTP122 */
_UBYTE MSTP123:1; /* MSTP123 */
_UBYTE :4; /* */
} BIT; /* */
} STBCR12; /* */
_UBYTE wk21[27]; /* */
union { /* SWRSTCR1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :1; /* */
_UBYTE SRST11:1; /* SRST11 */
_UBYTE SRST12:1; /* SRST12 */
_UBYTE SRST13:1; /* SRST13 */
_UBYTE SRST14:1; /* SRST14 */
_UBYTE SRST15:1; /* SRST15 */
_UBYTE SRST16:1; /* SRST16 */
_UBYTE AXTALE:1; /* AXTALE */
} BIT; /* */
} SWRSTCR1; /* */
_UBYTE wk22[3]; /* */
union { /* SWRSTCR2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :1; /* */
_UBYTE SRST21:1; /* SRST21 */
_UBYTE SRST22:1; /* SRST22 */
_UBYTE SRST23:1; /* SRST23 */
_UBYTE SRST24:1; /* SRST24 */
_UBYTE SRST25:1; /* SRST25 */
_UBYTE SRST26:1; /* SRST26 */
_UBYTE SRST27:1; /* SRST27 */
} BIT; /* */
} SWRSTCR2; /* */
_UBYTE wk23[3]; /* */
union { /* SWRSTCR3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :1; /* */
_UBYTE SRST31:1; /* SRST31 */
_UBYTE SRST32:1; /* SRST32 */
_UBYTE SRST33:1; /* SRST33 */
_UBYTE SRST34:1; /* SRST34 */
_UBYTE SRST35:1; /* SRST35 */
_UBYTE SRST36:1; /* SRST36 */
_UBYTE :1; /* */
} BIT; /* */
} SWRSTCR3; /* */
_UBYTE wk24[3]; /* */
union { /* SWRSTCR4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE SRST40:1; /* SRST40 */
_UBYTE SRST41:1; /* SRST41 */
_UBYTE :6; /* */
} BIT; /* */
} SWRSTCR4; /* */
_UBYTE wk25[70547]; /* */
union { /* RRAMKP */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE RRAMKP0:1; /* RRAMKP0 */
_UBYTE RRAMKP1:1; /* RRAMKP1 */
_UBYTE RRAMKP2:1; /* RRAMKP2 */
_UBYTE RRAMKP3:1; /* RRAMKP3 */
_UBYTE :4; /* */
} BIT; /* */
} RRAMKP; /* */
_UBYTE wk26[1]; /* */
union { /* DSCTR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE :6; /* */
_UBYTE RAMBOOT:1; /* RAMBOOT */
_UBYTE EBUSKEEPE:1; /* EBUSKEEPE */
} BIT; /* */
} DSCTR; /* */
_UBYTE wk27[1]; /* */
union { /* DSSSR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD P8_2:1; /* P8_2 */
_UWORD P9_1:1; /* P9_1 */
_UWORD P2_15:1; /* P2_15 */
_UWORD P7_8:1; /* P7_8 */
_UWORD P5_9:1; /* P5_9 */
_UWORD P6_4:1; /* P6_4 */
_UWORD RTCAR:1; /* RTCAR */
_UWORD :1; /* */
_UWORD NMI:1; /* NMI */
_UWORD P3_3:1; /* P3_3 */
_UWORD P8_7:1; /* P8_7 */
_UWORD P2_12:1; /* P2_12 */
_UWORD P3_1:1; /* P3_1 */
_UWORD P3_9:1; /* P3_9 */
_UWORD P6_2:1; /* P6_2 */
_UWORD :1; /* */
} BIT; /* */
} DSSSR; /* */
union { /* DSESR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD P8_2E:1; /* P8_2E */
_UWORD P9_1E:1; /* P9_1E */
_UWORD P2_15E:1; /* P2_15E */
_UWORD P7_8E:1; /* P7_8E */
_UWORD P5_9E:1; /* P5_9E */
_UWORD P6_4E:1; /* P6_4E */
_UWORD :2; /* */
_UWORD NMIE:1; /* NMIE */
_UWORD P3_3E:1; /* P3_3E */
_UWORD P8_7E:1; /* P8_7E */
_UWORD P2_12E:1; /* P2_12E */
_UWORD P3_1E:1; /* P3_1E */
_UWORD P3_9E:1; /* P3_9E */
_UWORD P6_2E:1; /* P6_2E */
_UWORD :1; /* */
} BIT; /* */
} DSESR; /* */
union { /* DSFR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD P8_2F:1; /* P8_2F */
_UWORD P9_1F:1; /* P9_1F */
_UWORD P2_15F:1; /* P2_15F */
_UWORD P7_8F:1; /* P7_8F */
_UWORD P5_9F:1; /* P5_9F */
_UWORD P6_4F:1; /* P6_4F */
_UWORD RTCARF:1; /* RTCARF */
_UWORD :1; /* */
_UWORD NMIF:1; /* NMIF */
_UWORD P3_3F:1; /* P3_3F */
_UWORD P8_7F:1; /* P8_7F */
_UWORD P2_12F:1; /* P2_12F */
_UWORD P3_1F:1; /* P3_1F */
_UWORD P3_9F:1; /* P3_9F */
_UWORD P6_2F:1; /* P6_2F */
_UWORD IOKEEP:1; /* IOKEEP */
} BIT; /* */
} DSFR; /* */
_UBYTE wk28[6]; /* */
union { /* XTALCTR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE GAIN0:1; /* GAIN0 */
_UBYTE GAIN1:1; /* GAIN1 */
_UBYTE :6; /* */
} BIT; /* */
} XTALCTR; /* */
}; /* */
#define CPG (*(volatile struct st_cpg *)0xFCFE0010) /* CPG Address */
#endif /* __CPG_IODEFINE_H__ */
/* End of File */

510
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/dmac_iodefine.h
Unescape Escape View File

@ -0,0 +1,510 @@
/******************************************************************************
* DISCLAIMER
*
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized.
*
* This software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
* DISCLAIMED.
*
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
*
* Renesas reserves the right, without notice, to make changes to this
* software and to discontinue the availability of this software.
* By using this software, you agree to the additional terms and
* conditions found by accessing the following link:
* http://www.renesas.com/disclaimer
********************************************************************************
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
**************************** Technical reference data **************************
* System Name :
* File Name : dmac_iodefine.h
* Abstract :
* Version : 1.00.00
* Device : ARM
* Tool-Chain :
* OS : None
* H/W Platform:
* Description :
********************************************************************************
* History : Mar.06,2012 Ver.1.00.00
*******************************************************************************/
#ifndef __DMAC_IODEFINE_H__
#define __DMAC_IODEFINE_H__
#include "typedefine.h"
struct st_dmac_n { /* struct DMAC */
union { /* N0SA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SA:32; /* SA */
} BIT; /* */
} N0SA; /* */
union { /* N0DA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD DA:32; /* DA */
} BIT; /* */
} N0DA; /* */
union { /* N0TB */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TB:32; /* TB */
} BIT; /* */
} N0TB; /* */
union { /* N1SA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SA:32; /* SA */
} BIT; /* */
} N1SA; /* */
union { /* N1DA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD DA:32; /* DA */
} BIT; /* */
} N1DA; /* */
union { /* N1TB */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TB:32; /* TB */
} BIT; /* */
} N1TB; /* */
union { /* CRSA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CRSA:32; /* CRSA */
} BIT; /* */
} CRSA; /* */
union { /* CRDA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CRDA:32; /* CRDA */
} BIT; /* */
} CRDA; /* */
union { /* CRTB */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CRTB:32; /* CRTB */
} BIT; /* */
} CRTB; /* */
union { /* CHSTAT */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD EN:1; /* EN */
_UDWORD RQST:1; /* RQST */
_UDWORD TACT:1; /* TACT */
_UDWORD SUS:1; /* SUS */
_UDWORD ER:1; /* ER */
_UDWORD END:1; /* END */
_UDWORD TC:1; /* TC */
_UDWORD SR:1; /* SR */
_UDWORD DL:1; /* DL */
_UDWORD DW:1; /* DW */
_UDWORD DER:1; /* DER */
_UDWORD MODE:1; /* MODE */
_UWORD :4; /* */
_UDWORD INTMSK:1; /* INTMSK */
_UWORD :15; /* */
} BIT; /* */
} CHSTAT; /* */
union { /* CHCTRL */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SETEN:1; /* SETEN */
_UDWORD CLREN:1; /* CLREN */
_UDWORD STG:1; /* STG */
_UDWORD SWRST:1; /* SWRST */
_UDWORD CLRRQ:1; /* CLRRQ */
_UDWORD CLREND:1; /* CLREND */
_UDWORD CLRTC:1; /* CLRTC */
_UWORD :1; /* */
_UDWORD SETSUS:1; /* SETSUS */
_UDWORD CLRSUS:1; /* CLRSUS */
_UWORD :6; /* */
_UDWORD SETINTMSK:1; /* SETINTMSK */
_UDWORD CLRINTMSK:1; /* CLRINTMSK */
_UWORD :14; /* */
} BIT; /* */
} CHCTRL; /* */
union { /* CHCFG */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SEL:3; /* SEL */
_UDWORD REQD:1; /* REQD */
_UDWORD LOEN:1; /* LOEN */
_UDWORD HIEN:1; /* HIEN */
_UDWORD LVL:1; /* LVL */
_UWORD :1; /* */
_UDWORD AM:3; /* AM */
_UWORD :1; /* */
_UDWORD SDS:4; /* SDS */
_UDWORD DDS:4; /* DDS */
_UDWORD SAD:1; /* SAD */
_UDWORD DAD:1; /* DAD */
_UDWORD TM:1; /* TM */
_UWORD :1; /* */
_UDWORD DEM:1; /* DEM */
_UDWORD TCM:1; /* TCM */
_UWORD :1; /* */
_UDWORD SBE:1; /* SBE */
_UDWORD RSEL:1; /* RSEL */
_UDWORD RSW:1; /* RSW */
_UDWORD REN:1; /* REN */
_UDWORD DMS:1; /* DMS */
} BIT; /* */
} CHCFG; /* */
union { /* CHITVL */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ITVL:16; /* ITVL */
_UWORD :16; /* */
} BIT; /* */
} CHITVL; /* */
union { /* CHEXT */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UWORD :4; /* */
_UDWORD SCA:4; /* SCA */
_UWORD :4; /* */
_UDWORD DCA:4; /* DCA */
_UWORD :16; /* */
} CHEXT; /* */
} CHEXT; /* */
union { /* NXLA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD NXLA:32; /* NXLA */
} BIT; /* */
} NXLA; /* */
union { /* CRLA */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CRLA:32; /* CRLA */
} BIT; /* */
} CRLA; /* */
}; /* */
struct st_dmac_07 { /* struct DMAC */
union { /* DCTRL */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD PR:1; /* PR */
_UDWORD LVINT:1; /* LVINT */
_UWORD :18; /* */
_UDWORD LDCA:4; /* LDCA */
_UWORD :4; /* */
_UDWORD LWCA:4; /* LWCA */
} BIT; /* */
} DCTRL; /* */
union { /* DSTAT_EN */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD EN0:1; /* EN0 */
_UDWORD EN1:1; /* EN1 */
_UDWORD EN2:1; /* EN2 */
_UDWORD EN3:1; /* EN3 */
_UDWORD EN4:1; /* EN4 */
_UDWORD EN5:1; /* EN5 */
_UDWORD EN6:1; /* EN6 */
_UDWORD EN7:1; /* EN7 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_EN; /* */
union { /* DSTAT_ER */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ER0:1; /* ER0 */
_UDWORD ER1:1; /* ER1 */
_UDWORD ER2:1; /* ER2 */
_UDWORD ER3:1; /* ER3 */
_UDWORD ER4:1; /* ER4 */
_UDWORD ER5:1; /* ER5 */
_UDWORD ER6:1; /* ER6 */
_UDWORD ER7:1; /* ER7 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_ER; /* */
union { /* DSTAT_END */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD END0:1; /* END0 */
_UDWORD END1:1; /* END1 */
_UDWORD END2:1; /* END2 */
_UDWORD END3:1; /* END3 */
_UDWORD END4:1; /* END4 */
_UDWORD END5:1; /* END5 */
_UDWORD END6:1; /* END6 */
_UDWORD END7:1; /* END7 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_END; /* */
union { /* DSTAT_TC */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TC0:1; /* TC0 */
_UDWORD TC1:1; /* TC1 */
_UDWORD TC2:1; /* TC2 */
_UDWORD TC3:1; /* TC3 */
_UDWORD TC4:1; /* TC4 */
_UDWORD TC5:1; /* TC5 */
_UDWORD TC6:1; /* TC6 */
_UDWORD TC7:1; /* TC7 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_TC; /* */
union { /* DSTAT_SUS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SUS0:1; /* SUS0 */
_UDWORD SUS1:1; /* SUS1 */
_UDWORD SUS2:1; /* SUS2 */
_UDWORD SUS3:1; /* SUS3 */
_UDWORD SUS4:1; /* SUS4 */
_UDWORD SUS5:1; /* SUS5 */
_UDWORD SUS6:1; /* SUS6 */
_UDWORD SUS7:1; /* SUS7 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_SUS; /* */
}; /* */
struct st_dmac_815 { /* struct DMAC */
union { /* DCTRL */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD PR:1; /* PR */
_UDWORD LVINT:1; /* LVINT */
_UWORD :18; /* */
_UDWORD LDCA:4; /* LDCA */
_UWORD :4; /* */
_UDWORD LWCA:4; /* LWCA */
} BIT; /* */
} DCTRL; /* */
union { /* DSTAT_EN */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD EN8:1; /* EN8 */
_UDWORD EN9:1; /* EN9 */
_UDWORD EN10:1; /* EN10 */
_UDWORD EN11:1; /* EN11 */
_UDWORD EN12:1; /* EN12 */
_UDWORD EN13:1; /* EN13 */
_UDWORD EN14:1; /* EN14 */
_UDWORD EN15:1; /* EN15 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_EN; /* */
union { /* DSTAT_ER */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ER8:1; /* ER8 */
_UDWORD ER9:1; /* ER9 */
_UDWORD ER10:1; /* ER10 */
_UDWORD ER11:1; /* ER11 */
_UDWORD ER12:1; /* ER12 */
_UDWORD ER13:1; /* ER13 */
_UDWORD ER14:1; /* ER14 */
_UDWORD ER15:1; /* ER15 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_ER; /* */
union { /* DSTAT_END */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD END8:1; /* END8 */
_UDWORD END9:1; /* END9 */
_UDWORD END10:1; /* END10 */
_UDWORD END11:1; /* END11 */
_UDWORD END12:1; /* END12 */
_UDWORD END13:1; /* END13 */
_UDWORD END14:1; /* END14 */
_UDWORD END15:1; /* END15 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_END; /* */
union { /* DSTAT_TC */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TC8:1; /* TC8 */
_UDWORD TC9:1; /* TC9 */
_UDWORD TC10:1; /* TC10 */
_UDWORD TC11:1; /* TC11 */
_UDWORD TC12:1; /* TC12 */
_UDWORD TC13:1; /* TC13 */
_UDWORD TC14:1; /* TC14 */
_UDWORD TC15:1; /* TC15 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_TC; /* */
union { /* DSTAT_SUS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SUS8:1; /* SUS8 */
_UDWORD SUS9:1; /* SUS9 */
_UDWORD SUS10:1; /* SUS10 */
_UDWORD SUS11:1; /* SUS11 */
_UDWORD SUS12:1; /* SUS12 */
_UDWORD SUS13:1; /* SUS13 */
_UDWORD SUS14:1; /* SUS14 */
_UDWORD SUS15:1; /* SUS15 */
_UWORD :24; /* */
} BIT; /* */
} DSTAT_SUS; /* */
}; /* */
struct st_dmac_01 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH0_RID:2; /* CH0_RID */
_UDWORD CH0_MID:7; /* CH0_MID */
_UWORD :7; /* */
_UDWORD CH1_RID:2; /* CH1_RID */
_UDWORD CH1_MID:7; /* CH1_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_23 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH2_RID:2; /* CH2_RID */
_UDWORD CH2_MID:7; /* CH2_MID */
_UWORD :7; /* */
_UDWORD CH3_RID:2; /* CH3_RID */
_UDWORD CH3_MID:7; /* CH3_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_45 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH4_RID:2; /* CH4_RID */
_UDWORD CH4_MID:7; /* CH4_MID */
_UWORD :7; /* */
_UDWORD CH5_RID:2; /* CH5_RID */
_UDWORD CH5_MID:7; /* CH5_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_67 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH6_RID:2; /* CH6_RID */
_UDWORD CH6_MID:7; /* CH6_MID */
_UWORD :7; /* */
_UDWORD CH7_RID:2; /* CH7_RID */
_UDWORD CH7_MID:7; /* CH7_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_89 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH8_RID:2; /* CH8_RID */
_UDWORD CH8_MID:7; /* CH8_MID */
_UWORD :7; /* */
_UDWORD CH9_RID:2; /* CH9_RID */
_UDWORD CH9_MID:7; /* CH9_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_1011 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH10_RID:2; /* CH10_RID */
_UDWORD CH10_MID:7; /* CH10_MID */
_UWORD :7; /* */
_UDWORD CH11_RID:2; /* CH11_RID */
_UDWORD CH11_MID:7; /* CH11_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_1213 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH12_RID:2; /* CH12_RID */
_UDWORD CH12_MID:7; /* CH12_MID */
_UWORD :7; /* */
_UDWORD CH13_RID:2; /* CH13_RID */
_UDWORD CH13_MID:7; /* CH13_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
struct st_dmac_1415 { /* struct DMAC */
union { /* DMARS */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CH14_RID:2; /* CH14_RID */
_UDWORD CH14_MID:7; /* CH14_MID */
_UWORD :7; /* */
_UDWORD CH15_RID:2; /* CH15_RID */
_UDWORD CH15_MID:7; /* CH15_MID */
_UWORD :7; /* */
} BIT; /* */
} DMARS; /* */
}; /* */
#define DMAC0 (*(volatile struct st_dmac_n *)0xE8200000) /* DMAC0 Address */
#define DMAC1 (*(volatile struct st_dmac_n *)0xE8200040) /* DMAC1 Address */
#define DMAC2 (*(volatile struct st_dmac_n *)0xE8200080) /* DMAC2 Address */
#define DMAC3 (*(volatile struct st_dmac_n *)0xE82000C0) /* DMAC3 Address */
#define DMAC4 (*(volatile struct st_dmac_n *)0xE8200100) /* DMAC4 Address */
#define DMAC5 (*(volatile struct st_dmac_n *)0xE8200140) /* DMAC5 Address */
#define DMAC6 (*(volatile struct st_dmac_n *)0xE8200180) /* DMAC6 Address */
#define DMAC7 (*(volatile struct st_dmac_n *)0xE82001C0) /* DMAC7 Address */
#define DMAC8 (*(volatile struct st_dmac_n *)0xE8200400) /* DMAC8 Address */
#define DMAC9 (*(volatile struct st_dmac_n *)0xE8200440) /* DMAC9 Address */
#define DMAC10 (*(volatile struct st_dmac_n *)0xE8200480) /* DMAC10 Address */
#define DMAC11 (*(volatile struct st_dmac_n *)0xE82004C0) /* DMAC11 Address */
#define DMAC12 (*(volatile struct st_dmac_n *)0xE8200500) /* DMAC12 Address */
#define DMAC13 (*(volatile struct st_dmac_n *)0xE8200540) /* DMAC13 Address */
#define DMAC14 (*(volatile struct st_dmac_n *)0xE8200580) /* DMAC14 Address */
#define DMAC15 (*(volatile struct st_dmac_n *)0xE82005C0) /* DMAC15 Address */
#define DMAC07 (*(volatile struct st_dmac_07 *)0xE8200300) /* DMAC0-7 Address */
#define DMAC815 (*(volatile struct st_dmac_815 *)0xE8200700) /* DMAC8-15 Address */
#define DMAC01 (*(volatile struct st_dmac_01 *)0xFCFE1000) /* DMAC0-1 Address */
#define DMAC23 (*(volatile struct st_dmac_23 *)0xFCFE1004) /* DMAC2-3 Address */
#define DMAC45 (*(volatile struct st_dmac_45 *)0xFCFE1008) /* DMAC4-5 Address */
#define DMAC67 (*(volatile struct st_dmac_67 *)0xFCFE100C) /* DMAC6-7 Address */
#define DMAC89 (*(volatile struct st_dmac_89 *)0xFCFE1010) /* DMAC8-9 Address */
#define DMAC1011 (*(volatile struct st_dmac_1011 *)0xFCFE1014) /* DMAC10-11 Address */
#define DMAC1213 (*(volatile struct st_dmac_1213 *)0xFCFE1018) /* DMAC12-13 Address */
#define DMAC1415 (*(volatile struct st_dmac_1415 *)0xFCFE101C) /* DMAC14-15 Address */
#endif /* __DMAC_IODEFINE_H__ */
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/intc_iodefine.h
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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/mtu2_iodefine.h
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@ -0,0 +1,715 @@
/******************************************************************************
* DISCLAIMER
*
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized.
*
* This software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
* DISCLAIMED.
*
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
*
* Renesas reserves the right, without notice, to make changes to this
* software and to discontinue the availability of this software.
* By using this software, you agree to the additional terms and
* conditions found by accessing the following link:
* http://www.renesas.com/disclaimer
********************************************************************************
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
**************************** Technical reference data **************************
* System Name :
* File Name : mtu2_iodefine.h
* Abstract :
* Version : 1.00.00
* Device : ARM
* Tool-Chain :
* OS : None
* H/W Platform:
* Description :
********************************************************************************
* History : Jan.11,2013 Ver.1.00.00
*******************************************************************************/
#ifndef __MTU2_IODEFINE_H__
#define __MTU2_IODEFINE_H__
#include "typedefine.h"
struct st_mtu2{ /* struct MTU2 */
union { /* TCR_2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TPSC:3; /* TPSC */
_UBYTE CKEG:2; /* CKEG */
_UBYTE CCLR:2; /* CCLR */
_UBYTE :1;
} BIT; /* */
} TCR_2; /* */
union { /* TMDR_2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MD:4; /* MD */
_UBYTE :4; /* */
} BIT; /* */
} TMDR_2; /* */
union { /* TIOR_2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOA:4; /* IOA */
_UBYTE IOB:4; /* IOB */
} BIT; /* */
} TIOR_2; /* */
_UBYTE wk0[1]; /* */
union { /* TIER_2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGIEA:1; /* TGIEA */
_UBYTE TGIEB:1; /* TGIEB */
_UBYTE :2; /* */
_UBYTE TCIEV:1; /* TCIEV */
_UBYTE TCIEU:1; /* TCIEU */
_UBYTE :1; /* */
_UBYTE TTGE:1; /* TTGE */
} BIT; /* */
} TIER_2; /* */
union { /* TSR_2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGFA:1; /* TGFA */
_UBYTE TGFB:1; /* TGFB */
_UBYTE :1; /* */
_UBYTE :1; /* */
_UBYTE TCFV:1; /* TCFV */
_UBYTE TCFU:1; /* TCFU */
_UBYTE :1; /* */
_UBYTE TCFD:1; /* TCFD */
} BIT; /* */
} TSR_2; /* */
union { /* TCNT_2 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCNT_2; /* */
union { /* TGRA_2 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRA_2; /* */
union { /* TGRB_2 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRB_2; /* */
_UBYTE wk1[500]; /* */
union { /* TCR_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TPSC:3; /* TPSC */
_UBYTE CKEG:2; /* CKEG */
_UBYTE CCLR:3; /* CCLR */
} BIT; /* */
} TCR_3; /* */
union { /* TCR_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TPSC:3; /* TPSC */
_UBYTE CKEG:2; /* CKEG */
_UBYTE CCLR:3; /* CCLR */
} BIT; /* */
} TCR_4; /* */
union { /* TMDR_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MD:4; /* MD */
_UBYTE BFA:1; /* BFA */
_UBYTE BFB:1; /* BFB */
_UBYTE :2; /* */
} BIT; /* */
} TMDR_3; /* */
union { /* TMDR_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MD:4; /* MD */
_UBYTE BFA:1; /* BFA */
_UBYTE BFB:1; /* BFB */
_UBYTE :2; /* */
} BIT; /* */
} TMDR_4; /* */
union { /* TIORH_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOA:4; /* IOA */
_UBYTE IOB:4; /* IOB */
} BIT; /* */
} TIORH_3; /* */
union { /* TIORL_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOC:4; /* IOC */
_UBYTE IOD:4; /* IOD */
} BIT; /* */
} TIORL_3; /* */
union { /* TIORH_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOA:4; /* IOA */
_UBYTE IOB:4; /* IOB */
} BIT; /* */
} TIORH_4; /* */
union { /* TIORL_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOC:4; /* IOC */
_UBYTE IOD:4; /* IOD */
} BIT; /* */
} TIORL_4; /* */
union { /* TIER_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGIEA:1; /* TGIEA */
_UBYTE TGIEB:1; /* TGIEB */
_UBYTE TGIEC:1; /* TGIEC */
_UBYTE TGIED:1; /* TGIED */
_UBYTE TCIEV:1; /* TCIEV */
_UBYTE :2; /* */
_UBYTE TTGE:1; /* TTGE */
} BIT; /* */
} TIER_3; /* */
union { /* TIER_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGIEA:1; /* TGIEA */
_UBYTE TGIEB:1; /* TGIEB */
_UBYTE TGIEC:1; /* TGIEC */
_UBYTE TGIED:1; /* TGIED */
_UBYTE TCIEV:1; /* TCIEV */
_UBYTE :1; /* */
_UBYTE TTGE2:1; /* TTGE2 */
_UBYTE TTGE:1; /* TTGE */
} BIT; /* */
} TIER_4; /* */
union { /* TOER */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OE3B:1; /* OE3B */
_UBYTE OE4A:1; /* OE4A */
_UBYTE OE4B:1; /* OE4B */
_UBYTE OE3D:1; /* OE3D */
_UBYTE OE4C:1; /* OE4C */
_UBYTE OE4D:1; /* OE4D */
_UBYTE :2; /* */
} BIT; /* */
} TOER; /* */
_UBYTE wk2[2]; /* */
union { /* TGCR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE UF:1; /* UF */
_UBYTE VF:1; /* VF */
_UBYTE WF:1; /* WF */
_UBYTE FB:1; /* FB */
_UBYTE P:1; /* P */
_UBYTE N:1; /* N */
_UBYTE BDC:1; /* BDC */
_UBYTE :1; /* */
} BIT; /* */
} TGCR; /* */
union { /* TOCR1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OLSP:1; /* OLSP */
_UBYTE OLSN:1; /* OLSN */
_UBYTE TOCS:1; /* TOCS */
_UBYTE TOCL:1; /* TOCL */
_UBYTE :2; /* */
_UBYTE PSYE:1; /* PSYE */
_UBYTE :1; /* */
} BIT; /* */
} TOCR1; /* */
union { /* TOCR2 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OLS1P:1; /* OLS1P */
_UBYTE OLS1N:1; /* OLS1N */
_UBYTE OLS2P:1; /* OLS2P */
_UBYTE OLS2N:1; /* OLS2N */
_UBYTE OLS3P:1; /* OLS3P */
_UBYTE OLS3N:1; /* OLS3N */
_UBYTE BF:2; /* BF */
} BIT; /* */
} TOCR2; /* */
union { /* TCNT_3 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCNT_3; /* */
union { /* TCNT_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCNT_4; /* */
union { /* TCDR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCDR; /* */
union { /* TDDR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TDDR; /* */
union { /* TGRA_3 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRA_3; /* */
union { /* TGRB_3 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRB_3; /* */
union { /* TGRA_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRA_4; /* */
union { /* TGRB_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRB_4; /* */
union { /* TCNTS */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCNTS; /* */
union { /* TCBR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCBR; /* */
union { /* TGRC_3 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRC_3; /* */
union { /* TGRD_3 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRD_3; /* */
union { /* TGRC_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRC_4; /* */
union { /* TGRD_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRD_4; /* */
union { /* TSR_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGFA:1; /* TGFA */
_UBYTE TGFB:1; /* TGFB */
_UBYTE TGFC:1; /* TGFC */
_UBYTE TGFD:1; /* TGFD */
_UBYTE TCFV:1; /* TCFV */
_UBYTE :2; /* */
_UBYTE TCFD:1; /* TCFD */
} BIT; /* */
} TSR_3; /* */
union { /* TSR_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGFA:1; /* TGFA */
_UBYTE TGFB:1; /* TGFB */
_UBYTE TGFC:1; /* TGFC */
_UBYTE TGFD:1; /* TGFD */
_UBYTE TCFV:1; /* TCFV */
_UBYTE :2; /* */
_UBYTE TCFD:1; /* TCFD */
} BIT; /* */
} TSR_4; /* */
_UBYTE wk3[2]; /* */
union { /* TITCR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE _4VCOR:3; /* _4VCOR */
_UBYTE T4VEN:1; /* T4VEN */
_UBYTE _3ACOR:3; /* _3ACOR */
_UBYTE T3AEN:1; /* T3AEN */
} BIT; /* */
} TITCR; /* */
union { /* TITCNT */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE _4VCNT:3; /* _4VCNT */
_UBYTE :1; /* */
_UBYTE _3ACNT:3; /* _3ACNT */
_UBYTE :1; /* */
} BIT; /* */
} TITCNT; /* */
union { /* TBTER */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE BTE:2; /* BTE */
_UBYTE :6; /* */
} BIT; /* */
} TBTER; /* */
_UBYTE wk4[1]; /* */
union { /* TDER */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TDER:1; /* TDER */
_UBYTE :7; /* */
} BIT; /* */
} TDER; /* */
_UBYTE wk5[1]; /* */
union { /* TOLBR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OLS1P:1; /* OLS1P */
_UBYTE OLS1N:1; /* OLS1N */
_UBYTE OLS2P:1; /* OLS2P */
_UBYTE OLS2N:1; /* OLS2N */
_UBYTE OLS3P:1; /* OLS3P */
_UBYTE OLS3N:1; /* OLS3N */
_UBYTE :2; /* */
} BIT; /* */
} TOLBR; /* */
_UBYTE wk6[1]; /* */
union { /* TBTM_3 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TTSA:1; /* TTSA */
_UBYTE TTSB:1; /* TTSB */
_UBYTE :6; /* */
} BIT; /* */
} TBTM_3; /* */
union { /* TBTM_4 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TTSA:1; /* TTSA */
_UBYTE TTSB:1; /* TTSB */
_UBYTE :6; /* */
} BIT; /* */
} TBTM_4; /* */
_UBYTE wk7[6]; /* */
union { /* TADCR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD ITB4VE:1; /* ITB4VE */
_UWORD ITB3AE:1; /* ITB3AE */
_UWORD ITA4VE:1; /* ITA4VE */
_UWORD ITA3AE:1; /* ITA3AE */
_UWORD DT4BE:1; /* DT4BE */
_UWORD UT4BE:1; /* UT4BE */
_UWORD DT4AE:1; /* DT4AE */
_UWORD UT4AE:1; /* UT4AE */
_UWORD :6; /* */
_UWORD BF:2; /* BF */
} BIT; /* */
} TADCR; /* */
_UBYTE wk8[2]; /* */
union { /* TADCORA_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TADCORA_4; /* */
union { /* TADCORB_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TADCORB_4; /* */
union { /* TADCOBRA_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TADCOBRA_4; /* */
union { /* TADCOBRB_4 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TADCOBRB_4; /* */
_UBYTE wk9[20]; /* */
union { /* TWCR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE WRE:1; /* WRE */
_UBYTE :6; /* */
_UBYTE CCE:1; /* CCE */
} BIT; /* */
} TWCR; /* */
_UBYTE wk10[31]; /* */
union { /* TSTR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE CST0:1; /* CST0 */
_UBYTE CST1:1; /* CST1 */
_UBYTE CST2:1; /* CST2 */
_UBYTE :3; /* */
_UBYTE CST3:1; /* CST3 */
_UBYTE CST4:1; /* CST4 */
} BIT; /* */
} TSTR; /* */
union { /* TSYR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE SYNC0:1; /* SYNC0 */
_UBYTE SYNC1:1; /* SYNC1 */
_UBYTE SYNC2:1; /* SYNC2 */
_UBYTE :3; /* */
_UBYTE SYNC3:1; /* SYNC3 */
_UBYTE SYNC4:1; /* SYNC4 */
} BIT; /* */
} TSYR; /* */
_UBYTE wk11[2]; /* */
union { /* TRWER */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE RWE:1; /* RWE */
_UBYTE :7; /* */
} BIT; /* */
} TRWER; /* */
_UBYTE wk12[123]; /* */
union { /* TCR_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TPSC:3; /* TPSC */
_UBYTE CKEG:2; /* CKEG */
_UBYTE CCLR:3; /* CCLR */
} BIT; /* */
} TCR_0; /* */
union { /* TMDR_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MD:4; /* MD */
_UBYTE BFA:1; /* BFA */
_UBYTE BFB:1; /* BFB */
_UBYTE BFE:1; /* BFE */
_UBYTE :1; /* */
} BIT; /* */
} TMDR_0; /* */
union { /* TIORH_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOA:4; /* IOA */
_UBYTE IOB:4; /* IOB */
} BIT; /* */
} TIORH_0; /* */
union { /* TIORL_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOC:4; /* IOC */
_UBYTE IOD:4; /* IOD */
} BIT; /* */
} TIORL_0; /* */
union { /* TIER_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGIEA:1; /* TGIEA */
_UBYTE TGIEB:1; /* TGIEB */
_UBYTE TGIEC:1; /* TGIEC */
_UBYTE TGIED:1; /* TGIED */
_UBYTE TCIEV:1; /* TCIEV */
_UBYTE :2; /* */
_UBYTE TTGE:1; /* TTGE */
} BIT; /* */
} TIER_0; /* */
union { /* TSR_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGFA:1; /* TGFA */
_UBYTE TGFB:1; /* TGFB */
_UBYTE TGFC:1; /* TGFC */
_UBYTE TGFD:1; /* TGFD */
_UBYTE TCFV:1; /* TCFV */
_UBYTE :3; /* */
} BIT; /* */
} TSR_0; /* */
union { /* TCNT_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCNT_0; /* */
union { /* TGRA_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRA_0; /* */
union { /* TGRB_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRB_0; /* */
union { /* TGRC_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRC_0; /* */
union { /* TGRD_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRD_0; /* */
_UBYTE wk13[16]; /* */
union { /* TGRE_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRE_0; /* */
union { /* TGRF_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRF_0; /* */
union { /* TIER2_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGIEE:1; /* TGIEE */
_UBYTE TGIEF:1; /* TGIEF */
_UBYTE :5; /* */
_UBYTE TTGE2:1; /* TTGE2 */
} BIT; /* */
} TIER2_0; /* */
union { /* TSR2_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGFE:1; /* TGFE */
_UBYTE TGFF:1; /* TGFF */
_UBYTE :6; /* */
} BIT; /* */
} TSR2_0; /* */
union { /* TBTM_0 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TTSA:1; /* TTSA */
_UBYTE TTSB:1; /* TTSB */
_UBYTE TTSE:1; /* TTSE */
_UBYTE :5; /* */
} BIT; /* */
} TBTM_0; /* */
_UBYTE wk14[89]; /* */
union { /* TCR_1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TPSC:3; /* TPSC */
_UBYTE CKEG:2; /* CKEG */
_UBYTE CCLR:2; /* CCLR */
_UBYTE :1;
} BIT; /* */
} TCR_1; /* */
union { /* TMDR_1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE MD:4; /* MD */
_UBYTE :4; /* */
} BIT; /* */
} TMDR_1; /* */
union { /* TIOR_1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE IOA:4; /* IOA */
_UBYTE IOB:4; /* IOB */
} BIT; /* */
} TIOR_1; /* */
_UBYTE wk15[1]; /* */
union { /* TIER_1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGIEA:1; /* TGIEA */
_UBYTE TGIEB:1; /* TGIEB */
_UBYTE :2; /* */
_UBYTE TCIEV:1; /* TCIEV */
_UBYTE TCIEU:1; /* TCIEU */
_UBYTE :1; /* */
_UBYTE TTGE:1; /* TTGE */
} BIT; /* */
} TIER_1; /* */
union { /* TSR_1 */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE TGFA:1; /* TGFA */
_UBYTE TGFB:1; /* TGFB */
_UBYTE :2; /* */
_UBYTE TCFV:1; /* TCFV */
_UBYTE TCFU:1; /* TCFU */
_UBYTE :1; /* */
_UBYTE TCFD:1; /* TCFD */
} BIT; /* */
} TSR_1; /* */
union { /* TCNT_1 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TCNT_1; /* */
union { /* TGRA_1 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRA_1; /* */
union { /* TGRB_1 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD D:16; /* D */
} BIT; /* */
} TGRB_1; /* */
_UBYTE wk16[4]; /* */
union { /* TICCR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE I1AE:1; /* I1AE */
_UBYTE I1BE:1; /* I1BE */
_UBYTE I2AE:1; /* I2AE */
_UBYTE I2BE:1; /* I2BE */
_UBYTE :4; /* */
} BIT; /* */
} TICCR; /* */
}; /* */
#define MTU2 (*(volatile struct st_mtu2 *)0xFCFF0000) /* MTU2 Address */
#endif /* __MTU2_IODEFINE_H__ */
/* End of File */

87
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/ostm_iodefine.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_iodefine.h
* Version : 0.01
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* ARM Complier
* :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program vecotr.s
*******************************************************************************/
/*******************************************************************************
* History : DD.MM.YYYY Version Description
* : 27.07.2012 0.01 ŽQ<EFBFBD>lŽ‘—¿<EFBFBD>Fsec11_OSTM_120601.pdf
*******************************************************************************/
#ifndef __OSTM_IODEFINE_H__
#define __OSTM_IODEFINE_H__
#include "typedefine.h"
struct st_ostm_n { /* struct OSTM */
_UDWORD OSTMnCMP; /* OSTMnCMP */
_UDWORD OSTMnCNT; /* OSTMnCNT */
_UBYTE wk0[8]; /* */
union { /* OSTMnTE */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OSTMnTE:1; /* OSTMnTE */
_UBYTE :7; /* */
} BIT; /* */
} OSTMnTE; /* */
_UBYTE wk1[3]; /* */
union { /* OSTMnTS */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OSTMnTS:1; /* OSTMnTS */
_UBYTE :7; /* */
} BIT; /* */
} OSTMnTS; /* */
_UBYTE wk2[3]; /* */
union { /* OSTMnTT */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OSTMnTT:1; /* OSTMnTT */
_UBYTE :7; /* */
} BIT; /* */
} OSTMnTT; /* */
_UBYTE wk3[7]; /* */
union { /* OSTMnCTL */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE OSTMnMD0:1; /* OSTMnMD0 */
_UBYTE OSTMnMD1:1; /* OSTMnMD1 */
_UBYTE :6; /* */
} BIT; /* */
} OSTMnCTL; /* */
}; /* */
#define OSTM0 (*(volatile struct st_ostm_n *)0xFCFEC000) /* OSTM0 Address */
#define OSTM1 (*(volatile struct st_ostm_n *)0xFCFEC400) /* OSTM1 Address */
#endif /* __OSTM_IODEFINE_H__ */
/* End of File */

436
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/pfc_iodefine.h
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/******************************************************************************
* DISCLAIMER
*
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized.
*
* This software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
* DISCLAIMED.
*
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
*
* Renesas reserves the right, without notice, to make changes to this
* software and to discontinue the availability of this software.
* By using this software, you agree to the additional terms and
* conditions found by accessing the following link:
* http://www.renesas.com/disclaimer
********************************************************************************
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
**************************** Technical reference data **************************
* System Name :
* File Name : pfc_iodefine.h
* Abstract :
* Version : 1.00.00
* Device : ARM
* Tool-Chain :
* OS : None
* H/W Platform:
* Description :
********************************************************************************
* History : Mar.06,2012 Ver.1.00.00
*******************************************************************************/
#ifndef __PFC_IODEFINE_H__
#define __PFC_IODEFINE_H__
#include "typedefine.h"
struct st_pfc_n { /* struct PFC */
union { /* Pn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD Pn0:1; /* */
_UWORD Pn1:1; /* */
_UWORD Pn2:1; /* */
_UWORD Pn3:1; /* */
_UWORD Pn4:1; /* */
_UWORD Pn5:1; /* */
_UWORD Pn6:1; /* */
_UWORD Pn7:1; /* */
_UWORD Pn8:1; /* */
_UWORD Pn9:1; /* */
_UWORD Pn10:1; /* */
_UWORD Pn11:1; /* */
_UWORD Pn12:1; /* */
_UWORD Pn13:1; /* */
_UWORD Pn14:1; /* */
_UWORD Pn15:1; /* */
} BIT; /* */
} Pn; /* */
_UBYTE wk0[0x100-2]; /* */
union { /* PSRn */
_UDWORD LONG; /* Long Access */
struct { /* WORD Access */
_UDWORD ENABLE:16; /* */
_UDWORD SET:16; /* */
} SET;
struct { /* Bit Access */
_UDWORD PSRn0:1; /* */
_UDWORD PSRn1:1; /* */
_UDWORD PSRn2:1; /* */
_UDWORD PSRn3:1; /* */
_UDWORD PSRn4:1; /* */
_UDWORD PSRn5:1; /* */
_UDWORD PSRn6:1; /* */
_UDWORD PSRn7:1; /* */
_UDWORD PSRn8:1; /* */
_UDWORD PSRn9:1; /* */
_UDWORD PSRn10:1; /* */
_UDWORD PSRn11:1; /* */
_UDWORD PSRn12:1; /* */
_UDWORD PSRn13:1; /* */
_UDWORD PSRn14:1; /* */
_UDWORD PSRn15:1; /* */
_UDWORD PSRn16:1; /* */
_UDWORD PSRn17:1; /* */
_UDWORD PSRn18:1; /* */
_UDWORD PSRn19:1; /* */
_UDWORD PSRn20:1; /* */
_UDWORD PSRn21:1; /* */
_UDWORD PSRn22:1; /* */
_UDWORD PSRn23:1; /* */
_UDWORD PSRn24:1; /* */
_UDWORD PSRn25:1; /* */
_UDWORD PSRn26:1; /* */
_UDWORD PSRn27:1; /* */
_UDWORD PSRn28:1; /* */
_UDWORD PSRn29:1; /* */
_UDWORD PSRn30:1; /* */
_UDWORD PSRn31:1; /* */
} BIT; /* */
} PSRn; /* */
_UBYTE wk1[0x100-4]; /* */
union { /* PPRn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PPRn0:1; /* */
_UWORD PPRn1:1; /* */
_UWORD PPRn2:1; /* */
_UWORD PPRn3:1; /* */
_UWORD PPRn4:1; /* */
_UWORD PPRn5:1; /* */
_UWORD PPRn6:1; /* */
_UWORD PPRn7:1; /* */
_UWORD PPRn8:1; /* */
_UWORD PPRn9:1; /* */
_UWORD PPRn10:1; /* */
_UWORD PPRn11:1; /* */
_UWORD PPRn12:1; /* */
_UWORD PPRn13:1; /* */
_UWORD PPRn14:1; /* */
_UWORD PPRn15:1; /* */
} BIT; /* */
} PPRn; /* */
_UBYTE wk2[0x100-2]; /* */
union { /* PMn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PMn0:1; /* */
_UWORD PMn1:1; /* */
_UWORD PMn2:1; /* */
_UWORD PMn3:1; /* */
_UWORD PMn4:1; /* */
_UWORD PMn5:1; /* */
_UWORD PMn6:1; /* */
_UWORD PMn7:1; /* */
_UWORD PMn8:1; /* */
_UWORD PMn9:1; /* */
_UWORD PMn10:1; /* */
_UWORD PMn11:1; /* */
_UWORD PMn12:1; /* */
_UWORD PMn13:1; /* */
_UWORD PMn14:1; /* */
_UWORD PMn15:1; /* */
} BIT; /* */
} PMn; /* */
_UBYTE wk3[0x100-2]; /* */
union { /* PMCn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PMCn0:1; /* */
_UWORD PMCn1:1; /* */
_UWORD PMCn2:1; /* */
_UWORD PMCn3:1; /* */
_UWORD PMCn4:1; /* */
_UWORD PMCn5:1; /* */
_UWORD PMCn6:1; /* */
_UWORD PMCn7:1; /* */
_UWORD PMCn8:1; /* */
_UWORD PMCn9:1; /* */
_UWORD PMCn10:1; /* */
_UWORD PMCn11:1; /* */
_UWORD PMCn12:1; /* */
_UWORD PMCn13:1; /* */
_UWORD PMCn14:1; /* */
_UWORD PMCn15:1; /* */
} BIT; /* */
} PMCn; /* */
_UBYTE wk4[0x100-2]; /* */
union { /* PFCn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PFCn0:1; /* */
_UWORD PFCn1:1; /* */
_UWORD PFCn2:1; /* */
_UWORD PFCn3:1; /* */
_UWORD PFCn4:1; /* */
_UWORD PFCn5:1; /* */
_UWORD PFCn6:1; /* */
_UWORD PFCn7:1; /* */
_UWORD PFCn8:1; /* */
_UWORD PFCn9:1; /* */
_UWORD PFCn10:1; /* */
_UWORD PFCn11:1; /* */
_UWORD PFCn12:1; /* */
_UWORD PFCn13:1; /* */
_UWORD PFCn14:1; /* */
_UWORD PFCn15:1; /* */
} BIT; /* */
} PFCn; /* */
_UBYTE wk5[0x100-2]; /* */
union { /* PFCEn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PFCEn0:1; /* */
_UWORD PFCEn1:1; /* */
_UWORD PFCEn2:1; /* */
_UWORD PFCEn3:1; /* */
_UWORD PFCEn4:1; /* */
_UWORD PFCEn5:1; /* */
_UWORD PFCEn6:1; /* */
_UWORD PFCEn7:1; /* */
_UWORD PFCEn8:1; /* */
_UWORD PFCEn9:1; /* */
_UWORD PFCEn10:1; /* */
_UWORD PFCEn11:1; /* */
_UWORD PFCEn12:1; /* */
_UWORD PFCEn13:1; /* */
_UWORD PFCEn14:1; /* */
_UWORD PFCEn15:1; /* */
} BIT; /* */
} PFCEn; /* */
_UBYTE wk6[0x100-2]; /* */
union { /* PNOTn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PNOTn0:1; /* */
_UWORD PNOTn1:1; /* */
_UWORD PNOTn2:1; /* */
_UWORD PNOTn3:1; /* */
_UWORD PNOTn4:1; /* */
_UWORD PNOTn5:1; /* */
_UWORD PNOTn6:1; /* */
_UWORD PNOTn7:1; /* */
_UWORD PNOTn8:1; /* */
_UWORD PNOTn9:1; /* */
_UWORD PNOTn10:1; /* */
_UWORD PNOTn11:1; /* */
_UWORD PNOTn12:1; /* */
_UWORD PNOTn13:1; /* */
_UWORD PNOTn14:1; /* */
_UWORD PNOTn15:1; /* */
} BIT; /* */
} PNOTn; /* */
_UBYTE wk7[0x100-2]; /* */
union { /* PMSRn */
_UDWORD LONG; /* Long Access */
struct { /* WORD Access */
_UDWORD ENABLE:16; /* */
_UDWORD SET:16; /* */
} SET;
struct { /* Bit Access */
_UDWORD PMSRn0:1; /* */
_UDWORD PMSRn1:1; /* */
_UDWORD PMSRn2:1; /* */
_UDWORD PMSRn3:1; /* */
_UDWORD PMSRn4:1; /* */
_UDWORD PMSRn5:1; /* */
_UDWORD PMSRn6:1; /* */
_UDWORD PMSRn7:1; /* */
_UDWORD PMSRn8:1; /* */
_UDWORD PMSRn9:1; /* */
_UDWORD PMSRn10:1; /* */
_UDWORD PMSRn11:1; /* */
_UDWORD PMSRn12:1; /* */
_UDWORD PMSRn13:1; /* */
_UDWORD PMSRn14:1; /* */
_UDWORD PMSRn15:1; /* */
_UDWORD PMSRn16:1; /* */
_UDWORD PMSRn17:1; /* */
_UDWORD PMSRn18:1; /* */
_UDWORD PMSRn19:1; /* */
_UDWORD PMSRn20:1; /* */
_UDWORD PMSRn21:1; /* */
_UDWORD PMSRn22:1; /* */
_UDWORD PMSRn23:1; /* */
_UDWORD PMSRn24:1; /* */
_UDWORD PMSRn25:1; /* */
_UDWORD PMSRn26:1; /* */
_UDWORD PMSRn27:1; /* */
_UDWORD PMSRn28:1; /* */
_UDWORD PMSRn29:1; /* */
_UDWORD PMSRn30:1; /* */
_UDWORD PMSRn31:1; /* */
} BIT; /* */
} PMSRn; /* */
_UBYTE wk8[0x100-4]; /* */
union { /* PMCSRn */
_UDWORD LONG; /* Long Access */
struct { /* WORD Access */
_UDWORD ENABLE:16; /* */
_UDWORD SET:16; /* */
} SET;
struct { /* Bit Access */
_UDWORD PMCSRn0:1; /* */
_UDWORD PMCSRn1:1; /* */
_UDWORD PMCSRn2:1; /* */
_UDWORD PMCSRn3:1; /* */
_UDWORD PMCSRn4:1; /* */
_UDWORD PMCSRn5:1; /* */
_UDWORD PMCSRn6:1; /* */
_UDWORD PMCSRn7:1; /* */
_UDWORD PMCSRn8:1; /* */
_UDWORD PMCSRn9:1; /* */
_UDWORD PMCSRn10:1; /* */
_UDWORD PMCSRn11:1; /* */
_UDWORD PMCSRn12:1; /* */
_UDWORD PMCSRn13:1; /* */
_UDWORD PMCSRn14:1; /* */
_UDWORD PMCSRn15:1; /* */
_UDWORD PMCSRn16:1; /* */
_UDWORD PMCSRn17:1; /* */
_UDWORD PMCSRn18:1; /* */
_UDWORD PMCSRn19:1; /* */
_UDWORD PMCSRn20:1; /* */
_UDWORD PMCSRn21:1; /* */
_UDWORD PMCSRn22:1; /* */
_UDWORD PMCSRn23:1; /* */
_UDWORD PMCSRn24:1; /* */
_UDWORD PMCSRn25:1; /* */
_UDWORD PMCSRn26:1; /* */
_UDWORD PMCSRn27:1; /* */
_UDWORD PMCSRn28:1; /* */
_UDWORD PMCSRn29:1; /* */
_UDWORD PMCSRn30:1; /* */
_UDWORD PMCSRn31:1; /* */
} BIT; /* */
} PMCSRn; /* */
_UBYTE wk9[0x100-4]; /* */
union { /* PFACEn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PFCAEn0:1; /* */
_UWORD PFCAEn1:1; /* */
_UWORD PFCAEn2:1; /* */
_UWORD PFCAEn3:1; /* */
_UWORD PFCAEn4:1; /* */
_UWORD PFCAEn5:1; /* */
_UWORD PFCAEn6:1; /* */
_UWORD PFCAEn7:1; /* */
_UWORD PFCAEn8:1; /* */
_UWORD PFCAEn9:1; /* */
_UWORD PFCAEn10:1; /* */
_UWORD PFCAEn11:1; /* */
_UWORD PFCAEn12:1; /* */
_UWORD PFCAEn13:1; /* */
_UWORD PFCAEn14:1; /* */
_UWORD PFCAEn15:1; /* */
} BIT; /* */
} PFCAEn; /* */
_UBYTE wk10[0x4000-0xa00-2]; /* */
union { /* PIBCn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PIBCn0:1; /* */
_UWORD PIBCn1:1; /* */
_UWORD PIBCn2:1; /* */
_UWORD PIBCn3:1; /* */
_UWORD PIBCn4:1; /* */
_UWORD PIBCn5:1; /* */
_UWORD PIBCn6:1; /* */
_UWORD PIBCn7:1; /* */
_UWORD PIBCn8:1; /* */
_UWORD PIBCn9:1; /* */
_UWORD PIBCn10:1; /* */
_UWORD PIBCn11:1; /* */
_UWORD PIBCn12:1; /* */
_UWORD PIBCn13:1; /* */
_UWORD PIBCn14:1; /* */
_UWORD PIBCn15:1; /* */
} BIT; /* */
} PIBCn; /* */
_UBYTE wk11[0x100-2]; /* */
union { /* PBDCn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PBDCn0:1; /* */
_UWORD PBDCn1:1; /* */
_UWORD PBDCn2:1; /* */
_UWORD PBDCn3:1; /* */
_UWORD PBDCn4:1; /* */
_UWORD PBDCn5:1; /* */
_UWORD PBDCn6:1; /* */
_UWORD PBDCn7:1; /* */
_UWORD PBDCn8:1; /* */
_UWORD PBDCn9:1; /* */
_UWORD PBDCn10:1; /* */
_UWORD PBDCn11:1; /* */
_UWORD PBDCn12:1; /* */
_UWORD PBDCn13:1; /* */
_UWORD PBDCn14:1; /* */
_UWORD PBDCn15:1; /* */
} BIT; /* */
} PBDCn; /* */
_UBYTE wk12[0x100-2]; /* */
union { /* PIPCn */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD PIPCn0:1; /* */
_UWORD PIPCn1:1; /* */
_UWORD PIPCn2:1; /* */
_UWORD PIPCn3:1; /* */
_UWORD PIPCn4:1; /* */
_UWORD PIPCn5:1; /* */
_UWORD PIPCn6:1; /* */
_UWORD PIPCn7:1; /* */
_UWORD PIPCn8:1; /* */
_UWORD PIPCn9:1; /* */
_UWORD PIPCn10:1; /* */
_UWORD PIPCn11:1; /* */
_UWORD PIPCn12:1; /* */
_UWORD PIPCn13:1; /* */
_UWORD PIPCn14:1; /* */
_UWORD PIPCn15:1; /* */
} BIT; /* */
} PIPCn; /* */
_UBYTE wk13[0x100-2]; /* */
}; /* */
#define PORTn_BASE 0xFCFE3000
#define PORT0 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 0))) /* PORT 0 Address */
#define PORT1 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 1))) /* PORT 1 Address */
#define PORT2 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 2))) /* PORT 2 Address */
#define PORT3 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 3))) /* PORT 3 Address */
#define PORT4 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 4))) /* PORT 4 Address */
#define PORT5 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 5))) /* PORT 5 Address */
#define PORT6 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 6))) /* PORT 6 Address */
#define PORT7 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 7))) /* PORT 7 Address */
#define PORT8 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 8))) /* PORT 8 Address */
#define PORT9 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 9))) /* PORT 9 Address */
#define PORT10 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 10))) /* PORT 10 Address */
#define PORT11 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 11))) /* PORT 11 Address */
#endif /* __PFC_IODEFINE_H__ */
/* End of File */

469
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/prr_iodefine.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : prr_iodefine.h
* Version : 0.01
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* ARM Complier
* :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program vecotr.s
*******************************************************************************/
/*******************************************************************************
* History : DD.MM.YYYY Version Description
* : 27.07.2012 0.01 参考資料：Aragon_PRR120614.xls !!!BSIDの内容が仕様書にない!!!
*******************************************************************************/
#ifndef __PRR_IODEFINE_H__
#define __PRR_IODEFINE_H__
#include "typedefine.h"
struct st_prr { /* struct PRR */
union { /* MDR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD BTMD:3; /* BTMD */
_UDWORD :1; /* */
_UDWORD BTTEST:1; /* BTTEST */
_UDWORD :1; /* */
_UDWORD SEC:1; /* SEC */
_UDWORD SELFEWP:1; /* SELFEWP */
_UDWORD RAMBOOT:1; /* RAMBOOT */
_UDWORD :23; /* */
} BIT; /* */
} MDR; /* */
union { /* BSID */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD dummy:32; /* */ /* !!!ビット決定次第、定義する!!! */
} BIT; /* */
} BSID; /* */
union { /* ECCRR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ECCEN:1; /* ECCEN */
_UDWORD :31; /* */
} BIT; /* */
} ECCRR; /* */
_UBYTE wk0[276]; /* */
union { /* SEMRn */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SEMF:1; /* SEMF */
_UDWORD :31; /* */
} BIT; /* */
} SEMRn[32]; /* */
_UBYTE wk1[96]; /* */
union { /* RMPR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD AXI64:1; /* AXI64 */
_UDWORD AXI128:1; /* AXI128 */
_UDWORD :30; /* */
} BIT; /* */
} RMPR; /* */
union { /* AXIBUSCTL0 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ETHAWCACHE:4; /* ETHAWCACHE */
_UDWORD :4; /* */
_UDWORD ETHARCACHE:4; /* ETHARCACHE */
_UDWORD :4; /* */
_UDWORD JCUAWCACHE:4; /* JCUAWCACHE */
_UDWORD :4; /* */
_UDWORD JCUARCACHE:4; /* JCUARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL0; /* */
union { /* AXIBUSCTL1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD IMR21AWCACHE:4; /* IMR21AWCACHE */
_UDWORD :4; /* */
_UDWORD IMR21ARCACHE:4; /* IMR21ARCACHE */
_UDWORD :4; /* */
_UDWORD IMR20AWCACHE:4; /* IMR20AWCACHE */
_UDWORD :4; /* */
_UDWORD IMR20ARCACHE:4; /* IMR20ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL1; /* */
union { /* AXIBUSCTL2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD CEUAWCACHE:4; /* CEUAWCACHE */
_UDWORD :4; /* */
_UDWORD CEUARCACHE:4; /* CEUARCACHE */
_UDWORD :4; /* */
_UDWORD IMRDAWCACHE:4; /* IMRDAWCACHE */
_UDWORD :4; /* */
_UDWORD IMRDARCACHE:4; /* IMRDARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL2; /* */
union { /* AXIBUSCTL3 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD RGP641AWCACHE:4; /* RGP641AWCACHE */
_UDWORD :4; /* */
_UDWORD RGP641ARCACHE:4; /* RGP641ARCACHE */
_UDWORD :4; /* */
_UDWORD RGP640AWCACHE:4; /* RGP640AWCACHE */
_UDWORD :4; /* */
_UDWORD RGP640ARCACHE:4; /* RGP640ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL3; /* */
union { /* AXIBUSCTL4 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD RGP1280AWCACHE:4; /* RGP1280AWCACHE */
_UDWORD :4; /* */
_UDWORD RGP1280ARCACHE:4; /* RGP1280ARCACHE */
_UDWORD :4; /* */
_UDWORD RGP642AWCACHE:4; /* RGP642AWCACHE */
_UDWORD :4; /* */
_UDWORD RGP642ARCACHE:4; /* RGP642ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL4; /* */
union { /* AXIBUSCTL5 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD MLB_AxCACHE:2; /* MLB_AxCACHE */
_UDWORD :14; /* */
_UDWORD RGP1281AWCACHE:4; /* RGP1281AWCACHE */
_UDWORD :4; /* */
_UDWORD RGP1281ARCACHE:4; /* RGP1281ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL5; /* */
union { /* AXIBUSCTL6 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :8; /* */
_UDWORD VDC502ARCACHE:4; /* VDC502ARCACHE */
_UDWORD :4; /* */
_UDWORD VDC501AWCACHE:4; /* VDC501AWCACHE */
_UDWORD :4; /* */
_UDWORD VDC501ARCACHE:4; /* VDC501ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL6; /* */
union { /* AXIBUSCTL7 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :8; /* */
_UDWORD VDC504ARCACHE:4; /* VDC504ARCACHE */
_UDWORD :4; /* */
_UDWORD VDC503AWCACHE:4; /* VDC503AWCACHE */
_UDWORD :4; /* */
_UDWORD VDC503ARCACHE:4; /* VDC503ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL7; /* */
union { /* AXIBUSCTL8 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD VDC511AWCACHE:4; /* VDC511AWCACHE */
_UDWORD :4; /* */
_UDWORD VDC511ARCACHE:4; /* VDC511ARCACHE */
_UDWORD :4; /* */
_UDWORD VDC505AWCACHE:4; /* VDC505AWCACHE */
_UDWORD :4; /* */
_UDWORD VDC505ARCACHE:4; /* VDC505ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL8; /* */
union { /* AXIBUSCTL9 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD VDC513AWCACHE:4; /* VDC513AWCACHE */
_UDWORD :4; /* */
_UDWORD VDC513ARCACHE:4; /* VDC513ARCACHE */
_UDWORD :12; /* */
_UDWORD VDC512ARCACHE:4; /* VDC512ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL9; /* */
union { /* AXIBUSCTL10 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD VDC515AWCACHE:4; /* VDC515AWCACHE */
_UDWORD :4; /* */
_UDWORD VDC515ARCACHE:4; /* VDC515ARCACHE */
_UDWORD :12; /* */
_UDWORD VDC514ARCACHE:4; /* VDC514ARCACHE */
_UDWORD :4; /* */
} BIT; /* */
} AXIBUSCTL10; /* */
union { /* AXIRERRCTL0 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :8; /* */
_UDWORD CEURERREN:1; /* CEURERREN */
_UDWORD :3; /* */
_UDWORD IMRDRERREN:1; /* IMRDRERREN */
_UDWORD :3; /* */
_UDWORD IMR21RERREN:1; /* IMR21RERREN */
_UDWORD :3; /* */
_UDWORD IMR20RERREN:1; /* IMR20RERREN */
_UDWORD :3; /* */
_UDWORD ETHRERREN:1; /* ETHRERREN */
_UDWORD :3; /* */
_UDWORD JCURERREN:1; /* JCURERREN */
_UDWORD :3; /* */
} BIT; /* */
} AXIRERRCTL0; /* */
union { /* AXIRERRCTL1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD RGP1281RERREN:1; /* RGP1281RERREN */
_UDWORD :3; /* */
_UDWORD RGP1280RERREN:1; /* RGP1280RERREN */
_UDWORD :3; /* */
_UDWORD RGP642RERREN:1; /* RGP642RERREN */
_UDWORD :3; /* */
_UDWORD RGP641RERREN:1; /* RGP641RERREN */
_UDWORD :3; /* */
_UDWORD RGP640RERREN:1; /* RGP640RERREN */
_UDWORD :3; /* */
} BIT; /* */
} AXIRERRCTL1; /* */
union { /* AXIRERRCTL2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD VDC505RERREN:1; /* VDC505RERREN */
_UDWORD :3; /* */
_UDWORD VDC504RERREN:1; /* VDC504RERREN */
_UDWORD :3; /* */
_UDWORD VDC503RERREN:1; /* VDC503RERREN */
_UDWORD :3; /* */
_UDWORD VDC502RERREN:1; /* VDC502RERREN */
_UDWORD :3; /* */
_UDWORD VDC501RERREN:1; /* VDC501RERREN */
_UDWORD :3; /* */
} BIT; /* */
} AXIRERRCTL2; /* */
union { /* AXIRERRCTL3 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD VDC515RERREN:1; /* VDC515RERREN */
_UDWORD :3; /* */
_UDWORD VDC514RERREN:1; /* VDC514RERREN */
_UDWORD :3; /* */
_UDWORD VDC513RERREN:1; /* VDC513RERREN */
_UDWORD :3; /* */
_UDWORD VDC512RERREN:1; /* VDC512RERREN */
_UDWORD :3; /* */
_UDWORD VDC511RERREN:1; /* VDC511RERREN */
_UDWORD :3; /* */
} BIT; /* */
} AXIRERRCTL3; /* */
union { /* AXIRERRST0 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :8; /* */
_UDWORD CEUBRESP:2; /* CEUBRESP */
_UDWORD CEURRESP:2; /* CEURRESP */
_UDWORD IMRDBRESP:2; /* IMRDBRESP */
_UDWORD IMRDRRESP:2; /* IMRDRRESP */
_UDWORD IMR21BRESP:2; /* IMR21BRESP */
_UDWORD IMR21RRESP:2; /* IMR21RRESP */
_UDWORD IMR20BRESP:2; /* IMR20BRESP */
_UDWORD IMR20RRESP:2; /* IMR20RRESP */
_UDWORD ETHBRESP:2; /* ETHBRESP */
_UDWORD ETHRRESP:2; /* ETHRRESP */
_UDWORD JCUBRESP:2; /* JCUBRESP */
_UDWORD JCURRESP:2; /* JCURRESP */
} BIT; /* */
} AXIRERRST0; /* */
union { /* AXIRERRST1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD RGP1281BRESP:2; /* RGP1281BRESP */
_UDWORD RGP1281RRESP:2; /* RGP1281RRESP */
_UDWORD RGP1280BRESP:2; /* RGP1280BRESP */
_UDWORD RGP1280RRESP:2; /* RGP1280RRESP */
_UDWORD RGP642BRESP:2; /* RGP642BRESP */
_UDWORD RGP642RRESP:2; /* RGP642RRESP */
_UDWORD RGP641BRESP:2; /* RGP641BRESP */
_UDWORD RGP641RRESP:2; /* RGP641RRESP */
_UDWORD RGP640BRESP:2; /* RGP640BRESP */
_UDWORD RGP640RRESP:2; /* RGP640RRESP */
} BIT; /* */
} AXIRERRST1; /* */
union { /* AXIRERRST2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD VDC505BRESP:2; /* VDC505BRESP */
_UDWORD VDC505RRESP:2; /* VDC505RRESP */
_UDWORD VDC504BRESP:2; /* VDC504BRESP */
_UDWORD VDC504RRESP:2; /* VDC504RRESP */
_UDWORD VDC503BRESP:2; /* VDC503BRESP */
_UDWORD VDC503RRESP:2; /* VDC503RRESP */
_UDWORD VDC502BRESP:2; /* VDC502BRESP */
_UDWORD VDC502RRESP:2; /* VDC502RRESP */
_UDWORD VDC501BRESP:2; /* VDC501BRESP */
_UDWORD VDC501RRESP:2; /* VDC501RRESP */
} BIT; /* */
} AXIRERRST2; /* */
union { /* AXIRERRST3 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD VDC515BRESP:2; /* VDC515BRESP */
_UDWORD VDC515RRESP:2; /* VDC515RRESP */
_UDWORD VDC514BRESP:2; /* VDC514BRESP */
_UDWORD VDC514RRESP:2; /* VDC514RRESP */
_UDWORD VDC513BRESP:2; /* VDC513BRESP */
_UDWORD VDC513RRESP:2; /* VDC513RRESP */
_UDWORD VDC512BRESP:2; /* VDC512BRESP */
_UDWORD VDC512RRESP:2; /* VDC512RRESP */
_UDWORD VDC511BRESP:2; /* VDC511BRESP */
_UDWORD VDC511RRESP:2; /* VDC511RRESP */
} BIT; /* */
} AXIRERRST3; /* */
union { /* AXIRERRCLR0 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :8; /* */
_UDWORD CEUBRESPCLR:1; /* CEUBRESPCLR */
_UDWORD :1; /* */
_UDWORD CEURRESPCLR:1; /* CEURRESPCLR */
_UDWORD :1; /* */
_UDWORD IMRDBRESPCLR:1; /* IMRDBRESPCLR */
_UDWORD :1; /* */
_UDWORD IMRDRRESPCLR:1; /* IMRDRRESPCLR */
_UDWORD :1; /* */
_UDWORD IMR21BRESPCLR:1; /* IMR21BRESPCLR */
_UDWORD :1; /* */
_UDWORD IMR21RRESPCLR:1; /* IMR21RRESPCLR */
_UDWORD :1; /* */
_UDWORD IMR20BRESPCLR:1; /* IMR20BRESPCLR */
_UDWORD :1; /* */
_UDWORD IMR20RRESPCLR:1; /* IMR20RRESPCLR */
_UDWORD :1; /* */
_UDWORD ETHBRESPCLR:1; /* ETHBRESPCLR */
_UDWORD :1; /* */
_UDWORD ETHRRESPCLR:1; /* ETHRRESPCLR */
_UDWORD :1; /* */
_UDWORD JCUBRESPCLR:1; /* JCUBRESPCLR */
_UDWORD :1; /* */
_UDWORD JCURRESPCLR:1; /* JCURRESPCLR */
_UDWORD :1; /* */
} BIT; /* */
} AXIRERRCLR0; /* */
union { /* AXIRERRCLR1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD RGP1281BRESPCLR:1; /* RGP1281BRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP1281RRESPCLR:1; /* RGP1281RRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP1280BRESPCLR:1; /* RGP1280BRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP1280RRESPCLR:1; /* RGP1280RRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP642BRESPCLR:1; /* RGP642BRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP642RRESPCLR:1; /* RGP642RRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP641BRESPCLR:1; /* RGP641BRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP641RRESPCLR:1; /* RGP641RRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP640BRESPCLR:1; /* RGP640BRESPCLR */
_UDWORD :1; /* */
_UDWORD RGP640RRESPCLR:1; /* RGP640RRESPCLR */
_UDWORD :1; /* */
} BIT; /* */
} AXIRERRCLR1; /* */
union { /* AXIRERRCLR2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD VDC505BRESPCLR:1; /* VDC505BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC505RRESPCLR:1; /* VDC505RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC504BRESPCLR:1; /* VDC504BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC504RRESPCLR:1; /* VDC504RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC503BRESPCLR:1; /* VDC503BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC503RRESPCLR:1; /* VDC503RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC502BRESPCLR:1; /* VDC502BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC502RRESPCLR:1; /* VDC502RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC501BRESPCLR:1; /* VDC501BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC501RRESPCLR:1; /* VDC501RRESPCLR */
_UDWORD :1; /* */
} BIT; /* */
} AXIRERRCLR2; /* */
union { /* AXIRERRCLR3 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :12; /* */
_UDWORD VDC515BRESPCLR:1; /* VDC515BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC515RRESPCLR:1; /* VDC515RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC514BRESPCLR:1; /* VDC514BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC514RRESPCLR:1; /* VDC514RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC513BRESPCLR:1; /* VDC513BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC513RRESPCLR:1; /* VDC513RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC512BRESPCLR:1; /* VDC512BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC512RRESPCLR:1; /* VDC512RRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC511BRESPCLR:1; /* VDC511BRESPCLR */
_UDWORD :1; /* */
_UDWORD VDC511RRESPCLR:1; /* VDC511RRESPCLR */
_UDWORD :1; /* */
} BIT; /* */
} AXIRERRCLR3; /* */
}; /* */
#define PRR (*(volatile struct st_prr *)0xFCFE1800) /* PRR Address */
#endif /* __PRR_IODEFINE_H__ */
/* End of File */

229
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/riic_iodefine.h
Unescape Escape View File

@ -0,0 +1,229 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : riic_iodefine.h
* Version : 0.01
* Device(s) : Aragon
* Tool-Chain : DS-5 Ver 5.8
* ARM Complier
* :
* H/W Platform : Aragon CPU Board
* Description : Aragon Sample Program vecotr.s
*******************************************************************************/
/*******************************************************************************
* History : DD.MM.YYYY Version Description
* : 27.07.2012 0.01 ŽQ<EFBFBD>lŽ‘—¿<EFBFBD>FRZ_A1H_05J_121010_11.pdf
*******************************************************************************/
#ifndef __RIIC_IODEFINE_H__
#define __RIIC_IODEFINE_H__
#include "typedefine.h"
typedef union { /* RIICnICSARy */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SVA0:1; /* SVA0 */
_UDWORD SVA:9; /* SVA */
_UDWORD :5; /* */
_UDWORD FSy:1; /* FSy */
_UDWORD :16; /* */
} BIT; /* */
} RIICnICSARy; /* */
struct st_riic_n { /* struct RIIC */
union { /* RIICnICCR1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SDAI:1; /* SDAI */
_UDWORD SCLI:1; /* SCLI */
_UDWORD SDAO:1; /* SDAO */
_UDWORD SCLO:1; /* SCLO */
_UDWORD SOWP:1; /* SOWP */
_UDWORD CLO:1; /* CLO */
_UDWORD IICRST:1; /* IICRST */
_UDWORD ICE:1; /* ICE */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICCR1; /* */
union { /* RIICnICCR2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :1; /* */
_UDWORD ST:1; /* ST */
_UDWORD RS:1; /* RS */
_UDWORD SP:1; /* SP */
_UDWORD :1; /* */
_UDWORD TRS:1; /* TRS */
_UDWORD MST:1; /* MST */
_UDWORD BBSY:1; /* BBSY */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICCR2; /* */
union { /* RIICnICMR1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD BC:3; /* BC */
_UDWORD BCWP:1; /* BCWP */
_UDWORD CKS:3; /* CKS */
_UDWORD MTWP:1; /* MTWP */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICMR1; /* */
union { /* RIICnICMR2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TMOS:1; /* TMOS */
_UDWORD TMOL:1; /* TMOL */
_UDWORD TMOH:1; /* TMOH */
_UDWORD :1; /* */
_UDWORD SDDL:3; /* SDDL */
_UDWORD DLCS:1; /* DLCS */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICMR2; /* */
union { /* RIICnICMR3 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD NF:2; /* NF */
_UDWORD ACKBR:1; /* ACKBR */
_UDWORD ACKBT:1; /* ACKBT */
_UDWORD ACKWP:1; /* ACKWP */
_UDWORD RDRFS:1; /* RDRFS */
_UDWORD WAIT:1; /* WAIT */
_UDWORD SMBS:1; /* SMBS */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICMR3; /* */
union { /* RIICnICFER */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TMOE:1; /* TMOE */
_UDWORD MALE:1; /* MALE */
_UDWORD NALE:1; /* NALE */
_UDWORD SALE:1; /* SALE */
_UDWORD NACKE:1; /* NACKE */
_UDWORD NFE:1; /* NFE */
_UDWORD SCLE:1; /* SCLE */
_UDWORD FMPE:1; /* FMPE */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICFER; /* */
union { /* RIICnICSER */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SAR0E:1; /* SAR0E */
_UDWORD SAR1E:1; /* SAR1E */
_UDWORD SAR2E:1; /* SAR2E */
_UDWORD GCAE:1; /* GCAE */
_UDWORD :1; /* */
_UDWORD DIDE:1; /* DIDE */
_UDWORD :1; /* */
_UDWORD HOAE:1; /* HOAE */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICSER; /* */
union { /* RIICnICIER */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TMOIE:1; /* TMOIE */
_UDWORD ALIE:1; /* ALIE */
_UDWORD STIE:1; /* STIE */
_UDWORD SPIE:1; /* SPIE */
_UDWORD NAKIE:1; /* NAKIE */
_UDWORD RIE:1; /* RIE */
_UDWORD TEIE:1; /* TEIE */
_UDWORD TIE:1; /* TIE */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICIER; /* */
union { /* RIICnICSR1 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD AAS0:1; /* AAS0 */
_UDWORD AAS1:1; /* AAS1 */
_UDWORD AAS2:1; /* AAS2 */
_UDWORD GCA:1; /* GCA */
_UDWORD :1; /* */
_UDWORD DID:1; /* DID */
_UDWORD :1; /* */
_UDWORD HOA:1; /* HOA */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICSR1; /* */
union { /* RIICnICSR2 */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TMOF:1; /* TMOF */
_UDWORD AL:1; /* AL */
_UDWORD START:1; /* START */
_UDWORD STOP:1; /* STOP */
_UDWORD NACKF:1; /* NACKF */
_UDWORD RDRF:1; /* RDRF */
_UDWORD TEND:1; /* TEND */
_UDWORD TDRE:1; /* TDRE */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICSR2; /* */
RIICnICSARy RIICnICSAR0; /* RIICnICSAR0 */
RIICnICSARy RIICnICSAR1; /* RIICnICSAR1 */
RIICnICSARy RIICnICSAR2; /* RIICnICSAR2 */
union { /* RIICnICBRL */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD BRL:5; /* BRL */
_UDWORD :27; /* */
} BIT; /* */
} RIICnICBRL; /* */
union { /* RIICnICBRH */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD BRH:5; /* BRH */
_UDWORD :27; /* */
} BIT; /* */
} RIICnICBRH; /* */
union { /* RIICnICDRT */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ICDRS:8; /* ICDRS */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICDRT; /* */
union { /* RIICnICDRR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ICDRR:8; /* ICDRR */
_UDWORD :24; /* */
} BIT; /* */
} RIICnICDRR; /* */
}; /* */
#define RIIC_0 (*(volatile struct st_riic_n *)0xFCFEE000) /* RIIC_0 Address */
#define RIIC_1 (*(volatile struct st_riic_n *)0xFCFEE400) /* RIIC_1 Address */
#define RIIC_2 (*(volatile struct st_riic_n *)0xFCFEE800) /* RIIC_2 Address */
#define RIIC_3 (*(volatile struct st_riic_n *)0xFCFEEC00) /* RIIC_3 Address */
#endif /* __RIIC_IODEFINE_H__ */
/* End of File */

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/******************************************************************************
* DISCLAIMER
*
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized.
*
* This software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
* DISCLAIMED.
*
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
*
* Renesas reserves the right, without notice, to make changes to this
* software and to discontinue the availability of this software.
* By using this software, you agree to the additional terms and
* conditions found by accessing the following link:
* http://www.renesas.com/disclaimer
********************************************************************************
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
**************************** Technical reference data **************************
* System Name :
* File Name : scif_iodefine.h
* Abstract :
* Version : 1.00.00
* Device : ARM
* Tool-Chain :
* OS : None
* H/W Platform:
* Description :
********************************************************************************
* History : Mar.06,2012 Ver.1.00.00
*******************************************************************************/
#ifndef __SCIF_IODEFINE_H__
#define __SCIF_IODEFINE_H__
#include "typedefine.h"
struct st_scif_n { /* struct SCIF */
union { /* SCSMR_0 */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD CKS:2; /* CKS */
_UWORD :1; /* */
_UWORD STOP:1; /* STOP */
_UWORD OE:1; /* O/E */
_UWORD PE:1; /* PE */
_UWORD CHR:1; /* CHR */
_UWORD CA:1; /* C/A */
_UWORD :8; /* */
} BIT; /* */
} SCSMR; /* */
_UBYTE wk0[2]; /* */
union { /* SCBRR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE D:8; /* D */
} BIT; /* */
} SCBRR; /* */
_UBYTE wk1[3]; /* */
union { /* SCSCR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD CKE:2; /* CKE */
_UWORD :1; /* */
_UWORD REIE:1; /* REIE */
_UWORD RE:1; /* RE */
_UWORD TE:1; /* TE */
_UWORD RIE:1; /* RIE */
_UWORD TIE:1; /* TIE */
_UWORD :8; /* */
} BIT; /* */
} SCSCR; /* */
_UBYTE wk2[2]; /* */
union { /* SCFTDR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE D:8; /* D */
} BIT; /* */
} SCFTDR; /* */
_UBYTE wk3[3]; /* */
union { /* SCFSR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD DR:1; /* DR */
_UWORD RDF:1; /* RDF */
_UWORD PER:1; /* PER */
_UWORD FER:1; /* FER */
_UWORD BRK:1; /* BRK */
_UWORD TDFE:1; /* TDFE */
_UWORD TEND:1; /* TEND */
_UWORD ER:1; /* ER */
_UWORD FERN:4; /* FERN */
_UWORD PERN:4; /* PERN */
} BIT; /* */
} SCFSR; /* */
_UBYTE wk4[2]; /* */
union { /* SCFRDR */
_UBYTE BYTE; /* Byte Access */
struct { /* Bit Access */
_UBYTE D:8; /* D */
} BIT; /* */
} SCFRDR; /* */
_UBYTE wk5[3]; /* */
union { /* SCFCR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD LOOP:1; /* LOOP */
_UWORD RFRST:1; /* RFRST */
_UWORD TFRST:1; /* TFRST */
_UWORD MCE:1; /* MCE */
_UWORD TTRG:2; /* TTRG */
_UWORD RTRG:2; /* RTRG */
_UWORD RSTRG:3; /* RSTRG */
_UWORD :5; /* */
} BIT; /* */
} SCFCR; /* */
_UBYTE wk6[2]; /* */
union { /* SCFDR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD R:5; /* R */
_UWORD :3; /* */
_UWORD T:5; /* T */
_UWORD :3; /* */
} BIT; /* */
} SCFDR; /* */
_UBYTE wk7[2]; /* */
union { /* SCSPTR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD SPB2DT:1; /* SPB2DT */
_UWORD SPB2IO:1; /* SPB2IO */
_UWORD SCKDT:1; /* SCKDT */
_UWORD SCKIO:1; /* SCKIO */
_UWORD CTSDT:1; /* CTSDT */
_UWORD CTSIO:1; /* CTSIO */
_UWORD RTSDT:1; /* RTSDT */
_UWORD RTSIO:1; /* RTSIO */
_UWORD :8; /* */
} BIT; /* */
} SCSPTR; /* */
_UBYTE wk8[2]; /* */
union { /* SCLSR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD ORER:1; /* ORER */
_UWORD :15; /* */
} BIT; /* */
} SCLSR; /* */
_UBYTE wk9[2]; /* */
union { /* SCEMR */
_UWORD WORD; /* Word Access */
struct { /* Bit Access */
_UWORD ABCS:1; /* ABCS */
_UWORD :6; /* */
_UWORD BGDM:1; /* BGDM */
_UWORD :8; /* */
} BIT; /* */
} SCEMR; /* */
}; /* */
#define SCIF0 (*(volatile struct st_scif_n *)0xE8007000) /* SCIF0 Address */
#define SCIF1 (*(volatile struct st_scif_n *)0xE8007800) /* SCIF1 Address */
#define SCIF2 (*(volatile struct st_scif_n *)0xE8008000) /* SCIF2 Address */
#define SCIF3 (*(volatile struct st_scif_n *)0xE8008800) /* SCIF3 Address */
#define SCIF4 (*(volatile struct st_scif_n *)0xE8009000) /* SCIF4 Address */
#define SCIF5 (*(volatile struct st_scif_n *)0xE8009800) /* SCIF5 Address */
#define SCIF6 (*(volatile struct st_scif_n *)0xE800A000) /* SCIF6 Address */
#define SCIF7 (*(volatile struct st_scif_n *)0xE800A800) /* SCIF7 Address */
#endif /* __SCIF_IODEFINE_H__ */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spibsc_iodefine.h
* Version : 0.01
* Device(s) :
* Tool-Chain : DS-5 Ver 5.8
* ARM Complier
* :
* H/W Platform : CPU Board
* Description :
*******************************************************************************/
/*******************************************************************************
* History : 05.11.2012 0.01 Version Description
*******************************************************************************/
#ifndef __SPIBSC_IODEFINE_H__
#define __SPIBSC_IODEFINE_H__
#include "typedefine.h"
/****************************************************************/
/* SPIBSC */
/****************************************************************/
struct st_spibsc_n { /* struct SPIBSC*/
union { /* CMNCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD BSZ:2; /* BSZ */
_UDWORD :1; /* */
_UDWORD CPOL:1; /* CPOL */
_UDWORD SSLP:1; /* SSLP */
_UDWORD CPHAR:1; /* CPHAR */
_UDWORD CPHAT:1; /* CPHAT */
_UDWORD :1; /* */
_UDWORD IO0FV:2; /* IO0FV */
_UDWORD :2; /* */
_UDWORD IO2FV:2; /* IO2FV */
_UDWORD IO3FV:2; /* IO3FV */
_UDWORD MOIIO0:2; /* MOIIO0 */
_UDWORD MOIIO1:2; /* MOIIO1 */
_UDWORD MOIIO2:2; /* MOIIO2 */
_UDWORD MOIIO3:2; /* MOIIO3 */
_UDWORD :7; /* */
_UDWORD MD:1; /* MD */
} BIT; /* */
} CMNCR; /* */
union { /* SSLDR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SCKDL:3; /* SCKDL */
_UDWORD :5; /* */
_UDWORD SLNDL:3; /* SLNDL */
_UDWORD :5; /* */
_UDWORD SPNDL:3; /* SPNDL */
_UDWORD :13; /* */
} BIT; /* */
} SSLDR; /* */
union { /* SPBCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD BRDV:2; /* BRDV */
_UDWORD :6; /* */
_UDWORD SPBR:8; /* SPBR */
_UDWORD :16; /* */
} BIT; /* */
} SPBCR; /* */
union { /* DRCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SSLE:1; /* SSLE */
_UDWORD :7; /* */
_UDWORD RBE:1; /* RBE */
_UDWORD RCF:1; /* RCF */
_UDWORD :6; /* */
_UDWORD RBURST:4; /* RBURST */
_UDWORD :4; /* */
_UDWORD SSLN:1; /* SSLN */
_UDWORD :7; /* */
} BIT; /* */
} DRCR; /* */
union { /* DRCMR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD OCMD:8; /* OCMD */
_UDWORD :8; /* */
_UDWORD CMD:8; /* CMD */
_UDWORD :8; /* */
} BIT; /* */
} DRCMR; /* */
union { /* DREAR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD EAC:3; /* EAC */
_UDWORD :13; /* */
_UDWORD EAV:8; /* EAV */
_UDWORD :8; /* */
} BIT; /* */
} DREAR; /* */
union { /* DROPR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD OPD0:8; /* OPD0 */
_UDWORD OPD1:8; /* OPD1 */
_UDWORD OPD2:8; /* OPD2 */
_UDWORD OPD3:8; /* OPD3 */
} BIT; /* */
} DROPR; /* */
union { /* DRENR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD :4; /* */
_UDWORD OPDE:4; /* OPDE */
_UDWORD ADE:4; /* ADE */
_UDWORD OCDE:1; /* OCDE */
_UDWORD :1; /* */
_UDWORD CDE:1; /* CDE */
_UDWORD DME:1; /* DME */
_UDWORD DRDB:2; /* DRDB */
_UDWORD :2; /* */
_UDWORD OPDB:2; /* OPDB */
_UDWORD :2; /* */
_UDWORD ADB:2; /* ADB */
_UDWORD :2; /* */
_UDWORD OCDB:2; /* OCDB */
_UDWORD CDB:2; /* CDB */
} BIT; /* */
} DRENR; /* */
union { /* SMCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SPIE:1; /* SPIE */
_UDWORD SPIWE:1; /* SPIWE */
_UDWORD SPIRE:1; /* SPIRE */
_UDWORD :5; /* */
_UDWORD SSLKP:1; /* SSLKP */
_UDWORD :23; /* */
} BIT; /* */
} SMCR; /* */
union { /* SMCMR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD OCMD:8; /* OCMD */
_UDWORD :8; /* */
_UDWORD CMD:8; /* CMD */
_UDWORD :8; /* */
} BIT; /* */
} SMCMR; /* */
union { /* SMADR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD ADR:32; /* ADR */
} BIT; /* */
} SMADR; /* */
union { /* SMOPR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD OPD0:8; /* OPD0 */
_UDWORD OPD1:8; /* OPD1 */
_UDWORD OPD2:8; /* OPD2 */
_UDWORD OPD3:8; /* OPD3 */
} BIT; /* */
} SMOPR; /* */
union { /* SMENR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SPIDE:4; /* SPIDE */
_UDWORD OPDE:4; /* OPDE */
_UDWORD ADE:4; /* ADE */
_UDWORD OCDE:1; /* OCDE */
_UDWORD :1; /* */
_UDWORD CDE:1; /* CDE */
_UDWORD DME:1; /* DME */
_UDWORD SPIDB:2; /* SPIDB */
_UDWORD :2; /* */
_UDWORD OPDB:2; /* OPDB */
_UDWORD :2; /* */
_UDWORD ADB:2; /* ADB */
_UDWORD :2; /* */
_UDWORD OCDB:2; /* OCDB */
_UDWORD CDB:2; /* CDB */
} BIT; /* */
} SMENR; /* */
_UBYTE wk0[4]; /* */
union { /* SMRDR0 */
_UDWORD LONG; /* Long Access */
struct { /* Word Access */
_UWORD L; /* Low */
_UWORD H; /* High */
} WORD; /* */
struct { /* Byte Access */
_UBYTE LL; /* Low, Low */
_UBYTE LH; /* Low, High */
_UBYTE HL; /* High, Low */
_UBYTE HH; /* High, High */
} BYTE; /* */
struct { /* Bit Access */
_UDWORD RDATA0:32; /* RDATA0 */
} BIT; /* */
} SMRDR0; /* */
union { /* SMRDR1 */
_UDWORD LONG; /* Long Access */
struct { /* Word Access */
_UWORD L; /* Low */
_UWORD H; /* High */
} WORD; /* */
struct { /* Byte Access */
_UBYTE LL; /* Low, Low */
_UBYTE LH; /* Low, High */
_UBYTE HL; /* High, Low */
_UBYTE HH; /* High, High */
} BYTE; /* */
struct { /* Bit Access */
_UDWORD RDATA1:32; /* RDATA1 */
} BIT; /* */
} SMRDR1; /* */
union { /* SMWDR0 */
_UDWORD LONG; /* Long Access */
struct { /* Word Access */
_UWORD L; /* Low */
_UWORD H; /* High */
} WORD; /* */
struct { /* Byte Access */
_UBYTE LL; /* Low, Low */
_UBYTE LH; /* Low, High */
_UBYTE HL; /* High, Low */
_UBYTE HH; /* High, High */
} BYTE; /* */
struct { /* Bit Access */
_UDWORD WDATA0:32; /* WDATA0 */
} BIT; /* */
} SMWDR0; /* */
union { /* SMWDR1 */
_UDWORD LONG; /* Long Access */
struct { /* Word Access */
_UWORD L; /* Low */
_UWORD H; /* High */
} WORD; /* */
struct { /* Byte Access */
_UBYTE LL; /* Low, Low */
_UBYTE LH; /* Low, High */
_UBYTE HL; /* High, Low */
_UBYTE HH; /* High, High */
} BYTE; /* */
struct { /* Bit Access */
_UDWORD WDATA1:32; /* WDATA1 */
} BIT; /* */
} SMWDR1; /* */
union { /* CMNSR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD TEND:1; /* TEND */
_UDWORD SSLF:1; /* SSLF */
_UDWORD :30; /* */
} BIT; /* */
} CMNSR; /* */
_UBYTE wk1[12]; /* */
union { /* DRDMCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD DMCYC:3; /* */
_UDWORD :13; /* */
_UDWORD DMDB:2; /* */
_UDWORD :14; /* */
} BIT; /* */
} DRDMCR; /* */
union { /* DRDRENR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD DRDRE:1; /* */
_UDWORD :3; /* */
_UDWORD OPDRE:1; /* */
_UDWORD :3; /* */
_UDWORD ADDRE:1; /* */
_UDWORD :23; /* */
} BIT; /* */
} DRDRENR; /* */
union { /* SMDMCR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD DMCYC:3; /* */
_UDWORD :13; /* */
_UDWORD DMDB:2; /* */
_UDWORD :14; /* */
} BIT; /* */
} SMDMCR; /* */
union { /* SMDRENR */
_UDWORD LONG; /* Long Access */
struct { /* Bit Access */
_UDWORD SPIDRE:1; /* */
_UDWORD :3; /* */
_UDWORD OPDRE:1; /* */
_UDWORD :3; /* */
_UDWORD ADDRE:1; /* */
_UDWORD :23; /* */
} BIT; /* */
} SMDRENR; /* */
}; /* */
#define SPIBSC0 (*(volatile struct st_spibsc_n *)0x3FEFA000)
#define SPIBSC1 (*(volatile struct st_spibsc_n *)0x3FEFB000)
#endif /* __SPIBSC_IODEFINE_H__ */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : main.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - Main
******************************************************************************/
#ifndef _MAIN_H_
#define _MAIN_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
int_t main(void);
void Sample_OSTM0_Interrupt(void);
#endif /* _MAIN_H_ */
/* End of File */

61
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/port_init.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : port_init.h
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - SCIF UART sample program
******************************************************************************/
#ifndef _PORT_INIT_H_
#define _PORT_INIT_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void PORT_Init(void);
#endif /* _PORT_INIT_H_ */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : r_typedefs.h
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : basic type definition
******************************************************************************/
#ifndef R_TYPEDEFS_H
#define R_TYPEDEFS_H
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include <stddef.h>
/******************************************************************************
Macro definitions
******************************************************************************/
#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus)
#define false 0
#define true 1
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
typedef char char_t;
typedef unsigned int bool_t;
typedef int int_t;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed long int32_t;
typedef signed long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned long uint32_t;
typedef unsigned long long uint64_t;
typedef float float32_t;
typedef double float64_t;
typedef long double float128_t;
#endif /* R_TYPEDEFS_H */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : resetprg.h
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - Program after reset
******************************************************************************/
#ifndef _RESETPRG_H_
#define _RESETPRG_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void io_init_cache(void);
int32_t io_cache_writeback(void);
#endif /* _RESETPRG_H_ */
/* End of File */

61
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sample_main.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : sample_main.h
* $Rev: $
* $Date:: $
* Description : Aragon Sample Program - RIIC sample program
******************************************************************************/
#ifndef _SAMPLE_MAIN_H_
#define _SAMPLE_MAIN_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void Sample_Main(void);
#endif /* _SAMPLE_MAIN_H_ */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : sio_char.h
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - Terminal I/O
******************************************************************************/
#ifndef _SIO_CHAR_H_
#define _SIO_CHAR_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
int32_t SioWrite(int32_t file_no, const char_t * buffer, uint32_t writing_b);
int32_t SioRead(int32_t file_no, char_t * buffer, uint32_t reading_b);
void IoInitScif2(void);
char_t IoGetchar(void);
void IoPutchar(char_t buffer);
#endif /* _SIO_CHAR_H_ */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/******************************************************************************
* File Name : stb_init.h
* $Rev: 17531 $
* $Date:: 2013-04-10 12:58:44 +0100#$
* Description : Aragon Sample Program - SCIF UART sample program
******************************************************************************/
#ifndef _STB_INIT_H_
#define _STB_INIT_H_
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void STB_Init(void);
#endif /* _STB_INIT_H_ */
/* End of File */

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/typedefine.h
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : typedefine.h
* Version : 1.00
* Description : Defines exact width integer types.
*******************************************************************************/
/*******************************************************************************
* History : DD.MM.YYYY Version Description
* : 24.05.2012 1.00 First Release
*******************************************************************************/
#ifndef _TYPE_DEFINE_H_
#define _TYPE_DEFINE_H_
/*******************************************************************************
Typedef definitions
*******************************************************************************/
typedef signed char _SBYTE;
typedef unsigned char _UBYTE;
typedef signed short _SWORD;
typedef unsigned short _UWORD;
typedef signed int _SINT;
typedef unsigned int _UINT;
typedef signed long _SDWORD;
typedef unsigned long _UDWORD;
typedef signed long long _SQWORD;
typedef unsigned long long _UQWORD;
#endif /* _TYPE_DEFINE_H_ */
/* End of File */

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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : vector_mirrortable.s
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.13
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program - Vector mirrortable
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
;==================================================================
; Entry point for the Reset handler
;==================================================================
PRESERVE8
AREA VECTOR_MIRROR_TABLE, CODE, READONLY
; EXPORT vector_table
IMPORT reset_handler
IMPORT undefined_handler
IMPORT prefetch_handler
IMPORT abort_handler
IMPORT reserved_handler
IMPORT FreeRTOS_IRQ_Handler
IMPORT fiq_handler
IMPORT FreeRTOS_SWI_Handler
; ENTRY
; EXPORT Start
;Start
vector_table2
LDR pc, =reset_handler ; 0x0000_0000
LDR pc, =undefined_handler ; 0x0000_0004
LDR pc, =FreeRTOS_SWI_Handler ; 0x0000_0008
LDR pc, =prefetch_handler ; 0x0000_000c
LDR pc, =abort_handler ; 0x0000_0010
LDR pc, =reserved_handler ; 0x0000_0014
LDR pc, =FreeRTOS_IRQ_Handler ; 0x0000_0018
LDR pc, =fiq_handler ; 0x0000_001c
Literals
LTORG
END

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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : vector_table.s
;* Version : 0.01
;* Device(s) : Aragon - RZ/A1H
;* Tool-Chain : DS-5 Ver 5.13
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program - Vector table
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
;==================================================================
; Entry point for the Reset handler
;==================================================================
PRESERVE8
AREA VECTOR_TABLE, CODE, READONLY
EXPORT vector_table
IMPORT reset_handler
IMPORT undefined_handler
IMPORT FreeRTOS_SWI_Handler
IMPORT prefetch_handler
IMPORT abort_handler
IMPORT reserved_handler
IMPORT FreeRTOS_IRQ_Handler
IMPORT fiq_handler
ENTRY
EXPORT Start
Start
vector_table
LDR pc, =reset_handler ; 0x0000_0000
LDR pc, =undefined_handler ; 0x0000_0004
LDR pc, =FreeRTOS_SWI_Handler ; 0x0000_0008
LDR pc, =prefetch_handler ; 0x0000_000c
LDR pc, =abort_handler ; 0x0000_0010
LDR pc, =reserved_handler ; 0x0000_0014
LDR pc, =FreeRTOS_IRQ_Handler ; 0x0000_0018
LDR pc, =fiq_handler ; 0x0000_001c
Literals
LTORG
END

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FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/main.c
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/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
*
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Standard demo includes. */
#include "partest.h"
#include "TimerDemo.h"
/* Renesas includes. */
#include "r_typedefs.h"
#include "sio_char.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* Configure the hardware as necessary to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
extern void main_blinky( void );
#else
extern void main_full( void );
#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
within this file. */
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );
void vApplicationTickHook( void );
/*
* Creates and verifies different files on the volume, demonstrating the use of
* various different API functions.
*/
extern void vCreateAndVerifySampleFiles( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* Configure the hardware ready to run the demo. */
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
of this file. */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Initialise the pins used by the LEDs (the obscure [now for historical
reasons] name ParTest stands for Parallel Port test). */
vParTestInitialise();
/* Call the Renesas driver that initialises the serial port. P1=66.67MHz
CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps. */
IoInitScif2();
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeHeapSpace;
/* This is just a trivial example of an idle hook. It is called on each
cycle of the idle task. It must *NOT* attempt to block. In this case the
idle task just queries the amount of FreeRTOS heap that remains. See the
memory management section on the http://www.FreeRTOS.org web site for memory
management options. If there is a lot of heap memory free then the
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
RAM. */
xFreeHeapSpace = xPortGetFreeHeapSize();
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
( void ) xFreeHeapSpace;
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1
{
/* If the file system is only going to be accessed from one task then
F_FS_THREAD_AWARE can be set to 0 and the set of example files is
created before the RTOS scheduler is started. If the file system is
going to be access from more than one task then F_FS_THREAD_AWARE must
be set to 1 and the set of sample files are created from the idle task
hook function. */
#if F_FS_THREAD_AWARE == 1
{
static portBASE_TYPE xCreatedSampleFiles = pdFALSE;
/* Initialise the drive and file system, then create a few example
files. The output from this function just goes to the stdout window,
allowing the output to be viewed when the UDP command console is not
connected. */
if( xCreatedSampleFiles == pdFALSE )
{
vCreateAndVerifySampleFiles();
xCreatedSampleFiles = pdTRUE;
}
}
#endif
}
#endif
}
/*-----------------------------------------------------------*/
void vAssertCalled( const char * pcFile, unsigned long ulLine )
{
volatile unsigned long ul = 0;
( void ) pcFile;
( void ) ulLine;
taskENTER_CRITICAL();
{
/* Set ul to a non-zero value using the debugger to step out of this
function. */
while( ul == 0 )
{
portNOP();
}
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
{
/* The full demo includes a software timer demo/test that requires
prodding periodically from the tick interrupt. */
vTimerPeriodicISRTests();
}
#endif
}

82
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/scatter.scat
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;/*******************************************************************************
;* DISCLAIMER
;* This software is supplied by Renesas Electronics Corporation and is only
;* intended for use with Renesas products. No other uses are authorized. This
;* software is owned by Renesas Electronics Corporation and is protected under
;* all applicable laws, including copyright laws.
;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* Renesas reserves the right, without notice, to make changes to this software
;* and to discontinue the availability of this software. By using this software,
;* you agree to the additional terms and conditions found by accessing the
;* following link:
;* http://www.renesas.com/disclaimer
;*
;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
;*******************************************************************************/
;/*******************************************************************************
;* File Name : scatter.scat
;* Version : 0.01
;* Device(s) : Aragon
;* Tool-Chain : DS-5 Ver 5.8
;* ARM Complier
;* :
;* H/W Platform : Aragon CPU Board
;* Description : Aragon Sample Program scatter file
;*******************************************************************************/
;/*******************************************************************************
;* History : DD.MM.YYYY Version Description
;* : 23.05.2012 0.01
;*******************************************************************************/
LOAD_MODULE3 0x20020000 0x209FFFFF ;; Internal RAM Area (0x20020000-0x2003FFFF)
{
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; use as RAM Area ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
VECTOR_MIRROR_TABLE 0x20020000 ;; Internal RAM Area (0x20020000-0x200200FF)
{ * (VECTOR_MIRROR_TABLE) } ;; Vector table
CODE +0 FIXED
{ * (+RO-CODE) }
CONST +0 FIXED
{ * (+RO-DATA) }
DATA +0
{ * (+RW) }
BSS +0
{ * (+ZI) }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; use as RAM Area(2) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ARM_LIB_HEAP 0x20080000 EMPTY 0x00008000 ; Application heap
{ }
ARM_LIB_STACK 0x20090000 EMPTY -0x00008000 ; Application stack
{ }
IRQ_STACK 0x20092000 EMPTY -0x00002000 ; IRQ mode stack
{ }
FIQ_STACK 0x20094000 EMPTY -0x00002000 ; FRQ mode stack
{ }
SVC_STACK 0x20096000 EMPTY -0x00002000 ; SVC mode stack
{ }
ABT_STACK 0x20098000 EMPTY -0x00002000 ; ABT mode stack
{ }
TTB (0x20098000 AND 0xFFFFC000) EMPTY 0x00008000 ; Level-1 Translation Table for MMU
{ }
}

54
FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds
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stop
pause 500
reset
stop
#reset
info memory
memory S:0x00000000 S:0x07ffffff ro
memory S:0x3fffff80 S:0x3fffffff nocache noverify
memory S:0xfcfe0000 S:0xfcfeffff nocache noverify
# USB Register accessed by only 16bit
memory S:0xe8010000 S:0xe801010f 16
memory S:0xe8207000 S:0xe820710f 16
info memory
######################################
# Release L2 cache standby ##
######################################
mem set 0x3fffff80 32 0x00000001
# ;*Writing to On-Chip Data-Retention RAM is enabled.
# ;SYSCR3.RRAMWE3=RRAMWE2=RRAMWE1=RRAMWE0=1
mem set 0xfcfe0408 32 0xf
######################################
# CS0 Port Setting ##
# CS1 Port Setting ##
######################################
# P9_1(A25), P9_0(A24),
mem set 0xfcfe3424 16 0x0003 # PMC9
mem set 0xfcfe3A24 16 0x0000 # PFCAE9
mem set 0xfcfe3624 16 0x0000 # PFCE9
mem set 0xfcfe3524 16 0x0000 # PFC9
mem set 0xfcfe7224 16 0x0003 # PIPC9
# P8_15(A23), P8_14(A22), P8_13(A21),
mem set 0xfcfe3420 16 0xffff # PMC8
mem set 0xfcfe3A20 16 0x0000 # PFCAE8
mem set 0xfcfe3620 16 0x0000 # PFCE8
mem set 0xfcfe3520 16 0x0000 # PFC8
mem set 0xfcfe7220 16 0xffff # PIPC8
# P7_6(WE0#), P7_8(RD#), P7_0(CS0#),
mem set 0xfcfe341c 16 0xff41 # PMC7
mem set 0xfcfe3A1c 16 0x0000 # PFCAE7
mem set 0xfcfe361c 16 0x0000 # PFCE7
mem set 0xfcfe351c 16 0x0000 # PFC7
mem set 0xfcfe721c 16 0xff41 # PIPC7
# P3_7(CS1#),
mem set 0xfcfe340c 16 0x0080 # PMC3
mem set 0xfcfe3A0c 16 0x0080 # PFCAE3
mem set 0xfcfe360c 16 0x0080 # PFCE3
mem set 0xfcfe350c 16 0x0000 # PFC3
mem set 0xfcfe720c 16 0x0080 # PIPC3
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