diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.cproject b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.cproject
new file mode 100644
index 000000000..52969dd3e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.cproject
@@ -0,0 +1,113 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.project b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.project
new file mode 100644
index 000000000..ef8123634
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.project
@@ -0,0 +1,245 @@
+
+
+ FreeRTOS_Demo
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+ ?name?
+
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.autoBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.buildArguments
+
+
+
+ org.eclipse.cdt.make.core.buildCommand
+ make
+
+
+ org.eclipse.cdt.make.core.buildLocation
+ ${workspace_loc:/FreeRTOS_Demo/Debug}
+
+
+ org.eclipse.cdt.make.core.cleanBuildTarget
+ clean
+
+
+ org.eclipse.cdt.make.core.contents
+ org.eclipse.cdt.make.core.activeConfigSettings
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ false
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.fullBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ true
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ Source/FreeRTOS-Source
+ 2
+ virtual:/virtual
+
+
+ Source/FreeRTOS-Source/Portable
+ 2
+ virtual:/virtual
+
+
+ Source/FreeRTOS-Source/include
+ 2
+ FreeRTOS_ROOT/FreeRTOS/Source/include
+
+
+ Source/FreeRTOS-Source/list.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Source/list.c
+
+
+ Source/FreeRTOS-Source/queue.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Source/queue.c
+
+
+ Source/FreeRTOS-Source/tasks.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Source/tasks.c
+
+
+ Source/FreeRTOS-Source/timers.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Source/timers.c
+
+
+ Source/Full-Demo/Common-Demo-Source
+ 2
+ virtual:/virtual
+
+
+ Source/Full-Demo/FreeRTOS-Plus-CLI
+ 2
+ FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI
+
+
+ Source/Full-Demo/FreeRTOS-Plus-FAT-SL
+ 2
+ virtual:/virtual
+
+
+ Source/FreeRTOS-Source/Portable/MemMang
+ 2
+ virtual:/virtual
+
+
+ Source/FreeRTOS-Source/Portable/RVDS
+ 2
+ virtual:/virtual
+
+
+ Source/Full-Demo/Common-Demo-Source/BlockQ.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/BlockQ.c
+
+
+ Source/Full-Demo/Common-Demo-Source/GenQTest.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/GenQTest.c
+
+
+ Source/Full-Demo/Common-Demo-Source/TimerDemo.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+
+
+ Source/Full-Demo/Common-Demo-Source/blocktim.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/blocktim.c
+
+
+ Source/Full-Demo/Common-Demo-Source/comtest.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/comtest.c
+
+
+ Source/Full-Demo/Common-Demo-Source/countsem.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/countsem.c
+
+
+ Source/Full-Demo/Common-Demo-Source/death.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/death.c
+
+
+ Source/Full-Demo/Common-Demo-Source/dynamic.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/dynamic.c
+
+
+ Source/Full-Demo/Common-Demo-Source/flop.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/flop.c
+
+
+ Source/Full-Demo/Common-Demo-Source/include
+ 2
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/include
+
+
+ Source/Full-Demo/Common-Demo-Source/recmutex.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/recmutex.c
+
+
+ Source/Full-Demo/Common-Demo-Source/semtest.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Demo/Common/Minimal/semtest.c
+
+
+ Source/Full-Demo/FreeRTOS-Plus-FAT-SL/Media-Driver
+ 2
+ virtual:/virtual
+
+
+ Source/Full-Demo/FreeRTOS-Plus-FAT-SL/api
+ 2
+ FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/api
+
+
+ Source/Full-Demo/FreeRTOS-Plus-FAT-SL/common
+ 2
+ FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/fat_sl/common
+
+
+ Source/Full-Demo/FreeRTOS-Plus-FAT-SL/rtc
+ 2
+ FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/psp/target/rtc
+
+
+ Source/FreeRTOS-Source/Portable/MemMang/heap_4.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c
+
+
+ Source/FreeRTOS-Source/Portable/RVDS/ARM_CA9
+ 2
+ FreeRTOS_ROOT/FreeRTOS/Source/portable/RVDS/ARM_CA9
+
+
+ Source/Full-Demo/FreeRTOS-Plus-FAT-SL/Media-Driver/ramdrv_f.c
+ 1
+ FreeRTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-FAT-SL/media-drv/ram/ramdrv_f.c
+
+
+
+
+ FreeRTOS_ROOT
+ $%7BPARENT-3-PROJECT_LOC%7D
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 000000000..86299018b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,4 @@
+#Sun Jun 16 20:16:37 BST 2013
+eclipse.preferences.version=1
+encoding//Source/RenesasFiles/handler/reset_handler.s=UTF-8
+encoding//Source/RenesasFiles/include/iodefine.h=UTF-8
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/LowLevelInitialise.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/LowLevelInitialise.c
new file mode 100644
index 000000000..93cc180cf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/LowLevelInitialise.c
@@ -0,0 +1,68 @@
+/*************************************************************************
+ *
+ * Used with ICCARM and AARM.
+ *
+ * (c) Copyright IAR Systems 2013
+ *
+ * File name : main.c
+ * Description : main module
+ **************************************************************************/
+
+/*
+ * Called from Cstart.s to configure the chip and board specific IO before
+ * main() is called.
+ */
+
+/** include files **/
+#include
+#include
+#include
+#include "armv7a_cp15_drv.h"
+#include "devdrv_common.h"
+
+/* Renesas include files. */
+#include "stb_init.h"
+#include "port_init.h"
+#include "devdrv_intc.h"
+
+
+/** external data **/
+#pragma section = ".intvec"
+
+extern void Peripheral_BasicInit( void );
+void LowLevelInitialisation(void);
+unsigned long __write(int fildes, const void *buf, unsigned long nbytes);
+
+/* Called from cstartup.s before the kernel is started. */
+void LowLevelInitialisation(void)
+{
+ /* Chip configuration functions from IAR. ********************************/
+ /* Disable MMU, enable ICache */
+ CP15_Mmu(FALSE);
+ CP15_ICache(FALSE);
+ CP15_SetVectorBase( (uint32_t )__section_begin( ".intvec" ) );
+
+ /* Set Low vectors mode in CP15 Control Register */
+ CP15_SetHighVectors(FALSE);
+
+
+ /* Chip and board specific configuration functions from Renesas. *********/
+ Peripheral_BasicInit();
+ STB_Init();
+ PORT_Init();
+ R_BSC_Init( ( uint8_t ) ( BSC_AREA_CS2 | BSC_AREA_CS3 ) );
+ R_INTC_Init();
+
+
+ CP15_ICache(TRUE);
+
+ /* Start with interrupts enabled. */
+ __enable_irq();
+ __enable_fiq();
+}
+
+/* Keep the linker happy. */
+unsigned long __write(int fildes, const void *buf, unsigned long nbytes)
+{
+ return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.ewp
new file mode 100644
index 000000000..e0a4dd3fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.ewp
@@ -0,0 +1,1213 @@
+
+
+
+ 2
+
+ RAM Debug
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 21
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 28
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 8
+ 1
+ 1
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 1
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 15
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 1
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ Blinky-Demo
+
+ $PROJ_DIR$\..\Source\Blinky-Demo\main_blinky.c
+
+
+
+ board
+
+ $PROJ_DIR$\board\board.h
+
+
+
+ FreeRTOS-Source
+
+ include
+
+ $PROJ_DIR$\..\..\..\Source\include\FreeRTOS.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\list.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\mpu_wrappers.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\portable.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\projdefs.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\queue.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\semphr.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\StackMacros.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\task.h
+
+
+ $PROJ_DIR$\..\..\..\Source\include\timers.h
+
+
+
+ portable
+
+ IAR
+
+ ARM_CA9
+
+ $PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\port.c
+
+
+ $PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\portASM.h
+
+
+ $PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\portASM.s
+
+
+ $PROJ_DIR$\..\..\..\Source\portable\IAR\ARM_CA9\portmacro.h
+
+
+
+
+ MemMang
+
+ $PROJ_DIR$\..\..\..\Source\portable\MemMang\heap_4.c
+
+
+
+
+ $PROJ_DIR$\..\..\..\Source\list.c
+
+
+ $PROJ_DIR$\..\..\..\Source\queue.c
+
+
+ $PROJ_DIR$\..\..\..\Source\tasks.c
+
+
+ $PROJ_DIR$\..\..\..\Source\timers.c
+
+
+
+ Full-Demo
+
+ Common-Demo-Source
+
+ $PROJ_DIR$\..\..\Common\Minimal\BlockQ.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\blocktim.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\comtest.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\countsem.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\death.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\dynamic.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\flop.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\GenQTest.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\recmutex.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\semtest.c
+
+
+ $PROJ_DIR$\..\..\Common\Minimal\TimerDemo.c
+
+
+
+ FreeRTOS-Plus-CLI
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c
+
+
+
+ FreeRTOS-Plus-FAT-SL
+
+ API
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api\api_mdriver.h
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api\api_mdriver_ram.h
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\api\fat_sl.h
+
+
+
+ Common
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\dir.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\drv.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\f_lock.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\fat.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\file.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\util_sfn.c
+
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\fat_sl\common\volume.c
+
+
+
+ Media-Driver
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\media-drv\ram\ramdrv_f.c
+
+
+
+ rtc
+
+ $PROJ_DIR$\..\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\psp\target\rtc\psp_rtc.c
+
+
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\File-releated-CLI-commands.c
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\File-system-demo.c
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\main_full.c
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\reg_test.s
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\Sample-CLI-commands.c
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\serial.c
+
+
+ $PROJ_DIR$\..\Source\Full-Demo\UARTCommandConsole.c
+
+
+
+ IAR-Files
+
+ $PROJ_DIR$\modules\armv7a_cp15_drv.c
+
+
+
+ Renesas-Files
+
+ include
+
+ $PROJ_DIR$\..\Source\RenesasFiles\include\iodefine.h
+
+
+
+ Initialisation and Drivers
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\common\common_driver\bsc.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\common\userdef\bsc_userdef.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\intc\intc_driver\intc.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\intc\intc_driver\intc_handler.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\intc\userdef\intc_userdef.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\ostm\ostm_driver\ostm.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\board_settings\peripheral_init_basic.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\board_settings\port_init.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\scif_uart\scif_uart_driver\scif_uart.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\drivers\scif_uart\userdef\scif_uart_userdef.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\board_settings\siochar.c
+
+
+ $PROJ_DIR$\..\Source\RenesasFiles\board_settings\stb_init.c
+
+
+
+ $PROJ_DIR$\cstartup.s
+
+
+
+ $PROJ_DIR$\..\Source\FreeRTOS_tick_config.c
+
+
+ $PROJ_DIR$\..\Source\FreeRTOSConfig.h
+
+
+ $PROJ_DIR$\..\Source\LEDs.c
+
+
+ $PROJ_DIR$\LowLevelInitialise.c
+
+
+ $PROJ_DIR$\..\Source\main.c
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.eww
new file mode 100644
index 000000000..5d9b9af90
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/RTOSDemo.eww
@@ -0,0 +1,34 @@
+
+
+
+
+ $WS_DIR$\RTOSDemo.ewp
+
+
+
+ All
+
+ RTOSDemo
+ NOR Debug
+
+
+ RTOSDemo
+ RAM Debug
+
+
+ RTOSDemo
+ SerialFlash Debug
+
+
+ RTOSDemo
+ SerialFlash for Bootloader
+
+
+ Bootloader
+ SerialFlash Bootloader
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/board/arm_comm.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/board/arm_comm.h
new file mode 100644
index 000000000..ebd37de8d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/board/arm_comm.h
@@ -0,0 +1,172 @@
+/***************************************************************************
+ **
+ ** Common definition for IAR EW ARM
+ **
+ ** Used with ARM IAR C/C++ Compiler and Assembler.
+ **
+ ** (c) Copyright IAR Systems 2006
+ **
+ ** $Revision: 52705 $
+ **
+ ***************************************************************************/
+#include
+
+#ifndef __ARM_COMM_DEF_H
+#define __ARM_COMM_DEF_H
+
+#define MHZ *1000000l
+#define KHZ *1000l
+#define HZ *1l
+
+#ifndef FALSE
+#define FALSE (1 == 0)
+#endif
+
+#ifndef TRUE
+#define TRUE (1 == 1)
+#endif
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+typedef double Flo64; // Double precision floating point
+typedef double * pFlo64;
+typedef float Flo32; // Single precision floating point
+typedef float * pFlo32;
+typedef signed long long Int64S; // Signed 64 bit quantity
+typedef signed long long * pInt64S;
+typedef unsigned long long Int64U; // Unsigned 64 bit quantity
+typedef unsigned long long * pInt64U;
+typedef signed int Int32S; // Signed 32 bit quantity
+typedef signed int * pInt32S;
+typedef unsigned int Int32U; // Unsigned 32 bit quantity
+typedef unsigned int * pInt32U;
+typedef signed short Int16S; // Signed 16 bit quantity
+typedef signed short * pInt16S;
+typedef unsigned short Int16U; // Unsigned 16 bit quantity
+typedef unsigned short * pInt16U;
+typedef signed char Int8S; // Signed 8 bit quantity
+typedef signed char * pInt8S;
+typedef unsigned char Int8U; // Unsigned 8 bit quantity
+typedef unsigned char * pInt8U;
+typedef unsigned int Boolean; // Boolean
+typedef unsigned int * pBoolean;
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define _2BL(a) (Int8U)(a),(Int8U)(a>>8)
+#define _2BB(a) (Int8U)(a>>8),(Int8U)(a),
+#define _3BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16)
+#define _3BB(a) (Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)
+#define _4BL(a) (Int8U)(a),(Int8U)(a>>8),(Int8U)(a>>16),(Int8U)(a>>24)
+#define _4BB(a) (Int8U)(a>>24),(Int8U)(a>>16),(Int8U)(a>>8),(Int8U)(a)
+
+typedef void * (*CommUserFpnt_t)(void *);
+typedef void (*VoidFpnt_t)(void);
+
+// Atomic exchange of data between a memory cell and a register
+// return value of the memory cell
+#if __CORE__ < 7
+inline __arm Int32U AtomicExchange (Int32U State, pInt32U Flag)
+{
+ asm("swp r0, r0, [r1]");
+ return(State);
+}
+
+#define IRQ_FLAG 0x80
+#define FIQ_FLAG 0x40
+
+inline __arm Int32U EntrCritSection(void)
+{
+unsigned long tmp;
+ tmp = __get_CPSR();
+ __set_CPSR(tmp | IRQ_FLAG);
+ return(tmp);
+}
+
+inline __arm void ExtCritSection(Int32U Save)
+{
+unsigned long tmp;
+ tmp = __get_CPSR();
+ __set_CPSR(tmp & (Save | ~IRQ_FLAG));
+}
+
+inline __arm Int32U EntrCritSectionFiq(void)
+{
+unsigned long tmp;
+ tmp = __get_CPSR();
+ __set_CPSR(tmp | (IRQ_FLAG | FIQ_FLAG));
+ return(tmp);
+}
+
+inline __arm void ExtCritSectionFiq(Int32U Save)
+{
+unsigned long tmp;
+ tmp = __get_CPSR();
+ __set_CPSR(tmp & (Save | ~(IRQ_FLAG | FIQ_FLAG)));
+}
+
+#define ENTR_CRT_SECTION(Save) Save = EntrCritSection()
+#define EXT_CRT_SECTION(Save) ExtCritSection(Save)
+
+#define ENTR_CRT_SECTION_F(Save) Save = EntrCritSectionFiq()
+#define EXT_CRT_SECTION_F(Save) ExtCritSectionFiq(Save)
+
+#elif __CORE__ == 7
+
+extern Int32U CriticalSecCntr;
+
+inline void EntrCritSection(void)
+{
+ if(CriticalSecCntr == 0)
+ {
+ asm("CPSID i");
+ }
+ // avoid lost of one count in case of simultaneously calling from both places
+ ++CriticalSecCntr;
+}
+
+inline void ExtCritSection(void)
+{
+ if(--CriticalSecCntr == 0)
+ {
+ asm("CPSIE i");
+ }
+}
+
+inline Int32U AtomicExchange (Int32U State, pInt32U Flag)
+{
+Int32U Hold;
+ EntrCritSection();
+ Hold = *Flag;
+ *Flag = State;
+ ExtCritSection();
+ return(Hold);
+}
+
+#define ENTR_CRT_SECTION() EntrCritSection()
+#define EXT_CRT_SECTION() ExtCritSection()
+#endif
+
+#define LongToBin(n) (((n >> 21) & 0x80) | \
+ ((n >> 18) & 0x40) | \
+ ((n >> 15) & 0x20) | \
+ ((n >> 12) & 0x10) | \
+ ((n >> 9) & 0x08) | \
+ ((n >> 6) & 0x04) | \
+ ((n >> 3) & 0x02) | \
+ ((n ) & 0x01))
+
+#define __BIN(n) LongToBin(0x##n##l)
+
+#define BIN8(n) __BIN(n)
+#define BIN(n) __BIN(n)
+#define BIN16(b1,b2) (( __BIN(b1) << 8UL) + \
+ __BIN(b2))
+#define BIN32(b1,b2,b3,b4) ((((Int32U)__BIN(b1)) << 24UL) + \
+ (((Int32U)__BIN(b2)) << 16UL) + \
+ (((Int32U)__BIN(b3)) << 8UL) + \
+ (Int32U)__BIN(b4))
+
+#endif // __ARM_COMM_DEF_H
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.icf b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.icf
new file mode 100644
index 000000000..caed4456f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.icf
@@ -0,0 +1,59 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000040;
+define symbol __ICFEDIT_region_ROM_end__ = 0x07FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x8000;
+define symbol __ICFEDIT_size_svcstack__ = 0x40;
+define symbol __ICFEDIT_size_irqstack__ = 0x40;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
+
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
+
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
+
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+do not initialize { section MMU_TT };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+
+place in RetRAM_region { section .retram };
+place in MirrorRAM_region { section .mirrorram };
+place in MirrorRetRAM_region { section .mirrorretram };
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.mac b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.mac
new file mode 100644
index 000000000..48f006f1b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_NOR.mac
@@ -0,0 +1,32 @@
+setup()
+{
+__var Reg;
+
+ // Enable I Cache
+ // Disable MMU and enable ICache
+ Reg = __jtagCP15ReadReg(1, 0, 0, 0);
+ Reg &= 0xFFFFFFFA;
+ Reg |= 1<<12;
+ __jtagCP15WriteReg(1, 0, 0, 0, Reg);
+
+ __writeMemory16(0x0000FF41, 0xFCFE721C, "Memory"); // set PIPC7.6 direction controlled by alt.WE0
+ __writeMemory16(0x0000FF41, 0xFCFE341C, "Memory"); // set PMC7.6 to be alt.WE0
+
+ __writeMemory16(0x0000FFFF, 0xFCFE7220, "Memory"); // set PIPC8 direction controlled by alt.A8-A23
+ __writeMemory16(0x0000FFFF, 0xFCFE3420, "Memory"); // set PMC8 to be alt.A8-A23
+
+ __writeMemory16(0x00000003, 0xFCFE7224, "Memory"); // set PIPC9 direction controlled by alt.A24-A25
+ __writeMemory16(0x00000003, 0xFCFE3424, "Memory"); // set PMC9 to be alt.A24-A25
+
+ __writeMemory16(0x00000080, 0xFCFE720C, "Memory"); // set PIPC3 direction controlled by alt.CS1
+ __writeMemory16(0x00000080, 0xFCFE340C, "Memory"); // set PMC3 to be alt.CS1
+ __writeMemory16(0x00000080, 0xFCFE360C, "Memory"); // set PFCE3 to be alt.CS1
+ __writeMemory16(0x00000080, 0xFCFE3A0C, "Memory"); // set PFCAE3 to be alt.CS1
+}
+
+execUserPreload()
+{
+ __message "----- Prepare hardware for debug -----\n";
+ __hwReset(0);
+ setup();
+}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.icf b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.icf
new file mode 100644
index 000000000..2c2e175f7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.icf
@@ -0,0 +1,59 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x18000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x18000040;
+define symbol __ICFEDIT_region_ROM_end__ = 0x1807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x8000;
+define symbol __ICFEDIT_size_svcstack__ = 0x40;
+define symbol __ICFEDIT_size_irqstack__ = 0x40;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
+
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
+
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
+
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+do not initialize { section MMU_TT };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+
+place in RetRAM_region { section .retram };
+place in MirrorRAM_region { section .mirrorram };
+place in MirrorRetRAM_region { section .mirrorretram };
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.mac b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.mac
new file mode 100644
index 000000000..bcbc48c59
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash.mac
@@ -0,0 +1,57 @@
+setup()
+{
+__var Reg;
+
+ // Enable I Cache
+ // Disable MMU and enable ICache
+ Reg = __jtagCP15ReadReg(1, 0, 0, 0);
+ Reg &= 0xFFFFFFFA;
+ Reg |= 1<<12;
+ __jtagCP15WriteReg(1, 0, 0, 0, Reg);
+
+ //__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR
+ //__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2
+
+ // Turn on clock for SPI
+ __writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9
+
+ // Configure PORTS for SPI (serial flash 1)
+ __writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode
+ __writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode
+ __writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode
+
+ // Configure PORTS for SPI (serial flash 2)
+ __writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode
+ __writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode
+ __writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode
+ __writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode
+
+ // Configure SPI for EXTREAD mode
+ __writeMemory32(0x01AA4020, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 1-memory, CPHA=0, CPOL=0, SFDE=1
+
+ // Configure SPI registers
+ __writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13
+ __writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1
+ __writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst
+ __writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range
+
+ // Set Bit Rate
+ __writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3
+
+ // Flush Read Cache
+ Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR_0
+ Reg |= 0x00000200; // Set RCF bit
+ __writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR_0
+}
+
+execUserPreload()
+{
+ __message "----- Prepare hardware for debug -----\n";
+ __hwReset(0);
+ setup();
+}
+
+execUserReset()
+{
+ setup();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.icf b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.icf
new file mode 100644
index 000000000..1917c8388
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.icf
@@ -0,0 +1,59 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x18080000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x18080040;
+define symbol __ICFEDIT_region_ROM_end__ = 0x1BFFFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x8000;
+define symbol __ICFEDIT_size_svcstack__ = 0x40;
+define symbol __ICFEDIT_size_irqstack__ = 0x40;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
+
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
+
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
+
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+do not initialize { section MMU_TT };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+
+place in RetRAM_region { section .retram };
+place in MirrorRAM_region { section .mirrorram };
+place in MirrorRetRAM_region { section .mirrorretram };
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.mac b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.mac
new file mode 100644
index 000000000..f49aab9d5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/config/RTK772100FC00000BR_SerialFlash_app.mac
@@ -0,0 +1,57 @@
+setup()
+{
+__var Reg;
+
+ // Enable I Cache
+ // Disable MMU and enable ICache
+ Reg = __jtagCP15ReadReg(1, 0, 0, 0);
+ Reg &= 0xFFFFFFFA;
+ Reg |= 1<<12;
+ __jtagCP15WriteReg(1, 0, 0, 0, Reg);
+
+ //__writeMemory16(0x0035, 0xFCFE0010, "Memory"); // FRQCR
+ //__writeMemory16(0x0001, 0xFCFE0014, "Memory"); // FRQCR2
+
+ // Turn on clock for SPI
+ __writeMemory8(0x00, 0xFCFE0438, "Memory"); // PDM_STBCR9
+
+ // Configure PORTS for SPI (serial flash 1)
+ __writeMemory16(0x00FC, 0xFCFE7224, "Memory"); // PIPC9 2-7 -> alt IO mode
+ __writeMemory16(0x00FC, 0xFCFE3424, "Memory"); // PMC9 2-7 -> alt mode
+ __writeMemory16(0x00FC, 0xFCFE3524, "Memory"); // PFC9 2-7 -> alt mode
+
+ // Configure PORTS for SPI (serial flash 2)
+ __writeMemory16(0xF000, 0xFCFE7208, "Memory"); // PIPC2 12-15 -> alt IO mode
+ __writeMemory16(0xF000, 0xFCFE3408, "Memory"); // PMC2 12-15 -> alt mode
+ __writeMemory16(0xF000, 0xFCFE3508, "Memory"); // PFC2 12-15 -> alt mode
+ __writeMemory16(0xF000, 0xFCFE3608, "Memory"); // PFCE2 12-15 -> alt mode
+
+ // Configure SPI for EXTREAD mode
+ __writeMemory32(0x01AA4021, 0x3FEFA000, "Memory"); // SPIBSC_CMNCR 2-memory, CPHAT=0, CPHAR=1, CPOL=0, SFDE=1
+
+ // Configure SPIBSC 32-bit addressing
+ __writeMemory32(0x00130000, 0x3FEFA010, "Memory"); // SPIBSC_DRCMR CMD = 0x13
+ __writeMemory32(0x00004F00, 0x3FEFA01C, "Memory"); // SPIBSC_DRENR ADE = 0xF, CDE=1
+ __writeMemory32(0x00010101, 0x3FEFA00C, "Memory"); // SPIBSC_DRCR enable burst
+ __writeMemory32(0x00000001, 0x3FEFA014, "Memory"); // SPIBSC_DREAR enable extended address range
+
+ // Set Bit Rate
+ __writeMemory32(0x00000003, 0x3FEFA008, "Memory"); // SPIBSC_SPBCR SPBR=0, BRDV=3
+
+ // Flush Read Cache
+ Reg = __readMemory32(0x3FEFA00C, "Memory"); // Read SPIBSC_DRCR
+ Reg |= 0x00000200; // Set RCF bit
+ __writeMemory32(Reg, 0x3FEFA00C, "Memory"); // Set SPIBSC_DRCR
+}
+
+execUserPreload()
+{
+ __message "----- Prepare hardware for debug -----\n";
+ __hwReset(0);
+ setup();
+}
+
+execUserReset()
+{
+ setup();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/cstartup.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/cstartup.s
new file mode 100644
index 000000000..057f6d792
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/cstartup.s
@@ -0,0 +1,173 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Part one of the system initialization code,
+;; contains low-level
+;; initialization.
+;;
+;; Copyright 2007 IAR Systems. All rights reserved.
+;;
+;; $Revision: 49919 $
+;;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION CSTACK:DATA:NOROOT(3)
+
+;
+; The module in this file are included in the libraries, and may be
+; replaced by any user-defined modules that define the PUBLIC symbol
+; __iar_program_start or a user defined start symbol.
+;
+; To override the cstartup defined in the library, simply add your
+; modified version to the workbench project.
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ PUBLIC __vector
+ PUBLIC __iar_program_start
+ EXTERN Undefined_Handler
+ EXTERN SWI_Handler
+ EXTERN Prefetch_Handler
+ EXTERN Abort_Handler
+ EXTERN IRQ_Handler
+ EXTERN FIQ_Handler
+ EXTERN LowLevelInitialisation
+
+ DATA
+
+__iar_init$$done: ; The vector table is not needed
+ ; until after copy initialization is done
+
+__vector: ; Make this a DATA label, so that stack usage
+ ; analysis doesn't consider it an uncalled fun
+
+ ARM
+
+ ; All default exception handlers (except reset) are
+ ; defined as weak symbol definitions.
+ ; If a handler is defined by the application it will take precedence.
+ LDR PC,Reset_Addr ; Reset
+ LDR PC,Undefined_Addr ; Undefined instructions
+ LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
+ LDR PC,Prefetch_Addr ; Prefetch abort
+ LDR PC,Abort_Addr ; Data abort
+ DCD 0 ; RESERVED
+ LDR PC,IRQ_Addr ; IRQ
+ LDR PC,FIQ_Addr ; FIQ
+
+ DATA
+
+Reset_Addr: DCD __iar_program_start
+Undefined_Addr: DCD Undefined_Handler
+SWI_Addr: DCD SWI_Handler
+Prefetch_Addr: DCD Prefetch_Handler
+Abort_Addr: DCD Abort_Handler
+IRQ_Addr: DCD IRQ_Handler
+FIQ_Addr: DCD FIQ_Handler
+
+
+; --------------------------------------------------
+; ?cstartup -- low-level system initialization code.
+;
+; After a reset execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+;
+
+
+
+ SECTION .text:CODE:NOROOT(2)
+
+ EXTERN __cmain
+ REQUIRE __vector
+ EXTWEAK __iar_init_core
+ EXTWEAK __iar_init_vfp
+
+
+ ARM
+
+__iar_program_start:
+?cstartup:
+
+;
+; Add initialization needed before setup of stackpointers here.
+;
+
+;
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+;
+
+
+; --------------------
+; Mode, correspords to bits 0-5 in CPSR
+
+#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR
+
+#define USR_MODE 0x10 ; User mode
+#define FIQ_MODE 0x11 ; Fast Interrupt Request mode
+#define IRQ_MODE 0x12 ; Interrupt Request mode
+#define SVC_MODE 0x13 ; Supervisor mode
+#define ABT_MODE 0x17 ; Abort mode
+#define UND_MODE 0x1B ; Undefined Instruction mode
+#define SYS_MODE 0x1F ; System mode
+
+
+ MRS r0, cpsr ; Original PSR value
+
+ ;; Set up the interrupt stack pointer.
+
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits
+ ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+ ;; Set up the fast interrupt stack pointer.
+
+ BIC r0, r0, #MODE_MSK ; Clear the mode bits
+ ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+ ;; Set up the normal SVC pointer.
+;; FreeRTOS Note:
+;; FreeRTOS does not need a System/User mode stack as only tasks run in
+;; System/User mode, and their stack is allocated when the task is created.
+;; Therefore the CSTACK allocated in the linker script is instead given to
+;; Supervisor mode, and main() is called from Supervisor mode.
+ BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
+ ORR r0 ,r0, #SVC_MODE ; Set System mode bits
+ MSR cpsr_c, r0 ; Change the mode
+ LDR sp, =SFE(CSTACK) ; End of CSTACK
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
+
+ ;; Turn on core features assumed to be enabled.
+ FUNCALL __iar_program_start, __iar_init_core
+ BL __iar_init_core
+
+ ;; Initialize VFP (if needed).
+ FUNCALL __iar_program_start, __iar_init_vfp
+ BL __iar_init_vfp
+
+ ;; Chip and board specific configuration
+ BL LowLevelInitialisation
+
+;;;
+;;; Add more initialization here
+;;;
+
+;;; Continue to __cmain for C-level initialization.
+
+ FUNCALL __iar_program_start, __cmain
+ B __cmain
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.c
new file mode 100644
index 000000000..4e3fffe93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.c
@@ -0,0 +1,768 @@
+/*************************************************************************
+ *
+ * Used with ICCARM and AARM.
+ *
+ * (c) Copyright IAR Systems 2012
+ *
+ * File name : armv7a_cp15_drv.c
+ * Description : Driver for the CP15 of ARMv7-A
+ *
+ * History :
+ * 1. Date : September, 8 2006
+ * Author : Stanimir Bonev
+ * Description : Driver for the ARM926EJ's CP15
+ *
+ * 2. Date : October, 2008
+ * Author : Stoyan Choynev
+ * Description : Port for ARM1136JF. The driver is backwards compatible
+ * with ARMv5 or earlier processors.
+ *
+ * 3. Date : March, 2012
+ * Author : Atanas Uzunov
+ * Description : Port for ARMv7-A architecture.
+ * Added cache maintenance functions.
+ *
+ * $Revision: 52705 $
+ **************************************************************************/
+
+#include "armv7a_cp15_drv.h"
+
+/*************************************************************************
+ * Function Name: CP15_GetID
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the ID register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetID (void)
+{
+ return(__MRC(15,0,CP15_ID,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetCacheType
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the Cache type
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetCacheType (void)
+{
+ return(__MRC(15,0,CP15_ID,0,1));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetTCM_Status
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the TCM status
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetTCM_Status (void)
+{
+ return(__MRC(15,0,CP15_ID,0,2));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetTtb0
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the TTB0 register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetTtb0 (void)
+{
+ return(__MRC(15,0,CP15_TTB_ADDR,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetTtb1
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the TTB1 register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetTtb1 (void)
+{
+ return(__MRC(15,0,CP15_TTB_ADDR,0,1));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetStatus
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the MMU control register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetStatus (void)
+{
+ return(__MRC(15,0,CP15_CTRL,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetDomain
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the MMU domain access register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetDomain (void)
+{
+ return(__MRC(15,0,CP15_DA_CTRL,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetDomains
+ * Parameters: Int32U DomainAccess
+ *
+ * Return: Int32U
+ *
+ * Description: Function set the MMU domain access register
+ *
+ *************************************************************************/
+__arm void CP15_SetDomains (Int32U DomainAccess)
+{
+register Int32U Val = DomainAccess;
+ __MCR(15,0,Val,CP15_DA_CTRL,0,0);
+}
+
+/*************************************************************************
+ * Function Name: log2_n_up
+ * Parameters: Int32U n
+ *
+ * Return: Int32S
+ *
+ * Description: Logarithm at base 2 , rounded up
+ *
+ *************************************************************************/
+Int32S log2_up(Int32U n)
+{
+ Int32S log = -1;
+ Int32U t = n;
+ while(t)
+ {
+ log++; t >>=1;
+ }
+ /* if n not power of 2 -> round up*/
+ if ( n & (n - 1) ) log++;
+ return log;
+}
+
+/*************************************************************************
+ * Function Name: CP15_MaintainDCacheSetWay
+ * Parameters: Int32U level - level of cache,
+ * Int32U maint - maintenance type
+ *
+ * Return: none
+ *
+ * Description: Maintain data cache line by Set/Way
+ *
+ *************************************************************************/
+__arm void CP15_MaintainDCacheSetWay(Int32U level, Int32U maint)
+{
+register volatile Int32U Dummy;
+register volatile Int32U ccsidr;
+Int32U num_sets;
+Int32U num_ways;
+Int32U shift_way;
+Int32U log2_linesize;
+Int32U log2_num_ways;
+
+ Dummy = level << 1;
+ /* set csselr, select ccsidr register */
+ __MCR(15,2,Dummy,0,0,0);
+ /* get current ccsidr register */
+ ccsidr = __MRC(15,1,0,0,0);
+ num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1;
+ num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1;
+ log2_linesize = (ccsidr & 0x00000007) + 2 + 2;
+ log2_num_ways = log2_up(num_ways);
+ shift_way = 32 - log2_num_ways;
+ for(int way = num_ways-1; way >= 0; way--)
+ for(int set = num_sets-1; set >= 0; set--)
+ {
+ Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way);
+ switch (maint)
+ {
+ case DCACHE_CLEAN_AND_INVALIDATE:
+ __MCR(15,0,Dummy,7,14,2);
+ break;
+
+ case DCACHE_INVALIDATE:
+ __MCR(15,0,Dummy,7,6,2);
+ break;
+ }
+ }
+ __DMB();
+}
+
+/*************************************************************************
+ * Function Name: CP15_MaintAllDCache
+ * Parameters: Int32U oper - type of maintenance, one of:
+ * DCACHE_CLEAN_AND_INVALIDATE
+ * DCACHE_INVALIDATE
+ *
+ * Return: none
+ *
+ * Description: Maintenance of all data cache
+ *
+ *************************************************************************/
+__arm void CP15_MaintainAllDCache(Int32U oper)
+{
+register volatile Int32U clidr;
+Int32U cache_type;
+ clidr = __MRC(15,1,0,0,1);
+ for(Int32U i = 0; i<7; i++)
+ {
+ cache_type = (clidr >> i*3) & 0x7UL;
+ if ((cache_type >= 2) && (cache_type <= 4))
+ {
+ CP15_MaintainDCacheSetWay(i,oper);
+ }
+ }
+}
+
+/*************************************************************************
+ * Function Name: CP15_InvalInstrCache
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Invalidate instruction cache
+ *
+ *************************************************************************/
+__arm void CP15_InvalInstrCache(void)
+{
+register volatile Int32U Dummy;
+ __MCR(15,0,Dummy,CP15_CACHE_OPR,5,0);
+ CP15_InvalPredictArray();
+ __DSB();
+ __ISB();
+}
+
+/*************************************************************************
+ * Function Name: CP15_InvalPredictArray
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Invalidate prediction array
+ *
+ *************************************************************************/
+__arm void CP15_InvalPredictArray(void)
+{
+register volatile Int32U Dummy;
+ __MCR(15,0,Dummy,CP15_CACHE_OPR,5,6); __ISB();
+}
+
+/*************************************************************************
+ * Function Name: CP15_InvalAllTbl
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Invalidate TLB
+ *
+ *************************************************************************/
+__arm void CP15_InvalAllTbl (void)
+{
+register volatile Int32U Dummy;
+ /* Invalidate entire unified TLB*/
+ __MCR(15,0,Dummy,CP15_TBL_OPR,7,0);
+ /* Invalidate entire data TLB*/
+ __MCR(15,0,Dummy,CP15_TBL_OPR,6,0);
+ /* Invalidate entire instruction TLB*/
+ __MCR(15,0,Dummy,CP15_TBL_OPR,5,0);
+ __DSB();
+ __ISB();
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetStatus
+ * Parameters: Int32U Ctrl
+ *
+ * Return: none
+ *
+ * Description: Set CP15 CTR (control) register
+ *
+ *************************************************************************/
+__arm void CP15_SetStatus (Int32U Ctrl)
+{
+register volatile Int32U Val = Ctrl;
+ __MCR(15,0,Val,CP15_CTRL,0,0);
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetTtb0
+ * Parameters: pInt32U pTtb
+ *
+ * Return: none
+ *
+ * Description: Set CP15 TTB0 base address register
+ *
+ *************************************************************************/
+__arm void CP15_SetTtb0 (pInt32U pTtb)
+{
+register volatile Int32U Val = (Int32U)pTtb;
+ __MCR(15,0,Val,CP15_TTB_ADDR,0,0);
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetTtb1
+ * Parameters: pInt32U pTtb
+ *
+ * Return: none
+ *
+ * Description: Set CP15 TTB1 base address register
+ *
+ *************************************************************************/
+__arm void CP15_SetTtb1 (pInt32U pTtb)
+{
+register volatile Int32U Val = (Int32U)pTtb;
+ __MCR(15,0,Val,CP15_TTB_ADDR,0,1);
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetDac
+ * Parameters: Int32U da
+ *
+ * Return: none
+ *
+ * Description: Set CP15 domain access register
+ *
+ *************************************************************************/
+__arm void CP15_SetDac (Int32U da)
+{
+register volatile Int32U Val = da;
+ __MCR(15,0,Val,CP15_DA_CTRL,0,0);
+}
+
+/*************************************************************************
+ * Function Name: CP15_WriteBuffFlush
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Flush the write buffer and wait for completion
+ * of the flush.
+ *
+ *************************************************************************/
+__arm void CP15_WriteBuffFlush (void)
+{
+register volatile Int32U Val;
+ __MCR(15,0,Val,CP15_CACHE_OPR,10,4);
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetFaultStat
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the MMU fault status register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetFaultStat (void)
+{
+ return(__MRC(15,0,CP15_FAULT_STAT,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetFaultAddr
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the MMU fault address register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetFaultAddr (void)
+{
+ return(__MRC(15,0,CP15_FAULT_ADDR,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetFcsePid
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the MMU Process identifier
+ * FCSE PID register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetFcsePid (void)
+{
+ return(__MRC(15,0,CP15_PROCESS_IDNF,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetPraceProcId
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returns the MMU Trace Process identifier
+ * register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetPraceProcId (void)
+{
+ return(__MRC(15,0,CP15_PROCESS_IDNF,0,1));
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetFcsePid
+ * Parameters: Int32U FcsePid
+ *
+ * Return: none
+ *
+ * Description: Function set the MMU Process identifier
+ * FCSE PID register
+ *
+ *************************************************************************/
+__arm void CP15_SetFcsePid (Int32U FcsePid)
+{
+register Int32U Val = FcsePid;
+ __MCR(15,0,Val,CP15_PROCESS_IDNF,0,0);
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetPraceProcId
+ * Parameters: Int32U
+ *
+ * Return: none
+ *
+ * Description: Function set the MMU Trace Process identifier
+ * register
+ *
+ *************************************************************************/
+__arm void CP15_SetPraceProcId(Int32U Trace)
+{
+register Int32U Val = Trace;
+ __MCR(15,0,Val,CP15_PROCESS_IDNF,0,1);
+}
+
+/*************************************************************************
+ * Function Name: CP15_InitMmuTtb
+ * Parameters: pTtSectionBlock_t pTtSB, pTtTableBlock_t pTtTB
+ *
+ * Return: Boolean
+ *
+ * Returns error if MMU is enabled or if target
+ * Translation Table address is not 16K aligned. Clear the
+ * Translation Table area. Build the Translation Table from the
+ * initialization data in the Section Block array. Return no error.
+ *
+ * Description: Initializes the MMU tables.
+ *
+ *
+ *************************************************************************/
+Boolean CP15_InitMmuTtb(const TtSectionBlock_t * pTtSB,
+ const TtTableBlock_t * pTtTB)
+{
+Int32U i, pa, pa_inc, va_ind;
+pInt32U pTtb;
+TableType_t TableType;
+ while(1)
+ {
+ TableType = pTtTB->TableType;
+ switch(TableType)
+ {
+ case TableL1:
+ pTtb = pTtTB->TableAddr;
+ if((Int32U)pTtb & L1_ENTRIES_NUMB-1)
+ {
+ return(FALSE);
+ }
+ pa_inc = 0x100000;
+ pa = L1_ENTRIES_NUMB;
+ break;
+ case TableL2_PageTable:
+ pTtb = pTtTB->TableAddr;
+ if((Int32U)pTtb & L2_CP_ENTRIES_NUMB-1)
+ {
+ return(FALSE);
+ }
+ pa_inc = 0x1000;
+ pa = L2_CP_ENTRIES_NUMB;
+ break;
+ default:
+ return(TRUE);
+ }
+
+ // Clear the entire Translation Table This results in LxD_TYPE_FAULT
+ // being the default for any uninitialized entries.
+ for(i = 0; i < pa; ++i)
+ {
+ *(pTtb+i) = TT_ENTRY_INVALID;
+ }
+
+ // Build the translation table from user provided pTtSectionBlock_t array
+ while(pTtSB->NubrOfSections != 0)
+ {
+Int32U Entrys = pTtSB->NubrOfSections;
+Int32U Data = pTtSB->Entry.Data;
+ pa = pTtSB->PhysAddr;
+
+ switch(TableType)
+ {
+ case TableL1:
+ va_ind = (pTtSB->VirtAddr >> 20) & (L1_ENTRIES_NUMB-1);
+
+ if((va_ind + Entrys) > L1_ENTRIES_NUMB)
+ {
+ return(FALSE);
+ }
+ break;
+ case TableL2_PageTable:
+ va_ind = (pTtSB->VirtAddr >> 12) & (L2_CP_ENTRIES_NUMB-1);
+ if((va_ind + Entrys) > L2_CP_ENTRIES_NUMB)
+ {
+ return(FALSE);
+ }
+ break;
+ }
+ for(i = 0; i < Entrys; ++i, ++va_ind)
+ {
+ switch(TableType)
+ {
+ case TableL1:
+ switch(pTtSB->Entry.Type)
+ {
+ case TtL1PageTable:
+ *(pTtb+va_ind) |= Data | (pa & TTL1_PT_PADDR_MASK);
+ break;
+ case TtL1Section:
+ *(pTtb+va_ind) |= Data | (pa & TTL1_SECTION_PADDR_MASK);
+ break;
+ case TtL1SuperSection:
+ *(pTtb+va_ind) |= Data | (pa & TTL1_S_SECTION_PADDR_MASK);
+ break;
+ default:
+ return(FALSE);
+ }
+ break;
+ case TableL2_PageTable:
+ switch(pTtSB->Entry.Type)
+ {
+ case TtL2LargePage:
+ *(pTtb+va_ind) |= Data | (pa & TTL2_LP_PADDR_MASK);
+ break;
+ case TtL2SmallPage:
+ *(pTtb+va_ind) |= Data | (pa & TTL2_SP_PADDR_MASK);
+ break;
+ default:
+ return(FALSE);
+ }
+ break;
+ }
+ pa += pa_inc;
+ }
+ ++pTtSB;
+ }
+ ++pTtSB;
+ ++pTtTB;
+ }
+}
+
+/*************************************************************************
+ * Function Name: CP15_Mmu
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable MMU
+ *
+ *************************************************************************/
+void CP15_Mmu(Boolean Enable)
+{
+Int32U Val = CP15_GetStatus();
+ if(Enable)
+ {
+ CP15_InvalAllTbl();
+ Val |= CP15_CTRL_M;
+ }
+ else
+ {
+ Val &= ~(CP15_CTRL_M | CP15_CTRL_C);
+ }
+ CP15_SetStatus(Val);
+}
+
+/*************************************************************************
+ * Function Name: CP15_Cache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable Both Cache
+ *
+ *************************************************************************/
+void CP15_Cache(Boolean Enable)
+{
+Int32U Val = CP15_GetStatus();
+ if(Enable)
+ {
+ Val |= CP15_CTRL_M | CP15_CTRL_C | CP15_CTRL_I;
+ }
+ else
+ {
+ Val &= ~CP15_CTRL_C;
+ }
+ CP15_SetStatus(Val);
+}
+
+/*************************************************************************
+ * Function Name: CP15_InvalidateCache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Invalidate Cache
+ *
+ *************************************************************************/
+void CP15_InvalidateCache()
+{
+ CP15_MaintainAllDCache(DCACHE_INVALIDATE);
+ __DSB();
+ CP15_InvalInstrCache(); /* includes invalidation of branch predictor */
+ __DSB();
+ __ISB();
+}
+
+/*************************************************************************
+ * Function Name: CP15_ICache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable I cache
+ *
+ *************************************************************************/
+void CP15_ICache (Boolean Enable)
+{
+Int32U Val = CP15_GetStatus();
+ if(Enable)
+ {
+ Val |= CP15_CTRL_I;
+ }
+ else
+ {
+ Val &= ~CP15_CTRL_I;
+ }
+ CP15_SetStatus(Val);
+}
+
+/*************************************************************************
+ * Function Name: CP15_DCache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable D cache
+ *
+ *************************************************************************/
+void CP15_DCache (Boolean Enable)
+{
+Int32U Val = CP15_GetStatus();
+ if(Enable)
+ {
+ Val |= CP15_CTRL_M | CP15_CTRL_C;
+ }
+ else
+ {
+ Val &= ~CP15_CTRL_C;
+ }
+ CP15_SetStatus(Val);
+}
+
+/*************************************************************************
+ * Function Name: CP15_ProgFlowPrediction
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable program flow prediction.
+ *
+ *************************************************************************/
+void CP15_ProgFlowPrediction (Boolean Enable)
+{
+Int32U Val = CP15_GetStatus();
+ if(Enable)
+ {
+ CP15_InvalPredictArray();
+ Val |= CP15_CTRL_Z;
+ }
+ else
+ {
+ Val &= ~CP15_CTRL_Z;
+ }
+ CP15_SetStatus(Val);
+}
+
+/*************************************************************************
+ * Function Name: CP15_GetVectorBase
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Get Vector Base Register (VBAR)
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetVectorBase(void)
+{
+ return(__MRC(15,0,CP15_VBAR,0,0));
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetVectorBase
+ * Parameters: Int32U
+ *
+ * Return: none
+ *
+ * Description: Set Vector Base Register (VBAR)
+ *
+ *************************************************************************/
+__arm void CP15_SetVectorBase(Int32U vector)
+{
+register volatile Int32U Val = vector;
+ __MCR(15,0,Val,CP15_VBAR,0,0);
+}
+
+/*************************************************************************
+ * Function Name: CP15_SetHighVectors
+ * Parameters: Boolean
+ *
+ * Return: none
+ *
+ * Description: Select High or Low vectors base in CP15 control register
+ *
+ *************************************************************************/
+__arm void CP15_SetHighVectors(Boolean Enable)
+{
+Int32U Val = CP15_GetStatus();
+ if(Enable)
+ {
+ Val |= CP15_CTRL_V;
+ }
+ else
+ {
+ Val &= ~CP15_CTRL_V;
+ }
+ CP15_SetStatus(Val);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.h
new file mode 100644
index 000000000..616c74dbe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/modules/armv7a_cp15_drv.h
@@ -0,0 +1,567 @@
+/*************************************************************************
+ *
+ * Used with ICCARM and AARM.
+ *
+ * (c) Copyright IAR Systems 2012
+ *
+ * File name : armv7a_cp15_drv.h
+ * Description : Definitions of a driver for the CP15 of ARMv7-A
+ *
+ * History :
+ * 1. Date : September, 8 2006
+ * Author : Stanimir Bonev
+ * Description : Create
+ *
+ * 2. Date : October, 2008
+ * Author : Stoyan Choynev
+ * Description : Port for ARM1136JF. The driver is backwards compatible with ARMv5 or earlier
+ * processors
+ *
+ * 3. Date : March, 2012
+ * Author : Atanas Uzunov
+ * Description : Port for ARMv7-A architecture.
+ * Added cache maintenance functions.
+ *
+ * $Revision: 52705 $
+ **************************************************************************/
+#include
+#include "arm_comm.h"
+
+#ifndef __ARMV7A_CP15_DRV_H
+#define __ARMV7A_CP15_DRV_H
+
+#define NON_CACHABLE_ADDR 0xFFFFFFFC
+
+#define L1_ENTRIES_NUMB 4096
+#define L2_CP_ENTRIES_NUMB 256
+
+#define DCACHE_CLEAN_AND_INVALIDATE 1
+#define DCACHE_INVALIDATE 2
+
+#define TSB_INVALID { 0, 0, 0, 0 }
+#define TTB_INVALID { 0, TableInvalid }
+
+#define L1_PAGE_TABLE_ENTRY(Numb, VirtAddr ,PhAddr, Domain, NS) \
+ { Numb, VirtAddr, PhAddr, \
+ ((Domain << 5) | (NS << 3) | \
+ TtL1PageTable)}
+
+#define L1_SECTION_ENTRY(Numb, VirtAddr ,PhAddr, NS, nG, S, AP2, TEX, AP01, Domain, XN, C, B) \
+ { Numb, VirtAddr, PhAddr, \
+ ((NS << 19) | (nG << 17) | (S << 16) | (AP2 << 15) | (TEX << 12) | (AP01 << 10) | (Domain << 5) | (XN << 4) | (C << 3) | (B << 2) | \
+ TtL1Section)}
+
+#define L1_SUPERSECTION_ENTRY(Numb, VirtAddr, PhAddr, ExtBaseAddr, NS, nG, S, AP2, TEX, AP01, Domain, XN, C, B) \
+ { Numb*16, VirtAddr, PhAddr, \
+ (((ExtBaseAddr&0x0FUL) << 20) | (((ExtBaseAddr&0xF0UL)>>4) << 5) | (NS << 19) | (nG << 17) | (S << 16) | (AP2 << 15) | (TEX << 12) | (AP01 << 10) | (Domain << 5) | (XN << 4) | (C << 3) | (B << 2) | \
+ TtL1SuperSection)}
+
+#define L2_LARGE_PAGE_ENTRY(Numb, VirtAddr ,PhAddr, XN, TEX, nG, S, AP2, AP01, C, B) \
+ { Numb*16, VirtAddr, PhAddr, \
+ ((XN << 15) | (TEX << 12) | (nG << 11) | (S << 10) | (AP2 << 9) | (AP01 << 4) | (C << 3) | (B << 2) | \
+ TtL2LargePage)}
+
+#define L2_SMALL_PAGE_ENTRY(Numb, VirtAddr ,PhAddr, XN, TEX, nG, S, AP2, AP01, C, B) \
+ { Numb, VirtAddr, PhAddr, \
+ ((nG << 11) | (S << 10) | (AP2 << 9) | (TEX<<6) | (AP01 << 4) | (C << 3) | (B << 2) | (XN << 0) | \
+ TtL2SmallPage)}
+
+// CP15 Registers
+// ID register
+#define CP15_ID 0
+
+// Control register
+#define CP15_CTRL 1
+// CP15 Control register bits
+#define CP15_CTRL_M (1UL << 0) // MMU enable/disable
+#define CP15_CTRL_A (1UL << 1) // Alignment fault enable/disable
+#define CP15_CTRL_C (1UL << 2) // DCache enable/disable
+#define CP15_CTRL_Z (1UL << 11) // Program flow prediction
+#define CP15_CTRL_I (1UL << 12) // ICache enable/disable
+#define CP15_CTRL_V (1UL << 13) // Location of exception vectors
+#define CP15_CTRL_EE (1UL << 25) // CPSR E bit on exception
+#define CP15_CTRL_NMFI (1UL << 27) // FIQ enable bit (1 - FIQ cannot be masked) READ-ONLY
+#define CP15_CTRL_TRE (1UL << 28) // TEX remap functionality bit. (TEX enabled/disabled)
+#define CP15_CTRL_AFE (1UL << 29) // Access Flag Enable bit.
+#define CP15_CTRL_TE (1UL << 30) // Thumb Exception enable bit.
+
+// Translation table base address (alignment 4KB)
+#define CP15_TTB_ADDR 2
+
+// Domain access control register
+#define CP15_DA_CTRL 3
+
+#define CP15_DA_CTRL_D0(Val) ((Val & 0x3) << 0)
+#define CP15_DA_CTRL_D1(Val) ((Val & 0x3) << 2)
+#define CP15_DA_CTRL_D2(Val) ((Val & 0x3) << 4)
+#define CP15_DA_CTRL_D3(Val) ((Val & 0x3) << 6)
+#define CP15_DA_CTRL_D4(Val) ((Val & 0x3) << 8)
+#define CP15_DA_CTRL_D5(Val) ((Val & 0x3) << 10)
+#define CP15_DA_CTRL_D6(Val) ((Val & 0x3) << 12)
+#define CP15_DA_CTRL_D7(Val) ((Val & 0x3) << 14)
+#define CP15_DA_CTRL_D8(Val) ((Val & 0x3) << 16)
+#define CP15_DA_CTRL_D9(Val) ((Val & 0x3) << 18)
+#define CP15_DA_CTRL_D10(Val) ((Val & 0x3) << 20)
+#define CP15_DA_CTRL_D11(Val) ((Val & 0x3) << 22)
+#define CP15_DA_CTRL_D12(Val) ((Val & 0x3) << 24)
+#define CP15_DA_CTRL_D13(Val) ((Val & 0x3) << 25)
+#define CP15_DA_CTRL_D14(Val) ((Val & 0x3) << 28)
+#define CP15_DA_CTRL_D15(Val) ((Val & 0x3) << 30)
+
+// CP15 fault status register
+#define CP15_FAULT_STAT 5
+
+// CP15 fault address register
+#define CP15_FAULT_ADDR 6
+
+// CP15 Cache operations
+#define CP15_CACHE_OPR 7
+
+// CP15 TLB operation
+#define CP15_TBL_OPR 8
+
+// CP15 Cache lockdown
+#define CP15_C_LD 9
+
+// CP15 TBL lockdown
+#define CP15_TBL_LD 10
+
+// CP15 VBAR
+#define CP15_VBAR 12
+
+// CP15 Process identifier register
+#define CP15_PROCESS_IDNF 13
+
+// CP15 Test
+#define CP15_TEST 15
+
+typedef enum {
+ DomainNoAccess = 0, DomainClient, DomainManager = 3,
+} MmuDomainType_t;
+
+typedef enum
+{
+ TtL1Invalid = 0, TtL1PageTable, TtL1Section, TtL1SuperSection = 0x40002,
+} TtL1EntryType_t;
+
+typedef enum
+{
+ TtL2Invalid = 0, TtL2LargePage, TtL2SmallPage,
+} TtL2EntryType_t;
+
+typedef enum
+{
+ TableInvalid = 0, TableL1, TableL2_PageTable,
+} TableType_t;
+
+typedef enum
+{
+ PC15_FASTBUS_MODE = 0, PC15_SYNC_MODE, PC15_ASYNC_MODE = 3
+} ClkMode_t;
+
+
+typedef union _TtEntry_t
+{
+ Int32U Data;
+ struct
+ {
+ Int32U Type : 2;
+ Int32U : 3;
+ Int32U Domain : 4;
+ Int32U :23;
+ };
+} TtEntry_t, *pTtEntry_t;
+
+typedef struct _TtSectionBlock_t
+{
+ Int32U NubrOfSections;
+ Int32U VirtAddr;
+ Int32U PhysAddr;
+ TtEntry_t Entry;
+} TtSectionBlock_t, * pTtSectionBlock_t;
+
+typedef struct _TtTableBlock_t
+{
+ pInt32U TableAddr;
+ TableType_t TableType;
+} TtTableBlock_t, * pTtTableBlock_t;
+
+#define TT_ENTRY_INVALID 0
+
+#define TTL1_SECTION_PADDR_MASK 0xFFF00000
+#define TTL1_S_SECTION_PADDR_MASK 0xFF000000
+#define TTL1_S_SECTION_EXT35_32_PADDR_MASK 0x00F00000
+#define TTL1_S_SECTION_EXT39_36_PADDR_MASK 0x000001E0
+#define TTL1_PT_PADDR_MASK 0xFFFFFC00
+
+#define TTL2_LP_PADDR_MASK 0xFFFF0000
+#define TTL2_SP_PADDR_MASK 0xFFFFF000
+
+/*************************************************************************
+ * Function Name: CP15_GetTtb0
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the TTB0 register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetTtb0 (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetTtb1
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the TTB1 register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetTtb1 (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetStatus
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the MMU control register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetStatus (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetDomain
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the MMU domain access register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetDomain (void);
+
+/*************************************************************************
+ * Function Name: CP15_SetDomains
+ * Parameters: Int32U DomainAccess
+ *
+ * Return: Int32U
+ *
+ * Description: Function set the MMU domain access register
+ *
+ *************************************************************************/
+__arm void CP15_SetDomains (Int32U DomainAccess);
+
+/*************************************************************************
+ * Function Name: CP15_MaintainDCacheSetWay
+ * Parameters: Int32U level - level of cache,
+ * Int32U maint - maintenance type
+ *
+ * Return: none
+ *
+ * Description: Maintain data cache line by Set/Way
+ *
+ *************************************************************************/
+__arm void CP15_MaintainDCacheSetWay(Int32U level, Int32U maint);
+
+/*************************************************************************
+ * Function Name: CP15_MaintAllDCache
+ * Parameters: Int32U oper - type of maintenance, one of:
+ * DCACHE_CLEAN_AND_INVALIDATE
+ * DCACHE_INVALIDATE
+ *
+ * Return: none
+ *
+ * Description: Maintenance of all data cache
+ *
+ *************************************************************************/
+__arm void CP15_MaintainAllDCache(Int32U oper);
+
+/*************************************************************************
+ * Function Name: CP15_InvalInstrCache
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Invalidate instruction cache
+ *
+ *************************************************************************/
+__arm void CP15_InvalInstrCache(void);
+
+/*************************************************************************
+ * Function Name: CP15_InvalPredictArray
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Invalidate prediction array
+ *
+ *************************************************************************/
+__arm void CP15_InvalPredictArray(void);
+
+/*************************************************************************
+ * Function Name: CP15_InvalAllTbl
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Invalidate TLB
+ *
+ *************************************************************************/
+__arm void CP15_InvalAllTbl (void);
+
+/*************************************************************************
+ * Function Name: CP15_SetStatus
+ * Parameters: Int32U Ctrl
+ *
+ * Return: none
+ *
+ * Description: Set CP15 CTR (control) register
+ *
+ *************************************************************************/
+__arm void CP15_SetStatus (Int32U Ctrl);
+
+/*************************************************************************
+ * Function Name: CP15_SetMmu
+ * Parameters: Int32U Ctrl
+ *
+ * Return: none
+ *
+ * Description: Set CP15 control register
+ *
+ *************************************************************************/
+__arm void CP15_SetMmu (Int32U Ctrl);
+
+/*************************************************************************
+ * Function Name: CP15_SetTtb0
+ * Parameters: pInt32U pTtb
+ *
+ * Return: none
+ *
+ * Description: Set CP15 TTB0 base address register
+ *
+ *************************************************************************/
+__arm void CP15_SetTtb0 (pInt32U pTtb);
+
+/*************************************************************************
+ * Function Name: CP15_SetTtb1
+ * Parameters: pInt32U pTtb
+ *
+ * Return: none
+ *
+ * Description: Set CP15 TTB1 base address register
+ *
+ *************************************************************************/
+__arm void CP15_SetTtb1 (pInt32U pTtb);
+
+/*************************************************************************
+ * Function Name: CP15_SetDac
+ * Parameters: Int32U da
+ *
+ * Return: none
+ *
+ * Description: Set CP15 domain access register
+ *
+ *************************************************************************/
+__arm void CP15_SetDac (Int32U da);
+
+/*************************************************************************
+ * Function Name: CP15_WriteBuffFlush
+ * Parameters: none
+ *
+ * Return: none
+ *
+ * Description: Flush the write buffer and wait for completion
+ * of the flush.
+ *
+ *************************************************************************/
+__arm void CP15_WriteBuffFlush (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetFaultStat
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the MMU fault status register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetFaultStat (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetFaultAddr
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the MMU fault address register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetFaultAddr (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetFcsePid
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the MMU Process identifier
+ * FCSE PID register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetFcsePid (void);
+
+/*************************************************************************
+ * Function Name: CP15_GetPraceProcId
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Function returning the MMU Trace Process identifier
+ * register
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetPraceProcId (void);
+
+/*************************************************************************
+ * Function Name: CP15_SetFcsePid
+ * Parameters: Int32U FcsePid
+ *
+ * Return: none
+ *
+ * Description: Function set the MMU Process identifier
+ * FCSE PID register
+ *
+ *************************************************************************/
+__arm void CP15_SetFcsePid (Int32U FcsePid);
+
+/*************************************************************************
+ * Function Name: CP15_SetPraceProcId
+ * Parameters: Int32U
+ *
+ * Return: none
+ *
+ * Description: Function set the MMU Trace Process identifier
+ * register
+ *
+ *************************************************************************/
+__arm void CP15_SetPraceProcId (Int32U Trace);
+
+/*************************************************************************
+ * Function Name: CP15_WriteBuffFlush
+ * Parameters: pTtSectionBlock_t pTtSB, pTtTableBlock_t pTtTB
+ *
+ * Return: Boolean
+ *
+ * Return error if MMU is enabled. Return error if target
+ * Translation Table address is not 16K aligned. Clear the
+ * Translation Table area. Build the Translation Table from the
+ * initialization data in the Section Block array. Return no error.
+ *
+ * Description: Initializes the MMU tables.
+ *
+ *
+ *************************************************************************/
+Boolean CP15_InitMmuTtb(const TtSectionBlock_t * pTtSB,
+ const TtTableBlock_t * pTtTB);
+
+/*************************************************************************
+ * Function Name: CP15_Mmu
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable MMU
+ *
+ *************************************************************************/
+void CP15_Mmu (Boolean Enable);
+
+/*************************************************************************
+ * Function Name: CP15_Cache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable Cache
+ *
+ *************************************************************************/
+void CP15_Cache (Boolean Enable);
+
+/*************************************************************************
+ * Function Name: CP15_InvalidateCache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Invalidate Cache
+ *
+ *************************************************************************/
+void CP15_InvalidateCache();
+
+/*************************************************************************
+ * Function Name: CP15_ICache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable I cache
+ *
+ *************************************************************************/
+void CP15_ICache (Boolean Enable);
+
+/*************************************************************************
+ * Function Name: CP15_DCache
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable D cache
+ *
+ *************************************************************************/
+void CP15_DCache (Boolean Enable);
+
+/*************************************************************************
+ * Function Name: CP15_ProgFlowPredictioin
+ * Parameters: Boolean Enable
+ *
+ * Return: none
+ *
+ * Description: Enable/Disable program flow prediction
+ *
+ *************************************************************************/
+void CP15_ProgFlowPrediction (Boolean Enable);
+
+/*************************************************************************
+ * Function Name: CP15_GetVectorBase
+ * Parameters: none
+ *
+ * Return: Int32U
+ *
+ * Description: Get Vector Base Register (VBAR)
+ *
+ *************************************************************************/
+__arm Int32U CP15_GetVectorBase(void);
+
+/*************************************************************************
+ * Function Name: CP15_SetVectorBase
+ * Parameters: Int32U
+ *
+ * Return: none
+ *
+ * Description: Set Vector Base Register (VBAR)
+ *
+ *************************************************************************/
+__arm void CP15_SetVectorBase(Int32U vector);
+
+/*************************************************************************
+ * Function Name: CP15_SetHighVectors
+ * Parameters: Boolean
+ *
+ * Return: none
+ *
+ * Description: Select High or Low Vectors base in CP15 control register
+ *
+ *************************************************************************/
+__arm void CP15_SetHighVectors(Boolean Enable);
+
+#endif // __ARMV7A_CP15_DRV_H
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/r7s721000.icf b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/r7s721000.icf
new file mode 100644
index 000000000..165fd0513
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/r7s721000.icf
@@ -0,0 +1,58 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20020000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20020040;
+define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_svcstack__ = 0x800;
+define symbol __ICFEDIT_size_irqstack__ = 0x800;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__ = 0x8;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
+
+define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60020000;
+define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
+
+define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
+define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
+
+define memory mem with size = 4G;
+
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
+define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
+define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+do not initialize { section MMU_TT };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+
+place in RetRAM_region { section .retram };
+place in MirrorRAM_region { section .mirrorram };
+place in MirrorRetRAM_region { section .mirrorretram };
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.cspy.bat b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.cspy.bat
new file mode 100644
index 000000000..9b9c492cf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.cspy.bat
@@ -0,0 +1,24 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM --download_only Downloads a code image without starting a debug
+@REM session afterwards.
+@REM --silent Omits the sign-on message.
+@REM --timeout Limits the maximum allowed execution time.
+@REM
+
+
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armsim2.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --backend -B "--endian=little" "--cpu=Cortex-A9" "--fpu=VFPv3Neon" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Renesas\R7S721000.ddf" "--semihosting=none" "--device=R7S721000"
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dbgdt
new file mode 100644
index 000000000..38ab87403
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dbgdt
@@ -0,0 +1,87 @@
+
+
+
+
+
+
+
+
+ 201622
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+
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+
+
+ 20121632481
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+
+
+
+
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+ 228272727
+
+
+
+
+
+ - Disassembly
- _I0
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+
+
+ - 500
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+ 20011
+ 200WATCH_1- Expression
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+ TabID-11794-23690Find in FilesFind-in-Files
+
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+ RTOSDemoRTOSDemo/Blinky-DemoRTOSDemo/FreeRTOS-SourceRTOSDemo/FreeRTOS-Source/portableRTOSDemo/FreeRTOS-Source/portable/IARRTOSDemo/FreeRTOS-Source/portable/IAR/ARM_CA9
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+ iaridepm.enu1debuggergui.enu1-2-2716302-2-2200200119048203666180952731161-2-21981682-2-216842001002381203666119048203666
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dni
new file mode 100644
index 000000000..3686f5c9a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.dni
@@ -0,0 +1,121 @@
+[Stack]
+FillEnabled=0
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=0
+WarnLogOnly=1
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[JLinkDriver]
+WatchCond=_ 0
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+CStepIntDis=_ 0
+[DebugChecksum]
+Checksum=-1646852950
+[Jet]
+JetConnSerialNo=73866
+JetConnFoundProbes=
+DisableInterrupts=0
+[PlDriver]
+MemConfigValue=C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Renesas\R7S721000.ddf
+FirstRun=0
+[ArmDriver]
+EnableCache=1
+[Exceptions]
+StopOnUncaught=_ 0
+StopOnThrow=_ 0
+[CallStack]
+ShowArgs=0
+[Disassembly]
+MixedMode=1
+[SWOManager]
+SamplingDivider=8192
+OverrideClock=0
+CpuClock=0
+SwoClock=-1
+DataLogMode=0
+ItmPortsEnabled=63
+ItmTermIOPorts=1
+ItmLogPorts=0
+ItmLogFile=$PROJ_DIR$\ITM.log
+PowerForcePC=1
+PowerConnectPC=1
+[PowerLog]
+LogEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=0
+Title0=ITrgPwr
+Symbol0=0 4 1
+LiveEnabled=0
+LiveFile=PowerLogLive.log
+[Trace2]
+Enabled=0
+ShowSource=0
+[SWOTraceWindow]
+ForcedPcSampling=0
+ForcedInterruptLogs=0
+ForcedItmLogs=0
+EventCPI=0
+EventEXC=0
+EventFOLD=0
+EventLSU=0
+EventSLEEP=0
+[PowerProbe]
+Frequency=10000
+Probe0=ITrgPwr
+ProbeSetup0=2 1 1 2 0 0
+[watch_formats]
+Fmt0={W}0:*(unsigned long *)0xE8202004 4 0
+Fmt1={W}0:*(unsigned long*)0xe8202004 4 0
+Fmt2={W}0:INTC_ICDIPR33 4 0
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[CallStackLog]
+Enabled=0
+[DriverProfiling]
+Enabled=0
+Mode=0
+Graph=0
+Symbiont=0
+Exclusions=
+[InterruptLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+SumSortOrder=0
+[DataLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+[Disassemble mode]
+mode=0
+[Breakpoints2]
+Count=0
+[Interrupts]
+Enabled=1
+[MemoryMap]
+Enabled=0
+Base=0
+UseAuto=0
+TypeViolation=1
+UnspecRange=1
+ActionState=1
+[Aliases]
+Count=0
+SuppressDialog=0
+[Trace1]
+Enabled=0
+ShowSource=1
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.wsdt
new file mode 100644
index 000000000..f7948697d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo.wsdt
@@ -0,0 +1,78 @@
+
+
+
+
+
+
+
+ RTOSDemo/RAM Debug
+
+
+
+
+
+
+
+
+ 306272727
+
+
+
+
+ 201622
+
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+
+
+ 20121632481
+ 58082994300- Breakpoint
- _I0
- 500
- 35
58082994
+
+
+
+
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+
+ TabID-16877-7786
+ Workspace
+ Workspace
+
+
+ RTOSDemoRTOSDemo/Full-Demo
+
+
+
+ 0
+
+
+ TabID-27919-7988
+ Debug Log
+ Debug-Log
+
+
+
+ TabID-13343-8671
+ Build
+ Build
+
+
+ TabID-959-438Ambiguous DefinitionsSelect-Ambiguous-DefinitionsTabID-21579-10611Find All DeclarationsFind-All-Declarations
+
+ 1
+
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+
+
+
+ TextEditor$WS_DIR$\..\Source\main.c00000674910491000100000010000001
+
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diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo_RAM Debug.jlink b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo_RAM Debug.jlink
new file mode 100644
index 000000000..4722ca16d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/IAR/settings/RTOSDemo_RAM Debug.jlink
@@ -0,0 +1,34 @@
+[BREAKPOINTS]
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 1
+Device="Unspecified"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Blinky-Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Blinky-Demo/main_blinky.c
new file mode 100644
index 000000000..2ab59fe3b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Blinky-Demo/main_blinky.c
@@ -0,0 +1,241 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ * NOTE 1: This project provides two demo applications. A simple blinky style
+ * project, and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c. This file implements the simply blinky style version.
+ *
+ * NOTE 2: This file only contains the source code that is specific to the
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks. It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 200 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky(). Once the value is sent, the task loops
+ * back around to block for another 200 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky(). When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, toggles an LED. The 'block
+ * time' parameter passed to the queue receive function specifies that the
+ * task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue. The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue. As the queue
+ * send task writes to the queue every 200 milliseconds, the queue receive
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Standard demo includes. */
+#include "partest.h"
+
+/* Priorities at which the tasks are created. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue. The 200ms value is converted
+to ticks using the portTICK_RATE_MS constant. */
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
+
+/* The number of items the queue can hold. This is 1 as the receive task
+will remove items as they are added, meaning the send task should always find
+the queue empty. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/* The LED toggled by the Rx task. */
+#define mainTASK_LED ( 0 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Called by main() to create the simply blinky style application if
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ */
+void main_blinky( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static xQueueHandle xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+
+ if( xQueue != NULL )
+ {
+ /* Start the two tasks as described in the comments at the top of this
+ file. */
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
+ NULL, /* The parameter passed to the task - not used in this case. */
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
+ NULL ); /* The task handle is not required, so NULL is passed. */
+
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+ }
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was either insufficient FreeRTOS heap memory available for the idle
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from
+ User mode. See the memory management section on the FreeRTOS web site for
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
+ mode from which main() is called is set in the C start up code and must be
+ a privileged mode (not user mode). */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Place this task in the blocked state until it is time to run again. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ toggle the LED. 0 is used as the block time so the sending operation
+ will not block - it shouldn't need to block as the queue should always
+ be empty at this point in the code. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, toggle the LED. */
+ if( ulReceivedValue == ulExpectedValue )
+ {
+ vParTestToggleLED( mainTASK_LED );
+ ulReceivedValue = 0U;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOSConfig.h
new file mode 100644
index 000000000..eeb753ab0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOSConfig.h
@@ -0,0 +1,210 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/*
+ * The FreeRTOS Cortex-A port implements a full interrupt nesting model.
+ *
+ * Interrupts that are assigned a priority at or below
+ * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM
+ * generic interrupt controller [GIC] means a priority that has a numerical
+ * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API
+ * functions and will nest.
+ *
+ * Interrupts that are assigned a priority above
+ * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical
+ * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS
+ * API functions, will nest, and will not be masked by FreeRTOS critical
+ * sections (although it is necessary for interrupts to be globally disabled
+ * extremely briefly as the interrupt mask is updated in the GIC).
+ *
+ * FreeRTOS functions that can be called from an interrupt are those that end in
+ * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable
+ * interrupt entry to be shorter, faster, simpler and smaller.
+ *
+ * The Renesas RZ implements 32 unique interrupt priorities. For the purpose of
+ * setting configMAX_API_CALL_INTERRUPT_PRIORITY 31 represents the lowest
+ * priority.
+ */
+#define configMAX_API_CALL_INTERRUPT_PRIORITY 25
+
+
+#define configCPU_CLOCK_HZ 100000000UL
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configPERIPHERAL_CLOCK_HZ ( 33333000UL )
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 160 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38912 ) )
+#define configMAX_TASK_NAME_LEN ( 10 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+
+/* Prevent C code being included in assembly files when the IAR compiler is
+used. */
+#ifndef __IASMARM__
+ /* Run time stats gathering definitions. */
+ unsigned long ulGetRunTimeCounterValue( void );
+ void vInitialiseRunTimeStats( void );
+
+ #define configGENERATE_RUN_TIME_STATS 1
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats()
+ #define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
+
+ /* The size of the global output buffer that is available for use when there
+ are multiple command interpreters running at once (for example, one on a UART
+ and one on TCP/IP). This is done to prevent an output buffer being defined by
+ each implementation - which would waste RAM. In this case, there is only one
+ command interpreter running. */
+ #define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096
+
+ /* Normal assert() semantics without relying on the provision of an assert.h
+ header file. */
+ void vAssertCalled( const char * pcFile, unsigned long ulLine );
+ #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );
+
+
+
+ /****** Hardware specific settings. *******************************************/
+
+ /*
+ * The application must provide a function that configures a peripheral to
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
+ * in FreeRTOSConfig.h to call the function. This file contains a function
+ * that is suitable for use on the Renesas RZ MPU. FreeRTOS_Tick_Handler() must
+ * be installed as the peripheral's interrupt handler.
+ */
+ void vConfigureTickInterrupt( void );
+ #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
+#endif /* __ICCARM__ */
+
+/* The following constants describe the hardware, and are correct for the
+Renesas RZ MPU. */
+#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0xE8201000
+#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000
+#define configUNIQUE_INTERRUPT_PRIORITIES 32
+
+/* Map the FreeRTOS IRQ and SVC/SWI handlers to the names used in the C startup
+code (which is where the vector table is defined). */
+#define FreeRTOS_IRQ_Handler IRQ_Handler
+#define FreeRTOS_SWI_Handler SWI_Handler
+
+#endif /* FREERTOS_CONFIG_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOS_tick_config.c
new file mode 100644
index 000000000..71c755999
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/FreeRTOS_tick_config.c
@@ -0,0 +1,170 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "Task.h"
+
+/* Renesas driver includes. */
+#include "stdint.h"
+#include "dev_drv.h"
+#include "devdrv_ostm.h"
+#include "devdrv_intc.h"
+#include "iodefine.h"
+
+#define runtimeCLOCK_SCALE_SHIFT ( 9UL )
+#define runtimeOVERFLOW_BIT ( 1UL << ( 32UL - runtimeCLOCK_SCALE_SHIFT ) )
+
+/* To make casting to the ISR prototype expected by the Renesas GIC drivers. */
+typedef void (*ISR_FUNCTION)( uint32_t );
+
+/*
+ * The application must provide a function that configures a peripheral to
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
+ * in FreeRTOSConfig.h to call the function. This file contains a function
+ * that is suitable for use on the Renesas RZ MPU.
+ */
+void vConfigureTickInterrupt( void )
+{
+ /* Stop the counter. */
+ OSTM0.OSTMnTT.BIT.OSTMnTT = 1;
+
+ /* Work in interval mode. */
+ OSTM0.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_INTERVAL;
+
+ /* Use interrupts after counting starts. */
+ OSTM0.OSTMnCTL.BIT.OSTMnMD0 = 1;
+
+ /* Start value for down counter. */
+ OSTM0.OSTMnCMP = configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ;
+
+ /* Configure the interrupt controller. */
+ R_INTC_RegistIntFunc( INTC_ID_OSTMI0, ( ISR_FUNCTION ) FreeRTOS_Tick_Handler );
+
+ /* Tick must be assigned the lowest interrupt priority. */
+ R_INTC_SetPriority( INTC_ID_OSTMI0, portLOWEST_USABLE_INTERRUPT_PRIORITY );
+
+ INTC.ICCBPR.BIT.Binarypoint = 0;
+ R_INTC_Enable( INTC_ID_OSTMI0 );
+
+ R_OSTM_Open( DEVDRV_CH_0 );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Crude implementation of a run time counter used to measure how much time
+ * each task spends in the Running state.
+ */
+unsigned long ulGetRunTimeCounterValue( void )
+{
+static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
+unsigned long ulValueNow;
+
+ ulValueNow = OSTM1.OSTMnCNT;
+
+ /* Has the value overflowed since it was last read. */
+ if( ulValueNow < ulLastCounterValue )
+ {
+ ulOverflows++;
+ }
+ ulLastCounterValue = ulValueNow;
+
+ /* There is no prescale on the counter, so simulate in software. */
+ ulValueNow >>= runtimeCLOCK_SCALE_SHIFT + ( runtimeOVERFLOW_BIT * ulOverflows );
+
+ return ulValueNow;
+}
+/*-----------------------------------------------------------*/
+
+void vInitialiseRunTimeStats( void )
+{
+ /* OSTM1 is used as the run time stats counter. */
+
+ /* Stop the counter. */
+ OSTM1.OSTMnTT.BIT.OSTMnTT = 1;
+
+ /* Work in compare mode mode. */
+ OSTM1.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_COMPARE;
+
+ /* Don't use interrupts. */
+ OSTM1.OSTMnCTL.BIT.OSTMnMD0 = 0;
+
+ /* Compare is just set to 0. */
+ OSTM1.OSTMnCMP = 0;
+
+ R_OSTM_Open( DEVDRV_CH_1 );
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/File-releated-CLI-commands.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/File-releated-CLI-commands.c
new file mode 100644
index 000000000..ec4cdbe29
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/File-releated-CLI-commands.c
@@ -0,0 +1,581 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include
+#include
+#include
+#include
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+
+#ifdef _WINDOWS_
+ #define snprintf _snprintf
+#endif
+
+#define cliNEW_LINE "\r\n"
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/*
+ * Print out information on a single file.
+ */
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct );
+
+/*
+ * Copies an existing file into a newly created file.
+ */
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,
+ int32_t lSourceFileLength,
+ int8_t *pcDestinationFile,
+ int8_t *pxWriteBuffer,
+ size_t xWriteBufferLen );
+
+/*
+ * Implements the DIR command.
+ */
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the CD command.
+ */
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the DEL command.
+ */
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the TYPE command.
+ */
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the COPY command.
+ */
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Registers the CLI commands that are specific to the files system with the
+ * FreeRTOS+CLI command interpreter.
+ */
+void vRegisterFileSystemCLICommands( void );
+
+/* Structure that defines the DIR command line command, which lists all the
+files in the current directory. */
+static const CLI_Command_Definition_t xDIR =
+{
+ "dir", /* The command string to type. */
+ "\r\ndir:\r\n Lists the files in the current directory\r\n",
+ prvDIRCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the CD command line command, which changes the
+working directory. */
+static const CLI_Command_Definition_t xCD =
+{
+ "cd", /* The command string to type. */
+ "\r\ncd :\r\n Changes the working directory\r\n",
+ prvCDCommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the TYPE command line command, which prints the
+contents of a file to the console. */
+static const CLI_Command_Definition_t xTYPE =
+{
+ "type", /* The command string to type. */
+ "\r\ntype :\r\n Prints file contents to the terminal\r\n",
+ prvTYPECommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the DEL command line command, which deletes a file. */
+static const CLI_Command_Definition_t xDEL =
+{
+ "del", /* The command string to type. */
+ "\r\ndel :\r\n deletes a file or directory\r\n",
+ prvDELCommand, /* The function to run. */
+ 1 /* One parameter is expected. */
+};
+
+/* Structure that defines the COPY command line command, which deletes a file. */
+static const CLI_Command_Definition_t xCOPY =
+{
+ "copy", /* The command string to type. */
+ "\r\ncopy :\r\n Copies to \r\n",
+ prvCOPYCommand, /* The function to run. */
+ 2 /* Two parameters are expected. */
+};
+
+/*-----------------------------------------------------------*/
+
+void vRegisterFileSystemCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xDIR );
+ FreeRTOS_CLIRegisterCommand( &xCD );
+ FreeRTOS_CLIRegisterCommand( &xTYPE );
+ FreeRTOS_CLIRegisterCommand( &xDEL );
+ FreeRTOS_CLIRegisterCommand( &xCOPY );
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;
+static F_FILE *pxFile = NULL;
+int iChar;
+size_t xByte;
+size_t xColumns = 50U;
+
+ /* Ensure there is always a null terminator after each character written. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+
+ /* Ensure the buffer leaves space for the \r\n. */
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+ xWriteBufferLen -= strlen( cliNEW_LINE );
+
+ if( xWriteBufferLen < xColumns )
+ {
+ /* Ensure the loop that uses xColumns as an end condition does not
+ write off the end of the buffer. */
+ xColumns = xWriteBufferLen;
+ }
+
+ if( pxFile == NULL )
+ {
+ /* The file has not been opened yet. Find the file name. */
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to open the requested file. */
+ pxFile = f_open( ( const char * ) pcParameter, "r" );
+ }
+
+ if( pxFile != NULL )
+ {
+ /* Read the next chunk of data from the file. */
+ for( xByte = 0; xByte < xColumns; xByte++ )
+ {
+ iChar = f_getc( pxFile );
+
+ if( iChar == -1 )
+ {
+ /* No more characters to return. */
+ f_close( pxFile );
+ pxFile = NULL;
+ break;
+ }
+ else
+ {
+ pcWriteBuffer[ xByte ] = ( int8_t ) iChar;
+ }
+ }
+ }
+
+ if( pxFile == NULL )
+ {
+ /* Either the file was not opened, or all the data from the file has
+ been returned and the file is now closed. */
+ xReturn = pdFALSE;
+ }
+
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+size_t xStringLength;
+
+ /* Obtain the parameter string. */
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to move to the requested directory. */
+ ucReturned = f_chdir( ( char * ) pcParameter );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ sprintf( ( char * ) pcWriteBuffer, "In: " );
+ xStringLength = strlen( ( const char * ) pcWriteBuffer );
+ f_getcwd( ( char * ) &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );
+ }
+ else
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Error" );
+ }
+
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+static F_FIND *pxFindStruct = NULL;
+unsigned char ucReturned;
+portBASE_TYPE xReturn = pdFALSE;
+
+ /* This assumes pcWriteBuffer is long enough. */
+ ( void ) pcCommandString;
+
+ /* Ensure the buffer leaves space for the \r\n. */
+ configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+ xWriteBufferLen -= strlen( cliNEW_LINE );
+
+ if( pxFindStruct == NULL )
+ {
+ /* This is the first time this function has been executed since the Dir
+ command was run. Create the find structure. */
+ pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );
+
+ if( pxFindStruct != NULL )
+ {
+ ucReturned = f_findfirst( "*.*", pxFindStruct );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );
+ }
+ }
+ else
+ {
+ snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );
+ }
+ }
+ else
+ {
+ /* The find struct has already been created. Find the next file in
+ the directory. */
+ ucReturned = f_findnext( pxFindStruct );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* There are no more files. Free the find structure. */
+ vPortFree( pxFindStruct );
+ pxFindStruct = NULL;
+
+ /* No string to return. */
+ pcWriteBuffer[ 0 ] = 0x00;
+ }
+ }
+
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+
+ /* This function assumes xWriteBufferLen is large enough! */
+ ( void ) xWriteBufferLen;
+
+ /* Obtain the parameter string. */
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Attempt to delete the file. */
+ ucReturned = f_delete( ( const char * ) pcParameter );
+
+ if( ucReturned == F_NO_ERROR )
+ {
+ sprintf( ( char * ) pcWriteBuffer, "%s was deleted", pcParameter );
+ }
+ else
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Error" );
+ }
+
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcSourceFile, *pcDestinationFile;
+portBASE_TYPE xParameterStringLength;
+long lSourceLength, lDestinationLength = 0;
+
+ /* Obtain the name of the destination file. */
+ pcDestinationFile = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 2, /* Return the second parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcDestinationFile );
+
+ /* Obtain the name of the source file. */
+ pcSourceFile = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcSourceFile );
+
+ /* Terminate the string. */
+ pcSourceFile[ xParameterStringLength ] = 0x00;
+
+ /* See if the source file exists, obtain its length if it does. */
+ lSourceLength = f_filelength( ( const char * ) pcSourceFile );
+
+ if( lSourceLength == 0 )
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Source file does not exist" );
+ }
+ else
+ {
+ /* See if the destination file exists. */
+ lDestinationLength = f_filelength( ( const char * ) pcDestinationFile );
+
+ if( lDestinationLength != 0 )
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Error: Destination file already exists" );
+ }
+ }
+
+ /* Continue only if the source file exists and the destination file does
+ not exist. */
+ if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )
+ {
+ if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Copy made" );
+ }
+ else
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Error during copy" );
+ }
+ }
+
+ strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,
+ int32_t lSourceFileLength,
+ int8_t *pcDestinationFile,
+ int8_t *pxWriteBuffer,
+ size_t xWriteBufferLen )
+{
+int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;
+F_FILE *pxFile;
+portBASE_TYPE xReturn = pdPASS;
+
+ /* NOTE: Error handling has been omitted for clarity. */
+
+ while( lBytesRead < lSourceFileLength )
+ {
+ /* How many bytes are left? */
+ lBytesRemaining = lSourceFileLength - lBytesRead;
+
+ /* How many bytes should be read this time around the loop. Can't
+ read more bytes than will fit into the buffer. */
+ if( lBytesRemaining > ( long ) xWriteBufferLen )
+ {
+ lBytesToRead = ( long ) xWriteBufferLen;
+ }
+ else
+ {
+ lBytesToRead = lBytesRemaining;
+ }
+
+ /* Open the source file, seek past the data that has already been
+ read from the file, read the next block of data, then close the
+ file again so the destination file can be opened. */
+ pxFile = f_open( ( const char * ) pcSourceFile, "r" );
+ if( pxFile != NULL )
+ {
+ f_seek( pxFile, lBytesRead, F_SEEK_SET );
+ f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );
+ f_close( pxFile );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ /* Open the destination file and write the block of data to the end of
+ the file. */
+ pxFile = f_open( ( const char * ) pcDestinationFile, "a" );
+ if( pxFile != NULL )
+ {
+ f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );
+ f_close( pxFile );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ break;
+ }
+
+ lBytesRead += lBytesToRead;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct )
+{
+const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";
+const char * pcAttrib;
+
+ /* Point pcAttrib to a string that describes the file. */
+ if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )
+ {
+ pcAttrib = pcDirectory;
+ }
+ else if( pxFindStruct->attr & F_ATTR_READONLY )
+ {
+ pcAttrib = pcReadOnlyFile;
+ }
+ else
+ {
+ pcAttrib = pcWritableFile;
+ }
+
+ /* Create a string that includes the file name, the file size and the
+ attributes string. */
+ sprintf( ( char * ) pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, pxFindStruct->filesize );
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/File-system-demo.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/File-system-demo.c
new file mode 100644
index 000000000..77fc87ee5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/File-system-demo.c
@@ -0,0 +1,384 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/* Standard includes. */
+#include
+#include
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+
+/* 8.3 format, plus null terminator. */
+#define fsMAX_FILE_NAME_LEN 13
+
+/* The number of bytes read/written to the example files at a time. */
+#define fsRAM_BUFFER_SIZE 200
+
+/* The number of bytes written to the file that uses f_putc() and f_getc(). */
+#define fsPUTC_FILE_SIZE 100
+
+/* The number of files created in root. */
+#define fsROOT_FILES 5
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+void vCreateAndVerifySampleFiles( void );
+
+/*
+ * Create a set of example files in the root directory of the volume using
+ * f_write().
+ */
+static void prvCreateDemoFilesUsing_f_write( void );
+
+/*
+ * Use f_read() to read back and verify the files that were created by
+ * prvCreateDemoFilesUsing_f_write().
+ */
+static void prvVerifyDemoFileUsing_f_read( void );
+
+/*
+ * Create an example file in a sub-directory using f_putc().
+ */
+static void prvCreateDemoFileUsing_f_putc( void );
+
+/*
+ * Use f_getc() to read back and verify the file that was created by
+ * prvCreateDemoFileUsing_f_putc().
+ */
+static void prvVerifyDemoFileUsing_f_getc( void );
+
+/*-----------------------------------------------------------*/
+
+/* A buffer used to both create content to write to disk, and read content back
+from a disk. Note there is no mutual exclusion on this buffer. */
+static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];
+
+/* Names of directories that are created. */
+static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";
+
+/*-----------------------------------------------------------*/
+
+void vCreateAndVerifySampleFiles( void )
+{
+unsigned char ucStatus;
+
+ /* First create the volume. */
+ ucStatus = f_initvolume( ram_initfunc );
+
+ /* It is expected that the volume is not formatted. */
+ if( ucStatus == F_ERR_NOTFORMATTED )
+ {
+ /* Format the created volume. */
+ ucStatus = f_format( F_FAT12_MEDIA );
+ }
+
+ if( ucStatus == F_NO_ERROR )
+ {
+ /* Create a set of files using f_write(). */
+ prvCreateDemoFilesUsing_f_write();
+
+ /* Read back and verify the files that were created using f_write(). */
+ prvVerifyDemoFileUsing_f_read();
+
+ /* Create sub directories two deep then create a file using putc. */
+ prvCreateDemoFileUsing_f_putc();
+
+ /* Read back and verify the file created by
+ prvCreateDemoFileUsing_f_putc(). */
+ prvVerifyDemoFileUsing_f_getc();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFilesUsing_f_write( void )
+{
+portBASE_TYPE xFileNumber, xWriteNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+long lItemsWritten;
+F_FILE *pxFile;
+
+ /* Create fsROOT_FILES files. Each created file will be
+ ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled
+ with a different repeating character. */
+ for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )
+ {
+ /* Generate a file name. */
+ sprintf( cFileName, "root%03d.txt", xFileNumber );
+
+ /* Obtain the current working directory and print out the file name and
+ the directory into which the file is being written. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Creating file %s in %s\r\n", cFileName, cRAMBuffer );
+
+ /* Open the file, creating the file if it does not already exist. */
+ pxFile = f_open( cFileName, "w" );
+ configASSERT( pxFile );
+
+ /* Fill the RAM buffer with data that will be written to the file. This
+ is just a repeating ascii character that indicates the file number. */
+ memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );
+
+ /* Write the RAM buffer to the opened file a number of times. The
+ number of times the RAM buffer is written to the file depends on the
+ file number, so the length of each created file will be different. */
+ for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )
+ {
+ lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+ configASSERT( lItemsWritten == 1 );
+ }
+
+ /* Close the file so another file can be created. */
+ f_close( pxFile );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_read( void )
+{
+portBASE_TYPE xFileNumber, xReadNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+long lItemsRead, lChar;
+F_FILE *pxFile;
+
+ /* Read back the files that were created by
+ prvCreateDemoFilesUsing_f_write(). */
+ for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )
+ {
+ /* Generate the file name. */
+ sprintf( cFileName, "root%03d.txt", xFileNumber );
+
+ /* Obtain the current working directory and print out the file name and
+ the directory from which the file is being read. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Reading file %s from %s\r\n", cFileName, cRAMBuffer );
+
+ /* Open the file for reading. */
+ pxFile = f_open( cFileName, "r" );
+ configASSERT( pxFile );
+
+ /* Read the file into the RAM buffer, checking the file contents are as
+ expected. The size of the file depends on the file number. */
+ for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )
+ {
+ /* Start with the RAM buffer clear. */
+ memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );
+
+ lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+ configASSERT( lItemsRead == 1 );
+
+ /* Check the RAM buffer is filled with the expected data. Each
+ file contains a different repeating ascii character that indicates
+ the number of the file. */
+ for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )
+ {
+ configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );
+ }
+ }
+
+ /* Close the file. */
+ f_close( pxFile );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFileUsing_f_putc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "In directory %s\r\n", cRAMBuffer );
+
+ /* Create a sub directory. */
+ ucReturn = f_mkdir( pcDirectory1 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Move into the created sub-directory. */
+ ucReturn = f_chdir( pcDirectory1 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "In directory %s\r\n", cRAMBuffer );
+
+ /* Create a subdirectory in the new directory. */
+ ucReturn = f_mkdir( pcDirectory2 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Move into the directory just created - now two directories down from
+ the root. */
+ ucReturn = f_chdir( pcDirectory2 );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "In directory %s\r\n", cRAMBuffer );
+ configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );
+
+ /* Generate the file name. */
+ sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+ /* Print out the file name and the directory into which the file is being
+ written. */
+ printf( "Writing file %s in %s\r\n", cFileName, cRAMBuffer );
+
+ pxFile = f_open( cFileName, "w" );
+
+ /* Create a file 1 byte at a time. The file is filled with incrementing
+ ascii characters starting from '0'. */
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+ {
+ iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );
+ }
+
+ /* Finished so close the file. */
+ f_close( pxFile );
+
+ /* Move back to the root directory. */
+ ucReturn = f_chdir( "../.." );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Back in root directory %s\r\n", cRAMBuffer );
+ configASSERT( strcmp( ( const char * ) cRAMBuffer, pcRoot ) == 0 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_getc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+ /* Move into the directory in which the file was created. */
+ ucReturn = f_chdir( pcFullPath );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Back in directory %s\r\n", cRAMBuffer );
+ configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );
+
+ /* Generate the file name. */
+ sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+ /* Print out the file name and the directory from which the file is being
+ read. */
+ printf( "Reading file %s in %s\r\n", cFileName, cRAMBuffer );
+
+ /* This time the file is opened for reading. */
+ pxFile = f_open( cFileName, "r" );
+
+ /* Read the file 1 byte at a time. */
+ for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+ {
+ iReturned = f_getc( pxFile );
+ configASSERT( iReturned == ( ( int ) '0' + iByte ) );
+ }
+
+ /* Finished so close the file. */
+ f_close( pxFile );
+
+ /* Move back to the root directory. */
+ ucReturn = f_chdir( "../.." );
+ configASSERT( ucReturn == F_NO_ERROR );
+
+ /* Obtain and print out the working directory. */
+ f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+ printf( "Back in root directory %s\r\n", cRAMBuffer );
+}
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/Sample-CLI-commands.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/Sample-CLI-commands.c
new file mode 100644
index 000000000..9cace7971
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/Sample-CLI-commands.c
@@ -0,0 +1,432 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include
+#include
+#include
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+ #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Registers the CLI commands defined within this file with the FreeRTOS+CLI
+ * command line interface.
+ */
+void vRegisterSampleCLICommands( void );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+#endif
+
+/* Structure that defines the "run-time-stats" command line command. This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+ "run-time-stats", /* The command string to type. */
+ "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",
+ prvRunTimeStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command. This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+ "task-stats", /* The command string to type. */
+ "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",
+ prvTaskStatsCommand, /* The function to run. */
+ 0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command. This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+ "echo-3-parameters",
+ "\r\necho-3-parameters :\r\n Expects three parameters, echos each in turn\r\n",
+ prvThreeParameterEchoCommand, /* The function to run. */
+ 3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command. This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+ "echo-parameters",
+ "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",
+ prvParameterEchoCommand, /* The function to run. */
+ -1 /* The user can enter any number of commands. */
+};
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+ /* Structure that defines the "trace" command line command. This takes a single
+ parameter, which can be either "start" or "stop". */
+ static const CLI_Command_Definition_t xStartStopTrace =
+ {
+ "trace",
+ "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",
+ prvStartStopTraceCommand, /* The function to run. */
+ 1 /* One parameter is expected. Valid values are "start" and "stop". */
+ };
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterSampleCLICommands( void )
+{
+ /* Register all the command line commands defined immediately above. */
+ FreeRTOS_CLIRegisterCommand( &xTaskStats );
+ FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+ FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+ FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+
+ #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )
+ {
+ FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t *const pcHeader = ( int8_t * ) "Task State Priority Stack #\r\n************************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+ vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t * const pcHeader = ( int8_t * ) "Task Abs Time % Time\r\n****************************************\r\n";
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Generate a table of task stats. */
+ strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+ vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+ strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ if( lParameterNumber == 3L )
+ {
+ /* If this is the last of the three parameters then there are no more
+ strings to return after this one. */
+ xReturn = pdFALSE;
+ lParameterNumber = 0L;
+ }
+ else
+ {
+ /* There are more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ if( lParameterNumber == 0 )
+ {
+ /* The first time the function is called after the command has been
+ entered just a header string is returned. */
+ sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );
+
+ /* Next time the function is called the first parameter will be echoed
+ back. */
+ lParameterNumber = 1L;
+
+ /* There is more data to be returned as no parameters have been echoed
+ back yet. */
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* Obtain the parameter string. */
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ lParameterNumber, /* Return the next parameter. */
+ &xParameterStringLength /* Store the parameter string length. */
+ );
+
+ if( pcParameter != NULL )
+ {
+ /* Return the parameter string. */
+ memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+ sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+ strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+ strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+ /* There might be more parameters to return after this one. */
+ xReturn = pdTRUE;
+ lParameterNumber++;
+ }
+ else
+ {
+ /* No more parameters were found. Make sure the write buffer does
+ not contain a valid string. */
+ pcWriteBuffer[ 0 ] = 0x00;
+
+ /* No more data to return. */
+ xReturn = pdFALSE;
+
+ /* Start over the next time this command is executed. */
+ lParameterNumber = 0;
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+ static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+ {
+ int8_t *pcParameter;
+ portBASE_TYPE lParameterStringLength;
+
+ /* Remove compile time warnings about unused parameters, and check the
+ write buffer is not NULL. NOTE - for simplicity, this example assumes the
+ write buffer length is adequate, so does not check for buffer overflows. */
+ ( void ) pcCommandString;
+ ( void ) xWriteBufferLen;
+ configASSERT( pcWriteBuffer );
+
+ /* Obtain the parameter string. */
+ pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+ (
+ pcCommandString, /* The command string itself. */
+ 1, /* Return the first parameter. */
+ &lParameterStringLength /* Store the parameter string length. */
+ );
+
+ /* Sanity check something was returned. */
+ configASSERT( pcParameter );
+
+ /* There are only two valid parameter values. */
+ if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )
+ {
+ /* Start or restart the trace. */
+ vTraceStop();
+ vTraceClear();
+ vTraceStart();
+
+ sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );
+ }
+ else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )
+ {
+ /* End the trace, if one is running. */
+ vTraceStop();
+ sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );
+ }
+ else
+ {
+ sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+ }
+
+ /* There is no more data to return after this single string, so return
+ pdFALSE. */
+ return pdFALSE;
+ }
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/UARTCommandConsole.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/UARTCommandConsole.c
new file mode 100644
index 000000000..ac17672bd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/UARTCommandConsole.c
@@ -0,0 +1,200 @@
+/*
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/* Standard includes. */
+#include "string.h"
+#include "stdio.h"
+#include "stdint.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Common demo includes. */
+#include "serial.h"
+
+/* Example includes. */
+#include "FreeRTOS_CLI.h"
+#include "UARTCommandConsole.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE 50
+
+/* The maximum time in ticks to wait for the UART access mutex. */
+#define cmdMAX_MUTEX_WAIT ( 200 / portTICK_RATE_MS )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that implements the command console processing.
+ */
+static void prvUARTCommandConsoleTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Const messages output by the command console. */
+static const signed char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
+static const signed char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";
+static const signed char * const pcNewLine = "\r\n";
+
+/*-----------------------------------------------------------*/
+
+void vUARTCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority )
+{
+ /* Create that task that handles the console itself. */
+ xTaskCreate( prvUARTCommandConsoleTask, /* The task that implements the command console. */
+ "CLI", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */
+ usStackSize, /* The size of the stack allocated to the task. */
+ NULL, /* The parameter is not used, so NULL is passed. */
+ uxPriority, /* The priority allocated to the task. */
+ NULL ); /* A handle is not required, so just pass NULL. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvUARTCommandConsoleTask( void *pvParameters )
+{
+int8_t cRxedChar, cInputIndex = 0, *pcOutputString;
+static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
+portBASE_TYPE xReturned;
+
+ ( void ) pvParameters;
+
+ /* Obtain the address of the output buffer. Note there is no mutual
+ exclusion on this buffer as it is assumed only one command console
+ interface will be used at any one time. */
+ pcOutputString = FreeRTOS_CLIGetOutputBuffer();
+
+ /* Send the welcome message. */
+ vSerialPutString( NULL, pcWelcomeMessage, strlen( ( char * ) pcWelcomeMessage ) );
+
+ for( ;; )
+ {
+ /* Only interested in reading one character at a time. */
+ while( xSerialGetChar( NULL, &cRxedChar, portMAX_DELAY ) == pdFALSE );
+
+ /* Echo the character back. */
+ xSerialPutChar( NULL, cRxedChar, portMAX_DELAY );
+
+ /* Was it the end of the line? */
+ if( cRxedChar == '\n' || cRxedChar == '\r' )
+ {
+ /* Just to space the output from the input. */
+ vSerialPutString( NULL, pcNewLine, strlen( ( char * ) pcNewLine ) );
+
+ /* See if the command is empty, indicating that the last command is
+ to be executed again. */
+ if( cInputIndex == 0 )
+ {
+ /* Copy the last command back into the input string. */
+ strcpy( ( char * ) cInputString, ( char * ) cLastInputString );
+ }
+
+ /* Pass the received command to the command interpreter. The
+ command interpreter is called repeatedly until it returns pdFALSE
+ (indicating there is no more output) as it might generate more than
+ one string. */
+ do
+ {
+ /* Get the next output string from the command interpreter. */
+ xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
+
+ /* Write the generated string to the UART. */
+ vSerialPutString( NULL, pcOutputString, strlen( ( char * ) pcOutputString ) );
+
+ } while( xReturned != pdFALSE );
+
+ /* All the strings generated by the input command have been sent.
+ Clear the input string ready to receive the next command. Remember
+ the command that was just processed first in case it is to be
+ processed again. */
+ strcpy( ( char * ) cLastInputString, ( char * ) cInputString );
+ cInputIndex = 0;
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+ vSerialPutString( NULL, pcEndOfOutputMessage, strlen( ( char * ) pcEndOfOutputMessage ) );
+ }
+ else
+ {
+ if( cRxedChar == '\r' )
+ {
+ /* Ignore the character. */
+ }
+ else if( cRxedChar == '\b' )
+ {
+ /* Backspace was pressed. Erase the last character in the
+ string - if any. */
+ if( cInputIndex > 0 )
+ {
+ cInputIndex--;
+ cInputString[ cInputIndex ] = '\0';
+ }
+ }
+ else
+ {
+ /* A character was entered. Add it to the string
+ entered so far. When a \n is entered the complete
+ string will be passed to the command interpreter. */
+ if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
+ {
+ if( cInputIndex < cmdMAX_INPUT_SIZE )
+ {
+ cInputString[ cInputIndex ] = cRxedChar;
+ cInputIndex++;
+ }
+ }
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/UARTCommandConsole.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/UARTCommandConsole.h
new file mode 100644
index 000000000..8ea292f04
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/UARTCommandConsole.h
@@ -0,0 +1,87 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+#ifndef UART_COMMAND_CONSOLE_H
+#define UART_COMMAND_CONSOLE_H
+
+/*
+ * Create the task that implements a command console using the USB virtual com
+ * port driver for intput and output.
+ */
+void vUARTCommandConsoleStart( unsigned short usStackSize, unsigned portBASE_TYPE uxPriority );
+
+#endif /* UART_COMMAND_CONSOLE_H */
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_fat_sl.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_fat_sl.h
new file mode 100644
index 000000000..a51ecb8ed
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_fat_sl.h
@@ -0,0 +1,67 @@
+/*
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_FAT_SL_H
+#define _CONFIG_FAT_SL_H
+
+#include "../version/ver_fat_sl.h"
+#if VER_FAT_SL_MAJOR != 3 || VER_FAT_SL_MINOR != 2
+ #error Incompatible FAT_SL version number!
+#endif
+
+#include "../api/api_mdriver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************************************************************
+**
+** FAT SL user settings
+**
+**************************************************************************/
+#define F_SECTOR_SIZE 512u /* Disk sector size. */
+#define F_FS_THREAD_AWARE 0 /* Set to one if the file system will be access from more than one task. */
+#define F_MAXPATH 64 /* Maximum length a file name (including its full path) can be. */
+#define F_MAX_LOCK_WAIT_TICKS 20 /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CONFIG_FAT_SL_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_mdriver_ram.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_mdriver_ram.h
new file mode 100644
index 000000000..b769abe9f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/config_mdriver_ram.h
@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_MDRIVER_RAM_H_
+#define _CONFIG_MDRIVER_RAM_H_
+
+#include "../version/ver_mdriver_ram.h"
+#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2
+ #error Incompatible MDRIVER_RAM version number!
+#endif
+
+#define MDRIVER_RAM_SECTOR_SIZE 512 /* Sector size */
+
+#define MDRIVER_RAM_VOLUME0_SIZE (64 * 1024) /* defintion for size of ramdrive0 */
+
+#define MDRIVER_MEM_LONG_ACCESS 1 /* set this value to 1 if 32bit access available */
+
+#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/main_full.c
new file mode 100644
index 000000000..3c893cebf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/main_full.c
@@ -0,0 +1,518 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ * NOTE 1: This project provides two demo applications. A simple blinky style
+ * project, and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c. This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2: This file only contains the source code that is specific to the
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ * NOTE 3: If mainINCLUDE_FAT_SL_DEMO is set to 1 then the UART is used to
+ * interface to the FreeRTOS+CLI command line interface. If
+ * mainINCLUDE_FAT_SL_DEMO is set to 0 then the UART is used to run the standard
+ * COM test tasks and a loopback connector must be fitted to the UART port
+ * because the test expects to receive every character that is transmitted. A
+ * simple loopback connector can be created by linking pins 2 and 3 of the 9 way
+ * UART connector.
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler. The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * FreeRTOS+CLI command console. The command console is access through UART2
+ * using 115200 baud if mainINCLUDE_FAT_SL_DEMO is set to 1. For reasons of
+ * robustness testing the UART driver is deliberately written to be inefficient
+ * and should not be used as a template for a production driver. Type "help" to
+ * see a list of registered commands. The FreeRTOS+CLI license is different to
+ * the FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage
+ * details.
+ *
+ * FreeRTOS+FAT SL. FreeRTOS+FAT SL is demonstrated using a RAM disk if
+ * mainINCLUDE_FAT_SL_DEMO is set to 1. [At the time of writing] The
+ * functionality of the file system demo is identical to the functionality of
+ * the FreeRTOS Win32 simulator file system demo, with the command console being
+ * accessed via the UART (as described above) instead of a network terminal.
+ * The FreeRTOS+FAT SL license is different to the FreeRTOS license, see
+ * http://www.FreeRTOS.org/fat_sl for license and usage details, and a
+ * description of the file system demo functionality.
+ *
+ * "Reg test" tasks - These fill both the core and floating point registers with
+ * known values, then check that each register maintains its expected value for
+ * the lifetime of the task. Each task uses a different set of values. The reg
+ * test tasks execute with a very low priority, so get preempted very
+ * frequently. A register containing an unexpected value is indicative of an
+ * error in the context switching mechanism.
+ *
+ * "Check" task - The check task period is initially set to three seconds. The
+ * task checks that all the standard demo tasks, and the register check tasks,
+ * are not only still executing, but are executing without reporting any errors.
+ * If the check task discovers that a task has either stalled, or reported an
+ * error, then it changes its own execution period from the initial three
+ * seconds, to just 200ms. The check task also toggles an LED each time it is
+ * called. This provides a visual indication of the system status: If the LED
+ * toggles every three seconds, then no issues have been discovered. If the LED
+ * toggles every 200ms, then an issue has been discovered with at least one
+ * task.
+ */
+
+/* Standard includes. */
+#include
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "flop.h"
+#include "semtest.h"
+#include "dynamic.h"
+#include "BlockQ.h"
+#include "blocktim.h"
+#include "countsem.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "death.h"
+#include "partest.h"
+#include "comtest2.h"
+#include "serial.h"
+#include "TimerDemo.h"
+
+/* FreeRTOS+CLI and FreeRTOS+FAT SL includes. */
+#include "UARTCommandConsole.h"
+
+/* Either the FreeRTOS+FAT SL demo or the COM test demo can be build into the
+project, not both (because they use the same UART). Set
+configINCLUDE_FAT_SL_DEMO to 1 to include the FreeRTOS+FAT SL (and therefore
+also FreeRTOS+CLI) demo in the build. Set configINCLUDE_FAT_SL_DEMO to 0 to
+include the COM test tasks. The COM test tasks require a loop back connector
+to be fitted to the UART port. */
+#define mainINCLUDE_FAT_SL_DEMO 0
+
+/* Priorities for the demo application tasks. */
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+
+/* The priority used by the UART command console task. */
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
+
+/* The LED used by the check timer. */
+#define mainCHECK_LED ( 0 )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK ( 0UL )
+
+/* In this example the baud rate is hard coded and there is no LED for use by
+the COM test tasks, so just set both to invalid values. */
+#define mainCOM_TEST_LED ( 100 )
+#define mainBAUD_RATE ( 0 )
+
+/* The period after which the check timer will expire, in ms, provided no errors
+have been reported by any of the standard demo tasks. ms are converted to the
+equivalent in ticks using the portTICK_RATE_MS constant. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_RATE_MS )
+
+/* The period at which the check timer will expire, in ms, if an error has been
+reported in one of the standard demo tasks. ms are converted to the equivalent
+in ticks using the portTICK_RATE_MS constant. */
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_RATE_MS )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctly. */
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD ( 50 )
+
+/* The length of queues used to pass characters into and out of the UART
+interrupt. Note the comments above about the UART driver being implemented in
+this way to test the kernel robustness rather than to provide a template for an
+efficient production driver. */
+#define mainUART_QUEUE_LENGTHS 10
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main() to run the full demo (as opposed to the blinky demo) when
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+void main_full( void );
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Register check tasks, and the tasks used to write over and check the contents
+ * of the FPU registers, as described at the top of this file. The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Register commands that can be used with FreeRTOS+CLI. The commands are
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
+ */
+extern void vRegisterSampleCLICommands( void );
+extern void vRegisterFileSystemCLICommands( void );
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+extern void vCreateAndVerifySampleFiles( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check software timer. If the variables keep
+incrementing, then the register check tasks has not discovered any errors. If
+a variable stops incrementing, then an error has been found. */
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+ /* The baud rate setting here has no effect, hence it is set to 0 to
+ make that obvious. */
+ xSerialPortInitMinimal( 0, mainUART_QUEUE_LENGTHS );
+
+ /* If the file system is only going to be accessed from one task then
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files are created
+ before the RTOS scheduler is started. If the file system is going to be
+ access from more than one task then F_FS_THREAD_AWARE must be set to 1 and
+ the set of sample files are created from the idle task hook function
+ vApplicationIdleHook() - which is defined in this file. */
+ #if ( mainINCLUDE_FAT_SL_DEMO == 1 )&& ( F_FS_THREAD_AWARE == 0 )
+ {
+ /* Initialise the drive and file system, then create a few example
+ files. The output from this function just goes to the stdout window,
+ allowing the output to be viewed when the UDP command console is not
+ connected. */
+ vCreateAndVerifySampleFiles();
+ }
+ #endif
+
+ /* Start all the other standard demo/test tasks. The have not particular
+ functionality, but do demonstrate how to use the FreeRTOS API and test the
+ kernel port. */
+ vStartDynamicPriorityTasks();
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+ vCreateBlockTimeTasks();
+ vStartCountingSemaphoreTasks();
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );
+ vStartRecursiveMutexTasks();
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+
+ #if mainINCLUDE_FAT_SL_DEMO == 1
+ {
+ /* Start the tasks that implements the command console on the UART, as
+ described above. */
+ vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );
+
+ /* Register both the standard and file system related CLI commands. */
+ vRegisterSampleCLICommands();
+ vRegisterFileSystemCLICommands();
+ }
+ #else
+ {
+ /* The COM test tasks can use the UART if the CLI is not used by the
+ FAT SL demo. The COM test tasks require a UART connector to be fitted
+ to the UART port. */
+ vAltStartComTestTasks( mainCOM_TEST_TASK_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );
+ }
+ #endif
+
+
+ /* Create the register check tasks, as described at the top of this
+ file */
+ xTaskCreate( prvRegTestTaskEntry1, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvRegTestTaskEntry2, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+ /* Create the task that performs the 'check' functionality, as described at
+ the top of this file. */
+ xTaskCreate( prvCheckTask, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+ /* The set of tasks created by the following function call have to be
+ created last as they keep account of the number of tasks they expect to see
+ running. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Start the scheduler. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was either insufficient FreeRTOS heap memory available for the idle
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from
+ User mode. See the memory management section on the FreeRTOS web site for
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
+ mode from which main() is called is set in the C start up code and must be
+ a privileged mode (not user mode). */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+portTickType xLastExecutionTime;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+unsigned long ulErrorFound = pdFALSE;
+
+ /* Just to stop compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+ works correctly. */
+ xLastExecutionTime = xTaskGetTickCount();
+
+ /* Cycle for ever, delaying then checking all the other tasks are still
+ operating without error. The onboard LED is toggled on each iteration.
+ If an error is detected then the delay period is decreased from
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
+ effect of increasing the rate at which the onboard LED toggles, and in so
+ doing gives visual feedback of the system status. */
+ for( ;; )
+ {
+ /* Delay until it is time to execute again. */
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+ /* Check all the demo tasks (other than the flash tasks) to ensure
+ that they are all still running, and that none have detected an error. */
+ if( xAreMathsTaskStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreTimerDemoTasksStillRunning( ( portTickType ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ #if mainINCLUDE_FAT_SL_DEMO == 0
+ {
+ if( xAreComTestTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+ }
+ #endif
+
+ /* Check that the register test 1 task is still running. */
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+ {
+ ulErrorFound = pdTRUE;
+ }
+ ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+ /* Check that the register test 2 task is still running. */
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+ {
+ ulErrorFound = pdTRUE;
+ }
+ ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+ /* Toggle the check LED to give an indication of the system status. If
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
+ everything is ok. A faster toggle indicates an error. */
+ vParTestToggleLED( mainCHECK_LED );
+
+ if( ulErrorFound != pdFALSE )
+ {
+ /* An error has been detected in one of the tasks - flash the LED
+ at a higher frequency to give visible feedback that something has
+ gone wrong (it might just be that the loop back connector required
+ by the comtest tasks has not been fitted). */
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+ /* Although the regtest task is written in assembler, its entry point is
+ written in C for convenience of checking the task parameter is being passed
+ in correctly. */
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+ {
+ /* The reg test task also tests the floating point registers. Tasks
+ that use the floating point unit must call vPortTaskUsesFPU() before
+ any floating point instructions are executed. */
+ vPortTaskUsesFPU();
+
+ /* Start the part of the test that is written in assembler. */
+ vRegTest1Implementation();
+ }
+
+ /* The following line will only execute if the task parameter is found to
+ be incorrect. The check timer will detect that the regtest loop counter is
+ not being incremented and flag an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+ /* Although the regtest task is written in assembler, its entry point is
+ written in C for convenience of checking the task parameter is being passed
+ in correctly. */
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+ {
+ /* The reg test task also tests the floating point registers. Tasks
+ that use the floating point unit must call vPortTaskUsesFPU() before
+ any floating point instructions are executed. */
+ vPortTaskUsesFPU();
+
+ /* Start the part of the test that is written in assembler. */
+ vRegTest2Implementation();
+ }
+
+ /* The following line will only execute if the task parameter is found to
+ be incorrect. The check timer will detect that the regtest loop counter is
+ not being incremented and flag an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/reg_test.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/reg_test.s
new file mode 100644
index 000000000..d93fc9352
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/reg_test.s
@@ -0,0 +1,670 @@
+;/*
+; FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+;
+; FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+; http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+;
+; ***************************************************************************
+; * *
+; * FreeRTOS tutorial books are available in pdf and paperback. *
+; * Complete, revised, and edited pdf reference manuals are also *
+; * available. *
+; * *
+; * Purchasing FreeRTOS documentation will not only help you, by *
+; * ensuring you get running as quickly as possible and with an *
+; * in-depth knowledge of how to use FreeRTOS, it will also help *
+; * the FreeRTOS project to continue with its mission of providing *
+; * professional grade, cross platform, de facto standard solutions *
+; * for microcontrollers - completely free of charge! *
+; * *
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+; * *
+; * Thank you for using FreeRTOS, and thank you for your support! *
+; * *
+; ***************************************************************************
+;
+;
+; This file is part of the FreeRTOS distribution.
+;
+; FreeRTOS is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License (version 2) as published by the
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+;
+; >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+; distribute a combined work that includes FreeRTOS without being obliged to
+; provide the source code for proprietary components outside of the FreeRTOS
+; kernel.
+;
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+; FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+; details. You should have received a copy of the GNU General Public License
+; and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+; viewed here: http://www.freertos.org/a00114.html and also obtained by
+; writing to Real Time Engineers Ltd., contact details for whom are available
+; on the FreeRTOS WEB site.
+;
+; 1 tab == 4 spaces!
+;
+; ***************************************************************************
+; * *
+; * Having a problem? Start by reading the FAQ "My application does *
+; * not run, what could be wrong?" *
+; * *
+; * http://www.FreeRTOS.org/FAQHelp.html *
+; * *
+; ***************************************************************************
+;
+;
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+; license and Real Time Engineers Ltd. contact details.
+;
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+; including FreeRTOS+Trace - an indispensable productivity tool, and our new
+; fully thread aware and reentrant UDP/IP stack.
+;
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+; Integrity Systems, who sell the code with commercial support,
+; indemnification and middleware, under the OpenRTOS brand.
+;
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+; engineered and independently SIL3 certified version for use in safety and
+; mission critical applications that require provable dependability.
+;*/
+
+ EXPORT vRegTest1Implementation
+ EXPORT vRegTest2Implementation
+
+ ; This file is built with IAR and ARM compilers. When the ARM compiler
+ ; is used the compiler options must define __IASMARM__ as 0 using the
+ ; --predefine "__IASMARM__ SETA 0" command line option. When compiling
+ ; with IAR __IASMARM__ is automatically set to 1 so no additional assembler
+ ; options are required.
+ if __IASMARM__ == 1
+ ; Syntax for IAR compiler.
+ SECTION .text:CODE:ROOT(2)
+ else
+ ; Syntax for ARM compiler.
+ AREA RegTest, CODE, READONLY
+ endif
+ ARM
+
+ ; This function is explained in the comments at the top of main-full.c.
+vRegTest1Implementation
+
+ PRESERVE8
+ IMPORT ulRegTest1LoopCounter
+
+ ; Fill each general purpose register with a known value.
+ mov r0, #0xFF
+ mov r1, #0x11
+ mov r2, #0x22
+ mov r3, #0x33
+ mov r4, #0x44
+ mov r5, #0x55
+ mov r6, #0x66
+ mov r7, #0x77
+ mov r8, #0x88
+ mov r9, #0x99
+ mov r10, #0xAA
+ mov r11, #0xBB
+ mov r12, #0xCC
+ mov r14, #0xEE
+
+ ; Fill each FPU register with a known value.
+ vmov d0, r0, r1
+ vmov d1, r2, r3
+ vmov d2, r4, r5
+ vmov d3, r6, r7
+ vmov d4, r8, r9
+ vmov d5, r10, r11
+ vmov d6, r0, r1
+ vmov d7, r2, r3
+ vmov d8, r4, r5
+ vmov d9, r6, r7
+ vmov d10, r8, r9
+ vmov d11, r10, r11
+ vmov d12, r0, r1
+ vmov d13, r2, r3
+ vmov d14, r4, r5
+ vmov d15, r6, r7
+
+ vmov d16, r0, r1
+ vmov d17, r2, r3
+ vmov d18, r4, r5
+ vmov d19, r6, r7
+ vmov d20, r8, r9
+ vmov d21, r10, r11
+ vmov d22, r0, r1
+ vmov d23, r2, r3
+ vmov d24, r4, r5
+ vmov d25, r6, r7
+ vmov d26, r8, r9
+ vmov d27, r10, r11
+ vmov d28, r0, r1
+ vmov d29, r2, r3
+ vmov d30, r4, r5
+ vmov d31, r6, r7
+
+ ; Loop, checking each itteration that each register still contains the
+ ; expected value.
+reg1_loop
+ ; Yield to increase test coverage
+ svc 0
+
+ ; Check all the VFP registers still contain the values set above.
+ ; First save registers that are clobbered by the test.
+ push { r0-r1 }
+
+ vmov r0, r1, d0
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d1
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d2
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d3
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d4
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d5
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d6
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d7
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d8
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d9
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d10
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d11
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d12
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d13
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d14
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d15
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+
+ vmov r0, r1, d16
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d17
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d18
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d19
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d20
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d21
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d22
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d23
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d24
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d25
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d26
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d27
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d28
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d29
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d30
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d31
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+
+ ; Restore the registers that were clobbered by the test.
+ pop {r0-r1}
+
+ ; VFP register test passed. Jump to the core register test.
+ b reg1_loopf_pass
+
+reg1_error_loopf
+ ; If this line is hit then a VFP register value was found to be
+ ; incorrect.
+ b reg1_error_loopf
+
+reg1_loopf_pass
+
+ ; Test each general purpose register to check that it still contains the
+ ; expected known value, jumping to reg1_error_loop if any register contains
+ ; an unexpected value.
+ cmp r0, #0xFF
+ bne reg1_error_loop
+ cmp r1, #0x11
+ bne reg1_error_loop
+ cmp r2, #0x22
+ bne reg1_error_loop
+ cmp r3, #0x33
+ bne reg1_error_loop
+ cmp r4, #0x44
+ bne reg1_error_loop
+ cmp r5, #0x55
+ bne reg1_error_loop
+ cmp r6, #0x66
+ bne reg1_error_loop
+ cmp r7, #0x77
+ bne reg1_error_loop
+ cmp r8, #0x88
+ bne reg1_error_loop
+ cmp r9, #0x99
+ bne reg1_error_loop
+ cmp r10, #0xAA
+ bne reg1_error_loop
+ cmp r11, #0xBB
+ bne reg1_error_loop
+ cmp r12, #0xCC
+ bne reg1_error_loop
+ cmp r14, #0xEE
+ bne reg1_error_loop
+
+ ; Everything passed, increment the loop counter.
+ push { r0-r1 }
+ ldr r0, =ulRegTest1LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0-r1 }
+
+ ; Start again.
+ b reg1_loop
+
+reg1_error_loop
+ ; If this line is hit then there was an error in a core register value.
+ ; The loop ensures the loop counter stops incrementing.
+ b reg1_error_loop
+ nop
+
+;/*-----------------------------------------------------------*/
+
+vRegTest2Implementation
+
+ PRESERVE8
+ IMPORT ulRegTest2LoopCounter
+
+ ; Put a known value in each register.
+ mov r0, #0xFF000000
+ mov r1, #0x11000000
+ mov r2, #0x22000000
+ mov r3, #0x33000000
+ mov r4, #0x44000000
+ mov r5, #0x55000000
+ mov r6, #0x66000000
+ mov r7, #0x77000000
+ mov r8, #0x88000000
+ mov r9, #0x99000000
+ mov r10, #0xAA000000
+ mov r11, #0xBB000000
+ mov r12, #0xCC000000
+ mov r14, #0xEE000000
+
+ ; Likewise the floating point registers
+ vmov d0, r0, r1
+ vmov d1, r2, r3
+ vmov d2, r4, r5
+ vmov d3, r6, r7
+ vmov d4, r8, r9
+ vmov d5, r10, r11
+ vmov d6, r0, r1
+ vmov d7, r2, r3
+ vmov d8, r4, r5
+ vmov d9, r6, r7
+ vmov d10, r8, r9
+ vmov d11, r10, r11
+ vmov d12, r0, r1
+ vmov d13, r2, r3
+ vmov d14, r4, r5
+ vmov d15, r6, r7
+
+ vmov d16, r0, r1
+ vmov d17, r2, r3
+ vmov d18, r4, r5
+ vmov d19, r6, r7
+ vmov d20, r8, r9
+ vmov d21, r10, r11
+ vmov d22, r0, r1
+ vmov d23, r2, r3
+ vmov d24, r4, r5
+ vmov d25, r6, r7
+ vmov d26, r8, r9
+ vmov d27, r10, r11
+ vmov d28, r0, r1
+ vmov d29, r2, r3
+ vmov d30, r4, r5
+ vmov d31, r6, r7
+
+ ; Loop, checking each itteration that each register still contains the
+ ; expected value.
+reg2_loop
+ ; Check all the VFP registers still contain the values set above.
+ ; First save registers that are clobbered by the test.
+ push { r0-r1 }
+
+ vmov r0, r1, d0
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d1
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d2
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d3
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d4
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d5
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d6
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d7
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d8
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d9
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d10
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d11
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d12
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d13
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d14
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d15
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+
+ vmov r0, r1, d16
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d17
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d18
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d19
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d20
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d21
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d22
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d23
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d24
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d25
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d26
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d27
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d28
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d29
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d30
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d31
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+
+ ; Restore the registers that were clobbered by the test.
+ pop {r0-r1}
+
+ ; VFP register test passed. Jump to the core register test.
+ b reg2_loopf_pass
+
+reg2_error_loopf
+ ; If this line is hit then a VFP register value was found to be
+ ; incorrect.
+ b reg2_error_loopf
+
+reg2_loopf_pass
+
+ cmp r0, #0xFF000000
+ bne reg2_error_loop
+ cmp r1, #0x11000000
+ bne reg2_error_loop
+ cmp r2, #0x22000000
+ bne reg2_error_loop
+ cmp r3, #0x33000000
+ bne reg2_error_loop
+ cmp r4, #0x44000000
+ bne reg2_error_loop
+ cmp r5, #0x55000000
+ bne reg2_error_loop
+ cmp r6, #0x66000000
+ bne reg2_error_loop
+ cmp r7, #0x77000000
+ bne reg2_error_loop
+ cmp r8, #0x88000000
+ bne reg2_error_loop
+ cmp r9, #0x99000000
+ bne reg2_error_loop
+ cmp r10, #0xAA000000
+ bne reg2_error_loop
+ cmp r11, #0xBB000000
+ bne reg2_error_loop
+ cmp r12, #0xCC000000
+ bne reg2_error_loop
+ cmp r14, #0xEE000000
+ bne reg2_error_loop
+
+ ; Everything passed, increment the loop counter.
+ push { r0-r1 }
+ ldr r0, =ulRegTest2LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0-r1 }
+
+ ; Start again.
+ b reg2_loop
+
+reg2_error_loop
+ ; If this line is hit then there was an error in a core register value.
+ ; The loop ensures the loop counter stops incrementing.
+ b reg2_error_loop
+ nop
+
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/serial.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/serial.c
new file mode 100644
index 000000000..e11888485
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/Full-Demo/serial.c
@@ -0,0 +1,301 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/*
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART2.
+
+ ***Note*** This example uses queues to send each character into an interrupt
+ service routine and out of an interrupt service routine individually. This
+ is done to demonstrate queues being used in an interrupt, and to deliberately
+ load the system to test the FreeRTOS port. It is *NOT* meant to be an
+ example of an efficient implementation. An efficient implementation should
+ use the DMA, and only use FreeRTOS API functions when enough has been
+ received to warrant a task being unblocked to process the data.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "semphr.h"
+#include "comtest2.h"
+
+/* Driver includes. */
+#include "r_typedefs.h"
+#include "dev_drv.h"
+#include "devdrv_scif_uart.h"
+#include "sio_char.h"
+#include "iodefine.h"
+#include "devdrv_intc.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Misc defines. */
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
+#define serNO_BLOCK ( ( portTickType ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Handlers for the Rx and Tx interrupts respectively. */
+static void prvRXI_Handler( uint32_t ulUnusedParameter );
+static void prvTXI_Handler( uint32_t ulUnusedParameter );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See the serial2.h header file.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+ /* Baud is set in IoInitScif2(), called in prvSetupHardware() in main.c. */
+ ( void ) ulWantedBaud;
+
+ /* Create the queues used to hold Rx/Tx characters. Note the comments at
+ the top of this file regarding the use of queues in this manner. */
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
+
+ /* If the queues were created correctly then setup the serial port
+ hardware. */
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
+ {
+ /* Register RXI and TXI handlers. */
+ R_INTC_RegistIntFunc( INTC_ID_RXI2, prvRXI_Handler );
+ R_INTC_RegistIntFunc( INTC_ID_TXI2, prvTXI_Handler );
+
+ /* Set both interrupts such that they can interrupt the tick. Also
+ set the Rx interrupt above the Tx interrupt in the hope that (for test
+ purposes) the Tx interrupt will interrupt the Rx interrupt. */
+ R_INTC_SetPriority( INTC_ID_RXI2, configMAX_API_CALL_INTERRUPT_PRIORITY );
+ R_INTC_SetPriority( INTC_ID_TXI2, ( configMAX_API_CALL_INTERRUPT_PRIORITY + 1 ) );
+
+ /* This driver is intended to test interrupt interactions, and not
+ intended to be efficient. Therefore set the RX trigger level to 1. */
+ SCIF2.SCFCR.BIT.RTRG = 0;
+ SCIF2.SCFCR.BIT.TTRG = 3;
+
+ /* Enable Rx interrupt. Tx interrupt will be enabled when a Tx is
+ performed. */
+ SCIF2.SCSCR.BIT.RIE = 1;
+ R_INTC_Enable( INTC_ID_RXI2 );
+ R_INTC_Enable( INTC_ID_TXI2 );
+ }
+
+ /* This demo file only supports a single port but we have to return
+ something to comply with the standard demo header file. */
+ return ( xComPortHandle ) 0;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
+{
+ /* The port handle is not required as this driver only supports one port. */
+ ( void ) pxPort;
+
+ /* Get the next character from the buffer. Return false if no characters
+ are available, or arrive before xBlockTime expires. */
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+ {
+ return pdTRUE;
+ }
+ else
+ {
+ return pdFALSE;
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned portSHORT usStringLength )
+{
+signed char *pxNext;
+
+ /* A couple of parameters that this port does not use. */
+ ( void ) usStringLength;
+ ( void ) pxPort;
+
+ /* Send each character in the string, one at a time. */
+ pxNext = ( signed char * ) pcString;
+ while( *pxNext )
+ {
+ xSerialPutChar( pxPort, *pxNext, portMAX_DELAY );
+ pxNext++;
+ }
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+ /* Note the comments at the top of this file regarding the use of queues in
+ this manner. */
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
+ {
+ xReturn = pdPASS;
+
+ /* Enable the interrupt which will remove the character from the
+ queue. */
+ SCIF2.SCSCR.BIT.TIE = 1;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+ /* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvRXI_Handler( uint32_t ulUnusedParameter )
+{
+unsigned char ucRxedByte;
+long lHigherPriorityTaskWoken = pdFALSE;
+
+ /* The parameter is not used. It is only present because Renesas drivers
+ are used to install the interrupt handlers, and the drivers expect the
+ parameter to be present. */
+ ( void ) ulUnusedParameter;
+
+ /* Note the comments at the top of this file regarding the use of queues in
+ this manner. */
+ while( ( SCIF2.SCFDR.WORD & 0x1F ) != 0 )
+ {
+ ucRxedByte = SCIF2.SCFRDR.BYTE;
+ xQueueSendFromISR( xRxedChars, &ucRxedByte, &lHigherPriorityTaskWoken );
+ }
+
+ SCIF2.SCFSR.BIT.RDF = 0;
+
+ /* If sending to the queue has caused a task to unblock, and the unblocked
+ task has a priority equal to or higher than the currently running task (the
+ task this ISR interrupted), then lHigherPriorityTaskWoken will have
+ automatically been set to pdTRUE within the queue send function.
+ portYIELD_FROM_ISR() will then ensure that this ISR returns directly to the
+ higher priority unblocked task. */
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTXI_Handler( uint32_t ulUnusedParameter )
+{
+unsigned char ucByte;
+long lHigherPriorityTaskWoken = pdFALSE;
+
+ /* The parameter is not used. It is only present because Renesas drivers
+ are used to install the interrupt handlers, and the drivers expect the
+ parameter to be present. */
+ ( void ) ulUnusedParameter;
+
+ /* Note the comments at the top of this file regarding the use of queues in
+ this manner. */
+ if( xQueueReceiveFromISR( xCharsForTx, &ucByte, &lHigherPriorityTaskWoken ) == pdPASS )
+ {
+ SCIF2.SCFTDR.BYTE = ucByte;
+
+ /* Clear TDRE and TEND flag */
+ SCIF2.SCFSR.WORD &= ~0x0060;
+ }
+ else
+ {
+ /* No more characters. Disable the interrupt. */
+ SCIF2.SCSCR.BIT.TIE = 0;
+ }
+
+ /* If receiving from the queue has caused a task to unblock, and the
+ unblocked task has a priority equal to or higher than the currently running
+ task (the task this ISR interrupted), then lHigherPriorityTaskWoken will
+ have automatically been set to pdTRUE within the queue receive function.
+ portYIELD_FROM_ISR() will then ensure that this ISR returns directly to the
+ higher priority unblocked task. */
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/LEDs.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/LEDs.c
new file mode 100644
index 000000000..a697f2d1b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/LEDs.c
@@ -0,0 +1,145 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/*-----------------------------------------------------------
+ * Simple IO routines to control the LEDs.
+ *-----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo includes. */
+#include "partest.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+ /* Initialise P4_10 for LED1. */
+ PORT4.PMCn.BIT.PMCn10 = 0;
+ PORT4.Pn.BIT.Pn10 = 1;
+ PORT4.PMn.BIT.PMn10 = 0;
+ PORT4.PIPCn.BIT.PIPCn10 = 0;
+
+ /* Initialise P4_11 for LED2. */
+ PORT4.PMCn.BIT.PMCn11 = 0;
+ PORT4.Pn.BIT.Pn11 = 1;
+ PORT4.PMn.BIT.PMn11 = 0;
+ PORT4.PIPCn.BIT.PIPCn11 = 0;
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned long ulLED, signed long xValue )
+{
+ /* A high value turns the LED off. */
+ xValue = !xValue;
+
+ taskENTER_CRITICAL();
+ {
+ if( ulLED == 0 )
+ {
+ PORT4.Pn.BIT.Pn10 = xValue;
+ }
+
+ if( ulLED == 1 )
+ {
+ PORT4.Pn.BIT.Pn11 = xValue;
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned long ulLED )
+{
+ taskENTER_CRITICAL();
+ {
+ if( ulLED == 0 )
+ {
+ PORT4.Pn.BIT.Pn10 = !PORT4.Pn.BIT.Pn10;
+ }
+
+ if( ulLED == 1 )
+ {
+ PORT4.Pn.BIT.Pn11 = !PORT4.Pn.BIT.Pn11;
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/peripheral_init_basic.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/peripheral_init_basic.c
new file mode 100644
index 000000000..9f7dcda26
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/peripheral_init_basic.c
@@ -0,0 +1,207 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : peripheral_init_basic.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Initialize peripheral function sample
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "devdrv_common.h" /* Common Driver Header */
+#include "iodefine.h"
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_BASIC_SETUP"
+ #pragma arm section rodata = "CONST_BASIC_SETUP"
+ #pragma arm section rwdata = "DATA_BASIC_SETUP"
+ #pragma arm section zidata = "BSS_BASIC_SETUP"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+void Peripheral_BasicInit(void);
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void CPG_Init(void);
+static void CS0_PORTInit(void);
+
+
+/******************************************************************************
+* Function Name: PeripheralBasicInit
+* Description :
+* :
+* :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Peripheral_BasicInit(void)
+{
+ /* ==== Clock Pulse Generator (CPG) setting ====*/
+ CPG_Init();
+
+ /* ==== Port setting ==== */
+ CS0_PORTInit();
+
+ /* ==== Bus State Controller (BSC) setting ==== */
+ R_BSC_Init((uint8_t)(BSC_AREA_CS0 | BSC_AREA_CS1));
+}
+
+/******************************************************************************
+* Function Name: CPG_Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+static void CPG_Init(void)
+{
+ volatile uint32_t dummy_buf_32b;
+ volatile uint8_t dummy_buf_8b;
+
+ *(volatile uint32_t *)(0x3fffff80) = 0x00000001;
+ dummy_buf_32b = *(volatile uint32_t *)(0x3fffff80);
+
+ /* ==== CPG Settings ==== */
+ CPG.FRQCR.WORD = 0x1035u; /* PLL(x30), I:G:B:P1:P0 = 30:20:10:5:5/2 */
+ CPG.FRQCR2.WORD = 0x0001u; /* CKIO:Output at time usually, */
+ /* Output when bus right is opened, */
+ /* output at standby"L" */
+ /* Clockin = 13.33MHz, CKIO = 66.67MHz, */
+ /* I Clock = 400.00MHz, */
+ /* G Clock = 266.67MHz, */
+ /* B Clock = 133.33MHz, */
+ /* P1 Clock = 66.67MHz, */
+ /* P0 Clock = 33.33MHz */
+
+ /* ---- Writing to On-Chip Data-Retention RAM is enabled. ---- */
+ CPG.SYSCR3.BYTE = 0x0Fu;
+ dummy_buf_8b = CPG.SYSCR3.BYTE;
+}
+
+/******************************************************************************
+* Function Name: CS0_PORTInit
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+static void CS0_PORTInit(void)
+{
+ /* ==== BSC settings ==== */
+
+ /* ---- P9_1 : A25 ---- */
+ PORT9.PMCn.BIT.PMCn1 = 1;
+ PORT9.PFCAEn.BIT.PFCAEn1 = 0;
+ PORT9.PFCEn.BIT.PFCEn1 = 0;
+ PORT9.PFCn.BIT.PFCn1 = 0;
+ PORT9.PIPCn.BIT.PIPCn1 = 1;
+
+ /* ---- P9_0 : A24 ---- */
+ PORT9.PMCn.BIT.PMCn0 = 1;
+ PORT9.PFCAEn.BIT.PFCAEn0 = 0;
+ PORT9.PFCEn.BIT.PFCEn0 = 0;
+ PORT9.PFCn.BIT.PFCn0 = 0;
+ PORT9.PIPCn.BIT.PIPCn0 = 1;
+
+ /* ---- P8_15 : A23 ---- */
+ PORT8.PMCn.BIT.PMCn15 = 1;
+ PORT8.PFCAEn.BIT.PFCAEn15 = 0;
+ PORT8.PFCEn.BIT.PFCEn15 = 0;
+ PORT8.PFCn.BIT.PFCn15 = 0;
+ PORT8.PIPCn.BIT.PIPCn15 = 1;
+
+ /* ---- P8_14 : A22 ---- */
+ PORT8.PMCn.BIT.PMCn14 = 1;
+ PORT8.PFCAEn.BIT.PFCAEn14 = 0;
+ PORT8.PFCEn.BIT.PFCEn14 = 0;
+ PORT8.PFCn.BIT.PFCn14 = 0;
+ PORT8.PIPCn.BIT.PIPCn14 = 1;
+
+ /* ---- P8_13 : A21 ---- */
+ PORT8.PMCn.BIT.PMCn13 = 1;
+ PORT8.PFCAEn.BIT.PFCAEn13 = 0;
+ PORT8.PFCEn.BIT.PFCEn13 = 0;
+ PORT8.PFCn.BIT.PFCn13 = 0;
+ PORT8.PIPCn.BIT.PIPCn13 = 1;
+
+ /* ---- P7_6 : WE0# / DQMLL# ---- */
+ PORT7.PMCn.BIT.PMCn6 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn6 = 0;
+ PORT7.PFCEn.BIT.PFCEn6 = 0;
+ PORT7.PFCn.BIT.PFCn6 = 0;
+ PORT7.PIPCn.BIT.PIPCn6 = 1;
+
+ /* ---- P7_8 : RD ---- */
+ PORT7.PMCn.BIT.PMCn8 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn8 = 0;
+ PORT7.PFCEn.BIT.PFCEn8 = 0;
+ PORT7.PFCn.BIT.PFCn8 = 0;
+ PORT7.PIPCn.BIT.PIPCn8 = 1;
+
+ /* ---- P7_0 : CS0 ---- */
+ PORT7.PMCn.BIT.PMCn0 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn0 = 0;
+ PORT7.PFCEn.BIT.PFCEn0 = 0;
+ PORT7.PFCn.BIT.PFCn0 = 0;
+ PORT7.PIPCn.BIT.PIPCn0 = 1;
+
+ /* ---- P3_7 : CS1 ---- */
+ PORT3.PMCn.BIT.PMCn7 = 1;
+ PORT3.PFCAEn.BIT.PFCAEn7 = 1;
+ PORT3.PFCEn.BIT.PFCEn7 = 1;
+ PORT3.PFCn.BIT.PFCn7 = 0;
+ PORT3.PIPCn.BIT.PIPCn7 = 1;
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/port_init.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/port_init.c
new file mode 100644
index 000000000..7054efa0c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/port_init.c
@@ -0,0 +1,143 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : port_init.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Initialize peripheral function sample
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "devdrv_common.h" /* Common Driver Header */
+#include "port_init.h"
+#include "iodefine.h"
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_RESET"
+ #pragma arm section rodata = "CONST_RESET"
+ #pragma arm section rwdata = "DATA_RESET"
+ #pragma arm section zidata = "BSS_RESET"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: PORT_Init
+* Description :
+* :
+* :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void PORT_Init(void)
+{
+ /* ==== BSC settings ==== */
+
+ /* ---- P7_2 : RAS# ---- */
+ PORT7.PMCn.BIT.PMCn2 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn2 = 0;
+ PORT7.PFCEn.BIT.PFCEn2 = 0;
+ PORT7.PFCn.BIT.PFCn2 = 0;
+ PORT7.PIPCn.BIT.PIPCn2 = 1;
+
+ /* ---- P7_3 : CAS# ---- */
+ PORT7.PMCn.BIT.PMCn3 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn3 = 0;
+ PORT7.PFCEn.BIT.PFCEn3 = 0;
+ PORT7.PFCn.BIT.PFCn3 = 0;
+ PORT7.PIPCn.BIT.PIPCn3 = 1;
+
+ /* ---- P7_4 : CKE ---- */
+ PORT7.PMCn.BIT.PMCn4 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn4 = 0;
+ PORT7.PFCEn.BIT.PFCEn4 = 0;
+ PORT7.PFCn.BIT.PFCn4 = 0;
+ PORT7.PIPCn.BIT.PIPCn4 = 1;
+
+ /* ---- P7_5 : RD/WR# ---- */
+ PORT7.PMCn.BIT.PMCn5 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn5 = 0;
+ PORT7.PFCEn.BIT.PFCEn5 = 0;
+ PORT7.PFCn.BIT.PFCn5 = 0;
+ PORT7.PIPCn.BIT.PIPCn5 = 1;
+
+ /* ---- P7_7 : DQMLU# ---- */
+ PORT7.PMCn.BIT.PMCn7 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn7 = 0;
+ PORT7.PFCEn.BIT.PFCEn7 = 0;
+ PORT7.PFCn.BIT.PFCn7 = 0;
+ PORT7.PIPCn.BIT.PIPCn7 = 1;
+
+ /* ---- P5_8 : CS2 ---- */
+ PORT5.PMCn.BIT.PMCn8 = 1;
+ PORT5.PFCAEn.BIT.PFCAEn8 = 1;
+ PORT5.PFCEn.BIT.PFCEn8 = 0;
+ PORT5.PFCn.BIT.PFCn8 = 1;
+ PORT5.PIPCn.BIT.PIPCn8 = 1;
+
+ /* ---- P7_1 : CS3 ---- */
+ PORT7.PMCn.BIT.PMCn1 = 1;
+ PORT7.PFCAEn.BIT.PFCAEn1 = 0;
+ PORT7.PFCEn.BIT.PFCEn1 = 0;
+ PORT7.PFCn.BIT.PFCn1 = 0;
+ PORT7.PIPCn.BIT.PIPCn1 = 1;
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/siochar.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/siochar.c
new file mode 100644
index 000000000..4a6ffe549
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/siochar.c
@@ -0,0 +1,173 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : siochar.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Serial I/O character R/W (SCIF 2-ch process)
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_scif_uart.h" /* UART Driver header */
+#include "sio_char.h"
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: IoInitScif2
+* Description : This function initializes SCIF channel 2 as UART mode.
+* : The transmit and the receive of SCIF channel 2 are enabled.
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void IoInitScif2(void)
+{
+ /* P1=66.67MHz CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps */
+ R_SCIF_UART_Init(DEVDRV_CH_2, SCIF_UART_MODE_RW, 0, 17);
+
+ /* === PORT ==== */
+ /* ---- P3_0 : TxD2 ---- */
+ PORT3.PMCn.BIT.PMCn0 = 1;
+ PORT3.PFCAEn.BIT.PFCAEn0 = 1;
+ PORT3.PFCEn.BIT.PFCEn0 = 0;
+ PORT3.PFCn.BIT.PFCn0 = 1;
+ PORT3.PIPCn.BIT.PIPCn0 = 1;
+
+ /* ---- P3_2 : RxD2 ---- */
+ PORT3.PMCn.BIT.PMCn2 = 1;
+ PORT3.PFCAEn.BIT.PFCAEn2 = 0;
+ PORT3.PFCEn.BIT.PFCEn2 = 1;
+ PORT3.PFCn.BIT.PFCn2 = 1;
+ PORT3.PIPCn.BIT.PIPCn2 = 1;
+
+ /* ---- Serial control register (SCSCRi) setting ---- */
+ SCIF2.SCSCR.WORD = 0x0030;
+ /* SCIF2 transmitting and receiving operations are enabled */
+}
+
+/******************************************************************************
+* Function Name: IoGetchar
+* Description : One character is received from SCIF2, and it's data is returned.
+* : This function keeps waiting until it can obtain the receiving data.
+* Arguments : none
+* Return Value : Character to receive (Byte).
+******************************************************************************/
+char_t IoGetchar(void)
+{
+ char_t data;
+
+ /* Confirming receive error(ER,DR,BRK) */
+ if (SCIF2.SCFSR.WORD & 0x09C)
+ {
+ /* Detect receive error */
+ SCIF2.SCSCR.BIT.RE = 0; /* Disable reception */
+ SCIF2.SCFCR.BIT.RFRST = 1; /* Reset receiving FIFO */
+ SCIF2.SCFCR.BIT.RFRST = 0; /* Clearing FIFO reception reset */
+ SCIF2.SCFSR.WORD &= ~0x9C; /* Error bit clear */
+ SCIF2.SCSCR.BIT.RE = 1; /* Enable reception */
+ return 0;
+ }
+
+ /* Is there receive FIFO data? */
+ while (0 == SCIF2.SCFSR.BIT.RDF)
+ {
+ /* WAIT */
+ }
+
+ /* Read receive data */
+ data = SCIF2.SCFRDR.BYTE;
+ /* Clear RDF */
+ SCIF2.SCFSR.BIT.RDF = 0;
+
+ /* Is it overflowed? */
+ if (1 == SCIF2.SCLSR.BIT.ORER)
+ {
+ SCIF2.SCLSR.BIT.ORER = 0; /* ORER clear */
+ }
+
+ return data;
+}
+
+/******************************************************************************
+* Function Name: IoPutchar
+* Description : Character "buffer" is output to SCIF2.
+* : This function keeps waiting until it becomes the transmission
+* : enabled state.
+* Arguments : char_t buffer : character to output
+* Return Value : None
+******************************************************************************/
+void IoPutchar(char_t buffer)
+{
+ /* Check if it is possible to transmit (TDFE flag) */
+ while (0 == SCIF2.SCFSR.BIT.TDFE)
+ {
+ /* Wait */
+ }
+
+ /* Write the receiving data in TDR */
+ SCIF2.SCFTDR.BYTE = buffer;
+
+ /* Clear TDRE and TEND flag */
+ SCIF2.SCFSR.WORD &= ~0x0060;
+}
+
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/stb_init.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/stb_init.c
new file mode 100644
index 000000000..1d3b6fa6b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/stb_init.c
@@ -0,0 +1,119 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : stb_init.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Initialize peripheral function sample
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "devdrv_common.h" /* Common Driver Header */
+#include "stb_init.h"
+#include "iodefine.h"
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_RESET"
+ #pragma arm section rodata = "CONST_RESET"
+ #pragma arm section rwdata = "DATA_RESET"
+ #pragma arm section zidata = "BSS_RESET"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: StbInit
+* Description :
+* :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void STB_Init(void)
+{
+ volatile uint8_t dummy_buf;
+
+ /* ---- The clock of all modules is permitted. ---- */
+ CPG.STBCR2.BYTE = 0x6Au; /* Port level is keep in standby mode, [1], [1], [0], */
+ /* [1], [0], [1], CoreSight */
+ dummy_buf = CPG.STBCR2.BYTE; /* (Dummy read) */
+ CPG.STBCR3.BYTE = 0x00u; /* IEBus, IrDA, LIN0, LIN1, MTU2, RSCAN2, [0], PWM */
+ dummy_buf = CPG.STBCR3.BYTE; /* (Dummy read) */
+ CPG.STBCR4.BYTE = 0x00u; /* SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 */
+ dummy_buf = CPG.STBCR4.BYTE; /* (Dummy read) */
+ CPG.STBCR5.BYTE = 0x00u; /* SCIM0, SCIM1, SDG0, SDG1, SDG2, SDG3, OSTM0, OSTM1 */
+ dummy_buf = CPG.STBCR5.BYTE; /* (Dummy read) */
+ CPG.STBCR6.BYTE = 0x00u; /* A/D, CEU, DISCOM0, DISCOM1, DRC0, DRC1, JCU, RTClock */
+ dummy_buf = CPG.STBCR6.BYTE; /* (Dummy read) */
+ CPG.STBCR7.BYTE = 0x24u; /* DVDEC0, DVDEC1, [1], ETHER, FLCTL, [1], USB0, USB1 */
+ dummy_buf = CPG.STBCR7.BYTE; /* (Dummy read) */
+ CPG.STBCR8.BYTE = 0x05u; /* IMR-LS20, IMR-LS21, IMR-LSD, MMCIF, MOST50, [1], SCUX, [1] */
+ dummy_buf = CPG.STBCR8.BYTE; /* (Dummy read) */
+ CPG.STBCR9.BYTE = 0x00u; /* I2C0, I2C1, I2C2, I2C3, SPIBSC0, SPIBSC1, VDC50, VDC51 */
+ dummy_buf = CPG.STBCR9.BYTE; /* (Dummy read) */
+ CPG.STBCR10.BYTE = 0x00u; /* RSPI0, RSPI1, RSPI2, RSPI3, RSPI4, CD-ROMDEC, RSPDIF, RGPVG */
+ dummy_buf = CPG.STBCR10.BYTE; /* (Dummy read) */
+ CPG.STBCR11.BYTE = 0xC0u; /* [1], [1], SSIF0, SSIF1, SSIF2, SSIF3, SSIF4, SSIF5 */
+ dummy_buf = CPG.STBCR11.BYTE; /* (Dummy read) */
+ CPG.STBCR12.BYTE = 0xF0u; /* [1], [1], [1], [1], SDHI00, SDHI01, SDHI10, SDHI11 */
+ dummy_buf = CPG.STBCR12.BYTE; /* (Dummy read) */
+}
+
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/ttb_init.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/ttb_init.s
new file mode 100644
index 000000000..ebb88546d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/board_settings/ttb_init.s
@@ -0,0 +1,220 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : ttb_init.s
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.8
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program - TTB initialize
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+; ---- Parameter setting to level1 descriptor (bits 19:0) ----
+; setting for Strongly-ordered memory
+TTB_PARA_STRGLY EQU 2_00000000000000000000110111100010
+; setting for Outer and inner not cache normal memory
+TTB_PARA_NORMAL_NOT_CACHE EQU 2_00000000000000000001110111100010
+; setting for Outer and inner write back, write allocate normal memory (Cacheable)
+TTB_PARA_NORMAL_CACHE EQU 2_00000000000000000001110111101110
+; setting for Outer and inner write back, write allocate normal memory (Cacheable)
+;TTB_PARA_NORMAL_CACHE EQU 2_00000000000000000101110111100110
+
+; ---- Memory area size (MB) ----
+M_SIZE_NOR EQU 128 ; [Area00] CS0, CS1 area (for NOR flash)
+M_SIZE_SDRAM EQU 128 ; [Area01] CS2, CS3 area (for SDRAM)
+M_SIZE_CS45 EQU 128 ; [Area02] CS4, CS5 area
+M_SIZE_SPI EQU 128 ; [Area03] SPI, SP2 area (for Serial flash)
+M_SIZE_RAM EQU 10 ; [Area04] Internal RAM
+M_SIZE_IO_1 EQU 502 ; [Area05] I/O area 1
+M_SIZE_NOR_M EQU 128 ; [Area06] CS0, CS1 area (for NOR flash) (mirror)
+M_SIZE_SDRAM_M EQU 128 ; [Area07] CS2, CS3 area (for SDRAM) (mirror)
+M_SIZE_CS45_M EQU 128 ; [Area08] CS4, CS5 area (mirror)
+M_SIZE_SPI_M EQU 128 ; [Area09] SPI, SP2 area (for Serial flash) (mirror)
+M_SIZE_RAM_M EQU 10 ; [Area10] Internal RAM (mirror)
+M_SIZE_IO_2 EQU 2550 ; [Area11] I/O area 2
+
+;==================================================================
+; This code provides basic global enable for Cortex-A9 cache.
+; It also enables branch prediction
+; This code must be run from a privileged mode
+;==================================================================
+ AREA INIT_TTB, CODE, READONLY
+
+ IMPORT ||Image$$TTB$$ZI$$Base|| ;;; From scatter file
+
+ EXPORT init_TTB
+
+init_TTB FUNCTION
+
+;===================================================================
+; Cortex-A9 MMU Configuration
+; Set translation table base
+;===================================================================
+ ;;; Cortex-A9 supports two translation tables
+ ;;; Configure translation table base (TTB) control register cp15,c2
+ ;;; to a value of all zeros, indicates we are using TTB register 0.
+ MOV r0,#0x0
+ MCR p15, 0, r0, c2, c0, 2 ;;; TTBCR
+
+ ;;; write the address of our page table base to TTB register 0
+ LDR r0,=||Image$$TTB$$ZI$$Base||
+ MOV r1, #0x08 ;;; RGN=b01 (outer cacheable write-back cached, write allocate)
+ ;;; S=0 (translation table walk to non-shared memory)
+ ORR r1,r1,#0x40 ;;; IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate)
+ ORR r0,r0,r1
+ MCR p15, 0, r0, c2, c0, 0 ;;; TTBR0
+
+;===================================================================
+; PAGE TABLE generation
+; Generate the page tables
+; Build a flat translation table for the whole address space.
+; ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx
+; 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0
+; |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0|
+;
+; Bits[31:20] - Top 12 bits of VA is pointer into table
+; nG[17]=0 - Non global, enables matching against ASID in the TLB when set.
+; S[16]=0 - Indicates normal memory is shared when set.
+; AP2[15]=0
+; AP[11:10]=11 - Configure for full read/write access in all modes
+; TEX[14:12]=000
+; CB[3:2]= 00 - Set attributes to Strongly-ordered memory.
+; (except for the descriptor where code segment is based, see below)
+; IMPP[9]=0 - Ignored
+; Domain[5:8]=1111 - Set all pages to use domain 15
+; XN[4]=0 - Execute never disabled
+; Bits[1:0]=10 - Indicate entry is a 1MB section
+;===================================================================
+ LDR r0,=||Image$$TTB$$ZI$$Base||
+ LDR r1,=0xFFF
+ LDR r2,=11
+ LDR r3,=0
+ LDR r4,=0
+ LDR r5,=0
+
+ ;;; r0 contains the address of the translation table base
+ ;;; r1 is loop counter
+ ;;; r2 is target area counter (Initialize value = Last area No.)
+ ;;; r3 is loop counter by area
+
+ ;;; use loop counter to create 4096 individual table entries.
+ ;;; this writes from address 'Image$$TTB$$ZI$$Base' +
+ ;;; offset 0x3FFC down to offset 0x0 in word steps (4 bytes)
+
+set_mem_accsess
+ CMP r2, #11
+ BEQ setting_area11
+ CMP r2, #10
+ BEQ setting_area10
+ CMP r2, #9
+ BEQ setting_area9
+ CMP r2, #8
+ BEQ setting_area8
+ CMP r2, #7
+ BEQ setting_area7
+ CMP r2, #6
+ BEQ setting_area6
+ CMP r2, #5
+ BEQ setting_area5
+ CMP r2, #4
+ BEQ setting_area4
+ CMP r2, #3
+ BEQ setting_area3
+ CMP r2, #2
+ BEQ setting_area2
+ CMP r2, #1
+ BEQ setting_area1
+ CMP r2, #0
+ BEQ setting_area0
+setting_area11 ;;; [area11] I/O area 2
+ LDR r3, =M_SIZE_IO_2
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
+ BAL init_counter
+setting_area10 ;;; [area10] Internal RAM (mirror)
+ LDR r3, =M_SIZE_RAM_M
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
+ BAL init_counter
+setting_area9 ;;; [area09] SPI, SP2 area (for Serial flash) (mirror)
+ LDR r3, =M_SIZE_SPI_M
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
+ BAL init_counter
+setting_area8 ;;; [area08] CS4, CS5 area (mirror)
+ LDR r3, =M_SIZE_CS45_M
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
+ BAL init_counter
+setting_area7 ;;; [area07] CS2, CS3 area (for SDRAM) (mirror)
+ LDR r3, =M_SIZE_SDRAM_M
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
+ BAL init_counter
+setting_area6 ;;; [area06] CS0, CS1 area (for NOR flash) (mirror)
+ LDR r3, =M_SIZE_NOR_M
+ LDR r4, =TTB_PARA_NORMAL_NOT_CACHE ;;; Normal (not cache)
+ BAL init_counter
+setting_area5 ;;; [area05] I/O area 1
+ LDR r3, =M_SIZE_IO_1
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
+ BAL init_counter
+setting_area4 ;;; [area04] Internal RAM
+ LDR r3, =M_SIZE_RAM
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
+ BAL init_counter
+setting_area3 ;;; [area03] SPI, SP2 area (for Serial flash)
+ LDR r3, =M_SIZE_SPI
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
+ BAL init_counter
+setting_area2 ;;; [area02] CS4, CS5 area
+ LDR r3, =M_SIZE_CS45
+ LDR r4, =TTB_PARA_STRGLY ;;; Strongly-ordered
+ BAL init_counter
+setting_area1 ;;; [area01] CS2, CS3 area (for SDRAM)
+ LDR r3, =M_SIZE_SDRAM
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
+ BAL init_counter
+setting_area0 ;;; [area00] CS0, CS1 area (for NOR flash)
+ LDR r3, =M_SIZE_NOR
+ LDR r4, =TTB_PARA_NORMAL_CACHE ;;; Normal (Cacheable)
+ BAL init_counter
+init_counter
+ SUBS r3, r3, #1 ;;; memory size -> loop counter value
+write_ttb
+ ORR r5, r4, r1, LSL#20 ;;; R5 now contains full level1 descriptor to write
+ STR r5, [r0, r1, LSL#2] ;;; Str table entry at TTB base + loopcount*4
+ SUB r1, r1, #1 ;;; Decrement loop counter
+ SUBS r3, r3, #1 ;;; Decrement loop counter by area
+ BPL write_ttb
+ SUBS r2, r2, #1 ;;; target area counter
+ BPL set_mem_accsess ;;; To the next area
+
+ BX lr
+
+ ENDFUNC
+
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/l1_cache_init.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/l1_cache_init.s
new file mode 100644
index 000000000..4579fdcb8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/l1_cache_init.s
@@ -0,0 +1,96 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : l1_cache_init.s
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.8
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program vecotr.s
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+;==================================================================
+; This code provides basic global enable for Cortex-A9 cache.
+; It also enables branch prediction
+; This code must be run from a privileged mode
+;==================================================================
+ AREA INITCA9CACHE, CODE, READONLY
+ EXPORT L1CacheInit
+
+L1CacheInit FUNCTION
+
+;==================================================================
+; Enable caches
+; Caches are controlled by the System Control Register:
+;==================================================================
+ ;;; I-cache is controlled by bit 12
+ ;;; D-cache is controlled by bit 2
+
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 register 1
+ ORR r0, r0, #(0x1 << 12) ;;; Enable I Cache
+ ORR r0, r0, #(0x1 << 2) ;;; Enable D Cache
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write CP15 register 1
+
+;==================================================================
+; Enable Program Flow Prediction
+;
+; Branch prediction is controlled by the System Control Register:
+; Set Bit 11 to enable branch prediction and return
+;==================================================================
+ ;;; Turning on branch prediction requires a general enable
+ ;;; CP15, c1. Control Register
+
+ ;;; Bit 11 [Z] bit Program flow prediction:
+ ;;; 0 = Program flow prediction disabled
+ ;;; 1 = Program flow prediction enabled.
+
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read System Control Register
+ ORR r0, r0, #(0x1 << 11)
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write System Control Register
+
+;==================================================================
+; Enable D-side prefetch
+;==================================================================
+ ;;; Bit 2 [DP] Dside prefetch:
+ ;;; 0 = Dside prefetch disabled
+ ;;; 1 = Dside prefetch enabled.
+
+ MRC p15, 0, r0, c1, c0, 1 ;;; Read Auxiliary Control Register
+ ORR r0, r0, #(0x1 << 2) ;;; Enable Dside prefetch
+ MCR p15, 0, r0, c1, c0, 1 ;;; Write Auxiliary Control Register
+
+ BX lr
+
+ ENDFUNC
+
+
+
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/resetprg.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/resetprg.c
new file mode 100644
index 000000000..7ec022f20
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/resetprg.c
@@ -0,0 +1,121 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : resetprg.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Sub Main
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "devdrv_common.h" /* Common Driver Header */
+#include "devdrv_intc.h" /* INTC Driver Header */
+#include "resetprg.h"
+#include "sio_char.h"
+#include "stb_init.h"
+#include "port_init.h"
+
+#pragma arm section code = "CODE_RESET"
+#pragma arm section rodata = "CONST_RESET"
+#pragma arm section rwdata = "DATA_RESET"
+#pragma arm section zidata = "BSS_RESET"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+extern void VbarInit(void);
+extern void L1CacheInit(void);
+extern int32_t $Super$$main(void);
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: $Sub$$main
+* Description :
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void $Sub$$main(void)
+{
+ STB_Init();
+
+ /* ==== PORT setting ==== */
+ PORT_Init();
+
+ /* ==== BSC setting ==== */
+ R_BSC_Init((uint8_t)(BSC_AREA_CS2 | BSC_AREA_CS3));
+
+ /* ==== INTC setting ==== */
+ R_INTC_Init();
+
+ /* ==== Cache setting ==== */
+// io_init_cache();
+
+ /* ==== Writeback Cache ==== */
+// io_cache_writeback();
+
+ L1CacheInit();
+
+ /* ==== Vector base address setting ==== */
+ VbarInit();
+
+ __enable_irq();
+ __enable_fiq();
+
+ /* ==== Function call of main function ==== */
+ $Super$$main();
+}
+
+
+/* END of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/vbar_init.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/vbar_init.s
new file mode 100644
index 000000000..fe7e5e168
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/vbar_init.s
@@ -0,0 +1,67 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : vbar_init.s
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.8
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+;==================================================================
+; This code provides basic global enable for Cortex-A9 cache.
+; It also enables branch prediction
+; This code must be run from a privileged mode
+;==================================================================
+ AREA INIT_VBAR, CODE, READONLY
+
+ IMPORT ||Image$$VECTOR_MIRROR_TABLE$$Base||
+; IMPORT ||Image$$VECTOR_TABLE$$Base||
+
+ EXPORT VbarInit
+
+VbarInit FUNCTION
+
+;===================================================================
+; Set Vector Base Address Register (VBAR) to point to this application's vector table
+;===================================================================
+ LDR r0, =||Image$$VECTOR_MIRROR_TABLE$$Base||
+; LDR r0, =||Image$$VECTOR_TABLE$$Base||
+ MCR p15, 0, r0, c12, c0, 0
+
+ BX lr
+
+ ENDFUNC
+
+
+
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/common_driver/bsc.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/common_driver/bsc.c
new file mode 100644
index 000000000..a5306d5eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/common_driver/bsc.c
@@ -0,0 +1,110 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc.c
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - BSC initialize
+*******************************************************************************/
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_common.h" /* Common Driver Header */
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_RESET"
+ #pragma arm section rodata = "CONST_RESET"
+ #pragma arm section rwdata = "DATA_RESET"
+ #pragma arm section zidata = "BSS_RESET"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_BSC_Init
+* Description :
+* Arguments : uint8 area
+* : B'xxxxxxxx
+* : |||||||+--- [0] CS0
+* : ||||||+---- [1] CS1
+* : |||||+----- [2] CS2
+* : ||||+------ [3] CS3
+* : |||+------- [4] CS4
+* : ||+-------- [5] CS5
+* : ++--------- [6-7] n/a
+* Return Value : none
+******************************************************************************/
+void R_BSC_Init(uint8_t area)
+{
+ /* ==== BSC initialize ==== */
+ if ((area & BSC_AREA_CS0) != 0) /* CS0 */
+ {
+ Userdef_BSC_CS0Init();
+ }
+ if ((area & BSC_AREA_CS1) != 0) /* CS1 */
+ {
+ Userdef_BSC_CS1Init();
+ }
+ if ((area & BSC_AREA_CS2) != 0) /* CS2 */
+ {
+ Userdef_BSC_CS2Init();
+ }
+ if ((area & BSC_AREA_CS3) != 0) /* CS3 */
+ {
+ Userdef_BSC_CS3Init();
+ }
+ if ((area & BSC_AREA_CS4) != 0) /* CS4 */
+ {
+ Userdef_BSC_CS4Init();
+ }
+ if ((area & BSC_AREA_CS5) != 0) /* CS5 */
+ {
+ Userdef_BSC_CS5Init();
+ }
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/userdef/bsc_userdef.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/userdef/bsc_userdef.c
new file mode 100644
index 000000000..429d72560
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/common/userdef/bsc_userdef.c
@@ -0,0 +1,240 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_userdef.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Common driver (User define function)
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_common.h" /* Common Driver Header */
+#include "iodefine.h"
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_RESET"
+ #pragma arm section rodata = "CONST_RESET"
+ #pragma arm section rwdata = "DATA_RESET"
+ #pragma arm section zidata = "BSS_RESET"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* The address when writing in a SDRAM mode register */
+#define SDRAM_MODE_CS2 (*(volatile uint16_t *)(0x3FFFD040))
+#define SDRAM_MODE_CS3 (*(volatile uint16_t *)(0x3FFFE040))
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS0Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_BSC_CS0Init(void)
+{
+ /* ---- CS0BCR settings ---- */
+ BSC.CS0BCR.LONG = 0x10000C00ul;
+ /* Idle Cycles between Write-read Cycles */
+ /* and Write-write Cycles : 1 idle cycle */
+ /* Data Bus Size: 16-bit */
+
+ /* ---- CS0WCR settings ---- */
+ BSC.CS0WCR.NORMAL.LONG = 0x00000B40ul;
+ /* Number of Delay Cycles from Address, */
+ /* CS0# Assertion to RD#,WEn Assertion */
+ /* : 1.5 cycles */
+ /* Number of Access Wait Cycles: 6 cycles */
+ /* Delay Cycles from RD,WEn# negation to */
+ /* Address,CSn# negation: 0.5 cycles */
+}
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS1Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_BSC_CS1Init(void)
+{
+ /* ---- CS1BCR settings ---- */
+ BSC.CS1BCR.LONG = 0x10000C00ul;
+ /* Idle Cycles between Write-read Cycles */
+ /* and Write-write Cycles : 1 idle cycle */
+ /* Data Bus Size: 16-bit */
+
+ /* ---- CS1WCR settings ---- */
+ BSC.CS1WCR.LONG = 0x00000B40ul;
+ /* Number of Delay Cycles from Address, */
+ /* CS0# Assertion to RD#,WEn Assertion */
+ /* : 1.5 cycles */
+ /* Number of Access Wait Cycles: 6 cycles */
+ /* Delay Cycles from RD,WEn# negation to */
+ /* Address,CSn# negation: 0.5 cycles */
+}
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS2Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_BSC_CS2Init(void)
+{
+ /* ==== CS2BCR settings ==== */
+ BSC.CS2BCR.LONG = 0x00004C00ul;
+ /* Idle Cycles between Write-read Cycles */
+ /* and Write-write Cycles : 0 idle cycles */
+ /* Memory type :SDRAM */
+ /* Data Bus Size : 16-bit */
+
+ /* ==== CS2WCR settings ==== */
+ BSC.CS2WCR.SDRAM.LONG = 0x00000480ul;
+ /* CAS latency for Area 2 : 2 cycles */
+
+
+ /* ==== Written in SDRAM Mode Register ==== */
+ SDRAM_MODE_CS2 = 0;
+ /* The writing data is arbitrary */
+ /* SDRAM mode register setting CS2 space */
+ /* Burst read (burst length 1)./Burst write */
+}
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS3Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_BSC_CS3Init(void)
+{
+ volatile int32_t cnt;
+
+ cnt = 150;
+ while (cnt-- > 0)
+ {
+ /* wait */
+ }
+
+ /* ==== CS3BCR settings ==== */
+ BSC.CS3BCR.LONG = 0x00004C00ul;
+ /* Idle Cycles between Write-read Cycles */
+ /* and Write-write Cycles : 0 idle cycles */
+ /* Memory type :SDRAM */
+ /* Data Bus Size : 16-bit */
+
+ /* ==== CS3WCR settings ==== */
+ BSC.CS3WCR.SDRAM.LONG = 0x00002492ul;
+ /* Precharge completion wait cycles: 1 cycle */
+ /* Wait cycles between ACTV command */
+ /* and READ(A)/WRITE(A) command : 1 cycles */
+ /* CAS latency for Area 3 : 2 cycles */
+ /* Auto-precharge startup wait cycles : 2 cycles */
+ /* Idle cycles from REF command/self-refresh */
+ /* Release to ACTV/REF/MRS command : 5 cycles */
+
+ /* ==== SDCR settings ==== */
+ BSC.SDCR.LONG = 0x00120812ul;
+ /* Row address for Area 2 : 13-bit */
+ /* Column Address for Area 2 : 10-bit */
+ /* Refresh Control :Refresh */
+ /* RMODE :Auto-refresh is performed */
+ /* BACTV :Auto-precharge mode */
+ /* Row address for Area 3 : 13-bit */
+ /* Column Address for Area 3 : 10-bit */
+
+ /* ==== RTCOR settings ==== */
+ BSC.RTCOR.LONG = 0xA55A0020ul;
+ /* 7.813usec /240nsec */
+ /* = 32(0x20)cycles per refresh */
+
+ /* ==== RTCSR settings ==== */
+ BSC.RTCSR.LONG = 0xA55A0010ul;
+ /* Initialization sequence start */
+ /* Clock select B-phy/16 */
+ /* Refresh count :Once */
+
+ /* ==== Written in SDRAM Mode Register ==== */
+ SDRAM_MODE_CS3 = 0;
+ /* The writing data is arbitrary */
+ /* SDRAM mode register setting CS3 space */
+ /* Burst read (burst length 1)./Burst write */
+}
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS4Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_BSC_CS4Init(void)
+{
+}
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS5Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_BSC_CS5Init(void)
+{
+}
+
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc.c
new file mode 100644
index 000000000..7101a622d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc.c
@@ -0,0 +1,298 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - Interrupt process
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_intc.h" /* INTC Driver Header */
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INTC_ICDISR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDISR */
+#define INTC_ICDICFR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 16) + 1) /* ICDICFR */
+#define INTC_ICDIPR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 4) + 1) /* ICDIPR */
+#define INTC_ICDIPTR_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 4) + 1) /* ICDIPTR */
+#define INTC_ICDISER_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDISER */
+#define INTC_ICDICER_REG_TOTAL (((uint16_t)INTC_ID_TOTAL / 32) + 1) /* ICDICER */
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+/* ==== Global variable ==== */
+static uint32_t intc_icdicfrn_table[] =
+{
+ 0xAAAAAAAA, /* ICDICFR0 : 15 - 0 */
+ 0x00000055, /* ICDICFR1 : 19 - 16 */
+ 0xFFFD5555, /* ICDICFR2 : 47 - 32 */
+ 0x555FFFFF, /* ICDICFR3 : 63 - 48 */
+ 0x55555555, /* ICDICFR4 : 79 - 64 */
+ 0x55555555, /* ICDICFR5 : 95 - 80 */
+ 0x55555555, /* ICDICFR6 : 111 - 96 */
+ 0x55555555, /* ICDICFR7 : 127 - 112 */
+ 0x5555F555, /* ICDICFR8 : 143 - 128 */
+ 0x55555555, /* ICDICFR9 : 159 - 144 */
+ 0x55555555, /* ICDICFR10 : 175 - 160 */
+ 0xF5555555, /* ICDICFR11 : 191 - 176 */
+ 0xF555F555, /* ICDICFR12 : 207 - 192 */
+ 0x5555F555, /* ICDICFR13 : 223 - 208 */
+ 0x55555555, /* ICDICFR14 : 239 - 224 */
+ 0x55555555, /* ICDICFR15 : 255 - 240 */
+ 0x55555555, /* ICDICFR16 : 271 - 256 */
+ 0xFD555555, /* ICDICFR17 : 287 - 272 */
+ 0x55555557, /* ICDICFR18 : 303 - 288 */
+ 0x55555555, /* ICDICFR19 : 319 - 304 */
+ 0x55555555, /* ICDICFR20 : 335 - 320 */
+ 0x5F555555, /* ICDICFR21 : 351 - 336 */
+ 0xFD55555F, /* ICDICFR22 : 367 - 352 */
+ 0x55555557, /* ICDICFR23 : 383 - 368 */
+ 0x55555555, /* ICDICFR24 : 399 - 384 */
+ 0x55555555, /* ICDICFR25 : 415 - 400 */
+ 0x55555555, /* ICDICFR26 : 431 - 416 */
+ 0x55555555, /* ICDICFR27 : 447 - 432 */
+ 0x55555555, /* ICDICFR28 : 463 - 448 */
+ 0x55555555, /* ICDICFR29 : 479 - 464 */
+ 0x55555555, /* ICDICFR30 : 495 - 480 */
+ 0x55555555, /* ICDICFR31 : 511 - 496 */
+ 0x55555555, /* ICDICFR32 : 527 - 512 */
+ 0x55555555, /* ICDICFR33 : 543 - 528 */
+ 0x55555555, /* ICDICFR34 : 559 - 544 */
+ 0x55555555, /* ICDICFR35 : 575 - 560 */
+ 0x00155555 /* ICDICFR36 : 586 - 576 */
+};
+
+
+/******************************************************************************
+* Function Name: R_INTC_RegistIntFunc
+* Description :
+* Arguments : uint16_t int_id
+* : void (* func)(uint32_t)
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense))
+{
+ if (int_id >= INTC_ID_TOTAL)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ Userdef_INTC_RegistIntFunc(int_id, func);
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: R_INTC_Init
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void R_INTC_Init(void)
+{
+ uint16_t offset;
+ volatile uint32_t * addr;
+
+ for (offset = 0; offset < INTC_ICDICFR_REG_TOTAL; offset++)
+ {
+ INTC.ICDICFR.LONG[offset] = intc_icdicfrn_table[offset];
+ }
+
+ addr = (volatile uint32_t *)&INTC.ICDIPR0.LONG;
+ for (offset = 0; offset < INTC_ICDIPR_REG_TOTAL; offset++)
+ {
+ *(addr + offset) = 0xF8F8F8F8;
+ }
+
+ addr = (volatile uint32_t *)&INTC.ICDIPTR0.LONG;
+ for (offset = 8; offset < INTC_ICDIPTR_REG_TOTAL; offset++)
+ {
+ *(addr + offset) = 0x01010101;
+ }
+
+ for (offset = 0; offset < INTC_ICDICER_REG_TOTAL; offset++)
+ {
+ INTC.ICDICER.LONG[offset] = 0xFFFFFFFF;
+ }
+
+ R_INTC_SetMaskLevel(31);
+
+ INTC.ICCBPR.BIT.Binarypoint = 0;
+
+ INTC.ICCICR.LONG = 3;
+
+ /* Distributor Control Register */
+ INTC.ICDDCR.BIT.Enable = 1;
+}
+
+/******************************************************************************
+* Function Name: R_INTC_Enable
+* Description :
+* Arguments : uint16_t int_id
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_INTC_Enable(uint16_t int_id)
+{
+ uint32_t reg_value;
+ uint32_t mask;
+
+ if (int_id >= INTC_ID_TOTAL)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ mask = 1;
+ mask = mask << (int_id % 32);
+
+ reg_value = INTC.ICDISER.LONG[int_id / 32];
+ reg_value |= mask;
+ INTC.ICDISER.LONG[int_id / 32] = reg_value;
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: R_INTC_Disable
+* Description :
+* Arguments : uint16_t int_id
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_INTC_Disable(uint16_t int_id)
+{
+ uint32_t reg_value;
+ uint32_t mask;
+
+ if (int_id >= INTC_ID_TOTAL)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ mask = 1;
+ mask = mask << (int_id % 32);
+
+ reg_value = INTC.ICDICER.LONG[int_id / 32];
+ reg_value |= mask;
+ INTC.ICDICER.LONG[int_id / 32] = reg_value;
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: R_INTC_SetPriority
+* Description :
+* Arguments : uint16_t int_id
+* : uint8_t priority
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_INTC_SetPriority(uint16_t int_id, uint8_t priority)
+{
+ uint32_t icdipr;
+ uint32_t mask;
+ volatile uint32_t * addr;
+
+ if ((int_id >= INTC_ID_TOTAL) || priority >= 32)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ priority = priority << 3;
+
+ addr = (volatile uint32_t *)&INTC.ICDIPR0.LONG;
+
+ icdipr = *(addr + (int_id / 4));
+
+ mask = (uint32_t)0x000000FF;
+ mask = mask << ((int_id % 4) * 8);
+ icdipr &= ~mask;
+ mask = (uint32_t)priority;
+ mask = mask << ((int_id % 4) * 8);
+ icdipr |= mask;
+
+ *(addr + (int_id / 4)) = icdipr;
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: R_INTC_SetMaskLevel
+* Description :
+* Arguments : uint8_t mask_level
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_INTC_SetMaskLevel(uint8_t mask_level)
+{
+ if (mask_level >= 32)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ mask_level = mask_level << 3;
+ INTC.ICCPMR.BIT.Priority = mask_level;
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: R_INTC_GetMaskLevel
+* Description :
+* Arguments : uint8_t * mask_level
+* Return Value : none
+******************************************************************************/
+void R_INTC_GetMaskLevel(uint8_t * mask_level)
+{
+ *mask_level = INTC.ICCPMR.BIT.Priority;
+ *mask_level = *mask_level >> 3;
+}
+
+/* END of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc_handler.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc_handler.c
new file mode 100644
index 000000000..cc7d5763f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/intc_driver/intc_handler.c
@@ -0,0 +1,88 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_handler.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - Handler process
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "FreeRTOS.h"
+#include
+#include "r_typedefs.h"
+#include "devdrv_intc.h" /* INTC Driver Header */
+#include "iodefine.h"
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_HANDLER"
+ #pragma arm section rodata = "CONST_HANDLER"
+ #pragma arm section rwdata = "DATA_HANDLER"
+ #pragma arm section zidata = "BSS_HANDLER"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* ==== Prototype declaration ==== */
+__irq void FiqHandler_Interrupt(void);
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: FiqHandler_Interrupt
+* Description :
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+__irq void FiqHandler_Interrupt(void)
+{
+ Userdef_FIQ_HandlerExe();
+}
+
+
+/* END of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/userdef/intc_userdef.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/userdef/intc_userdef.c
new file mode 100644
index 000000000..a98387974
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/intc/userdef/intc_userdef.c
@@ -0,0 +1,742 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_userdef.c
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - Interrupt func table
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "devdrv_intc.h" /* INTC Driver Header */
+#include "iodefine.h"
+
+/* Do not include the following pragmas when compiling with IAR. */
+#ifndef __ICCARM__
+ #pragma arm section code = "CODE_HANDLER_JMPTBL"
+ #pragma arm section rodata = "CONST_HANDLER_JMPTBL"
+ #pragma arm section rwdata = "DATA_HANDLER_JMPTBL"
+ #pragma arm section zidata = "BSS_HANDLER_JMPTBL"
+#else
+ /* IAR requires intrinsics.h for the __enable_irq() function. */
+ #include
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+/* ==== Prototype function ==== */
+static void Userdef_INTC_Dummy_Interrupt(uint32_t int_sense);
+
+/* ==== Global variable ==== */
+static void (* intc_func_table[INTC_ID_TOTAL])(uint32_t int_sense) =
+{
+ Userdef_INTC_Dummy_Interrupt, /* 0 : SW0 */
+ Userdef_INTC_Dummy_Interrupt, /* 1 : SW1 */
+ Userdef_INTC_Dummy_Interrupt, /* 2 : SW2 */
+ Userdef_INTC_Dummy_Interrupt, /* 3 : SW3 */
+ Userdef_INTC_Dummy_Interrupt, /* 4 : SW4 */
+ Userdef_INTC_Dummy_Interrupt, /* 5 : SW5 */
+ Userdef_INTC_Dummy_Interrupt, /* 6 : SW6 */
+ Userdef_INTC_Dummy_Interrupt, /* 7 : SW7 */
+ Userdef_INTC_Dummy_Interrupt, /* 8 : SW8 */
+ Userdef_INTC_Dummy_Interrupt, /* 9 : SW9 */
+ Userdef_INTC_Dummy_Interrupt, /* 10 : SW10 */
+ Userdef_INTC_Dummy_Interrupt, /* 11 : SW11 */
+ Userdef_INTC_Dummy_Interrupt, /* 12 : SW12 */
+ Userdef_INTC_Dummy_Interrupt, /* 13 : SW13 */
+ Userdef_INTC_Dummy_Interrupt, /* 14 : SW14 */
+ Userdef_INTC_Dummy_Interrupt, /* 15 : SW15 */
+ Userdef_INTC_Dummy_Interrupt, /* 16 : PMUIRQ0 */
+ Userdef_INTC_Dummy_Interrupt, /* 17 : COMMRX0 */
+ Userdef_INTC_Dummy_Interrupt, /* 18 : COMMTX0 */
+ Userdef_INTC_Dummy_Interrupt, /* 19 : CTIIRQ0 */
+ Userdef_INTC_Dummy_Interrupt, /* 20 : */
+ Userdef_INTC_Dummy_Interrupt, /* 21 : */
+ Userdef_INTC_Dummy_Interrupt, /* 22 : */
+ Userdef_INTC_Dummy_Interrupt, /* 23 : */
+ Userdef_INTC_Dummy_Interrupt, /* 24 : */
+ Userdef_INTC_Dummy_Interrupt, /* 25 : */
+ Userdef_INTC_Dummy_Interrupt, /* 26 : */
+ Userdef_INTC_Dummy_Interrupt, /* 27 : */
+ Userdef_INTC_Dummy_Interrupt, /* 28 : */
+ Userdef_INTC_Dummy_Interrupt, /* 29 : */
+ Userdef_INTC_Dummy_Interrupt, /* 30 : */
+ Userdef_INTC_Dummy_Interrupt, /* 31 : */
+ Userdef_INTC_Dummy_Interrupt, /* 32 : IRQ0 */
+ Userdef_INTC_Dummy_Interrupt, /* 33 : IRQ1 */
+ Userdef_INTC_Dummy_Interrupt, /* 34 : IRQ2 */
+ Userdef_INTC_Dummy_Interrupt, /* 35 : IRQ3 */
+ Userdef_INTC_Dummy_Interrupt, /* 36 : IRQ4 */
+ Userdef_INTC_Dummy_Interrupt, /* 37 : IRQ5 */
+ Userdef_INTC_Dummy_Interrupt, /* 38 : IRQ6 */
+ Userdef_INTC_Dummy_Interrupt, /* 39 : IRQ7 */
+ Userdef_INTC_Dummy_Interrupt, /* 40 : PL310ERR */
+ Userdef_INTC_Dummy_Interrupt, /* 41 : DMAINT0 */
+ Userdef_INTC_Dummy_Interrupt, /* 42 : DMAINT1 */
+ Userdef_INTC_Dummy_Interrupt, /* 43 : DMAINT2 */
+ Userdef_INTC_Dummy_Interrupt, /* 44 : DMAINT3 */
+ Userdef_INTC_Dummy_Interrupt, /* 45 : DMAINT4 */
+ Userdef_INTC_Dummy_Interrupt, /* 46 : DMAINT5 */
+ Userdef_INTC_Dummy_Interrupt, /* 47 : DMAINT6 */
+ Userdef_INTC_Dummy_Interrupt, /* 48 : DMAINT7 */
+ Userdef_INTC_Dummy_Interrupt, /* 49 : DMAINT8 */
+ Userdef_INTC_Dummy_Interrupt, /* 50 : DMAINT9 */
+ Userdef_INTC_Dummy_Interrupt, /* 51 : DMAINT10 */
+ Userdef_INTC_Dummy_Interrupt, /* 52 : DMAINT11 */
+ Userdef_INTC_Dummy_Interrupt, /* 53 : DMAINT12 */
+ Userdef_INTC_Dummy_Interrupt, /* 54 : DMAINT13 */
+ Userdef_INTC_Dummy_Interrupt, /* 55 : DMAINT14 */
+ Userdef_INTC_Dummy_Interrupt, /* 56 : DMAINT15 */
+ Userdef_INTC_Dummy_Interrupt, /* 57 : DMAERR */
+ Userdef_INTC_Dummy_Interrupt, /* 58 : */
+ Userdef_INTC_Dummy_Interrupt, /* 59 : */
+ Userdef_INTC_Dummy_Interrupt, /* 60 : */
+ Userdef_INTC_Dummy_Interrupt, /* 61 : */
+ Userdef_INTC_Dummy_Interrupt, /* 62 : */
+ Userdef_INTC_Dummy_Interrupt, /* 63 : */
+ Userdef_INTC_Dummy_Interrupt, /* 64 : */
+ Userdef_INTC_Dummy_Interrupt, /* 65 : */
+ Userdef_INTC_Dummy_Interrupt, /* 66 : */
+ Userdef_INTC_Dummy_Interrupt, /* 67 : */
+ Userdef_INTC_Dummy_Interrupt, /* 68 : */
+ Userdef_INTC_Dummy_Interrupt, /* 69 : */
+ Userdef_INTC_Dummy_Interrupt, /* 70 : */
+ Userdef_INTC_Dummy_Interrupt, /* 71 : */
+ Userdef_INTC_Dummy_Interrupt, /* 72 : */
+ Userdef_INTC_Dummy_Interrupt, /* 73 : USBI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 74 : USBI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 75 : S0_VI_VSYNC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 76 : S0_LO_VSYNC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 77 : S0_VSYNCERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 78 : GR3_VLINE0 */
+ Userdef_INTC_Dummy_Interrupt, /* 79 : S0_VFIELD0 */
+ Userdef_INTC_Dummy_Interrupt, /* 80 : IV1_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 81 : IV3_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 82 : IV5_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 83 : IV6_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 84 : S0_WLINE0 */
+ Userdef_INTC_Dummy_Interrupt, /* 85 : S1_VI_VSYNC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 86 : S1_LO_VSYNC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 87 : S1_VSYNCERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 88 : S1_VFIELD0 */
+ Userdef_INTC_Dummy_Interrupt, /* 89 : IV2_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 90 : IV4_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 91 : S1_WLINE0 */
+ Userdef_INTC_Dummy_Interrupt, /* 92 : OIR_VI_VSYNC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 93 : OIR_LO_VSYNC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 94 : OIR_VSYNCERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 95 : OIR_VFIELD0 */
+ Userdef_INTC_Dummy_Interrupt, /* 96 : IV7_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 97 : IV8_VBUFERR0 */
+ Userdef_INTC_Dummy_Interrupt, /* 98 : OIR_WLINE0 */
+ Userdef_INTC_Dummy_Interrupt, /* 99 : S0_VI_VSYNC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 100 : S0_LO_VSYNC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 101 : S0_VSYNCERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 102 : GR3_VLINE1 */
+ Userdef_INTC_Dummy_Interrupt, /* 103 : S0_VFIELD1 */
+ Userdef_INTC_Dummy_Interrupt, /* 104 : IV1_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 105 : IV3_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 106 : IV5_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 107 : IV6_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 108 : S0_WLINE1 */
+ Userdef_INTC_Dummy_Interrupt, /* 109 : S1_VI_VSYNC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 110 : S1_LO_VSYNC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 111 : S1_VSYNCERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 112 : S1_VFIELD1 */
+ Userdef_INTC_Dummy_Interrupt, /* 113 : IV2_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 114 : IV4_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 115 : S1_WLINE1 */
+ Userdef_INTC_Dummy_Interrupt, /* 116 : OIR_VI_VSYNC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 117 : OIR_LO_VSYNC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 118 : OIR_VLINE1 */
+ Userdef_INTC_Dummy_Interrupt, /* 119 : OIR_VFIELD1 */
+ Userdef_INTC_Dummy_Interrupt, /* 120 : IV7_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 121 : IV8_VBUFERR1 */
+ Userdef_INTC_Dummy_Interrupt, /* 122 : OIR_WLINE1 */
+ Userdef_INTC_Dummy_Interrupt, /* 123 : IMRDI */
+ Userdef_INTC_Dummy_Interrupt, /* 124 : IMR2I0 */
+ Userdef_INTC_Dummy_Interrupt, /* 125 : IMR2I1 */
+ Userdef_INTC_Dummy_Interrupt, /* 126 : JEDI */
+ Userdef_INTC_Dummy_Interrupt, /* 127 : JDTI */
+ Userdef_INTC_Dummy_Interrupt, /* 128 : CMP0 */
+ Userdef_INTC_Dummy_Interrupt, /* 129 : CMP1 */
+ Userdef_INTC_Dummy_Interrupt, /* 130 : INT0 */
+ Userdef_INTC_Dummy_Interrupt, /* 131 : INT1 */
+ Userdef_INTC_Dummy_Interrupt, /* 132 : INT2 */
+ Userdef_INTC_Dummy_Interrupt, /* 133 : INT3 */
+ Userdef_INTC_Dummy_Interrupt, /* 134 : OSTMI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 135 : OSTMI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 136 : CMI */
+ Userdef_INTC_Dummy_Interrupt, /* 137 : WTOUT */
+ Userdef_INTC_Dummy_Interrupt, /* 138 : ITI */
+ Userdef_INTC_Dummy_Interrupt, /* 139 : TGI0A */
+ Userdef_INTC_Dummy_Interrupt, /* 140 : TGI0B */
+ Userdef_INTC_Dummy_Interrupt, /* 141 : TGI0C */
+ Userdef_INTC_Dummy_Interrupt, /* 142 : TGI0D */
+ Userdef_INTC_Dummy_Interrupt, /* 143 : TGI0V */
+ Userdef_INTC_Dummy_Interrupt, /* 144 : TGI0E */
+ Userdef_INTC_Dummy_Interrupt, /* 145 : TGI0F */
+ Userdef_INTC_Dummy_Interrupt, /* 146 : TGI1A */
+ Userdef_INTC_Dummy_Interrupt, /* 147 : TGI1B */
+ Userdef_INTC_Dummy_Interrupt, /* 148 : TGI1V */
+ Userdef_INTC_Dummy_Interrupt, /* 149 : TGI1U */
+ Userdef_INTC_Dummy_Interrupt, /* 150 : TGI2A */
+ Userdef_INTC_Dummy_Interrupt, /* 151 : TGI2B */
+ Userdef_INTC_Dummy_Interrupt, /* 152 : TGI2V */
+ Userdef_INTC_Dummy_Interrupt, /* 153 : TGI2U */
+ Userdef_INTC_Dummy_Interrupt, /* 154 : TGI3A */
+ Userdef_INTC_Dummy_Interrupt, /* 155 : TGI3B */
+ Userdef_INTC_Dummy_Interrupt, /* 156 : TGI3C */
+ Userdef_INTC_Dummy_Interrupt, /* 157 : TGI3D */
+ Userdef_INTC_Dummy_Interrupt, /* 158 : TGI3V */
+ Userdef_INTC_Dummy_Interrupt, /* 159 : TGI4A */
+ Userdef_INTC_Dummy_Interrupt, /* 160 : TGI4B */
+ Userdef_INTC_Dummy_Interrupt, /* 161 : TGI4C */
+ Userdef_INTC_Dummy_Interrupt, /* 162 : TGI4D */
+ Userdef_INTC_Dummy_Interrupt, /* 163 : TGI4V */
+ Userdef_INTC_Dummy_Interrupt, /* 164 : CMI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 165 : CMI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 166 : SGDEI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 167 : SGDEI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 168 : SGDEI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 169 : SGDEI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 170 : ADI */
+ Userdef_INTC_Dummy_Interrupt, /* 171 : ADWAR */
+ Userdef_INTC_Dummy_Interrupt, /* 172 : SSII0 */
+ Userdef_INTC_Dummy_Interrupt, /* 173 : SSIRXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 174 : SSITXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 175 : SSII1 */
+ Userdef_INTC_Dummy_Interrupt, /* 176 : SSIRXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 177 : SSITXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 178 : SSII2 */
+ Userdef_INTC_Dummy_Interrupt, /* 179 : SSIRTI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 180 : SSII3 */
+ Userdef_INTC_Dummy_Interrupt, /* 181 : SSIRXI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 182 : SSITXI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 183 : SSII4 */
+ Userdef_INTC_Dummy_Interrupt, /* 184 : SSIRTI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 185 : SSII5 */
+ Userdef_INTC_Dummy_Interrupt, /* 186 : SSIRXI5 */
+ Userdef_INTC_Dummy_Interrupt, /* 187 : SSITXI5 */
+ Userdef_INTC_Dummy_Interrupt, /* 188 : SPDIFI */
+ Userdef_INTC_Dummy_Interrupt, /* 189 : TEI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 190 : RI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 191 : TI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 192 : SPI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 193 : STI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 194 : NAKI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 195 : ALI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 196 : TMOI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 197 : TEI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 198 : RI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 199 : TI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 200 : SPI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 201 : STI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 202 : NAKI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 203 : ALI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 204 : TMOI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 205 : TEI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 206 : RI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 207 : TI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 208 : SPI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 209 : STI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 210 : NAKI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 211 : ALI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 212 : TMOI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 213 : TEI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 214 : RI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 215 : TI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 216 : SPI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 217 : STI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 218 : NAKI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 219 : ALI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 220 : TMOI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 221 : BRI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 222 : ERI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 223 : RXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 224 : TXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 225 : BRI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 226 : ERI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 227 : RXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 228 : TXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 229 : BRI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 230 : ERI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 231 : RXI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 232 : TXI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 233 : BRI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 234 : ERI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 235 : RXI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 236 : TXI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 237 : BRI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 238 : ERI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 239 : RXI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 240 : TXI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 241 : BRI5 */
+ Userdef_INTC_Dummy_Interrupt, /* 242 : ERI5 */
+ Userdef_INTC_Dummy_Interrupt, /* 243 : RXI5 */
+ Userdef_INTC_Dummy_Interrupt, /* 244 : TXI5 */
+ Userdef_INTC_Dummy_Interrupt, /* 245 : BRI6 */
+ Userdef_INTC_Dummy_Interrupt, /* 246 : ERI6 */
+ Userdef_INTC_Dummy_Interrupt, /* 247 : RXI6 */
+ Userdef_INTC_Dummy_Interrupt, /* 248 : TXI6 */
+ Userdef_INTC_Dummy_Interrupt, /* 249 : BRI7 */
+ Userdef_INTC_Dummy_Interrupt, /* 250 : ERI7 */
+ Userdef_INTC_Dummy_Interrupt, /* 251 : RXI7 */
+ Userdef_INTC_Dummy_Interrupt, /* 252 : TXI7 */
+ Userdef_INTC_Dummy_Interrupt, /* 253 : GERI */
+ Userdef_INTC_Dummy_Interrupt, /* 254 : RFI */
+ Userdef_INTC_Dummy_Interrupt, /* 255 : CFRXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 256 : CERI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 257 : CTXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 258 : CFRXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 259 : CERI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 260 : CTXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 261 : CFRXI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 262 : CERI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 263 : CTXI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 264 : CFRXI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 265 : CERI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 266 : CTXI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 267 : CFRXI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 268 : CERI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 269 : CTXI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 270 : SPEI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 271 : SPRI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 272 : SPTI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 273 : SPEI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 274 : SPRI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 275 : SPTI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 276 : SPEI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 277 : SPRI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 278 : SPTI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 279 : SPEI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 280 : SPRI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 281 : SPTI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 282 : SPEI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 283 : SPRI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 284 : SPTI4 */
+ Userdef_INTC_Dummy_Interrupt, /* 285 : IEBBTD */
+ Userdef_INTC_Dummy_Interrupt, /* 286 : IEBBTERR */
+ Userdef_INTC_Dummy_Interrupt, /* 287 : IEBBTSTA */
+ Userdef_INTC_Dummy_Interrupt, /* 288 : IEBBTV */
+ Userdef_INTC_Dummy_Interrupt, /* 289 : ISY */
+ Userdef_INTC_Dummy_Interrupt, /* 290 : IERR */
+ Userdef_INTC_Dummy_Interrupt, /* 291 : ITARG */
+ Userdef_INTC_Dummy_Interrupt, /* 292 : ISEC */
+ Userdef_INTC_Dummy_Interrupt, /* 293 : IBUF */
+ Userdef_INTC_Dummy_Interrupt, /* 294 : IREADY */
+ Userdef_INTC_Dummy_Interrupt, /* 295 : FLSTE */
+ Userdef_INTC_Dummy_Interrupt, /* 296 : FLTENDI */
+ Userdef_INTC_Dummy_Interrupt, /* 297 : FLTREQ0I */
+ Userdef_INTC_Dummy_Interrupt, /* 298 : FLTREQ1I */
+ Userdef_INTC_Dummy_Interrupt, /* 299 : MMC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 300 : MMC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 301 : MMC2 */
+ Userdef_INTC_Dummy_Interrupt, /* 302 : SDHI0_3 */
+ Userdef_INTC_Dummy_Interrupt, /* 303 : SDHI0_0 */
+ Userdef_INTC_Dummy_Interrupt, /* 304 : SDHI0_1 */
+ Userdef_INTC_Dummy_Interrupt, /* 305 : SDHI1_3 */
+ Userdef_INTC_Dummy_Interrupt, /* 306 : SDHI1_0 */
+ Userdef_INTC_Dummy_Interrupt, /* 307 : SDHI1_1 */
+ Userdef_INTC_Dummy_Interrupt, /* 308 : ARM */
+ Userdef_INTC_Dummy_Interrupt, /* 309 : PRD */
+ Userdef_INTC_Dummy_Interrupt, /* 310 : CUP */
+ Userdef_INTC_Dummy_Interrupt, /* 311 : SCUAI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 312 : SCUAI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 313 : SCUFDI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 314 : SCUFDI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 315 : SCUFDI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 316 : SCUFDI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 317 : SCUFUI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 318 : SCUFUI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 319 : SCUFUI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 320 : SCUFUI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 321 : SCUDVI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 322 : SCUDVI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 323 : SCUDVI2 */
+ Userdef_INTC_Dummy_Interrupt, /* 324 : SCUDVI3 */
+ Userdef_INTC_Dummy_Interrupt, /* 325 : MLBCI */
+ Userdef_INTC_Dummy_Interrupt, /* 326 : MLBSI */
+ Userdef_INTC_Dummy_Interrupt, /* 327 : DRC0 */
+ Userdef_INTC_Dummy_Interrupt, /* 328 : DRC1 */
+ Userdef_INTC_Dummy_Interrupt, /* 329 : */
+ Userdef_INTC_Dummy_Interrupt, /* 330 : */
+ Userdef_INTC_Dummy_Interrupt, /* 331 : LINI0_INT_T */
+ Userdef_INTC_Dummy_Interrupt, /* 332 : LINI0_INT_R */
+ Userdef_INTC_Dummy_Interrupt, /* 333 : LINI0_INT_S */
+ Userdef_INTC_Dummy_Interrupt, /* 334 : LINI0_INT_M */
+ Userdef_INTC_Dummy_Interrupt, /* 335 : LINI1_INT_T */
+ Userdef_INTC_Dummy_Interrupt, /* 336 : LINI1_INT_R */
+ Userdef_INTC_Dummy_Interrupt, /* 337 : LINI1_INT_S */
+ Userdef_INTC_Dummy_Interrupt, /* 338 : LINI1_INT_M */
+ Userdef_INTC_Dummy_Interrupt, /* 339 : */
+ Userdef_INTC_Dummy_Interrupt, /* 340 : */
+ Userdef_INTC_Dummy_Interrupt, /* 341 : */
+ Userdef_INTC_Dummy_Interrupt, /* 342 : */
+ Userdef_INTC_Dummy_Interrupt, /* 343 : */
+ Userdef_INTC_Dummy_Interrupt, /* 344 : */
+ Userdef_INTC_Dummy_Interrupt, /* 345 : */
+ Userdef_INTC_Dummy_Interrupt, /* 346 : */
+ Userdef_INTC_Dummy_Interrupt, /* 347 : ERI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 348 : RXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 349 : TXI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 350 : TEI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 351 : ERI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 352 : RXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 353 : TXI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 354 : TEI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 355 : */
+ Userdef_INTC_Dummy_Interrupt, /* 356 : */
+ Userdef_INTC_Dummy_Interrupt, /* 357 : */
+ Userdef_INTC_Dummy_Interrupt, /* 358 : */
+ Userdef_INTC_Dummy_Interrupt, /* 359 : ETHERI */
+ Userdef_INTC_Dummy_Interrupt, /* 360 : */
+ Userdef_INTC_Dummy_Interrupt, /* 361 : */
+ Userdef_INTC_Dummy_Interrupt, /* 362 : */
+ Userdef_INTC_Dummy_Interrupt, /* 363 : */
+ Userdef_INTC_Dummy_Interrupt, /* 364 : CEUI */
+ Userdef_INTC_Dummy_Interrupt, /* 365 : */
+ Userdef_INTC_Dummy_Interrupt, /* 366 : */
+ Userdef_INTC_Dummy_Interrupt, /* 367 : */
+ Userdef_INTC_Dummy_Interrupt, /* 368 : */
+ Userdef_INTC_Dummy_Interrupt, /* 369 : */
+ Userdef_INTC_Dummy_Interrupt, /* 370 : */
+ Userdef_INTC_Dummy_Interrupt, /* 371 : */
+ Userdef_INTC_Dummy_Interrupt, /* 372 : */
+ Userdef_INTC_Dummy_Interrupt, /* 373 : */
+ Userdef_INTC_Dummy_Interrupt, /* 374 : */
+ Userdef_INTC_Dummy_Interrupt, /* 375 : */
+ Userdef_INTC_Dummy_Interrupt, /* 376 : */
+ Userdef_INTC_Dummy_Interrupt, /* 377 : */
+ Userdef_INTC_Dummy_Interrupt, /* 378 : */
+ Userdef_INTC_Dummy_Interrupt, /* 379 : */
+ Userdef_INTC_Dummy_Interrupt, /* 380 : */
+ Userdef_INTC_Dummy_Interrupt, /* 381 : H2XMLB_ERRINT */
+ Userdef_INTC_Dummy_Interrupt, /* 382 : H2XIC1_ERRINT */
+ Userdef_INTC_Dummy_Interrupt, /* 383 : X2HPERI1_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 384 : X2HPERI2_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 385 : X2HPERI34_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 386 : X2HPERI5_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 387 : X2HPERI67_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 388 : X2HDBGR_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 389 : X2HBSC_ERRINT */
+ Userdef_INTC_Dummy_Interrupt, /* 390 : X2HSPI1_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 391 : X2HSPI2_ERRINT*/
+ Userdef_INTC_Dummy_Interrupt, /* 392 : PRRI */
+ Userdef_INTC_Dummy_Interrupt, /* 393 : IFEI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 394 : OFFI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 395 : PFVEI0 */
+ Userdef_INTC_Dummy_Interrupt, /* 396 : IFEI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 397 : OFFI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 398 : PFVEI1 */
+ Userdef_INTC_Dummy_Interrupt, /* 399 : */
+ Userdef_INTC_Dummy_Interrupt, /* 400 : */
+ Userdef_INTC_Dummy_Interrupt, /* 401 : */
+ Userdef_INTC_Dummy_Interrupt, /* 402 : */
+ Userdef_INTC_Dummy_Interrupt, /* 403 : */
+ Userdef_INTC_Dummy_Interrupt, /* 404 : */
+ Userdef_INTC_Dummy_Interrupt, /* 405 : */
+ Userdef_INTC_Dummy_Interrupt, /* 406 : */
+ Userdef_INTC_Dummy_Interrupt, /* 407 : */
+ Userdef_INTC_Dummy_Interrupt, /* 408 : */
+ Userdef_INTC_Dummy_Interrupt, /* 409 : */
+ Userdef_INTC_Dummy_Interrupt, /* 410 : */
+ Userdef_INTC_Dummy_Interrupt, /* 411 : */
+ Userdef_INTC_Dummy_Interrupt, /* 412 : */
+ Userdef_INTC_Dummy_Interrupt, /* 413 : */
+ Userdef_INTC_Dummy_Interrupt, /* 414 : */
+ Userdef_INTC_Dummy_Interrupt, /* 415 : */
+ Userdef_INTC_Dummy_Interrupt, /* 416 : TINT0 */
+ Userdef_INTC_Dummy_Interrupt, /* 417 : TINT1 */
+ Userdef_INTC_Dummy_Interrupt, /* 418 : TINT2 */
+ Userdef_INTC_Dummy_Interrupt, /* 419 : TINT3 */
+ Userdef_INTC_Dummy_Interrupt, /* 420 : TINT4 */
+ Userdef_INTC_Dummy_Interrupt, /* 421 : TINT5 */
+ Userdef_INTC_Dummy_Interrupt, /* 422 : TINT6 */
+ Userdef_INTC_Dummy_Interrupt, /* 423 : TINT7 */
+ Userdef_INTC_Dummy_Interrupt, /* 424 : TINT8 */
+ Userdef_INTC_Dummy_Interrupt, /* 425 : TINT9 */
+ Userdef_INTC_Dummy_Interrupt, /* 426 : TINT10 */
+ Userdef_INTC_Dummy_Interrupt, /* 427 : TINT11 */
+ Userdef_INTC_Dummy_Interrupt, /* 428 : TINT12 */
+ Userdef_INTC_Dummy_Interrupt, /* 429 : TINT13 */
+ Userdef_INTC_Dummy_Interrupt, /* 430 : TINT14 */
+ Userdef_INTC_Dummy_Interrupt, /* 431 : TINT15 */
+ Userdef_INTC_Dummy_Interrupt, /* 432 : TINT16 */
+ Userdef_INTC_Dummy_Interrupt, /* 433 : TINT17 */
+ Userdef_INTC_Dummy_Interrupt, /* 434 : TINT18 */
+ Userdef_INTC_Dummy_Interrupt, /* 435 : TINT19 */
+ Userdef_INTC_Dummy_Interrupt, /* 436 : TINT20 */
+ Userdef_INTC_Dummy_Interrupt, /* 437 : TINT21 */
+ Userdef_INTC_Dummy_Interrupt, /* 438 : TINT22 */
+ Userdef_INTC_Dummy_Interrupt, /* 439 : TINT23 */
+ Userdef_INTC_Dummy_Interrupt, /* 440 : TINT24 */
+ Userdef_INTC_Dummy_Interrupt, /* 441 : TINT25 */
+ Userdef_INTC_Dummy_Interrupt, /* 442 : TINT26 */
+ Userdef_INTC_Dummy_Interrupt, /* 443 : TINT27 */
+ Userdef_INTC_Dummy_Interrupt, /* 444 : TINT28 */
+ Userdef_INTC_Dummy_Interrupt, /* 445 : TINT29 */
+ Userdef_INTC_Dummy_Interrupt, /* 446 : TINT30 */
+ Userdef_INTC_Dummy_Interrupt, /* 447 : TINT31 */
+ Userdef_INTC_Dummy_Interrupt, /* 448 : TINT32 */
+ Userdef_INTC_Dummy_Interrupt, /* 449 : TINT33 */
+ Userdef_INTC_Dummy_Interrupt, /* 450 : TINT34 */
+ Userdef_INTC_Dummy_Interrupt, /* 451 : TINT35 */
+ Userdef_INTC_Dummy_Interrupt, /* 452 : TINT36 */
+ Userdef_INTC_Dummy_Interrupt, /* 453 : TINT37 */
+ Userdef_INTC_Dummy_Interrupt, /* 454 : TINT38 */
+ Userdef_INTC_Dummy_Interrupt, /* 455 : TINT39 */
+ Userdef_INTC_Dummy_Interrupt, /* 456 : TINT40 */
+ Userdef_INTC_Dummy_Interrupt, /* 457 : TINT41 */
+ Userdef_INTC_Dummy_Interrupt, /* 458 : TINT42 */
+ Userdef_INTC_Dummy_Interrupt, /* 459 : TINT43 */
+ Userdef_INTC_Dummy_Interrupt, /* 460 : TINT44 */
+ Userdef_INTC_Dummy_Interrupt, /* 461 : TINT45 */
+ Userdef_INTC_Dummy_Interrupt, /* 462 : TINT46 */
+ Userdef_INTC_Dummy_Interrupt, /* 463 : TINT47 */
+ Userdef_INTC_Dummy_Interrupt, /* 464 : TINT48 */
+ Userdef_INTC_Dummy_Interrupt, /* 465 : TINT49 */
+ Userdef_INTC_Dummy_Interrupt, /* 466 : TINT50 */
+ Userdef_INTC_Dummy_Interrupt, /* 467 : TINT51 */
+ Userdef_INTC_Dummy_Interrupt, /* 468 : TINT52 */
+ Userdef_INTC_Dummy_Interrupt, /* 469 : TINT53 */
+ Userdef_INTC_Dummy_Interrupt, /* 470 : TINT54 */
+ Userdef_INTC_Dummy_Interrupt, /* 471 : TINT55 */
+ Userdef_INTC_Dummy_Interrupt, /* 472 : TINT56 */
+ Userdef_INTC_Dummy_Interrupt, /* 473 : TINT57 */
+ Userdef_INTC_Dummy_Interrupt, /* 474 : TINT58 */
+ Userdef_INTC_Dummy_Interrupt, /* 475 : TINT59 */
+ Userdef_INTC_Dummy_Interrupt, /* 476 : TINT60 */
+ Userdef_INTC_Dummy_Interrupt, /* 477 : TINT61 */
+ Userdef_INTC_Dummy_Interrupt, /* 478 : TINT62 */
+ Userdef_INTC_Dummy_Interrupt, /* 479 : TINT63 */
+ Userdef_INTC_Dummy_Interrupt, /* 480 : TINT64 */
+ Userdef_INTC_Dummy_Interrupt, /* 481 : TINT65 */
+ Userdef_INTC_Dummy_Interrupt, /* 482 : TINT66 */
+ Userdef_INTC_Dummy_Interrupt, /* 483 : TINT67 */
+ Userdef_INTC_Dummy_Interrupt, /* 484 : TINT68 */
+ Userdef_INTC_Dummy_Interrupt, /* 485 : TINT69 */
+ Userdef_INTC_Dummy_Interrupt, /* 486 : TINT70 */
+ Userdef_INTC_Dummy_Interrupt, /* 487 : TINT71 */
+ Userdef_INTC_Dummy_Interrupt, /* 488 : TINT72 */
+ Userdef_INTC_Dummy_Interrupt, /* 489 : TINT73 */
+ Userdef_INTC_Dummy_Interrupt, /* 490 : TINT74 */
+ Userdef_INTC_Dummy_Interrupt, /* 491 : TINT75 */
+ Userdef_INTC_Dummy_Interrupt, /* 492 : TINT76 */
+ Userdef_INTC_Dummy_Interrupt, /* 493 : TINT77 */
+ Userdef_INTC_Dummy_Interrupt, /* 494 : TINT78 */
+ Userdef_INTC_Dummy_Interrupt, /* 495 : TINT79 */
+ Userdef_INTC_Dummy_Interrupt, /* 496 : TINT80 */
+ Userdef_INTC_Dummy_Interrupt, /* 497 : TINT81 */
+ Userdef_INTC_Dummy_Interrupt, /* 498 : TINT82 */
+ Userdef_INTC_Dummy_Interrupt, /* 499 : TINT83 */
+ Userdef_INTC_Dummy_Interrupt, /* 500 : TINT84 */
+ Userdef_INTC_Dummy_Interrupt, /* 501 : TINT85 */
+ Userdef_INTC_Dummy_Interrupt, /* 502 : TINT86 */
+ Userdef_INTC_Dummy_Interrupt, /* 503 : TINT87 */
+ Userdef_INTC_Dummy_Interrupt, /* 504 : TINT88 */
+ Userdef_INTC_Dummy_Interrupt, /* 505 : TINT89 */
+ Userdef_INTC_Dummy_Interrupt, /* 506 : TINT90 */
+ Userdef_INTC_Dummy_Interrupt, /* 507 : TINT91 */
+ Userdef_INTC_Dummy_Interrupt, /* 508 : TINT92 */
+ Userdef_INTC_Dummy_Interrupt, /* 509 : TINT93 */
+ Userdef_INTC_Dummy_Interrupt, /* 510 : TINT94 */
+ Userdef_INTC_Dummy_Interrupt, /* 511 : TINT95 */
+ Userdef_INTC_Dummy_Interrupt, /* 512 : TINT96 */
+ Userdef_INTC_Dummy_Interrupt, /* 513 : TINT97 */
+ Userdef_INTC_Dummy_Interrupt, /* 514 : TINT98 */
+ Userdef_INTC_Dummy_Interrupt, /* 515 : TINT99 */
+ Userdef_INTC_Dummy_Interrupt, /* 516 : TINT100 */
+ Userdef_INTC_Dummy_Interrupt, /* 517 : TINT101 */
+ Userdef_INTC_Dummy_Interrupt, /* 518 : TINT102 */
+ Userdef_INTC_Dummy_Interrupt, /* 519 : TINT103 */
+ Userdef_INTC_Dummy_Interrupt, /* 520 : TINT104 */
+ Userdef_INTC_Dummy_Interrupt, /* 521 : TINT105 */
+ Userdef_INTC_Dummy_Interrupt, /* 522 : TINT106 */
+ Userdef_INTC_Dummy_Interrupt, /* 523 : TINT107 */
+ Userdef_INTC_Dummy_Interrupt, /* 524 : TINT108 */
+ Userdef_INTC_Dummy_Interrupt, /* 525 : TINT109 */
+ Userdef_INTC_Dummy_Interrupt, /* 526 : TINT110 */
+ Userdef_INTC_Dummy_Interrupt, /* 527 : TINT111 */
+ Userdef_INTC_Dummy_Interrupt, /* 528 : TINT112 */
+ Userdef_INTC_Dummy_Interrupt, /* 529 : TINT113 */
+ Userdef_INTC_Dummy_Interrupt, /* 530 : TINT114 */
+ Userdef_INTC_Dummy_Interrupt, /* 531 : TINT115 */
+ Userdef_INTC_Dummy_Interrupt, /* 532 : TINT116 */
+ Userdef_INTC_Dummy_Interrupt, /* 533 : TINT117 */
+ Userdef_INTC_Dummy_Interrupt, /* 534 : TINT118 */
+ Userdef_INTC_Dummy_Interrupt, /* 535 : TINT119 */
+ Userdef_INTC_Dummy_Interrupt, /* 536 : TINT120 */
+ Userdef_INTC_Dummy_Interrupt, /* 537 : TINT121 */
+ Userdef_INTC_Dummy_Interrupt, /* 538 : TINT122 */
+ Userdef_INTC_Dummy_Interrupt, /* 539 : TINT123 */
+ Userdef_INTC_Dummy_Interrupt, /* 540 : TINT124 */
+ Userdef_INTC_Dummy_Interrupt, /* 541 : TINT125 */
+ Userdef_INTC_Dummy_Interrupt, /* 542 : TINT126 */
+ Userdef_INTC_Dummy_Interrupt, /* 543 : TINT127 */
+ Userdef_INTC_Dummy_Interrupt, /* 544 : TINT128 */
+ Userdef_INTC_Dummy_Interrupt, /* 545 : TINT129 */
+ Userdef_INTC_Dummy_Interrupt, /* 546 : TINT130 */
+ Userdef_INTC_Dummy_Interrupt, /* 547 : TINT131 */
+ Userdef_INTC_Dummy_Interrupt, /* 548 : TINT132 */
+ Userdef_INTC_Dummy_Interrupt, /* 549 : TINT133 */
+ Userdef_INTC_Dummy_Interrupt, /* 550 : TINT134 */
+ Userdef_INTC_Dummy_Interrupt, /* 551 : TINT135 */
+ Userdef_INTC_Dummy_Interrupt, /* 552 : TINT136 */
+ Userdef_INTC_Dummy_Interrupt, /* 553 : TINT137 */
+ Userdef_INTC_Dummy_Interrupt, /* 554 : TINT138 */
+ Userdef_INTC_Dummy_Interrupt, /* 555 : TINT139 */
+ Userdef_INTC_Dummy_Interrupt, /* 556 : TINT140 */
+ Userdef_INTC_Dummy_Interrupt, /* 557 : TINT141 */
+ Userdef_INTC_Dummy_Interrupt, /* 558 : TINT142 */
+ Userdef_INTC_Dummy_Interrupt, /* 559 : TINT143 */
+ Userdef_INTC_Dummy_Interrupt, /* 560 : TINT144 */
+ Userdef_INTC_Dummy_Interrupt, /* 561 : TINT145 */
+ Userdef_INTC_Dummy_Interrupt, /* 562 : TINT146 */
+ Userdef_INTC_Dummy_Interrupt, /* 563 : TINT147 */
+ Userdef_INTC_Dummy_Interrupt, /* 564 : TINT148 */
+ Userdef_INTC_Dummy_Interrupt, /* 565 : TINT149 */
+ Userdef_INTC_Dummy_Interrupt, /* 566 : TINT150 */
+ Userdef_INTC_Dummy_Interrupt, /* 567 : TINT151 */
+ Userdef_INTC_Dummy_Interrupt, /* 568 : TINT152 */
+ Userdef_INTC_Dummy_Interrupt, /* 569 : TINT153 */
+ Userdef_INTC_Dummy_Interrupt, /* 570 : TINT154 */
+ Userdef_INTC_Dummy_Interrupt, /* 571 : TINT155 */
+ Userdef_INTC_Dummy_Interrupt, /* 572 : TINT156 */
+ Userdef_INTC_Dummy_Interrupt, /* 573 : TINT157 */
+ Userdef_INTC_Dummy_Interrupt, /* 574 : TINT158 */
+ Userdef_INTC_Dummy_Interrupt, /* 575 : TINT159 */
+ Userdef_INTC_Dummy_Interrupt, /* 576 : TINT160 */
+ Userdef_INTC_Dummy_Interrupt, /* 577 : TINT161 */
+ Userdef_INTC_Dummy_Interrupt, /* 578 : TINT162 */
+ Userdef_INTC_Dummy_Interrupt, /* 579 : TINT163 */
+ Userdef_INTC_Dummy_Interrupt, /* 580 : TINT164 */
+ Userdef_INTC_Dummy_Interrupt, /* 581 : TINT165 */
+ Userdef_INTC_Dummy_Interrupt, /* 582 : TINT166 */
+ Userdef_INTC_Dummy_Interrupt, /* 583 : TINT167 */
+ Userdef_INTC_Dummy_Interrupt, /* 584 : TINT168 */
+ Userdef_INTC_Dummy_Interrupt, /* 585 : TINT169 */
+ Userdef_INTC_Dummy_Interrupt, /* 586 : TINT170 */
+};
+
+
+/******************************************************************************
+* Function Name: Userdef_INTC_RegistIntFunc
+* Description :
+* Arguments : uint16_t int_id
+* : void (* func)(uint32_t)
+* Return Value : none
+******************************************************************************/
+void Userdef_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense))
+{
+ intc_func_table[int_id] = func;
+}
+
+/******************************************************************************
+* Function Name: Userdef_INTC_UndefId
+* Description :
+* Arguments : uint16_t int_id
+* Return Value : none
+******************************************************************************/
+void Userdef_INTC_UndefId(uint16_t int_id)
+{
+ while (1)
+ {
+ /* Do Nothing */
+ }
+}
+
+/******************************************************************************
+* Function Name: Userdef_INTC_Dummy_Interrupt
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+static void Userdef_INTC_Dummy_Interrupt(uint32_t int_sense)
+{
+ /* Do Nothing */
+}
+
+/******************************************************************************
+* Function Name: Userdef_FIQ_HandlerExe
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+void Userdef_FIQ_HandlerExe(void)
+{
+}
+
+/* The function called by the RTOS port layer after it has managed interrupt
+entry. */
+void vApplicationIRQHandler( uint32_t ulICCIAR )
+{
+uint32_t ulInterruptID;
+
+ /* Re-enable interrupts. */
+ __enable_irq();
+
+ /* The ID of the interrupt can be obtained by bitwise anding the ICCIAR value
+ with 0x3FF. */
+ ulInterruptID = ulICCIAR & 0x3FFUL;
+
+ /* Call the function installed in the array of installed handler functions. */
+ intc_func_table[ ulInterruptID ]( 0 );
+}
+
+
+/* END of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/ostm/ostm_driver/ostm.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/ostm/ostm_driver/ostm.c
new file mode 100644
index 000000000..cb1c0fc11
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/ostm/ostm_driver/ostm.c
@@ -0,0 +1,207 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm.c
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - OS timer device driver (Initialize process)
+*******************************************************************************/
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_ostm.h" /* OSTM Driver header */
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== OSTM H/W ==== */
+#define OSTM_CH_TOTAL (2)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void OSTM_Open(volatile struct st_ostm_n * ostm);
+static void OSTM_Close(volatile struct st_ostm_n * ostm, uint32_t * count);
+
+/******************************************************************************
+* Function Name: R_OSTM_Init
+* Description :
+* Arguments : uint32_t channel
+* : uint32_t mode
+* : uint32_t cycle
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_OSTM_Init(uint32_t channel, uint32_t mode, uint32_t cycle)
+{
+ int32_t ret;
+
+ if ((channel >= OSTM_CH_TOTAL) || (mode > OSTM_MODE_COMPARE))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ switch (channel)
+ {
+ case DEVDRV_CH_0:
+ ret = Userdef_OSTM0_Init(mode, cycle);
+ break;
+ case DEVDRV_CH_1:
+ ret = Userdef_OSTM1_Init(mode, cycle);
+ break;
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/******************************************************************************
+* Function Name: R_OSTM_Open
+* Description :
+* Arguments : int32_t channel
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_OSTM_Open(uint32_t channel)
+{
+ if (channel >= OSTM_CH_TOTAL)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ switch (channel)
+ {
+ case DEVDRV_CH_0:
+ OSTM_Open(&OSTM0);
+ break;
+ case DEVDRV_CH_1:
+ OSTM_Open(&OSTM1);
+ break;
+ default:
+ break;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: R_OSTM_Close
+* Description :
+* Arguments : uint32_t channel
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t R_OSTM_Close(uint32_t channel, uint32_t * count)
+{
+ if (channel >= OSTM_CH_TOTAL)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ switch (channel)
+ {
+ case DEVDRV_CH_0:
+ OSTM_Close(&OSTM0, count);
+ break;
+ case DEVDRV_CH_1:
+ OSTM_Close(&OSTM1, count);
+ break;
+ default:
+ break;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: int_ostm0_interrupt
+* Description :
+* Arguments : none
+* Return Value : none
+******************************************************************************/
+int32_t R_OSTM_Interrupt(uint32_t channel)
+{
+ if (channel >= OSTM_CH_TOTAL)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ switch (channel)
+ {
+ case DEVDRV_CH_0:
+ Userdef_OSTM0_Int();
+ break;
+ case DEVDRV_CH_1:
+ Userdef_OSTM1_Int();
+ break;
+ default:
+ break;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: OSTM_Open
+* Description : This function opens OSTM.
+* Arguments : volatile struct st_scif_n * ostm
+* Return Value : none
+*******************************************************************************/
+static void OSTM_Open(volatile struct st_ostm_n * ostm)
+{
+ ostm->OSTMnTS.BIT.OSTMnTS = 1;
+}
+
+/******************************************************************************
+* Function Name: OSTM_Close
+* Description : This function closes OSTM.
+* Arguments : volatile struct st_scif_n * ostm
+* Return Value : none
+******************************************************************************/
+static void OSTM_Close(volatile struct st_ostm_n * ostm, uint32_t * count)
+{
+ ostm->OSTMnTT.BIT.OSTMnTT = 1;
+ *count = ostm->OSTMnCNT;
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/ostm/userdef/ostm_userdef.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/ostm/userdef/ostm_userdef.c
new file mode 100644
index 000000000..795ddf35a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/ostm/userdef/ostm_userdef.c
@@ -0,0 +1,134 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_userdef.c
+* $Rev: $
+* $Date:: $
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.13
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - OS timer device driver (User define function)
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_ostm.h" /* OSTM Driver header */
+#include "devdrv_intc.h" /* INTC Driver Header */
+#include "iodefine.h"
+#include "main.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define P0_CLOCK_FREQUENCY_kHz (33.333 * 1000) /* 33.333MHz */
+#define MAX_CYCLE_msec (0xFFFFFFFF / P0_CLOCK_FREQUENCY_kHz)
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static volatile uint8_t ostm_int_flg;
+
+/******************************************************************************
+* Function Name: Userdef_OSTM0_Init
+* Description :
+* Arguments : uint32_t mode
+* : uint32_t cycle
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t Userdef_OSTM0_Init(uint32_t mode, uint32_t cycle)
+{
+ return DEVDRV_SUCCESS;
+}
+
+/******************************************************************************
+* Function Name: Userdef_OSTM1_Init
+* Description :
+* Arguments : uint32_t mode
+* : uint32_t cycle
+* Return Value : DEVDRV_SUCCESS
+* : DEVDRV_ERROR
+******************************************************************************/
+int32_t Userdef_OSTM1_Init(uint32_t mode, uint32_t cycle)
+{
+ return 0;
+}
+
+/******************************************************************************
+* Function Name: Userdef_OSTM0_Int
+* Description :
+* Arguments :
+* Return Value : none
+******************************************************************************/
+void Userdef_OSTM0_Int(void)
+{
+}
+
+/******************************************************************************
+* Function Name: Userdef_OSTM1_Int
+* Description :
+* Arguments :
+* Return Value : none
+******************************************************************************/
+void Userdef_OSTM1_Int(void)
+{
+}
+
+/******************************************************************************
+* Function Name: Userdef_OSTM0_WaitInt
+* Description :
+* Arguments :
+* Return Value : none
+******************************************************************************/
+void Userdef_OSTM0_WaitInt(void)
+{
+}
+
+/******************************************************************************
+* Function Name: Userdef_OSTM1_WaitInt
+* Description :
+* Arguments :
+* Return Value : none
+******************************************************************************/
+void Userdef_OSTM1_WaitInt(void)
+{
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/scif_uart_driver/scif_uart.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/scif_uart_driver/scif_uart.c
new file mode 100644
index 000000000..657f0a2ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/scif_uart_driver/scif_uart.c
@@ -0,0 +1,94 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_uart_initialize.c
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - SCIF UART device driver (Initialize process)
+*******************************************************************************/
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_scif_uart.h" /* UART Driver header */
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define SCIF_UART_CH_TOTAL (8)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_SCIF_UART_Init
+* Description :
+* Arguments : uint32_t channel
+* : uint32_t mode
+* : : SCIF_UART_MODE_W
+* : : SCIF_UART_MODE_R
+* : : SCIF_UART_MODE_RW
+* : uint16_t cks
+* : uint8_t scbrr
+* Return Value : DEVDRV_SUCCESS : Success
+* : DEVDRV_ERROR : Error
+******************************************************************************/
+int32_t R_SCIF_UART_Init(uint32_t channel, uint32_t mode, uint16_t cks, uint8_t scbrr)
+{
+ if ((channel >= SCIF_UART_CH_TOTAL) || (mode < SCIF_UART_MODE_W) || (mode > SCIF_UART_MODE_RW) || (cks > 3))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ switch (channel)
+ {
+ case DEVDRV_CH_2:
+ Userdef_SCIF2_UART_Init(mode, cks, scbrr);
+ break;
+ default:
+ /* Do Nothing */
+ break;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/userdef/scif_uart_userdef.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/userdef/scif_uart_userdef.c
new file mode 100644
index 000000000..ca95bc105
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/drivers/scif_uart/userdef/scif_uart_userdef.c
@@ -0,0 +1,143 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_uart_userdef.c
+* $Rev: $
+* $Date:: $
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.13
+* : ARM Complier
+* OS :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program - SCIF UART device driver (User define function)
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include
+#include "r_typedefs.h"
+#include "dev_drv.h" /* Device Driver common header */
+#include "devdrv_scif_uart.h" /* UART Driver header */
+#include "devdrv_intc.h" /* INTC Driver Header */
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: Userdef_SCIF2_UART_Init
+* Description :
+* Arguments : uint8_t mode
+* : uint16_t cks
+* : uint8_t scbrr
+* Return Value : none
+******************************************************************************/
+void Userdef_SCIF2_UART_Init(uint8_t mode, uint16_t cks, uint8_t scbrr)
+{
+ /* ==== SCIF initial setting ==== */
+ /* ---- Serial control register (SCSCR2) setting ---- */
+ /* SCIF transmitting and receiving operations stop */
+ SCIF2.SCSCR.WORD = 0x0000;
+
+ if (SCIF_UART_MODE_W == (mode & SCIF_UART_MODE_W))
+ {
+ /* ---- FIFO control register (SCFCR2) setting ---- */
+ SCIF2.SCFCR.BIT.TFRST = 1; /* Transmit FIFO reset */
+ }
+
+ if (SCIF_UART_MODE_R == (mode & SCIF_UART_MODE_R))
+ {
+ /* ---- FIFO control register (SCFCR2) setting ---- */
+ /* SCIF transmitting and receiving operations stop */
+ SCIF2.SCFCR.BIT.RFRST = 1;
+
+ /* Receive FIFO data register reset */
+ }
+
+ /* ---- Serial status register(SCFSR2) setting ---- */
+ /* ER,BRK,DR bit clear */
+ SCIF2.SCFSR.WORD &= 0xFF6E;
+
+ /* ---- Line status register (SCLSR2) setting ---- */
+ /* ORER bit clear */
+ SCIF2.SCLSR.BIT.ORER = 0;
+
+ /* ---- Serial control register (SCSCR2) setting ---- */
+ /* B'00 : Internal CLK */
+ SCIF2.SCSCR.BIT.CKE = 0x0;
+
+ /* ---- Serial mode register (SCSMR2) setting ---- */
+ /* Communication mode 0: Asynchronous mode */
+ /* Character length 0: 8-bit data */
+ /* Parity enable 0: Add and check are disabled */
+ /* Stop bit length 0: 1 stop bit */
+ /* Clock select cks(argument) */
+ SCIF2.SCSMR.WORD = cks & 0x0003;
+
+ /* ---- Sets the Serial extension mode register (SCEMR2) ---- */
+ /* Baud rate generator double-speed mode, 0: Normal mode */
+ /* Base clock select in asynchronous mode, */
+ /* 0: Base clock is 16 times the bit rate */
+ SCIF2.SCEMR.WORD = 0x0000;
+
+ /* ---- Bit rate register (SCBRR2) setting ---- */
+ SCIF2.SCBRR.BYTE = scbrr;
+
+ /* ---- FIFO control register (SCFCR2) setting ---- */
+ /* RTS output active trigger :Initial value */
+ /* Receive FIFO data trigger :1-data */
+ /* Transmit FIFO data trigger :0-data */
+ /* Modem control enable :Disabled */
+ /* Receive FIFO data register reset :Disabled */
+ /* Loop-back test :Disabled */
+ SCIF2.SCFCR.WORD = 0x0030;
+
+ /* ---- Serial port register (SCSPTR2) setting ---- */
+ /* Serial port break output(SPB2IO) 1: Enabled */
+ /* Serial port break data(SPB2DT) 1: High-level */
+ SCIF2.SCSPTR.WORD |= 0x0003;
+}
+
+/* End of File */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/irqfiq_handler.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/irqfiq_handler.s
new file mode 100644
index 000000000..10347fb95
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/irqfiq_handler.s
@@ -0,0 +1,64 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : irqfiq_handler.s
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.13
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program - IRQ, FIQ handler
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
+INTC_ICCIAR_ADDR EQU 0xE820200C
+INTC_ICCEOIR_ADDR EQU 0xE8202010
+
+
+;==================================================================
+; Entry point for the FIQ handler
+;==================================================================
+ PRESERVE8
+ AREA IRQ_FIQ_HANDLER, CODE, READONLY
+
+ IMPORT FiqHandler_Interrupt
+
+ EXPORT fiq_handler
+
+fiq_handler
+ BL FiqHandler_Interrupt
+
+fiq_handler_end
+ B fiq_handler_end
+
+
+Literals3
+ LTORG
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/reset_handler.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/reset_handler.s
new file mode 100644
index 000000000..0aae64252
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/handler/reset_handler.s
@@ -0,0 +1,257 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : reset_handler.s
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.8
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program - Reset handler
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
+USR_MODE EQU 0x10
+FIQ_MODE EQU 0x11
+IRQ_MODE EQU 0x12
+SVC_MODE EQU 0x13
+ABT_MODE EQU 0x17
+UND_MODE EQU 0x1b
+SYS_MODE EQU 0x1f
+Thum_bit EQU 0x20 ; CPSR/SPSR Thumb bit
+
+
+;==================================================================
+; Entry point for the Reset handler
+;==================================================================
+ PRESERVE8
+ AREA RESET_HANDLER, CODE, READONLY
+
+ IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ IMPORT ||Image$$IRQ_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ IMPORT ||Image$$FIQ_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ IMPORT ||Image$$SVC_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+ IMPORT ||Image$$ABT_STACK$$ZI$$Limit|| ; Linker symbol from scatter file
+
+ IMPORT Peripheral_BasicInit
+ IMPORT init_TTB
+ IMPORT __main
+
+ EXPORT reset_handler
+ EXPORT undefined_handler
+ EXPORT svc_handler
+ EXPORT prefetch_handler
+ EXPORT abort_handler
+ EXPORT reserved_handler
+
+;==================================================================
+; Reset Handler
+;==================================================================
+reset_handler FUNCTION {}
+
+;==================================================================
+; Disable cache and MMU in case it was left enabled from an earlier run
+; This does not need to be done from a cold reset
+;==================================================================
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 System Control register (SCTLR)
+ BIC r0, r0, #(0x1 << 12) ;;; Clear I bit 12 to disable I Cache
+ BIC r0, r0, #(0x1 << 2) ;;; Clear C bit 2 to disable D Cache
+ BIC r0, r0, #0x1 ;;; Clear M bit 0 to disable MMU
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write value back to CP15 System Control register
+
+;==================================================================
+; Setting up Stack Area
+;==================================================================
+ ;;; SVC Mode(Default)
+ LDR sp, =||Image$$SVC_STACK$$ZI$$Limit||
+
+ CPS #IRQ_MODE ;;; IRQ Mode
+ LDR sp, =||Image$$IRQ_STACK$$ZI$$Limit||
+
+ CPS #FIQ_MODE ;;; FIQ Mode
+ LDR sp, =||Image$$FIQ_STACK$$ZI$$Limit||
+
+ CPS #ABT_MODE ;;; ABT Mode
+ LDR sp, =||Image$$ABT_STACK$$ZI$$Limit||
+
+;; FreeRTOS Note:
+;; FreeRTOS does not need a System/User mode stack as only tasks run in
+;; System/User mode, and their stack is allocated when the task is created.
+;; Therefore the CSTACK allocated in the linker script is instead given to
+;; Supervisor mode, and main() is called from Supervisor mode.
+
+ CPS #SVC_MODE ;;; SVC Mode
+
+;; SVC mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry()
+ LDR sp, =||Image$$ARM_LIB_STACK$$ZI$$Limit||
+
+;==================================================================
+; TLB maintenance, Invalidate Data and Instruction TLBs
+;==================================================================
+ MOV r0,#0
+ MCR p15, 0, r0, c8, c7, 0 ;;; Cortex-A9 I-TLB and D-TLB invalidation (TLBIALL)
+
+;===================================================================
+; Invalidate instruction cache, also flushes BTAC
+;===================================================================
+ MOV r0, #0 ;;; SBZ
+ MCR p15, 0, r0, c7, c5, 0 ;;; ICIALLU - Invalidate entire I Cache, and flushes branch target cache
+
+;==================================================================
+; Cache Invalidation code for Cortex-A9
+;==================================================================
+ ;;; Invalidate L1 Instruction Cache
+ MRC p15, 1, r0, c0, c0, 1 ;;; Read Cache Level ID Register (CLIDR)
+ TST r0, #0x3 ;;; Harvard Cache?
+ MOV r0, #0
+ MCRNE p15, 0, r0, c7, c5, 0 ;;; Invalidate Instruction Cache
+
+ ;;; Invalidate Data/Unified Caches
+ MRC p15, 1, r0, c0, c0, 1 ;;; Read CLIDR
+ ANDS r3, r0, #0x07000000 ;;; Extract coherency level
+ MOV r3, r3, LSR #23 ;;; Total cache levels << 1
+ BEQ Finished ;;; If 0, no need to clean
+
+ MOV r10, #0 ;;; R10 holds current cache level << 1
+Loop1
+ ADD r2, r10, r10, LSR #1 ;;; R2 holds cache "Set" position
+ MOV r1, r0, LSR r2 ;;; Bottom 3 bits are the Cache-type for this level
+ AND r1, r1, #7 ;;; Isolate those lower 3 bits
+ CMP r1, #2
+ BLT Skip ;;; No cache or only instruction cache at this level
+
+ MCR p15, 2, r10, c0, c0, 0 ;;; Write the Cache Size selection register (CSSELR)
+ ISB ;;; ISB to sync the change to the CacheSizeID reg
+ MRC p15, 1, r1, c0, c0, 0 ;;; Reads current Cache Size ID register (CCSIDR)
+ AND r2, r1, #7 ;;; Extract the line length field
+ ADD r2, r2, #4 ;;; Add 4 for the line length offset (log2 16 bytes)
+ LDR r4, =0x3FF
+ ANDS r4, r4, r1, LSR #3 ;;; R4 is the max number on the way size (right aligned)
+ CLZ r5, r4 ;;; R5 is the bit position of the way size increment
+ LDR r7, =0x7FFF
+ ANDS r7, r7, r1, LSR #13 ;;; R7 is the max number of the index size (right aligned)
+Loop2
+ MOV r9, r4 ;;; R9 working copy of the max way size (right aligned)
+
+Loop3
+ ORR r11, r10, r9, LSL r5 ;;; Factor in the Way number and cache number into R11
+ ORR r11, r11, r7, LSL r2 ;;; Factor in the Set number
+ MCR p15, 0, r11, c7, c6, 2 ;;; Invalidate by Set/Way (DCISW)
+ SUBS r9, r9, #1 ;;; Decrement the Way number
+ BGE Loop3
+ SUBS r7, r7, #1 ;;; Decrement the Set number
+ BGE Loop2
+Skip
+ ADD r10, r10, #2 ;;; increment the cache number
+ CMP r3, r10
+ BGT Loop1
+
+Finished
+
+;==================================================================
+; TTB initialize
+;==================================================================
+ BL init_TTB ;;; Initialize TTB
+
+;===================================================================
+; Setup domain control register - Enable all domains to client mode
+;===================================================================
+ MRC p15, 0, r0, c3, c0, 0 ;;; Read Domain Access Control Register (DACR)
+ LDR r0, =0x55555555 ;;; Initialize every domain entry to b01 (client)
+ MCR p15, 0, r0, c3, c0, 0 ;;; Write Domain Access Control Register
+
+ IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP}
+;==================================================================
+; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+; Enables Full Access i.e. in both privileged and non privileged modes
+;==================================================================
+ MRC p15, 0, r0, c1, c0, 2 ;;; Read Coprocessor Access Control Register (CPACR)
+ ORR r0, r0, #(0xF << 20) ;;; Enable access to CP 10 & 11
+ MCR p15, 0, r0, c1, c0, 2 ;;; Write Coprocessor Access Control Register (CPACR)
+ ISB
+
+;=================================================================
+; Switch on the VFP and NEON hardware
+;=================================================================
+ MOV r0, #0x40000000
+ VMSR FPEXC, r0 ;;; Write FPEXC register, EN bit set
+
+ ENDIF
+
+;===================================================================
+; Enable MMU
+; Leaving the caches disabled until after scatter loading(__main).
+;===================================================================
+ MRC p15, 0, r0, c1, c0, 0 ;;; Read CP15 System Control register (SCTLR)
+ BIC r0, r0, #(0x1 << 12) ;;; Clear I bit 12 to disable I Cache
+ BIC r0, r0, #(0x1 << 2) ;;; Clear C bit 2 to disable D Cache
+ BIC r0, r0, #0x2 ;;; Clear A bit 1 to disable strict alignment fault checking
+ ORR r0, r0, #0x1 ;;; Set M bit 0 to enable MMU before scatter loading
+ MCR p15, 0, r0, c1, c0, 0 ;;; Write CP15 System Control register
+
+;==================================================================
+; Hardware initialize
+; Initialize CPG, BSC for CS0 and CS1, and enable On-Chip Data-Retention RAM
+;==================================================================
+ LDR r12,=Peripheral_BasicInit ;;; Save this in register for possible long jump
+ BLX r12 ;;; Hardware Initialize
+
+;===================================================================
+; Branch to __main
+;===================================================================
+ LDR r12,=__main ;;; Save this in register for possible long jump
+ BX r12 ;;; Branch to __main C library entry point
+
+
+ ENDFUNC
+
+Literals2
+ LTORG
+
+
+;==================================================================
+; Other Handler
+;==================================================================
+undefined_handler
+ B undefined_handler ;;; Ž©â€Ã”’nƒ‹�[Æ’v
+
+svc_handler
+ B svc_handler ;;; Ž©â€Ã”’nƒ‹�[Æ’v
+
+prefetch_handler
+ B prefetch_handler ;;; Ž©â€Ã”’nƒ‹�[Æ’v
+
+abort_handler
+ B abort_handler ;;; Ž©â€Ã”’nƒ‹�[Æ’v
+
+reserved_handler
+ B reserved_handler ;;; Ž©â€Ã”’nƒ‹�[Æ’v
+
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/command.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/command.h
new file mode 100644
index 000000000..14a479e33
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/command.h
@@ -0,0 +1,69 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : command.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - Command header
+******************************************************************************/
+#ifndef _COMMAND_H_
+#define _COMMAND_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct command_list
+{
+ char_t *cmd_str;
+ int32_t (*cmdexe)(int32_t, char_t **);
+ int32_t (*helpexe)(void);
+} command_list_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Maximum number of characters for arguments */
+#define COMMAND_MAX_ARGLENGTH (256)
+
+#define COMMAND_EXIT (-100)
+#define COMMAND_SUCCESS (0)
+#define COMMAND_ERROR (-1)
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+int32_t CommandExe(char_t * buff);
+void CommandSetCmdList(const command_list_t * cmd);
+
+#endif /* _COMMAND_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/dev_drv.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/dev_drv.h
new file mode 100644
index 000000000..a6c9d86b4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/dev_drv.h
@@ -0,0 +1,80 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : dev_drv.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - Device driver header
+******************************************************************************/
+#ifndef _DEV_DRV_H_
+#define _DEV_DRV_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define DEVDRV_SUCCESS (0) /* Success */
+#define DEVDRV_ERROR (-1) /* Failure */
+
+#define DEVDRV_FLAG_OFF (0) /* Flag OFF */
+#define DEVDRV_FLAG_ON (1) /* Flag ON */
+
+typedef enum devdrv_ch
+{
+ DEVDRV_CH_0, /* Channel 0 */
+ DEVDRV_CH_1, /* Channel 1 */
+ DEVDRV_CH_2, /* Channel 2 */
+ DEVDRV_CH_3, /* Channel 3 */
+ DEVDRV_CH_4, /* Channel 4 */
+ DEVDRV_CH_5, /* Channel 5 */
+ DEVDRV_CH_6, /* Channel 6 */
+ DEVDRV_CH_7, /* Channel 7 */
+ DEVDRV_CH_8, /* Channel 8 */
+ DEVDRV_CH_9, /* Channel 9 */
+ DEVDRV_CH_10, /* Channel 10 */
+ DEVDRV_CH_11, /* Channel 11 */
+ DEVDRV_CH_12, /* Channel 12 */
+ DEVDRV_CH_13, /* Channel 13 */
+ DEVDRV_CH_14, /* Channel 14 */
+ DEVDRV_CH_15 /* Channel 15 */
+} devdrv_ch_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif /* _DEV_DRV_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_common.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_common.h
new file mode 100644
index 000000000..c6ea1303c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_common.h
@@ -0,0 +1,68 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : devdrv_common.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - Common driver header
+******************************************************************************/
+#ifndef _DEVDRV_COMMON_H_
+#define _DEVDRV_COMMON_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define BSC_AREA_CS0 (0x01) /* CS0 */
+#define BSC_AREA_CS1 (0x02) /* CS1 */
+#define BSC_AREA_CS2 (0x04) /* CS2 */
+#define BSC_AREA_CS3 (0x08) /* CS3 */
+#define BSC_AREA_CS4 (0x10) /* CS4 */
+#define BSC_AREA_CS5 (0x20) /* CS5 */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void R_BSC_Init(uint8_t area);
+void Userdef_BSC_CS0Init(void);
+void Userdef_BSC_CS1Init(void);
+void Userdef_BSC_CS2Init(void);
+void Userdef_BSC_CS3Init(void);
+void Userdef_BSC_CS4Init(void);
+void Userdef_BSC_CS5Init(void);
+
+#endif /* _DEVDRV_COMMON_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_intc.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_intc.h
new file mode 100644
index 000000000..e379abf11
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_intc.h
@@ -0,0 +1,585 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : devdrv_intc.h
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - INTC device driver header
+******************************************************************************/
+#ifndef _DEVDRV_INTC_H_
+#define _DEVDRV_INTC_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INTC_ID_TOTAL (587)
+
+#define INTC_ID_SW0 (0)
+#define INTC_ID_SW1 (1) /* */
+#define INTC_ID_SW2 (2) /* */
+#define INTC_ID_SW3 (3) /* */
+#define INTC_ID_SW4 (4) /* */
+#define INTC_ID_SW5 (5) /* */
+#define INTC_ID_SW6 (6) /* */
+#define INTC_ID_SW7 (7) /* */
+#define INTC_ID_SW8 (8) /* */
+#define INTC_ID_SW9 (9) /* */
+#define INTC_ID_SW10 (10) /* */
+#define INTC_ID_SW11 (11) /* */
+#define INTC_ID_SW12 (12) /* */
+#define INTC_ID_SW13 (13) /* */
+#define INTC_ID_SW14 (14) /* */
+#define INTC_ID_SW15 (15) /* */
+#define INTC_ID_PMUIRQ0 (16) /* CPU */
+#define INTC_ID_COMMRX0 (17) /* */
+#define INTC_ID_COMMTX0 (18) /* */
+#define INTC_ID_CTIIRQ0 (19) /* */
+#define INTC_ID_IRQ0 (32) /* IRQ */
+#define INTC_ID_IRQ1 (33) /* */
+#define INTC_ID_IRQ2 (34) /* */
+#define INTC_ID_IRQ3 (35) /* */
+#define INTC_ID_IRQ4 (36) /* */
+#define INTC_ID_IRQ5 (37) /* */
+#define INTC_ID_IRQ6 (38) /* */
+#define INTC_ID_IRQ7 (39) /* */
+#define INTC_ID_PL310ERR (40)
+#define INTC_ID_DMAINT0 (41)
+#define INTC_ID_DMAINT1 (42) /* */
+#define INTC_ID_DMAINT2 (43) /* */
+#define INTC_ID_DMAINT3 (44) /* */
+#define INTC_ID_DMAINT4 (45) /* */
+#define INTC_ID_DMAINT5 (46) /* */
+#define INTC_ID_DMAINT6 (47) /* */
+#define INTC_ID_DMAINT7 (48) /* */
+#define INTC_ID_DMAINT8 (49) /* */
+#define INTC_ID_DMAINT9 (50) /* */
+#define INTC_ID_DMAINT10 (51) /* */
+#define INTC_ID_DMAINT11 (52) /* */
+#define INTC_ID_DMAINT12 (53) /* */
+#define INTC_ID_DMAINT13 (54) /* */
+#define INTC_ID_DMAINT14 (55) /* */
+#define INTC_ID_DMAINT15 (56) /* */
+#define INTC_ID_DMAERR (57) /* */
+#define INTC_ID_USBI0 (73)
+#define INTC_ID_USBI1 (74) /* */
+#define INTC_ID_S0_VI_VSYNC0 (75)
+#define INTC_ID_S0_LO_VSYNC0 (76) /* */
+#define INTC_ID_S0_VSYNCERR0 (77) /* */
+#define INTC_ID_GR3_VLINE0 (78) /* */
+#define INTC_ID_S0_VFIELD0 (79) /* */
+#define INTC_ID_IV1_VBUFERR0 (80) /* */
+#define INTC_ID_IV3_VBUFERR0 (81) /* */
+#define INTC_ID_IV5_VBUFERR0 (82) /* */
+#define INTC_ID_IV6_VBUFERR0 (83) /* */
+#define INTC_ID_S0_WLINE0 (84) /* */
+#define INTC_ID_S1_VI_VSYNC0 (85) /* */
+#define INTC_ID_S1_LO_VSYNC0 (86) /* */
+#define INTC_ID_S1_VSYNCERR0 (87) /* */
+#define INTC_ID_S1_VFIELD0 (88) /* */
+#define INTC_ID_IV2_VBUFERR0 (89) /* */
+#define INTC_ID_IV4_VBUFERR0 (90) /* */
+#define INTC_ID_S1_WLINE0 (91) /* */
+#define INTC_ID_OIR_VI_VSYNC0 (92) /* */
+#define INTC_ID_OIR_LO_VSYNC0 (93) /* */
+#define INTC_ID_OIR_VSYNCERR0 (94) /* */
+#define INTC_ID_OIR_VFIELD0 (95) /* */
+#define INTC_ID_IV7_VBUFERR0 (96) /* */
+#define INTC_ID_IV8_VBUFERR0 (97) /* */
+#define INTC_ID_OIR_WLINE0 (98) /* */
+#define INTC_ID_S0_VI_VSYNC1 (99) /* */
+#define INTC_ID_S0_LO_VSYNC1 (100) /* */
+#define INTC_ID_S0_VSYNCERR1 (101) /* */
+#define INTC_ID_GR3_VLINE1 (102) /* */
+#define INTC_ID_S0_VFIELD1 (103) /* */
+#define INTC_ID_IV1_VBUFERR1 (104) /* */
+#define INTC_ID_IV3_VBUFERR1 (105) /* */
+#define INTC_ID_IV5_VBUFERR1 (106) /* */
+#define INTC_ID_IV6_VBUFERR1 (107) /* */
+#define INTC_ID_S0_WLINE1 (108) /* */
+#define INTC_ID_S1_VI_VSYNC1 (109) /* */
+#define INTC_ID_S1_LO_VSYNC1 (110) /* */
+#define INTC_ID_S1_VSYNCERR1 (111) /* */
+#define INTC_ID_S1_VFIELD1 (112) /* */
+#define INTC_ID_IV2_VBUFERR1 (113) /* */
+#define INTC_ID_IV4_VBUFERR1 (114) /* */
+#define INTC_ID_S1_WLINE1 (115) /* */
+#define INTC_ID_OIR_VI_VSYNC1 (116) /* */
+#define INTC_ID_OIR_LO_VSYNC1 (117) /* */
+#define INTC_ID_OIR_VLINE1 (118) /* */
+#define INTC_ID_OIR_VFIELD1 (119) /* */
+#define INTC_ID_IV7_VBUFERR1 (120) /* */
+#define INTC_ID_IV8_VBUFERR1 (121) /* */
+#define INTC_ID_OIR_WLINE1 (122) /* */
+#define INTC_ID_IMRDI (123)
+#define INTC_ID_IMR2I0 (124) /* */
+#define INTC_ID_IMR2I1 (125) /* */
+#define INTC_ID_JEDI (126)
+#define INTC_ID_JDTI (127) /* */
+#define INTC_ID_CMP0 (128)
+#define INTC_ID_CMP1 (129) /* */
+#define INTC_ID_INT0 (130)
+#define INTC_ID_INT1 (131) /* */
+#define INTC_ID_INT2 (132) /* */
+#define INTC_ID_INT3 (133) /* */
+#define INTC_ID_OSTMI0 (134)
+#define INTC_ID_OSTMI1 (135) /* */
+#define INTC_ID_CMI (136)
+#define INTC_ID_WTOUT (137) /* */
+#define INTC_ID_ITI (138)
+#define INTC_ID_TGI0A (139)
+#define INTC_ID_TGI0B (140) /* */
+#define INTC_ID_TGI0C (141) /* */
+#define INTC_ID_TGI0D (142) /* */
+#define INTC_ID_TGI0V (143) /* */
+#define INTC_ID_TGI0E (144) /* */
+#define INTC_ID_TGI0F (145) /* */
+#define INTC_ID_TGI1A (146) /* */
+#define INTC_ID_TGI1B (147) /* */
+#define INTC_ID_TGI1V (148) /* */
+#define INTC_ID_TGI1U (149) /* */
+#define INTC_ID_TGI2A (150) /* */
+#define INTC_ID_TGI2B (151) /* */
+#define INTC_ID_TGI2V (152) /* */
+#define INTC_ID_TGI2U (153) /* */
+#define INTC_ID_TGI3A (154) /* */
+#define INTC_ID_TGI3B (155) /* */
+#define INTC_ID_TGI3C (156) /* */
+#define INTC_ID_TGI3D (157) /* */
+#define INTC_ID_TGI3V (158) /* */
+#define INTC_ID_TGI4A (159) /* */
+#define INTC_ID_TGI4B (160) /* */
+#define INTC_ID_TGI4C (161) /* */
+#define INTC_ID_TGI4D (162) /* */
+#define INTC_ID_TGI4V (163) /* */
+#define INTC_ID_CMI1 (164)
+#define INTC_ID_CMI2 (165) /* */
+#define INTC_ID_SGDEI0 (166)
+#define INTC_ID_SGDEI1 (167) /* */
+#define INTC_ID_SGDEI2 (168) /* */
+#define INTC_ID_SGDEI3 (169) /* */
+#define INTC_ID_ADI (170)
+#define INTC_ID_ADWAR (171) /* */
+#define INTC_ID_SSII0 (172)
+#define INTC_ID_SSIRXI0 (173) /* */
+#define INTC_ID_SSITXI0 (174) /* */
+#define INTC_ID_SSII1 (175) /* */
+#define INTC_ID_SSIRXI1 (176) /* */
+#define INTC_ID_SSITXI1 (177) /* */
+#define INTC_ID_SSII2 (178) /* */
+#define INTC_ID_SSIRTI2 (179) /* */
+#define INTC_ID_SSII3 (180) /* */
+#define INTC_ID_SSIRXI3 (181) /* */
+#define INTC_ID_SSITXI3 (182) /* */
+#define INTC_ID_SSII4 (183) /* */
+#define INTC_ID_SSIRTI4 (184) /* */
+#define INTC_ID_SSII5 (185) /* */
+#define INTC_ID_SSIRXI5 (186) /* */
+#define INTC_ID_SSITXI5 (187) /* */
+#define INTC_ID_SPDIFI (188)
+#define INTC_ID_TEI0 (189)
+#define INTC_ID_RI0 (190) /* */
+#define INTC_ID_TI0 (191) /* */
+#define INTC_ID_SPI0 (192) /* */
+#define INTC_ID_STI0 (193) /* */
+#define INTC_ID_NAKI0 (194) /* */
+#define INTC_ID_ALI0 (195) /* */
+#define INTC_ID_TMOI0 (196) /* */
+#define INTC_ID_TEI1 (197) /* */
+#define INTC_ID_RI1 (198) /* */
+#define INTC_ID_TI1 (199) /* */
+#define INTC_ID_SPI1 (200) /* */
+#define INTC_ID_STI1 (201) /* */
+#define INTC_ID_NAKI1 (202) /* */
+#define INTC_ID_ALI1 (203) /* */
+#define INTC_ID_TMOI1 (204) /* */
+#define INTC_ID_TEI2 (205) /* */
+#define INTC_ID_RI2 (206) /* */
+#define INTC_ID_TI2 (207) /* */
+#define INTC_ID_SPI2 (208) /* */
+#define INTC_ID_STI2 (209) /* */
+#define INTC_ID_NAKI2 (210) /* */
+#define INTC_ID_ALI2 (211) /* */
+#define INTC_ID_TMOI2 (212) /* */
+#define INTC_ID_TEI3 (213) /* */
+#define INTC_ID_RI3 (214) /* */
+#define INTC_ID_TI3 (215) /* */
+#define INTC_ID_SPI3 (216) /* */
+#define INTC_ID_STI3 (217) /* */
+#define INTC_ID_NAKI3 (218) /* */
+#define INTC_ID_ALI3 (219) /* */
+#define INTC_ID_TMOI3 (220) /* */
+#define INTC_ID_BRI0 (221)
+#define INTC_ID_ERI0 (222) /* */
+#define INTC_ID_RXI0 (223) /* */
+#define INTC_ID_TXI0 (224) /* */
+#define INTC_ID_BRI1 (225) /* */
+#define INTC_ID_ERI1 (226) /* */
+#define INTC_ID_RXI1 (227) /* */
+#define INTC_ID_TXI1 (228) /* */
+#define INTC_ID_BRI2 (229) /* */
+#define INTC_ID_ERI2 (230) /* */
+#define INTC_ID_RXI2 (231) /* */
+#define INTC_ID_TXI2 (232) /* */
+#define INTC_ID_BRI3 (233) /* */
+#define INTC_ID_ERI3 (234) /* */
+#define INTC_ID_RXI3 (235) /* */
+#define INTC_ID_TXI3 (236) /* */
+#define INTC_ID_BRI4 (237) /* */
+#define INTC_ID_ERI4 (238) /* */
+#define INTC_ID_RXI4 (239) /* */
+#define INTC_ID_TXI4 (240) /* */
+#define INTC_ID_BRI5 (241) /* */
+#define INTC_ID_ERI5 (242) /* */
+#define INTC_ID_RXI5 (243) /* */
+#define INTC_ID_TXI5 (244) /* */
+#define INTC_ID_BRI6 (245) /* */
+#define INTC_ID_ERI6 (246) /* */
+#define INTC_ID_RXI6 (247) /* */
+#define INTC_ID_TXI6 (248) /* */
+#define INTC_ID_BRI7 (249) /* */
+#define INTC_ID_ERI7 (250) /* */
+#define INTC_ID_RXI7 (251) /* */
+#define INTC_ID_TXI7 (252) /* */
+#define INTC_ID_GERI (253)
+#define INTC_ID_RFI (254) /* */
+#define INTC_ID_CFRXI0 (255) /* */
+#define INTC_ID_CERI0 (256) /* */
+#define INTC_ID_CTXI0 (257) /* */
+#define INTC_ID_CFRXI1 (258) /* */
+#define INTC_ID_CERI1 (259) /* */
+#define INTC_ID_CTXI1 (260) /* */
+#define INTC_ID_CFRXI2 (261) /* */
+#define INTC_ID_CERI2 (262) /* */
+#define INTC_ID_CTXI2 (263) /* */
+#define INTC_ID_CFRXI3 (264) /* */
+#define INTC_ID_CERI3 (265) /* */
+#define INTC_ID_CTXI3 (266) /* */
+#define INTC_ID_CFRXI4 (267) /* */
+#define INTC_ID_CERI4 (268) /* */
+#define INTC_ID_CTXI4 (269) /* */
+#define INTC_ID_SPEI0 (270)
+#define INTC_ID_SPRI0 (271) /* */
+#define INTC_ID_SPTI0 (272) /* */
+#define INTC_ID_SPEI1 (273) /* */
+#define INTC_ID_SPRI1 (274) /* */
+#define INTC_ID_SPTI1 (275) /* */
+#define INTC_ID_SPEI2 (276) /* */
+#define INTC_ID_SPRI2 (277) /* */
+#define INTC_ID_SPTI2 (278) /* */
+#define INTC_ID_SPEI3 (279) /* */
+#define INTC_ID_SPRI3 (280) /* */
+#define INTC_ID_SPTI3 (281) /* */
+#define INTC_ID_SPEI4 (282) /* */
+#define INTC_ID_SPRI4 (283) /* */
+#define INTC_ID_SPTI4 (284) /* */
+#define INTC_ID_IEBBTD (285)
+#define INTC_ID_IEBBTERR (286) /* */
+#define INTC_ID_IEBBTSTA (287) /* */
+#define INTC_ID_IEBBTV (288) /* */
+#define INTC_ID_ISY (289)
+#define INTC_ID_IERR (290) /* */
+#define INTC_ID_ITARG (291) /* */
+#define INTC_ID_ISEC (292) /* */
+#define INTC_ID_IBUF (293) /* */
+#define INTC_ID_IREADY (294) /* */
+#define INTC_ID_FLSTE (295)
+#define INTC_ID_FLTENDI (296) /* */
+#define INTC_ID_FLTREQ0I (297) /* */
+#define INTC_ID_FLTREQ1I (298) /* */
+#define INTC_ID_MMC0 (299)
+#define INTC_ID_MMC1 (300) /* */
+#define INTC_ID_MMC2 (301) /* */
+#define INTC_ID_SDHI0_3 (302)
+#define INTC_ID_SDHI0_0 (303) /* */
+#define INTC_ID_SDHI0_1 (304) /* */
+#define INTC_ID_SDHI1_3 (305) /* */
+#define INTC_ID_SDHI1_0 (306) /* */
+#define INTC_ID_SDHI1_1 (307) /* */
+#define INTC_ID_ARM (308)
+#define INTC_ID_PRD (309) /* */
+#define INTC_ID_CUP (310) /* */
+#define INTC_ID_SCUAI0 (311) /* SCUX */
+#define INTC_ID_SCUAI1 (312) /* */
+#define INTC_ID_SCUFDI0 (313) /* */
+#define INTC_ID_SCUFDI1 (314) /* */
+#define INTC_ID_SCUFDI2 (315) /* */
+#define INTC_ID_SCUFDI3 (316) /* */
+#define INTC_ID_SCUFUI0 (317) /* */
+#define INTC_ID_SCUFUI1 (318) /* */
+#define INTC_ID_SCUFUI2 (319) /* */
+#define INTC_ID_SCUFUI3 (320) /* */
+#define INTC_ID_SCUDVI0 (321) /* */
+#define INTC_ID_SCUDVI1 (322) /* */
+#define INTC_ID_SCUDVI2 (323) /* */
+#define INTC_ID_SCUDVI3 (324) /* */
+#define INTC_ID_MLBCI (325)
+#define INTC_ID_MLBSI (326) /* */
+#define INTC_ID_DRC0 (327)
+#define INTC_ID_DRC1 (328) /* */
+#define INTC_ID_LINI0_INT_T (331) /* Renesas LIN3 */
+#define INTC_ID_LINI0_INT_R (332) /* */
+#define INTC_ID_LINI0_INT_S (333) /* */
+#define INTC_ID_LINI0_INT_M (334) /* */
+#define INTC_ID_LINI1_INT_T (335) /* */
+#define INTC_ID_LINI1_INT_R (336) /* */
+#define INTC_ID_LINI1_INT_S (337) /* */
+#define INTC_ID_LINI1_INT_M (338) /* */
+#define INTC_ID_SCI_ERI0 (347)
+#define INTC_ID_SCI_RXI0 (348) /* */
+#define INTC_ID_SCI_TXI0 (349) /* */
+#define INTC_ID_SCI_TEI0 (350) /* */
+#define INTC_ID_SCI_ERI1 (351) /* */
+#define INTC_ID_SCI_RXI1 (352) /* */
+#define INTC_ID_SCI_TXI1 (353) /* */
+#define INTC_ID_SCI_TEI1 (354) /* */
+#define INTC_ID_ETHERI (359)
+#define INTC_ID_CEUI (364)
+#define INTC_ID_H2XMLB_ERRINT (381)
+#define INTC_ID_H2XIC1_ERRINT (382) /* */
+#define INTC_ID_X2HPERI1_ERRINT (383) /* */
+#define INTC_ID_X2HPERI2_ERRINT (384) /* */
+#define INTC_ID_X2HPERI34_ERRINT (385) /* */
+#define INTC_ID_X2HPERI5_ERRINT (386) /* */
+#define INTC_ID_X2HPERI67_ERRINT (387) /* */
+#define INTC_ID_X2HDBGR_ERRINT (388) /* */
+#define INTC_ID_X2HBSC_ERRINT (389) /* */
+#define INTC_ID_X2HSPI1_ERRINT (390) /* */
+#define INTC_ID_X2HSPI2_ERRINT (391) /* */
+#define INTC_ID_PRRI (392) /* */
+#define INTC_ID_IFEI0 (393)
+#define INTC_ID_OFFI0 (394) /* */
+#define INTC_ID_PFVEI0 (395) /* */
+#define INTC_ID_IFEI1 (396) /* */
+#define INTC_ID_OFFI1 (397) /* */
+#define INTC_ID_PFVEI1 (398) /* */
+#define INTC_ID_TINT0 (416)
+#define INTC_ID_TINT1 (417) /* */
+#define INTC_ID_TINT2 (418) /* */
+#define INTC_ID_TINT3 (419) /* */
+#define INTC_ID_TINT4 (420) /* */
+#define INTC_ID_TINT5 (421) /* */
+#define INTC_ID_TINT6 (422) /* */
+#define INTC_ID_TINT7 (423) /* */
+#define INTC_ID_TINT8 (424) /* */
+#define INTC_ID_TINT9 (425) /* */
+#define INTC_ID_TINT10 (426) /* */
+#define INTC_ID_TINT11 (427) /* */
+#define INTC_ID_TINT12 (428) /* */
+#define INTC_ID_TINT13 (429) /* */
+#define INTC_ID_TINT14 (430) /* */
+#define INTC_ID_TINT15 (431) /* */
+#define INTC_ID_TINT16 (432) /* */
+#define INTC_ID_TINT17 (433) /* */
+#define INTC_ID_TINT18 (434) /* */
+#define INTC_ID_TINT19 (435) /* */
+#define INTC_ID_TINT20 (436) /* */
+#define INTC_ID_TINT21 (437) /* */
+#define INTC_ID_TINT22 (438) /* */
+#define INTC_ID_TINT23 (439) /* */
+#define INTC_ID_TINT24 (440) /* */
+#define INTC_ID_TINT25 (441) /* */
+#define INTC_ID_TINT26 (442) /* */
+#define INTC_ID_TINT27 (443) /* */
+#define INTC_ID_TINT28 (444) /* */
+#define INTC_ID_TINT29 (445) /* */
+#define INTC_ID_TINT30 (446) /* */
+#define INTC_ID_TINT31 (447) /* */
+#define INTC_ID_TINT32 (448) /* */
+#define INTC_ID_TINT33 (449) /* */
+#define INTC_ID_TINT34 (450) /* */
+#define INTC_ID_TINT35 (451) /* */
+#define INTC_ID_TINT36 (452) /* */
+#define INTC_ID_TINT37 (453) /* */
+#define INTC_ID_TINT38 (454) /* */
+#define INTC_ID_TINT39 (455) /* */
+#define INTC_ID_TINT40 (456) /* */
+#define INTC_ID_TINT41 (457) /* */
+#define INTC_ID_TINT42 (458) /* */
+#define INTC_ID_TINT43 (459) /* */
+#define INTC_ID_TINT44 (460) /* */
+#define INTC_ID_TINT45 (461) /* */
+#define INTC_ID_TINT46 (462) /* */
+#define INTC_ID_TINT47 (463) /* */
+#define INTC_ID_TINT48 (464) /* */
+#define INTC_ID_TINT49 (465) /* */
+#define INTC_ID_TINT50 (466) /* */
+#define INTC_ID_TINT51 (467) /* */
+#define INTC_ID_TINT52 (468) /* */
+#define INTC_ID_TINT53 (469) /* */
+#define INTC_ID_TINT54 (470) /* */
+#define INTC_ID_TINT55 (471) /* */
+#define INTC_ID_TINT56 (472) /* */
+#define INTC_ID_TINT57 (473) /* */
+#define INTC_ID_TINT58 (474) /* */
+#define INTC_ID_TINT59 (475) /* */
+#define INTC_ID_TINT60 (476) /* */
+#define INTC_ID_TINT61 (477) /* */
+#define INTC_ID_TINT62 (478) /* */
+#define INTC_ID_TINT63 (479) /* */
+#define INTC_ID_TINT64 (480) /* */
+#define INTC_ID_TINT65 (481) /* */
+#define INTC_ID_TINT66 (482) /* */
+#define INTC_ID_TINT67 (483) /* */
+#define INTC_ID_TINT68 (484) /* */
+#define INTC_ID_TINT69 (485) /* */
+#define INTC_ID_TINT70 (486) /* */
+#define INTC_ID_TINT71 (487) /* */
+#define INTC_ID_TINT72 (488) /* */
+#define INTC_ID_TINT73 (489) /* */
+#define INTC_ID_TINT74 (490) /* */
+#define INTC_ID_TINT75 (491) /* */
+#define INTC_ID_TINT76 (492) /* */
+#define INTC_ID_TINT77 (493) /* */
+#define INTC_ID_TINT78 (494) /* */
+#define INTC_ID_TINT79 (495) /* */
+#define INTC_ID_TINT80 (496) /* */
+#define INTC_ID_TINT81 (497) /* */
+#define INTC_ID_TINT82 (498) /* */
+#define INTC_ID_TINT83 (499) /* */
+#define INTC_ID_TINT84 (500) /* */
+#define INTC_ID_TINT85 (501) /* */
+#define INTC_ID_TINT86 (502) /* */
+#define INTC_ID_TINT87 (503) /* */
+#define INTC_ID_TINT88 (504) /* */
+#define INTC_ID_TINT89 (505) /* */
+#define INTC_ID_TINT90 (506) /* */
+#define INTC_ID_TINT91 (507) /* */
+#define INTC_ID_TINT92 (508) /* */
+#define INTC_ID_TINT93 (509) /* */
+#define INTC_ID_TINT94 (510) /* */
+#define INTC_ID_TINT95 (511) /* */
+#define INTC_ID_TINT96 (512) /* */
+#define INTC_ID_TINT97 (513) /* */
+#define INTC_ID_TINT98 (514) /* */
+#define INTC_ID_TINT99 (515) /* */
+#define INTC_ID_TINT100 (516) /* */
+#define INTC_ID_TINT101 (517) /* */
+#define INTC_ID_TINT102 (518) /* */
+#define INTC_ID_TINT103 (519) /* */
+#define INTC_ID_TINT104 (520) /* */
+#define INTC_ID_TINT105 (521) /* */
+#define INTC_ID_TINT106 (522) /* */
+#define INTC_ID_TINT107 (523) /* */
+#define INTC_ID_TINT108 (524) /* */
+#define INTC_ID_TINT109 (525) /* */
+#define INTC_ID_TINT110 (526) /* */
+#define INTC_ID_TINT111 (527) /* */
+#define INTC_ID_TINT112 (528) /* */
+#define INTC_ID_TINT113 (529) /* */
+#define INTC_ID_TINT114 (530) /* */
+#define INTC_ID_TINT115 (531) /* */
+#define INTC_ID_TINT116 (532) /* */
+#define INTC_ID_TINT117 (533) /* */
+#define INTC_ID_TINT118 (534) /* */
+#define INTC_ID_TINT119 (535) /* */
+#define INTC_ID_TINT120 (536) /* */
+#define INTC_ID_TINT121 (537) /* */
+#define INTC_ID_TINT122 (538) /* */
+#define INTC_ID_TINT123 (539) /* */
+#define INTC_ID_TINT124 (540) /* */
+#define INTC_ID_TINT125 (541) /* */
+#define INTC_ID_TINT126 (542) /* */
+#define INTC_ID_TINT127 (543) /* */
+#define INTC_ID_TINT128 (544) /* */
+#define INTC_ID_TINT129 (545) /* */
+#define INTC_ID_TINT130 (546) /* */
+#define INTC_ID_TINT131 (547) /* */
+#define INTC_ID_TINT132 (548) /* */
+#define INTC_ID_TINT133 (549) /* */
+#define INTC_ID_TINT134 (550) /* */
+#define INTC_ID_TINT135 (551) /* */
+#define INTC_ID_TINT136 (552) /* */
+#define INTC_ID_TINT137 (553) /* */
+#define INTC_ID_TINT138 (554) /* */
+#define INTC_ID_TINT139 (555) /* */
+#define INTC_ID_TINT140 (556) /* */
+#define INTC_ID_TINT141 (557) /* */
+#define INTC_ID_TINT142 (558) /* */
+#define INTC_ID_TINT143 (559) /* */
+#define INTC_ID_TINT144 (560) /* */
+#define INTC_ID_TINT145 (561) /* */
+#define INTC_ID_TINT146 (562) /* */
+#define INTC_ID_TINT147 (563) /* */
+#define INTC_ID_TINT148 (564) /* */
+#define INTC_ID_TINT149 (565) /* */
+#define INTC_ID_TINT150 (566) /* */
+#define INTC_ID_TINT151 (567) /* */
+#define INTC_ID_TINT152 (568) /* */
+#define INTC_ID_TINT153 (569) /* */
+#define INTC_ID_TINT154 (570) /* */
+#define INTC_ID_TINT155 (571) /* */
+#define INTC_ID_TINT156 (572) /* */
+#define INTC_ID_TINT157 (573) /* */
+#define INTC_ID_TINT158 (574) /* */
+#define INTC_ID_TINT159 (575) /* */
+#define INTC_ID_TINT160 (576) /* */
+#define INTC_ID_TINT161 (577) /* */
+#define INTC_ID_TINT162 (578) /* */
+#define INTC_ID_TINT163 (579) /* */
+#define INTC_ID_TINT164 (580) /* */
+#define INTC_ID_TINT165 (581) /* */
+#define INTC_ID_TINT166 (582) /* */
+#define INTC_ID_TINT167 (583) /* */
+#define INTC_ID_TINT168 (584) /* */
+#define INTC_ID_TINT169 (585) /* */
+#define INTC_ID_TINT170 (586) /* */
+
+#define INTC_LEVEL_SENSITIVE (0)
+#define INTC_EDGE_TRIGGER (1)
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+int32_t R_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense));
+void R_INTC_Init(void);
+int32_t R_INTC_Enable(uint16_t int_id);
+int32_t R_INTC_Disable(uint16_t int_id);
+int32_t R_INTC_SetPriority(uint16_t int_id, uint8_t priority);
+int32_t R_INTC_SetMaskLevel(uint8_t mask_level);
+void R_INTC_GetMaskLevel(uint8_t * mask_level);
+
+void Userdef_INTC_RegistIntFunc(uint16_t int_id, void (* func)(uint32_t int_sense));
+void Userdef_INTC_UndefId(uint16_t int_id);
+void Userdef_INTC_HandlerExe(uint16_t int_id, uint32_t int_sense);
+void Userdef_FIQ_HandlerExe(void);
+
+#endif /* _DEVDRV_INTC_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_ostm.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_ostm.h
new file mode 100644
index 000000000..d5921380d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_ostm.h
@@ -0,0 +1,69 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : devdrv_ostm.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - OS timer device driver header
+******************************************************************************/
+#ifndef _DEVDRV_OSTM_H_
+#define _DEVDRV_OSTM_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define OSTM_MODE_INTERVAL (0)
+#define OSTM_MODE_COMPARE (1)
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+int32_t R_OSTM_Init(uint32_t channel, uint32_t mode, uint32_t cycle);
+int32_t R_OSTM_Open(uint32_t channel);
+int32_t R_OSTM_Close(uint32_t channel, uint32_t * count);
+int32_t R_OSTM_Interrupt(uint32_t channel);
+
+int32_t Userdef_OSTM0_Init(uint32_t mode, uint32_t cycle);
+int32_t Userdef_OSTM1_Init(uint32_t mode, uint32_t cycle);
+void Userdef_OSTM0_Int(void);
+void Userdef_OSTM1_Int(void);
+void Userdef_OSTM0_WaitInt(void);
+void Userdef_OSTM1_WaitInt(void);
+
+#endif /* _DEVDRV_OSTM_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_scif_uart.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_scif_uart.h
new file mode 100644
index 000000000..91b9cd9d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/devdrv_scif_uart.h
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : scif_uart.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - SCIF UART device driver header
+******************************************************************************/
+#ifndef _DEVDRV_SCIF_UART_H_
+#define _DEVDRV_SCIF_UART_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include "iodefine.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define SCIF_UART_MODE_W (1)
+#define SCIF_UART_MODE_R (2)
+#define SCIF_UART_MODE_RW (3)
+
+typedef enum scif_cks_division
+{
+ SCIF_CKS_DIVISION_1,
+ SCIF_CKS_DIVISION_4,
+ SCIF_CKS_DIVISION_16,
+ SCIF_CKS_DIVISION_64
+} scif_cks_division_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+int32_t R_SCIF_UART_Init(uint32_t channel, uint32_t mode, uint16_t cks, uint8_t scbrr);
+
+void Userdef_SCIF2_UART_Init(uint8_t mode, uint16_t cks, uint8_t scbrr);
+
+#endif /* _DEVDRV_SCIF_UART_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefine.h
new file mode 100644
index 000000000..828a97b7c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefine.h
@@ -0,0 +1,13969 @@
+/*******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2010(2011) Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name : SH7269 Sample Program
+* File Name : iodefine.h
+* Abstract : SH7269 IO define file
+* Version : 0.11.00
+* Device : SH7269
+
+* Tool-Chain : High-performance Embedded Workshop (Ver.4.07.00).
+* : C/C++ compiler package for the SuperH RISC engine family
+* : (Ver.9.03 Release02).
+* OS : None
+* H/W Platform: R0K57269(CPU board)
+* Description :
+********************************************************************************
+* History : Sep.02,2010 Ver.0.01.00 Preliminary version issued
+* : Oct.06.2010 Ver.0.02.00 VDC4.GR1_AB1 modified
+* : Oct.07.2010 Ver.0.03.00 VDC4.GR1_AB1 type definition modified
+* : Oct.19.2010 Ver.0.04.00 MMC.CE_DMA_MODE added
+* MMC.CE_BOOT deleted
+* : Nov.09.2010 Ver.0.05.00 VDC4.GR3_CLUT_INT.GR3_LINE added
+* : Jan.28.2011 Ver.0.06.00 DVDEC.ADDCR->ADCCR1 changed
+* DVDEC.ADCCR1.AGCMODEXA->AGCMODE changed
+* DVDEC.INSCR deleted
+* DVDEC.AGCCR2.AGCMAXGAIN deleted
+* DVDEC.AGCCR2.VIDEOGAIN deleted
+* DVDEC.AGCCR2.VIDEOGAIN deleted
+* DVDEC.CROMASR2.NCOMODE deleted
+* DVDEC.DCPSR3~5 deleted
+* DVDEC.YCSCR1 deleted
+* DVDEC.YCSCR3~7,9,11 added
+* DVDEC.YCSCR8.HFIL_TAP_SEL added
+* DVDEC.YCSCR12.DET2_MIX_C added
+* DVDEC.YCSCR12.DET2_MIX_Y added
+* DVDEC.DCPCR9.CLP_FIL_SEL deleted
+* DVDEC.DCPCR10~13 deleted
+* DVDEC.PGA_UPDATE added
+* DVDEC.PGACR added
+* DVDEC.ADCCR2 added
+* module SPIBSC added
+* : Feb.23.2011 Ver.0.07.00 CPG.STBCR7.MSTP75 added
+* : Feb.28.2011 Ver.0.08.00 PORT.PBCR5 modified
+* PORT.PBCR4 modified
+* PORT.PBCR3 modified
+* JCU.JCSTS deleted
+* VDC4.INP_SEL_CNT.INP_VSP_SYNC_SEL deleted
+* VDC4.SCL0_DS4.RES_DS_H_INIPHASE deleted
+* VDC4.GR1_AB1.GR1_ARC_ON deleted
+* VDC4.GR1_AB1.GR1_ARC_DISP_ON deleted
+* VDC4.GR1_AB4 deleted
+* VDC4.GR1_AB5 deleted
+* VDC4.GR1_AB6 deleted
+* VDC4.GR1_AB7.GR1_ARC_DEF deleted
+* VDC4.GR1_MON deleted
+* VDC4.ADJ_MTX_MODE.MTX_MD->ADJ_MTX_MD changed
+* VDC4.OUT_SET.OUT_PIXEL_INV_ON deleted
+* VDC4.OUT_SET.OUT_SUM_MOVE deleted
+* : Mar.02.2011 Ver.0.09.00 JCU.JCQTBL0 modified
+* JCU.JCQTBL1 modified
+* JCU.JCQTBL2 modified
+* JCU.JCQTBL3 modified
+* JCU.JCHTBD0 modified
+* JCU.JCHTBA0 modified
+* JCU.JCHTBD1 modified
+* JCU.JCHTBA1 modified
+* : Apr.04.2011 Ver.0.10.00 CPG.SWRSTCR2.JCUSRST added
+* : May.09.2011 Ver.0.11.00 BSC.ACSWR deleted
+* BSC.ACKEYR deleted
+* USB.USBACSWR1 deleted
+*******************************************************************************/
+#ifndef _IODEFINE_H_
+#define _IODEFINE_H_
+
+#include "typedefine.h"
+
+/* new iodefine ADC */
+
+struct st_adc
+{ /* ADC */
+ unsigned short DRA; /* DRA */
+ unsigned short DRB; /* DRB */
+ unsigned short DRC; /* DRC */
+ unsigned short DRD; /* DRD */
+ unsigned short DRE; /* DRE */
+ unsigned short DRF; /* DRF */
+ unsigned short DRG; /* DRG */
+ unsigned short DRH; /* DRH */
+ unsigned char dummy32[16]; /* */
+ unsigned short MPHA; /* MPHA */
+ unsigned short MPLA; /* MPLA */
+ unsigned short MPHB; /* MPHB */
+ unsigned short MPLB; /* MPLB */
+ unsigned short MPHC; /* MPHC */
+ unsigned short MPLC; /* MPLC */
+ unsigned short MPHD; /* MPHD */
+ unsigned short MPLD; /* MPLD */
+ unsigned short MPHE; /* MPHE */
+ unsigned short MPLE; /* MPLE */
+ unsigned short MPHF; /* MPHF */
+ unsigned short MPLF; /* MPLF */
+ unsigned short MPHG; /* MPHG */
+ unsigned short MPLG; /* MPLG */
+ unsigned short MPHH; /* MPHH */
+ unsigned short MPLH; /* MPLH */
+ unsigned char dummy33[32]; /* */
+ unsigned short SR; /* SR */
+ unsigned short MPER; /* MPER */
+ unsigned short MPSR; /* MPSR */
+};
+
+#define ADCDRA ADC.DRA
+#define ADCDRB ADC.DRB
+#define ADCDRC ADC.DRC
+#define ADCDRD ADC.DRD
+#define ADCDRE ADC.DRE
+#define ADCDRF ADC.DRF
+#define ADCDRG ADC.DRG
+#define ADCDRH ADC.DRH
+#define ADCMPHA ADC.MPHA
+#define ADCMPLA ADC.MPLA
+#define ADCMPHB ADC.MPHB
+#define ADCMPLB ADC.MPLB
+#define ADCMPHC ADC.MPHC
+#define ADCMPLC ADC.MPLC
+#define ADCMPHD ADC.MPHD
+#define ADCMPLD ADC.MPLD
+#define ADCMPHE ADC.MPHE
+#define ADCMPLE ADC.MPLE
+#define ADCMPHF ADC.MPHF
+#define ADCMPLF ADC.MPLF
+#define ADCMPHG ADC.MPHG
+#define ADCMPLG ADC.MPLG
+#define ADCMPHH ADC.MPHH
+#define ADCMPLH ADC.MPLH
+#define ADCSR ADC.SR
+#define ADCMPER ADC.MPER
+#define ADCMPSR ADC.MPSR
+
+#define ADC (*(volatile struct st_adc *)0xE8005800) /* ADC */
+
+/* new iodefine ADC */
+
+
+ #if 0
+struct st_cpg { /* struct CPG */
+ union { /* FRQCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD CKOEN2:1; /* CKOEN2 */
+ _UWORD CKOEN:2; /* CKOEN */
+ _UWORD :2; /* */
+ _UWORD IFC:2; /* IFC */
+ _UWORD :2; /* */
+ _UWORD BFC:2; /* BFC */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } FRQCR; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* STBCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE STBY:1; /* STBY */
+ _UBYTE DEEP:1; /* DEEP */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } STBCR1; /* */
+ _UBYTE wk1[3]; /* */
+ union { /* STBCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP10:1; /* MSTP10 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP8:1; /* MSTP8 */
+ _UBYTE MSTP7:1; /* MSTP7 */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } STBCR2; /* */
+ _UBYTE wk2[999]; /* */
+ union { /* SYSCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE RAME3:1; /* RAME3 */
+ _UBYTE RAME2:1; /* RAME2 */
+ _UBYTE RAME1:1; /* RAME1 */
+ _UBYTE RAME0:1; /* RAME0 */
+ } BIT; /* */
+ } SYSCR1; /* */
+ _UBYTE wk3[3]; /* */
+ union { /* SYSCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE RAMWE3:1; /* RAMWE3 */
+ _UBYTE RAMWE2:1; /* RAMWE2 */
+ _UBYTE RAMWE1:1; /* RAMWE1 */
+ _UBYTE RAMWE0:1; /* RAMWE0 */
+ } BIT; /* */
+ } SYSCR2; /* */
+ _UBYTE wk4[3]; /* */
+ union { /* STBCR3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE HIZ:1; /* HIZ */
+ _UBYTE MSTP36:1; /* MSTP36 */
+ _UBYTE MSTP35:1; /* MSTP35 */
+ _UBYTE :1; /* MSTP34 */
+ _UBYTE :1; /* MSTP33 */
+ _UBYTE MSTP32:1; /* MSTP32 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP30:1; /* MSTP30 */
+ } BIT; /* */
+ } STBCR3; /* */
+ _UBYTE wk5[3]; /* */
+ union { /* STBCR4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP47:1; /* MSTP47 */
+ _UBYTE MSTP46:1; /* MSTP46 */
+ _UBYTE MSTP45:1; /* MSTP45 */
+ _UBYTE MSTP44:1; /* MSTP44 */
+ _UBYTE MSTP43:1; /* MSTP43 */
+ _UBYTE MSTP42:1; /* MSTP42 */
+ _UBYTE MSTP41:1; /* MSTP41 */
+ _UBYTE MSTP40:1; /* MSTP40 */
+ } BIT; /* */
+ } STBCR4; /* */
+ _UBYTE wk6[3]; /* */
+ union { /* STBCR5 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP57:1; /* MSTP57 */
+ _UBYTE MSTP56:1; /* MSTP56 */
+ _UBYTE MSTP55:1; /* MSTP55 */
+ _UBYTE MSTP54:1; /* MSTP54 */
+ _UBYTE MSTP53:1; /* MSTP53 */
+ _UBYTE MSTP52:1; /* MSTP52 */
+ _UBYTE MSTP51:1; /* MSTP51 */
+ _UBYTE MSTP50:1; /* MSTP50 */
+ } BIT; /* */
+ } STBCR5; /* */
+ _UBYTE wk7[3]; /* */
+ union { /* STBCR6 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP67:1; /* MSTP67 */
+ _UBYTE MSTP66:1; /* MSTP66 */
+ _UBYTE MSTP65:1; /* MSTP65 */
+ _UBYTE MSTP64:1; /* MSTP64 */
+ _UBYTE MSTP63:1; /* MSTP63 */
+ _UBYTE MSTP62:1; /* MSTP62 */
+ _UBYTE MSTP61:1; /* MSTP61 */
+ _UBYTE MSTP60:1; /* MSTP60 */
+ } BIT; /* */
+ } STBCR6; /* */
+ _UBYTE wk8[3]; /* */
+ union { /* STBCR7 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP77:1; /* MSTP77 */
+ _UBYTE MSTP76:1; /* MSTP76 */
+ _UBYTE MSTP75:1; /* MSTP75 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP73:1; /* MSTP73 */
+ _UBYTE MSTP72:1; /* MSTP72 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP70:1; /* MSTP70 */
+ } BIT; /* */
+ } STBCR7; /* */
+ _UBYTE wk9[3]; /* */
+ union { /* STBCR8 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP87:1; /* MSTP87 */
+ _UBYTE MSTP86:1; /* MSTP86 */
+ _UBYTE MSTP85:1; /* MSTP85 */
+ _UBYTE MSTP84:1; /* MSTP84 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP82:1; /* MSTP82 */
+ _UBYTE MSTP81:1; /* MSTP81 */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } STBCR8; /* */
+ _UBYTE wk10[3]; /* */
+ union { /* SYSCR3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE VRAME5:1; /* VRAME5 */
+ _UBYTE VRAME4:1; /* VRAME4 */
+ _UBYTE VRAME3:1; /* VRAME3 */
+ _UBYTE VRAME2:1; /* VRAME2 */
+ _UBYTE VRAME1:1; /* VRAME1 */
+ _UBYTE VRAME0:1; /* VRAME0 */
+ } BIT; /* */
+ } SYSCR3; /* */
+ _UBYTE wk11[3]; /* */
+ union { /* SYSCR4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE VRAMWE5:1; /* VRAMWE5 */
+ _UBYTE VRAMWE4:1; /* VRAMWE4 */
+ _UBYTE VRAMWE3:1; /* VRAMWE3 */
+ _UBYTE VRAMWE2:1; /* VRAMWE2 */
+ _UBYTE VRAMWE1:1; /* VRAMWE1 */
+ _UBYTE VRAMWE0:1; /* VRAMWE0 */
+ } BIT; /* */
+ } SYSCR4; /* */
+ _UBYTE wk12[3]; /* */
+ union { /* SYSCR5 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE RRAMWE3:1; /* RRAMWE3 */
+ _UBYTE RRAMWE2:1; /* RRAMWE2 */
+ _UBYTE RRAMWE1:1; /* RRAMWE1 */
+ _UBYTE RRAMWE0:1; /* RRAMWE0 */
+ } BIT; /* */
+ } SYSCR5; /* */
+ _UBYTE wk13[7]; /* */
+ union { /* SWRSTCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE AXTALE:1; /* AXTALE */
+ _UBYTE SSIF5SRST:1; /* SSIF5SRST */
+ _UBYTE SSIF4SRST:1; /* SSIF4SRST */
+ _UBYTE IEBSRST:1; /* IEBSRST */
+ _UBYTE SSIF3SRST:1; /* SSIF3SRST */
+ _UBYTE SSIF2SRST:1; /* SSIF2SRST */
+ _UBYTE SSIF1SRST:1; /* SSIF1SRST */
+ _UBYTE SSIF0SRST:1; /* SSIF0SRST */
+ } BIT; /* */
+ } SWRSTCR1; /* */
+ _UBYTE wk14[3]; /* */
+ union { /* SWRSTCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :3; /* */
+ _UBYTE JCUSRST:1; /* JCUSRST */
+ _UBYTE RGPVGSRST:1; /* SSIF3SRST */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } SWRSTCR2; /* */
+ _UBYTE wk15[11]; /* */
+ union { /* STBCR9 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP97:1; /* MSTP97 */
+ _UBYTE MSTP96:1; /* MSTP96 */
+ _UBYTE MSTP95:1; /* MSTP95 */
+ _UBYTE MSTP94:1; /* MSTP94 */
+ _UBYTE MSTP93:1; /* MSTP93 */
+ _UBYTE MSTP92:1; /* MSTP92 */
+ _UBYTE MSTP91:1; /* MSTP91 */
+ _UBYTE MSTP90:1; /* MSTP90 */
+ } BIT; /* */
+ } STBCR9; /* */
+ _UBYTE wk16[3]; /* */
+ union { /* STBCR10 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP107:1; /* MSTP107 */
+ _UBYTE MSTP106:1; /* MSTP106 */
+ _UBYTE MSTP105:1; /* MSTP105 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP103:1; /* MSTP103 */
+ _UBYTE MSTP102:1; /* MSTP102 */
+ _UBYTE MSTP101:1; /* MSTP101 */
+ _UBYTE MSTP100:1; /* MSTP100 */
+ } BIT; /* */
+ } STBCR10; /* */
+ _UBYTE wk17[25531]; /* */
+ union { /* RRAMKP */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE RRAMKP3:1; /* RRAMKP3 */
+ _UBYTE RRAMKP2:1; /* RRAMKP2 */
+ _UBYTE RRAMKP1:1; /* RRAMKP1 */
+ _UBYTE RRAMKP0:1; /* RRAMKP0 */
+ } BIT; /* */
+ } RRAMKP; /* */
+ _UBYTE wk18[1]; /* */
+ union { /* DSCTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE EBUSKEEPE:1; /* EBUSKEEPE */
+ _UBYTE RAMBOOT:1; /* RAMBOOT */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } DSCTR; /* */
+ _UBYTE wk19[1]; /* */
+ union { /* DSSSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD PJ23:1; /* PJ23 */
+ _UWORD PJ22:1; /* PJ22 */
+ _UWORD PJ21:1; /* PJ21 */
+ _UWORD PJ20:1; /* PJ20 */
+ _UWORD PG3:1; /* PG3 */
+ _UWORD PG2:1; /* PG2 */
+ _UWORD NMI:1; /* NMI */
+ _UWORD :1; /* */
+ _UWORD RTCAR:1; /* RTCAR */
+ _UWORD PF19:1; /* PF19 */
+ _UWORD PF18:1; /* PF18 */
+ _UWORD PF17:1; /* PF17 */
+ _UWORD PF16:1; /* PF16 */
+ _UWORD PC7:1; /* PC7 */
+ _UWORD PC5:1; /* PC5 */
+ } BIT; /* */
+ } DSSSR; /* */
+ union { /* DSESR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD PJ23E:1; /* PJ23E */
+ _UWORD PJ22E:1; /* PJ22E */
+ _UWORD PJ21E:1; /* PJ21E */
+ _UWORD PJ20E:1; /* PJ20E */
+ _UWORD PG3E:1; /* PG3E */
+ _UWORD PG2E:1; /* PG2E */
+ _UWORD NMIE:1; /* NMIE */
+ _UWORD :1; /* */
+ _UWORD :1; /* */
+ _UWORD PF19E:1; /* PF19E */
+ _UWORD PF18E:1; /* PF18E */
+ _UWORD PF17E:1; /* PF17E */
+ _UWORD PF16E:1; /* PF16E */
+ _UWORD PC7E:1; /* PC7E */
+ _UWORD PC5E:1; /* PC5E */
+ } BIT; /* */
+ } DSESR; /* */
+ union { /* DSFR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD IOKEEP:1; /* IOKEEP */
+ _UWORD PJ23F:1; /* PJ23F */
+ _UWORD PJ22F:1; /* PJ22F */
+ _UWORD PJ21F:1; /* PJ21F */
+ _UWORD PJ20F:1; /* PJ20F */
+ _UWORD PG3F:1; /* PG3F */
+ _UWORD PG2F:1; /* PG2F */
+ _UWORD NMIF:1; /* NMIF */
+ _UWORD :1; /* */
+ _UWORD RTCARF:1; /* RTCARF */
+ _UWORD PF19F:1; /* PF19F */
+ _UWORD PF18F:1; /* PF18F */
+ _UWORD PF17F:1; /* PF17F */
+ _UWORD PF16F:1; /* PF16F */
+ _UWORD PC7F:1; /* PC7F */
+ _UWORD PC5F:1; /* PC5F */
+ } BIT; /* */
+ } DSFR; /* */
+ _UBYTE wk20[6]; /* */
+ union { /* XTALCTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE GAIN:1; /* GAIN */
+ } BIT; /* */
+ } XTALCTR; /* */
+}; /* */
+struct st_intc { /* struct INTC */
+ union { /* ICR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD NMIL:1; /* NMIL */
+ _UWORD :6; /* */
+ _UWORD NMIE:1; /* NMIE */
+ _UWORD :6; /* */
+ _UWORD NMIF:1; /* NMIF */
+ _UWORD NMIM:1; /* NMIM */
+ } BIT; /* */
+ } ICR0; /* */
+ union { /* ICR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD IRQ71S:1; /* IRQ71S */
+ _UWORD IRQ70S:1; /* IRQ70S */
+ _UWORD IRQ61S:1; /* IRQ61S */
+ _UWORD IRQ60S:1; /* IRQ60S */
+ _UWORD IRQ51S:1; /* IRQ51S */
+ _UWORD IRQ50S:1; /* IRQ50S */
+ _UWORD IRQ41S:1; /* IRQ41S */
+ _UWORD IRQ40S:1; /* IRQ40S */
+ _UWORD IRQ31S:1; /* IRQ31S */
+ _UWORD IRQ30S:1; /* IRQ30S */
+ _UWORD IRQ21S:1; /* IRQ21S */
+ _UWORD IRQ20S:1; /* IRQ20S */
+ _UWORD IRQ11S:1; /* IRQ11S */
+ _UWORD IRQ10S:1; /* IRQ10S */
+ _UWORD IRQ01S:1; /* IRQ01S */
+ _UWORD IRQ00S:1; /* IRQ00S */
+ } BIT; /* */
+ } ICR1; /* */
+ union { /* ICR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD PINT7S:1; /* PINT7S */
+ _UWORD PINT6S:1; /* PINT6S */
+ _UWORD PINT5S:1; /* PINT5S */
+ _UWORD PINT4S:1; /* PINT4S */
+ _UWORD PINT3S:1; /* PINT3S */
+ _UWORD PINT2S:1; /* PINT2S */
+ _UWORD PINT1S:1; /* PINT1S */
+ _UWORD PINT0S:1; /* PINT0S */
+ } BIT; /* */
+ } ICR2; /* */
+ union { /* IRQRR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD IRQ7F:1; /* IRQ7F */
+ _UWORD IRQ6F:1; /* IRQ6F */
+ _UWORD IRQ5F:1; /* IRQ5F */
+ _UWORD IRQ4F:1; /* IRQ4F */
+ _UWORD IRQ3F:1; /* IRQ3F */
+ _UWORD IRQ2F:1; /* IRQ2F */
+ _UWORD IRQ1F:1; /* IRQ1F */
+ _UWORD IRQ0F:1; /* IRQ0F */
+ } BIT; /* */
+ } IRQRR; /* */
+ union { /* PINTER */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD PINT7E:1; /* PINT7E */
+ _UWORD PINT6E:1; /* PINT6E */
+ _UWORD PINT5E:1; /* PINT5E */
+ _UWORD PINT4E:1; /* PINT4E */
+ _UWORD PINT3E:1; /* PINT3E */
+ _UWORD PINT2E:1; /* PINT2E */
+ _UWORD PINT1E:1; /* PINT1E */
+ _UWORD PINT0E:1; /* PINT0E */
+ } BIT; /* */
+ } PINTER; /* */
+ union { /* PIRR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD PINT7R:1; /* PINT7R */
+ _UWORD PINT6R:1; /* PINT6R */
+ _UWORD PINT5R:1; /* PINT5R */
+ _UWORD PINT4R:1; /* PINT4R */
+ _UWORD PINT3R:1; /* PINT3R */
+ _UWORD PINT2R:1; /* PINT2R */
+ _UWORD PINT1R:1; /* PINT1R */
+ _UWORD PINT0R:1; /* PINT0R */
+ } BIT; /* */
+ } PIRR; /* */
+ union { /* IBCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD E15:1; /* E15 */
+ _UWORD E14:1; /* E14 */
+ _UWORD E13:1; /* E13 */
+ _UWORD E12:1; /* E12 */
+ _UWORD E11:1; /* E11 */
+ _UWORD E10:1; /* E10 */
+ _UWORD E9:1; /* E9 */
+ _UWORD E8:1; /* E8 */
+ _UWORD E7:1; /* E7 */
+ _UWORD E6:1; /* E6 */
+ _UWORD E5:1; /* E5 */
+ _UWORD E4:1; /* E4 */
+ _UWORD E3:1; /* E3 */
+ _UWORD E2:1; /* E2 */
+ _UWORD E1:1; /* E1 */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } IBCR; /* */
+ union { /* IBNR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BE:2; /* BE */
+ _UWORD BOVE:1; /* BOVE */
+ _UWORD :9; /* */
+ _UWORD BN:4; /* BN */
+ } BIT; /* */
+ } IBNR; /* */
+ _UBYTE wk0[8]; /* */
+ union { /* IPR01 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _IRQ0:4; /* _IRQ0 */
+ _UWORD _IRQ1:4; /* _IRQ1 */
+ _UWORD _IRQ2:4; /* _IRQ2 */
+ _UWORD _IRQ3:4; /* _IRQ3 */
+ } BIT; /* */
+ } IPR01; /* */
+ union { /* IPR02 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _IRQ4:4; /* _IRQ4 */
+ _UWORD _IRQ5:4; /* _IRQ5 */
+ _UWORD _IRQ6:4; /* _IRQ6 */
+ _UWORD _IRQ7:4; /* _IRQ7 */
+ } BIT; /* */
+ } IPR02; /* */
+ _UBYTE wk1[4]; /* */
+ union { /* IPR05 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _PINT:4; /* PINT7-0 */
+ _UWORD :12; /* */
+ } BIT; /* */
+ } IPR05; /* */
+ _UBYTE wk2[990]; /* */
+ union { /* IPR06 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _DMAC0:4; /* _DMAC0 */
+ _UWORD _DMAC1:4; /* _DMAC1 */
+ _UWORD _DMAC2:4; /* _DMAC2 */
+ _UWORD _DMAC3:4; /* _DMAC3 */
+ } BIT; /* */
+ } IPR06; /* */
+ union { /* IPR07 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _DMAC4:4; /* _DMAC4 */
+ _UWORD _DMAC5:4; /* _DMAC5 */
+ _UWORD _DMAC6:4; /* _DMAC6 */
+ _UWORD _DMAC7:4; /* _DMAC7 */
+ } BIT; /* */
+ } IPR07; /* */
+ union { /* IPR08 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _DMAC8:4; /* _DMAC8 */
+ _UWORD _DMAC9:4; /* _DMAC9 */
+ _UWORD _DMAC10:4; /* _DMAC10 */
+ _UWORD _DMAC11:4; /* _DMAC11 */
+ } BIT; /* */
+ } IPR08; /* */
+ union { /* IPR09 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _DMAC12:4; /* _DMAC12 */
+ _UWORD _DMAC13:4; /* _DMAC13 */
+ _UWORD _DMAC14:4; /* _DMAC14 */
+ _UWORD _DMAC15:4; /* _DMAC15 */
+ } BIT; /* */
+ } IPR09; /* */
+ union { /* IPR10 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _USB:4; /* _USB */
+ _UWORD _VDC40:4; /* _VDC40 */
+ _UWORD _VDC41:4; /* _VDC41 */
+ _UWORD _VDC42:4; /* _VDC42 */
+ } BIT; /* */
+ } IPR10; /* */
+ union { /* IPR11 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _IMRLS:4; /* IMRLS */
+ _UWORD _JCU:4; /* JCU */
+ _UWORD _DISCOM:4; /* DISCOM */
+ _UWORD _RGPVG:4; /* RGPVG */
+ } BIT; /* */
+ } IPR11; /* */
+ union { /* IPR12 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _CMT0:4; /* _CMT0 */
+ _UWORD _CMT1:4; /* _CMT1 */
+ _UWORD _BSC:4; /* _BSC */
+ _UWORD _WDT:4; /* _WDT */
+ } BIT; /* */
+ } IPR12; /* */
+ union { /* IPR13 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _MTU00:4; /* _MTU00 */
+ _UWORD _MTU01:4; /* _MTU01 */
+ _UWORD _MTU10:4; /* _MTU10 */
+ _UWORD _MTU11:4; /* _MTU11 */
+ } BIT; /* */
+ } IPR13; /* */
+ union { /* IPR14 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _MTU20:4; /* _MTU20 */
+ _UWORD _MTU21:4; /* _MTU21 */
+ _UWORD _MTU30:4; /* _MTU30 */
+ _UWORD _MTU31:4; /* _MTU31 */
+ } BIT; /* */
+ } IPR14; /* */
+ union { /* IPR15 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _MTU40:4; /* _MTU40 */
+ _UWORD _MTU41:4; /* _MTU41 */
+ _UWORD _PWM1:4; /* _PWM1 */
+ _UWORD _PWM2:4; /* _PWM2 */
+ } BIT; /* */
+ } IPR15; /* */
+ union { /* IPR16 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SDG0:4; /* _SDG0 */
+ _UWORD _SDG1:4; /* _SDG1 */
+ _UWORD _SDG2:4; /* _SDG2 */
+ _UWORD _SDG3:4; /* _SDG3 */
+ } BIT; /* */
+ } IPR16; /* */
+ union { /* IPR17 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _ADC:4; /* _ADC */
+ _UWORD _SSI0:4; /* _SSI0 */
+ _UWORD _SSI1:4; /* _SSI1 */
+ _UWORD _SSI2:4; /* _SSI2 */
+ } BIT; /* */
+ } IPR17; /* */
+ union { /* IPR18 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SSI3:4; /* _SSI3 */
+ _UWORD _SSI4:4; /* _SSI4 */
+ _UWORD _SSI5:4; /* _SSI5 */
+ _UWORD _SPDIF:4; /* _SPDIF */
+ } BIT; /* */
+ } IPR18; /* */
+ union { /* IPR19 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _IIC30:4; /* _IIC30 */
+ _UWORD _IIC31:4; /* _IIC31 */
+ _UWORD _IIC32:4; /* _IIC32 */
+ _UWORD _IIC33:4; /* _IIC33 */
+ } BIT; /* */
+ } IPR19; /* */
+ union { /* IPR20 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SCIF0:4; /* _SCIF0 */
+ _UWORD _SCIF1:4; /* _SCIF1 */
+ _UWORD _SCIF2:4; /* _SCIF2 */
+ _UWORD _SCIF3:4; /* _SCIF3 */
+ } BIT; /* */
+ } IPR20; /* */
+ union { /* IPR21 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SCIF4:4; /* _SCIF4 */
+ _UWORD _SCIF5:4; /* _SCIF5 */
+ _UWORD _SCIF6:4; /* _SCIF6 */
+ _UWORD _SCIF7:4; /* _SCIF7 */
+ } BIT; /* */
+ } IPR21; /* */
+ union { /* IPR22 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SIOF:4; /* _SIOF */
+ _UWORD _RCAN0:4; /* _RCAN0 */
+ _UWORD _RCAN1:4; /* _RCAN1 */
+ _UWORD _RCAN2:4; /* _RCAN2 */
+ } BIT; /* */
+ } IPR22; /* */
+ union { /* IPR23 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _RSPI0:4; /* _RSPI0 */
+ _UWORD _RSPI1:4; /* _RSPI1 */
+ _UWORD _RQSPI0:4; /* _RQSPI0 */
+ _UWORD _RQSPI1:4; /* _RQSPI1 */
+ } BIT; /* */
+ } IPR23; /* */
+ union { /* IPR24 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _IEB:4; /* _IEB */
+ _UWORD _ROMDEC:4; /* _ROMDEC */
+ _UWORD _FLCTL:4; /* _FLCTL */
+ _UWORD _MMC:4; /* _MMC */
+ } BIT; /* */
+ } IPR24; /* */
+ union { /* IPR25 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SDHI0:4; /* _SDHI0 */
+ _UWORD _SDHI1:4; /* _SDHI1 */
+ _UWORD _RTC:4; /* _RTC */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } IPR25; /* */
+ union { /* IPR26 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD _SRC0:4; /* _SRC0 */
+ _UWORD _SRC1:4; /* _SRC1 */
+ _UWORD _SRC2:4; /* _SRC2 */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } IPR26; /* */
+}; /* */
+ #endif
+struct st_ccnt { /* struct CCNT */
+ union { /* CCR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :20; /* */
+ _UDWORD ICF:1; /* ICF */
+ _UDWORD :2; /* */
+ _UDWORD ICE:1; /* ICE */
+ _UDWORD :4; /* */
+ _UDWORD OCF:1; /* OCF */
+ _UDWORD :1; /* */
+ _UDWORD WT:1; /* WT */
+ _UDWORD OCE:1; /* OCE */
+ } BIT; /* */
+ } CCR1; /* */
+ union { /* CCR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :15; /* */
+ _UDWORD LE:1; /* LE */
+ _UDWORD :6; /* */
+ _UDWORD W3LOAD:1; /* W3LOAD */
+ _UDWORD W3LOCK:1; /* W3LOCK */
+ _UDWORD :6; /* */
+ _UDWORD W2LOAD:1; /* W2LOAD */
+ _UDWORD W2LOCK:1; /* W2LOCK */
+ } BIT; /* */
+ } CCR2; /* */
+};
+ #if 0
+union CSnBCR{ /* CSnBCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :1; /* */
+ _UDWORD IWW:3; /* IWW */
+ _UDWORD IWRWD:3; /* IWRWD */
+ _UDWORD IWRWS:3; /* IWRWS */
+ _UDWORD IWRRD:3; /* IWRRD */
+ _UDWORD IWRRS:3; /* IWRRS */
+ _UDWORD :1; /* */
+ _UDWORD TYPE:3; /* TYPE */
+ _UDWORD ENDIAN:1; /* ENDIAN */
+ _UDWORD BSZ:2; /* BSZ */
+ _UDWORD :9; /* */
+ } BIT; /* */
+}; /* */
+struct st_bsc { /* struct BSC */
+ union { /* CMNCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :20; /* */
+ _UDWORD BLOCK:1; /* BLOCK */
+ _UDWORD DPRTY:2; /* DPRTY */
+ _UDWORD DMAIW:3; /* DMAIW */
+ _UDWORD DMAIWA:1; /* DMAIWA */
+ _UDWORD :3; /* */
+ _UDWORD HIZMEM:1; /* HIZMEM */
+ _UDWORD HIZCNT:1; /* HIZCNT */
+ } BIT; /* */
+ } CMNCR; /* */
+ union CSnBCR CS0BCR; /* CS0BCR */
+ union CSnBCR CS1BCR; /* CS1BCR */
+ union CSnBCR CS2BCR; /* CS2BCR */
+ union CSnBCR CS3BCR; /* CS3BCR */
+ union CSnBCR CS4BCR; /* CS4BCR */
+ union CSnBCR CS5BCR; /* CS5BCR */
+ _UBYTE wk0[12]; /* */
+ union { /* CS0WCR */
+ union { /* CS0WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :7; /* */
+ _UDWORD SW:2; /* SW */
+ _UDWORD WR:4; /* WR */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :4; /* */
+ _UDWORD HW:2; /* HW */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS0WCR(BROM_ASY) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :10; /* */
+ _UDWORD BST:2; /* BST */
+ _UDWORD :2; /* */
+ _UDWORD BW:2; /* BW */
+ _UDWORD :5; /* */
+ _UDWORD W:4; /* W */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :6; /* */
+ } BIT; /* */
+ } BROM_ASY; /* */
+ union { /* CS0WCR(BROM_SY) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :14; /* */
+ _UDWORD BW:2; /* BW */
+ _UDWORD :5; /* */
+ _UDWORD W:4; /* W */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :6; /* */
+ } BIT; /* */
+ } BROM_SY; /* */
+ } CS0WCR;
+ union { /* CS1WCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :1; /* */
+ _UDWORD WW:3; /* WW */
+ _UDWORD :3; /* */
+ _UDWORD SW:2; /* SW */
+ _UDWORD WR:4; /* WR */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :4; /* */
+ _UDWORD HW:2; /* HW */
+ } BIT; /* */
+ } CS1WCR; /* */
+ union { /* CS2WCR */
+ union { /* CS2WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :9; /* */
+ _UDWORD WR:4; /* WR */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :6; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS2WCR(SDRAM) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD A2CL:2; /* A2CL */
+ _UDWORD :7; /* */
+ } BIT; /* */
+ } SDRAM; /* */
+ } CS2WCR; /* */
+ union { /* CS3WCR */
+ union { /* CS3WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :9; /* */
+ _UDWORD WR:4; /* WR */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :6; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS3WCR(SDRAM) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :17; /* */
+ _UDWORD WTRP:2; /* WTRP */
+ _UDWORD :1; /* */
+ _UDWORD WTRCD:2; /* WTRCD */
+ _UDWORD :1; /* */
+ _UDWORD A3CL:2; /* A3CL */
+ _UDWORD :2; /* */
+ _UDWORD TRWL:2; /* TRWL */
+ _UDWORD :1; /* */
+ _UDWORD WTRC:2; /* WTRC */
+ } BIT; /* */
+ } SDRAM; /* */
+ } CS3WCR; /* */
+ union { /* CS4WCR */
+ union { /* CS4WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :1; /* */
+ _UDWORD WW:3; /* WW */
+ _UDWORD :3; /* */
+ _UDWORD SW:2; /* SW */
+ _UDWORD WR:4; /* WR */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :4; /* */
+ _UDWORD HW:2; /* HW */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS4WCR(BROM_ASY) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :10; /* */
+ _UDWORD BST:2; /* BST */
+ _UDWORD :2; /* */
+ _UDWORD BW:2; /* BW */
+ _UDWORD :3; /* */
+ _UDWORD SW:2; /* SW */
+ _UDWORD W:4; /* W */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :4; /* */
+ _UDWORD HW:2; /* HW */
+ } BIT; /* */
+ } BROM_ASY; /* */
+ } CS4WCR; /* */
+ union { /* CS5WCR */
+ union { /* CS5WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :10; /* */
+ _UDWORD SZSEL:1; /* SZSEL */
+ _UDWORD MPXWBAS:1; /* MPXW/BAS */
+ _UDWORD :1; /* */
+ _UDWORD WW:3; /* WW */
+ _UDWORD :3; /* */
+ _UDWORD SW:2; /* SW */
+ _UDWORD WR:4; /* WR */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :4; /* */
+ _UDWORD HW:2; /* HW */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS5WCR(PCMCIA) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :10; /* */
+ _UDWORD SA:2; /* SA */
+ _UDWORD :5; /* */
+ _UDWORD TED:4; /* TED */
+ _UDWORD PCW:4; /* PCW */
+ _UDWORD WM:1; /* WM */
+ _UDWORD :2; /* */
+ _UDWORD TEH:4; /* TEH */
+ } BIT; /* */
+ } PCMCIA; /* */
+ } CS5WCR; /* */
+ _UBYTE wk1[12]; /* */
+ union { /* SDCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD A2ROW:2; /* A2ROW */
+ _UDWORD :1; /* */
+ _UDWORD A2COL:2; /* A2COL */
+ _UDWORD :2; /* */
+ _UDWORD DEEP:1; /* DEEP */
+ _UDWORD :1; /* */
+ _UDWORD RFSH:1; /* RFSH */
+ _UDWORD RMODE:1; /* RMODE */
+ _UDWORD PDOWN:1; /* PDOWN */
+ _UDWORD BACTV:1; /* BACTV */
+ _UDWORD :3; /* */
+ _UDWORD A3ROW:2; /* A3ROW */
+ _UDWORD :1; /* */
+ _UDWORD A3COL:2; /* A3COL */
+ } BIT; /* */
+ } SDCR; /* */
+ union { /* RTCSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD CMF:1; /* CMF */
+ _UDWORD CMIE:1; /* CMIE */
+ _UDWORD CKS:3; /* CKS */
+ _UDWORD RRC:3; /* RRC */
+ } BIT; /* */
+ } RTCSR; /* */
+ union { /* RTCNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RTCNT; /* */
+ union { /* RTCOR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RTCOR; /* */
+}; /* */
+struct st_dmac { /* struct DMAC */
+ union { /* SAR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR0; /* */
+ union { /* DAR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR0; /* */
+ union { /* DMATCR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR0; /* */
+ union { /* CHCR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE DO:1; /* DO */
+ _UBYTE TL:1; /* TL */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE AM:1; /* AM */
+ _UBYTE AL:1; /* AL */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE DL:1; /* DL */
+ _UBYTE DS:1; /* DS */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR0; /* */
+ union { /* SAR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR1; /* */
+ union { /* DAR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR1; /* */
+ union { /* DMATCR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR1; /* */
+ union { /* CHCR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :3; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :2; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :2; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR1; /* */
+ union { /* SAR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR2; /* */
+ union { /* DAR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR2; /* */
+ union { /* DMATCR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR2; /* */
+ union { /* CHCR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR2; /* */
+ union { /* SAR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR3; /* */
+ union { /* DAR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR3; /* */
+ union { /* DMATCR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR3; /* */
+ union { /* CHCR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR3; /* */
+ union { /* SAR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR4; /* */
+ union { /* DAR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR4; /* */
+ union { /* DMATCR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR4; /* */
+ union { /* CHCR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR4; /* */
+ union { /* SAR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR5; /* */
+ union { /* DAR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR5; /* */
+ union { /* DMATCR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR5; /* */
+ union { /* CHCR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR5; /* */
+ union { /* SAR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR6; /* */
+ union { /* DAR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR6; /* */
+ union { /* DMATCR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR6; /* */
+ union { /* CHCR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR6; /* */
+ union { /* SAR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR7; /* */
+ union { /* DAR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR7; /* */
+ union { /* DMATCR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR7; /* */
+ union { /* CHCR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR7; /* */
+ union { /* SAR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR8; /* */
+ union { /* DAR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR8; /* */
+ union { /* DMATCR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR8; /* */
+ union { /* CHCR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR8; /* */
+ union { /* SAR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR9; /* */
+ union { /* DAR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR9; /* */
+ union { /* DMATCR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR9; /* */
+ union { /* CHCR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR9; /* */
+ union { /* SAR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR10; /* */
+ union { /* DAR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR10; /* */
+ union { /* DMATCR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR10; /* */
+ union { /* CHCR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR10; /* */
+ union { /* SAR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR11; /* */
+ union { /* DAR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR11; /* */
+ union { /* DMATCR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR11; /* */
+ union { /* CHCR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR11; /* */
+ union { /* SAR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR12; /* */
+ union { /* DAR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR12; /* */
+ union { /* DMATCR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR12; /* */
+ union { /* CHCR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR12; /* */
+ union { /* SAR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR13; /* */
+ union { /* DAR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR13; /* */
+ union { /* DMATCR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR13; /* */
+ union { /* CHCR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR13; /* */
+ union { /* SAR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR14; /* */
+ union { /* DAR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR14; /* */
+ union { /* DMATCR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR14; /* */
+ union { /* CHCR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR14; /* */
+ union { /* SAR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } SAR15; /* */
+ union { /* DAR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DAR15; /* */
+ union { /* DMATCR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } DMATCR15; /* */
+ union { /* CHCR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE TC:1; /* TC */
+ _UBYTE :1; /* */
+ _UBYTE RLDSAR:1; /* RLDSAR */
+ _UBYTE RLDDAR:1; /* RLDDAR */
+ _UBYTE :1; /* */
+ _UBYTE DAF:1; /* DAF */
+ _UBYTE SAF:1; /* SAF */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TEMASK:1; /* TEMASK */
+ _UBYTE HE:1; /* HE */
+ _UBYTE HIE:1; /* HIE */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE DM:2; /* DM */
+ _UBYTE SM:2; /* SM */
+ _UBYTE RS:4; /* RS */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TB:1; /* TB */
+ _UBYTE TS:2; /* TS */
+ _UBYTE IE:1; /* IE */
+ _UBYTE TE:1; /* TE */
+ _UBYTE DE:1; /* DE */
+ } BIT; /* */
+ } CHCR15; /* */
+ union { /* RSAR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR0; /* */
+ union { /* RDAR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR0; /* */
+ union { /* RDMATCR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR0; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* RSAR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR1; /* */
+ union { /* RDAR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR1; /* */
+ union { /* RDMATCR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR1; /* */
+ _UBYTE wk1[4]; /* */
+ union { /* RSAR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR2; /* */
+ union { /* RDAR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR2; /* */
+ union { /* RDMATCR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR2; /* */
+ _UBYTE wk2[4]; /* */
+ union { /* RSAR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR3; /* */
+ union { /* RDAR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR3; /* */
+ union { /* RDMATCR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR3; /* */
+ _UBYTE wk3[4]; /* */
+ union { /* RSAR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR4; /* */
+ union { /* RDAR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR4; /* */
+ union { /* RDMATCR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR4; /* */
+ _UBYTE wk4[4]; /* */
+ union { /* RSAR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR5; /* */
+ union { /* RDAR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR5; /* */
+ union { /* RDMATCR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR5; /* */
+ _UBYTE wk5[4]; /* */
+ union { /* RSAR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR6; /* */
+ union { /* RDAR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR6; /* */
+ union { /* RDMATCR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR6; /* */
+ _UBYTE wk6[4]; /* */
+ union { /* RSAR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR7; /* */
+ union { /* RDAR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR7; /* */
+ union { /* RDMATCR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR7; /* */
+ _UBYTE wk7[4]; /* */
+ union { /* RSAR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR8; /* */
+ union { /* RDAR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR8; /* */
+ union { /* RDMATCR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR8; /* */
+ _UBYTE wk8[4]; /* */
+ union { /* RSAR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR9; /* */
+ union { /* RDAR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR9; /* */
+ union { /* RDMATCR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR9; /* */
+ _UBYTE wk9[4]; /* */
+ union { /* RSAR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR10; /* */
+ union { /* RDAR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR10; /* */
+ union { /* RDMATCR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR10; /* */
+ _UBYTE wk10[4]; /* */
+ union { /* RSAR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR11; /* */
+ union { /* RDAR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR11; /* */
+ union { /* RDMATCR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR11; /* */
+ _UBYTE wk11[4]; /* */
+ union { /* RSAR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR12; /* */
+ union { /* RDAR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR12; /* */
+ union { /* RDMATCR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR12; /* */
+ _UBYTE wk12[4]; /* */
+ union { /* RSAR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR13; /* */
+ union { /* RDAR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR13; /* */
+ union { /* RDMATCR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR13; /* */
+ _UBYTE wk13[4]; /* */
+ union { /* RSAR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR14; /* */
+ union { /* RDAR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR14; /* */
+ union { /* RDMATCR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR14; /* */
+ _UBYTE wk14[4]; /* */
+ union { /* RSAR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RSAR15; /* */
+ union { /* RDAR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDAR15; /* */
+ union { /* RDMATCR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RDMATCR15; /* */
+ _UBYTE wk15[4]; /* */
+ union { /* DMAOR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD CMS:2; /* CMS */
+ _UWORD :2; /* */
+ _UWORD PR:2; /* PR */
+ _UWORD :5; /* */
+ _UWORD AE:1; /* AE */
+ _UWORD NMIF:1; /* NMIF */
+ _UWORD DME:1; /* DME */
+ } BIT; /* */
+ } DMAOR; /* */
+ _UBYTE wk16[254]; /* */
+ union { /* DMARS0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH1:8; /* CH1 */
+ _UWORD CH0:8; /* CH0 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH1MID:6; /* CH1MID */
+ _UWORD CH1RID:2; /* CH1RID */
+ _UWORD CH0MID:6; /* CH0MID */
+ _UWORD CH0RID:2; /* CH0RID */
+ } BIT; /* */
+ } DMARS0; /* */
+ _UBYTE wk17[2]; /* */
+ union { /* DMARS1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH3:8; /* CH3 */
+ _UWORD CH2:8; /* CH2 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH3MID:6; /* CH3ID */
+ _UWORD CH3RID:2; /* CH3RID */
+ _UWORD CH2MID:6; /* CH2MID */
+ _UWORD CH2RID:2; /* CH2RID */
+ } BIT; /* */
+ } DMARS1; /* */
+ _UBYTE wk18[2]; /* */
+ union { /* DMARS2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH5:8; /* CH5 */
+ _UWORD CH4:8; /* CH4 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH5MID:6; /* CH5MID */
+ _UWORD CH5RID:2; /* CH5RID */
+ _UWORD CH4MID:6; /* CH4MID */
+ _UWORD CH4RID:2; /* CH4RID */
+ } BIT; /* */
+ } DMARS2; /* */
+ _UBYTE wk19[2]; /* */
+ union { /* DMARS3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH7:8; /* CH7 */
+ _UWORD CH6:8; /* CH6 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH7MID:6; /* CH7MID */
+ _UWORD CH7RID:2; /* CH7RID */
+ _UWORD CH6MID:6; /* CH6MID */
+ _UWORD CH6RID:2; /* CH6RID */
+ } BIT; /* */
+ } DMARS3; /* */
+ _UBYTE wk20[2]; /* */
+ union { /* DMARS4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH9:8; /* CH9 */
+ _UWORD CH8:8; /* CH8 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH9MID:6; /* CH9MID */
+ _UWORD CH9RID:2; /* CH9RID */
+ _UWORD CH8MID:6; /* CH8MID */
+ _UWORD CH8RID:2; /* CH8RID */
+ } BIT; /* */
+ } DMARS4; /* */
+ _UBYTE wk21[2]; /* */
+ union { /* DMARS5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH11:8; /* CH11 */
+ _UWORD CH10:8; /* CH10 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH11MID:6; /* CH11MID */
+ _UWORD CH11RID:2; /* CH11RID */
+ _UWORD CH10MID:6; /* CH10MID */
+ _UWORD CH10RID:2; /* CH10RID */
+ } BIT; /* */
+ } DMARS5; /* */
+ _UBYTE wk22[2]; /* */
+ union { /* DMARS6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH13:8; /* CH13 */
+ _UWORD CH12:8; /* CH12 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH13MID:6; /* CH13MID */
+ _UWORD CH13RID:2; /* CH13RID */
+ _UWORD CH12MID:6; /* CH12MID */
+ _UWORD CH12RID:2; /* CH12RID */
+ } BIT; /* */
+ } DMARS6; /* */
+ _UBYTE wk23[2]; /* */
+ union { /* DMARS7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UWORD CH15:8; /* CH15 */
+ _UWORD CH14:8; /* CH14 */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD CH15MID:6; /* CH15MID */
+ _UWORD CH15RID:2; /* CH15RID */
+ _UWORD CH14MID:6; /* CH14MID */
+ _UWORD CH14RID:2; /* CH14RID */
+ } BIT; /* */
+ } DMARS7; /* */
+}; /* */
+ #endif
+#if 0
+struct st_mtu2 { /* struct MTU2 */
+ union { /* TCR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE CCLR:2; /* CCLR */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE TPSC:3; /* TPSC */
+ } BIT; /* */
+ } TCR_2; /* */
+ union { /* TMDR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE MD:4; /* MD */
+ } BIT; /* */
+ } TMDR_2; /* */
+ union { /* TIOR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOB:4; /* IOB */
+ _UBYTE IOA:4; /* IOA */
+ } BIT; /* */
+ } TIOR_2; /* */
+ _UBYTE wk0[1]; /* */
+ union { /* TIER_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTGE:1; /* TTGE */
+ _UBYTE :1; /* */
+ _UBYTE TCIEU:1; /* TCIEU */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE :2; /* */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEA:1; /* TGIEA */
+ } BIT; /* */
+ } TIER_2; /* */
+ union { /* TSR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TCFD:1; /* TCFD */
+ _UBYTE :1; /* */
+ _UBYTE TCFU:1; /* TCFU */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFA:1; /* TGFA */
+ } BIT; /* */
+ } TSR_2; /* */
+ union { /* TCNT_2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_2; /* */
+ union { /* TGRA_2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_2; /* */
+ union { /* TGRB_2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_2; /* */
+ _UBYTE wk1[500]; /* */
+ union { /* TCR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CCLR:3; /* CCLR */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE TPSC:3; /* TPSC */
+ } BIT; /* */
+ } TCR_3; /* */
+ union { /* TCR_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CCLR:3; /* CCLR */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE TPSC:3; /* TPSC */
+ } BIT; /* */
+ } TCR_4; /* */
+ union { /* TMDR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE BFB:1; /* BFB */
+ _UBYTE BFA:1; /* BFA */
+ _UBYTE MD:4; /* MD */
+ } BIT; /* */
+ } TMDR_3; /* */
+ union { /* TMDR_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE BFB:1; /* BFB */
+ _UBYTE BFA:1; /* BFA */
+ _UBYTE MD:4; /* MD */
+ } BIT; /* */
+ } TMDR_4; /* */
+ union { /* TIORH_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOB:4; /* IOB */
+ _UBYTE IOA:4; /* IOA */
+ } BIT; /* */
+ } TIORH_3; /* */
+ union { /* TIORL_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOD:4; /* IOD */
+ _UBYTE IOC:4; /* IOC */
+ } BIT; /* */
+ } TIORL_3; /* */
+ union { /* TIORH_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOB:4; /* IOB */
+ _UBYTE IOA:4; /* IOA */
+ } BIT; /* */
+ } TIORH_4; /* */
+ union { /* TIORL_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOD:4; /* IOD */
+ _UBYTE IOC:4; /* IOC */
+ } BIT; /* */
+ } TIORL_4; /* */
+ union { /* TIER_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTGE:1; /* TTGE */
+ _UBYTE :2; /* */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE TGIED:1; /* TGIED */
+ _UBYTE TGIEC:1; /* TGIEC */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEA:1; /* TGIEA */
+ } BIT; /* */
+ } TIER_3; /* */
+ union { /* TIER_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTGE:1; /* TTGE */
+ _UBYTE TTGE2:1; /* TTGE2 */
+ _UBYTE :1; /* */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE TGIED:1; /* TGIED */
+ _UBYTE TGIEC:1; /* TGIEC */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEA:1; /* TGIEA */
+ } BIT; /* */
+ } TIER_4; /* */
+ union { /* TOER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE OE4D:1; /* OE4D */
+ _UBYTE OE4C:1; /* OE4C */
+ _UBYTE OE3D:1; /* OE3D */
+ _UBYTE OE4B:1; /* OE4B */
+ _UBYTE OE4A:1; /* OE4A */
+ _UBYTE OE3B:1; /* OE3B */
+ } BIT; /* */
+ } TOER; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* TGCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE BDC:1; /* BDC */
+ _UBYTE N:1; /* N */
+ _UBYTE P:1; /* P */
+ _UBYTE FB:1; /* FB */
+ _UBYTE WF:1; /* WF */
+ _UBYTE VF:1; /* VF */
+ _UBYTE UF:1; /* UF */
+ } BIT; /* */
+ } TGCR; /* */
+ union { /* TOCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PSYE:1; /* PSYE */
+ _UBYTE :2; /* */
+ _UBYTE TOCL:1; /* TOCL */
+ _UBYTE TOCS:1; /* TOCS */
+ _UBYTE OLSN:1; /* OLSN */
+ _UBYTE OLSP:1; /* OLSP */
+ } BIT; /* */
+ } TOCR1; /* */
+ union { /* TOCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BF:2; /* BF */
+ _UBYTE OLS3N:1; /* OLS3N */
+ _UBYTE OLS3P:1; /* OLS3P */
+ _UBYTE OLS2N:1; /* OLS2N */
+ _UBYTE OLS2P:1; /* OLS2P */
+ _UBYTE OLS1N:1; /* OLS1N */
+ _UBYTE OLS1P:1; /* OLS1P */
+ } BIT; /* */
+ } TOCR2; /* */
+ union { /* TCNT_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_3; /* */
+ union { /* TCNT_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_4; /* */
+ union { /* TCDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCDR; /* */
+ union { /* TDDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TDDR; /* */
+ union { /* TGRA_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_3; /* */
+ union { /* TGRB_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_3; /* */
+ union { /* TGRA_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_4; /* */
+ union { /* TGRB_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_4; /* */
+ union { /* TCNTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNTS; /* */
+ union { /* TCBR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCBR; /* */
+ union { /* TGRC_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRC_3; /* */
+ union { /* TGRD_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRD_3; /* */
+ union { /* TGRC_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRC_4; /* */
+ union { /* TGRD_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRD_4; /* */
+ union { /* TSR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TCFD:1; /* TCFD */
+ _UBYTE :2; /* */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFA:1; /* TGFA */
+ } BIT; /* */
+ } TSR_3; /* */
+ union { /* TSR_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TCFD:1; /* TCFD */
+ _UBYTE :2; /* */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFA:1; /* TGFA */
+ } BIT; /* */
+ } TSR_4; /* */
+ _UBYTE wk3[2]; /* */
+ union { /* TITCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE T3AEN:1; /* T3AEN */
+ _UBYTE _3ACOR:3; /* _3ACOR */
+ _UBYTE T4VEN:1; /* T4VEN */
+ _UBYTE _4VCOR:3; /* _4VCOR */
+ } BIT; /* */
+ } TITCR; /* */
+ union { /* TITCNT */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE _3ACNT:3; /* _3ACNT */
+ _UBYTE :1; /* */
+ _UBYTE _4VCNT:3; /* _4VCNT */
+ } BIT; /* */
+ } TITCNT; /* */
+ union { /* TBTER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE BTE:2; /* BTE */
+ } BIT; /* */
+ } TBTER; /* */
+ _UBYTE wk4[1]; /* */
+ union { /* TDER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE TDER:1; /* TDER */
+ } BIT; /* */
+ } TDER; /* */
+ _UBYTE wk5[1]; /* */
+ union { /* TOLBR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE OLS3N:1; /* OLS3N */
+ _UBYTE OLS3P:1; /* OLS3P */
+ _UBYTE OLS2N:1; /* OLS2N */
+ _UBYTE OLS2P:1; /* OLS2P */
+ _UBYTE OLS1N:1; /* OLS1N */
+ _UBYTE OLS1P:1; /* OLS1P */
+ } BIT; /* */
+ } TOLBR; /* */
+ _UBYTE wk6[1]; /* */
+ union { /* TBTM_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE TTSB:1; /* TTSB */
+ _UBYTE TTSA:1; /* TTSA */
+ } BIT; /* */
+ } TBTM_3; /* */
+ union { /* TBTM_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE TTSB:1; /* TTSB */
+ _UBYTE TTSA:1; /* TTSA */
+ } BIT; /* */
+ } TBTM_4; /* */
+ _UBYTE wk7[6]; /* */
+ union { /* TADCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BF:2; /* BF */
+ _UWORD :6; /* */
+ _UWORD UT4AE:1; /* UT4AE */
+ _UWORD DT4AE:1; /* DT4AE */
+ _UWORD UT4BE:1; /* UT4BE */
+ _UWORD DT4BE:1; /* DT4BE */
+ _UWORD ITA3AE:1; /* ITA3AE */
+ _UWORD ITA4VE:1; /* ITA4VE */
+ _UWORD ITB3AE:1; /* ITB3AE */
+ _UWORD ITB4VE:1; /* ITB4VE */
+ } BIT; /* */
+ } TADCR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* TADCORA_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCORA_4; /* */
+ union { /* TADCORB_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCORB_4; /* */
+ union { /* TADCOBRA_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCOBRA_4; /* */
+ union { /* TADCOBRB_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCOBRB_4; /* */
+ _UBYTE wk9[20]; /* */
+ union { /* TWCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CCE:1; /* CCE */
+ _UBYTE :6; /* */
+ _UBYTE WRE:1; /* WRE */
+ } BIT; /* */
+ } TWCR; /* */
+ _UBYTE wk10[31]; /* */
+ union { /* TSTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CST4:1; /* CST4 */
+ _UBYTE CST3:1; /* CST3 */
+ _UBYTE :3; /* */
+ _UBYTE CST2:1; /* CST2 */
+ _UBYTE CST1:1; /* CST1 */
+ _UBYTE CST0:1; /* CST0 */
+ } BIT; /* */
+ } TSTR; /* */
+ union { /* TSYR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SYNC4:1; /* SYNC4 */
+ _UBYTE SYNC3:1; /* SYNC3 */
+ _UBYTE :3; /* */
+ _UBYTE SYNC2:1; /* SYNC2 */
+ _UBYTE SYNC1:1; /* SYNC1 */
+ _UBYTE SYNC0:1; /* SYNC0 */
+ } BIT; /* */
+ } TSYR; /* */
+ _UBYTE wk11[2]; /* */
+ union { /* TRWER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE RWE:1; /* RWE */
+ } BIT; /* */
+ } TRWER; /* */
+ _UBYTE wk12[123]; /* */
+ union { /* TCR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CCLR:3; /* CCLR */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE TPSC:3; /* TPSC */
+ } BIT; /* */
+ } TCR_0; /* */
+ union { /* TMDR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE BFE:1; /* BFE */
+ _UBYTE BFB:1; /* BFB */
+ _UBYTE BFA:1; /* BFA */
+ _UBYTE MD:4; /* MD */
+ } BIT; /* */
+ } TMDR_0; /* */
+ union { /* TIORH_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOB:4; /* IOB */
+ _UBYTE IOA:4; /* IOA */
+ } BIT; /* */
+ } TIORH_0; /* */
+ union { /* TIORL_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOD:4; /* IOD */
+ _UBYTE IOC:4; /* IOC */
+ } BIT; /* */
+ } TIORL_0; /* */
+ union { /* TIER_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTGE:1; /* TTGE */
+ _UBYTE :2; /* */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE TGIED:1; /* TGIED */
+ _UBYTE TGIEC:1; /* TGIEC */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEA:1; /* TGIEA */
+ } BIT; /* */
+ } TIER_0; /* */
+ union { /* TSR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TCFD:1; /* TCFD */
+ _UBYTE :2; /* */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFA:1; /* TGFA */
+ } BIT; /* */
+ } TSR_0; /* */
+ union { /* TCNT_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_0; /* */
+ union { /* TGRA_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_0; /* */
+ union { /* TGRB_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_0; /* */
+ union { /* TGRC_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRC_0; /* */
+ union { /* TGRD_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRD_0; /* */
+ _UBYTE wk13[16]; /* */
+ union { /* TGRE_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRE_0; /* */
+ union { /* TGRF_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRF_0; /* */
+ union { /* TIER2_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTGE2:1; /* TTGE2 */
+ _UBYTE :5; /* */
+ _UBYTE TGIEF:1; /* TGIEF */
+ _UBYTE TGIEE:1; /* TGIEE */
+ } BIT; /* */
+ } TIER2_0; /* */
+ union { /* TSR2_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE TGFF:1; /* TGFF */
+ _UBYTE TGFE:1; /* TGFE */
+ } BIT; /* */
+ } TSR2_0; /* */
+ union { /* TBTM_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE TTSE:1; /* TTSE */
+ _UBYTE TTSB:1; /* TTSB */
+ _UBYTE TTSA:1; /* TTSA */
+ } BIT; /* */
+ } TBTM_0; /* */
+ _UBYTE wk14[89]; /* */
+ union { /* TCR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE CCLR:2; /* CCLR */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE TPSC:3; /* TPSC */
+ } BIT; /* */
+ } TCR_1; /* */
+ union { /* TMDR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE MD:4; /* MD */
+ } BIT; /* */
+ } TMDR_1; /* */
+ union { /* TIOR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOB:4; /* IOB */
+ _UBYTE IOA:4; /* IOA */
+ } BIT; /* */
+ } TIOR_1; /* */
+ _UBYTE wk15[1]; /* */
+ union { /* TIER_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTGE:1; /* TTGE */
+ _UBYTE :1; /* */
+ _UBYTE TCIEU:1; /* TCIEU */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE :2; /* */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEA:1; /* TGIEA */
+ } BIT; /* */
+ } TIER_1; /* */
+ union { /* TSR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TCFD:1; /* TCFD */
+ _UBYTE :1; /* */
+ _UBYTE TCFU:1; /* TCFU */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFA:1; /* TGFA */
+ } BIT; /* */
+ } TSR_1; /* */
+ union { /* TCNT_1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_1; /* */
+ union { /* TGRA_1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_1; /* */
+ union { /* TGRB_1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_1; /* */
+ _UBYTE wk16[4]; /* */
+ union { /* TICCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE I2BE:1; /* I2BE */
+ _UBYTE I2AE:1; /* I2AE */
+ _UBYTE I1BE:1; /* I1BE */
+ _UBYTE I1AE:1; /* I1AE */
+ } BIT; /* */
+ } TICCR; /* */
+}; /* */
+#endif
+
+struct st_cmt { /* struct CMT */
+ union { /* CMSTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :14; /* */
+ _UWORD STR1:1; /* STR1 */
+ _UWORD STR0:1; /* STR0 */
+ } BIT; /* */
+ } CMSTR; /* */
+ union { /* CMCSR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD CMF:1; /* CMF */
+ _UWORD CMIE:1; /* CMIE */
+ _UWORD :4; /* */
+ _UWORD CKS:2; /* CKS */
+ } BIT; /* */
+ } CMCSR0; /* */
+ union { /* CMCNT0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } CMCNT0; /* */
+ union { /* CMCOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } CMCOR0; /* */
+ union { /* CMCSR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD CMF:1; /* CMF */
+ _UWORD CMIE:1; /* CMIE */
+ _UWORD :4; /* */
+ _UWORD CKS:2; /* CKS */
+ } BIT; /* */
+ } CMCSR1; /* */
+ union { /* CMCNT1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } CMCNT1; /* */
+ union { /* CMCOR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } CMCOR1; /* */
+}; /* */
+union un_wdt { /* union WDT */
+ struct { /* Read Access */
+ union { /* WTCSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOVF:1; /* IOVF */
+ _UBYTE WTIT:1; /* WT/IT */
+ _UBYTE TME:1; /* TME */
+ _UBYTE :2; /* */
+ _UBYTE CKS:3; /* CKS */
+ } BIT; /* */
+ } WTCSR; /* */
+ _UBYTE wk1; /* */
+ _UBYTE WTCNT; /* WTCNT */
+ _UBYTE wk2; /* */
+ union { /* WRCSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE WOVF:1; /* WOVF */
+ _UBYTE RSTE:1; /* RSTE */
+ _UBYTE RSTS:1; /* RSTS */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } WRCSR; /* */
+ } READ; /* */
+ struct { /* Write Access */
+ _UWORD WTCSR; /* WTCSR */
+ _UWORD WTCNT; /* WTCNT */
+ _UWORD WRCSR; /* WRCSR */
+ } WRITE; /* */
+}; /* */
+struct st_rtc { /* struct RTC */
+ union { /* R64CNT */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE _1Hz:1; /* _1Hz */
+ _UBYTE _2Hz:1; /* _2Hz */
+ _UBYTE _4Hz:1; /* _4Hz */
+ _UBYTE _8Hz:1; /* _8Hz */
+ _UBYTE _16Hz:1; /* _16Hz */
+ _UBYTE _32Hz:1; /* _32Hz */
+ _UBYTE _64Hz:1; /* _64Hz */
+ } BIT; /* */
+ } R64CNT; /* */
+ _UBYTE wk0[1]; /* */
+ _UBYTE RSECCNT; /* RSECCNT */
+ _UBYTE wk1[1]; /* */
+ _UBYTE RMINCNT; /* RMINCNT */
+ _UBYTE wk2[1]; /* */
+ _UBYTE RHRCNT; /* RHRCNT */
+ _UBYTE wk3[1]; /* */
+ _UBYTE RWKCNT; /* RWKCNT */
+ _UBYTE wk4[1]; /* */
+ _UBYTE RDAYCNT; /* RDAYCNT */
+ _UBYTE wk5[1]; /* */
+ _UBYTE RMONCNT; /* RMONCNT */
+ _UBYTE wk6[1]; /* */
+ _UWORD RYRCNT; /* RYRCNT */
+ union { /* RSECAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RSECAR; /* */
+ _UBYTE wk7[1]; /* */
+ union { /* RMINAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RMINAR; /* */
+ _UBYTE wk8[1]; /* */
+ union { /* RHRAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RHRAR; /* */
+ _UBYTE wk9[1]; /* */
+ union { /* RWKAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RWKAR; /* */
+ _UBYTE wk10[1]; /* */
+ union { /* RDAYAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RDAYAR; /* */
+ _UBYTE wk11[1]; /* */
+ union { /* RMONAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RMONAR; /* */
+ _UBYTE wk12[1]; /* */
+ union { /* RCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CF:1; /* CF */
+ _UBYTE :2; /* */
+ _UBYTE CIE:1; /* CIE */
+ _UBYTE AIE:1; /* AIE */
+ _UBYTE :2; /* */
+ _UBYTE AF:1; /* AF */
+ } BIT; /* */
+ } RCR1; /* */
+ _UBYTE wk13[1]; /* */
+ union { /* RCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE PEF:1; /* PEF */
+ _UBYTE PES:3; /* PES */
+ _UBYTE RTCEN:1; /* RTCEN */
+ _UBYTE ADJ:1; /* ADJ */
+ _UBYTE RESET:1; /* RESET */
+ _UBYTE START:1; /* START */
+ } BIT; /* */
+ } RCR2; /* */
+ _UBYTE wk14[1]; /* */
+ _UWORD RYRAR; /* RYRAR */
+ _UBYTE wk15[2]; /* */
+ union { /* RCR3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ENB:1; /* ENB */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RCR3; /* */
+ _UBYTE wk16[1]; /* */
+ union { /* RCR5 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE RCKSEL:2; /* RCKSEL */
+ } BIT; /* */
+ } RCR5; /* */
+ _UBYTE wk17[2]; /* */
+ _UBYTE wk18[1]; /* */
+ union { /* RFRH */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SEL64:1; /* SEL64 */
+ _UWORD :12; /* */
+ _UWORD RFC18:1; /* RFC[18] */
+ _UWORD RFC17:1; /* RFC[17] */
+ _UWORD RFC16:1; /* RFC[16] */
+ } BIT; /* */
+ } RFRH; /* */
+ union { /* RFRL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD RFC15:1; /* RFC[15] */
+ _UWORD RFC14:1; /* RFC[14] */
+ _UWORD RFC13:1; /* RFC[13] */
+ _UWORD RFC12:1; /* RFC[12] */
+ _UWORD RFC11:1; /* RFC[11] */
+ _UWORD RFC10:1; /* RFC[10] */
+ _UWORD RFC9:1; /* RFC[9] */
+ _UWORD RFC8:1; /* RFC[8] */
+ _UWORD RFC7:1; /* RFC[7] */
+ _UWORD RFC6:1; /* RFC[6] */
+ _UWORD RFC5:1; /* RFC[5] */
+ _UWORD RFC4:1; /* RFC[4] */
+ _UWORD RFC3:1; /* RFC[3] */
+ _UWORD RFC2:1; /* RFC[2] */
+ _UWORD RFC1:1; /* RFC[1] */
+ _UWORD RFC0:1; /* RFC[0] */
+ } BIT; /* */
+ } RFRL; /* */
+}; /* */
+ #if 0
+struct st_scif02346 { /* struct SCIF */
+ union { /* SCSMR_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD CA:1; /* C/A */
+ _UWORD CHR:1; /* CHR */
+ _UWORD PE:1; /* PE */
+ _UWORD OE:1; /* O/E */
+ _UWORD STOP:1; /* STOP */
+ _UWORD :1; /* */
+ _UWORD CKS:2; /* CKS */
+ } BIT; /* */
+ } SCSMR; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* SCBRR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCBRR; /* */
+ _UBYTE wk1[3]; /* */
+ union { /* SCSCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TIE:1; /* TIE */
+ _UWORD RIE:1; /* RIE */
+ _UWORD TE:1; /* TE */
+ _UWORD RE:1; /* RE */
+ _UWORD REIE:1; /* REIE */
+ _UWORD :1; /* */
+ _UWORD CKE:2; /* CKE */
+ } BIT; /* */
+ } SCSCR; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* SCFTDR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCFTDR; /* */
+ _UBYTE wk3[3]; /* */
+ union { /* SCFSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PERN:4; /* PERN */
+ _UWORD FERN:4; /* FERN */
+ _UWORD ER:1; /* ER */
+ _UWORD TEND:1; /* TEND */
+ _UWORD TDFE:1; /* TDFE */
+ _UWORD BRK:1; /* BRK */
+ _UWORD FER:1; /* FER */
+ _UWORD PER:1; /* PER */
+ _UWORD RDF:1; /* RDF */
+ _UWORD DR:1; /* DR */
+ } BIT; /* */
+ } SCFSR; /* */
+ _UBYTE wk4[2]; /* */
+ union { /* SCFRDR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCFRDR; /* */
+ _UBYTE wk5[3]; /* */
+ union { /* SCFCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RSTRG:3; /* RSTRG */
+ _UWORD RTRG:2; /* RTRG */
+ _UWORD TTRG:2; /* TTRG */
+ _UWORD MCE:1; /* MCE */
+ _UWORD TFRST:1; /* TFRST */
+ _UWORD RFRST:1; /* RFRST */
+ _UWORD LOOP:1; /* LOOP */
+ } BIT; /* */
+ } SCFCR; /* */
+ _UBYTE wk6[2]; /* */
+ union { /* SCFDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD T:5; /* T */
+ _UWORD :3; /* */
+ _UWORD R:5; /* R */
+ } BIT; /* */
+ } SCFDR; /* */
+ _UBYTE wk7[2]; /* */
+ union { /* SCSPTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :12; /* */
+ _UWORD SCKIO:1; /* SCKIO */
+ _UWORD SCKDT:1; /* SCKDT */
+ _UWORD SPB2IO:1; /* SPB2IO */
+ _UWORD SPB2DT:1; /* SPB2DT */
+ } BIT; /* */
+ } SCSPTR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* SCLSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD ORER:1; /* ORER */
+ } BIT; /* */
+ } SCLSR; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* SCEMR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD BGDM:1; /* BGDM */
+ _UWORD :6; /* */
+ _UWORD ABCS:1; /* ABCS */
+ } BIT; /* */
+ } SCEMR; /* */
+}; /* */
+struct st_scif157 { /* struct SCIF */
+ union { /* SCSMR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD CA:1; /* C/A */
+ _UWORD CHR:1; /* CHR */
+ _UWORD PE:1; /* PE */
+ _UWORD OE:1; /* O/E */
+ _UWORD STOP:1; /* STOP */
+ _UWORD :1; /* */
+ _UWORD CKS:2; /* CKS */
+ } BIT; /* */
+ } SCSMR; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* SCBRR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCBRR; /* */
+ _UBYTE wk1[3]; /* */
+ union { /* SCSCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TIE:1; /* TIE */
+ _UWORD RIE:1; /* RIE */
+ _UWORD TE:1; /* TE */
+ _UWORD RE:1; /* RE */
+ _UWORD REIE:1; /* REIE */
+ _UWORD :1; /* */
+ _UWORD CKE:2; /* CKE */
+ } BIT; /* */
+ } SCSCR ; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* SCFTDR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCFTDR; /* */
+ _UBYTE wk3[3]; /* */
+ union { /* SCFSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PERN:4; /* PERN */
+ _UWORD FERN:4; /* FERN */
+ _UWORD ER:1; /* ER */
+ _UWORD TEND:1; /* TEND */
+ _UWORD TDFE:1; /* TDFE */
+ _UWORD BRK:1; /* BRK */
+ _UWORD FER:1; /* FER */
+ _UWORD PER:1; /* PER */
+ _UWORD RDF:1; /* RDF */
+ _UWORD DR:1; /* DR */
+ } BIT; /* */
+ } SCFSR ; /* */
+ _UBYTE wk4[2]; /* */
+ union { /* SCFRDR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCFRDR; /* */
+ _UBYTE wk5[3]; /* */
+ union { /* SCFCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RSTRG:3; /* RSTRG */
+ _UWORD RTRG:2; /* RTRG */
+ _UWORD TTRG:2; /* TTRG */
+ _UWORD MCE:1; /* MCE */
+ _UWORD TFRST:1; /* TFRST */
+ _UWORD RFRST:1; /* RFRST */
+ _UWORD LOOP:1; /* LOOP */
+ } BIT; /* */
+ } SCFCR; /* */
+ _UBYTE wk6[2]; /* */
+ union { /* SCFDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD T:5; /* T */
+ _UWORD :3; /* */
+ _UWORD R:5; /* R */
+ } BIT; /* */
+ } SCFDR; /* */
+ _UBYTE wk7[2]; /* */
+ union { /* SCSPTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD RTSIO:1; /* RTSIO */
+ _UWORD RTSDT:1; /* RTSDT */
+ _UWORD CTSIO:1; /* CTSIO */
+ _UWORD CTSDT:1; /* CTSDT */
+ _UWORD SCKIO:1; /* SCKIO */
+ _UWORD SCKDT:1; /* SCKDT */
+ _UWORD SPB2IO:1; /* SPB2IO */
+ _UWORD SPB2DT:1; /* SPB2DT */
+ } BIT; /* */
+ } SCSPTR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* SCLSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD ORER:1; /* ORER */
+ } BIT; /* */
+ } SCLSR; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* SCEMR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD BGDM:1; /* BGDM */
+ _UWORD :6; /* */
+ _UWORD ABCS:1; /* ABCS */
+ } BIT; /* */
+ } SCEMR; /* */
+}; /* */
+ #endif
+struct st_rspi { /* struct RSPI */
+ union { /* SPCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SPRIE:1; /* SPRIE */
+ _UBYTE SPE:1; /* SPE */
+ _UBYTE SPTIE:1; /* SPTIE */
+ _UBYTE SPEIE:1; /* SPEIE */
+ _UBYTE MSTR:1; /* MSTR */
+ _UBYTE MODFEN:1; /* MODFEN */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } SPCR; /* */
+ union { /* SSLP */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE SSL0P:1; /* SSL0P */
+ } BIT; /* */
+ } SSLP; /* */
+ union { /* SPPCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE MOIFE:1; /* MOIFE */
+ _UBYTE MOIFV:1; /* MOIFV */
+ _UBYTE :3; /* */
+ _UBYTE SPLP:1; /* SPLP */
+ } BIT; /* */
+ } SPPCR; /* */
+ union { /* SPSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SPRF:1; /* SPRF */
+ _UBYTE TEND:1; /* TEND */
+ _UBYTE SPTEF:1; /* SPTEF */
+ _UBYTE :2; /* */
+ _UBYTE MODF:1; /* MODF */
+ _UBYTE :1; /* */
+ _UBYTE OVRF:1; /* OVRF */
+ } BIT; /* */
+ } SPSR; /* */
+ union { /* SPDR */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD; /* Word Access */
+ _UBYTE BYTE; /* Byte Access */
+ } SPDR; /* */
+ union { /* SPSCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE SPSLN:2; /* SPSLN */
+ } BIT; /* */
+ } SPSCR; /* */
+ union { /* SPSSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE SPCP:2; /* SPCP */
+ } BIT; /* */
+ } SPSSR; /* */
+ union { /* SPBR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SPR:8; /* SPR */
+ } BIT; /* */
+ } SPBR; /* */
+ union { /* SPDCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TXDMY:1; /* TXDMY */
+ _UBYTE SPLW:2; /* SPLW */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } SPDCR; /* */
+ union { /* SPCKD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE SCKDL:3; /* SCKDL */
+ } BIT; /* */
+ } SPCKD; /* */
+ union { /* SSLND */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE SLNDL:3; /* SLNDL */
+ } BIT; /* */
+ } SSLND; /* */
+ union { /* SPND */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE SPNDL:3; /* SPNDL */
+ } BIT; /* */
+ } SPND; /* */
+ _UBYTE wk0[1]; /* */
+ union { /* SPCMD0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD :3; /* */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD0; /* */
+ union { /* SPCMD1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD :3; /* */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD1 ; /* */
+ union { /* SPCMD2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD :3; /* */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD2 ; /* */
+ union { /* SPCMD3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD :3; /* */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD3 ; /* */
+ _UBYTE wk1[8]; /* */
+ union { /* SPBFCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TXRST:1; /* TXRST */
+ _UBYTE RXRST:1; /* RXRST */
+ _UBYTE TXTRG:2; /* TXTRG */
+ _UBYTE :1; /* */
+ _UBYTE RXTRG:3; /* RXTRG */
+ } BIT; /* */
+ } SPBFCR; /* */
+ _UBYTE wk2[1]; /* */
+ union { /* SPBFDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD T:4 ; /* T */
+ _UWORD :2; /* */
+ _UWORD R:6; /* R */
+ } BIT; /* */
+ } SPBFDR; /* */
+}; /* */
+ #if 0
+struct st_iic3 { /* struct IIC3 */
+ union { /* ICCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ICE:1; /* ICE */
+ _UBYTE RCVD:1; /* RCVD */
+ _UBYTE MST:1; /* MST */
+ _UBYTE TRS:1; /* TRS */
+ _UBYTE CKS:4; /* CKS */
+ } BIT; /* */
+ } ICCR1; /* */
+ union { /* ICCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BBSY:1; /* BBSY */
+ _UBYTE SCP:1; /* SCP */
+ _UBYTE SDAO:1; /* SDAO */
+ _UBYTE SDAOP:1; /* SDAOP */
+ _UBYTE SCLO:1; /* SCLO */
+ _UBYTE :1; /* */
+ _UBYTE IICRST:1; /* IICRST */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } ICCR2; /* */
+ union { /* ICMR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MLS:1; /* MLS */
+ _UBYTE :3; /* */
+ _UBYTE BCWP:1; /* BCWP */
+ _UBYTE BC:3; /* BC */
+ } BIT; /* */
+ } ICMR; /* */
+ union { /* ICIER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TIE:1; /* TIE */
+ _UBYTE TEIE:1; /* TEIE */
+ _UBYTE RIE:1; /* RIE */
+ _UBYTE NAKIE:1; /* NAKIE */
+ _UBYTE STIE:1; /* STIE */
+ _UBYTE ACKE:1; /* ACKE */
+ _UBYTE ACKBR:1; /* ACKBR */
+ _UBYTE ACKBT:1; /* ACKBT */
+ } BIT; /* */
+ } ICIER; /* */
+ union { /* ICSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TDRE:1; /* TDRE */
+ _UBYTE TEND:1; /* TEND */
+ _UBYTE RDRF:1; /* RDRF */
+ _UBYTE NACKF:1; /* NACKF */
+ _UBYTE STOP:1; /* STOP */
+ _UBYTE ALOVE:1; /* AL/OVE */
+ _UBYTE AAS:1; /* AAS */
+ _UBYTE ADZ:1; /* ADZ */
+ } BIT; /* */
+ } ICSR; /* */
+ union { /* SAR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SVA:7; /* SVA */
+ _UBYTE FS:1; /* FS */
+ } BIT; /* */
+ } SAR; /* */
+ _UBYTE ICDRT; /* ICDRT */
+ _UBYTE ICDRR; /* ICDRR */
+ union { /* NF2CYC */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :3; /* */
+ _UBYTE CKS4:1; /* CKS4 */
+ _UBYTE :2; /* */
+ _UBYTE PRS:1; /* PRS */
+ _UBYTE NF2CYC:1; /* NF2CYC */
+ } BIT; /* */
+ } NF2CYC; /* */
+}; /* */
+ #endif
+struct st_ssif { /* struct SSIF */
+ union { /* SSICR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :1; /* */
+ _UDWORD CKS:1; /* CKS */
+ _UDWORD TUIEN:1; /* TUIEN */
+ _UDWORD TOIEN:1; /* TOIEN */
+ _UDWORD RUIEN:1; /* RUIEN */
+ _UDWORD ROIEN:1; /* ROIEN */
+ _UDWORD IIEN:1; /* IIEN */
+ _UDWORD :1; /* */
+ _UDWORD CHNL:2; /* CHNL */
+ _UDWORD DWL:3; /* DWL */
+ _UDWORD SWL:3; /* SWL */
+ _UDWORD SCKD:1; /* SCKD */
+ _UDWORD SWSD:1; /* SWSD */
+ _UDWORD SCKP:1; /* SCKP */
+ _UDWORD SWSP:1; /* SWSP */
+ _UDWORD SPDP:1; /* SPDP */
+ _UDWORD SDTA:1; /* SDTA */
+ _UDWORD PDTA:1; /* PDTA */
+ _UDWORD DEL:1; /* DEL */
+ _UDWORD CKDV:4; /* CKDV */
+ _UDWORD MUEN:1; /* MUEN */
+ _UDWORD :1; /* */
+ _UDWORD TEN:1; /* TEN */
+ _UDWORD REN:1; /* REN */
+ } BIT; /* */
+ } SSICR; /* */
+ union { /* SSISR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD :2; /* */
+ _UDWORD TUIRQ:1; /* TUIRQ */
+ _UDWORD TOIRQ:1; /* TOIRQ */
+ _UDWORD RUIRQ:1; /* RUIRQ */
+ _UDWORD ROIRQ:1; /* ROIRQ */
+ _UDWORD IIRQ:1; /* IIRQ */
+ _UDWORD :18; /* */
+ _UDWORD TCHNO:2; /* TCHNO */
+ _UDWORD TSWNO:1; /* TSWNO */
+ _UDWORD RCHNO:2; /* RCHNO */
+ _UDWORD RSWNO:1; /* RSWNO */
+ _UDWORD IDST:1; /* IDST */
+ } BIT; /* */
+ } SSISR; /* */
+ _UBYTE wk0[8]; /* */
+ union { /* SSIFCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD TTRG:2; /* TTRG */
+ _UDWORD RTRG:2; /* RTRG */
+ _UDWORD TIE:1; /* TIE */
+ _UDWORD RIE:1; /* RIE */
+ _UDWORD TFRST:1; /* TFRST */
+ _UDWORD RFRST:1; /* RFRST */
+ } BIT; /* */
+ } SSIFCR; /* */
+ union { /* SSIFSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :4; /* */
+ _UDWORD TDC:4; /* TDC */
+ _UDWORD :7; /* */
+ _UDWORD TDE:1; /* TDE */
+ _UDWORD :4; /* */
+ _UDWORD RDC:4; /* RDC */
+ _UDWORD :7; /* */
+ _UDWORD RDF:1; /* RDF */
+ } BIT; /* */
+ } SSIFSR; /* */
+ _UDWORD SSIFTDR; /* SSIFTDR */
+ _UDWORD SSIFRDR; /* SSIFRDR */
+ union { /* SSITDMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD CONT:1; /* CONT */
+ _UDWORD :7; /* */
+ _UDWORD TDM:1; /* TDM */
+ } BIT; /* */
+ } SSITDMR; /* */
+}; /* */
+struct st_siof { /* struct SIOF */
+ union { /* SIMDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TRMD:2; /* TRMD */
+ _UWORD SYNCAT:1; /* SYNCAT */
+ _UWORD REDG:1; /* REDG */
+ _UWORD FL:4; /* FL */
+ _UWORD TXDIZ:1; /* TXDIZ */
+ _UWORD :1; /* */
+ _UWORD SYNCAC:1; /* SYNCAC */
+ _UWORD SYNCDL:1; /* SYNCDL */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } SIMDR; /* */
+ union { /* SISCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MSSEL:1; /* MSSEL */
+ _UWORD :2; /* */
+ _UWORD BRPS:5; /* BRPS */
+ _UWORD :5; /* */
+ _UWORD BRDV:3; /* BRDV */
+ } BIT; /* */
+ } SISCR; /* */
+ union { /* SITDAR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TDLE:1; /* TDLE */
+ _UWORD :3; /* */
+ _UWORD TDLA:4; /* TDLA */
+ _UWORD TDRE:1; /* TDRE */
+ _UWORD TLREP:1; /* TLREP */
+ _UWORD :2; /* */
+ _UWORD TDRA:4; /* TDRA */
+ } BIT; /* */
+ } SITDAR; /* */
+ union { /* SIRDAR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD RDLE:1; /* RDLE */
+ _UWORD :3; /* */
+ _UWORD RDLA:4; /* RDLA */
+ _UWORD RDRE:1; /* RDRE */
+ _UWORD :3; /* */
+ _UWORD RDRA:4; /* RDRA */
+ } BIT; /* */
+ } SIRDAR; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* SICTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKE:1; /* SCKE */
+ _UWORD FSE:1; /* FSE */
+ _UWORD :4; /* */
+ _UWORD TXE:1; /* TXE */
+ _UWORD RXE:1; /* RXE */
+ _UWORD :6; /* */
+ _UWORD TXRST:1; /* TXRST */
+ _UWORD RXRST:1; /* RXRST */
+ } BIT; /* */
+ } SICTR; /* */
+ _UBYTE wk1[2]; /* */
+ union { /* SIFCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TFWM:3; /* TFWM */
+ _UWORD TFUA:5; /* TFUA */
+ _UWORD RFWM:3; /* RFWM */
+ _UWORD RFUA:5; /* RFUA */
+ } BIT; /* */
+ } SIFCTR; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* SISTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD TFEMP:1; /* TFEMP */
+ _UWORD TDREQ:1; /* TDREQ */
+ _UWORD :2; /* */
+ _UWORD RFFUL:1 ; /* RFFUL */
+ _UWORD RDREQ:1; /* RDREQ */
+ _UWORD :3; /* */
+ _UWORD FSERR:1; /* FSERR */
+ _UWORD TFOVF:1; /* TFOVF */
+ _UWORD TFUDF:1; /* TFUDF */
+ _UWORD RFUDF:1; /* RFUDF */
+ _UWORD RFOVF:1; /* RFOVF */
+ } BIT; /* */
+ } SISTR; /* */
+ union { /* SIIER */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TDMAE:1; /* TDMAE */
+ _UWORD :1; /* */
+ _UWORD TFEMPE:1; /* TFEMPE */
+ _UWORD TDREQE:1; /* TDREQE */
+ _UWORD RDMAE:1; /* RDMAE */
+ _UWORD :1; /* */
+ _UWORD RFFULE:1; /* RFFULE */
+ _UWORD RDREQE:1; /* RDREQE */
+ _UWORD :3; /* */
+ _UWORD FSERRE:1; /* FSERRE */
+ _UWORD TFOVFE:1; /* TFOVFE */
+ _UWORD TFUDFE:1; /* TFUDFE */
+ _UWORD RFUDFE:1; /* RFUDFE */
+ _UWORD RFOVFE:1; /* RFOVFE */
+ } BIT; /* */
+ } SIIER; /* */
+ _UBYTE wk3[8]; /* */
+ union { /* SITDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD SITDL:16; /* SITDL */
+ _UWORD SITDR:16; /* SITDR */
+ } BIT; /* */
+ } SITDR; /* */
+ union { /* SIRDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD SIRDL:16; /* SIRDL */
+ _UWORD SIRDR:16; /* SIRDR */
+ } BIT; /* */
+ } SIRDR; /* */
+};
+union un_mb3116{ /* MB31-MB16 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MB31:1; /* MB31 */
+ _UWORD MB30:1; /* MB30 */
+ _UWORD MB29:1; /* MB29 */
+ _UWORD MB28:1; /* MB28 */
+ _UWORD MB27:1; /* MB27 */
+ _UWORD MB26:1; /* MB26 */
+ _UWORD MB25:1; /* MB25 */
+ _UWORD MB24:1; /* MB24 */
+ _UWORD MB23:1; /* MB23 */
+ _UWORD MB22:1; /* MB22 */
+ _UWORD MB21:1; /* MB21 */
+ _UWORD MB20:1; /* MB20 */
+ _UWORD MB19:1; /* MB19 */
+ _UWORD MB18:1; /* MB18 */
+ _UWORD MB17:1; /* MB17 */
+ _UWORD MB16:1; /* MB16 */
+ } BIT; /* */
+};
+union un_mb15_0{ /* MB15-MB0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MB15:1; /* MB15 */
+ _UWORD MB14:1; /* MB14 */
+ _UWORD MB13:1; /* MB13 */
+ _UWORD MB12:1; /* MB12 */
+ _UWORD MB11:1; /* MB11 */
+ _UWORD MB10:1; /* MB10 */
+ _UWORD MB9:1; /* MB9 */
+ _UWORD MB8:1; /* MB8 */
+ _UWORD MB7:1; /* MB7 */
+ _UWORD MB6:1; /* MB6 */
+ _UWORD MB5:1; /* MB5 */
+ _UWORD MB4:1; /* MB4 */
+ _UWORD MB3:1; /* MB3 */
+ _UWORD MB2:1; /* MB2 */
+ _UWORD MB1:1; /* MB1 */
+ _UWORD MB0:1; /* MB0 */
+ } BIT; /* */
+};
+union un_mb15_1{ /* MB15-MB1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MB15:1; /* MB15 */
+ _UWORD MB14:1; /* MB14 */
+ _UWORD MB13:1; /* MB13 */
+ _UWORD MB12:1; /* MB12 */
+ _UWORD MB11:1; /* MB11 */
+ _UWORD MB10:1; /* MB10 */
+ _UWORD MB9:1; /* MB9 */
+ _UWORD MB8:1; /* MB8 */
+ _UWORD MB7:1; /* MB7 */
+ _UWORD MB6:1; /* MB6 */
+ _UWORD MB5:1; /* MB5 */
+ _UWORD MB4:1; /* MB4 */
+ _UWORD MB3:1; /* MB3 */
+ _UWORD MB2:1; /* MB2 */
+ _UWORD MB1:1; /* MB1 */
+ _UWORD :1; /* */
+ } BIT; /* */
+};
+struct st_rcan { /* struct RCAN */
+ union { /* MCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD IDR :1; /* IDR */
+ _UWORD AHBO :1; /* AHBO */
+ _UWORD :3; /* */
+ _UWORD TST :3; /* TST */
+ _UWORD AWM :1; /* AWM */
+ _UWORD HTBO :1; /* HTBO */
+ _UWORD SLPM :1; /* SLPM */
+ _UWORD :2; /* */
+ _UWORD MTP :1; /* MTP */
+ _UWORD HLTRQ:1; /* HLTRQ */
+ _UWORD RSTRQ:1; /* RSTRQ */
+ } BIT; /* */
+ } MCR; /* */
+ union { /* GSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :10; /* */
+ _UWORD EPS:1; /* EPS */
+ _UWORD HSS:1; /* HSS */
+ _UWORD RS:1; /* RS */
+ _UWORD MTPF:1; /* MTPF */
+ _UWORD TRWF:1; /* TRWF */
+ _UWORD BOF:1; /* BOF */
+ } BIT; /* */
+ } GSR; /* */
+ union { /* BCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TSG1:4; /* TSG1 */
+ _UWORD :1; /* */
+ _UWORD TSG2:3; /* TSG2 */
+ _UWORD :2; /* */
+ _UWORD SJW:2; /* SJW */
+ _UWORD :3; /* */
+ _UWORD BSP:1; /* BSP */
+ } BIT; /* */
+ } BCR1; /* */
+ union { /* BCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD BRP:8; /* BRP */
+ } BIT; /* */
+ } BCR0; /* */
+ union { /* IRR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TCMI1 :1; /* TCMI1 */
+ _UWORD TCMI0 :1; /* TCMI0 */
+ _UWORD TOI :1; /* TOI */
+ _UWORD BASMIF:1; /* BASMIF */
+ _UWORD TCMI2 :1; /* TCMI2 */
+ _UWORD SNSMI :1; /* SNSMI */
+ _UWORD MOOIF :1; /* MOOIF */
+ _UWORD MBEIF :1; /* MBEIF */
+ _UWORD OLF :1; /* OLF */
+ _UWORD BOFIF :1; /* BOFIF */
+ _UWORD EPIF :1; /* EPIF */
+ _UWORD RECWIF:1; /* RECWIF */
+ _UWORD TECWIF:1; /* TECWIF */
+ _UWORD RFRIF :1; /* RFRIF */
+ _UWORD DFRIF :1; /* DFRIF */
+ _UWORD RSTIF :1; /* RSTIF */
+ } BIT; /* */
+ } IRR; /* */
+ union { /* IMR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TCMI1M:1; /* TCMI1M */
+ _UWORD TCMI0M:1; /* TCMI0M */
+ _UWORD TOIM :1; /* TOIM */
+ _UWORD BASMIM:1; /* BASMIM */
+ _UWORD TCMI2M:1; /* TCMI2M */
+ _UWORD SNSMIM:1; /* SNSMIM */
+ _UWORD MOOIM :1; /* MOOIM */
+ _UWORD MBEIM :1; /* MBEIM */
+ _UWORD OLFM :1; /* OLFM */
+ _UWORD BOFIM :1; /* BOFIM */
+ _UWORD EPIM :1; /* EPIM */
+ _UWORD RECWIM:1; /* RECWIM */
+ _UWORD TECWIM:1; /* TECWIM */
+ _UWORD RFRIM :1; /* RFRIM */
+ _UWORD DFRIM :1; /* DFRIM */
+ _UWORD RSTIM :1; /* RSTIM */
+ } BIT; /* */
+ } IMR; /* */
+ union { /* TEC_REC */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TEC:8; /* TEC */
+ _UWORD REC:8; /* REC */
+ } BIT; /* */
+ } TEC_REC ; /* */
+ _UBYTE wk0[18]; /* */
+ union{ /* TXPR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD MB31:1; /* MB31 */
+ _UDWORD MB30:1; /* MB30 */
+ _UDWORD MB29:1; /* MB29 */
+ _UDWORD MB28:1; /* MB28 */
+ _UDWORD MB27:1; /* MB27 */
+ _UDWORD MB26:1; /* MB26 */
+ _UDWORD MB25:1; /* MB25 */
+ _UDWORD MB24:1; /* MB24 */
+ _UDWORD MB23:1; /* MB23 */
+ _UDWORD MB22:1; /* MB22 */
+ _UDWORD MB21:1; /* MB21 */
+ _UDWORD MB20:1; /* MB20 */
+ _UDWORD MB19:1; /* MB19 */
+ _UDWORD MB18:1; /* MB18 */
+ _UDWORD MB17:1; /* MB17 */
+ _UDWORD MB16:1; /* MB16 */
+ _UDWORD MB15:1; /* MB15 */
+ _UDWORD MB14:1; /* MB14 */
+ _UDWORD MB13:1; /* MB13 */
+ _UDWORD MB12:1; /* MB12 */
+ _UDWORD MB11:1; /* MB11 */
+ _UDWORD MB10:1; /* MB10 */
+ _UDWORD MB9:1; /* MB9 */
+ _UDWORD MB8:1; /* MB8 */
+ _UDWORD MB7:1; /* MB7 */
+ _UDWORD MB6:1; /* MB6 */
+ _UDWORD MB5:1; /* MB5 */
+ _UDWORD MB4:1; /* MB4 */
+ _UDWORD MB3:1; /* MB3 */
+ _UDWORD MB2:1; /* MB2 */
+ _UDWORD MB1:1; /* MB1 */
+ } BIT; /* */
+ } TXPR0 ; /* */
+ _UBYTE wk1[4]; /* */
+ union un_mb3116 TXCR1; /* TXCR1 */
+ union un_mb15_1 TXCR0; /* TXCR0 */
+ _UBYTE wk2[4]; /* */
+ union un_mb3116 TXACK1; /* TXACK1 */
+ union un_mb15_1 TXACK0; /* TXACK0 */
+ _UBYTE wk3[4]; /* */
+ union un_mb3116 ABACK1; /* ABACK1 */
+ union un_mb15_1 ABACK0; /* ABACK0 */
+ _UBYTE wk4[4]; /* */
+ union un_mb3116 RXPR1; /* RXPR1 */
+ union un_mb15_0 RXPR0; /* RXPR0 */
+ _UBYTE wk5[4]; /* */
+ union un_mb3116 RFPR1; /* RFPR1 */
+ union un_mb15_0 RFPR0; /* RFPR0 */
+ _UBYTE wk6[4]; /* */
+ union un_mb3116 MBIMR1; /* MBIMR1 */
+ union un_mb15_0 MBIMR0; /* MBIMR0 */
+ _UBYTE wk7[4]; /* */
+ union un_mb3116 UMSR1; /* UMSR1 */
+ union un_mb15_0 UMSR0; /* UMSR0 */
+ _UBYTE wk8[36]; /* */
+ union { /* TTCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TE:1; /* TE */
+ _UWORD TS:1; /* TS */
+ _UWORD CANC :1; /* CANC */
+ _UWORD CME2:1; /* CME2 */
+ _UWORD CME1:1; /* CME1 */
+ _UWORD CME0:1; /* CME0 */
+ _UWORD :3; /* */
+ _UWORD TCSC:1; /* TCSC */
+ _UWORD TPSC :6; /* TPSC */
+ } BIT; /* */
+ } TTCR0; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* CMAX_TEW */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD CMAX:3; /* CMAX */
+ _UWORD :4; /* */
+ _UWORD TEW:4 ; /* TEW */
+ } BIT; /* */
+ } CMAX_TEW; /* */
+ _UWORD RFTROFF; /* RFTROFF */
+ union { /* TSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD SNSM:1; /* SNSM */
+ _UWORD TCMF2:1; /* TCMF2 */
+ _UWORD TCMF1:1; /* TCMF1 */
+ _UWORD TCMF0:1; /* TCMF0 */
+ _UWORD TO_NGR_ME:1; /* TO_NGR_ME */
+ } BIT; /* */
+ } TSR; /* */
+ _UWORD CCR; /* CCR */
+ _UWORD TCNTR; /* TCNTR */
+ _UBYTE wk10[2]; /* */
+ _UWORD CYCTR; /* CYCTR */
+ _UBYTE wk11[2]; /* */
+ _UWORD RFMK; /* RFMK */
+ _UBYTE wk12[2]; /* */
+ _UWORD TCMR0; /* TCMR0 */
+ _UBYTE wk13[2]; /* */
+ _UWORD TCMR1; /* TCMR1 */
+ _UBYTE wk14[2]; /* */
+ _UWORD TCMR2; /* TCMR2 */
+ _UBYTE wk15[2]; /* */
+ _UWORD TTTSEL; /* TTTSEL */
+ _UBYTE wk16[90]; /* */
+ struct {
+ union { /* CONTROL0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD IDE:1; /* IDE */
+ _UDWORD RTR:1; /* RTR */
+ _UDWORD :1; /* */
+ _UDWORD STDID:11; /* STDID */
+ _UDWORD EXTID:18; /* EXTID */
+ } BIT; /* */
+ } CONTROL0; /* */
+ union { /* LAFM */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD IDE:1; /* IDE */
+ _UDWORD :2; /* */
+ _UDWORD STDID_LAFM:11;/* STDID_LAFM */
+ _UDWORD EXTID_LAFM:18;/* EXTID_LAFM */
+ } BIT; /* */
+ } LAFM; /* */
+ _UBYTE MSG_DATA[8]; /* MSG_DATA */
+ union { /* CONTROL1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD NMC:1; /* NMC */
+ _UWORD ATX:1; /* ATX */
+ _UWORD DART:1; /* DART */
+ _UWORD MBC:3; /* MBC */
+ _UWORD :4; /* */
+ _UWORD DLC:4; /* DLC */
+ } BIT; /* */
+ } CONTROL1; /* */
+ _UWORD TIMESTAMP; /* TIMESTAMP */
+ _UWORD TTT; /* TTT */
+ union { /* TTC */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TTW:2; /* TTW */
+ _UWORD Offset:6; /* Offset */
+ _UWORD :5; /* */
+ _UWORD rep_factor:3; /* rep_factor */
+ } BIT; /* */
+ } TTC; /* */
+ _UBYTE wk17[8]; /* */
+ } MB[32]; /* */
+}; /* */
+struct st_ieb { /* struct IEB */
+ union { /* IECTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE IOL:1; /* IOL */
+ _UBYTE DEE:1; /* DEE */
+ _UBYTE :1; /* */
+ _UBYTE RE:1; /* RE */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } IECTR; /* */
+ union { /* IECMR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE CMD:3; /* CMD */
+ } BIT; /* */
+ } IECMR; /* */
+ union { /* IEMCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SS:1; /* SS */
+ _UBYTE RN:3; /* RN */
+ _UBYTE CTL:4; /* CTL */
+ } BIT; /* */
+ } IEMCR; /* */
+ union { /* IEAR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IARL4:4; /* IARL4 */
+ _UBYTE IMD:2; /* IMD */
+ _UBYTE :1; /* */
+ _UBYTE STE:1; /* STE */
+ } BIT; /* */
+ } IEAR1; /* */
+ union { /* IEAR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IARU8:8; /* IARU8 */
+ } BIT; /* */
+ } IEAR2; /* */
+ union { /* IESA1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ISAL4:4; /* ISAL4 */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } IESA1; /* */
+ union { /* IESA2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ISAU8:8; /* ISAU8 */
+ } BIT; /* */
+ } IESA2; /* */
+ _UBYTE IETBFL; /* IETBFL */
+ _UBYTE wk0[1]; /* */
+ union { /* IEMA1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IMAL4:4; /* IMAL4 */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } IEMA1; /* */
+ union { /* IEMA2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IMAU8:8; /* IMAU8 */
+ } BIT; /* */
+ } IEMA2; /* */
+ union { /* IERCTL */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE RCTL:4; /* RCTL */
+ } BIT; /* */
+ } IERCTL; /* */
+ _UBYTE IERBFL; /* IERBFL */
+ _UBYTE wk1[1]; /* */
+ union { /* IELA1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ILAL8:8; /* ILAL8 */
+ } BIT; /* */
+ } IELA1; /* */
+ union { /* IELA2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE ILAU4:4; /* ILAU4 */
+ } BIT; /* */
+ } IELA2; /* */
+ union { /* IEFLG */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CMX:1; /* CMX */
+ _UBYTE MRQ:1; /* MRQ */
+ _UBYTE SRQ:1; /* SRQ */
+ _UBYTE SRE:1; /* SRE */
+ _UBYTE LCK:1; /* LCK */
+ _UBYTE :1; /* */
+ _UBYTE RSS:1; /* RSS */
+ _UBYTE GG:1; /* GG */
+ } BIT; /* */
+ } IEFLG; /* */
+ union { /* IETSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE TXS:1; /* TXS */
+ _UBYTE TXF:1; /* TXF */
+ _UBYTE :1; /* */
+ _UBYTE TXEAL:1; /* TXEAL */
+ _UBYTE TXETTME:1; /* TXETTME */
+ _UBYTE TXERO:1; /* TXERO */
+ _UBYTE TXEACK:1; /* TXEACK */
+ } BIT; /* */
+ } IETSR; /* */
+ union { /* IEIET */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE TXSE:1; /* TXSE */
+ _UBYTE TXFE:1; /* TXFE */
+ _UBYTE :1; /* */
+ _UBYTE TXEALE:1; /* TXEALE */
+ _UBYTE TXETTMEE:1; /* TXETTMEE */
+ _UBYTE TXEROE:1; /* TXEROE */
+ _UBYTE TXEACKE:1; /* TXEACKE */
+ } BIT; /* */
+ } IEIET; /* */
+ _UBYTE wk2[1]; /* */
+ union { /* IERSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RXBSY:1; /* RXBSY */
+ _UBYTE RXS:1; /* RXS */
+ _UBYTE RXF:1; /* RXF */
+ _UBYTE RXEDE:1; /* RXEDE */
+ _UBYTE RXEOVE:1; /* RXEOVE */
+ _UBYTE RXERTME:1; /* RXERTME */
+ _UBYTE RXEDLE:1; /* RXEDLE */
+ _UBYTE RXEPE:1; /* RXEPE */
+ } BIT; /* */
+ } IERSR; /* */
+ union { /* IEIER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RXBSYE:1; /* RXBSYE */
+ _UBYTE RXSE:1; /* RXSE */
+ _UBYTE RXFE:1; /* RXFE */
+ _UBYTE RXEDEE:1; /* RXEDEE */
+ _UBYTE RXEOVEE:1; /* RXEOVEE */
+ _UBYTE RXERTMEE:1; /* RXERTMEE */
+ _UBYTE RXEDLEE:1; /* RXEDLEE */
+ _UBYTE RXEPEE:1; /* RXEPEE */
+ } BIT; /* */
+ } IEIER; /* */
+ _UBYTE wk3[2]; /* */
+ union { /* IECKSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :3; /* */
+ _UBYTE CKS3:1; /* CKS3 */
+ _UBYTE :1; /* */
+ _UBYTE CKS:3; /* CKS */
+ } BIT; /* */
+ } IECKSR; /* */
+ _UBYTE wk4[231]; /* */
+ union { /* IETB001-128 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TB:8; /* TB */
+ } BIT; /* */
+ } IETB[128]; /* */
+ _UBYTE wk5[128]; /* */
+ union { /* IERB001-128 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RB:8; /* RB */
+ } BIT; /* */
+ } IERB[128]; /* */
+}; /* */
+struct st_spdif { /* struct SPDIF */
+ _UDWORD TLCA; /* TLCA */
+ _UDWORD TRCA; /* TRCA */
+ union { /* TLCS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :2; /* */
+ _UDWORD CLAC:2; /* CLAC */
+ _UDWORD FS:4; /* FS */
+ _UDWORD CHNO:4; /* CHNO */
+ _UDWORD SRCNO:4; /* SRCNO */
+ _UDWORD CATCD:8; /* CATCD */
+ _UDWORD :2; /* */
+ _UDWORD CTL:5; /* CTL */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } TLCS; /* */
+ union { /* TRCS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :2; /* */
+ _UDWORD CLAC:2; /* CLAC */
+ _UDWORD FS:4; /* FS */
+ _UDWORD CHNO:4; /* CHNO */
+ _UDWORD SRCNO:4; /* SRCNO */
+ _UDWORD CATCD:8; /* CATCD */
+ _UDWORD :2; /* */
+ _UDWORD CTL:5; /* CTL */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } TRCS; /* */
+ _UDWORD TUI; /* TUI */
+ _UDWORD RLCA; /* RLCA */
+ _UDWORD RRCA; /* RRCA */
+ union { /* RLCS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :2; /* */
+ _UDWORD CLAC:2; /* CLAC */
+ _UDWORD FS:4; /* FS */
+ _UDWORD CHNO:4; /* CHNO */
+ _UDWORD SRCNO:4; /* SRCNO */
+ _UDWORD CATCD:8; /* CATCD */
+ _UDWORD :2; /* */
+ _UDWORD CTL:5; /* CTL */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } RLCS; /* */
+ union { /* RRCS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :2; /* */
+ _UDWORD CLAC:2; /* CLAC */
+ _UDWORD FS:4; /* FS */
+ _UDWORD CHNO:4; /* CHNO */
+ _UDWORD SRCNO:4; /* SRCNO */
+ _UDWORD CATCD:8; /* CATCD */
+ _UDWORD :2; /* */
+ _UDWORD CTL:5; /* CTL */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } RRCS; /* */
+ _UDWORD RUI; /* RUI */
+ union { /* CTRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :3; /* */
+ _UDWORD CKS:1; /* CKS */
+ _UDWORD :1; /* */
+ _UDWORD PB:1; /* PB */
+ _UDWORD RASS:2; /* RASS */
+ _UDWORD TASS:2; /* TASS */
+ _UDWORD RDE:1; /* RDE */
+ _UDWORD TDE:1; /* TDE */
+ _UDWORD NCSI:1; /* NCSI */
+ _UDWORD AOS:1; /* AOS */
+ _UDWORD RME:1; /* RME */
+ _UDWORD TME:1; /* TME */
+ _UDWORD REIE:1; /* REIE */
+ _UDWORD TEIE:1; /* TEIE */
+ _UDWORD UBOI:1; /* UBOI */
+ _UDWORD UBUI:1; /* UBUI */
+ _UDWORD CREI:1; /* CREI */
+ _UDWORD PAEI:1; /* PAEI */
+ _UDWORD PREI:1; /* PREI */
+ _UDWORD CSEI:1; /* CSEI */
+ _UDWORD ABOI:1; /* ABOI */
+ _UDWORD ABUI:1; /* ABUI */
+ _UDWORD RUII:1; /* RUII */
+ _UDWORD TUII:1; /* TUII */
+ _UDWORD RCSI:1; /* RCSI */
+ _UDWORD RCBI:1; /* RCBI */
+ _UDWORD TCSI:1; /* TCSI */
+ _UDWORD TCBI:1; /* TCBI */
+ } BIT; /* */
+ } CTRL; /* */
+ union { /* STAT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :15; /* */
+ _UDWORD CMD:1; /* CMD */
+ _UDWORD RIS:1; /* RIS */
+ _UDWORD TIS:1; /* TIS */
+ _UDWORD UBO:1; /* UBO */
+ _UDWORD UBU:1; /* UBU */
+ _UDWORD CE:1; /* CE */
+ _UDWORD PARE:1; /* PARE */
+ _UDWORD PREE:1; /* PREE */
+ _UDWORD CSE:1; /* CSE */
+ _UDWORD ABO:1; /* ABO */
+ _UDWORD ABU:1; /* ABU */
+ _UDWORD RUIR:1; /* RUIR */
+ _UDWORD TUIR:1; /* TUIR */
+ _UDWORD CSRX:1; /* CSRX */
+ _UDWORD CBRX:1; /* CBRX */
+ _UDWORD CSTX:1; /* CSTX */
+ _UDWORD CBTX:1; /* CBTX */
+ } BIT; /* */
+ } STAT; /* */
+ _UDWORD TDAD; /* TDAD */
+ _UDWORD RDAD; /* RDAD */
+}; /* */
+struct st_romdec { /* struct ROMDEC */
+ union { /* CROMEN */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SUBC_EN:1; /* SUBC_EN */
+ _UBYTE CROM_EN:1; /* CROM_EN */
+ _UBYTE CROM_STP:1; /* CROM_STP */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } CROMEN; /* */
+ union { /* CROMSY0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SY_AUT:1; /* SY_AUT */
+ _UBYTE SY_IEN:1; /* SY_IEN */
+ _UBYTE SY_DEN:1; /* SY_DEN */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } CROMSY0; /* */
+ union { /* CROMCTL0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MD_DESC:1; /* MD_DESC */
+ _UBYTE :1; /* */
+ _UBYTE MD_AUTO:1; /* MD_AUTO */
+ _UBYTE MD_AUTOS1:1; /* MD_AUTOS1 */
+ _UBYTE MD_AUTOS2:1; /* MD_AUTOS2 */
+ _UBYTE MD_SEC:3; /* MD_SEC */
+ } BIT; /* */
+ } CROMCTL0; /* */
+ union { /* CROMCTL1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE M2F2EDC:1; /* M2F2EDC */
+ _UBYTE MD_DEC:3; /* MD_DEC */
+ _UBYTE :2; /* */
+ _UBYTE MD_PQREP:2; /* MD_PQREP */
+ } BIT; /* */
+ } CROMCTL1; /* */
+ _UBYTE wk0[1]; /* */
+ union { /* CROMCTL3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE STP_ECC:1; /* STP_ECC */
+ _UBYTE STP_EDC:1; /* STP_EDC */
+ _UBYTE :1; /* */
+ _UBYTE STP_MD:1; /* STP_MD */
+ _UBYTE STP_MIN:1; /* STP_MIN */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } CROMCTL3; /* */
+ union { /* CROMCTL4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE LINKOFF:1; /* LINKOFF */
+ _UBYTE LINK2:1; /* LINK2 */
+ _UBYTE :1; /* */
+ _UBYTE EROSEL:1; /* EROSEL */
+ _UBYTE NO_ECC:1; /* NO_ECC */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } CROMCTL4; /* */
+ union { /* CROMCTL5 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE MSF_LBA_SEL:1; /* MSF_LBA_SEL */
+ } BIT; /* */
+ } CROMCTL5; /* */
+ union { /* CROMST0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE ST_SYIL:1; /* ST_SYIL */
+ _UBYTE ST_SYNO:1; /* ST_SYNO */
+ _UBYTE ST_BLKS:1; /* ST_BLKS */
+ _UBYTE ST_BLKL:1; /* ST_BLKL */
+ _UBYTE ST_SECS:1; /* ST_SECS */
+ _UBYTE ST_SECL:1; /* ST_SECL */
+ } BIT; /* */
+ } CROMST0; /* */
+ union { /* CROMST1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE ER2_HEAD0:1; /* ER2_HEAD0 */
+ _UBYTE ER2_HEAD1:1; /* ER2_HEAD1 */
+ _UBYTE ER2_HEAD2:1; /* ER2_HEAD2 */
+ _UBYTE ER2_HEAD3:1; /* ER2_HEAD3 */
+ } BIT; /* */
+ } CROMST1; /* */
+ _UBYTE wk1[1]; /* */
+ union { /* CROMST3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ER2_SHEAD0:1; /* ER2_SHEAD0 */
+ _UBYTE ER2_SHEAD1:1; /* ER2_SHEAD1 */
+ _UBYTE ER2_SHEAD2:1; /* ER2_SHEAD2 */
+ _UBYTE ER2_SHEAD3:1; /* ER2_SHEAD3 */
+ _UBYTE ER2_SHEAD4:1; /* ER2_SHEAD4 */
+ _UBYTE ER2_SHEAD5:1; /* ER2_SHEAD5 */
+ _UBYTE ER2_SHEAD6:1; /* ER2_SHEAD6 */
+ _UBYTE ER2_SHEAD7:1; /* ER2_SHEAD7 */
+ } BIT; /* */
+ } CROMST3; /* */
+ union { /* CROMST4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE NG_MD:1; /* NG_MD */
+ _UBYTE NG_MDCMP1:1; /* NG_MDCMP1 */
+ _UBYTE NG_MDCMP2:1; /* NG_MDCMP2 */
+ _UBYTE NG_MDCMP3:1; /* NG_MDCMP3 */
+ _UBYTE NG_MDCMP4:1; /* NG_MDCMP4 */
+ _UBYTE NG_MDDEF:1; /* NG_MDDEF */
+ _UBYTE NG_MDTIM1:1; /* NG_MDTIM1 */
+ _UBYTE NG_MDTIM2:1; /* NG_MDTIM2 */
+ } BIT; /* */
+ } CROMST4; /* */
+ union { /* CROMST5 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ST_AMD:3; /* ST_AMD */
+ _UBYTE ST_MDX:1; /* ST_MDX */
+ _UBYTE LINK_ON:1; /* LINK_ON */
+ _UBYTE LINK_DET:1; /* LINK_DET */
+ _UBYTE LINK_SDET:1; /* LINK_SDET */
+ _UBYTE LINK_OUT1:1; /* LINK_OUT1 */
+ } BIT; /* */
+ } CROMST5; /* */
+ union { /* CROMST6 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ST_ERR:1; /* ST_ERR */
+ _UBYTE :1; /* */
+ _UBYTE ST_ECCABT:1; /* ST_ECCABT */
+ _UBYTE ST_ECCNG:1; /* ST_ECCNG */
+ _UBYTE ST_ECCP:1; /* ST_ECCP */
+ _UBYTE ST_ECCQ:1; /* ST_ECCQ */
+ _UBYTE ST_EDC1:1; /* ST_EDC1 */
+ _UBYTE ST_EDC2:1; /* ST_EDC2 */
+ } BIT; /* */
+ } CROMST6; /* */
+ _UBYTE wk2[5]; /* */
+ union { /* CBUFST0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BUF_REF:1; /* BUF_REF */
+ _UBYTE BUF_ACT:1; /* BUF_ACT */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } CBUFST0; /* */
+ union { /* CBUFST1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BUF_ECC:1; /* BUF_ECC */
+ _UBYTE BUF_EDC:1; /* BUF_EDC */
+ _UBYTE :1; /* */
+ _UBYTE BUF_MD:1; /* BUF_MD */
+ _UBYTE BUF_MIN:1; /* BUF_MIN */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } CBUFST1; /* */
+ union { /* CBUFST2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BUF_NG:1; /* BUF_NG */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } CBUFST2; /* */
+ _UBYTE wk3[1]; /* */
+ _UBYTE HEAD00; /* HEAD00 */
+ _UBYTE HEAD01; /* HEAD01 */
+ _UBYTE HEAD02; /* HEAD02 */
+ _UBYTE HEAD03; /* HEAD03 */
+ _UBYTE SHEAD00; /* SHEAD00 */
+ _UBYTE SHEAD01; /* SHEAD01 */
+ _UBYTE SHEAD02; /* SHEAD02 */
+ _UBYTE SHEAD03; /* SHEAD03 */
+ _UBYTE SHEAD04; /* SHEAD04 */
+ _UBYTE SHEAD05; /* SHEAD05 */
+ _UBYTE SHEAD06; /* SHEAD06 */
+ _UBYTE SHEAD07; /* SHEAD07 */
+ _UBYTE HEAD20; /* HEAD20 */
+ _UBYTE HEAD21; /* HEAD21 */
+ _UBYTE HEAD22; /* HEAD22 */
+ _UBYTE HEAD23; /* HEAD23 */
+ _UBYTE SHEAD20; /* SHEAD20 */
+ _UBYTE SHEAD21; /* SHEAD21 */
+ _UBYTE SHEAD22; /* SHEAD22 */
+ _UBYTE SHEAD23; /* SHEAD23 */
+ _UBYTE SHEAD24; /* SHEAD24 */
+ _UBYTE SHEAD25; /* SHEAD25 */
+ _UBYTE SHEAD26; /* SHEAD26 */
+ _UBYTE SHEAD27; /* SHEAD27 */
+ _UBYTE wk4[16]; /* */
+ union { /* CBUFCTL0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CBUF_AUT:1; /* CBUF_AUT */
+ _UBYTE CBUF_EN:1; /* CBUF_EN */
+ _UBYTE CBUF_LINK:1; /* CBUF_LINK */
+ _UBYTE CBUF_MD:2; /* CBUF_MD */
+ _UBYTE CBUF_TS:1; /* CBUF_TS */
+ _UBYTE CBUF_Q:1; /* CBUF_Q */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } CBUFCTL0; /* */
+ _UBYTE CBUFCTL1; /* CBUFCTL1 */
+ _UBYTE CBUFCTL2; /* CBUFCTL2 */
+ _UBYTE CBUFCTL3; /* CBUFCTL3 */
+ _UBYTE wk5[1]; /* */
+ union { /* CROMST0M */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE ST_SYILM:1; /* ST_SYILM */
+ _UBYTE ST_SYNOM:1; /* ST_SYNOM */
+ _UBYTE ST_BLKSM:1; /* ST_BLKSM */
+ _UBYTE ST_BLKLM:1; /* ST_BLKLM */
+ _UBYTE ST_SECSM:1; /* ST_SECSM */
+ _UBYTE ST_SECLM:1; /* ST_SECLM */
+ } BIT; /* */
+ } CROMST0M; /* */
+ _UBYTE wk6[186]; /* */
+ union { /* ROMDECRST */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE LOGICRST:1; /* LOGICRST */
+ _UBYTE RAMRST:1; /* RAMRST */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } ROMDECRST; /* */
+ union { /* RSTSTAT */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RAMCLRST:1; /* RAMCLRST */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } RSTSTAT; /* */
+ union { /* SSI */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BYTEND:1; /* BYTEND */
+ _UBYTE BITEND:1; /* BITEND */
+ _UBYTE BUFEND0:2; /* BUFEND0 */
+ _UBYTE BUFEND1:2; /* BUFEND1 */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } SSI; /* */
+ _UBYTE wk7[5]; /* */
+ union { /* INTHOLD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE ISEC:1; /* ISEC */
+ _UBYTE ITARG:1; /* ITARG */
+ _UBYTE ISY:1; /* ISY */
+ _UBYTE IERR:1; /* IERR */
+ _UBYTE IBUF:1; /* IBUF */
+ _UBYTE IREADY:1; /* IREADY */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } INTHOLD; /* */
+ union { /* INHINT */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE INHISEC:1; /* INHISEC */
+ _UBYTE INHITARG:1; /* INHITARG */
+ _UBYTE INHISY:1; /* INHISY */
+ _UBYTE INHIERR:1; /* INHIERR */
+ _UBYTE INHIBUF:1; /* INHIBUF */
+ _UBYTE INHIREADY:1; /* INHIREADY */
+ _UBYTE PREINHREQDM:1; /* PREINHREQDM */
+ _UBYTE PREINHIREADY:1; /* PREINHIREADY */
+ } BIT; /* */
+ } INHINT; /* */
+ _UBYTE wk8[246]; /* */
+ _UDWORD STRMDIN; /* STRMDIN */
+ _UWORD STRMDOUT; /* STRMDOUT */
+};
+
+
+#if 0 /* Viodefine.h‚ÌADC’è‹`‚ð—p‚¢‚邽‚ß•s—v */
+ /* */
+struct st_adc { /* struct ADC */
+ union { /* ADDRA */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRA; /* */
+ union { /* ADDRB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRB; /* */
+ union { /* ADDRC */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRC; /* */
+ union { /* ADDRD */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRD; /* */
+ union { /* ADDRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRE; /* */
+ union { /* ADDRF */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRF; /* */
+ union { /* ADDRG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRG; /* */
+ union { /* ADDRH */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } ADDRH; /* */
+ _UBYTE wk0[16]; /* */
+ union { /* ADCSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD ADF:1; /* ADF */
+ _UWORD ADIE:1; /* ADIE */
+ _UWORD ADST:1; /* ADST */
+ _UWORD TRGS:4; /* TRGS */
+ _UWORD CKS:3; /* CKS */
+ _UWORD MDS:3; /* MDS */
+ _UWORD CH:3; /* CH */
+ } BIT; /* */
+ } ADCSR; /* */
+}; /* */
+#endif
+
+
+
+struct st_flctl { /* struct FLCTL */
+ union { /* FLCMNCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :10; /* */
+ _UDWORD BUSYON:1; /* BUSYON */
+ _UDWORD :2; /* */
+ _UDWORD SNAND:1; /* SNAND */
+ _UDWORD QTSEL:1; /* QTSEL */
+ _UDWORD :5; /* */
+ _UDWORD ACM:2; /* ACM */
+ _UDWORD NANDWF:1; /* NANDWF */
+ _UDWORD :5; /* */
+ _UDWORD CE:1; /* CE */
+ _UDWORD :3; /* */
+ } BIT; /* */
+ } FLCMNCR; /* */
+ union { /* FLCMDCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ADRCNT2:1; /* ADRCNT2 */
+ _UDWORD SCTCNT_:4; /* SCTCNT */
+ _UDWORD ADRMD:1; /* ADRMD */
+ _UDWORD CDSRC:1; /* CDSRC */
+ _UDWORD DOSR:1; /* DOSR */
+ _UDWORD :2; /* */
+ _UDWORD SELRW:1; /* SELRW */
+ _UDWORD DOADR:1; /* DOADR */
+ _UDWORD ADRCNT:2; /* ADRCNT */
+ _UDWORD DOCMD2:1; /* DOCMD2 */
+ _UDWORD DOCMD1:1; /* DOCMD1 */
+ _UDWORD SCTCNT:16; /* SCTCNT */
+ } BIT; /* */
+ } FLCMDCR; /* */
+ union { /* FLCMCDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD CMD2:8; /* CMD2 */
+ _UDWORD CMD1:8; /* CMD1 */
+ } BIT; /* */
+ } FLCMCDR; /* */
+ _UDWORD FLADR; /* FLADR */
+ _UDWORD FLDATAR; /* FLDATAR */
+ union { /* FLDTCNTR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECFLW:8; /* ECFLW */
+ _UDWORD DTFLW:8; /* DTFLW */
+ _UDWORD :4; /* */
+ _UDWORD DTCNT:12; /* DTCNT */
+ } BIT; /* */
+ } FLDTCNTR; /* */
+ union { /* FLINTDMACR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :10; /* */
+ _UDWORD FIFOTRG:2; /* FIFOTRG */
+ _UDWORD AC1CLR:1; /* AC1CLR */
+ _UDWORD AC0CLR:1; /* AC0CLR */
+ _UDWORD DREQ1EN:1; /* DREQ1EN */
+ _UDWORD DREQ0EN:1; /* DREQ0EN */
+ _UDWORD :7; /* */
+ _UDWORD STERB:1; /* STERB */
+ _UDWORD BTOERB:1; /* BTOERB */
+ _UDWORD TRREQF1:1; /* TRREQF1 */
+ _UDWORD TRREQF0:1; /* TRREQF0 */
+ _UDWORD STERINTE:1; /* STERINTE */
+ _UDWORD RBERINTE:1; /* RBERINTE */
+ _UDWORD TEINTE:1; /* TEINTE */
+ _UDWORD TRINTE1:1; /* TRINTE1 */
+ _UDWORD TRINTE0:1; /* TRINTE0 */
+ } BIT; /* */
+ } FLINTDMACR; /* */
+ union { /* FLBSYTMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD RBTMOUT:20; /* RBTMOUT */
+ } BIT; /* */
+ } FLBSYTMR; /* */
+ union { /* FLBSYCNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD STAT:8; /* STAT */
+ _UDWORD :4; /* */
+ _UDWORD RBTIMCNT:20; /* RBTIMCNT */
+ } BIT; /* */
+ } FLBSYCNT; /* */
+ _UBYTE wk0[8]; /* */
+ union { /* FLTRCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE TRSTAT:1; /* TRSTAT */
+ _UBYTE TREND:1; /* TREND */
+ _UBYTE TRSTRT:1; /* TRSTRT */
+ } BIT; /* */
+ } FLTRCR; /* */
+ _UBYTE wk1[11]; /* */
+ union { /* FLHOLDCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD HOLDEN:1; /* HOLDEN */
+ } BIT; /* */
+ } FLHOLDCR; /* */
+ _UDWORD FLADR2; /* FLADR2 */
+ _UBYTE wk2[16]; /* */
+ _UDWORD FLDTFIFO; /* FLDTFIFO */
+ _UBYTE wk3[12]; /* */
+ _UDWORD FLECFIFO; /* FLECFIFO */
+}; /* */
+ #if 0
+struct st_usb { /* struct USB */
+ union { /* SYSCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD SCKE:1; /* SCKE */
+ _UWORD :2; /* */
+ _UWORD HSE:1; /* HSE */
+ _UWORD DCFM:1; /* DCFM */
+ _UWORD DRPD:1; /* DRPD */
+ _UWORD DPRPU:1; /* DPRPU */
+ _UWORD UCKFSEL:1; /* UCKFSEL */
+ _UWORD UCKPSEL:1; /* UCKPSEL */
+ _UWORD UPLLE:1; /* UPLLE */
+ _UWORD USBE:1; /* USBE */
+ } BIT; /* */
+ } SYSCFG; /* */
+ union { /* BUSWAIT */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :12; /* */
+ _UWORD BWAIT:4; /* BWAIT */
+ } BIT; /* */
+ } BUSWAIT; /* */
+ union { /* SYSSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :14; /* */
+ _UWORD LNST:2; /* LNST */
+ } BIT; /* */
+ } SYSSTS; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* DVSTCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD WKUP:1; /* WKUP */
+ _UWORD RWUPE:1; /* RWUPE */
+ _UWORD USBRST:1; /* USBRST */
+ _UWORD RESUME:1; /* RESUME */
+ _UWORD UACT:1; /* UACT */
+ _UWORD :1; /* */
+ _UWORD RHST:3; /* RHST */
+ } BIT; /* */
+ } DVSTCTR; /* */
+ _UBYTE wk1[2]; /* */
+ union { /* TESTMODE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :12; /* */
+ _UWORD UTST:4; /* UTST */
+ } BIT; /* */
+ } TESTMODE; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* D0FBCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD TENDE:1; /* TENDE */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } D0FBCFG; /* */
+ union { /* D1FBCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD TENDE:1; /* TENDE */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } D1FBCFG; /* */
+ union { /* CFIFO */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD; /* Word Access */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } CFIFO; /* */
+ union { /* D0FIFO */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD; /* Word Access */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFO; /* */
+ union { /* D1FIFO */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD; /* Word Access */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFO; /* */
+ union { /* CFIFOSEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD RCNT:1; /* RCNT */
+ _UWORD REW:1; /* REW */
+ _UWORD :2; /* */
+ _UWORD MBW:2; /* MBW */
+ _UWORD :1; /* */
+ _UWORD BIGEND:1; /* BIGEND */
+ _UWORD :2; /* */
+ _UWORD ISEL:1; /* ISEL */
+ _UWORD :1; /* */
+ _UWORD CURPIPE:4; /* CURPIPE */
+ } BIT; /* */
+ } CFIFOSEL; /* */
+ union { /* CFIFOCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BVAL:1; /* BVAL */
+ _UWORD BCLR:1; /* BCLR */
+ _UWORD FRDY:1; /* FRDY */
+ _UWORD :1; /* */
+ _UWORD DTLN:12; /* DTLN */
+ } BIT; /* */
+ } CFIFOCTR; /* */
+ _UBYTE wk3[4]; /* */
+ union { /* D0FIFOSEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD RCNT:1; /* RCNT */
+ _UWORD REW:1; /* REW */
+ _UWORD DCLRM:1; /* DCLRM */
+ _UWORD DREQE:1; /* DREQE */
+ _UWORD MBW:2; /* MBW */
+ _UWORD :1; /* */
+ _UWORD BIGEND:1; /* BIGEND */
+ _UWORD :4; /* */
+ _UWORD CURPIPE:4; /* CURPIPE */
+ } BIT; /* */
+ } D0FIFOSEL; /* */
+ union { /* D0FIFOCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BVAL:1; /* BVAL */
+ _UWORD BCLR:1; /* BCLR */
+ _UWORD FRDY:1; /* FRDY */
+ _UWORD :1; /* */
+ _UWORD DTLN:12; /* DTLN */
+ } BIT; /* */
+ } D0FIFOCTR; /* */
+ union { /* D1FIFOSEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD RCNT:1; /* RCNT */
+ _UWORD REW:1; /* REW */
+ _UWORD DCLRM:1; /* DCLRM */
+ _UWORD DREQE:1; /* DREQE */
+ _UWORD MBW:2; /* MBW */
+ _UWORD :1; /* */
+ _UWORD BIGEND:1; /* BIGEND */
+ _UWORD :4; /* */
+ _UWORD CURPIPE:4; /* CURPIPE */
+ } BIT; /* */
+ } D1FIFOSEL; /* */
+ union { /* D1FIFOCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BVAL:1; /* BVAL */
+ _UWORD BCLR:1; /* BCLR */
+ _UWORD FRDY:1; /* FRDY */
+ _UWORD :1; /* */
+ _UWORD DTLN:12; /* DTLN */
+ } BIT; /* */
+ } D1FIFOCTR; /* */
+ union { /* INTENB0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD VBSE:1; /* VBSE */
+ _UWORD RSME:1; /* RSME */
+ _UWORD SOFE:1; /* SOFE */
+ _UWORD DVSE:1; /* DVSE */
+ _UWORD CTRE:1; /* CTRE */
+ _UWORD BEMPE:1; /* BEMPE */
+ _UWORD NRDYE:1; /* NRDYE */
+ _UWORD BRDYE:1; /* BRDYE */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } INTENB0; /* */
+ union { /* INTENB1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD BCHGE:1; /* BCHGE */
+ _UWORD :1; /* */
+ _UWORD DTCHE:1; /* DTCHE */
+ _UWORD ATTCHE:1; /* ATTCHE */
+ _UWORD :4; /* */
+ _UWORD EOFERRE:1; /* EOFERRE */
+ _UWORD SIGNE:1; /* SIGNE */
+ _UWORD SACKE:1; /* SACKE */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } INTENB1; /* */
+ _UBYTE wk4[2]; /* */
+ union { /* BRDYENB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PIPE9BRDYE:1; /* PIPE9BRDYE */
+ _UWORD PIPE8BRDYE:1; /* PIPE8BRDYE */
+ _UWORD PIPE7BRDYE:1; /* PIPE7BRDYE */
+ _UWORD PIPE6BRDYE:1; /* PIPE6BRDYE */
+ _UWORD PIPE5BRDYE:1; /* PIPE5BRDYE */
+ _UWORD PIPE4BRDYE:1; /* PIPE4BRDYE */
+ _UWORD PIPE3BRDYE:1; /* PIPE3BRDYE */
+ _UWORD PIPE2BRDYE:1; /* PIPE2BRDYE */
+ _UWORD PIPE1BRDYE:1; /* PIPE1BRDYE */
+ _UWORD PIPE0BRDYE:1; /* PIPE0BRDYE */
+ } BIT; /* */
+ } BRDYENB; /* */
+ union { /* NRDYENB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PIPE9NRDYE:1; /* PIPE9NRDYE */
+ _UWORD PIPE8NRDYE:1; /* PIPE8NRDYE */
+ _UWORD PIPE7NRDYE:1; /* PIPE7NRDYE */
+ _UWORD PIPE6NRDYE:1; /* PIPE6NRDYE */
+ _UWORD PIPE5NRDYE:1; /* PIPE5NRDYE */
+ _UWORD PIPE4NRDYE:1; /* PIPE4NRDYE */
+ _UWORD PIPE3NRDYE:1; /* PIPE3NRDYE */
+ _UWORD PIPE2NRDYE:1; /* PIPE2NRDYE */
+ _UWORD PIPE1NRDYE:1; /* PIPE1NRDYE */
+ _UWORD PIPE0NRDYE:1; /* PIPE0NRDYE */
+ } BIT; /* */
+ } NRDYENB; /* */
+ union { /* BEMPENB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PIPE9BEMPE:1; /* PIPE9BEMPE */
+ _UWORD PIPE8BEMPE:1; /* PIPE8BEMPE */
+ _UWORD PIPE7BEMPE:1; /* PIPE7BEMPE */
+ _UWORD PIPE6BEMPE:1; /* PIPE6BEMPE */
+ _UWORD PIPE5BEMPE:1; /* PIPE5BEMPE */
+ _UWORD PIPE4BEMPE:1; /* PIPE4BEMPE */
+ _UWORD PIPE3BEMPE:1; /* PIPE3BEMPE */
+ _UWORD PIPE2BEMPE:1; /* PIPE2BEMPE */
+ _UWORD PIPE1BEMPE:1; /* PIPE1BEMPE */
+ _UWORD PIPE0BEMPE:1; /* PIPE0BEMPE */
+ } BIT; /* */
+ } BEMPENB; /* */
+ union { /* SOFCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD TRNENSEL:1; /* TRNENSEL */
+ _UWORD :1; /* */
+ _UWORD BRDYM:1; /* BRDYM */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } SOFCFG; /* */
+ _UBYTE wk5[2]; /* */
+ union { /* INTSTS0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD VBINT:1; /* VBINT */
+ _UWORD RESM:1; /* RESM */
+ _UWORD SOFR:1; /* SOFR */
+ _UWORD DVST:1; /* DVST */
+ _UWORD CTRT:1; /* CTRT */
+ _UWORD BEMP:1; /* BEMP */
+ _UWORD NRDY:1; /* NRDY */
+ _UWORD BRDY:1; /* BRDY */
+ _UWORD VBSTS:1; /* VBSTS */
+ _UWORD DVSQ:3; /* DVSQ */
+ _UWORD VALID:1; /* VALID */
+ _UWORD CTSQ:3; /* CTSQ */
+ } BIT; /* */
+ } INTSTS0; /* */
+ union { /* INTSTS1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD BCHG:1; /* BCHG */
+ _UWORD :1; /* */
+ _UWORD DTCH:1; /* DTCH */
+ _UWORD ATTCH:1; /* ATTCH */
+ _UWORD :4; /* */
+ _UWORD EOFERR:1; /* EOFERR */
+ _UWORD SIGN:1; /* SIGN */
+ _UWORD SACK:1; /* SACK */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } INTSTS1; /* */
+ _UBYTE wk6[2]; /* */
+ union { /* BRDYSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PIPE9BRDY:1; /* PIPE9BRDY */
+ _UWORD PIPE8BRDY:1; /* PIPE8BRDY */
+ _UWORD PIPE7BRDY:1; /* PIPE7BRDY */
+ _UWORD PIPE6BRDY:1; /* PIPE6BRDY */
+ _UWORD PIPE5BRDY:1; /* PIPE5BRDY */
+ _UWORD PIPE4BRDY:1; /* PIPE4BRDY */
+ _UWORD PIPE3BRDY:1; /* PIPE3BRDY */
+ _UWORD PIPE2BRDY:1; /* PIPE2BRDY */
+ _UWORD PIPE1BRDY:1; /* PIPE1BRDY */
+ _UWORD PIPE0BRDY:1; /* PIPE0BRDY */
+ } BIT; /* */
+ } BRDYSTS; /* */
+ union { /* NRDYSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PIPE9NRDY:1; /* PIPE9NRDY */
+ _UWORD PIPE8NRDY:1; /* PIPE8NRDY */
+ _UWORD PIPE7NRDY:1; /* PIPE7NRDY */
+ _UWORD PIPE6NRDY:1; /* PIPE6NRDY */
+ _UWORD PIPE5NRDY:1; /* PIPE5NRDY */
+ _UWORD PIPE4NRDY:1; /* PIPE4NRDY */
+ _UWORD PIPE3NRDY:1; /* PIPE3NRDY */
+ _UWORD PIPE2NRDY:1; /* PIPE2NRDY */
+ _UWORD PIPE1NRDY:1; /* PIPE1NRDY */
+ _UWORD PIPE0NRDY:1; /* PIPE0NRDY */
+ } BIT; /* */
+ } NRDYSTS; /* */
+ union { /* BEMPSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PIPE9BEMP:1; /* PIPE9BEMP */
+ _UWORD PIPE8BEMP:1; /* PIPE8BEMP */
+ _UWORD PIPE7BEMP:1; /* PIPE7BEMP */
+ _UWORD PIPE6BEMP:1; /* PIPE6BEMP */
+ _UWORD PIPE5BEMP:1; /* PIPE5BEMP */
+ _UWORD PIPE4BEMP:1; /* PIPE4BEMP */
+ _UWORD PIPE3BEMP:1; /* PIPE3BEMP */
+ _UWORD PIPE2BEMP:1; /* PIPE2BEMP */
+ _UWORD PIPE1BEMP:1; /* PIPE1BEMP */
+ _UWORD PIPE0BEMP:1; /* PIPE0BEMP */
+ } BIT; /* */
+ } BEMPSTS; /* */
+ union { /* FRMNUM */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD OVRN:1; /* OVRN */
+ _UWORD CRCE:1; /* CRCE */
+ _UWORD :3; /* */
+ _UWORD FRNM:11; /* FRNM */
+ } BIT; /* */
+ } FRMNUM; /* */
+ union { /* UFRMNUM */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :13; /* */
+ _UWORD UFRNM:3; /* UFRNM */
+ } BIT; /* */
+ } UFRMNUM; /* */
+ union { /* USBADDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :9; /* */
+ _UWORD USBADDR:7; /* USBADDR */
+ } BIT; /* */
+ } USBADDR; /* */
+ _UBYTE wk7[2]; /* */
+ union { /* USBREQ */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BREQUEST:8; /* BREQUEST */
+ _UWORD BMREQUESTTYPE:8; /* BMREQUESTTYPE */
+ } BIT; /* */
+ } USBREQ; /* */
+ _UWORD USBVAL; /* USBVAL */
+ _UWORD USBINDX; /* USBINDX */
+ _UWORD USBLENG; /* USBLENG */
+ union { /* DCPCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD DIR:1; /* DIR */
+ _UWORD :4; /* */
+ } BIT; /* */
+ } DCPCFG; /* */
+ union { /* DCPMAXP */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DEVSEL:4; /* DEVSEL */
+ _UWORD :5; /* */
+ _UWORD MXPS:7; /* MXPS */
+ } BIT; /* */
+ } DCPMAXP; /* */
+ union { /* DCPCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD SUREQ:1; /* SUREQ */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD SUREQCLR:1; /* SUREQCLR */
+ _UWORD :2; /* */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD PINGE:1; /* PINGE */
+ _UWORD :1; /* */
+ _UWORD CCPL:1; /* CCPL */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } DCPCTR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* PIPESEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :12; /* */
+ _UWORD PIPESEL:4; /* PIPESEL */
+ } BIT; /* */
+ } PIPESEL; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* PIPECFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TYPE:2; /* TYPE */
+ _UWORD :3; /* */
+ _UWORD BFRE:1; /* BFRE */
+ _UWORD DBLB:1; /* DBLB */
+ _UWORD CNTMD:1; /* CNTMD */
+ _UWORD SHTNAK:1; /* SHTNAK */
+ _UWORD :2; /* */
+ _UWORD DIR:1; /* DIR */
+ _UWORD EPNUM:4; /* EPNUM */
+ } BIT; /* */
+ } PIPECFG; /* */
+ union { /* PIPEBUF */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD BUFSIZE:5; /* BUFSIZE */
+ _UWORD :3; /* */
+ _UWORD BUFNMB:7; /* BUFNMB */
+ } BIT; /* */
+ } PIPEBUF; /* */
+ union { /* PIPEMAXP */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DEVSEL:4; /* DEVSEL */
+ _UWORD :1; /* */
+ _UWORD MXPS:11; /* MXPS */
+ } BIT; /* */
+ } PIPEMAXP; /* */
+ union { /* PIPEPERI */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD IFIS:1; /* IFIS */
+ _UWORD :9; /* */
+ _UWORD IITV:3; /* IITV */
+ } BIT; /* */
+ } PIPEPERI; /* */
+ union { /* PIPE1CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :1; /* */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE1CTR; /* */
+ union { /* PIPE2CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :1; /* */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE2CTR; /* */
+ union { /* PIPE3CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :1; /* */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE3CTR; /* */
+ union { /* PIPE4CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :1; /* */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE4CTR; /* */
+ union { /* PIPE5CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :1; /* */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE5CTR; /* */
+ union { /* PIPE6CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD :1; /* */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :2; /* */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE6CTR; /* */
+ union { /* PIPE7CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD :1; /* */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :2; /* */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE7CTR; /* */
+ union { /* PIPE8CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD :1; /* */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :2; /* */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE8CTR; /* */
+ union { /* PIPE9CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BSTS:1; /* BSTS */
+ _UWORD :1; /* */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD :2; /* */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD :3; /* */
+ _UWORD PID:2; /* PID */
+ } BIT; /* */
+ } PIPE9CTR; /* */
+ _UBYTE wk10[14]; /* */
+ union { /* PIPE1TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } PIPE1TRE; /* */
+ _UWORD PIPE1TRN; /* PIPE1TRN */
+ union { /* PIPE2TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } PIPE2TRE; /* */
+ _UWORD PIPE2TRN; /* PIPE2TRN */
+ union { /* PIPE3TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } PIPE3TRE; /* */
+ _UWORD PIPE3TRN; /* PIPE3TRN */
+ union { /* PIPE4TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } PIPE4TRE; /* */
+ _UWORD PIPE4TRN; /* PIPE4TRN */
+ union { /* PIPE5TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } PIPE5TRE; /* */
+ _UWORD PIPE5TRN; /* PIPE5TRN */
+ _UBYTE wk11[44]; /* */
+ union { /* DEVADD0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD0; /* */
+ union { /* DEVADD1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD1; /* */
+ union { /* DEVADD2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD2; /* */
+ union { /* DEVADD3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD3; /* */
+ union { /* DEVADD4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD4; /* */
+ union { /* DEVADD5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD5; /* */
+ union { /* DEVADD6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD6; /* */
+ union { /* DEVADD7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD7; /* */
+ union { /* DEVADD8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD8; /* */
+ union { /* DEVADD9 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADD9; /* */
+ union { /* DEVADDA */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } DEVADDA; /* */
+}; /* */
+ #endif
+struct st_vdc4 { /* struct VDC4 */
+ union { /* INP_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD INP_EXT_UPDATE:1; /* INP_EXT_UPDATE */
+ _UDWORD :3; /* */
+ _UDWORD INP_IMG_UPDATE:1; /* INP_IMG_UPDATE */
+ } BIT; /* */
+ } INP_UPDATE; /* */
+ union { /* INP_SEL_CNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD INP_SEL:1; /* INP_SEL */
+ _UWORD :4; /* */
+ _UWORD :1; /* */
+ _UWORD INP_FORMAT:3; /* INP_FORMAT */
+ _UWORD :3; /* */
+ _UWORD INP_PXD_EDGE:1; /* INP_PXD_EDGE */
+ _UWORD :3; /* */
+ _UWORD INP_VS_EDGE:1; /* INP_VS_EDGE */
+ _UWORD :3; /* */
+ _UWORD INP_HS_EDGE:1; /* INP_HS_EDGE */
+ } BIT; /* */
+ } INP_SEL_CNT; /* */
+ union { /* INP_EXT_SYNC_CNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD INP_ENDIAN_ON:1; /* INP_ENDIAN_ON */
+ _UWORD :3; /* */
+ _UWORD INP_SWAP_ON:1; /* INP_SWAP_ON */
+ _UWORD :3; /* */
+ _UWORD INP_VS_INV:1; /* INP_VS_INV */
+ _UWORD :3; /* */
+ _UWORD INP_HS_INV:1; /* INP_HS_INV */
+ _UWORD :7; /* */
+ _UWORD INP_H_EDGE_SEL:1; /* INP_H_EDGE_SEL */
+ _UWORD :3; /* */
+ _UWORD INP_F525_625:1; /* INP_F525_625 */
+ _UWORD :2; /* */
+ _UWORD INP_H_POS:2; /* INP_H_POS */
+ } BIT; /* */
+ } INP_EXT_SYNC_CNT; /* */
+ union { /* INP_VSYNC_PH_ADJ */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD INP_FH50:10; /* INP_FH50 */
+ _UWORD :6; /* */
+ _UWORD INP_FH25:10; /* INP_FH25 */
+ } BIT; /* */
+ } INP_VSYNC_PH_ADJ; /* */
+ union { /* INP_DLY_ADJ */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD INP_VS_DLY_L:3; /* INP_VS_DLY_L */
+ _UWORD INP_FLD_DLY:8; /* INP_FLD_DLY */
+ _UWORD INP_VS_DLY:8; /* INP_VS_DLY */
+ _UWORD INP_HS_DLY:8; /* INP_HS_DLY */
+ } BIT; /* */
+ } INP_DLY_ADJ; /* */
+ _UBYTE wk0[108]; /* */
+ union { /* IMGCNT_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD IMGCNT_VEN:1; /* IMGCNT_VEN */
+ } BIT; /* */
+ } IMGCNT_UPDATE; /* */
+ union { /* IMGCNT_NR_CNT0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD NR1D_MD:1; /* NR1D_MD */
+ _UWORD :3; /* */
+ _UWORD NR1D_ON:1; /* NR1D_ON */
+ _UWORD :1; /* */
+ _UWORD NR1D_Y_TH:7; /* NR1D_Y_TH */
+ _UWORD :2; /* */
+ _UWORD NR1D_Y_TAP:2; /* NR1D_Y_TAP */
+ _UWORD :2; /* */
+ _UWORD NR1D_Y_GAIN:2; /* NR1D_Y_GAIN */
+ } BIT; /* */
+ } IMGCNT_NR_CNT0; /* */
+ union { /* IMGCNT_NR_CNT1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD NR1D_CB_TH:7; /* NR1D_CB_TH */
+ _UWORD :2; /* */
+ _UWORD NR1D_CB_TAP:2; /* NR1D_CB_TAP */
+ _UWORD :2; /* */
+ _UWORD NR1D_CB_GAIN:2; /* NR1D_CB_GAIN */
+ _UWORD :1; /* */
+ _UWORD NR1D_CR_TH:7; /* NR1D_CR_TH */
+ _UWORD :2; /* */
+ _UWORD NR1D_CR_TAP:2; /* NR1D_CR_TAP */
+ _UWORD :2; /* */
+ _UWORD NR1D_CR_GAIN:2; /* NR1D_CR_GAIN */
+ } BIT; /* */
+ } IMGCNT_NR_CNT1; /* */
+ _UBYTE wk1[20]; /* */
+ union { /* IMGCNT_MTX_MODE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :30; /* */
+ _UDWORD IMGCNT_MTX_MD:2; /* IMGCNT_MTX_MD */
+ } BIT; /* */
+ } IMGCNT_MTX_MODE; /* */
+ union { /* IMGCNT_MTX_YG_ADJ0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD IMGCNT_MTX_YG:8; /* IMGCNT_MTX_YG */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_GG:11; /* IMGCNT_MTX_GG */
+ } BIT; /* */
+ } IMGCNT_MTX_YG_ADJ0; /* */
+ union { /* IMGCNT_MTX_YG_ADJ1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_GB:11; /* IMGCNT_MTX_GB */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_GR:11; /* IMGCNT_MTX_GR */
+ } BIT; /* */
+ } IMGCNT_MTX_YG_ADJ1; /* */
+ union { /* IMGCNT_MTX_CBB_ADJ0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD IMGCNT_MTX_B:8; /* IMGCNT_MTX_B */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_BG:11; /* IMGCNT_MTX_BG */
+ } BIT; /* */
+ } IMGCNT_MTX_CBB_ADJ0; /* */
+ union { /* IMGCNT_MTX_CBB_ADJ1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_BB:11; /* IMGCNT_MTX_BB */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_BR:11; /* IMGCNT_MTX_BR */
+ } BIT; /* */
+ } IMGCNT_MTX_CBB_ADJ1; /* */
+ union { /* IMGCNT_MTX_CRR_ADJ0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD IMGCNT_MTX_R:8; /* IMGCNT_MTX_R */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_RG:11; /* IMGCNT_MTX_RG */
+ } BIT; /* */
+ } IMGCNT_MTX_CRR_ADJ0; /* */
+ union { /* IMGCNT_MTX_CRR_ADJ1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_RB:11; /* IMGCNT_MTX_RB */
+ _UWORD :5; /* */
+ _UWORD IMGCNT_MTX_RR:11; /* IMGCNT_MTX_RR */
+ } BIT; /* */
+ } IMGCNT_MTX_CRR_ADJ1; /* */
+ _UBYTE wk2[68]; /* */
+ union { /* SCL0_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :18; /* */
+ _UDWORD SCL0_VEN_D:1; /* SCL0_VEN_D */
+ _UDWORD SCL0_VEN_C:1; /* SCL0_VEN_C */
+ _UDWORD :3; /* */
+ _UDWORD SCL0_UPDATE:1; /* SCL0_UPDATE */
+ _UDWORD :3; /* */
+ _UDWORD SCL0_VEN_B:1; /* SCL0_VEN_B */
+ _UDWORD :3; /* */
+ _UDWORD SCL0_VEN_A:1; /* SCL0_VEN_A */
+ } BIT; /* */
+ } SCL0_UPDATE; /* */
+ union { /* SCL0_FRC1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD RES_VMASK:16; /* RES_VMASK */
+ _UWORD :15; /* */
+ _UWORD RES_VMASK_ON:1; /* RES_VMASK_ON */
+ } BIT; /* */
+ } SCL0_FRC1; /* */
+ union { /* SCL0_FRC2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD RES_VLACK:16; /* RES_VLACK */
+ _UWORD :15; /* */
+ _UWORD RES_VLACK_ON:1; /* RES_VLACK_ON */
+ } BIT; /* */
+ } SCL0_FRC2; /* */
+ union { /* SCL0_FRC3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD RES_VS_SEL:1; /* RES_VS_SEL */
+ } BIT; /* */
+ } SCL0_FRC3; /* */
+ union { /* SCL0_FRC4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_FV:11; /* RES_FV */
+ _UWORD :5; /* */
+ _UWORD RES_FH:11; /* RES_FH */
+ } BIT; /* */
+ } SCL0_FRC4; /* */
+ union { /* SCL0_FRC5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD RES_FLD_DLY_SEL:1; /* RES_FLD_DLY_SEL */
+ _UDWORD RES_VSDLY:8; /* RES_VSDLY */
+ } BIT; /* */
+ } SCL0_FRC5; /* */
+ union { /* SCL0_FRC6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_F_VS:11; /* RES_F_VS */
+ _UWORD :5; /* */
+ _UWORD RES_F_VW:11; /* RES_F_VW */
+ } BIT; /* */
+ } SCL0_FRC6; /* */
+ union { /* SCL0_FRC7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_F_HS:11; /* RES_F_HS */
+ _UWORD :5; /* */
+ _UWORD RES_F_HW:11; /* RES_F_HW */
+ } BIT; /* */
+ } SCL0_FRC7; /* */
+ _UBYTE wk3[4]; /* */
+ union { /* SCL0_FRC9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD RES_QVLOCK:1; /* RES_QVLOCK */
+ _UDWORD :3; /* */
+ _UDWORD RES_QVLACK:1; /* RES_QVLACK */
+ } BIT; /* */
+ } SCL0_FRC9; /* */
+ _UBYTE wk4[4]; /* */
+ union { /* SCL0_DS1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD RES_DS_V_ON:1; /* RES_DS_V_ON */
+ _UDWORD :3; /* */
+ _UDWORD RES_DS_H_ON:1; /* RES_DS_H_ON */
+ } BIT; /* */
+ } SCL0_DS1; /* */
+ union { /* SCL0_DS2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_VS:11; /* RES_VS */
+ _UWORD :5; /* */
+ _UWORD RES_VW:11; /* RES_VW */
+ } BIT; /* */
+ } SCL0_DS2; /* */
+ union { /* SCL0_DS3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_HS:11; /* RES_HS */
+ _UWORD :5; /* */
+ _UWORD RES_HW:11; /* RES_HW */
+ } BIT; /* */
+ } SCL0_DS3; /* */
+ union { /* SCL0_DS4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD RES_PFIL_SEL:1; /* RES_PFIL_SEL */
+ _UWORD RES_DS_H_INTERPOTYP:1; /* RES_DS_H_INTERPOTYP */
+ _UWORD :12; /* */
+ _UWORD RES_DS_H_RATIO:16; /* RES_DS_H_RATIO */
+ } BIT; /* */
+ } SCL0_DS4; /* */
+ union { /* SCL0_DS5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD RES_V_INTERPOTYP:1; /* RES_V_INTERPOTYP */
+ _UWORD RES_TOP_INIPHASE:12; /* RES_TOP_INIPHASE */
+ _UWORD :4; /* */
+ _UWORD RES_BTM_INIPHASE:12; /* RES_BTM_INIPHASE */
+ } BIT; /* */
+ } SCL0_DS5; /* */
+ union { /* SCL0_DS6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :16; /* */
+ _UWORD RES_V_RATIO:16; /* RES_V_RATIO */
+ } BIT; /* */
+ } SCL0_DS6; /* */
+ union { /* SCL0_DS7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_OUT_VW:11; /* RES_OUT_VW */
+ _UWORD :5; /* */
+ _UWORD RES_OUT_HW:11; /* RES_OUT_HW */
+ } BIT; /* */
+ } SCL0_DS7; /* */
+ union { /* SCL0_US1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD RES_US_V_ON:1; /* RES_US_V_ON */
+ _UDWORD :3; /* */
+ _UDWORD RES_US_H_ON:1; /* RES_US_H_ON */
+ } BIT; /* */
+ } SCL0_US1; /* */
+ union { /* SCL0_US2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_P_VS:11; /* RES_P_VS */
+ _UWORD :5; /* */
+ _UWORD RES_P_VW:11; /* RES_P_VW */
+ } BIT; /* */
+ } SCL0_US2; /* */
+ union { /* SCL0_US3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_P_HS:11; /* RES_P_HS */
+ _UWORD :5; /* */
+ _UWORD RES_P_HW:11; /* RES_P_HW */
+ } BIT; /* */
+ } SCL0_US3; /* */
+ union { /* SCL0_US4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD RES_IN_VW:11; /* RES_IN_VW */
+ _UWORD :5; /* */
+ _UWORD RES_IN_HW:11; /* RES_IN_HW */
+ } BIT; /* */
+ } SCL0_US4; /* */
+ union { /* SCL0_US5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :16; /* */
+ _UWORD RES_US_H_RATIO:16; /* RES_US_H_RATIO */
+ } BIT; /* */
+ } SCL0_US5; /* */
+ union { /* SCL0_US6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD RES_US_H_INTERPOTYP:1; /* RES_US_H_INTERPOTYP */
+ _UWORD RES_US_HT_INIPHASE:12; /* RES_US_HT_INIPHASE */
+ _UWORD :4; /* */
+ _UWORD RES_US_HB_INIPHASE:12; /* RES_US_HB_INIPHASE */
+ } BIT; /* */
+ } SCL0_US6; /* */
+ union { /* SCL0_US7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :16; /* */
+ _UWORD RES_HCUT:8; /* RES_HCUT */
+ _UWORD RES_VCUT:8; /* RES_VCUT */
+ } BIT; /* */
+ } SCL0_US7; /* */
+ union { /* SCL0_US8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD RES_IBUS_SYNC_SEL:1; /* RES_IBUS_SYNC_SEL */
+ _UDWORD :3; /* */
+ _UDWORD RES_DISP_ON:1; /* RES_DISP_ON */
+ } BIT; /* */
+ } SCL0_US8; /* */
+ _UBYTE wk5[4]; /* */
+ union { /* SCL0_OVR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD RES_BK_COL_R:8; /* RES_BK_COL_R */
+ _UWORD RES_BK_COL_G:8; /* RES_BK_COL_G */
+ _UWORD RES_BK_COL_B:8; /* RES_BK_COL_B */
+ } BIT; /* */
+ } SCL0_OVR1; /* */
+ _UBYTE wk6[16]; /* */
+ union { /* SCL1_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD SCL1_VEN_B:1; /* SCL1_VEN_B */
+ _UDWORD :3; /* */
+ _UDWORD SCL1_VEN_A:1; /* SCL1_VEN_A */
+ } BIT; /* */
+ } SCL1_UPDATE; /* */
+ _UBYTE wk7[4]; /* */
+ union { /* SCL1_WR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD RES_DS_WR_MD:3; /* RES_DS_WR_MD */
+ _UDWORD RES_MD:2; /* RES_MD */
+ _UDWORD RES_LOOP:1; /* RES_LOOP */
+ _UDWORD RES_BST_MD:1; /* RES_BST_MD */
+ } BIT; /* */
+ } SCL1_WR1; /* */
+ union { /* SCL1_WR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD RES_BASE:32; /* RES_BASE */
+ } BIT; /* */
+ } SCL1_WR2; /* */
+ union { /* SCL1_WR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD RES_LN_OFF:15; /* RES_LN_OFF */
+ _UWORD :6; /* */
+ _UWORD RES_FLM_NUM:10; /* RES_FLM_NUM */
+ } BIT; /* */
+ } SCL1_WR3; /* */
+ union { /* SCL1_WR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :9; /* */
+ _UDWORD RES_FLM_OFF:23; /* RES_FLM_OFF */
+ } BIT; /* */
+ } SCL1_WR4; /* */
+ _UBYTE wk8[4]; /* */
+ union { /* SCL1_WR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :19; /* */
+ _UDWORD RES_INTER:1; /* RES_INTER */
+ _UDWORD :2; /* */
+ _UDWORD RES_FS_RATE:2; /* RES_FS_RATE */
+ _UDWORD :3; /* */
+ _UDWORD RES_FLD_SEL:1; /* RES_FLD_SEL */
+ _UDWORD :3; /* */
+ _UDWORD RES_WENB:1; /* RES_WENB */
+ } BIT; /* */
+ } SCL1_WR5; /* */
+ union { /* SCL1_WR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD RES_DTH_ON:1; /* RES_DTH_ON */
+ _UDWORD :3; /* */
+ _UDWORD RES_BITDEC_ON:1; /* RES_BITDEC_ON */
+ } BIT; /* */
+ } SCL1_WR6; /* */
+ union { /* SCL1_WR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD RES_OVERFLOW:1; /* RES_OVERFLOW */
+ _UWORD :6; /* */
+ _UWORD RES_FLM_CNT:10; /* RES_FLM_CNT */
+ } BIT; /* */
+ } SCL1_WR7; /* */
+ _UBYTE wk9[88]; /* */
+ union { /* GR1_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD GR1_P_VEN:1; /* GR1_P_VEN */
+ _UDWORD :3; /* */
+ _UDWORD GR1_IBUS_VEN:1; /* GR1_IBUS_VEN */
+ } BIT; /* */
+ } GR1_UPDATE; /* */
+ union { /* GR1_FLM_RD */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GR1_R_ENB:1; /* GR1_R_ENB */
+ } BIT; /* */
+ } GR1_FLM_RD; /* */
+ union { /* GR1_FLM1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD GR1_LN_OFF_DIR:1; /* GR1_LN_OFF_DIR */
+ _UWORD :6; /* */
+ _UWORD GR1_FLM_SEL:2; /* GR1_FLM_SEL */
+ _UWORD :3; /* */
+ _UWORD GR1_IMR_FLM_INV:1; /* GR1_IMR_FLM_INV */
+ _UWORD :3; /* */
+ _UWORD GR1_BST_MD:1; /* GR1_BST_MD */
+ } BIT; /* */
+ } GR1_FLM1; /* */
+ union { /* GR1_FLM2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD GR1_BASE:32; /* GR1_BASE */
+ } BIT; /* */
+ } GR1_FLM2; /* */
+ union { /* GR1_FLM3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD GR1_LN_OFF:15; /* GR1_LN_OFF */
+ _UWORD :6; /* */
+ _UWORD GR1_FLM_NUM:10; /* GR1_FLM_NUM */
+ } BIT; /* */
+ } GR1_FLM3; /* */
+ union { /* GR1_FLM4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :9; /* */
+ _UDWORD GR1_FLM_OFF:23; /* GR1_FLM_OFF */
+ } BIT; /* */
+ } GR1_FLM4; /* */
+ union { /* GR1_FLM5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD GR1_FLM_LNUM:10; /* GR1_FLM_LNUM */
+ _UWORD :6; /* */
+ _UWORD GR1_FLM_LOOP:10; /* GR1_FLM_LOOP */
+ } BIT; /* */
+ } GR1_FLM5; /* */
+ union { /* GR1_FLM6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR1_FORMAT:4; /* GR1_FORMAT */
+ _UWORD :2; /* */
+ _UWORD GR1_HW:10; /* GR1_HW */
+ _UWORD GR1_YCC_SWAP:3; /* GR1_YCC_SWAP */
+ _UWORD GR1_ENDIAN_ON:1; /* GR1_ENDIAN_ON */
+ _UWORD :3; /* */
+ _UWORD GR1_CNV444_MD:1; /* GR1_CNV444_MD */
+ _UWORD :2; /* */
+ _UWORD GR1_STA_POS:6; /* GR1_STA_POS */
+ } BIT; /* */
+ } GR1_FLM6; /* */
+ union { /* GR1_AB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :16; /* */
+ _UWORD :11; /* */
+ _UWORD GR1_GRC_DISP_ON:1; /* GR1_GRC_DISP_ON */
+ _UWORD :2; /* */
+ _UWORD GR1_DISP_SEL:2; /* GR1_DISP_SEL */
+ } BIT; /* */
+ } GR1_AB1; /* */
+ union { /* GR1_AB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR1_GRC_VS:11; /* GR1_GRC_VS */
+ _UWORD :5; /* */
+ _UWORD GR1_GRC_VW:11; /* GR1_GRC_VW */
+ } BIT; /* */
+ } GR1_AB2; /* */
+ union { /* GR1_AB3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR1_GRC_HS:11; /* GR1_GRC_HS */
+ _UWORD :5; /* */
+ _UWORD GR1_GRC_HW:11; /* GR1_GRC_HW */
+ } BIT; /* */
+ } GR1_AB3; /* */
+ _UBYTE wk10_0[12]; /* */
+ union { /* GR1_AB7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :16; /* */
+ _UWORD :15; /* */
+ _UWORD GR1_CK_ON:1; /* GR1_CK_ON */
+ } BIT; /* */
+ } GR1_AB7; /* */
+ union { /* GR1_AB8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR1_CK_KCLUT:8; /* GR1_CK_KCLUT */
+ _UWORD GR1_CK_KG:8; /* GR1_CK_KG */
+ _UWORD GR1_CK_KB:8; /* GR1_CK_KB */
+ _UWORD GR1_CK_KR:8; /* GR1_CK_KR */
+ } BIT; /* */
+ } GR1_AB8; /* */
+ union { /* GR1_AB9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR1_CK_A:8; /* GR1_CK_A */
+ _UWORD GR1_CK_G:8; /* GR1_CK_G */
+ _UWORD GR1_CK_B:8; /* GR1_CK_B */
+ _UWORD GR1_CK_R:8; /* GR1_CK_R */
+ } BIT; /* */
+ } GR1_AB9; /* */
+ union { /* GR1_AB10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR1_A0:8; /* GR1_A0 */
+ _UWORD GR1_G0:8; /* GR1_G0 */
+ _UWORD GR1_B0:8; /* GR1_B0 */
+ _UWORD GR1_R0:8; /* GR1_R0 */
+ } BIT; /* */
+ } GR1_AB10; /* */
+ union { /* GR1_AB11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR1_A1:8; /* GR1_A1 */
+ _UWORD GR1_G1:8; /* GR1_G1 */
+ _UWORD GR1_B1:8; /* GR1_B1 */
+ _UWORD GR1_R1:8; /* GR1_R1 */
+ } BIT; /* */
+ } GR1_AB11; /* */
+ union { /* GR1_BASE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GR1_BASE_G:8; /* GR1_BASE_G */
+ _UWORD GR1_BASE_B:8; /* GR1_BASE_B */
+ _UWORD GR1_BASE_R:8; /* GR1_BASE_R */
+ } BIT; /* */
+ } GR1_BASE; /* */
+ union { /* GR1_CLUT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD GR1_CLT_SEL:1; /* GR1_CLT_SEL */
+ _UWORD :16; /* */
+ } BIT; /* */
+ } GR1_CLUT; /* */
+ _UBYTE wk10[44]; /* */
+ union { /* ADJ_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD ADJ_VEN:1; /* ADJ_VEN */
+ } BIT; /* */
+ } ADJ_UPDATE; /* */
+ union { /* ADJ_BKSTR_SET */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD BKSTR_ON:1; /* BKSTR_ON */
+ _UWORD BKSTR_ST:4; /* BKSTR_ST */
+ _UWORD BKSTR_D:4; /* BKSTR_D */
+ _UWORD :3; /* */
+ _UWORD BKSTR_T1:5; /* BKSTR_T1 */
+ _UWORD :3; /* */
+ _UWORD BKSTR_T2:5; /* BKSTR_T2 */
+ } BIT; /* */
+ } ADJ_BKSTR_SET; /* */
+ union { /* ADJ_ENH_TIM1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD ENH_MD:1; /* ENH_MD */
+ _UDWORD :3; /* */
+ _UDWORD ENH_DISP_ON:1; /* ENH_DISP_ON */
+ } BIT; /* */
+ } ADJ_ENH_TIM1; /* */
+ union { /* ADJ_ENH_TIM2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD ENH_VS:11; /* ENH_VS */
+ _UWORD :5; /* */
+ _UWORD ENH_VW:11; /* ENH_VW */
+ } BIT; /* */
+ } ADJ_ENH_TIM2; /* */
+ union { /* ADJ_ENH_TIM3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD ENH_HS:11; /* ENH_HS */
+ _UWORD :5; /* */
+ _UWORD ENH_HW:11; /* ENH_HW */
+ } BIT; /* */
+ } ADJ_ENH_TIM3; /* */
+ union { /* ADJ_ENH_SHP1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD SHP_H_ON:1; /* SHP_H_ON */
+ _UWORD :9; /* */
+ _UWORD SHP_H1_CORE:7; /* SHP_H1_CORE */
+ } BIT; /* */
+ } ADJ_ENH_SHP1; /* */
+ union { /* ADJ_ENH_SHP2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD SHP_H1_CLIP_O:8; /* SHP_H1_CLIP_O */
+ _UWORD SHP_H1_CLIP_U:8; /* SHP_H1_CLIP_U */
+ _UWORD SHP_H1_GAIN_O:8; /* SHP_H1_GAIN_O */
+ _UWORD SHP_H1_GAIN_U:8; /* SHP_H1_GAIN_U */
+ } BIT; /* */
+ } ADJ_ENH_SHP2; /* */
+ union { /* ADJ_ENH_SHP3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD SHP_H2_LPF_SEL:1; /* SHP_H2_LPF_SEL */
+ _UWORD :9; /* */
+ _UWORD SHP_H2_CORE:7; /* SHP_H2_CORE */
+ } BIT; /* */
+ } ADJ_ENH_SHP3; /* */
+ union { /* ADJ_ENH_SHP4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD SHP_H2_CLIP_O:8; /* SHP_H2_CLIP_O */
+ _UWORD SHP_H2_CLIP_U:8; /* SHP_H2_CLIP_U */
+ _UWORD SHP_H2_GAIN_O:8; /* SHP_H2_GAIN_O */
+ _UWORD SHP_H2_GAIN_U:8; /* SHP_H2_GAIN_U */
+ } BIT; /* */
+ } ADJ_ENH_SHP4; /* */
+ union { /* ADJ_ENH_SHP5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD SHP_H3_CORE:7; /* SHP_H3_CORE */
+ } BIT; /* */
+ } ADJ_ENH_SHP5; /* */
+ union { /* ADJ_ENH_SHP6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD SHP_H3_CLIP_O:8; /* SHP_H3_CLIP_O */
+ _UWORD SHP_H3_CLIP_U:8; /* SHP_H3_CLIP_U */
+ _UWORD SHP_H3_GAIN_O:8; /* SHP_H3_GAIN_O */
+ _UWORD SHP_H3_GAIN_U:8; /* SHP_H3_GAIN_U */
+ } BIT; /* */
+ } ADJ_ENH_SHP6; /* */
+ union { /* ADJ_ENH_LTI1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD LTI_H_ON:1; /* LTI_H_ON */
+ _UWORD :6; /* */
+ _UWORD LTI_H2_LPF_SEL:1; /* LTI_H2_LPF_SEL */
+ _UWORD LTI_H2_INC_ZERO:8; /* LTI_H2_INC_ZERO */
+ _UWORD LTI_H2_GAIN:8; /* LTI_H2_GAIN */
+ _UWORD LTI_H2_CORE:8; /* LTI_H2_CORE */
+ } BIT; /* */
+ } ADJ_ENH_LTI1; /* */
+ union { /* ADJ_ENH_LTI2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD LTI_H4_MEDIAN_TAP_SEL:1; /* LTI_H4_MEDIAN_TAP_SEL */
+ _UWORD LTI_H4_INC_ZERO:8; /* LTI_H4_INC_ZERO */
+ _UWORD LTI_H4_GAIN:8; /* LTI_H4_GAIN */
+ _UWORD LTI_H4_CORE:8; /* LTI_H4_CORE */
+ } BIT; /* */
+ } ADJ_ENH_LTI2; /* */
+ union { /* ADJ_MTX_MODE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :30; /* */
+ _UDWORD ADJ_MTX_MD:2; /* ADJ_MTX_MD */
+ } BIT; /* */
+ } ADJ_MTX_MODE; /* */
+ union { /* ADJ_MTX_YG_ADJ0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD ADJ_MTX_YG:8; /* ADJ_MTX_YG */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_GG:11; /* ADJ_MTX_GG */
+ } BIT; /* */
+ } ADJ_MTX_YG_ADJ0; /* */
+ union { /* ADJ_MTX_YG_ADJ1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_GB:11; /* ADJ_MTX_GB */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_GR:11; /* ADJ_MTX_GR */
+ } BIT; /* */
+ } ADJ_MTX_YG_ADJ1; /* */
+ union { /* ADJ_MTX_CBB_ADJ0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD ADJ_MTX_B:8; /* ADJ_MTX_B */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_BG:11; /* ADJ_MTX_BG */
+ } BIT; /* */
+ } ADJ_MTX_CBB_ADJ0; /* */
+ union { /* ADJ_MTX_CBB_ADJ1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_BB:11; /* ADJ_MTX_BB */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_BR:11; /* ADJ_MTX_BR */
+ } BIT; /* */
+ } ADJ_MTX_CBB_ADJ1; /* */
+ union { /* ADJ_MTX_CRR_ADJ0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD ADJ_MTX_R:8; /* ADJ_MTX_R */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_RG:11; /* ADJ_MTX_RG */
+ } BIT; /* */
+ } ADJ_MTX_CRR_ADJ0; /* */
+ union { /* ADJ_MTX_CRR_ADJ1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_RB:11; /* ADJ_MTX_RB */
+ _UWORD :5; /* */
+ _UWORD ADJ_MTX_RR:11; /* ADJ_MTX_RR */
+ } BIT; /* */
+ } ADJ_MTX_CRR_ADJ1; /* */
+ _UBYTE wk11[48]; /* */
+ union { /* GR2_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD GR2_P_VEN:1; /* GR2_P_VEN */
+ _UDWORD :3; /* */
+ _UDWORD GR2_IBUS_VEN:1; /* GR2_IBUS_VEN */
+ } BIT; /* */
+ } GR2_UPDATE; /* */
+ union { /* GR2_FLM_RD */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GR2_R_ENB:1; /* GR2_R_ENB */
+ } BIT; /* */
+ } GR2_FLM_RD; /* */
+ union { /* GR2_FLM1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD GR2_LN_OFF_DIR:1; /* GR2_LN_OFF_DIR */
+ _UWORD :6; /* */
+ _UWORD GR2_FLM_SEL:2; /* GR2_FLM_SEL */
+ _UWORD :7; /* */
+ _UWORD GR2_BST_MD:1; /* GR2_BST_MD */
+ } BIT; /* */
+ } GR2_FLM1; /* */
+ union { /* GR2_FLM2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD GR2_BASE:32; /* GR2_BASE */
+ } BIT; /* */
+ } GR2_FLM2; /* */
+ union { /* GR2_FLM3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD GR2_LN_OFF:15; /* GR2_LN_OFF */
+ _UWORD :6; /* */
+ _UWORD GR2_FLM_NUM:10; /* GR2_FLM_NUM */
+ } BIT; /* */
+ } GR2_FLM3; /* */
+ union { /* GR2_FLM4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :9; /* */
+ _UDWORD GR2_FLM_OFF:23; /* GR2_FLM_OFF */
+ } BIT; /* */
+ } GR2_FLM4; /* */
+ union { /* GR2_FLM5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD GR2_FLM_LNUM:10; /* GR2_FLM_LNUM */
+ _UWORD :6; /* */
+ _UWORD GR2_FLM_LOOP:10; /* GR2_FLM_LOOP */
+ } BIT; /* */
+ } GR2_FLM5; /* */
+ union { /* GR2_FLM6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR2_FORMAT:4; /* GR2_FORMAT */
+ _UWORD :2; /* */
+ _UWORD GR2_HW:10; /* GR2_HW */
+ _UWORD :3; /* */
+ _UWORD GR2_ENDIAN_ON:1; /* GR2_ENDIAN_ON */
+ _UWORD :6; /* */
+ _UWORD GR2_STA_POS:6; /* GR2_STA_POS */
+ } BIT; /* */
+ } GR2_FLM6; /* */
+ union { /* GR2_AB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :19; /* */
+ _UDWORD GR2_ARC_ON:1; /* GR2_ARC_ON */
+ _UDWORD :3; /* */
+ _UDWORD GR2_ARC_DISP_ON:1; /* GR2_ARC_DISP_ON */
+ _UDWORD :3; /* */
+ _UDWORD GR2_GRC_DISP_ON:1; /* GR2_GRC_DISP_ON */
+ _UDWORD :2; /* */
+ _UDWORD GR2_DISP_SEL:2; /* GR2_DISP_SEL */
+ } BIT; /* */
+ } GR2_AB1; /* */
+ union { /* GR2_AB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR2_GRC_VS:11; /* GR2_GRC_VS */
+ _UWORD :5; /* */
+ _UWORD GR2_GRC_VW:11; /* GR2_GRC_VW */
+ } BIT; /* */
+ } GR2_AB2; /* */
+ union { /* GR2_AB3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR2_GRC_HS:11; /* GR2_GRC_HS */
+ _UWORD :5; /* */
+ _UWORD GR2_GRC_HW:11; /* GR2_GRC_HW */
+ } BIT; /* */
+ } GR2_AB3; /* */
+ union { /* GR2_AB4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR2_ARC_VS:11; /* GR2_ARC_VS */
+ _UWORD :5; /* */
+ _UWORD GR2_ARC_VW:11; /* GR2_ARC_VW */
+ } BIT; /* */
+ } GR2_AB4; /* */
+ union { /* GR2_AB5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR2_ARC_HS:11; /* GR2_ARC_HS */
+ _UWORD :5; /* */
+ _UWORD GR2_ARC_HW:11; /* GR2_ARC_HW */
+ } BIT; /* */
+ } GR2_AB5; /* */
+ union { /* GR2_AB6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD GR2_ARC_MODE:1; /* GR2_ARC_MODE */
+ _UWORD GR2_ARC_COEF:8; /* GR2_ARC_COEF */
+ _UWORD :8; /* */
+ _UWORD GR2_ARC_RATE:8; /* GR2_ARC_RATE */
+ } BIT; /* */
+ } GR2_AB6; /* */
+ union { /* GR2_AB7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GR2_ARC_DEF:8; /* GR2_ARC_DEF */
+ _UWORD :15; /* */
+ _UWORD GR2_CK_ON:1; /* GR2_CK_ON */
+ } BIT; /* */
+ } GR2_AB7; /* */
+ union { /* GR2_AB8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR2_CK_KCLUT:8; /* GR2_CK_KCLUT */
+ _UWORD GR2_CK_KG:8; /* GR2_CK_KG */
+ _UWORD GR2_CK_KB:8; /* GR2_CK_KB */
+ _UWORD GR2_CK_KR:8; /* GR2_CK_KR */
+ } BIT; /* */
+ } GR2_AB8; /* */
+ union { /* GR2_AB9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR2_CK_A:8; /* GR2_CK_A */
+ _UWORD GR2_CK_G:8; /* GR2_CK_G */
+ _UWORD GR2_CK_B:8; /* GR2_CK_B */
+ _UWORD GR2_CK_R:8; /* GR2_CK_R */
+ } BIT; /* */
+ } GR2_AB9; /* */
+ union { /* GR2_AB10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR2_A0:8; /* GR2_A0 */
+ _UWORD GR2_G0:8; /* GR2_G0 */
+ _UWORD GR2_B0:8; /* GR2_B0 */
+ _UWORD GR2_R0:8; /* GR2_R0 */
+ } BIT; /* */
+ } GR2_AB10; /* */
+ union { /* GR2_AB11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR2_A1:8; /* GR2_A1 */
+ _UWORD GR2_G1:8; /* GR2_G1 */
+ _UWORD GR2_B1:8; /* GR2_B1 */
+ _UWORD GR2_R1:8; /* GR2_R1 */
+ } BIT; /* */
+ } GR2_AB11; /* */
+ union { /* GR2_BASE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GR2_BASE_G:8; /* GR2_BASE_G */
+ _UWORD GR2_BASE_B:8; /* GR2_BASE_B */
+ _UWORD GR2_BASE_R:8; /* GR2_BASE_R */
+ } BIT; /* */
+ } GR2_BASE; /* */
+ union { /* GR2_CLUT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD GR2_CLT_SEL:1; /* GR2_CLT_SEL */
+ _UWORD :16; /* */
+ } BIT; /* */
+ } GR2_CLUT; /* */
+ union { /* GR2_MON */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GR2_ARC_ST:1; /* GR2_ARC_ST */
+ } BIT; /* */
+ } GR2_MON; /* */
+ _UBYTE wk12[40]; /* */
+ union { /* GR3_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD GR3_P_VEN:1; /* GR3_P_VEN */
+ _UDWORD :3; /* */
+ _UDWORD GR3_IBUS_VEN:1; /* GR3_IBUS_VEN */
+ } BIT; /* */
+ } GR3_UPDATE; /* */
+ union { /* GR3_FLM_RD */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GR3_R_ENB:1; /* GR3_R_ENB */
+ } BIT; /* */
+ } GR3_FLM_RD; /* */
+ union { /* GR3_FLM1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD GR3_LN_OFF_DIR:1; /* GR3_LN_OFF_DIR */
+ _UWORD :6; /* */
+ _UWORD GR3_FLM_SEL:2; /* GR3_FLM_SEL */
+ _UWORD :7; /* */
+ _UWORD GR3_BST_MD:1; /* GR3_BST_MD */
+ } BIT; /* */
+ } GR3_FLM1; /* */
+ union { /* GR3_FLM2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD GR3_BASE:32; /* GR3_BASE */
+ } BIT; /* */
+ } GR3_FLM2; /* */
+ union { /* GR3_FLM3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD GR3_LN_OFF:15; /* GR3_LN_OFF */
+ _UWORD :6; /* */
+ _UWORD GR3_FLM_NUM:10; /* GR3_FLM_NUM */
+ } BIT; /* */
+ } GR3_FLM3; /* */
+ union { /* GR3_FLM4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :9; /* */
+ _UDWORD GR3_FLM_OFF:23; /* GR3_FLM_OFF */
+ } BIT; /* */
+ } GR3_FLM4; /* */
+ union { /* GR3_FLM5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD GR3_FLM_LNUM:10; /* GR3_FLM_LNUM */
+ _UWORD :6; /* */
+ _UWORD GR3_FLM_LOOP:10; /* GR3_FLM_LOOP */
+ } BIT; /* */
+ } GR3_FLM5; /* */
+ union { /* GR3_FLM6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR3_FORMAT:4; /* GR3_FORMAT */
+ _UWORD :2; /* */
+ _UWORD GR3_HW:10; /* GR3_HW */
+ _UWORD :3; /* */
+ _UWORD GR3_ENDIAN_ON:1; /* GR3_ENDIAN_ON */
+ _UWORD :6; /* */
+ _UWORD GR3_STA_POS:6; /* GR3_STA_POS */
+ } BIT; /* */
+ } GR3_FLM6; /* */
+ union { /* GR3_AB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :19; /* */
+ _UDWORD GR3_ARC_ON:1; /* GR3_ARC_ON */
+ _UDWORD :3; /* */
+ _UDWORD GR3_ARC_DISP_ON:1; /* GR3_ARC_DISP_ON */
+ _UDWORD :3; /* */
+ _UDWORD GR3_GRC_DISP_ON:1; /* GR3_GRC_DISP_ON */
+ _UDWORD :2; /* */
+ _UDWORD GR3_DISP_SEL:2; /* GR3_DISP_SEL */
+ } BIT; /* */
+ } GR3_AB1; /* */
+ union { /* GR3_AB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR3_GRC_VS:11; /* GR3_GRC_VS */
+ _UWORD :5; /* */
+ _UWORD GR3_GRC_VW:11; /* GR3_GRC_VW */
+ } BIT; /* */
+ } GR3_AB2; /* */
+ union { /* GR3_AB3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR3_GRC_HS:11; /* GR3_GRC_HS */
+ _UWORD :5; /* */
+ _UWORD GR3_GRC_HW:11; /* GR3_GRC_HW */
+ } BIT; /* */
+ } GR3_AB3; /* */
+ union { /* GR3_AB4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR3_ARC_VS:11; /* GR3_ARC_VS */
+ _UWORD :5; /* */
+ _UWORD GR3_ARC_VW:11; /* GR3_ARC_VW */
+ } BIT; /* */
+ } GR3_AB4; /* */
+ union { /* GR3_AB5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GR3_ARC_HS:11; /* GR3_ARC_HS */
+ _UWORD :5; /* */
+ _UWORD GR3_ARC_HW:11; /* GR3_ARC_HW */
+ } BIT; /* */
+ } GR3_AB5; /* */
+ union { /* GR3_AB6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD GR3_ARC_MODE:1; /* GR3_ARC_MODE */
+ _UWORD GR3_ARC_COEF:8; /* GR3_ARC_COEF */
+ _UWORD :8; /* */
+ _UWORD GR3_ARC_RATE:8; /* GR3_ARC_RATE */
+ } BIT; /* */
+ } GR3_AB6; /* */
+ union { /* GR3_AB7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GR3_ARC_DEF:8; /* GR3_ARC_DEF */
+ _UWORD :15; /* */
+ _UWORD GR3_CK_ON:1; /* GR3_CK_ON */
+ } BIT; /* */
+ } GR3_AB7; /* */
+ union { /* GR3_AB8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR3_CK_KCLUT:8; /* GR3_CK_KCLUT */
+ _UWORD GR3_CK_KG:8; /* GR3_CK_KG */
+ _UWORD GR3_CK_KB:8; /* GR3_CK_KB */
+ _UWORD GR3_CK_KR:8; /* GR3_CK_KR */
+ } BIT; /* */
+ } GR3_AB8; /* */
+ union { /* GR3_AB9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR3_CK_A:8; /* GR3_CK_A */
+ _UWORD GR3_CK_G:8; /* GR3_CK_G */
+ _UWORD GR3_CK_B:8; /* GR3_CK_B */
+ _UWORD GR3_CK_R:8; /* GR3_CK_R */
+ } BIT; /* */
+ } GR3_AB9; /* */
+ union { /* GR3_AB10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR3_A0:8; /* GR3_A0 */
+ _UWORD GR3_G0:8; /* GR3_G0 */
+ _UWORD GR3_B0:8; /* GR3_B0 */
+ _UWORD GR3_R0:8; /* GR3_R0 */
+ } BIT; /* */
+ } GR3_AB10; /* */
+ union { /* GR3_AB11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GR3_A1:8; /* GR3_A1 */
+ _UWORD GR3_G1:8; /* GR3_G1 */
+ _UWORD GR3_B1:8; /* GR3_B1 */
+ _UWORD GR3_R1:8; /* GR3_R1 */
+ } BIT; /* */
+ } GR3_AB11; /* */
+ union { /* GR3_BASE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GR3_BASE_G:8; /* GR3_BASE_G */
+ _UWORD GR3_BASE_B:8; /* GR3_BASE_B */
+ _UWORD GR3_BASE_R:8; /* GR3_BASE_R */
+ } BIT; /* */
+ } GR3_BASE; /* */
+ union { /* GR3_CLUT_INT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD GR3_CLT_SEL:1; /* GR3_CLT_SEL */
+ _UWORD :5; /* */
+ _UWORD GR3_LINE:11; /* */
+ } BIT; /* */
+ } GR3_CLUT_INT; /* */
+ union { /* GR3_MON */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GR3_ARC_ST:1; /* GR3_ARC_ST */
+ } BIT; /* */
+ } GR3_MON; /* */
+ _UBYTE wk13[40]; /* */
+ union { /* GAM_G_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GAM_G_VEN:1; /* GAM_G_VEN */
+ } BIT; /* */
+ } GAM_G_UPDATE; /* */
+ union { /* GAM_SW */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GAM_ON:1; /* GAM_ON */
+ } BIT; /* */
+ } GAM_SW; /* */
+ union { /* GAM_G_LUT1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_00:11; /* GAM_G_GAIN_00 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_01:11; /* GAM_G_GAIN_01 */
+ } BIT; /* */
+ } GAM_G_LUT1; /* */
+ union { /* GAM_G_LUT2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_02:11; /* GAM_G_GAIN_02 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_03:11; /* GAM_G_GAIN_03 */
+ } BIT; /* */
+ } GAM_G_LUT2; /* */
+ union { /* GAM_G_LUT3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_04:11; /* GAM_G_GAIN_04 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_05:11; /* GAM_G_GAIN_05 */
+ } BIT; /* */
+ } GAM_G_LUT3; /* */
+ union { /* GAM_G_LUT4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_06:11; /* GAM_G_GAIN_06 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_07:11; /* GAM_G_GAIN_07 */
+ } BIT; /* */
+ } GAM_G_LUT4; /* */
+ union { /* GAM_G_LUT5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_08:11; /* GAM_G_GAIN_08 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_09:11; /* GAM_G_GAIN_09 */
+ } BIT; /* */
+ } GAM_G_LUT5; /* */
+ union { /* GAM_G_LUT6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_10:11; /* GAM_G_GAIN_10 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_11:11; /* GAM_G_GAIN_11 */
+ } BIT; /* */
+ } GAM_G_LUT6; /* */
+ union { /* GAM_G_LUT7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_12:11; /* GAM_G_GAIN_12 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_13:11; /* GAM_G_GAIN_13 */
+ } BIT; /* */
+ } GAM_G_LUT7; /* */
+ union { /* GAM_G_LUT8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_14:11; /* GAM_G_GAIN_14 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_15:11; /* GAM_G_GAIN_15 */
+ } BIT; /* */
+ } GAM_G_LUT8; /* */
+ union { /* GAM_G_LUT9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_16:11; /* GAM_G_GAIN_16 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_17:11; /* GAM_G_GAIN_17 */
+ } BIT; /* */
+ } GAM_G_LUT9; /* */
+ union { /* GAM_G_LUT10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_18:11; /* GAM_G_GAIN_18 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_19:11; /* GAM_G_GAIN_19 */
+ } BIT; /* */
+ } GAM_G_LUT10; /* */
+ union { /* GAM_G_LUT11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_20:11; /* GAM_G_GAIN_20 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_21:11; /* GAM_G_GAIN_21 */
+ } BIT; /* */
+ } GAM_G_LUT11; /* */
+ union { /* GAM_G_LUT12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_22:11; /* GAM_G_GAIN_22 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_23:11; /* GAM_G_GAIN_23 */
+ } BIT; /* */
+ } GAM_G_LUT12; /* */
+ union { /* GAM_G_LUT13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_24:11; /* GAM_G_GAIN_24 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_25:11; /* GAM_G_GAIN_25 */
+ } BIT; /* */
+ } GAM_G_LUT13; /* */
+ union { /* GAM_G_LUT14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_26:11; /* GAM_G_GAIN_26 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_27:11; /* GAM_G_GAIN_27 */
+ } BIT; /* */
+ } GAM_G_LUT14; /* */
+ union { /* GAM_G_LUT15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_28:11; /* GAM_G_GAIN_28 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_29:11; /* GAM_G_GAIN_29 */
+ } BIT; /* */
+ } GAM_G_LUT15; /* */
+ union { /* GAM_G_LUT16 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_30:11; /* GAM_G_GAIN_30 */
+ _UWORD :5; /* */
+ _UWORD GAM_G_GAIN_31:11; /* GAM_G_GAIN_31 */
+ } BIT; /* */
+ } GAM_G_LUT16; /* */
+ union { /* GAM_G_AREA1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GAM_G_TH_01:8; /* GAM_G_TH_01 */
+ _UWORD GAM_G_TH_02:8; /* GAM_G_TH_02 */
+ _UWORD GAM_G_TH_03:8; /* GAM_G_TH_03 */
+ } BIT; /* */
+ } GAM_G_AREA1; /* */
+ union { /* GAM_G_AREA2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_04:8; /* GAM_G_TH_04 */
+ _UWORD GAM_G_TH_05:8; /* GAM_G_TH_05 */
+ _UWORD GAM_G_TH_06:8; /* GAM_G_TH_06 */
+ _UWORD GAM_G_TH_07:8; /* GAM_G_TH_07 */
+ } BIT; /* */
+ } GAM_G_AREA2; /* */
+ union { /* GAM_G_AREA3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_08:8; /* GAM_G_TH_08 */
+ _UWORD GAM_G_TH_09:8; /* GAM_G_TH_09 */
+ _UWORD GAM_G_TH_10:8; /* GAM_G_TH_10 */
+ _UWORD GAM_G_TH_11:8; /* GAM_G_TH_11 */
+ } BIT; /* */
+ } GAM_G_AREA3; /* */
+ union { /* GAM_G_AREA4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_12:8; /* GAM_G_TH_12 */
+ _UWORD GAM_G_TH_13:8; /* GAM_G_TH_13 */
+ _UWORD GAM_G_TH_14:8; /* GAM_G_TH_14 */
+ _UWORD GAM_G_TH_15:8; /* GAM_G_TH_15 */
+ } BIT; /* */
+ } GAM_G_AREA4; /* */
+ union { /* GAM_G_AREA5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_16:8; /* GAM_G_TH_16 */
+ _UWORD GAM_G_TH_17:8; /* GAM_G_TH_17 */
+ _UWORD GAM_G_TH_18:8; /* GAM_G_TH_18 */
+ _UWORD GAM_G_TH_19:8; /* GAM_G_TH_19 */
+ } BIT; /* */
+ } GAM_G_AREA5; /* */
+ union { /* GAM_G_AREA6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_20:8; /* GAM_G_TH_20 */
+ _UWORD GAM_G_TH_21:8; /* GAM_G_TH_21 */
+ _UWORD GAM_G_TH_22:8; /* GAM_G_TH_22 */
+ _UWORD GAM_G_TH_23:8; /* GAM_G_TH_23 */
+ } BIT; /* */
+ } GAM_G_AREA6; /* */
+ union { /* GAM_G_AREA7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_24:8; /* GAM_G_TH_24 */
+ _UWORD GAM_G_TH_25:8; /* GAM_G_TH_25 */
+ _UWORD GAM_G_TH_26:8; /* GAM_G_TH_26 */
+ _UWORD GAM_G_TH_27:8; /* GAM_G_TH_27 */
+ } BIT; /* */
+ } GAM_G_AREA7; /* */
+ union { /* GAM_G_AREA8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_G_TH_28:8; /* GAM_G_TH_28 */
+ _UWORD GAM_G_TH_29:8; /* GAM_G_TH_29 */
+ _UWORD GAM_G_TH_30:8; /* GAM_G_TH_30 */
+ _UWORD GAM_G_TH_31:8; /* GAM_G_TH_31 */
+ } BIT; /* */
+ } GAM_G_AREA8; /* */
+ _UBYTE wk14[24]; /* */
+ union { /* GAM_B_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GAM_B_VEN:1; /* GAM_B_VEN */
+ } BIT; /* */
+ } GAM_B_UPDATE; /* */
+ _UBYTE wk15[4]; /* */
+ union { /* GAM_B_LUT1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_00:11; /* GAM_B_GAIN_00 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_01:11; /* GAM_B_GAIN_01 */
+ } BIT; /* */
+ } GAM_B_LUT1; /* */
+ union { /* GAM_B_LUT2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_02:11; /* GAM_B_GAIN_02 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_03:11; /* GAM_B_GAIN_03 */
+ } BIT; /* */
+ } GAM_B_LUT2; /* */
+ union { /* GAM_B_LUT3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_04:11; /* GAM_B_GAIN_04 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_05:11; /* GAM_B_GAIN_05 */
+ } BIT; /* */
+ } GAM_B_LUT3; /* */
+ union { /* GAM_B_LUT4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_06:11; /* GAM_B_GAIN_06 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_07:11; /* GAM_B_GAIN_07 */
+ } BIT; /* */
+ } GAM_B_LUT4; /* */
+ union { /* GAM_B_LUT5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_08:11; /* GAM_B_GAIN_08 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_09:11; /* GAM_B_GAIN_09 */
+ } BIT; /* */
+ } GAM_B_LUT5; /* */
+ union { /* GAM_B_LUT6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_10:11; /* GAM_B_GAIN_10 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_11:11; /* GAM_B_GAIN_11 */
+ } BIT; /* */
+ } GAM_B_LUT6; /* */
+ union { /* GAM_B_LUT7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_12:11; /* GAM_B_GAIN_12 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_13:11; /* GAM_B_GAIN_13 */
+ } BIT; /* */
+ } GAM_B_LUT7; /* */
+ union { /* GAM_B_LUT8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_14:11; /* GAM_B_GAIN_14 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_15:11; /* GAM_B_GAIN_15 */
+ } BIT; /* */
+ } GAM_B_LUT8; /* */
+ union { /* GAM_B_LUT9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_16:11; /* GAM_B_GAIN_16 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_17:11; /* GAM_B_GAIN_17 */
+ } BIT; /* */
+ } GAM_B_LUT9; /* */
+ union { /* GAM_B_LUT10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_18:11; /* GAM_B_GAIN_18 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_19:11; /* GAM_B_GAIN_19 */
+ } BIT; /* */
+ } GAM_B_LUT10; /* */
+ union { /* GAM_B_LUT11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_20:11; /* GAM_B_GAIN_20 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_21:11; /* GAM_B_GAIN_21 */
+ } BIT; /* */
+ } GAM_B_LUT11; /* */
+ union { /* GAM_B_LUT12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_22:11; /* GAM_B_GAIN_22 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_23:11; /* GAM_B_GAIN_23 */
+ } BIT; /* */
+ } GAM_B_LUT12; /* */
+ union { /* GAM_B_LUT13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_24:11; /* GAM_B_GAIN_24 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_25:11; /* GAM_B_GAIN_25 */
+ } BIT; /* */
+ } GAM_B_LUT13; /* */
+ union { /* GAM_B_LUT14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_26:11; /* GAM_B_GAIN_26 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_27:11; /* GAM_B_GAIN_27 */
+ } BIT; /* */
+ } GAM_B_LUT14; /* */
+ union { /* GAM_B_LUT15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_28:11; /* GAM_B_GAIN_28 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_29:11; /* GAM_B_GAIN_29 */
+ } BIT; /* */
+ } GAM_B_LUT15; /* */
+ union { /* GAM_B_LUT16 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_30:11; /* GAM_B_GAIN_30 */
+ _UWORD :5; /* */
+ _UWORD GAM_B_GAIN_31:11; /* GAM_B_GAIN_31 */
+ } BIT; /* */
+ } GAM_B_LUT16; /* */
+ union { /* GAM_B_AREA1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GAM_B_TH_01:8; /* GAM_B_TH_01 */
+ _UWORD GAM_B_TH_02:8; /* GAM_B_TH_02 */
+ _UWORD GAM_B_TH_03:8; /* GAM_B_TH_03 */
+ } BIT; /* */
+ } GAM_B_AREA1; /* */
+ union { /* GAM_B_AREA2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_04:8; /* GAM_B_TH_04 */
+ _UWORD GAM_B_TH_05:8; /* GAM_B_TH_05 */
+ _UWORD GAM_B_TH_06:8; /* GAM_B_TH_06 */
+ _UWORD GAM_B_TH_07:8; /* GAM_B_TH_07 */
+ } BIT; /* */
+ } GAM_B_AREA2; /* */
+ union { /* GAM_B_AREA3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_08:8; /* GAM_B_TH_08 */
+ _UWORD GAM_B_TH_09:8; /* GAM_B_TH_09 */
+ _UWORD GAM_B_TH_10:8; /* GAM_B_TH_10 */
+ _UWORD GAM_B_TH_11:8; /* GAM_B_TH_11 */
+ } BIT; /* */
+ } GAM_B_AREA3; /* */
+ union { /* GAM_B_AREA4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_12:8; /* GAM_B_TH_12 */
+ _UWORD GAM_B_TH_13:8; /* GAM_B_TH_13 */
+ _UWORD GAM_B_TH_14:8; /* GAM_B_TH_14 */
+ _UWORD GAM_B_TH_15:8; /* GAM_B_TH_15 */
+ } BIT; /* */
+ } GAM_B_AREA4; /* */
+ union { /* GAM_B_AREA5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_16:8; /* GAM_B_TH_16 */
+ _UWORD GAM_B_TH_17:8; /* GAM_B_TH_17 */
+ _UWORD GAM_B_TH_18:8; /* GAM_B_TH_18 */
+ _UWORD GAM_B_TH_19:8; /* GAM_B_TH_19 */
+ } BIT; /* */
+ } GAM_B_AREA5; /* */
+ union { /* GAM_B_AREA6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_20:8; /* GAM_B_TH_20 */
+ _UWORD GAM_B_TH_21:8; /* GAM_B_TH_21 */
+ _UWORD GAM_B_TH_22:8; /* GAM_B_TH_22 */
+ _UWORD GAM_B_TH_23:8; /* GAM_B_TH_23 */
+ } BIT; /* */
+ } GAM_B_AREA6; /* */
+ union { /* GAM_B_AREA7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_24:8; /* GAM_B_TH_24 */
+ _UWORD GAM_B_TH_25:8; /* GAM_B_TH_25 */
+ _UWORD GAM_B_TH_26:8; /* GAM_B_TH_26 */
+ _UWORD GAM_B_TH_27:8; /* GAM_B_TH_27 */
+ } BIT; /* */
+ } GAM_B_AREA7; /* */
+ union { /* GAM_B_AREA8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_B_TH_28:8; /* GAM_B_TH_28 */
+ _UWORD GAM_B_TH_29:8; /* GAM_B_TH_29 */
+ _UWORD GAM_B_TH_30:8; /* GAM_B_TH_30 */
+ _UWORD GAM_B_TH_31:8; /* GAM_B_TH_31 */
+ } BIT; /* */
+ } GAM_B_AREA8; /* */
+ _UBYTE wk16[24]; /* */
+ union { /* GAM_R_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD GAM_R_VEN:1; /* GAM_R_VEN */
+ } BIT; /* */
+ } GAM_R_UPDATE; /* */
+ _UBYTE wk17[4]; /* */
+ union { /* GAM_R_LUT1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_00:11; /* GAM_R_GAIN_00 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_01:11; /* GAM_R_GAIN_01 */
+ } BIT; /* */
+ } GAM_R_LUT1; /* */
+ union { /* GAM_R_LUT2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_02:11; /* GAM_R_GAIN_02 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_03:11; /* GAM_R_GAIN_03 */
+ } BIT; /* */
+ } GAM_R_LUT2; /* */
+ union { /* GAM_R_LUT3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_04:11; /* GAM_R_GAIN_04 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_05:11; /* GAM_R_GAIN_05 */
+ } BIT; /* */
+ } GAM_R_LUT3; /* */
+ union { /* GAM_R_LUT4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_06:11; /* GAM_R_GAIN_06 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_07:11; /* GAM_R_GAIN_07 */
+ } BIT; /* */
+ } GAM_R_LUT4; /* */
+ union { /* GAM_R_LUT5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_08:11; /* GAM_R_GAIN_08 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_09:11; /* GAM_R_GAIN_09 */
+ } BIT; /* */
+ } GAM_R_LUT5; /* */
+ union { /* GAM_R_LUT6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_10:11; /* GAM_R_GAIN_10 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_11:11; /* GAM_R_GAIN_11 */
+ } BIT; /* */
+ } GAM_R_LUT6; /* */
+ union { /* GAM_R_LUT7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_12:11; /* GAM_R_GAIN_12 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_13:11; /* GAM_R_GAIN_13 */
+ } BIT; /* */
+ } GAM_R_LUT7; /* */
+ union { /* GAM_R_LUT8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_14:11; /* GAM_R_GAIN_14 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_15:11; /* GAM_R_GAIN_15 */
+ } BIT; /* */
+ } GAM_R_LUT8; /* */
+ union { /* GAM_R_LUT9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_16:11; /* GAM_R_GAIN_16 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_17:11; /* GAM_R_GAIN_17 */
+ } BIT; /* */
+ } GAM_R_LUT9; /* */
+ union { /* GAM_R_LUT10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_18:11; /* GAM_R_GAIN_18 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_19:11; /* GAM_R_GAIN_19 */
+ } BIT; /* */
+ } GAM_R_LUT10; /* */
+ union { /* GAM_R_LUT11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_20:11; /* GAM_R_GAIN_20 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_21:11; /* GAM_R_GAIN_21 */
+ } BIT; /* */
+ } GAM_R_LUT11; /* */
+ union { /* GAM_R_LUT12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_22:11; /* GAM_R_GAIN_22 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_23:11; /* GAM_R_GAIN_23 */
+ } BIT; /* */
+ } GAM_R_LUT12; /* */
+ union { /* GAM_R_LUT13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_24:11; /* GAM_R_GAIN_24 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_25:11; /* GAM_R_GAIN_25 */
+ } BIT; /* */
+ } GAM_R_LUT13; /* */
+ union { /* GAM_R_LUT14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_26:11; /* GAM_R_GAIN_26 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_27:11; /* GAM_R_GAIN_27 */
+ } BIT; /* */
+ } GAM_R_LUT14; /* */
+ union { /* GAM_R_LUT15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_28:11; /* GAM_R_GAIN_28 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_29:11; /* GAM_R_GAIN_29 */
+ } BIT; /* */
+ } GAM_R_LUT15; /* */
+ union { /* GAM_R_LUT16 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_30:11; /* GAM_R_GAIN_30 */
+ _UWORD :5; /* */
+ _UWORD GAM_R_GAIN_31:11; /* GAM_R_GAIN_31 */
+ } BIT; /* */
+ } GAM_R_LUT16; /* */
+ union { /* GAM_R_AREA1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD GAM_R_TH_01:8; /* GAM_R_TH_01 */
+ _UWORD GAM_R_TH_02:8; /* GAM_R_TH_02 */
+ _UWORD GAM_R_TH_03:8; /* GAM_R_TH_03 */
+ } BIT; /* */
+ } GAM_R_AREA1; /* */
+ union { /* GAM_R_AREA2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_04:8; /* GAM_R_TH_04 */
+ _UWORD GAM_R_TH_05:8; /* GAM_R_TH_05 */
+ _UWORD GAM_R_TH_06:8; /* GAM_R_TH_06 */
+ _UWORD GAM_R_TH_07:8; /* GAM_R_TH_07 */
+ } BIT; /* */
+ } GAM_R_AREA2; /* */
+ union { /* GAM_R_AREA3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_08:8; /* GAM_R_TH_08 */
+ _UWORD GAM_R_TH_09:8; /* GAM_R_TH_09 */
+ _UWORD GAM_R_TH_10:8; /* GAM_R_TH_10 */
+ _UWORD GAM_R_TH_11:8; /* GAM_R_TH_11 */
+ } BIT; /* */
+ } GAM_R_AREA3; /* */
+ union { /* GAM_R_AREA4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_12:8; /* GAM_R_TH_12 */
+ _UWORD GAM_R_TH_13:8; /* GAM_R_TH_13 */
+ _UWORD GAM_R_TH_14:8; /* GAM_R_TH_14 */
+ _UWORD GAM_R_TH_15:8; /* GAM_R_TH_15 */
+ } BIT; /* */
+ } GAM_R_AREA4; /* */
+ union { /* GAM_R_AREA5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_16:8; /* GAM_R_TH_16 */
+ _UWORD GAM_R_TH_17:8; /* GAM_R_TH_17 */
+ _UWORD GAM_R_TH_18:8; /* GAM_R_TH_18 */
+ _UWORD GAM_R_TH_19:8; /* GAM_R_TH_19 */
+ } BIT; /* */
+ } GAM_R_AREA5; /* */
+ union { /* GAM_R_AREA6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_20:8; /* GAM_R_TH_20 */
+ _UWORD GAM_R_TH_21:8; /* GAM_R_TH_21 */
+ _UWORD GAM_R_TH_22:8; /* GAM_R_TH_22 */
+ _UWORD GAM_R_TH_23:8; /* GAM_R_TH_23 */
+ } BIT; /* */
+ } GAM_R_AREA6; /* */
+ union { /* GAM_R_AREA7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_24:8; /* GAM_R_TH_24 */
+ _UWORD GAM_R_TH_25:8; /* GAM_R_TH_25 */
+ _UWORD GAM_R_TH_26:8; /* GAM_R_TH_26 */
+ _UWORD GAM_R_TH_27:8; /* GAM_R_TH_27 */
+ } BIT; /* */
+ } GAM_R_AREA7; /* */
+ union { /* GAM_R_AREA8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD GAM_R_TH_28:8; /* GAM_R_TH_28 */
+ _UWORD GAM_R_TH_29:8; /* GAM_R_TH_29 */
+ _UWORD GAM_R_TH_30:8; /* GAM_R_TH_30 */
+ _UWORD GAM_R_TH_31:8; /* GAM_R_TH_31 */
+ } BIT; /* */
+ } GAM_R_AREA8; /* */
+ _UBYTE wk18[24]; /* */
+ union { /* TCON_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD TCON_VEN:1; /* TCON_VEN */
+ } BIT; /* */
+ } TCON_UPDATE; /* */
+ union { /* TCON_TIM */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_HALF:11; /* TCON_HALF */
+ _UWORD :5; /* */
+ _UWORD TCON_OFFSET:11; /* TCON_OFFSET */
+ } BIT; /* */
+ } TCON_TIM; /* */
+ union { /* TCON_TIM_STVA1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_STVA_VS:11; /* TCON_STVA_VS */
+ _UWORD :5; /* */
+ _UWORD TCON_STVA_VW:11; /* TCON_STVA_VW */
+ } BIT; /* */
+ } TCON_TIM_STVA1; /* */
+ union { /* TCON_TIM_STVA2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD TCON_STVA_INV:1; /* TCON_STVA_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_STVA_SEL:3; /* TCON_STVA_SEL */
+ } BIT; /* */
+ } TCON_TIM_STVA2; /* */
+ union { /* TCON_TIM_STVB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_STVB_VS:11; /* TCON_STVB_VS */
+ _UWORD :5; /* */
+ _UWORD TCON_STVB_VW:11; /* TCON_STVB_VW */
+ } BIT; /* */
+ } TCON_TIM_STVB1; /* */
+ union { /* TCON_TIM_STVB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD TCON_STVB_INV:1; /* TCON_STVB_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_STVB_SEL:3; /* TCON_STVB_SEL */
+ } BIT; /* */
+ } TCON_TIM_STVB2; /* */
+ union { /* TCON_TIM_STH1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_STH_HS:11; /* TCON_STH_HS */
+ _UWORD :5; /* */
+ _UWORD TCON_STH_HW:11; /* TCON_STH_HW */
+ } BIT; /* */
+ } TCON_TIM_STH1; /* */
+ union { /* TCON_TIM_STH2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD TCON_STH_HS_SEL:1; /* TCON_STH_HS_SEL */
+ _UDWORD :3; /* */
+ _UDWORD TCON_STH_INV:1; /* TCON_STH_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_STH_SEL:3; /* TCON_STH_SEL */
+ } BIT; /* */
+ } TCON_TIM_STH2; /* */
+ union { /* TCON_TIM_STB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_STB_HS:11; /* TCON_STB_HS */
+ _UWORD :5; /* */
+ _UWORD TCON_STB_HW:11; /* TCON_STB_HW */
+ } BIT; /* */
+ } TCON_TIM_STB1; /* */
+ union { /* TCON_TIM_STB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD TCON_STB_HS_SEL:1; /* TCON_STB_HS_SEL */
+ _UDWORD :3; /* */
+ _UDWORD TCON_STB_INV:1; /* TCON_STB_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_STB_SEL:3; /* TCON_STB_SEL */
+ } BIT; /* */
+ } TCON_TIM_STB2; /* */
+ union { /* TCON_TIM_CPV1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_CPV_HS:11; /* TCON_CPV_HS */
+ _UWORD :5; /* */
+ _UWORD TCON_CPV_HW:11; /* TCON_CPV_HW */
+ } BIT; /* */
+ } TCON_TIM_CPV1; /* */
+ union { /* TCON_TIM_CPV2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD TCON_CPV_HS_SEL:1; /* TCON_CPV_HS_SEL */
+ _UDWORD :3; /* */
+ _UDWORD TCON_CPV_INV:1; /* TCON_CPV_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_CPV_SEL:3; /* TCON_CPV_SEL */
+ } BIT; /* */
+ } TCON_TIM_CPV2; /* */
+ union { /* TCON_TIM_POLA1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_POLA_HS:11; /* TCON_POLA_HS */
+ _UWORD :5; /* */
+ _UWORD TCON_POLA_HW:11; /* TCON_POLA_HW */
+ } BIT; /* */
+ } TCON_TIM_POLA1; /* */
+ union { /* TCON_TIM_POLA2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :18; /* */
+ _UDWORD TCON_POLA_MD:2; /* TCON_POLA_MD */
+ _UDWORD :3; /* */
+ _UDWORD TCON_POLA_HS_SEL:1; /* TCON_POLA_HS_SEL */
+ _UDWORD :3; /* */
+ _UDWORD TCON_POLA_INV:1; /* TCON_POLA_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_POLA_SEL:3; /* TCON_POLA_SEL */
+ } BIT; /* */
+ } TCON_TIM_POLA2; /* */
+ union { /* TCON_TIM_POLB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD TCON_POLB_HS:11; /* TCON_POLB_HS */
+ _UWORD :5; /* */
+ _UWORD TCON_POLB_HW:11; /* TCON_POLB_HW */
+ } BIT; /* */
+ } TCON_TIM_POLB1; /* */
+ union { /* TCON_TIM_POLB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :18; /* */
+ _UDWORD TCON_POLB_MD:2; /* TCON_POLB_MD */
+ _UDWORD :3; /* */
+ _UDWORD TCON_POLB_HS_SEL:1; /* TCON_POLB_HS_SEL */
+ _UDWORD :3; /* */
+ _UDWORD TCON_POLB_INV:1; /* TCON_POLB_INV */
+ _UDWORD :1; /* */
+ _UDWORD TCON_POLB_SEL:3; /* TCON_POLB_SEL */
+ } BIT; /* */
+ } TCON_TIM_POLB2; /* */
+ union { /* TCON_TIM_DE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD TCON_DE_INV:1; /* TCON_DE_INV */
+ } BIT; /* */
+ } TCON_TIM_DE; /* */
+ _UBYTE wk19[60]; /* */
+ union { /* OUT_UPDATE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD OUTCNT_VEN:1; /* OUTCNT_VEN */
+ } BIT; /* */
+ } OUT_UPDATE; /* */
+ union { /* OUT_SET */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OUT_ENDIAN_ON:1; /* OUT_ENDIAN_ON */
+ _UWORD :3; /* */
+ _UWORD OUT_SWAP_ON:1; /* OUT_SWAP_ON */
+ _UWORD :8; /* */
+ _UWORD :2; /* */
+ _UWORD OUT_FORMAT:2; /* OUT_FORMAT */
+ _UWORD :2; /* */
+ _UWORD OUT_FRQ_SEL:2; /* OUT_FRQ_SEL */
+ _UWORD :3; /* */
+ _UWORD OUT_DIR_SEL:1; /* OUT_DIR_SEL */
+ _UWORD :2; /* */
+ _UWORD OUT_PHASE:2; /* OUT_PHASE */
+ } BIT; /* */
+ } OUT_SET; /* */
+ union { /* OUT_BRIGHT1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD PBRT_G:10; /* PBRT_G */
+ } BIT; /* */
+ } OUT_BRIGHT1; /* */
+ union { /* OUT_BRIGHT2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD PBRT_B:10; /* PBRT_B */
+ _UWORD :6; /* */
+ _UWORD PBRT_R:10; /* PBRT_R */
+ } BIT; /* */
+ } OUT_BRIGHT2; /* */
+ union { /* OUT_CONTRAST */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD CONT_G:8; /* CONT_G */
+ _UWORD CONT_B:8; /* CONT_B */
+ _UWORD CONT_R:8; /* CONT_R */
+ } BIT; /* */
+ } OUT_CONTRAST; /* */
+ union { /* OUT_PDTHA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :10; /* */
+ _UWORD PDTH_SEL:2; /* PDTH_SEL */
+ _UWORD :2; /* */
+ _UWORD PDTH_FORMAT:2; /* PDTH_FORMAT */
+ _UWORD :2; /* */
+ _UWORD PDTH_PA:2; /* PDTH_PA */
+ _UWORD :2; /* */
+ _UWORD PDTH_PB:2; /* PDTH_PB */
+ _UWORD :2; /* */
+ _UWORD PDTH_PC:2; /* PDTH_PC */
+ _UWORD :2; /* */
+ _UWORD PDTH_PD:2; /* PDTH_PD */
+ } BIT; /* */
+ } OUT_PDTHA; /* */
+ _UBYTE wk20[12]; /* */
+ union { /* OUT_CLK_PHASE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :19; /* */
+ _UDWORD OUTCNT_FRONT_GAM:1; /* OUTCNT_FRONT_GAM */
+ _UDWORD :3; /* */
+ _UDWORD OUTCNT_LCD_EDGE:1; /* OUTCNT_LCD_EDGE */
+ _UDWORD :1; /* */
+ _UDWORD OUTCNT_STVA_EDGE:1; /* OUTCNT_STVA_EDGE */
+ _UDWORD OUTCNT_STVB_EDGE:1; /* OUTCNT_STVB_EDGE */
+ _UDWORD OUTCNT_STH_EDGE:1; /* OUTCNT_STH_EDGE */
+ _UDWORD OUTCNT_STB_EDGE:1; /* OUTCNT_STB_EDGE */
+ _UDWORD OUTCNT_CPV_EDGE:1; /* OUTCNT_CPV_EDGE */
+ _UDWORD OUTCNT_POLA_EDGE:1; /* OUTCNT_POLA_EDGE */
+ _UDWORD OUTCNT_POLB_EDGE:1; /* OUTCNT_POLB_EDGE */
+ } BIT; /* */
+ } OUT_CLK_PHASE; /* */
+ _UBYTE wk21[88]; /* */
+ union { /* SYSCNT_INT1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD INT_STA8:1; /* INT_STA8 */
+ } BIT; /* */
+ } SYSCNT_INT1; /* */
+ union { /* SYSCNT_INT2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD INT_STA7:1; /* INT_STA7 */
+ _UWORD :3; /* */
+ _UWORD INT_STA6:1; /* INT_STA6 */
+ _UWORD :3; /* */
+ _UWORD INT_STA5:1; /* INT_STA5 */
+ _UWORD :3; /* */
+ _UWORD INT_STA4:1; /* INT_STA4 */
+ _UWORD :3; /* */
+ _UWORD INT_STA3:1; /* INT_STA3 */
+ _UWORD :3; /* */
+ _UWORD INT_STA2:1; /* INT_STA2 */
+ _UWORD :3; /* */
+ _UWORD INT_STA1:1; /* INT_STA1 */
+ _UWORD :3; /* */
+ _UWORD INT_STA0:1; /* INT_STA0 */
+ } BIT; /* */
+ } SYSCNT_INT2; /* */
+ union { /* SYSCNT_INT3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD INT_OUT8_ON:1; /* INT_OUT8_ON */
+ } BIT; /* */
+ } SYSCNT_INT3; /* */
+ union { /* SYSCNT_INT4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD INT_OUT7_ON:1; /* INT_OUT7_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT6_ON:1; /* INT_OUT6_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT5_ON:1; /* INT_OUT5_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT4_ON:1; /* INT_OUT4_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT3_ON:1; /* INT_OUT3_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT2_ON:1; /* INT_OUT2_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT1_ON:1; /* INT_OUT1_ON */
+ _UWORD :3; /* */
+ _UWORD INT_OUT0_ON:1; /* INT_OUT0_ON */
+ } BIT; /* */
+ } SYSCNT_INT4; /* */
+ union { /* SYSCNT_PANEL_CLK */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD PANEL_ICKSEL:2; /* PANEL_ICKSEL */
+ _UWORD :3; /* */
+ _UWORD PANEL_ICKEN:1; /* PANEL_ICKEN */
+ _UWORD :2; /* */
+ _UWORD PANEL_DCDR:6; /* PANEL_DCDR */
+ } BIT; /* */
+ } SYSCNT_PANEL_CLK; /* */
+ union { /* SYSCNT_CLUT */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD GR3_CLT_SEL_ST:1; /* GR3_CLT_SEL_ST */
+ _UWORD :3; /* */
+ _UWORD GR2_CLT_SEL_ST:1; /* GR2_CLT_SEL_ST */
+ _UWORD :3; /* */
+ _UWORD GR1_CLT_SEL_ST:1; /* GR1_CLT_SEL_ST */
+ } BIT; /* */
+ } SYSCNT_CLUT; /* */
+}; /* */
+struct st_src { /* struct SRC */
+ union { /* SRCID */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ } SRCID; /* */
+ union { /* SRCOD */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ } SRCOD; /* */
+ union { /* SRCIDCTRL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD IED:1; /* IED */
+ _UWORD IEN:1; /* IEN */
+ _UWORD :6; /* */
+ _UWORD IFTRG:2; /* IFTRG */
+ } BIT; /* */
+ } SRCIDCTRL; /* */
+ union { /* SRCODCTRL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD OCH:1; /* OCH */
+ _UWORD OED:1; /* OED */
+ _UWORD OEN:1; /* OEN */
+ _UWORD :6; /* */
+ _UWORD OFTRG:2; /* OFTRG */
+ } BIT; /* */
+ } SRCODCTRL; /* */
+ union { /* SRCCTRL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD CEEN:1; /* CEEN */
+ _UWORD SRCEN:1; /* SRCEN */
+ _UWORD UDEN:1; /* UDEN */
+ _UWORD OVEN:1; /* OVEN */
+ _UWORD FL:1; /* FL */
+ _UWORD CL:1; /* CL */
+ _UWORD IFS:4; /* IFS */
+ _UWORD :1; /* */
+ _UWORD OFS:3; /* OFS */
+ } BIT; /* */
+ } SRCCTRL; /* */
+ union { /* SRCSTAT */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD OFDN:5; /* OFDN */
+ _UWORD IFDN:4; /* IFDN */
+ _UWORD :1; /* */
+ _UWORD CEF:1; /* CEF */
+ _UWORD FLF:1; /* FLF */
+ _UWORD UDF:1; /* UDF */
+ _UWORD OVF:1; /* OVF */
+ _UWORD IINT:1; /* IINT */
+ _UWORD OINT:1; /* OINT */
+ } BIT; /* */
+ } SRCSTAT; /* */
+}; /* */
+ #if 0
+struct st_gpio { /* struct GPIO */
+ _UBYTE wk0[2]; /* */
+ union { /* PAIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE PA1IOR:1; /* PA1IOR */
+ _UBYTE :7; /* */
+ _UBYTE PA0IOR:1; /* PA0IOR */
+ } BIT; /* */
+ } PAIOR0; /* */
+ _UBYTE wk1[2]; /* */
+ union { /* PADR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE PA1DR:1; /* PA1DR */
+ _UBYTE :7; /* */
+ _UBYTE PA0DR:1; /* PA0DR */
+ } BIT; /* */
+ } PADR0; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* PAPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE :6; /* */
+ _UBYTE PA1PR:1; /* PA1PR */
+ _UBYTE PA0PR:1; /* PA0PR */
+ } BIT; /* */
+ } PAPR0; /* */
+ _UBYTE wk3[8]; /* */
+ union { /* PBCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE PB22MD:3; /* PB22MD */
+ _UBYTE :2; /* */
+ _UBYTE PB21MD:2; /* PB21MD */
+ _UBYTE :1; /* */
+ _UBYTE PB20MD:3; /* PB20MD */
+ } BIT; /* */
+ } PBCR5; /* */
+ union { /* PBCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PB19MD:3; /* PB19MD */
+ _UBYTE :1; /* */
+ _UBYTE PB18MD:3; /* PB18MD */
+ _UBYTE :1; /* */
+ _UBYTE PB17MD:3; /* PB17MD */
+ _UBYTE :1; /* */
+ _UBYTE PB16MD:3; /* PB16MD */
+ } BIT; /* */
+ } PBCR4; /* */
+ union { /* PBCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PB15MD:3; /* PB15MD */
+ _UBYTE :1; /* */
+ _UBYTE PB14MD:3; /* PB14MD */
+ _UBYTE :1; /* */
+ _UBYTE PB13MD:3; /* PB13MD */
+ _UBYTE :2; /* */
+ _UBYTE PB12MD:2; /* PB12MD */
+ } BIT; /* */
+ } PBCR3; /* */
+ union { /* PBCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PB11MD:2; /* PB11MD */
+ _UBYTE :2; /* */
+ _UBYTE PB10MD:2; /* PB10MD */
+ _UBYTE :2; /* */
+ _UBYTE PB9MD:2; /* PB9MD */
+ _UBYTE :2; /* */
+ _UBYTE PB8MD:2; /* PB8MD */
+ } BIT; /* */
+ } PBCR2; /* */
+ union { /* PBCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PB7MD:2; /* PB7MD */
+ _UBYTE :2; /* */
+ _UBYTE PB6MD:2; /* PB6MD */
+ _UBYTE :2; /* */
+ _UBYTE PB5MD:2; /* PB5MD */
+ _UBYTE :2; /* */
+ _UBYTE PB4MD:2; /* PB4MD */
+ } BIT; /* */
+ } PBCR1; /* */
+ union { /* PBCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PB3MD:2; /* PB3MD */
+ _UBYTE :2; /* */
+ _UBYTE PB2MD:2; /* PB2MD */
+ _UBYTE :2; /* */
+ _UBYTE PB1MD:2; /* PB1MD */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } PBCR0; /* */
+ union { /* PBIOR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE :1; /* */
+ _UBYTE PB22IOR:1; /* PB22IOR */
+ _UBYTE PB21IOR:1; /* PB21IOR */
+ _UBYTE PB20IOR:1; /* PB20IOR */
+ _UBYTE PB19IOR:1; /* PB19IOR */
+ _UBYTE PB18IOR:1; /* PB18IOR */
+ _UBYTE PB17IOR:1; /* PB17IOR */
+ _UBYTE PB16IOR:1; /* PB16IOR */
+ } BIT; /* */
+ } PBIOR1; /* */
+ union { /* PBIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PB15IOR:1; /* PB15IOR */
+ _UBYTE PB14IOR:1; /* PB14IOR */
+ _UBYTE PB13IOR:1; /* PB13IOR */
+ _UBYTE PB12IOR:1; /* PB12IOR */
+ _UBYTE PB11IOR:1; /* PB11IOR */
+ _UBYTE PB10IOR:1; /* PB10IOR */
+ _UBYTE PB9IOR:1; /* PB9IOR */
+ _UBYTE PB8IOR:1; /* PB8IOR */
+ _UBYTE PB7IOR:1; /* PB7IOR */
+ _UBYTE PB6IOR:1; /* PB6IOR */
+ _UBYTE PB5IOR:1; /* PB5IOR */
+ _UBYTE PB4IOR:1; /* PB4IOR */
+ _UBYTE PB3IOR:1; /* PB3IOR */
+ _UBYTE PB2IOR:1; /* PB2IOR */
+ _UBYTE PB1IOR:1; /* PB1IOR */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } PBIOR0; /* */
+ union { /* PBDR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE :1; /* */
+ _UBYTE PB22DR:1; /* PB22DR */
+ _UBYTE PB21DR:1; /* PB21DR */
+ _UBYTE PB20DR:1; /* PB20DR */
+ _UBYTE PB19DR:1; /* PB19DR */
+ _UBYTE PB18DR:1; /* PB18DR */
+ _UBYTE PB17DR:1; /* PB17DR */
+ _UBYTE PB16DR:1; /* PB16DR */
+ } BIT; /* */
+ } PBDR1; /* */
+ union { /* PBDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PB15DR:1; /* PB15DR */
+ _UBYTE PB14DR:1; /* PB14DR */
+ _UBYTE PB13DR:1; /* PB13DR */
+ _UBYTE PB12DR:1; /* PB12DR */
+ _UBYTE PB11DR:1; /* PB11DR */
+ _UBYTE PB10DR:1; /* PB10DR */
+ _UBYTE PB9DR:1; /* PB9DR */
+ _UBYTE PB8DR:1; /* PB8DR */
+ _UBYTE PB7DR:1; /* PB7DR */
+ _UBYTE PB6DR:1; /* PB6DR */
+ _UBYTE PB5DR:1; /* PB5DR */
+ _UBYTE PB4DR:1; /* PB4DR */
+ _UBYTE PB3DR:1; /* PB3DR */
+ _UBYTE PB2DR:1; /* PB2DR */
+ _UBYTE PB1DR:1; /* PB1DR */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } PBDR0; /* */
+ union { /* PBPR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE :1; /* */
+ _UBYTE PB22PR:1; /* PB22PR */
+ _UBYTE PB21PR:1; /* PB21PR */
+ _UBYTE PB20PR:1; /* PB20PR */
+ _UBYTE PB19PR:1; /* PB19PR */
+ _UBYTE PB18PR:1; /* PB18PR */
+ _UBYTE PB17PR:1; /* PB17PR */
+ _UBYTE PB16PR:1; /* PB16PR */
+ } BIT; /* */
+ } PBPR1; /* */
+ union { /* PBPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PB15PR:1; /* PB15PR */
+ _UBYTE PB14PR:1; /* PB14PR */
+ _UBYTE PB13PR:1; /* PB13PR */
+ _UBYTE PB12PR:1; /* PB12PR */
+ _UBYTE PB11PR:1; /* PB11PR */
+ _UBYTE PB10PR:1; /* PB10PR */
+ _UBYTE PB9PR:1; /* PB9PR */
+ _UBYTE PB8PR:1; /* PB8PR */
+ _UBYTE PB7PR:1; /* PB7PR */
+ _UBYTE PB6PR:1; /* PB6PR */
+ _UBYTE PB5PR:1; /* PB5PR */
+ _UBYTE PB4PR:1; /* PB4PR */
+ _UBYTE PB3PR:1; /* PB3PR */
+ _UBYTE PB2PR:1; /* PB2PR */
+ _UBYTE PB1PR:1; /* PB1PR */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } PBPR0; /* */
+ _UBYTE wk4[14]; /* */
+ union { /* PCCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE :5; /* */
+ _UBYTE PC8MD:3; /* PC8MD */
+ } BIT; /* */
+ } PCCR2; /* */
+ union { /* PCCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PC7MD:3; /* PC7MD */
+ _UBYTE :1; /* */
+ _UBYTE PC6MD:3; /* PC6MD */
+ _UBYTE :1; /* */
+ _UBYTE PC5MD:3; /* PC5MD */
+ _UBYTE :2; /* */
+ _UBYTE PC4MD:2; /* PC4MD */
+ } BIT; /* */
+ } PCCR1; /* */
+ union { /* PCCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PC3MD:2; /* PC3MD */
+ _UBYTE :2; /* */
+ _UBYTE PC2MD:2; /* PC2MD */
+ _UBYTE :3; /* */
+ _UBYTE PC1MD:1; /* PC1MD */
+ _UBYTE :3; /* */
+ _UBYTE PC0MD:1; /* PC0MD */
+ } BIT; /* */
+ } PCCR0; /* */
+ _UBYTE wk5[2]; /* */
+ union { /* PCIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE PC8IOR:1; /* PC8IOR */
+ _UBYTE PC7IOR:1; /* PC7IOR */
+ _UBYTE PC6IOR:1; /* PC6IOR */
+ _UBYTE PC5IOR:1; /* PC5IOR */
+ _UBYTE PC4IOR:1; /* PC4IOR */
+ _UBYTE PC3IOR:1; /* PC3IOR */
+ _UBYTE PC2IOR:1; /* PC2IOR */
+ _UBYTE PC1IOR:1; /* PC1IOR */
+ _UBYTE PC0IOR:1; /* PC0IOR */
+ } BIT; /* */
+ } PCIOR0; /* */
+ _UBYTE wk6[2]; /* */
+ union { /* PCDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE PC8DR:1; /* PC8DR */
+ _UBYTE PC7DR:1; /* PC7DR */
+ _UBYTE PC6DR:1; /* PC6DR */
+ _UBYTE PC5DR:1; /* PC5DR */
+ _UBYTE PC4DR:1; /* PC4DR */
+ _UBYTE PC3DR:1; /* PC3DR */
+ _UBYTE PC2DR:1; /* PC2DR */
+ _UBYTE PC1DR:1; /* PC1DR */
+ _UBYTE PC0DR:1; /* PC0DR */
+ } BIT; /* */
+ } PCDR0; /* */
+ _UBYTE wk7[2]; /* */
+ union { /* PCPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE PC8PR:1; /* PC8PR */
+ _UBYTE PC7PR:1; /* PC7PR */
+ _UBYTE PC6PR:1; /* PC6PR */
+ _UBYTE PC5PR:1; /* PC5PR */
+ _UBYTE PC4PR:1; /* PC4PR */
+ _UBYTE PC3PR:1; /* PC3PR */
+ _UBYTE PC2PR:1; /* PC2PR */
+ _UBYTE PC1PR:1; /* PC1PR */
+ _UBYTE PC0PR:1; /* PC0PR */
+ } BIT; /* */
+ } PCPR0; /* */
+ _UBYTE wk8[12]; /* */
+ union { /* PDCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PD15MD:2; /* PD15MD */
+ _UBYTE :2; /* */
+ _UBYTE PD14MD:2; /* PD14MD */
+ _UBYTE :2; /* */
+ _UBYTE PD13MD:2; /* PD13MD */
+ _UBYTE :2; /* */
+ _UBYTE PD12MD:2; /* PD12MD */
+ } BIT; /* */
+ } PDCR3; /* */
+ union { /* PDCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PD11MD:2; /* PD11MD */
+ _UBYTE :2; /* */
+ _UBYTE PD10MD:2; /* PD10MD */
+ _UBYTE :2; /* */
+ _UBYTE PD9MD:2; /* PD9MD */
+ _UBYTE :2; /* */
+ _UBYTE PD8MD:2; /* PD8MD */
+ } BIT; /* */
+ } PDCR2; /* */
+ union { /* PDCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PD7MD:2; /* PD7MD */
+ _UBYTE :2; /* */
+ _UBYTE PD6MD:2; /* PD6MD */
+ _UBYTE :2; /* */
+ _UBYTE PD5MD:2; /* PD5MD */
+ _UBYTE :2; /* */
+ _UBYTE PD4MD:2; /* PD4MD */
+ } BIT; /* */
+ } PDCR1; /* */
+ union { /* PDCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PD3MD:2; /* PD3MD */
+ _UBYTE :2; /* */
+ _UBYTE PD2MD:2; /* PD2MD */
+ _UBYTE :2; /* */
+ _UBYTE PD1MD:2; /* PD1MD */
+ _UBYTE :2; /* */
+ _UBYTE PD0MD:2; /* PD0MD */
+ } BIT; /* */
+ } PDCR0; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* PDIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PD15IOR:1; /* PD15IOR */
+ _UBYTE PD14IOR:1; /* PD14IOR */
+ _UBYTE PD13IOR:1; /* PD13IOR */
+ _UBYTE PD12IOR:1; /* PD12IOR */
+ _UBYTE PD11IOR:1; /* PD11IOR */
+ _UBYTE PD10IOR:1; /* PD10IOR */
+ _UBYTE PD9IOR:1; /* PD9IOR */
+ _UBYTE PD8IOR:1; /* PD8IOR */
+ _UBYTE PD7IOR:1; /* PD7IOR */
+ _UBYTE PD6IOR:1; /* PD6IOR */
+ _UBYTE PD5IOR:1; /* PD5IOR */
+ _UBYTE PD4IOR:1; /* PD4IOR */
+ _UBYTE PD3IOR:1; /* PD3IOR */
+ _UBYTE PD2IOR:1; /* PD2IOR */
+ _UBYTE PD1IOR:1; /* PD1IOR */
+ _UBYTE PD0IOR:1; /* PD0IOR */
+ } BIT; /* */
+ } PDIOR0; /* */
+ _UBYTE wk10[2]; /* */
+ union { /* PDDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PD15DR:1; /* PD15DR */
+ _UBYTE PD14DR:1; /* PD14DR */
+ _UBYTE PD13DR:1; /* PD13DR */
+ _UBYTE PD12DR:1; /* PD12DR */
+ _UBYTE PD11DR:1; /* PD11DR */
+ _UBYTE PD10DR:1; /* PD10DR */
+ _UBYTE PD9DR:1; /* PD9DR */
+ _UBYTE PD8DR:1; /* PD8DR */
+ _UBYTE PD7DR:1; /* PD7DR */
+ _UBYTE PD6DR:1; /* PD6DR */
+ _UBYTE PD5DR:1; /* PD5DR */
+ _UBYTE PD4DR:1; /* PD4DR */
+ _UBYTE PD3DR:1; /* PD3DR */
+ _UBYTE PD2DR:1; /* PD2DR */
+ _UBYTE PD1DR:1; /* PD1DR */
+ _UBYTE PD0DR:1; /* PD0DR */
+ } BIT; /* */
+ } PDDR0; /* */
+ _UBYTE wk11[2]; /* */
+ union { /* PDPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PD15PR:1; /* PD15PR */
+ _UBYTE PD14PR:1; /* PD14PR */
+ _UBYTE PD13PR:1; /* PD13PR */
+ _UBYTE PD12PR:1; /* PD12PR */
+ _UBYTE PD11PR:1; /* PD11PR */
+ _UBYTE PD10PR:1; /* PD10PR */
+ _UBYTE PD9PR:1; /* PD9PR */
+ _UBYTE PD8PR:1; /* PD8PR */
+ _UBYTE PD7PR:1; /* PD7PR */
+ _UBYTE PD6PR:1; /* PD6PR */
+ _UBYTE PD5PR:1; /* PD5PR */
+ _UBYTE PD4PR:1; /* PD4PR */
+ _UBYTE PD3PR:1; /* PD3PR */
+ _UBYTE PD2PR:1; /* PD2PR */
+ _UBYTE PD1PR:1; /* PD1PR */
+ _UBYTE PD0PR:1; /* PD0PR */
+ } BIT; /* */
+ } PDPR0; /* */
+ _UBYTE wk12[16]; /* */
+ union { /* PECR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PE7MD:2; /* PE7MD */
+ _UBYTE :2; /* */
+ _UBYTE PE6MD:2; /* PE6MD */
+ _UBYTE :2; /* */
+ _UBYTE PE5MD:2; /* PE5MD */
+ _UBYTE :2; /* */
+ _UBYTE PE4MD:2; /* PE4MD */
+ } BIT; /* */
+ } PECR1; /* */
+ union { /* PECR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PE3MD:3; /* PE3MD */
+ _UBYTE :1; /* */
+ _UBYTE PE2MD:3; /* PE2MD */
+ _UBYTE :1; /* */
+ _UBYTE PE1MD:3; /* PE1MD */
+ _UBYTE :2; /* */
+ _UBYTE PE0MD:2; /* PE0MD */
+ } BIT; /* */
+ } PECR0; /* */
+ _UBYTE wk13[2]; /* */
+ union { /* PEIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PE7IOR:1; /* PE7IOR */
+ _UBYTE PE6IOR:1; /* PE6IOR */
+ _UBYTE PE5IOR:1; /* PE5IOR */
+ _UBYTE PE4IOR:1; /* PE4IOR */
+ _UBYTE PE3IOR:1; /* PE3IOR */
+ _UBYTE PE2IOR:1; /* PE2IOR */
+ _UBYTE PE1IOR:1; /* PE1IOR */
+ _UBYTE PE0IOR:1; /* PE0IOR */
+ } BIT; /* */
+ } PEIOR0; /* */
+ _UBYTE wk14[2]; /* */
+ union { /* PEDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PE7DR:1; /* PE7DR */
+ _UBYTE PE6DR:1; /* PE6DR */
+ _UBYTE PE5DR:1; /* PE5DR */
+ _UBYTE PE4DR:1; /* PE4DR */
+ _UBYTE PE3DR:1; /* PE3DR */
+ _UBYTE PE2DR:1; /* PE2DR */
+ _UBYTE PE1DR:1; /* PE1DR */
+ _UBYTE PE0DR:1; /* PE0DR */
+ } BIT; /* */
+ } PEDR0; /* */
+ _UBYTE wk15[2]; /* */
+ union { /* PEPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PE7PR:1; /* PE7PR */
+ _UBYTE PE6PR:1; /* PE6PR */
+ _UBYTE PE5PR:1; /* PE5PR */
+ _UBYTE PE4PR:1; /* PE4PR */
+ _UBYTE PE3PR:1; /* PE3PR */
+ _UBYTE PE2PR:1; /* PE2PR */
+ _UBYTE PE1PR:1; /* PE1PR */
+ _UBYTE PE0PR:1; /* PE0PR */
+ } BIT; /* */
+ } PEPR0; /* */
+ _UBYTE wk16[6]; /* */
+ union { /* PFCR6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PF23MD :3; /* PF23MD */
+ _UBYTE :1; /* */
+ _UBYTE PF22MD :3; /* PF22MD */
+ _UBYTE :1; /* */
+ _UBYTE PF21MD :3; /* PF21MD */
+ _UBYTE :1; /* */
+ _UBYTE PF20MD :3; /* PF20MD */
+ } BIT; /* */
+ } PFCR6; /* */
+ union { /* PFCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PF19MD :3; /* PF19MD */
+ _UBYTE :1; /* */
+ _UBYTE PF18MD :3; /* PF18MD */
+ _UBYTE :1; /* */
+ _UBYTE PF17MD :3; /* PF17MD */
+ _UBYTE :1; /* */
+ _UBYTE PF16MD :3; /* PF16MD */
+ } BIT; /* */
+ } PFCR5; /* */
+ union { /* PFCR4 */
+ _UWORD WORD; /* Read/Write Access */
+ } PFCR4; /* Writing H'5A in the upper byte */
+ union { /* PFCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE PF14MD:3; /* PF14MD */
+ _UBYTE :1; /* */
+ _UBYTE PF13MD:3; /* PF13MD */
+ _UBYTE :1; /* */
+ _UBYTE PF12MD:3; /* PF12MD */
+ } BIT; /* */
+ } PFCR3; /* */
+ union { /* PFCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PF11MD:3; /* PF11MD */
+ _UBYTE :1; /* */
+ _UBYTE PF10MD:3; /* PF10MD */
+ _UBYTE :1; /* */
+ _UBYTE PF9MD:3; /* PF9MD */
+ _UBYTE :1; /* */
+ _UBYTE PF8MD:3; /* PF8MD */
+ } BIT; /* */
+ } PFCR2; /* */
+ union { /* PFCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PF7MD:3; /* PF7MD */
+ _UBYTE :1; /* */
+ _UBYTE PF6MD:3; /* PF6MD */
+ _UBYTE :1; /* */
+ _UBYTE PF5MD:3; /* PF5MD */
+ _UBYTE :1; /* */
+ _UBYTE PF4MD:3; /* PF4MD */
+ } BIT; /* */
+ } PFCR1; /* */
+ union { /* PFCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PF3MD:3; /* PF3MD */
+ _UBYTE :1; /* */
+ _UBYTE PF2MD:3; /* PF2MD */
+ _UBYTE :1; /* */
+ _UBYTE PF1MD:3; /* PF1MD */
+ _UBYTE :1; /* */
+ _UBYTE PF0MD:3; /* PF0MD */
+ } BIT; /* */
+ } PFCR0; /* */
+ union { /* PFIOR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PF23IOR:1; /* PF23IOR */
+ _UBYTE PF22IOR:1; /* PF22IOR */
+ _UBYTE PF21IOR:1; /* PF21IOR */
+ _UBYTE PF20IOR:1; /* PF20IOR */
+ _UBYTE PF19IOR:1; /* PF19IOR */
+ _UBYTE PF18IOR:1; /* PF18IOR */
+ _UBYTE PF17IOR:1; /* PF17IOR */
+ _UBYTE PF16IOR:1; /* PF16IOR */
+ } BIT; /* */
+ } PFIOR1; /* */
+ union { /* PFIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PF15IOR:1; /* PF15IOR */
+ _UBYTE PF14IOR:1; /* PF14IOR */
+ _UBYTE PF13IOR:1; /* PF13IOR */
+ _UBYTE PF12IOR:1; /* PF12IOR */
+ _UBYTE PF11IOR:1; /* PF11IOR */
+ _UBYTE PF10IOR:1; /* PF10IOR */
+ _UBYTE PF9IOR:1; /* PF9IOR */
+ _UBYTE PF8IOR:1; /* PF8IOR */
+ _UBYTE PF7IOR:1; /* PF7IOR */
+ _UBYTE PF6IOR:1; /* PF6IOR */
+ _UBYTE PF5IOR:1; /* PF5IOR */
+ _UBYTE PF4IOR:1; /* PF4IOR */
+ _UBYTE PF3IOR:1; /* PF3IOR */
+ _UBYTE PF2IOR:1; /* PF2IOR */
+ _UBYTE PF1IOR:1; /* PF1IOR */
+ _UBYTE PF0IOR:1; /* PF0IOR */
+ } BIT; /* */
+ } PFIOR0; /* */
+ union { /* PFDR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PF23DR:1; /* PF23DR */
+ _UBYTE PF22DR:1; /* PF22DR */
+ _UBYTE PF21DR:1; /* PF21DR */
+ _UBYTE PF20DR:1; /* PF20DR */
+ _UBYTE PF19DR:1; /* PF19DR */
+ _UBYTE PF18DR:1; /* PF18DR */
+ _UBYTE PF17DR:1; /* PF17DR */
+ _UBYTE PF16DR:1; /* PF16DR */
+ } BIT; /* */
+ } PFDR1; /* */
+ union { /* PFDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PF15DR:1; /* PF15DR */
+ _UBYTE PF14DR:1; /* PF14DR */
+ _UBYTE PF13DR:1; /* PF13DR */
+ _UBYTE PF12DR:1; /* PF12DR */
+ _UBYTE PF11DR:1; /* PF11DR */
+ _UBYTE PF10DR:1; /* PF10DR */
+ _UBYTE PF9DR:1; /* PF9DR */
+ _UBYTE PF8DR:1; /* PF8DR */
+ _UBYTE PF7DR:1; /* PF7DR */
+ _UBYTE PF6DR:1; /* PF6DR */
+ _UBYTE PF5DR:1; /* PF5DR */
+ _UBYTE PF4DR:1; /* PF4DR */
+ _UBYTE PF3DR:1; /* PF3DR */
+ _UBYTE PF2DR:1; /* PF2DR */
+ _UBYTE PF1DR:1; /* PF1DR */
+ _UBYTE PF0DR:1; /* PF0DR */
+ } BIT; /* */
+ } PFDR0; /* */
+ union { /* PFPR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PF23PR:1; /* PF23PR */
+ _UBYTE PF22PR:1; /* PF22PR */
+ _UBYTE PF21PR:1; /* PF21PR */
+ _UBYTE PF20PR:1; /* PF20PR */
+ _UBYTE PF19PR:1; /* PF19PR */
+ _UBYTE PF18PR:1; /* PF18PR */
+ _UBYTE PF17PR:1; /* PF17PR */
+ _UBYTE PF16PR:1; /* PF16PR */
+ } BIT; /* */
+ } PFPR1; /* */
+ union { /* PFPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PF15PR:1; /* PF15PR */
+ _UBYTE PF14PR:1; /* PF14PR */
+ _UBYTE PF13PR:1; /* PF13PR */
+ _UBYTE PF12PR:1; /* PF12PR */
+ _UBYTE PF11PR:1; /* PF11PR */
+ _UBYTE PF10PR:1; /* PF10PR */
+ _UBYTE PF9PR:1; /* PF9PR */
+ _UBYTE PF8PR:1; /* PF8PR */
+ _UBYTE PF7PR:1; /* PF7PR */
+ _UBYTE PF6PR:1; /* PF6PR */
+ _UBYTE PF5PR:1; /* PF5PR */
+ _UBYTE PF4PR:1; /* PF4PR */
+ _UBYTE PF3PR:1; /* PF3PR */
+ _UBYTE PF2PR:1; /* PF2PR */
+ _UBYTE PF1PR:1; /* PF1PR */
+ _UBYTE PF0PR:1; /* PF0PR */
+ } BIT; /* */
+ } PFPR0; /* */
+ _UBYTE wk17[6]; /* */
+ union { /* PGCR6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PG27MD:2; /* PG27MD */
+ _UBYTE :2; /* */
+ _UBYTE PG26MD:2; /* PG26MD */
+ _UBYTE :2; /* */
+ _UBYTE PG25MD:2; /* PG25MD */
+ _UBYTE :2; /* */
+ _UBYTE PG24MD:2; /* PG24MD */
+ } BIT; /* */
+ } PGCR6; /* */
+ union { /* PGCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PG23MD:3; /* PG23MD */
+ _UBYTE :1; /* */
+ _UBYTE PG22MD:3; /* PG22MD */
+ _UBYTE :1; /* */
+ _UBYTE PG21MD:3; /* PG21MD */
+ _UBYTE :1; /* */
+ _UBYTE PG20MD:3; /* PG20MD */
+ } BIT; /* */
+ } PGCR5; /* */
+ union { /* PGCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PG19MD:3; /* PG19MD */
+ _UBYTE :1; /* */
+ _UBYTE PG18MD:3; /* PG18MD */
+ _UBYTE :2; /* */
+ _UBYTE PG17MD:2; /* PG17MD */
+ _UBYTE :2; /* */
+ _UBYTE PG16MD:2; /* PG16MD */
+ } BIT; /* */
+ } PGCR4; /* */
+ union { /* PGCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PG15MD:2; /* PG15MD */
+ _UBYTE :2; /* */
+ _UBYTE PG14MD:2; /* PG14MD */
+ _UBYTE :2; /* */
+ _UBYTE PG13MD:2; /* PG13MD */
+ _UBYTE :2; /* */
+ _UBYTE PG12MD:2; /* PG12MD */
+ } BIT; /* */
+ } PGCR3; /* */
+ union { /* PGCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PG11MD:3; /* PG11MD */
+ _UBYTE :1; /* */
+ _UBYTE PG10MD:3; /* PG10MD */
+ _UBYTE :1; /* */
+ _UBYTE PG9MD:3; /* PG9MD */
+ _UBYTE :1; /* */
+ _UBYTE PG8MD:3; /* PG8MD */
+ } BIT; /* */
+ } PGCR2; /* */
+ union { /* PGCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PG7MD:3; /* PG7MD */
+ _UBYTE :1; /* */
+ _UBYTE PG6MD:3; /* PG6MD */
+ _UBYTE :1; /* */
+ _UBYTE PG5MD:3; /* PG5MD */
+ _UBYTE :1; /* */
+ _UBYTE PG4MD:3; /* PG4MD */
+ } BIT; /* */
+ } PGCR1; /* */
+ union { /* PGCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PG3MD:3; /* PG3MD */
+ _UBYTE :1; /* */
+ _UBYTE PG2MD:3; /* PG2MD */
+ _UBYTE :1; /* */
+ _UBYTE PG1MD:3; /* PG1MD */
+ _UBYTE :1; /* */
+ _UBYTE PG0MD:3; /* PG0MD */
+ } BIT; /* */
+ } PGCR0; /* */
+ union { /* PGIOR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE PG27IOR:1; /* PG27IOR */
+ _UBYTE PG26IOR:1; /* PG26IOR */
+ _UBYTE PG25IOR:1; /* PG25IOR */
+ _UBYTE PG24IOR:1; /* PG24IOR */
+ _UBYTE PG23IOR:1; /* PG23IOR */
+ _UBYTE PG22IOR:1; /* PG22IOR */
+ _UBYTE PG21IOR:1; /* PG21IOR */
+ _UBYTE PG20IOR:1; /* PG20IOR */
+ _UBYTE PG19IOR:1; /* PG19IOR */
+ _UBYTE PG18IOR:1; /* PG18IOR */
+ _UBYTE PG17IOR:1; /* PG17IOR */
+ _UBYTE PG16IOR:1; /* PG16IOR */
+ } BIT; /* */
+ } PGIOR1; /* */
+ union { /* PGIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PG15IOR:1; /* PG15IOR */
+ _UBYTE PG14IOR:1; /* PG14IOR */
+ _UBYTE PG13IOR:1; /* PG13IOR */
+ _UBYTE PG12IOR:1; /* PG12IOR */
+ _UBYTE PG11IOR:1; /* PG11IOR */
+ _UBYTE PG10IOR:1; /* PG10IOR */
+ _UBYTE PG9IOR:1; /* PG9IOR */
+ _UBYTE PG8IOR:1; /* PG8IOR */
+ _UBYTE PG7IOR:1; /* PG7IOR */
+ _UBYTE PG6IOR:1; /* PG6IOR */
+ _UBYTE PG5IOR:1; /* PG5IOR */
+ _UBYTE PG4IOR:1; /* PG4IOR */
+ _UBYTE PG3IOR:1; /* PG3IOR */
+ _UBYTE PG2IOR:1; /* PG2IOR */
+ _UBYTE PG1IOR:1; /* PG1IOR */
+ _UBYTE PG0IOR:1; /* PG0IOR */
+ } BIT; /* */
+ } PGIOR0; /* */
+ union { /* PGDR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE PG27DR:1; /* PG27DR */
+ _UBYTE PG26DR:1; /* PG26DR */
+ _UBYTE PG25DR:1; /* PG25DR */
+ _UBYTE PG24DR:1; /* PG24DR */
+ _UBYTE PG23DR:1; /* PG23DR */
+ _UBYTE PG22DR:1; /* PG22DR */
+ _UBYTE PG21DR:1; /* PG21DR */
+ _UBYTE PG20DR:1; /* PG20DR */
+ _UBYTE PG19DR:1; /* PG19DR */
+ _UBYTE PG18DR:1; /* PG18DR */
+ _UBYTE PG17DR:1; /* PG17DR */
+ _UBYTE PG16DR:1; /* PG16DR */
+ } BIT; /* */
+ } PGDR1; /* */
+ union { /* PGDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PG15DR:1; /* PG15DR */
+ _UBYTE PG14DR:1; /* PG14DR */
+ _UBYTE PG13DR:1; /* PG13DR */
+ _UBYTE PG12DR:1; /* PG12DR */
+ _UBYTE PG11DR:1; /* PG11DR */
+ _UBYTE PG10DR:1; /* PG10DR */
+ _UBYTE PG9DR:1; /* PG9DR */
+ _UBYTE PG8DR:1; /* PG8DR */
+ _UBYTE PG7DR:1; /* PG7DR */
+ _UBYTE PG6DR:1; /* PG6DR */
+ _UBYTE PG5DR:1; /* PG5DR */
+ _UBYTE PG4DR:1; /* PG4DR */
+ _UBYTE PG3DR:1; /* PG3DR */
+ _UBYTE PG2DR:1; /* PG2DR */
+ _UBYTE PG1DR:1; /* PG1DR */
+ _UBYTE PG0DR:1; /* PG0DR */
+ } BIT; /* */
+ } PGDR0; /* */
+ union { /* PGPR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE PG27PR:1; /* PG27PR */
+ _UBYTE PG26PR:1; /* PG26PR */
+ _UBYTE PG25PR:1; /* PG25PR */
+ _UBYTE PG24PR:1; /* PG24PR */
+ _UBYTE PG23PR:1; /* PG23PR */
+ _UBYTE PG22PR:1; /* PG22PR */
+ _UBYTE PG21PR:1; /* PG21PR */
+ _UBYTE PG20PR:1; /* PG20PR */
+ _UBYTE PG19PR:1; /* PG19PR */
+ _UBYTE PG18PR:1; /* PG18PR */
+ _UBYTE PG17PR:1; /* PG17PR */
+ _UBYTE PG16PR:1; /* PG16PR */
+ } BIT; /* */
+ } PGPR1; /* */
+ union { /* PGPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PG15PR:1; /* PG15PR */
+ _UBYTE PG14PR:1; /* PG14PR */
+ _UBYTE PG13PR:1; /* PG13PR */
+ _UBYTE PG12PR:1; /* PG12PR */
+ _UBYTE PG11PR:1; /* PG11PR */
+ _UBYTE PG10PR:1; /* PG10PR */
+ _UBYTE PG9PR:1; /* PG9PR */
+ _UBYTE PG8PR:1; /* PG8PR */
+ _UBYTE PG7PR:1; /* PG7PR */
+ _UBYTE PG6PR:1; /* PG6PR */
+ _UBYTE PG5PR:1; /* PG5PR */
+ _UBYTE PG4PR:1; /* PG4PR */
+ _UBYTE PG3PR:1; /* PG3PR */
+ _UBYTE PG2PR:1; /* PG2PR */
+ _UBYTE PG1PR:1; /* PG1PR */
+ _UBYTE PG0PR:1; /* PG0PR */
+ } BIT; /* */
+ } PGPR0; /* */
+ _UBYTE wk18[16]; /* */
+ union { /* PHCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PH7MD:2; /* PH7MD */
+ _UBYTE :2; /* */
+ _UBYTE PH6MD:2; /* PH6MD */
+ _UBYTE :2; /* */
+ _UBYTE PH5MD:2; /* PH5MD */
+ _UBYTE :2; /* */
+ _UBYTE PH4MD:2; /* PH4MD */
+ } BIT; /* */
+ } PHCR1; /* */
+ union { /* PHCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE PH3MD:2; /* PH3MD */
+ _UBYTE :2; /* */
+ _UBYTE PH2MD:2; /* PH2MD */
+ _UBYTE :2; /* */
+ _UBYTE PH1MD:2; /* PH1MD */
+ _UBYTE :2; /* */
+ _UBYTE PH0MD:2; /* PH0MD */
+ } BIT; /* */
+ } PHCR0; /* */
+ _UBYTE wk19[10]; /* */
+ union { /* PHPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE PH7PR:1; /* PH7PR */
+ _UBYTE PH6PR:1; /* PH6PR */
+ _UBYTE PH5PR:1; /* PH5PR */
+ _UBYTE PH4PR:1; /* PH4PR */
+ _UBYTE PH3PR:1; /* PH3PR */
+ _UBYTE PH2PR:1; /* PH2PR */
+ _UBYTE PH1PR:1; /* PH1PR */
+ _UBYTE PH0PR:1; /* PH0PR */
+ } BIT; /* */
+ } PHPR0; /* */
+ _UBYTE wk20[4]; /* */
+ union { /* PJCR7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :3; /* */
+ _UBYTE PJ31MD:1; /* PJ31MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ30MD:3; /* PJ30MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ29MD:3; /* PJ29MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ28MD:3; /* PJ28MD */
+ } BIT; /* */
+ } PJCR7; /* */
+ union { /* PJCR6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ27MD:3; /* PJ27MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ26MD:3; /* PJ26MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ25MD:3; /* PJ25MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ24MD:3; /* PJ24MD */
+ } BIT; /* */
+ } PJCR6; /* */
+ union { /* PJCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ23MD:3; /* PJ23MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ22MD:3; /* PJ22MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ21MD:3; /* PJ21MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ20MD:3; /* PJ20MD */
+ } BIT; /* */
+ } PJCR5; /* */
+ union { /* PJCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ19MD:3; /* PJ19MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ18MD:3; /* PJ18MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ17MD:3; /* PJ17MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ16MD:3; /* PJ16MD */
+ } BIT; /* */
+ } PJCR4; /* */
+ union { /* PJCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ15MD:3; /* PJ15MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ14MD:3; /* PJ14MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ13MD:3; /* PJ13MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ12MD:3; /* PJ12MD */
+ } BIT; /* */
+ } PJCR3; /* */
+ union { /* PJCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ11MD:3; /* PJ11MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ10MD:3; /* PJ10MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ9MD:3; /* PJ9MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ8MD:3; /* PJ8MD */
+ } BIT; /* */
+ } PJCR2; /* */
+ union { /* PJCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ7MD:3; /* PJ7MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ6MD:3; /* PJ6MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ5MD:3; /* PJ5MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ4MD:3; /* PJ4MD */
+ } BIT; /* */
+ } PJCR1; /* */
+ union { /* PJCR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE PJ3MD:3; /* PJ3MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ2MD:3; /* PJ2MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ1MD:3; /* PJ1MD */
+ _UBYTE :1; /* */
+ _UBYTE PJ0MD:3; /* PJ0MD */
+ } BIT; /* */
+ } PJCR0; /* */
+ union { /* PJIOR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PJ31IOR:1; /* PJ31IOR */
+ _UBYTE PJ30IOR:1; /* PJ30IOR */
+ _UBYTE PJ29IOR:1; /* PJ29IOR */
+ _UBYTE PJ28IOR:1; /* PJ28IOR */
+ _UBYTE PJ27IOR:1; /* PJ27IOR */
+ _UBYTE PJ26IOR:1; /* PJ26IOR */
+ _UBYTE PJ25IOR:1; /* PJ25IOR */
+ _UBYTE PJ24IOR:1; /* PJ24IOR */
+ _UBYTE PJ23IOR:1; /* PJ23IOR */
+ _UBYTE PJ22IOR:1; /* PJ22IOR */
+ _UBYTE PJ21IOR:1; /* PJ21IOR */
+ _UBYTE PJ20IOR:1; /* PJ20IOR */
+ _UBYTE PJ19IOR:1; /* PJ19IOR */
+ _UBYTE PJ18IOR:1; /* PJ18IOR */
+ _UBYTE PJ17IOR:1; /* PJ17IOR */
+ _UBYTE PJ16IOR:1; /* PJ16IOR */
+ } BIT; /* */
+ } PJIOR1; /* */
+ union { /* PJIOR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PJ15IOR:1; /* PJ15IOR */
+ _UBYTE PJ14IOR:1; /* PJ14IOR */
+ _UBYTE PJ13IOR:1; /* PJ13IOR */
+ _UBYTE PJ12IOR:1; /* PJ12IOR */
+ _UBYTE PJ11IOR:1; /* PJ11IOR */
+ _UBYTE PJ10IOR:1; /* PJ10IOR */
+ _UBYTE PJ9IOR:1; /* PJ9IOR */
+ _UBYTE PJ8IOR:1; /* PJ8IOR */
+ _UBYTE PJ7IOR:1; /* PJ7IOR */
+ _UBYTE PJ6IOR:1; /* PJ6IOR */
+ _UBYTE PJ5IOR:1; /* PJ5IOR */
+ _UBYTE PJ4IOR:1; /* PJ4IOR */
+ _UBYTE PJ3IOR:1; /* PJ3IOR */
+ _UBYTE PJ2IOR:1; /* PJ2IOR */
+ _UBYTE PJ1IOR:1; /* PJ1IOR */
+ _UBYTE PJ0IOR:1; /* PJ0IOR */
+ } BIT; /* */
+ } PJIOR0; /* */
+ union { /* PJDR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PJ31DR:1; /* PJ31DR */
+ _UBYTE PJ30DR:1; /* PJ30DR */
+ _UBYTE PJ29DR:1; /* PJ29DR */
+ _UBYTE PJ28DR:1; /* PJ28DR */
+ _UBYTE PJ27DR:1; /* PJ27DR */
+ _UBYTE PJ26DR:1; /* PJ26DR */
+ _UBYTE PJ25DR:1; /* PJ25DR */
+ _UBYTE PJ24DR:1; /* PJ24DR */
+ _UBYTE PJ23DR:1; /* PJ23DR */
+ _UBYTE PJ22DR:1; /* PJ22DR */
+ _UBYTE PJ21DR:1; /* PJ21DR */
+ _UBYTE PJ20DR:1; /* PJ20DR */
+ _UBYTE PJ19DR:1; /* PJ19DR */
+ _UBYTE PJ18DR:1; /* PJ18DR */
+ _UBYTE PJ17DR:1; /* PJ17DR */
+ _UBYTE PJ16DR:1; /* PJ16DR */
+ } BIT; /* */
+ } PJDR1; /* */
+ union { /* PJDR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PJ15DR:1; /* PJ15DR */
+ _UBYTE PJ14DR:1; /* PJ14DR */
+ _UBYTE PJ13DR:1; /* PJ13DR */
+ _UBYTE PJ12DR:1; /* PJ12DR */
+ _UBYTE PJ11DR:1; /* PJ11DR */
+ _UBYTE PJ10DR:1; /* PJ10DR */
+ _UBYTE PJ9DR:1; /* PJ9DR */
+ _UBYTE PJ8DR:1; /* PJ8DR */
+ _UBYTE PJ7DR:1; /* PJ7DR */
+ _UBYTE PJ6DR:1; /* PJ6DR */
+ _UBYTE PJ5DR:1; /* PJ5DR */
+ _UBYTE PJ4DR:1; /* PJ4DR */
+ _UBYTE PJ3DR:1; /* PJ3DR */
+ _UBYTE PJ2DR:1; /* PJ2DR */
+ _UBYTE PJ1DR:1; /* PJ1DR */
+ _UBYTE PJ0DR:1; /* PJ0DR */
+ } BIT; /* */
+ } PJDR0; /* */
+ union { /* PJPR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PJ31PR:1; /* PJ31PR */
+ _UBYTE PJ30PR:1; /* PJ30PR */
+ _UBYTE PJ29PR:1; /* PJ29PR */
+ _UBYTE PJ28PR:1; /* PJ28PR */
+ _UBYTE PJ27PR:1; /* PJ27PR */
+ _UBYTE PJ26PR:1; /* PJ26PR */
+ _UBYTE PJ25PR:1; /* PJ25PR */
+ _UBYTE PJ24PR:1; /* PJ24PR */
+ _UBYTE PJ23PR:1; /* PJ23PR */
+ _UBYTE PJ22PR:1; /* PJ22PR */
+ _UBYTE PJ21PR:1; /* PJ21PR */
+ _UBYTE PJ20PR:1; /* PJ20PR */
+ _UBYTE PJ19PR:1; /* PJ19PR */
+ _UBYTE PJ18PR:1; /* PJ18PR */
+ _UBYTE PJ17PR:1; /* PJ17PR */
+ _UBYTE PJ16PR:1; /* PJ16PR */
+ } BIT; /* */
+ } PJPR1;
+ union { /* PJPR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE PJ15PR:1; /* PJ15PR */
+ _UBYTE PJ14PR:1; /* PJ14PR */
+ _UBYTE PJ13PR:1; /* PJ13PR */
+ _UBYTE PJ12PR:1; /* PJ12PR */
+ _UBYTE PJ11PR:1; /* PJ11PR */
+ _UBYTE PJ10PR:1; /* PJ10PR */
+ _UBYTE PJ9PR:1; /* PJ9PR */
+ _UBYTE PJ8PR:1; /* PJ8PR */
+ _UBYTE PJ7PR:1; /* PJ7PR */
+ _UBYTE PJ6PR:1; /* PJ6PR */
+ _UBYTE PJ5PR:1; /* PJ5PR */
+ _UBYTE PJ4PR:1; /* PJ4PR */
+ _UBYTE PJ3PR:1; /* PJ3PR */
+ _UBYTE PJ2PR:1; /* PJ2PR */
+ _UBYTE PJ1PR:1; /* PJ1PR */
+ _UBYTE PJ0PR:1; /* PJ0PR */
+ } BIT; /* */
+ } PJPR0; /* */
+ _UBYTE wk21[34]; /* */
+ union { /* SNCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Byte Access */
+ _UBYTE H; /* High */
+ _UBYTE L; /* Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UBYTE :8; /* */
+ _UBYTE :2; /* */
+ _UBYTE SSI5NCE:1; /* SSI5NCE */
+ _UBYTE SSI4NCE:1; /* SSI4NCE */
+ _UBYTE SSI3NCE:1; /* SSI3NCE */
+ _UBYTE SSI2NCE:1; /* SSI2NCE */
+ _UBYTE SSI1NCE:1; /* SSI1NCE */
+ _UBYTE SSI0NCE:1; /* SSI0NCE */
+ } BIT; /* */
+ }SNCR; /* */
+}; /* */
+ #endif
+struct st_hudi { /* struct HUDI */
+ union { /* SDIR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TI:8; /* TI */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } SDIR; /* */
+}; /* */
+struct st_pwm { /* struct PWM */
+ union { /* PWBTCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BTC2G:1; /* BTC2G */
+ _UBYTE BTC2E:1; /* BTC2E */
+ _UBYTE BTC2C:1; /* BTC2C */
+ _UBYTE BTC2A:1; /* BTC2A */
+ _UBYTE BTC1G:1; /* BTC1G */
+ _UBYTE BTC1E:1; /* BTC1E */
+ _UBYTE BTC1C:1; /* BTC1C */
+ _UBYTE BTC1A:1; /* BTC1A */
+ } BIT; /* */
+ } PWBTCR; /* */
+ _UBYTE wk0[217]; /* */
+ union { /* PWCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE IE:1; /* IE */
+ _UBYTE CMF:1; /* CMF */
+ _UBYTE CST:1; /* CST */
+ _UBYTE CKS:3; /* CKS */
+ } BIT; /* */
+ } PWCR1; /* */
+ _UBYTE wk1[3]; /* */
+ union { /* PWPR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OPS1H:1; /* OPS1H */
+ _UBYTE OPS1G:1; /* OPS1G */
+ _UBYTE OPS1F:1; /* OPS1F */
+ _UBYTE OPS1E:1; /* OPS1E */
+ _UBYTE OPS1D:1; /* OPS1D */
+ _UBYTE OPS1C:1; /* OPS1C */
+ _UBYTE OPS1B:1; /* OPS1B */
+ _UBYTE OPS1A:1; /* OPS1A */
+ } BIT; /* */
+ } PWPR1; /* */
+ _UBYTE wk2[1]; /* */
+ union { /* PWCYR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PWCY15:1; /* PWCY15 */
+ _UWORD PWCY14:1; /* PWCY14 */
+ _UWORD PWCY13:1; /* PWCY13 */
+ _UWORD PWCY12:1; /* PWCY12 */
+ _UWORD PWCY11:1; /* PWCY11 */
+ _UWORD PWCY10:1; /* PWCY10 */
+ _UWORD PWCY9:1; /* PWCY9 */
+ _UWORD PWCY8:1; /* PWCY8 */
+ _UWORD PWCY7:1; /* PWCY7 */
+ _UWORD PWCY6:1; /* PWCY6 */
+ _UWORD PWCY5:1; /* PWCY5 */
+ _UWORD PWCY4:1; /* PWCY4 */
+ _UWORD PWCY3:1; /* PWCY3 */
+ _UWORD PWCY2:1; /* PWCY2 */
+ _UWORD PWCY1:1; /* PWCY1 */
+ _UWORD PWCY0:1; /* PWCY0 */
+ } BIT; /* */
+ } PWCYR1; /* */
+ union { /* PWBFR1A */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR1A; /* */
+ union { /* PWBFR1C */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR1C; /* */
+ union { /* PWBFR1E */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR1E; /* */
+ union { /* PWBFR1G */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR1G; /* */
+ union { /* PWCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE IE:1; /* IE */
+ _UBYTE CMF:1; /* CMF */
+ _UBYTE CST:1; /* CST */
+ _UBYTE CKS:3; /* CKS */
+ } BIT; /* */
+ } PWCR2; /* */
+ _UBYTE wk3[3]; /* */
+ union { /* PWPR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OPS2H:1; /* OPS2H */
+ _UBYTE OPS2G:1; /* OPS2G */
+ _UBYTE OPS2F:1; /* OPS2F */
+ _UBYTE OPS2E:1; /* OPS2E */
+ _UBYTE OPS2D:1; /* OPS2D */
+ _UBYTE OPS2C:1; /* OPS2C */
+ _UBYTE OPS2B:1; /* OPS2B */
+ _UBYTE OPS2A:1; /* OPS2A */
+ } BIT; /* */
+ } PWPR2; /* */
+ _UBYTE wk4[1]; /* */
+ union { /* PWCYR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PWCY15:1; /* PWCY15 */
+ _UWORD PWCY14:1; /* PWCY14 */
+ _UWORD PWCY13:1; /* PWCY13 */
+ _UWORD PWCY12:1; /* PWCY12 */
+ _UWORD PWCY11:1; /* PWCY11 */
+ _UWORD PWCY10:1; /* PWCY10 */
+ _UWORD PWCY9:1; /* PWCY9 */
+ _UWORD PWCY8:1; /* PWCY8 */
+ _UWORD PWCY7:1; /* PWCY7 */
+ _UWORD PWCY6:1; /* PWCY6 */
+ _UWORD PWCY5:1; /* PWCY5 */
+ _UWORD PWCY4:1; /* PWCY4 */
+ _UWORD PWCY3:1; /* PWCY3 */
+ _UWORD PWCY2:1; /* PWCY2 */
+ _UWORD PWCY1:1; /* PWCY1 */
+ _UWORD PWCY0:1; /* PWCY0 */
+ } BIT; /* */
+ } PWCYR2; /* */
+ union { /* PWBFR2A */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR2A; /* */
+ union { /* PWBFR2C */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR2C; /* */
+ union { /* PWBFR2E */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR2E; /* */
+ union { /* PWBFR2G */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD OTS:1; /* OTS */
+ _UWORD :2; /* */
+ _UWORD DT9:1; /* DT9 */
+ _UWORD DT8:1; /* DT8 */
+ _UWORD DT7:1; /* DT7 */
+ _UWORD DT6:1; /* DT6 */
+ _UWORD DT5:1; /* DT5 */
+ _UWORD DT4:1; /* DT4 */
+ _UWORD DT3:1; /* DT3 */
+ _UWORD DT2:1; /* DT2 */
+ _UWORD DT1:1; /* DT1 */
+ _UWORD DT0:1; /* DT0 */
+ } BIT; /* */
+ } PWBFR2G; /* */
+}; /* */
+struct st_rqspi { /* struct RQSPI */
+ union { /* SPCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SPRIE:1; /* SPRIE */
+ _UBYTE SPE:1; /* SPE */
+ _UBYTE SPTIE:1; /* SPTIE */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } SPCR; /* */
+ union { /* SSLP */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE SSLP:1; /* SSLP */
+ } BIT; /* */
+ } SSLP; /* */
+ union { /* SPPCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE MOIFE:1; /* MOIFE */
+ _UBYTE MOIFV:1; /* MOIFV */
+ _UBYTE :1; /* */
+ _UBYTE IO3FV:1; /* IO3FV */
+ _UBYTE IO2FV:1; /* IO2FV */
+ _UBYTE SPLP:1; /* SPLP */
+ } BIT; /* */
+ } SPPCR; /* */
+ union { /* SPSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SPRFF:1; /* SPRFF */
+ _UBYTE TEND:1; /* TEND */
+ _UBYTE SPTEF:1; /* SPTEF */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } SPSR; /* */
+ union { /* SPDR */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD; /* Word Access */
+ _UBYTE BYTE; /* Byte Access */
+ } SPDR; /* */
+ union { /* SPSCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE SPSC:2; /* SPSC */
+ } BIT; /* */
+ } SPSCR; /* */
+ union { /* SPSSR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE SPSS:2; /* SPSS */
+ } BIT; /* */
+ } SPSSR; /* */
+ union { /* SPBR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SPBR:8; /* SPBR */
+ } BIT; /* */
+ } SPBR; /* */
+ union { /* SPDCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TXDMY:1; /* TXDMY */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } SPDCR; /* */
+ union { /* SPCKD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE SCKDL:3; /* SCKDL */
+ } BIT; /* */
+ } SPCKD; /* */
+ union { /* SSLND */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE SLNDL:3; /* SLNDL */
+ } BIT; /* */
+ } SSLND; /* */
+ union { /* SPND */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :5; /* */
+ _UBYTE SPNDL:3; /* SPNDL */
+ } BIT; /* */
+ } SPND; /* */
+ _UBYTE wk0[1]; /* */
+ union { /* SPCMD0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD SPIMOD:2; /* SPIMOD */
+ _UWORD SPRW:1; /* SPRW */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD0; /* */
+ union { /* SPCMD1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD SPIMOD:2; /* SPIMOD */
+ _UWORD SPRW:1; /* SPRW */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD1 ; /* */
+ union { /* SPCMD2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD SPIMOD:2; /* SPIMOD */
+ _UWORD SPRW:1; /* SPRW */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD2 ; /* */
+ union { /* SPCMD3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SCKDEN:1; /* SCKDEN */
+ _UWORD SLNDEN:1; /* SLNDEN */
+ _UWORD SPNDEN:1; /* SPNDEN */
+ _UWORD LSBF:1; /* LSBF */
+ _UWORD SPB:4; /* SPB */
+ _UWORD SSLKP:1; /* SSLKP */
+ _UWORD SPIMOD:2; /* SPIMOD */
+ _UWORD SPRW:1; /* SPRW */
+ _UWORD BRDV:2; /* BRDV */
+ _UWORD CPOL:1; /* CPOL */
+ _UWORD CPHA:1; /* CPHA */
+ } BIT; /* */
+ } SPCMD3 ; /* */
+ union { /* SPBFCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TXRST:1; /* TXRST */
+ _UBYTE RXRST:1; /* RXRST */
+ _UBYTE TXTRG:2; /* TXTRG */
+ _UBYTE :1; /* */
+ _UBYTE RXTRG:3; /* RXTRG */
+ } BIT; /* */
+ } SPBFCR; /* */
+ _UBYTE wk1[1]; /* */
+ union { /* SPBDCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD TXBC:6 ; /* TXBC */
+ _UWORD :2; /* */
+ _UWORD RXBC:6; /* RXBC */
+ } BIT; /* */
+ } SPBDCR; /* */
+ union { /* SPBMUL0 */
+ _UDWORD LONG; /* Long Access */
+ } SPBMUL0; /* */
+ union { /* SPBMUL1 */
+ _UDWORD LONG; /* Long Access */
+ } SPBMUL1; /* */
+ union { /* SPBMUL2 */
+ _UDWORD LONG; /* Long Access */
+ } SPBMUL2; /* */
+ union { /* SPBMUL3 */
+ _UDWORD LONG; /* Long Access */
+ } SPBMUL3; /* */
+}; /* */
+struct st_imrls { /* struct IMRLS */
+ union { /* CR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD SWRST:1; /* SWRST */
+ _UDWORD :9; /* */
+ _UDWORD RESUME:1; /* RESUME */
+ _UDWORD STOP:1; /* STOP */
+ _UDWORD :1; /* */
+ _UDWORD SFE:1; /* SFE */
+ _UDWORD ARS:1; /* ARS */
+ _UDWORD RS:1; /* RS */
+ } BIT; /* */
+ } CR; /* */
+ union { /* SR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD DSA:1; /* DSA */
+ _UDWORD :1; /* */
+ _UDWORD STP:1; /* STP */
+ _UDWORD :1; /* */
+ _UDWORD INT:1; /* INT */
+ _UDWORD IER:1; /* IER */
+ _UDWORD TRA:1; /* TRA */
+ } BIT; /* */
+ } SR; /* */
+ union { /* SRCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD STPCLR:1; /* STPCLR */
+ _UDWORD :1; /* */
+ _UDWORD INTCLR:1; /* INTCLR */
+ _UDWORD IERCLR:1; /* IERCLR */
+ _UDWORD TRACLR:1; /* TRACLR */
+ } BIT; /* */
+ } SRCR; /* */
+ union { /* ICR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD STPENB:1; /* STPENB */
+ _UDWORD :1; /* */
+ _UDWORD INTENB:1; /* INTENB */
+ _UDWORD IERENB:1; /* IERENB */
+ _UDWORD TRAENB:1; /* TRAENB */
+ } BIT; /* */
+ } ICR; /* */
+ union { /* IMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :27; /* */
+ _UDWORD STM:1; /* STM */
+ _UDWORD :1; /* */
+ _UDWORD INM:1; /* INM */
+ _UDWORD IEM:1; /* IEM */
+ _UDWORD TRAM:1; /* TRAM */
+ } BIT; /* */
+ } IMR; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* DLPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DLP:32; /* DLP */
+ } BIT; /* */
+ } DLPR; /* */
+ _UBYTE wk1[12]; /* */
+ union { /* DLSAR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DLSA:32; /* DLSA */
+ } BIT; /* */
+ } DLSAR; /* */
+ union { /* DSAR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DSAR:32; /* DSAR */
+ } BIT; /* */
+ } DSAR; /* */
+ _UBYTE wk2[4]; /* */
+ union { /* DSTR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :19; /* */
+ _UDWORD DSTR:13; /* DSTR */
+ } BIT; /* */
+ } DSTR; /* */
+ _UBYTE wk3[8]; /* */
+ union { /* DSAR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DSAR2:32; /* DSAR2 */
+ } BIT; /* */
+ } DSAR2; /* */
+ union { /* DLSAR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DLSA2:32; /* DLSA2 */
+ } BIT; /* */
+ } DLSAR2; /* */
+ _UBYTE wk4[16]; /* */
+ union { /* TRIMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD TCM:1; /* TCM */
+ _UDWORD DUDVM:1; /* DUDVM */
+ _UDWORD DXDYM:1; /* DXDYM */
+ _UDWORD AUTOSG:1; /* AUTOSG */
+ _UDWORD AUTODG:1; /* AUTODG */
+ _UDWORD BFE:1; /* BFE */
+ _UDWORD TME:1; /* TME */
+ } BIT; /* */
+ } TRIMR; /* */
+ union { /* TRIMSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD TCMS:1; /* TCMS */
+ _UDWORD DUDVMS:1; /* DUDVMS */
+ _UDWORD DXDYMS:1; /* DXDYMS */
+ _UDWORD AUTOSGS:1; /* AUTOSGS */
+ _UDWORD AUTODGS:1; /* AUTODGS */
+ _UDWORD BFES:1; /* BFES */
+ _UDWORD TMES:1; /* TMES */
+ } BIT; /* */
+ } TRIMSR; /* */
+ union { /* TRIMCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD TCMC:1; /* TCMC */
+ _UDWORD DUDVMC:1; /* DUDVMC */
+ _UDWORD DXDYMC:1; /* DXDYMC */
+ _UDWORD AUTOSGC:1; /* AUTOSGC */
+ _UDWORD AUTODGC:1; /* AUTODGC */
+ _UDWORD BFEC:1; /* BFEC */
+ _UDWORD TMEC:1; /* TMEC */
+ } BIT; /* */
+ } TRIMCR; /* */
+ union { /* TRICR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD TCV:8; /* TCV */
+ _UDWORD TCU:8; /* TCU */
+ _UDWORD TCY:8; /* TCY */
+ } BIT; /* */
+ } TRICR; /* */
+ union { /* UVDPOR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD DDP:1; /* DDP */
+ _UDWORD :5; /* */
+ _UDWORD UVDPO:3; /* UVDPO */
+ } BIT; /* */
+ } UVDPOR; /* */
+ union { /* SUSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :6; /* */
+ _UDWORD SUW:10; /* SUW */
+ _UDWORD :6; /* */
+ _UDWORD SVW:10; /* SVW */
+ } BIT; /* */
+ } SUSR; /* */
+ union { /* SVSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD SVSR:10; /* SVSR */
+ } BIT; /* */
+ } SVSR; /* */
+ _UBYTE wk5[4]; /* */
+ union { /* XMINR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :20; /* */
+ _UDWORD XMIN:12; /* XMIN */
+ } BIT; /* */
+ } XMINR; /* */
+ union { /* YMINR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :20; /* */
+ _UDWORD YMIN:12; /* YMIN */
+ } BIT; /* */
+ } YMINR; /* */
+ union { /* XMAXR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :20; /* */
+ _UDWORD XMAX:12; /* XMAX */
+ } BIT; /* */
+ } XMAXR; /* */
+ union { /* YMAXR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :20; /* */
+ _UDWORD YMAX:12; /* YMAX */
+ } BIT; /* */
+ } YMAXR; /* */
+ union { /* AMXSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD AMXS:10; /* AMXS */
+ } BIT; /* */
+ } AMXSR; /* */
+ union { /* AMYSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD AMYS:10; /* AMYS */
+ } BIT; /* */
+ } AMYSR; /* */
+ union { /* AMXOR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD AMXO:10; /* AMXO */
+ } BIT; /* */
+ } AMXOR; /* */
+ union { /* AMYOR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD AMYO:10; /* AMYO */
+ } BIT; /* */
+ } AMYOR; /* */
+ union { /* MACR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD QWSWPI:1; /* QWSWPI */
+ _UDWORD QWSWPC:1; /* QWSWPC */
+ _UDWORD :17; /* */
+ _UDWORD EMAM:1; /* EMAM */
+ _UDWORD :2; /* */
+ _UDWORD LWSWAP:1; /* LWSWAP */
+ _UDWORD :9; /* */
+ } BIT; /* */
+ } MACR1; /* */
+ _UBYTE wk6[2396]; /* */
+ union { /* LSPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD LSPR:10; /* LSPR */
+ } BIT; /* */
+ } LSPR; /* */
+ union { /* LEPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :22; /* */
+ _UDWORD LEPR:10; /* LEPR */
+ } BIT; /* */
+ } LEPR; /* */
+ union { /* LMSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :29; /* */
+ _UDWORD LMSR:3; /* LMSR */
+ } BIT; /* */
+ } LMSR; /* */
+}; /* */
+struct st_sdg0 { /* struct SDG0 */
+ union { /* SGCR1_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGST:1; /* SGST */
+ _UBYTE STPM:1; /* STPM */
+ _UBYTE :1; /* */
+ _UBYTE SGCK:2; /* SGCK */
+ _UBYTE DPF:3; /* DPF */
+ } BIT; /* */
+ } SGCR1_0; /* */
+ union { /* SGCSR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGIE:1; /* SGIE */
+ _UBYTE SGDEF:1; /* SGDEF */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCSR_0; /* */
+ union { /* SGCR2_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGEND:1; /* SGEND */
+ _UBYTE TCHG:1; /* TCHG */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCR2_0; /* */
+ union { /* SGLR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE LD:8; /* LD */
+ } BIT; /* */
+ } SGLR_0; /* */
+ union { /* SGTFR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE TONE:7; /* TONE */
+ } BIT; /* */
+ } SGTFR_0; /* */
+ union { /* SGSFR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SFS:8; /* SFS */
+ } BIT; /* */
+ } SGSFR_0; /* */
+}; /* */
+struct st_sdg1 { /* struct SDG1 */
+ union { /* SGCR1_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGST:1; /* SGST */
+ _UBYTE STPM:1; /* STPM */
+ _UBYTE :1; /* */
+ _UBYTE SGCK:2; /* SGCK */
+ _UBYTE DPF:3; /* DPF */
+ } BIT; /* */
+ } SGCR1_1; /* */
+ union { /* SGCSR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGIE:1; /* SGIE */
+ _UBYTE SGDEF:1; /* SGDEF */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCSR_1; /* */
+ union { /* SGCR2_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGEND:1; /* SGEND */
+ _UBYTE TCHG:1; /* TCHG */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCR2_1; /* */
+ union { /* SGLR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE LD:8; /* LD */
+ } BIT; /* */
+ } SGLR_1; /* */
+ union { /* SGTFR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE TONE:7; /* TONE */
+ } BIT; /* */
+ } SGTFR_1; /* */
+ union { /* SGSFR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SFS:8; /* SFS */
+ } BIT; /* */
+ } SGSFR_1; /* */
+}; /* */
+struct st_sdg2 { /* struct SDG2 */
+ union { /* SGCR1_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGST:1; /* SGST */
+ _UBYTE STPM:1; /* STPM */
+ _UBYTE :1; /* */
+ _UBYTE SGCK:2; /* SGCK */
+ _UBYTE DPF:3; /* DPF */
+ } BIT; /* */
+ } SGCR1_2; /* */
+ union { /* SGCSR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGIE:1; /* SGIE */
+ _UBYTE SGDEF:1; /* SGDEF */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCSR_2; /* */
+ union { /* SGCR2_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGEND:1; /* SGEND */
+ _UBYTE TCHG:1; /* TCHG */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCR2_2; /* */
+ union { /* SGLR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE LD:8; /* LD */
+ } BIT; /* */
+ } SGLR_2; /* */
+ union { /* SGTFR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE TONE:7; /* TONE */
+ } BIT; /* */
+ } SGTFR_2; /* */
+ union { /* SGSFR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SFS:8; /* SFS */
+ } BIT; /* */
+ } SGSFR_2; /* */
+}; /* */
+struct st_sdg3 { /* struct SDG3 */
+ union { /* SGCR1_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGST:1; /* SGST */
+ _UBYTE STPM:1; /* STPM */
+ _UBYTE :1; /* */
+ _UBYTE SGCK:2; /* SGCK */
+ _UBYTE DPF:3; /* DPF */
+ } BIT; /* */
+ } SGCR1_3; /* */
+ union { /* SGCSR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGIE:1; /* SGIE */
+ _UBYTE SGDEF:1; /* SGDEF */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCSR_3; /* */
+ union { /* SGCR2_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SGEND:1; /* SGEND */
+ _UBYTE TCHG:1; /* TCHG */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SGCR2_3; /* */
+ union { /* SGLR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE LD:8; /* LD */
+ } BIT; /* */
+ } SGLR_3; /* */
+ union { /* SGTFR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE TONE:7; /* TONE */
+ } BIT; /* */
+ } SGTFR_3; /* */
+ union { /* SGSFR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SFS:8; /* SFS */
+ } BIT; /* */
+ } SGSFR_3; /* */
+}; /* */
+struct st_mmc { /* struct MMC */
+ union { /* CE_CMD_SET */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD BOOT:1; /* BOOT */
+ _UWORD CMD:6; /* CMD */
+ _UWORD RTYP:2; /* RTYP */
+ _UWORD RBSY:1; /* RBSY */
+ _UWORD CCSEN:1; /* CCSEN */
+ _UWORD WDAT:1; /* WDAT */
+ _UWORD DWEN:1; /* DWEN */
+ _UWORD CMLTE:1; /* CMLTE */
+ _UWORD CMD12EN:1; /* CMD12EN */
+ _UWORD RIDXC:2; /* RIDXC */
+ _UWORD RCRC7C:2; /* RCRC7C */
+ _UWORD :1; /* */
+ _UWORD CRC16C:1; /* CRC16C */
+ _UWORD BOOTACK:1; /* BOOTACK */
+ _UWORD CRCSTE:1; /* CRCSTE */
+ _UWORD TBIT:1; /* TBIT */
+ _UWORD OPDM:1; /* OPDM */
+ _UWORD CCSH:1; /* CCSH */
+ _UWORD :3; /* */
+ _UWORD DATW:2; /* DATW */
+ } BIT; /* */
+ } CE_CMD_SET; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* CE_ARG */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD ARG:32; /* ARG */
+ } BIT; /* */
+ } CE_ARG; /* */
+ union { /* CE_ARG_CMD12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD C12ARG:32; /* C12ARG */
+ } BIT; /* */
+ } CE_ARG_CMD12; /* */
+ union { /* CE_CMD_CTRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :30; /* */
+ _UDWORD CCSD:1; /* CCSD */
+ _UDWORD BREAK:1; /* BREAK */
+ } BIT; /* */
+ } CE_CMD_CTRL; /* */
+ union { /* CE_BLOCK_SET */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD BLKCNT:16; /* BLKCNT */
+ _UWORD BLKSIZ:16; /* BLKSIZ */
+ } BIT; /* */
+ } CE_BLOCK_SET; /* */
+ union { /* CE_CLK_CTRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :7; /* */
+ _UDWORD CLKEN:1; /* CLKEN */
+ _UDWORD :4; /* */
+ _UDWORD CLKDIV:4; /* CLKDIV */
+ _UDWORD :2; /* */
+ _UDWORD SRSPTO:2; /* SRSPTO */
+ _UDWORD SRBSYTO:4; /* SRBSYTO */
+ _UDWORD SRWDTO:4; /* SRWDTO */
+ _UDWORD SCCSTO:4; /* SCCSTO */
+ } BIT; /* */
+ } CE_CLK_CTRL; /* */
+ union { /* CE_BUF_ACC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD DMAWEN:1; /* DMAWEN */
+ _UWORD DMAREN:1; /* DMAREN */
+ _UWORD :6; /* */
+ _UWORD BUSW:1; /* BUSW */
+ _UWORD ATYP:1; /* ATYP */
+ _UWORD :16; /* */
+ } BIT; /* */
+ } CE_BUF_ACC; /* */
+ union { /* CE_RESP3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD RSP:32; /* RSP */
+ } BIT; /* */
+ } CE_RESP3; /* */
+ union { /* CE_RESP2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD RSP:32; /* RSP */
+ } BIT; /* */
+ } CE_RESP2; /* */
+ union { /* CE_RESP1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD RSP:32; /* RSP */
+ } BIT; /* */
+ } CE_RESP1; /* */
+ union { /* CE_RESP0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD RSP:32; /* RSP */
+ } BIT; /* */
+ } CE_RESP0; /* */
+ union { /* CE_RESP_CMD12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD RSP12:32; /* RSP12 */
+ } BIT; /* */
+ } CE_RESP_CMD12; /* */
+ union { /* CE_DATA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD DATA:32; /* DATA */
+ } BIT; /* */
+ } CE_DATA; /* */
+ _UBYTE wk1[8]; /* */
+ union { /* CE_INT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD CCSDE:1; /* CCSDE */
+ _UWORD :2; /* */
+ _UWORD CMD12DRE:1; /* CMD12DRE */
+ _UWORD CMD12RBE:1; /* CMD12RBE */
+ _UWORD CMD12CRE:1; /* CMD12CRE */
+ _UWORD DTRANE:1; /* DTRANE */
+ _UWORD BUFRE:1; /* BUFRE */
+ _UWORD BUFWEN:1; /* BUFWEN */
+ _UWORD BUFREN:1; /* BUFREN */
+ _UWORD CCSRCV:1; /* CCSRCV */
+ _UWORD :1; /* */
+ _UWORD RBSYE:1; /* RBSYE */
+ _UWORD CRSPE:1; /* CRSPE */
+ _UWORD CMDVIO:1; /* CMDVIO */
+ _UWORD BUFVIO:1; /* BUFVIO */
+ _UWORD :2; /* */
+ _UWORD WDATERR:1; /* WDATERR */
+ _UWORD RDATERR:1; /* RDATERR */
+ _UWORD RIDXERR:1; /* RIDXERR */
+ _UWORD RSPERR:1; /* RSPERR */
+ _UWORD :2; /* */
+ _UWORD CCSTO:1; /* CCSTO */
+ _UWORD CRCSTO:1; /* CRCSTO */
+ _UWORD WDATTO:1; /* WDATTO */
+ _UWORD RDATTO:1; /* RDATTO */
+ _UWORD RBSYTO:1; /* RBSYTO */
+ _UWORD RSPTO:1; /* RSPTO */
+ } BIT; /* */
+ } CE_INT; /* */
+ union { /* CE_INT_EN */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD MCCSDE:1; /* MCCSDE */
+ _UWORD :2; /* */
+ _UWORD MCMD12DRE:1; /* MCMD12DRE */
+ _UWORD MCMD12RBE:1; /* MCMD12RBE */
+ _UWORD MCMD12CRE:1; /* MCMD12CRE */
+ _UWORD MDTRANE:1; /* MDTRANE */
+ _UWORD MBUFRE:1; /* MBUFRE */
+ _UWORD MBUFWEN:1; /* MBUFWEN */
+ _UWORD MBUFREN:1; /* MBUFREN */
+ _UWORD MCCSRCV:1; /* MCCSRCV */
+ _UWORD :1; /* */
+ _UWORD MRBSYE:1; /* MRBSYE */
+ _UWORD MCRSPE:1; /* MCRSPE */
+ _UWORD MCMDVIO:1; /* MCMDVIO */
+ _UWORD MBUFVIO:1; /* MBUFVIO */
+ _UWORD :2; /* */
+ _UWORD MWDATERR:1; /* MWDATERR */
+ _UWORD MRDATERR:1; /* MRDATERR */
+ _UWORD MRIDXERR:1; /* MRIDXERR */
+ _UWORD MRSPERR:1; /* MRSPERR */
+ _UWORD :2; /* */
+ _UWORD MCCSTO:1; /* MCCSTO */
+ _UWORD MCRCSTO:1; /* MCRCSTO */
+ _UWORD MWDATTO:1; /* MWDATTO */
+ _UWORD MRDATTO:1; /* MRDATTO */
+ _UWORD MRBSYTO:1; /* MRBSYTO */
+ _UWORD MRSPTO:1; /* MRSPTO */
+ } BIT; /* */
+ } CE_INT_EN; /* */
+ union { /* CE_HOST_STS1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD CMDSEQ:1; /* CMDSEQ */
+ _UWORD CMDSIG:1; /* CMDSIG */
+ _UWORD RSPIDX:6; /* RSPIDX */
+ _UWORD DATSIG:8; /* DATSIG */
+ _UWORD RCVBLK:16; /* RCVBLK */
+ } BIT; /* */
+ } CE_HOST_STS1; /* */
+ union { /* CE_HOST_STS2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD CRCSTE:1; /* CRCSTE */
+ _UWORD CRC16E:1; /* CRC16E */
+ _UWORD AC12CRCE:1; /* AC12CRCE */
+ _UWORD RSPCRC7E:1; /* RSPCRC7E */
+ _UWORD CRCSTEBE:1; /* CRCSTEBE */
+ _UWORD RDATEBE:1; /* RDATEBE */
+ _UWORD AC12REBE:1; /* AC12REBE */
+ _UWORD RSPEBE:1; /* RSPEBE */
+ _UWORD AC12IDXE:1; /* AC12IDXE */
+ _UWORD RSPIDXE:1; /* RSPIDXE */
+ _UWORD BTACKPATE:1; /* BTACKPATE */
+ _UWORD BTACKEBE:1; /* BTACKEBE */
+ _UWORD :1; /* */
+ _UWORD CRCST:3; /* CRCST */
+ _UWORD STCCSTO:1; /* STCCSTO */
+ _UWORD STRDATTO:1; /* STRDATTO */
+ _UWORD DATBSYTO:1; /* DATBSYTO */
+ _UWORD CRCSTTO:1; /* CRCSTTO */
+ _UWORD AC12BSYTO:1; /* AC12BSYTO */
+ _UWORD RSPBSYTO:1; /* RSPBSYTO */
+ _UWORD AC12RSPTO:1; /* AC12RSPTO */
+ _UWORD STRSPTO:1; /* STRSPTO */
+ _UWORD BTACKTO:1; /* BTACKTO */
+ _UWORD FSTBTDATTO:1; /* FSTBTDATTO */
+ _UWORD BTDATTO:1; /* BTDATTO */
+ _UWORD :5; /* */
+ } BIT; /* */
+ } CE_HOST_STS2; /* */
+ _UBYTE wk2_0[12]; /* */
+ union { /* CE_DMA_MODE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD DMASEL:1; /* DMASEL */
+ } BIT; /* */
+ } CE_DMA_MODE; /* */
+ _UBYTE wk2_1[16]; /* */
+ union { /* CE_DETECT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :17; /* */
+ _UDWORD CDSIG:1; /* CDSIG */
+ _UDWORD CDRISE:1; /* CDRISE */
+ _UDWORD CDFALL:1; /* CDFALL */
+ _UDWORD :6; /* */
+ _UDWORD MCDRISE:1; /* MCDRISE */
+ _UDWORD MCDFALL:1; /* MCDFALL */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } CE_DETECT; /* */
+ union { /* CE_ADD_MODE */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD CLKMAIN:1; /* CLKMAIN */
+ _UDWORD :19; /* */
+ } BIT; /* */
+ } CE_ADD_MODE; /* */
+ _UBYTE wk3[4]; /* */
+ union { /* CE_VERSION */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Bit Access */
+ _UWORD SWRST:1; /* SWRST */
+ _UWORD :15; /* */
+ _UWORD VERSION:16; /* VERSION */
+ } BIT; /* */
+ } CE_VERSION; /* */
+}; /* */
+struct st_dvdec { /* struct DVDEC */
+ union { /* ADCCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD AGCMODE:1; /* AGCMODE */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } ADCCR1; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* TGCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD SRCLEFT:9; /* SRCLEFT */
+ } BIT; /* */
+ } TGCR1; /* */
+ union { /* TGCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SRCTOP:6; /* SRCTOP */
+ _UWORD SRCHEIGHT:10; /* SRCHEIGHT */
+ } BIT; /* */
+ } TGCR2; /* */
+ union { /* TGCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD SRCWIDTH:11; /* SRCWIDTH */
+ } BIT; /* */
+ } TGCR3; /* */
+ _UBYTE wk1[6]; /* */
+ union { /* SYNSCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD LPFVSYNC:3; /* LPFVSYNC */
+ _UWORD LPFHSYNC:3; /* LPFHSYNC */
+ _UWORD :2; /* */
+ _UWORD VELOCITYSHIFT_H:4; /* VELOCITYSHIFT_H */
+ _UWORD SLICERMODE_H:2; /* SLICERMODE_H */
+ _UWORD SLICERMODE_V:2; /* SLICERMODE_V */
+ } BIT; /* */
+ } SYNSCR1; /* */
+ union { /* SYNSCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD SYNCMAXDUTY_H:6; /* SYNCMAXDUTY_H */
+ _UWORD SYNCMINDUTY_H:6; /* SYNCMINDUTY_H */
+ } BIT; /* */
+ } SYNSCR2; /* */
+ union { /* SYNSCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD SSCLIPSEL:4; /* SSCLIPSEL */
+ _UWORD CSYNCSLICE_H:10; /* CSYNCSLICE_H */
+ } BIT; /* */
+ } SYNSCR3; /* */
+ union { /* SYNSCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD SYNCMAXDUTY_V:6; /* SYNCMAXDUTY_V */
+ _UWORD SYNCMINDUTY_V:6; /* SYNCMINDUTY_V */
+ } BIT; /* */
+ } SYNSCR4; /* */
+ union { /* SYNSCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD VSYNCDELAY:1; /* VSYNCDELAY */
+ _UWORD VSYNCSLICE:5; /* VSYNCSLICE */
+ _UWORD CSYNCSLICE_V:10; /* CSYNCSLICE_V */
+ } BIT; /* */
+ } SYNSCR5; /* */
+ union { /* HAFCCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD HAFCGAIN:4; /* HAFCGAIN */
+ _UWORD :1; /* */
+ _UWORD HAFCFREERUN:1; /* HAFCFREERUN */
+ _UWORD HAFCTYP:10; /* HAFCTYP */
+ } BIT; /* */
+ } HAFCCR1; /* */
+ union { /* HAFCCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD HAFCSTART:4; /* HAFCSTART */
+ _UWORD NOX2HOSC:1; /* NOX2HOSC */
+ _UWORD DOX2HOSC:1; /* DOX2HOSC */
+ _UWORD HAFCMAX:10; /* HAFCMAX */
+ } BIT; /* */
+ } HAFCCR2; /* */
+ union { /* HAFCCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD HAFCEND:4; /* HAFCEND */
+ _UWORD HAFCMODE:2; /* HAFCMODE */
+ _UWORD HAFCMIN:10; /* HAFCMIN */
+ } BIT; /* */
+ } HAFCCR3; /* */
+ union { /* VCDWCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD VCDFREERUN:1; /* VCDFREERUN */
+ _UWORD NOVCD50:1; /* NOVCD50 */
+ _UWORD NOVCD60:1; /* NOVCD60 */
+ _UWORD VCDDEFAULT:2; /* VCDDEFAULT */
+ _UWORD VCDWINDOW:6; /* VCDWINDOW */
+ _UWORD VCDOFFSET:5; /* VCDOFFSET */
+ } BIT; /* */
+ } VCDWCR1; /* */
+ _UBYTE wk2[4]; /* */
+ union { /* DCPCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DCPMODE_Y:1; /* DCPMODE_Y */
+ _UWORD :3; /* */
+ _UWORD DCPCHECK:1; /* DCPCHECK */
+ _UWORD :1; /* */
+ _UWORD BLANKLEVEL_Y:10; /* BLANKLEVEL_Y */
+ } BIT; /* */
+ } DCPCR1; /* */
+ union { /* DCPCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DCPMODE_C:1; /* DCPMODE_C */
+ _UWORD :3; /* */
+ _UWORD BLANKLEVEL_CB:6; /* BLANKLEVEL_CB */
+ _UWORD BLANKLEVEL_CR:6; /* BLANKLEVEL_CR */
+ } BIT; /* */
+ } DCPCR2; /* */
+ union { /* DCPCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD DCPRESPONSE:3; /* DCPRESPONSE */
+ _UWORD :12; /* */
+ } BIT; /* */
+ } DCPCR3; /* */
+ union { /* DCPCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DCPSTART:6; /* DCPSTART */
+ _UWORD :10; /* */
+ } BIT; /* */
+ } DCPCR4; /* */
+ union { /* DCPCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DCPEND:6; /* DCPEND */
+ _UWORD :10; /* */
+ } BIT; /* */
+ } DCPCR5; /* */
+ union { /* DCPCR6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD DCPWIDTH:7; /* DCPWIDTH */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } DCPCR6; /* */
+ union { /* DCPCR7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DCPPOS_Y:8; /* DCPPOS_Y */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } DCPCR7; /* */
+ union { /* DCPCR8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DCPPOS_C:8; /* DCPPOS_C */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } DCPCR8; /* */
+ union { /* NSDCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD ACFINPUT:2; /* ACFINPUT */
+ _UWORD :3; /* */
+ _UWORD ACFLAGTIME:5; /* ACFLAGTIME */
+ _UWORD :2; /* */
+ _UWORD ACFFILTER:2; /* ACFFILTER */
+ } BIT; /* */
+ } NSDCR; /* */
+ union { /* BTLCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD LOCKRANGE:2; /* LOCKRANGE */
+ _UWORD LOOPGAIN:2; /* LOOPGAIN */
+ _UWORD LOCKLIMIT:2; /* LOCKLIMIT */
+ _UWORD BCOFREERUN:1; /* BCOFREERUN */
+ _UWORD :1; /* */
+ _UWORD DEFAULTSYS:2; /* DEFAULTSYS */
+ _UWORD NONTSC358:1; /* NONTSC358 */
+ _UWORD NONTSC443:1; /* NONTSC443 */
+ _UWORD NOPALM:1; /* NOPALM */
+ _UWORD NOPALN:1; /* NOPALN */
+ _UWORD NOPAL443:1; /* NOPAL443 */
+ _UWORD NOSECAM:1; /* NOSECAM */
+ } BIT; /* */
+ } BTLCR; /* */
+ union { /* BTGPCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BGPCHECK:1; /* BGPCHECK */
+ _UWORD BGPWIDTH:7; /* BGPWIDTH */
+ _UWORD BGPSTART:8; /* BGPSTART */
+ } BIT; /* */
+ } BTGPCR; /* */
+ union { /* ACCCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD KILLEROFFSET:4; /* KILLEROFFSET */
+ _UWORD ACCMODE:1; /* ACCMODE */
+ _UWORD ACCMAXGAIN:2; /* ACCMAXGAIN */
+ _UWORD ACCLEVEL:9; /* ACCLEVEL */
+ } BIT; /* */
+ } ACCCR1; /* */
+ union { /* ACCCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :5; /* */
+ _UWORD CHROMASUBGAIN:2; /* CHROMASUBGAIN */
+ _UWORD CHROMAMAINGAIN:9; /* CHROMAMAINGAIN */
+ } BIT; /* */
+ } ACCCR2; /* */
+ union { /* ACCCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD ACCRESPONSE:2; /* ACCRESPONSE */
+ _UWORD ACCPRECIS:6; /* ACCPRECIS */
+ _UWORD KILLERMODE:1; /* KILLERMODE */
+ _UWORD KILLERLEVEL:6; /* KILLERLEVEL */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } ACCCR3; /* */
+ union { /* TINTCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD TINTSUB:6; /* TINTSUB */
+ _UWORD TINTMAIN:10; /* TINTMAIN */
+ } BIT; /* */
+ } TINTCR; /* */
+ union { /* YCDCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD LUMADELAY:5; /* LUMADELAY */
+ _UWORD :1; /* */
+ _UWORD CHROMALPF:1; /* CHROMALPF */
+ _UWORD DEMODMODE:2; /* DEMODMODE */
+ } BIT; /* */
+ } YCDCR; /* */
+ union { /* AGCCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD DOREDUCE:1; /* DOREDUCE */
+ _UWORD NOREDUCE:1; /* NOREDUCE */
+ _UWORD AGCRESPONSE:3; /* AGCRESPONSE */
+ _UWORD AGCLEVEL:9; /* AGCLEVEL */
+ } BIT; /* */
+ } AGCCR1; /* */
+ union { /* AGCCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD AGCPRECIS:6; /* AGCPRECIS */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } AGCCR2; /* */
+ union { /* PKLIMITCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PEAKLEVEL:2; /* PEAKLEVEL */
+ _UWORD PEAKATTACK:2; /* PEAKATTACK */
+ _UWORD PEAKRELEASE:2; /* PEAKRELEASE */
+ _UWORD PEAKRATIO:2; /* PEAKRATIO */
+ _UWORD MAXPEAKSAMPLES:8; /* MAXPEAKSAMPLES */
+ } BIT; /* */
+ } PKLIMITCR; /* */
+ union { /* RGORCR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD RADJ_O_LEVEL0:10; /* RADJ_O_LEVEL0 */
+ } BIT; /* */
+ } RGORCR1; /* */
+ union { /* RGORCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD RADJ_U_LEVEL0:10; /* RADJ_U_LEVEL0 */
+ } BIT; /* */
+ } RGORCR2; /* */
+ union { /* RGORCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD RADJ_O_LEVEL1:10; /* RADJ_O_LEVEL1 */
+ } BIT; /* */
+ } RGORCR3; /* */
+ union { /* RGORCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD RADJ_U_LEVEL1:10; /* RADJ_U_LEVEL1 */
+ } BIT; /* */
+ } RGORCR4; /* */
+ union { /* RGORCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD RADJ_O_LEVEL2:10; /* RADJ_O_LEVEL2 */
+ } BIT; /* */
+ } RGORCR5; /* */
+ union { /* RGORCR6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD RADJ_U_LEVEL2:10; /* RADJ_U_LEVEL2 */
+ } BIT; /* */
+ } RGORCR6; /* */
+ union { /* RGORCR7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD TEST_MONI:3; /* TEST_MONI */
+ _UWORD RADJ_MIX_K_FIX:3; /* RADJ_MIX_K_FIX */
+ _UWORD :6; /* */
+ _UWORD UCMP_SW:1; /* UCMP_SW */
+ _UWORD DCMP_SW:1; /* DCMP_SW */
+ _UWORD HWIDE_SW:1; /* HWIDE_SW */
+ } BIT; /* */
+ } RGORCR7; /* */
+ _UBYTE wk3[24]; /* */
+ union { /* AFCPFCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :11; /* */
+ _UWORD PHDET_FIX:1; /* PHDET_FIX */
+ _UWORD :1; /* */
+ _UWORD PHDET_DIV:3; /* PHDET_DIV */
+ } BIT; /* */
+ } AFCPFCR; /* */
+ union { /* RUPDCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD NEWSETTING:1; /* NEWSETTING */
+ _UWORD :15; /* */
+ } BIT; /* */
+ } RUPDCR; /* */
+ union { /* VSYNCSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD FHCOUNT_L:1; /* FHCOUNT_L */
+ _UWORD FHLOCK:1; /* FHLOCK */
+ _UWORD ISNOISY:1; /* ISNOISY */
+ _UWORD FHMODE:1; /* FHMODE */
+ _UWORD NOSIGNAL:1; /* NOSIGNAL */
+ _UWORD FVLOCK:1; /* FVLOCK */
+ _UWORD FVMODE:1; /* FVMODE */
+ _UWORD INTERLACED:1; /* INTERLACED */
+ _UWORD FVCOUNT:8; /* FVCOUNT */
+ } BIT; /* */
+ } VSYNCSR; /* */
+ union { /* HSYNCSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD FHCOUNT_H:16; /* FHCOUNT_H */
+ } BIT; /* */
+ } HSYNCSR; /* */
+ union { /* DCPSR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CLAMPLEVEL_CB:6; /* CLAMPLEVEL_CB */
+ _UWORD CLAMPLEVEL_Y:10; /* CLAMPLEVEL_Y */
+ } BIT; /* */
+ } DCPSR1; /* */
+ union { /* DCPSR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CLAMPLEVEL_CR:6; /* CLAMPLEVEL_CR */
+ _UWORD :10; /* */
+ } BIT; /* */
+ } DCPSR2; /* */
+ _UBYTE wk4[4]; /* */
+ union { /* NSDSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD ACFSTRENGTH:16; /* ACFSTRENGTH */
+ } BIT; /* */
+ } NSDSR; /* */
+ union { /* CROMASR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD COLORSYS:2; /* COLORSYS */
+ _UWORD FSCMODE:1; /* FSCMODE */
+ _UWORD FSCLOCK:1; /* FSCLOCK */
+ _UWORD NOBURST:1; /* NOBURST */
+ _UWORD ACCSUBGAIN:2; /* ACCSUBGAIN */
+ _UWORD ACCMAINGAIN:9; /* ACCMAINGAIN */
+ } BIT; /* */
+ } CROMASR1; /* */
+ union { /* CROMASR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD ISSECAM:1; /* ISSECAM */
+ _UWORD ISPAL:1; /* ISPAL */
+ _UWORD ISNTSC:1; /* ISNTSC */
+ _UWORD :2; /* */
+ _UWORD LOCKLEVEL:8; /* LOCKLEVEL */
+ } BIT; /* */
+ } CROMASR2; /* */
+ union { /* SYNCSSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD ISREDUCED:1; /* ISREDUCED */
+ _UWORD :2; /* */
+ _UWORD SYNCDEPTH:10; /* SYNCDEPTH */
+ } BIT; /* */
+ } SYNCSSR; /* */
+ union { /* AGCCSR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD HIGHSAMPLES:8; /* HIGHSAMPLES */
+ _UWORD PEAKSAMPLES:8; /* PEAKSAMPLES */
+ } BIT; /* */
+ } AGCCSR1; /* */
+ union { /* AGCCSR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD AGCCONVERGE:1; /* AGCCONVERGE */
+ _UWORD AGCGAIN:8; /* AGCGAIN */
+ } BIT; /* */
+ } AGCCSR2; /* */
+ _UBYTE wk5[14]; /* */
+ _UBYTE wk6[90]; /* */
+ _UBYTE wk7[4]; /* */
+ union { /* YCSCR3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD K15:4; /* K15 */
+ _UWORD K13:6; /* K13 */
+ _UWORD K11:6; /* K11 */
+ } BIT; /* */
+ } YCSCR3; /* */
+ union { /* YCSCR4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD K16:4; /* K16 */
+ _UWORD K14:6; /* K14 */
+ _UWORD K12:6; /* K12 */
+ } BIT; /* */
+ } YCSCR4; /* */
+ union { /* YCSCR5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD K22A:8; /* K22A */
+ _UWORD :2; /* */
+ _UWORD K21A:6; /* K21A */
+ } BIT; /* */
+ } YCSCR5; /* */
+ union { /* YCSCR6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD K22B:8; /* K22B */
+ _UWORD :2; /* */
+ _UWORD K21B:6; /* K21B */
+ } BIT; /* */
+ } YCSCR6; /* */
+ union { /* YCSCR7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD K23B:4; /* K23B */
+ _UWORD K23A:4; /* K23A */
+ _UWORD :3; /* */
+ _UWORD K24:5; /* K24 */
+ } BIT; /* */
+ } YCSCR7; /* */
+ union { /* YCSCR8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD HBPF_NARROW:1; /* HBPF_NARROW */
+ _UWORD HVBPF_NARROW:1; /* HVBPF_NARROW */
+ _UWORD HBPF1_9TAP_ON:1; /* HBPF1_9TAP_ON */
+ _UWORD HVBPF1_9TAP_ON:1; /* HVBPF1_9TAP_ON */
+ _UWORD HFIL_TAP_SEL:1; /* HFIL_TAP_SEL */
+ _UWORD :11; /* */
+ } BIT; /* */
+ } YCSCR8; /* */
+ union { /* YCSCR9 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DET2_ON:1; /* DET2_ON */
+ _UWORD :3; /* */
+ _UWORD HSEL_MIX_Y:4; /* HSEL_MIX_Y */
+ _UWORD VSEL_MIX_Y:4; /* VSEL_MIX_Y */
+ _UWORD HVSEL_MIX_Y:4; /* HVSEL_MIX_Y */
+ } BIT; /* */
+ } YCSCR9; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* YCSCR11 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :7; /* */
+ _UWORD V_Y_LEVEL:9; /* V_Y_LEVEL */
+ } BIT; /* */
+ } YCSCR11; /* */
+ union { /* YCSCR12 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DET2_MIX_C:4; /* DET2_MIX_C */
+ _UWORD DET2_MIX_Y:4; /* DET2_MIX_Y */
+ _UWORD :4; /* */
+ _UWORD FIL2_MODE_2D:2; /* FIL2_MODE_2D */
+ _UWORD :1; /* */
+ _UWORD FIL2_NARROW_2D:1; /* FIL2_NARROW_2D */
+ } BIT; /* */
+ } YCSCR12; /* */
+ _UBYTE wk9[104]; /* */
+ union { /* DCPCR9 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD CLP_HOLD_ON_Y:1; /* CLP_HOLD_ON_Y */
+ _UWORD CLP_HOLD_ON_CB:1; /* CLP_HOLD_ON_CB */
+ _UWORD CLP_HOLD_ON_CR:1; /* CLP_HOLD_ON_CR */
+ _UWORD :10; /* */
+ } BIT; /* */
+ } DCPCR9; /* */
+ _UBYTE wk10[12]; /* */
+ _UBYTE wk11[4]; /* */
+ union { /* YCTWA_F0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F0:13; /* FIL2_2D_WA_F0 */
+ } BIT; /* */
+ } YCTWA_F0; /* */
+ union { /* YCTWA_F1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F1:13; /* FIL2_2D_WA_F1 */
+ } BIT; /* */
+ } YCTWA_F1; /* */
+ union { /* YCTWA_F2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F2:13; /* FIL2_2D_WA_F2 */
+ } BIT; /* */
+ } YCTWA_F2; /* */
+ union { /* YCTWA_F3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F3:13; /* FIL2_2D_WA_F3 */
+ } BIT; /* */
+ } YCTWA_F3; /* */
+ union { /* YCTWA_F4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F4:13; /* FIL2_2D_WA_F4 */
+ } BIT; /* */
+ } YCTWA_F4; /* */
+ union { /* YCTWA_F5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F5:13; /* FIL2_2D_WA_F5 */
+ } BIT; /* */
+ } YCTWA_F5; /* */
+ union { /* YCTWA_F6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F6:13; /* FIL2_2D_WA_F6 */
+ } BIT; /* */
+ } YCTWA_F6; /* */
+ union { /* YCTWA_F7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F7:13; /* FIL2_2D_WA_F7 */
+ } BIT; /* */
+ } YCTWA_F7; /* */
+ union { /* YCTWA_F8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WA_F8:13; /* FIL2_2D_WA_F8 */
+ } BIT; /* */
+ } YCTWA_F8; /* */
+ union { /* YCTWB_F0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F0:13; /* FIL2_2D_WB_F0 */
+ } BIT; /* */
+ } YCTWB_F0; /* */
+ union { /* YCTWB_F1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F1:13; /* FIL2_2D_WB_F1 */
+ } BIT; /* */
+ } YCTWB_F1; /* */
+ union { /* YCTWB_F2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F2:13; /* FIL2_2D_WB_F2 */
+ } BIT; /* */
+ } YCTWB_F2; /* */
+ union { /* YCTWB_F3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F3:13; /* FIL2_2D_WB_F3 */
+ } BIT; /* */
+ } YCTWB_F3; /* */
+ union { /* YCTWB_F4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F4:13; /* FIL2_2D_WB_F4 */
+ } BIT; /* */
+ } YCTWB_F4; /* */
+ union { /* YCTWB_F5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F5:13; /* FIL2_2D_WB_F5 */
+ } BIT; /* */
+ } YCTWB_F5; /* */
+ union { /* YCTWB_F6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F6:13; /* FIL2_2D_WB_F6 */
+ } BIT; /* */
+ } YCTWB_F6; /* */
+ union { /* YCTWB_F7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F7:13; /* FIL2_2D_WB_F7 */
+ } BIT; /* */
+ } YCTWB_F7; /* */
+ union { /* YCTWB_F8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_WB_F8:13; /* FIL2_2D_WB_F8 */
+ } BIT; /* */
+ } YCTWB_F8; /* */
+ union { /* YCTNA_F0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F0:13; /* FIL2_2D_NA_F0 */
+ } BIT; /* */
+ } YCTNA_F0; /* */
+ union { /* YCTNA_F1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F1:13; /* FIL2_2D_NA_F1 */
+ } BIT; /* */
+ } YCTNA_F1; /* */
+ union { /* YCTNA_F2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F2:13; /* FIL2_2D_NA_F2 */
+ } BIT; /* */
+ } YCTNA_F2; /* */
+ union { /* YCTNA_F3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F3:13; /* FIL2_2D_NA_F3 */
+ } BIT; /* */
+ } YCTNA_F3; /* */
+ union { /* YCTNA_F4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F4:13; /* FIL2_2D_NA_F4 */
+ } BIT; /* */
+ } YCTNA_F4; /* */
+ union { /* YCTNA_F5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F5:13; /* FIL2_2D_NA_F5 */
+ } BIT; /* */
+ } YCTNA_F5; /* */
+ union { /* YCTNA_F6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F6:13; /* FIL2_2D_NA_F6 */
+ } BIT; /* */
+ } YCTNA_F6; /* */
+ union { /* YCTNA_F7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F7:13; /* FIL2_2D_NA_F7 */
+ } BIT; /* */
+ } YCTNA_F7; /* */
+ union { /* YCTNA_F8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NA_F8:13; /* FIL2_2D_NA_F8 */
+ } BIT; /* */
+ } YCTNA_F8; /* */
+ union { /* YCTNB_F0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F0:13; /* FIL2_2D_NB_F0 */
+ } BIT; /* */
+ } YCTNB_F0; /* */
+ union { /* YCTNB_F1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F1:13; /* FIL2_2D_NB_F1 */
+ } BIT; /* */
+ } YCTNB_F1; /* */
+ union { /* YCTNB_F2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F2:13; /* FIL2_2D_NB_F2 */
+ } BIT; /* */
+ } YCTNB_F2; /* */
+ union { /* YCTNB_F3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F3:13; /* FIL2_2D_NB_F3 */
+ } BIT; /* */
+ } YCTNB_F3; /* */
+ union { /* YCTNB_F4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F4:13; /* FIL2_2D_NB_F4 */
+ } BIT; /* */
+ } YCTNB_F4; /* */
+ union { /* YCTNB_F5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F5:13; /* FIL2_2D_NB_F5 */
+ } BIT; /* */
+ } YCTNB_F5; /* */
+ union { /* YCTNB_F6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F6:13; /* FIL2_2D_NB_F6 */
+ } BIT; /* */
+ } YCTNB_F6; /* */
+ union { /* YCTNB_F7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F7:13; /* FIL2_2D_NB_F7 */
+ } BIT; /* */
+ } YCTNB_F7; /* */
+ union { /* YCTNB_F8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :3; /* */
+ _UWORD FIL2_2D_NB_F8:13; /* FIL2_2D_NB_F8 */
+ } BIT; /* */
+ } YCTNB_F8; /* */
+ _UBYTE wk12[38]; /* */
+ union { /* YGAINCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD Y_GAIN2:10; /* Y_GAIN2 */
+ } BIT; /* */
+ } YGAINCR; /* */
+ union { /* CBGAINCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD CB_GAIN2:10; /* CB_GAIN2 */
+ } BIT; /* */
+ } CBGAINCR; /* */
+ union { /* CRGAINCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD CR_GAIN2:10; /* CR_GAIN2 */
+ } BIT; /* */
+ } CRGAINCR; /* */
+ _UBYTE wk13[122]; /* */
+ union { /* PGA_UPDATE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD PGA_VEN:1; /* PGA_VEN */
+ } BIT; /* */
+ } PGA_UPDATE; /* */
+ union { /* PGACR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD PGA_GAIN_SEL:1; /* PGA_GAIN_SEL */
+ _UWORD PGA_GAIN:5; /* PGA_GAIN */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } PGACR; /* */
+ union { /* ADCCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :15; /* */
+ _UWORD ADC_VINSEL:1; /* ADC_VINSEL */
+ } BIT; /* */
+ } ADCCR2; /* */
+}; /* */
+struct st_ubc { /* struct UBC */
+ union { /* BAR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BA0_:32; /* BA0_ */
+ } BIT; /* */
+ } BAR0; /* */
+ union { /* BAMR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BAM0_:32; /* BAM0_ */
+ } BIT;
+ } BAMR0;
+ union { /* BDR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BD0_:32; /* BD0_ */
+ } BIT;
+ } BDR0;
+ union { /* BDMR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BDM0_:32; /* BDM0_ */
+ } BIT;
+ } BDMR0;
+ union { /* BAR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BA1_:32; /* BA1_ */
+ } BIT;
+ } BAR1;
+ union { /* BAMR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BAM1_:32; /* BAM1_ */
+ } BIT;
+ } BAMR1;
+ union { /* BDR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BD1_:32; /* BD1_ */
+ } BIT;
+ } BDR1;
+ union { /* BDMR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BDM1_:32; /* BDM1_ */
+ } BIT;
+ } BDMR1;
+ _UBYTE wk0[128];
+ union { /* BBR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2;
+ _UWORD UBID0:1; /* UBID0 */
+ _UWORD DBE0:1; /* DBE0 */
+ _UWORD :2; /* */
+ _UWORD CP0_:2; /* CP0_ */
+ _UWORD CD0_:2; /* CD0_ */
+ _UWORD ID0_:2; /* ID0_ */
+ _UWORD RW0_:2; /* RW0_ */
+ _UWORD SZ0_:2; /* SZ0_ */
+ } BIT;
+ } BBR0;
+ _UBYTE wk1[14];
+ union { /* BBR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :2; /* */
+ _UWORD UBID1:1; /* UBID1 */
+ _UWORD DBE1:1; /* DBE1 */
+ _UWORD :2; /* */
+ _UWORD CP1_:2; /* CP1_ */
+ _UWORD CD1_:2; /* CD1_ */
+ _UWORD ID1_:2; /* ID1_ */
+ _UWORD RW1_:2; /* RW1_ */
+ _UWORD SZ1_:2; /* SZ1_ */
+ } BIT;
+ } BBR1;
+ _UBYTE wk2[14];
+ union { /* BRCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD UTOD1:1; /* UTOD1 */
+ _UDWORD UTOD0:1; /* UTOD0 */
+ _UDWORD CKS:2; /* CKS */
+ _UDWORD SCMFC0:1; /* SCMFC0 */
+ _UDWORD SCMFC1:1; /* SCMFC1 */
+ _UDWORD SCMFD0:1; /* SCMFD0 */
+ _UDWORD SCMFD1:1; /* SCMFD1 */
+ _UDWORD :5; /* */
+ _UDWORD PCB1:1; /* PCB1 */
+ _UDWORD PCB0:1; /* PCB0 */
+ _UDWORD :5; /* */
+ } BIT;
+ } BRCR;
+};
+struct st_disc { /* struct DISC */
+ union { /* DOCMCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :15; /* */
+ _UDWORD CMPRU:1; /* CMPRU */
+ _UDWORD :15; /* */
+ _UDWORD CMPR:1; /* CMPR */
+ } BIT; /* */
+ } DOCMCR; /* */
+ union { /* DOCMSTR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD CMPST:1; /* CMPST */
+ } BIT; /* */
+ } DOCMSTR; /* */
+ union { /* DOCMCLSTR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD CMPCLST:1; /* CMPCLST */
+ } BIT; /* */
+ } DOCMCLSTR; /* */
+ union { /* DOCMIENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :31; /* */
+ _UDWORD CMPIEN:1; /* CMPIEN */
+ } BIT; /* */
+ } DOCMIENR; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* DOCMPMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :15; /* */
+ _UDWORD CMPBT:1; /* CMPBT */
+ _UDWORD CMPDFA:8; /* CMPDFA */
+ _UDWORD CMPDAUF:1; /* CMPDAUF */
+ _UDWORD :3; /* */
+ _UDWORD CMPSELP:4; /* CMPSELP */
+ } BIT; /* */
+ } DOCMPMR; /* */
+ union { /* DOCMECRCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMPECRC:32; /* CMPECRC */
+ } BIT; /* */
+ } DOCMECRCR; /* */
+ union { /* DOCMCCRCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMPCCRC:32; /* CMPCCRC */
+ } BIT; /* */
+ } DOCMCCRCR; /* */
+ union { /* DOCMSPXR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :21; /* */
+ _UDWORD CMPSPX:11; /* CMPSPX */
+ } BIT; /* */
+ } DOCMSPXR; /* */
+ union { /* DOCMSPYR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :21; /* */
+ _UDWORD CMPSPY:11; /* CMPSPY */
+ } BIT; /* */
+ } DOCMSPYR; /* */
+ union { /* DOCMSZXR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :21; /* */
+ _UDWORD CMPSZX:11; /* CMPSZX */
+ } BIT; /* */
+ } DOCMSZXR; /* */
+ union { /* DOCMSZYR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :21; /* */
+ _UDWORD CMPSZY:11; /* CMPSZY */
+ } BIT; /* */
+ } DOCMSZYR; /* */
+ union { /* DOCMCRCIR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CRCINI:32; /* CRCINI */
+ } BIT; /* */
+ } DOCMCRCIR; /* */
+}; /* */
+struct st_jcu { /* struct JCU */
+ union { /* JCMOD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE DSP:1; /* DSP */
+ _UBYTE REDU:3; /* REDU */
+ } BIT; /* */
+ } JCMOD; /* */
+ union { /* JCCMD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BRST:1; /* BRST */
+ _UBYTE :4; /* */
+ _UBYTE JEND:1; /* JEND */
+ _UBYTE JRST:1; /* JRST */
+ _UBYTE JSRT:1; /* JSRT */
+ } BIT; /* */
+ } JCCMD; /* */
+ _UBYTE wk0_0[1]; /* */
+ union { /* JCQTN */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE QT3:2; /* QT3 */
+ _UBYTE QT2:2; /* QT2 */
+ _UBYTE QT1:2; /* QT1 */
+ } BIT; /* */
+ } JCQTN; /* */
+ union { /* JCHTN */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :2; /* */
+ _UBYTE HTA3:1; /* HTA3 */
+ _UBYTE HTD3:1; /* HTD3 */
+ _UBYTE HTA2:1; /* HTA2 */
+ _UBYTE HTD2:1; /* HTD2 */
+ _UBYTE HTA1:1; /* HTA1 */
+ _UBYTE HTD1:1; /* HTD1 */
+ } BIT; /* */
+ } JCHTN; /* */
+ union { /* JCDRIU */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE DRIU:8; /* DRIU */
+ } BIT; /* */
+ } JCDRIU; /* */
+ union { /* JCDRID */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE DRID:8; /* DRID */
+ } BIT; /* */
+ } JCDRID; /* */
+ union { /* JCVSZU */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE VSZU:8; /* VSZU */
+ } BIT; /* */
+ } JCVSZU; /* */
+ union { /* JCVSZD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE VSZD:8; /* VSZD */
+ } BIT; /* */
+ } JCVSZD; /* */
+ union { /* JCHSZU */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE HSZU:8; /* HSZU */
+ } BIT; /* */
+ } JCHSZU; /* */
+ union { /* JCHSZD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE HSZD:8; /* HSZD */
+ } BIT; /* */
+ } JCHSZD; /* */
+ union { /* JCDTCU */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE DCU:8; /* DCU */
+ } BIT; /* */
+ } JCDTCU; /* */
+ union { /* JCDTCM */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE DCM:8; /* DCM */
+ } BIT; /* */
+ } JCDTCM; /* */
+ union { /* JCDTCD */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE DCD:8; /* DCD */
+ } BIT; /* */
+ } JCDTCD; /* */
+ union { /* JINTE0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE INT7:1; /* INT7 */
+ _UBYTE INT6:1; /* INT6 */
+ _UBYTE INT5:1; /* INT5 */
+ _UBYTE :1; /* */
+ _UBYTE INT3:1; /* INT3 */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } JINTE0; /* */
+ union { /* JINTS0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE INS6:1; /* INS6 */
+ _UBYTE INS5:1; /* INS5 */
+ _UBYTE :1; /* */
+ _UBYTE INS3:1; /* INS3 */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } JINTS0; /* */
+ union { /* JCDERR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE ERR:4; /* ERR */
+ } BIT; /* */
+ } JCDERR; /* */
+ union { /* JCRST */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :7; /* */
+ _UBYTE RST:1; /* RST */
+ } BIT; /* */
+ } JCRST; /* */
+ _UBYTE wk0[46]; /* */
+ union { /* JIFECNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :17; /* */
+ _UDWORD JOUTRINI:1; /* JOUTRINI */
+ _UDWORD JOUTRCMD:1; /* JOUTRCMD */
+ _UDWORD JOUTC:1; /* JOUTC */
+ _UDWORD :1; /* */
+ _UDWORD JOUTSWAP:3; /* JOUTSWAP */
+ _UDWORD :1; /* */
+ _UDWORD DINRINI:1; /* DINRINI */
+ _UDWORD DINRCMD:1; /* DINRCMD */
+ _UDWORD DINLC:1; /* DINLC */
+ _UDWORD :1; /* */
+ _UDWORD DINSWAP:3; /* DINSWAP */
+ } BIT; /* */
+ } JIFECNT; /* */
+ union { /* JIFESA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ESA:32; /* ESA */
+ } BIT; /* */
+ } JIFESA; /* */
+ union { /* JIFESOFST */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :17; /* */
+ _UDWORD ESMW:15; /* ESMW */
+ } BIT; /* */
+ } JIFESOFST; /* */
+ union { /* JIFEDA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EDA:32; /* EDA */
+ } BIT; /* */
+ } JIFEDA; /* */
+ union { /* JIFESLC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD LINES:16; /* LINES */
+ } BIT; /* */
+ } JIFESLC; /* */
+ union { /* JIFEDDC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD JDATAS:16; /* JDATAS */
+ } BIT; /* */
+ } JIFEDDC; /* */
+ union { /* JIFDCNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :2; /* */
+ _UDWORD VINTER:2; /* VINTER */
+ _UDWORD HINTER:2; /* HINTER */
+ _UDWORD OPF:2; /* OPF */
+ _UDWORD :9; /* */
+ _UDWORD JINRINI:1; /* JINRINI */
+ _UDWORD JINRCMD:1; /* JINRCMD */
+ _UDWORD JINC:1; /* JINC */
+ _UDWORD :1; /* */
+ _UDWORD JINSWAP:3; /* JINSWAP */
+ _UDWORD :1; /* */
+ _UDWORD DOUTRINI:1; /* DOUTRINI */
+ _UDWORD DOUTRCMD:1; /* DOUTRCMD */
+ _UDWORD DOUTLC:1; /* DOUTLC */
+ _UDWORD :1; /* */
+ _UDWORD DOUTSWAP:3; /* DOUTSWAP */
+ } BIT; /* */
+ } JIFDCNT; /* */
+ union { /* JIFDSA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DSA:32; /* DSA */
+ } BIT; /* */
+ } JIFDSA; /* */
+ union { /* JIFDDOFST */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :17; /* */
+ _UDWORD DDMW:15; /* DDMW */
+ } BIT; /* */
+ } JIFDDOFST; /* */
+ union { /* JIFDDA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DDA:32; /* DDA */
+ } BIT; /* */
+ } JIFDDA; /* */
+ union { /* JIFDSDC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD JDATAS:16; /* JDATAS */
+ } BIT; /* */
+ } JIFDSDC; /* */
+ union { /* JIFDDLC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD LINES:16; /* LINES */
+ } BIT; /* */
+ } JIFDDLC; /* */
+ union { /* JIFDADT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD ALPHA:8; /* ALPHA */
+ } BIT; /* */
+ } JIFDADT; /* */
+ _UBYTE wk1[24]; /* */
+ union { /* JINTE1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD CBTEN:1; /* CBTEN */
+ _UDWORD DINLEN:1; /* DINLEN */
+ _UDWORD JOUTEN:1; /* JOUTEN */
+ _UDWORD :1; /* */
+ _UDWORD DBTEN:1; /* DBTEN */
+ _UDWORD JINEN:1; /* JINEN */
+ _UDWORD DOUTLEN:1; /* DOUTLEN */
+ } BIT; /* */
+ } JINTE1; /* */
+ union { /* JINTS1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :25; /* */
+ _UDWORD CBTF:1; /* CBTF */
+ _UDWORD DINLF:1; /* DINLF */
+ _UDWORD JOUTF:1; /* JOUTF */
+ _UDWORD :1; /* */
+ _UDWORD DBTF:1; /* DBTF */
+ _UDWORD JINF:1; /* JINF */
+ _UDWORD DOUTLF:1; /* DOUTLF */
+ } BIT; /* */
+ } JINTS1; /* */
+ _UBYTE wk2[108]; /* */
+ _UBYTE JCQTBL0[64]; /* JCQTBL0 */
+ _UBYTE JCQTBL1[64]; /* JCQTBL1 */
+ _UBYTE JCQTBL2[64]; /* JCQTBL2 */
+ _UBYTE JCQTBL3[64]; /* JCQTBL3 */
+ _UBYTE JCHTBD0[28]; /* JCHTBD0 */
+ _UBYTE wk7[4]; /* */
+ _UBYTE JCHTBA0[178]; /* JCHTBA0 */
+ _UBYTE wk8[46]; /* */
+ _UBYTE JCHTBD1[28]; /* JCHTBD1 */
+ _UBYTE wk9[4]; /* */
+ _UBYTE JCHTBA1[178]; /* JCHTBA1 */
+}; /* */
+struct st_spibsc { /* struct SPIBSC */
+ union { /* CMNCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD MD:1; /* MD */
+ _UDWORD :7; /* */
+ _UDWORD MOIIO3:2; /* MOIIO3 */
+ _UDWORD MOIIO2:2; /* MOIIO2 */
+ _UDWORD MOIIO1:2; /* MOIIO1 */
+ _UDWORD MOIIO0:2; /* MOIIO0 */
+ _UDWORD IO3FV:2; /* IO3FV */
+ _UDWORD IO2FV:2; /* IO2FV */
+ _UDWORD :2; /* */
+ _UDWORD IO0FV:2; /* IO0FV */
+ _UDWORD :1; /* */
+ _UDWORD CPHAT:1; /* CPHAT */
+ _UDWORD CPHAR:1; /* CPHAR */
+ _UDWORD SSLP:1; /* SSLP */
+ _UDWORD CPOL:1; /* CPOL */
+ _UDWORD :1; /* */
+ _UDWORD BSZ:2; /* BSZ */
+ } BIT; /* */
+ } CMNCR; /* */
+ union { /* SSLDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :13; /* */
+ _UDWORD SPNDL:3; /* SPNDL */
+ _UDWORD :5; /* */
+ _UDWORD SLNDL:3; /* SLNDL */
+ _UDWORD :5; /* */
+ _UDWORD SCKDL:3; /* SCKDL */
+ } BIT; /* */
+ } SSLDR; /* */
+ union { /* SPBCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :16; /* */
+ _UDWORD SPBR:8; /* SPBR */
+ _UDWORD :6; /* */
+ _UDWORD BRDV:2; /* BRDV */
+ } BIT; /* */
+ } SPBCR; /* */
+ union { /* DRCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD RBURST:4; /* RBURST */
+ _UDWORD :6; /* */
+ _UDWORD RCF:1; /* RCF */
+ _UDWORD RBE:1; /* RBE */
+ _UDWORD :7; /* */
+ _UDWORD SSLE:1; /* SSLE */
+ } BIT; /* */
+ } DRCR; /* */
+ union { /* DRCMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD CMD:8; /* CMD */
+ _UDWORD :8; /* */
+ _UDWORD OCMD:8; /* OCMD */
+ } BIT; /* */
+ } DRCMR; /* */
+ union { /* DREAR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD EAV:8; /* EAV */
+ _UDWORD :13; /* */
+ _UDWORD EAC:3; /* EAC */
+ } BIT; /* */
+ } DREAR; /* */
+ union { /* DROPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OPD3:8; /* OPD3 */
+ _UDWORD OPD2:8; /* OPD2 */
+ _UDWORD OPD1:8; /* OPD1 */
+ _UDWORD OPD0:8; /* OPD0 */
+ } BIT; /* */
+ } DROPR; /* */
+ union { /* DRENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CDB:2; /* CDB */
+ _UDWORD OCDB:2; /* OCDB */
+ _UDWORD :2; /* */
+ _UDWORD ADB:2; /* ADB */
+ _UDWORD :2; /* */
+ _UDWORD OPDB:2; /* OPDB */
+ _UDWORD :2; /* */
+ _UDWORD DRDB:2; /* DRDB */
+ _UDWORD :1; /* */
+ _UDWORD CDE:1; /* CDE */
+ _UDWORD :1; /* */
+ _UDWORD OCDE:1; /* OCDE */
+ _UDWORD ADE:4; /* ADE */
+ _UDWORD OPDE:4; /* OPDE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } DRENR; /* */
+ union { /* SMCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :23; /* */
+ _UDWORD SSLKP:1; /* SSLKP */
+ _UDWORD :5; /* */
+ _UDWORD SPIRE:1; /* SPIRE */
+ _UDWORD SPIWE:1; /* SPIWE */
+ _UDWORD SPIE:1; /* SPIE */
+ } BIT; /* */
+ } SMCR; /* */
+ union { /* SMCMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD CMD:8; /* CMD */
+ _UDWORD :8; /* */
+ _UDWORD OCMD:8; /* OCMD */
+ } BIT; /* */
+ } SMCMR; /* */
+ union { /* SMADR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ADR:32; /* ADR */
+ } BIT; /* */
+ } SMADR; /* */
+ union { /* SMOPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OPD3:8; /* OPD3 */
+ _UDWORD OPD2:8; /* OPD2 */
+ _UDWORD OPD1:8; /* OPD1 */
+ _UDWORD OPD0:8; /* OPD0 */
+ } BIT; /* */
+ } SMOPR; /* */
+ union { /* SMENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CDB:2; /* CDB */
+ _UDWORD OCDB:2; /* OCDB */
+ _UDWORD :2; /* */
+ _UDWORD ADB:2; /* ADB */
+ _UDWORD :2; /* */
+ _UDWORD OPDB:2; /* OPDB */
+ _UDWORD :2; /* */
+ _UDWORD SPIDB:2; /* SPIDB */
+ _UDWORD :1; /* */
+ _UDWORD CDE:1; /* CDE */
+ _UDWORD :1; /* */
+ _UDWORD OCDE:1; /* OCDE */
+ _UDWORD ADE:4; /* ADE */
+ _UDWORD OPDE:4; /* OPDE */
+ _UDWORD SPIDE:4; /* SPIDE */
+ } BIT; /* */
+ } SMENR; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* SMRDR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD RDATA0:32; /* RDATA0 */
+ } BIT; /* */
+ } SMRDR0; /* */
+ union { /* SMRDR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD RDATA1:32; /* RDATA1 */
+ } BIT; /* */
+ } SMRDR1; /* */
+ union { /* SMWDR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD WDATA0:32; /* WDATA0 */
+ } BIT; /* */
+ } SMWDR0; /* */
+ union { /* SMWDR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD H; /* High */
+ _UWORD L; /* Low */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE HH; /* High, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE LL; /* Low, Low */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD WDATA1:32; /* WDATA1 */
+ } BIT; /* */
+ } SMWDR1; /* */
+ union { /* CMNSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :30; /* */
+ _UDWORD SSLF:1; /* SSLF */
+ _UDWORD TEND:1; /* TEND */
+ } BIT; /* */
+ } CMNSR; /* */
+}; /* */
+
+ #if 0
+#define CPG (*(volatile struct st_cpg *)0xFFFE0010) /* CPG Address */
+#define INTC (*(volatile struct st_intc *)0xFFFE0800) /* INTC Address */
+ #endif
+#define CCNT (*(volatile struct st_ccnt *)0xFFFC1000) /* CCNT Address */
+ #if 0
+#define BSC (*(volatile struct st_bsc *)0xFFFC0000) /* BSC Address */
+#define DMAC (*(volatile struct st_dmac *)0xFFFE1000) /* DMAC Address */
+ #endif
+ #if 0
+#define MTU2 (*(volatile struct st_mtu2 *)0xFFFE4000) /* MTU2 Address */
+ #endif
+#define CMT (*(volatile struct st_cmt *)0xFFFEC000) /* CMT Address */
+#define WDT (*(volatile union un_wdt *)0xFFFE0000) /* WDT Address */
+#define RTC (*(volatile struct st_rtc *)0xFFFE6000) /* RTC Address */
+ #if 0
+#define SCIF0 (*(volatile struct st_scif02346 *)0xE8007000)/* SCIF0 Address */
+#define SCIF1 (*(volatile struct st_scif157 *)0xE8007800)/* SCIF1 Address */
+#define SCIF2 (*(volatile struct st_scif02346 *)0xE8008000)/* SCIF2 Address */
+#define SCIF3 (*(volatile struct st_scif02346 *)0xE8008800)/* SCIF3 Address */
+#define SCIF4 (*(volatile struct st_scif02346 *)0xE8009000)/* SCIF4 Address */
+#define SCIF5 (*(volatile struct st_scif157 *)0xE8009800)/* SCIF5 Address */
+#define SCIF6 (*(volatile struct st_scif02346 *)0xE800A000)/* SCIF6 Address */
+#define SCIF7 (*(volatile struct st_scif157 *)0xE800A800)/* SCIF7 Address */
+ #endif
+#define RSPI0 (*(volatile struct st_rspi *)0xE800E000) /* RSPI0 Address */
+#define RSPI1 (*(volatile struct st_rspi *)0xE800E800) /* RSPI1 Address */
+ #if 0
+#define IIC3_0 (*(volatile struct st_iic3 *)0xFFFEE000)/* IIC3_0 Address */
+#define IIC3_1 (*(volatile struct st_iic3 *)0xFFFEE400)/* IIC3_1 Address */
+#define IIC3_2 (*(volatile struct st_iic3 *)0xFFFEE800)/* IIC3_2 Address */
+#define IIC3_3 (*(volatile struct st_iic3 *)0xFFFEEC00)/* IIC3_3 Address */
+ #endif
+#define SSIF0 (*(volatile struct st_ssif *)0xFFFF0000)/* SSIF0 Address */
+#define SSIF1 (*(volatile struct st_ssif *)0xFFFF0800)/* SSIF1 Address */
+#define SSIF2 (*(volatile struct st_ssif *)0xFFFF1000)/* SSIF2 Address */
+#define SSIF3 (*(volatile struct st_ssif *)0xFFFF1800)/* SSIF3 Address */
+#define SSIF4 (*(volatile struct st_ssif *)0xFFFF2000)/* SSIF4 Address */
+#define SSIF5 (*(volatile struct st_ssif *)0xFFFF2800)/* SSIF5 Address */
+#define SIOF (*(volatile struct st_siof *)0xFFFF4800) /* SIOF Address */
+#define RCAN0 (*(volatile struct st_rcan *)0xFFFE5000) /* RCAN0 Address */
+#define RCAN1 (*(volatile struct st_rcan *)0xFFFE5800) /* RCAN1 Address */
+#define RCAN2 (*(volatile struct st_rcan *)0xFFFED800) /* RCAN2 Address */
+#define IEB (*(volatile struct st_ieb *)0xFFFEF000) /* IEB Address */
+#define SPDIF (*(volatile struct st_spdif *)0xE8012000)/* SPDIF Address */
+#define ROMDEC (*(volatile struct st_romdec *)0xE8005000)/* ROMDEC Address */
+ #if 0 /* Old ADC iodefine */
+#define ADC (*(volatile struct st_adc *)0xE8005800) /* ADC Address */
+ #endif/* Old ADC iodefine */
+#define FLCTL (*(volatile struct st_flctl *)0xFFFF4000)/* FLCTL Address */
+ #if 0
+#define USB (*(volatile struct st_usb *)0xE8010000) /* USB Address */
+ #endif
+#define VDC4 (*(volatile struct st_vdc4 *)0xFFFF7400) /* VDC4 Address */
+#define SRC0 (*(volatile struct st_src *)0xFFFE7000) /* SRC0 Address */
+#define SRC1 (*(volatile struct st_src *)0xFFFE7800) /* SRC1 Address */
+#define SRC2 (*(volatile struct st_src *)0xFFFE8000) /* SRC2 Address */
+ #if 0
+#define PORT (*(volatile struct st_gpio *)0xFFFE3810) /* GPIO Address */
+ #endif
+#define HUDI (*(volatile struct st_hudi *)0xFFFE2000) /* HUDI Address */
+#define PWM (*(volatile struct st_pwm *)0xFFFEF406) /* PWM Address */
+#define QSPI0 (*(volatile struct st_rqspi *)0xE8033800) /* RQSPI0 Address */
+#define QSPI1 (*(volatile struct st_rqspi *)0xE8034000) /* RQSPI1 Address */
+#define IMRLS (*(volatile struct st_imrls *)0xFFFF3008)/* IMRLS Address */
+#define SDG0 (*(volatile struct st_sdg0 *)0xFFFEC800) /* SDG0 Address */
+#define SDG1 (*(volatile struct st_sdg1 *)0xFFFECA00) /* SDG1 Address */
+#define SDG2 (*(volatile struct st_sdg2 *)0xFFFECC00) /* SDG2 Address */
+#define SDG3 (*(volatile struct st_sdg3 *)0xFFFECE00) /* SDG3 Address */
+#define MMC (*(volatile struct st_mmc *)0xE8030800) /* MMC Address */
+#define DVDEC (*(volatile struct st_dvdec *)0xFFFFA008)/* DVDEC Address */
+#define UBC (*(volatile struct st_ubc *)0xFFFC0400) /* UBC Address */
+#define DISC (*(volatile struct st_disc *)0xFFFFA800) /* DISC Address */
+#define JCU (*(volatile struct st_jcu *)0xE8017000) /* JCU Address */
+#define SPIBSC (*(volatile struct st_spibsc *)0xFFFC1C00)/* SPIBSC Address */
+
+
+/* ==== includes each iodefine ==== */
+#include "usb_iodefine.h" /* for USB module */
+#include "scif_iodefine.h" /* for SCIF module */
+#include "pfc_iodefine.h" /* for PFC module */
+#include "bsc_iodefine.h" /* for BSC module */
+#include "cpg_iodefine.h" /* for CPG module */
+//#include "dmac_iodefine.h" /* for DMAC module */
+#include "intc_iodefine.h" /* for INTC module */
+#include "ostm_iodefine.h" /* for OSTM module */
+#include "riic_iodefine.h" /* for RIIC module */
+#include "prr_iodefine.h" /* for »•iƒo[ƒWƒ‡ƒ“ƒŒƒWƒXƒ^ */
+#include "spibsc_iodefine.h" /* for SPIBSC module */
+#include "mtu2_iodefine.h" /* for MTU2 module */
+
+#endif /* _IODEFINE_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/bsc_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/bsc_iodefine.h
new file mode 100644
index 000000000..a13eae30c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/bsc_iodefine.h
@@ -0,0 +1,324 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_iodefine.h
+* Version : 0.01
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* ARM Complier
+* :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program vecotr.s
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 27.07.2012 0.01 ŽQlŽ‘—¿Fsec08_BSC_20120615.doc !!!TOSCORn‚ÉŽd—l‘‚É‚È‚¢ƒrƒbƒg–¼‚ ‚è!!!
+*******************************************************************************/
+#ifndef __BSC_IODEFINE_H__
+#define __BSC_IODEFINE_H__
+
+#include "typedefine.h"
+
+typedef union { /* CSnBCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :9; /* */
+ _UDWORD BSZ:2; /* BSZ */
+ _UDWORD :1; /* */
+ _UDWORD TYPE:3; /* TYPE */
+ _UDWORD :1; /* */
+ _UDWORD IWRRS:3; /* IWRRS */
+ _UDWORD IWRRD:3; /* IWRRD */
+ _UDWORD IWRWS:3; /* IWRWS */
+ _UDWORD IWRWD:3; /* IWRWD */
+ _UDWORD IWW:3; /* IWW */
+ _UDWORD :1; /* */
+ } BIT; /* */
+} CSnBCR; /* */
+typedef union { /* TOSCORn */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD xxx:16; /* xxx */ /* !!!ƒrƒbƒg–¼Œˆ’莟‘æA’è‹`‚·‚é!!! */
+ _UDWORD :16; /* */
+ } BIT; /* */
+} TOSCORn; /* */
+
+struct st_bsc { /* struct BSC */
+ union { /* CMNCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD HIZCNT:1; /* HIZCNT */
+ _UDWORD HIZMEM:1; /* HIZMEM */
+ _UDWORD :7; /* */
+ _UDWORD DPRTY:2; /* DPRTY */
+ _UDWORD :13; /* */
+ _UDWORD AL0:1; /* AL0 */
+ _UDWORD :3; /* */
+ _UDWORD TL0:1; /* TL0 */
+ _UDWORD :3; /* */
+ } BIT; /* */
+ } CMNCR; /* */
+ CSnBCR CS0BCR; /* CS0BCR */
+ CSnBCR CS1BCR; /* CS1BCR */
+ CSnBCR CS2BCR; /* CS2BCR */
+ CSnBCR CS3BCR; /* CS3BCR */
+ CSnBCR CS4BCR; /* CS4BCR */
+ CSnBCR CS5BCR; /* CS5BCR */
+ _UBYTE wk0[12]; /* */
+ union { /* CS0WCR */
+ union { /* CS0WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD HW:2; /* HW */
+ _UDWORD :4; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD WR:4; /* WR */
+ _UDWORD SW:2; /* SW */
+ _UDWORD :7; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :11; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS0WCR(BROM_ASY) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :6; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD W:4; /* W */
+ _UDWORD :5; /* */
+ _UDWORD BW:2; /* BW */
+ _UDWORD :2; /* */
+ _UDWORD BST:2; /* BST */
+ _UDWORD :10; /* */
+ } BIT; /* */
+ } BROM_ASY; /* */
+ union { /* CS0WCR(BROM_SY) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :6; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD W:4; /* W */
+ _UDWORD :5; /* */
+ _UDWORD BW:2; /* BW */
+ _UDWORD :14; /* */
+ } BIT; /* */
+ } BROM_SY; /* */
+ } CS0WCR; /* */
+ union { /* CS1WCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD HW:2; /* HW */
+ _UDWORD :4; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD WR:4; /* WR */
+ _UDWORD SW:2; /* SW */
+ _UDWORD :3; /* */
+ _UDWORD WW:3; /* WW */
+ _UDWORD :1; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :11; /* */
+ } BIT; /* */
+ } CS1WCR; /* */
+ union { /* CS2WCR */
+ union { /* CS2WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :6; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD WR:4; /* WR */
+ _UDWORD :9; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :11; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS2WCR(SDRAM) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :7; /* */
+ _UDWORD A2CL:2; /* A2CL */
+ _UDWORD :23; /* */
+ } BIT; /* */
+ } SDRAM; /* */
+ } CS2WCR; /* */
+ union { /* CS3WCR */
+ union { /* CS3WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :6; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD WR:4; /* WR */
+ _UDWORD :9; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :11; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS3WCR(SDRAM) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD WTRC:2; /* WTRC */
+ _UDWORD :1; /* */
+ _UDWORD TRWL:2; /* TRWL */
+ _UDWORD :2; /* */
+ _UDWORD A3CL:2; /* A3CL */
+ _UDWORD :1; /* */
+ _UDWORD WTRCD:2; /* WTRCD */
+ _UDWORD :1; /* */
+ _UDWORD WTRP:2; /* WTRP */
+ _UDWORD :17; /* */
+ } BIT; /* */
+ } SDRAM; /* */
+ } CS3WCR; /* */
+ union { /* CS4WCR */
+ union { /* CS4WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD HW:2; /* HW */
+ _UDWORD :4; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD WR:4; /* WR */
+ _UDWORD SW:2; /* SW */
+ _UDWORD :3; /* */
+ _UDWORD WW:3; /* WW */
+ _UDWORD :1; /* */
+ _UDWORD BAS:1; /* BAS */
+ _UDWORD :11; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ union { /* CS4WCR(BROM_ASY) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD HW:2; /* HW */
+ _UDWORD :4; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD W:4; /* W */
+ _UDWORD SW:2; /* SW */
+ _UDWORD :3; /* */
+ _UDWORD BW:2; /* BW */
+ _UDWORD :2; /* */
+ _UDWORD BST:2; /* BST */
+ _UDWORD :10; /* */
+ } BIT; /* */
+ } BROM_ASY; /* */
+ } CS4WCR; /* */
+ union { /* CS5WCR */
+ union { /* CS5WCR(NORMAL) */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD HW:2; /* HW */
+ _UDWORD :4; /* */
+ _UDWORD WM:1; /* WM */
+ _UDWORD WR:4; /* WR */
+ _UDWORD SW:2; /* SW */
+ _UDWORD :3; /* */
+ _UDWORD WW:3; /* WW */
+ _UDWORD :1; /* */
+ _UDWORD MPXWBAS:1; /* MPXW/BAS */
+ _UDWORD SZSEL:1; /* SZSEL */
+ _UDWORD :10; /* */
+ } BIT; /* */
+ } NORMAL; /* */
+ } CS5WCR; /* */
+ _UBYTE wk1[12]; /* */
+ union { /* SDCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD A3COL:2; /* A3COL */
+ _UDWORD :1; /* */
+ _UDWORD A3ROW:2; /* A3ROW */
+ _UDWORD :3; /* */
+ _UDWORD BACTV:1; /* BACTV */
+ _UDWORD PDOWN:1; /* PDOWN */
+ _UDWORD RMODE:1; /* RMODE */
+ _UDWORD RFSH:1; /* RFSH */
+ _UDWORD :1; /* */
+ _UDWORD DEEP:1; /* DEEP */
+ _UDWORD :2; /* */
+ _UDWORD A2COL:2; /* A2COL */
+ _UDWORD :1; /* */
+ _UDWORD A2ROW:2; /* A2ROW */
+ _UDWORD :11; /* */
+ } BIT; /* */
+ } SDCR; /* */
+ union { /* RTCSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RRC:3; /* RRC */
+ _UDWORD CKS:3; /* CKS */
+ _UDWORD CMIE:1; /* CMIE */
+ _UDWORD CMF:1; /* CMF */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RTCSR; /* */
+ union { /* RTCNT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RTCNT; /* */
+ union { /* RTCOR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD D:32; /* D */
+ } BIT; /* */
+ } RTCOR; /* */
+ _UBYTE wk2[4]; /* */
+ TOSCORn TOSCOR0; /* TOSCOR0 */
+ TOSCORn TOSCOR1; /* TOSCOR1 */
+ TOSCORn TOSCOR2; /* TOSCOR2 */
+ TOSCORn TOSCOR3; /* TOSCOR3 */
+ TOSCORn TOSCOR4; /* TOSCOR4 */
+ TOSCORn TOSCOR5; /* TOSCOR5 */
+ _UBYTE wk3[8]; /* */
+ union { /* TOSTR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CS0TOSTF:1; /* CS0TOSTF */
+ _UDWORD CS1TOSTF:1; /* CS1TOSTF */
+ _UDWORD CS2TOSTF:1; /* CS2TOSTF */
+ _UDWORD CS3TOSTF:1; /* CS3TOSTF */
+ _UDWORD CS4TOSTF:1; /* CS4TOSTF */
+ _UDWORD CS5TOSTF:1; /* CS5TOSTF */
+ _UDWORD :26; /* */
+ } BIT; /* */
+ } TOSTR; /* */
+ union { /* TOENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CS0TOEN:1; /* CS0TOEN */
+ _UDWORD CS1TOEN:1; /* CS1TOEN */
+ _UDWORD CS2TOEN:1; /* CS2TOEN */
+ _UDWORD CS3TOEN:1; /* CS3TOEN */
+ _UDWORD CS4TOEN:1; /* CS4TOEN */
+ _UDWORD CS5TOEN:1; /* CS5TOEN */
+ _UDWORD :26; /* */
+ } BIT; /* */
+ } TOENR; /* */
+}; /* */
+
+#define BSC (*(volatile struct st_bsc *)0x3FFFC000) /* BSC Address */
+
+
+#endif /* __BSC_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/cpg_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/cpg_iodefine.h
new file mode 100644
index 000000000..1c4036202
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/cpg_iodefine.h
@@ -0,0 +1,463 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : cpg_iodefine.h
+* Version : 0.01
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* ARM Complier
+* :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program vecotr.s
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 27.07.2012 0.01 ŽQlŽ‘—¿FRZ_A1H_05J_121010_11.pdf
+*******************************************************************************/
+#ifndef __CPG_IODEFINE_H__
+#define __CPG_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_cpg { /* struct CPG */
+ union { /* FRQCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD IFC:2; /* IFC */
+ _UWORD :2; /* */
+ _UWORD CKOEN:2; /* CKOEN */
+ _UWORD CKOEN2:1; /* CKOEN2 */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } FRQCR; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* FRQCR2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD GFC:2; /* GFC */
+ _UWORD :14; /* */
+ } BIT; /* */
+ } FRQCR2; /* */
+ _UBYTE wk1[2]; /* */
+ union { /* CPUSTS */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :4; /* */
+ _UBYTE ISBUSY0:1; /* ISBUSY0 */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } CPUSTS; /* */
+ _UBYTE wk2[7]; /* */
+ union { /* STBCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE DEEP:1; /* DEEP */
+ _UBYTE STBY:1; /* STBY */
+ } BIT; /* */
+ } STBCR1; /* */
+ _UBYTE wk3[3]; /* */
+ union { /* STBCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP20:1; /* MSTP20 */
+ _UBYTE :6; /* */
+ _UBYTE HIZ:1; /* HIZ */
+ } BIT; /* */
+ } STBCR2; /* */
+ _UBYTE wk4[11]; /* */
+ union { /* STBREQ1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE STBRQ10:1; /* STBRQ10 */
+ _UBYTE :2; /* */
+ _UBYTE STBRQ13:1; /* STBRQ13 */
+ _UBYTE :1; /* */
+ _UBYTE STBRQ15:1; /* STBRQ15 */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } STBREQ1; /* */
+ _UBYTE wk5[3]; /* */
+ union { /* STBREQ2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE STBRQ20:1; /* STBRQ20 */
+ _UBYTE STBRQ21:1; /* STBRQ21 */
+ _UBYTE STBRQ22:1; /* STBRQ22 */
+ _UBYTE STBRQ23:1; /* STBRQ23 */
+ _UBYTE STBRQ24:1; /* STBRQ24 */
+ _UBYTE STBRQ25:1; /* STBRQ25 */
+ _UBYTE STBRQ26:1; /* STBRQ26 */
+ _UBYTE STBRQ27:1; /* STBRQ27 */
+ } BIT; /* */
+ } STBREQ2; /* */
+ _UBYTE wk6[11]; /* */
+ union { /* STBACK1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE STBAK10:1; /* STBAK10 */
+ _UBYTE :2; /* */
+ _UBYTE STBAK13:1; /* STBAK13 */
+ _UBYTE :1; /* */
+ _UBYTE STBAK15:1; /* STBAK15 */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } STBACK1; /* */
+ _UBYTE wk7[3]; /* */
+ union { /* STBACK2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE STBAK20:1; /* STBAK20 */
+ _UBYTE STBAK21:1; /* STBAK21 */
+ _UBYTE STBAK22:1; /* STBAK22 */
+ _UBYTE STBAK23:1; /* STBAK23 */
+ _UBYTE STBAK24:1; /* STBAK24 */
+ _UBYTE STBAK25:1; /* STBAK25 */
+ _UBYTE STBAK26:1; /* STBAK26 */
+ _UBYTE STBAK27:1; /* STBAK27 */
+ } BIT; /* */
+ } STBACK2; /* */
+ _UBYTE wk8[955]; /* */
+ union { /* SYSCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE VRAME0:1; /* VRAME0 */
+ _UBYTE VRAME1:1; /* VRAME1 */
+ _UBYTE VRAME2:1; /* VRAME2 */
+ _UBYTE VRAME3:1; /* VRAME3 */
+ _UBYTE VRAME4:1; /* VRAME4 */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } SYSCR1; /* */
+ _UBYTE wk9[3]; /* */
+ union { /* SYSCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE VRAMWE0:1; /* VRAMWE0 */
+ _UBYTE VRAMWE1:1; /* VRAMWE1 */
+ _UBYTE VRAMWE2:1; /* VRAMWE2 */
+ _UBYTE VRAMWE3:1; /* VRAMWE3 */
+ _UBYTE VRAMWE4:1; /* VRAMWE4 */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } SYSCR2; /* */
+ _UBYTE wk10[3]; /* */
+ union { /* SYSCR3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RRAMWE0:1; /* RRAMWE0 */
+ _UBYTE RRAMWE1:1; /* RRAMWE1 */
+ _UBYTE RRAMWE2:1; /* RRAMWE2 */
+ _UBYTE RRAMWE3:1; /* RRAMWE3 */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } SYSCR3; /* */
+ _UBYTE wk11[23]; /* */
+ union { /* STBCR3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP30:1; /* MSTP30 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP32:1; /* MSTP32 */
+ _UBYTE MSTP33:1; /* MSTP33 */
+ _UBYTE MSTP34:1; /* MSTP34 */
+ _UBYTE MSTP35:1; /* MSTP35 */
+ _UBYTE MSTP36:1; /* MSTP36 */
+ _UBYTE MSTP37:1; /* MSTP37 */
+ } BIT; /* */
+ } STBCR3; /* */
+ _UBYTE wk12[3]; /* */
+ union { /* STBCR4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP40:1; /* MSTP40 */
+ _UBYTE MSTP41:1; /* MSTP41 */
+ _UBYTE MSTP42:1; /* MSTP42 */
+ _UBYTE MSTP43:1; /* MSTP43 */
+ _UBYTE MSTP44:1; /* MSTP44 */
+ _UBYTE MSTP45:1; /* MSTP45 */
+ _UBYTE MSTP46:1; /* MSTP46 */
+ _UBYTE MSTP47:1; /* MSTP47 */
+ } BIT; /* */
+ } STBCR4; /* */
+ _UBYTE wk13[3]; /* */
+ union { /* STBCR5 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP50:1; /* MSTP50 */
+ _UBYTE MSTP51:1; /* MSTP51 */
+ _UBYTE MSTP52:1; /* MSTP52 */
+ _UBYTE MSTP53:1; /* MSTP53 */
+ _UBYTE MSTP54:1; /* MSTP54 */
+ _UBYTE MSTP55:1; /* MSTP55 */
+ _UBYTE MSTP56:1; /* MSTP56 */
+ _UBYTE MSTP57:1; /* MSTP57 */
+ } BIT; /* */
+ } STBCR5; /* */
+ _UBYTE wk14[3]; /* */
+ union { /* STBCR6 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP60:1; /* MSTP60 */
+ _UBYTE MSTP61:1; /* MSTP61 */
+ _UBYTE MSTP62:1; /* MSTP62 */
+ _UBYTE MSTP63:1; /* MSTP63 */
+ _UBYTE MSTP64:1; /* MSTP64 */
+ _UBYTE MSTP65:1; /* MSTP65 */
+ _UBYTE MSTP66:1; /* MSTP66 */
+ _UBYTE MSTP67:1; /* MSTP67 */
+ } BIT; /* */
+ } STBCR6; /* */
+ _UBYTE wk15[3]; /* */
+ union { /* STBCR7 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP70:1; /* MSTP70 */
+ _UBYTE MSTP71:1; /* MSTP71 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP73:1; /* MSTP73 */
+ _UBYTE MSTP74:1; /* MSTP74 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP76:1; /* MSTP76 */
+ _UBYTE MSTP77:1; /* MSTP77 */
+ } BIT; /* */
+ } STBCR7; /* */
+ _UBYTE wk16[3]; /* */
+ union { /* STBCR8 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE MSTP81:1; /* MSTP81 */
+ _UBYTE :1; /* */
+ _UBYTE MSTP83:1; /* MSTP83 */
+ _UBYTE MSTP84:1; /* MSTP84 */
+ _UBYTE MSTP85:1; /* MSTP85 */
+ _UBYTE MSTP86:1; /* MSTP86 */
+ _UBYTE MSTP87:1; /* MSTP87 */
+ } BIT; /* */
+ } STBCR8; /* */
+ _UBYTE wk17[3]; /* */
+ union { /* STBCR9 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP90:1; /* MSTP60 */
+ _UBYTE MSTP91:1; /* MSTP61 */
+ _UBYTE MSTP92:1; /* MSTP62 */
+ _UBYTE MSTP93:1; /* MSTP63 */
+ _UBYTE MSTP94:1; /* MSTP64 */
+ _UBYTE MSTP95:1; /* MSTP65 */
+ _UBYTE MSTP96:1; /* MSTP66 */
+ _UBYTE MSTP97:1; /* MSTP67 */
+ } BIT; /* */
+ } STBCR9; /* */
+ _UBYTE wk18[3]; /* */
+ union { /* STBCR10 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP100:1; /* MSTP100 */
+ _UBYTE MSTP101:1; /* MSTP101 */
+ _UBYTE MSTP102:1; /* MSTP102 */
+ _UBYTE MSTP103:1; /* MSTP103 */
+ _UBYTE MSTP104:1; /* MSTP104 */
+ _UBYTE MSTP105:1; /* MSTP105 */
+ _UBYTE MSTP106:1; /* MSTP106 */
+ _UBYTE MSTP107:1; /* MSTP107 */
+ } BIT; /* */
+ } STBCR10; /* */
+ _UBYTE wk19[3]; /* */
+ union { /* STBCR11 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP110:1; /* MSTP110 */
+ _UBYTE MSTP111:1; /* MSTP111 */
+ _UBYTE MSTP112:1; /* MSTP112 */
+ _UBYTE MSTP113:1; /* MSTP113 */
+ _UBYTE MSTP114:1; /* MSTP114 */
+ _UBYTE MSTP115:1; /* MSTP115 */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } STBCR11; /* */
+ _UBYTE wk20[3]; /* */
+ union { /* STBCR12 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MSTP120:1; /* MSTP120 */
+ _UBYTE MSTP121:1; /* MSTP121 */
+ _UBYTE MSTP122:1; /* MSTP122 */
+ _UBYTE MSTP123:1; /* MSTP123 */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } STBCR12; /* */
+ _UBYTE wk21[27]; /* */
+ union { /* SWRSTCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE SRST11:1; /* SRST11 */
+ _UBYTE SRST12:1; /* SRST12 */
+ _UBYTE SRST13:1; /* SRST13 */
+ _UBYTE SRST14:1; /* SRST14 */
+ _UBYTE SRST15:1; /* SRST15 */
+ _UBYTE SRST16:1; /* SRST16 */
+ _UBYTE AXTALE:1; /* AXTALE */
+ } BIT; /* */
+ } SWRSTCR1; /* */
+ _UBYTE wk22[3]; /* */
+ union { /* SWRSTCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE SRST21:1; /* SRST21 */
+ _UBYTE SRST22:1; /* SRST22 */
+ _UBYTE SRST23:1; /* SRST23 */
+ _UBYTE SRST24:1; /* SRST24 */
+ _UBYTE SRST25:1; /* SRST25 */
+ _UBYTE SRST26:1; /* SRST26 */
+ _UBYTE SRST27:1; /* SRST27 */
+ } BIT; /* */
+ } SWRSTCR2; /* */
+ _UBYTE wk23[3]; /* */
+ union { /* SWRSTCR3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :1; /* */
+ _UBYTE SRST31:1; /* SRST31 */
+ _UBYTE SRST32:1; /* SRST32 */
+ _UBYTE SRST33:1; /* SRST33 */
+ _UBYTE SRST34:1; /* SRST34 */
+ _UBYTE SRST35:1; /* SRST35 */
+ _UBYTE SRST36:1; /* SRST36 */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } SWRSTCR3; /* */
+ _UBYTE wk24[3]; /* */
+ union { /* SWRSTCR4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SRST40:1; /* SRST40 */
+ _UBYTE SRST41:1; /* SRST41 */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } SWRSTCR4; /* */
+ _UBYTE wk25[70547]; /* */
+ union { /* RRAMKP */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RRAMKP0:1; /* RRAMKP0 */
+ _UBYTE RRAMKP1:1; /* RRAMKP1 */
+ _UBYTE RRAMKP2:1; /* RRAMKP2 */
+ _UBYTE RRAMKP3:1; /* RRAMKP3 */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } RRAMKP; /* */
+ _UBYTE wk26[1]; /* */
+ union { /* DSCTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE :6; /* */
+ _UBYTE RAMBOOT:1; /* RAMBOOT */
+ _UBYTE EBUSKEEPE:1; /* EBUSKEEPE */
+ } BIT; /* */
+ } DSCTR; /* */
+ _UBYTE wk27[1]; /* */
+ union { /* DSSSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD P8_2:1; /* P8_2 */
+ _UWORD P9_1:1; /* P9_1 */
+ _UWORD P2_15:1; /* P2_15 */
+ _UWORD P7_8:1; /* P7_8 */
+ _UWORD P5_9:1; /* P5_9 */
+ _UWORD P6_4:1; /* P6_4 */
+ _UWORD RTCAR:1; /* RTCAR */
+ _UWORD :1; /* */
+ _UWORD NMI:1; /* NMI */
+ _UWORD P3_3:1; /* P3_3 */
+ _UWORD P8_7:1; /* P8_7 */
+ _UWORD P2_12:1; /* P2_12 */
+ _UWORD P3_1:1; /* P3_1 */
+ _UWORD P3_9:1; /* P3_9 */
+ _UWORD P6_2:1; /* P6_2 */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DSSSR; /* */
+ union { /* DSESR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD P8_2E:1; /* P8_2E */
+ _UWORD P9_1E:1; /* P9_1E */
+ _UWORD P2_15E:1; /* P2_15E */
+ _UWORD P7_8E:1; /* P7_8E */
+ _UWORD P5_9E:1; /* P5_9E */
+ _UWORD P6_4E:1; /* P6_4E */
+ _UWORD :2; /* */
+ _UWORD NMIE:1; /* NMIE */
+ _UWORD P3_3E:1; /* P3_3E */
+ _UWORD P8_7E:1; /* P8_7E */
+ _UWORD P2_12E:1; /* P2_12E */
+ _UWORD P3_1E:1; /* P3_1E */
+ _UWORD P3_9E:1; /* P3_9E */
+ _UWORD P6_2E:1; /* P6_2E */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DSESR; /* */
+ union { /* DSFR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD P8_2F:1; /* P8_2F */
+ _UWORD P9_1F:1; /* P9_1F */
+ _UWORD P2_15F:1; /* P2_15F */
+ _UWORD P7_8F:1; /* P7_8F */
+ _UWORD P5_9F:1; /* P5_9F */
+ _UWORD P6_4F:1; /* P6_4F */
+ _UWORD RTCARF:1; /* RTCARF */
+ _UWORD :1; /* */
+ _UWORD NMIF:1; /* NMIF */
+ _UWORD P3_3F:1; /* P3_3F */
+ _UWORD P8_7F:1; /* P8_7F */
+ _UWORD P2_12F:1; /* P2_12F */
+ _UWORD P3_1F:1; /* P3_1F */
+ _UWORD P3_9F:1; /* P3_9F */
+ _UWORD P6_2F:1; /* P6_2F */
+ _UWORD IOKEEP:1; /* IOKEEP */
+ } BIT; /* */
+ } DSFR; /* */
+ _UBYTE wk28[6]; /* */
+ union { /* XTALCTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE GAIN0:1; /* GAIN0 */
+ _UBYTE GAIN1:1; /* GAIN1 */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } XTALCTR; /* */
+}; /* */
+
+#define CPG (*(volatile struct st_cpg *)0xFCFE0010) /* CPG Address */
+
+
+#endif /* __CPG_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/dmac_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/dmac_iodefine.h
new file mode 100644
index 000000000..52050e34b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/dmac_iodefine.h
@@ -0,0 +1,510 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name :
+* File Name : dmac_iodefine.h
+* Abstract :
+* Version : 1.00.00
+* Device : ARM
+* Tool-Chain :
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : Mar.06,2012 Ver.1.00.00
+*******************************************************************************/
+#ifndef __DMAC_IODEFINE_H__
+#define __DMAC_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_dmac_n { /* struct DMAC */
+ union { /* N0SA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SA:32; /* SA */
+ } BIT; /* */
+ } N0SA; /* */
+ union { /* N0DA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DA:32; /* DA */
+ } BIT; /* */
+ } N0DA; /* */
+ union { /* N0TB */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TB:32; /* TB */
+ } BIT; /* */
+ } N0TB; /* */
+ union { /* N1SA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SA:32; /* SA */
+ } BIT; /* */
+ } N1SA; /* */
+ union { /* N1DA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DA:32; /* DA */
+ } BIT; /* */
+ } N1DA; /* */
+ union { /* N1TB */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TB:32; /* TB */
+ } BIT; /* */
+ } N1TB; /* */
+ union { /* CRSA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CRSA:32; /* CRSA */
+ } BIT; /* */
+ } CRSA; /* */
+ union { /* CRDA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CRDA:32; /* CRDA */
+ } BIT; /* */
+ } CRDA; /* */
+ union { /* CRTB */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CRTB:32; /* CRTB */
+ } BIT; /* */
+ } CRTB; /* */
+ union { /* CHSTAT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EN:1; /* EN */
+ _UDWORD RQST:1; /* RQST */
+ _UDWORD TACT:1; /* TACT */
+ _UDWORD SUS:1; /* SUS */
+ _UDWORD ER:1; /* ER */
+ _UDWORD END:1; /* END */
+ _UDWORD TC:1; /* TC */
+ _UDWORD SR:1; /* SR */
+ _UDWORD DL:1; /* DL */
+ _UDWORD DW:1; /* DW */
+ _UDWORD DER:1; /* DER */
+ _UDWORD MODE:1; /* MODE */
+ _UWORD :4; /* */
+ _UDWORD INTMSK:1; /* INTMSK */
+ _UWORD :15; /* */
+ } BIT; /* */
+ } CHSTAT; /* */
+ union { /* CHCTRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SETEN:1; /* SETEN */
+ _UDWORD CLREN:1; /* CLREN */
+ _UDWORD STG:1; /* STG */
+ _UDWORD SWRST:1; /* SWRST */
+ _UDWORD CLRRQ:1; /* CLRRQ */
+ _UDWORD CLREND:1; /* CLREND */
+ _UDWORD CLRTC:1; /* CLRTC */
+ _UWORD :1; /* */
+ _UDWORD SETSUS:1; /* SETSUS */
+ _UDWORD CLRSUS:1; /* CLRSUS */
+ _UWORD :6; /* */
+ _UDWORD SETINTMSK:1; /* SETINTMSK */
+ _UDWORD CLRINTMSK:1; /* CLRINTMSK */
+ _UWORD :14; /* */
+ } BIT; /* */
+ } CHCTRL; /* */
+ union { /* CHCFG */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SEL:3; /* SEL */
+ _UDWORD REQD:1; /* REQD */
+ _UDWORD LOEN:1; /* LOEN */
+ _UDWORD HIEN:1; /* HIEN */
+ _UDWORD LVL:1; /* LVL */
+ _UWORD :1; /* */
+ _UDWORD AM:3; /* AM */
+ _UWORD :1; /* */
+ _UDWORD SDS:4; /* SDS */
+ _UDWORD DDS:4; /* DDS */
+ _UDWORD SAD:1; /* SAD */
+ _UDWORD DAD:1; /* DAD */
+ _UDWORD TM:1; /* TM */
+ _UWORD :1; /* */
+ _UDWORD DEM:1; /* DEM */
+ _UDWORD TCM:1; /* TCM */
+ _UWORD :1; /* */
+ _UDWORD SBE:1; /* SBE */
+ _UDWORD RSEL:1; /* RSEL */
+ _UDWORD RSW:1; /* RSW */
+ _UDWORD REN:1; /* REN */
+ _UDWORD DMS:1; /* DMS */
+ } BIT; /* */
+ } CHCFG; /* */
+ union { /* CHITVL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ITVL:16; /* ITVL */
+ _UWORD :16; /* */
+ } BIT; /* */
+ } CHITVL; /* */
+ union { /* CHEXT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UDWORD SCA:4; /* SCA */
+ _UWORD :4; /* */
+ _UDWORD DCA:4; /* DCA */
+ _UWORD :16; /* */
+ } CHEXT; /* */
+ } CHEXT; /* */
+ union { /* NXLA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD NXLA:32; /* NXLA */
+ } BIT; /* */
+ } NXLA; /* */
+ union { /* CRLA */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CRLA:32; /* CRLA */
+ } BIT; /* */
+ } CRLA; /* */
+}; /* */
+
+struct st_dmac_07 { /* struct DMAC */
+ union { /* DCTRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PR:1; /* PR */
+ _UDWORD LVINT:1; /* LVINT */
+ _UWORD :18; /* */
+ _UDWORD LDCA:4; /* LDCA */
+ _UWORD :4; /* */
+ _UDWORD LWCA:4; /* LWCA */
+ } BIT; /* */
+ } DCTRL; /* */
+ union { /* DSTAT_EN */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EN0:1; /* EN0 */
+ _UDWORD EN1:1; /* EN1 */
+ _UDWORD EN2:1; /* EN2 */
+ _UDWORD EN3:1; /* EN3 */
+ _UDWORD EN4:1; /* EN4 */
+ _UDWORD EN5:1; /* EN5 */
+ _UDWORD EN6:1; /* EN6 */
+ _UDWORD EN7:1; /* EN7 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_EN; /* */
+ union { /* DSTAT_ER */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ER0:1; /* ER0 */
+ _UDWORD ER1:1; /* ER1 */
+ _UDWORD ER2:1; /* ER2 */
+ _UDWORD ER3:1; /* ER3 */
+ _UDWORD ER4:1; /* ER4 */
+ _UDWORD ER5:1; /* ER5 */
+ _UDWORD ER6:1; /* ER6 */
+ _UDWORD ER7:1; /* ER7 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_ER; /* */
+ union { /* DSTAT_END */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD END0:1; /* END0 */
+ _UDWORD END1:1; /* END1 */
+ _UDWORD END2:1; /* END2 */
+ _UDWORD END3:1; /* END3 */
+ _UDWORD END4:1; /* END4 */
+ _UDWORD END5:1; /* END5 */
+ _UDWORD END6:1; /* END6 */
+ _UDWORD END7:1; /* END7 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_END; /* */
+ union { /* DSTAT_TC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TC0:1; /* TC0 */
+ _UDWORD TC1:1; /* TC1 */
+ _UDWORD TC2:1; /* TC2 */
+ _UDWORD TC3:1; /* TC3 */
+ _UDWORD TC4:1; /* TC4 */
+ _UDWORD TC5:1; /* TC5 */
+ _UDWORD TC6:1; /* TC6 */
+ _UDWORD TC7:1; /* TC7 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_TC; /* */
+ union { /* DSTAT_SUS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SUS0:1; /* SUS0 */
+ _UDWORD SUS1:1; /* SUS1 */
+ _UDWORD SUS2:1; /* SUS2 */
+ _UDWORD SUS3:1; /* SUS3 */
+ _UDWORD SUS4:1; /* SUS4 */
+ _UDWORD SUS5:1; /* SUS5 */
+ _UDWORD SUS6:1; /* SUS6 */
+ _UDWORD SUS7:1; /* SUS7 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_SUS; /* */
+}; /* */
+
+struct st_dmac_815 { /* struct DMAC */
+ union { /* DCTRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PR:1; /* PR */
+ _UDWORD LVINT:1; /* LVINT */
+ _UWORD :18; /* */
+ _UDWORD LDCA:4; /* LDCA */
+ _UWORD :4; /* */
+ _UDWORD LWCA:4; /* LWCA */
+ } BIT; /* */
+ } DCTRL; /* */
+ union { /* DSTAT_EN */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EN8:1; /* EN8 */
+ _UDWORD EN9:1; /* EN9 */
+ _UDWORD EN10:1; /* EN10 */
+ _UDWORD EN11:1; /* EN11 */
+ _UDWORD EN12:1; /* EN12 */
+ _UDWORD EN13:1; /* EN13 */
+ _UDWORD EN14:1; /* EN14 */
+ _UDWORD EN15:1; /* EN15 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_EN; /* */
+ union { /* DSTAT_ER */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ER8:1; /* ER8 */
+ _UDWORD ER9:1; /* ER9 */
+ _UDWORD ER10:1; /* ER10 */
+ _UDWORD ER11:1; /* ER11 */
+ _UDWORD ER12:1; /* ER12 */
+ _UDWORD ER13:1; /* ER13 */
+ _UDWORD ER14:1; /* ER14 */
+ _UDWORD ER15:1; /* ER15 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_ER; /* */
+ union { /* DSTAT_END */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD END8:1; /* END8 */
+ _UDWORD END9:1; /* END9 */
+ _UDWORD END10:1; /* END10 */
+ _UDWORD END11:1; /* END11 */
+ _UDWORD END12:1; /* END12 */
+ _UDWORD END13:1; /* END13 */
+ _UDWORD END14:1; /* END14 */
+ _UDWORD END15:1; /* END15 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_END; /* */
+ union { /* DSTAT_TC */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TC8:1; /* TC8 */
+ _UDWORD TC9:1; /* TC9 */
+ _UDWORD TC10:1; /* TC10 */
+ _UDWORD TC11:1; /* TC11 */
+ _UDWORD TC12:1; /* TC12 */
+ _UDWORD TC13:1; /* TC13 */
+ _UDWORD TC14:1; /* TC14 */
+ _UDWORD TC15:1; /* TC15 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_TC; /* */
+ union { /* DSTAT_SUS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SUS8:1; /* SUS8 */
+ _UDWORD SUS9:1; /* SUS9 */
+ _UDWORD SUS10:1; /* SUS10 */
+ _UDWORD SUS11:1; /* SUS11 */
+ _UDWORD SUS12:1; /* SUS12 */
+ _UDWORD SUS13:1; /* SUS13 */
+ _UDWORD SUS14:1; /* SUS14 */
+ _UDWORD SUS15:1; /* SUS15 */
+ _UWORD :24; /* */
+ } BIT; /* */
+ } DSTAT_SUS; /* */
+}; /* */
+
+struct st_dmac_01 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH0_RID:2; /* CH0_RID */
+ _UDWORD CH0_MID:7; /* CH0_MID */
+ _UWORD :7; /* */
+ _UDWORD CH1_RID:2; /* CH1_RID */
+ _UDWORD CH1_MID:7; /* CH1_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_23 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH2_RID:2; /* CH2_RID */
+ _UDWORD CH2_MID:7; /* CH2_MID */
+ _UWORD :7; /* */
+ _UDWORD CH3_RID:2; /* CH3_RID */
+ _UDWORD CH3_MID:7; /* CH3_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_45 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH4_RID:2; /* CH4_RID */
+ _UDWORD CH4_MID:7; /* CH4_MID */
+ _UWORD :7; /* */
+ _UDWORD CH5_RID:2; /* CH5_RID */
+ _UDWORD CH5_MID:7; /* CH5_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_67 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH6_RID:2; /* CH6_RID */
+ _UDWORD CH6_MID:7; /* CH6_MID */
+ _UWORD :7; /* */
+ _UDWORD CH7_RID:2; /* CH7_RID */
+ _UDWORD CH7_MID:7; /* CH7_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_89 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH8_RID:2; /* CH8_RID */
+ _UDWORD CH8_MID:7; /* CH8_MID */
+ _UWORD :7; /* */
+ _UDWORD CH9_RID:2; /* CH9_RID */
+ _UDWORD CH9_MID:7; /* CH9_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_1011 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH10_RID:2; /* CH10_RID */
+ _UDWORD CH10_MID:7; /* CH10_MID */
+ _UWORD :7; /* */
+ _UDWORD CH11_RID:2; /* CH11_RID */
+ _UDWORD CH11_MID:7; /* CH11_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_1213 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH12_RID:2; /* CH12_RID */
+ _UDWORD CH12_MID:7; /* CH12_MID */
+ _UWORD :7; /* */
+ _UDWORD CH13_RID:2; /* CH13_RID */
+ _UDWORD CH13_MID:7; /* CH13_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+struct st_dmac_1415 { /* struct DMAC */
+ union { /* DMARS */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CH14_RID:2; /* CH14_RID */
+ _UDWORD CH14_MID:7; /* CH14_MID */
+ _UWORD :7; /* */
+ _UDWORD CH15_RID:2; /* CH15_RID */
+ _UDWORD CH15_MID:7; /* CH15_MID */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DMARS; /* */
+}; /* */
+
+#define DMAC0 (*(volatile struct st_dmac_n *)0xE8200000) /* DMAC0 Address */
+#define DMAC1 (*(volatile struct st_dmac_n *)0xE8200040) /* DMAC1 Address */
+#define DMAC2 (*(volatile struct st_dmac_n *)0xE8200080) /* DMAC2 Address */
+#define DMAC3 (*(volatile struct st_dmac_n *)0xE82000C0) /* DMAC3 Address */
+#define DMAC4 (*(volatile struct st_dmac_n *)0xE8200100) /* DMAC4 Address */
+#define DMAC5 (*(volatile struct st_dmac_n *)0xE8200140) /* DMAC5 Address */
+#define DMAC6 (*(volatile struct st_dmac_n *)0xE8200180) /* DMAC6 Address */
+#define DMAC7 (*(volatile struct st_dmac_n *)0xE82001C0) /* DMAC7 Address */
+#define DMAC8 (*(volatile struct st_dmac_n *)0xE8200400) /* DMAC8 Address */
+#define DMAC9 (*(volatile struct st_dmac_n *)0xE8200440) /* DMAC9 Address */
+#define DMAC10 (*(volatile struct st_dmac_n *)0xE8200480) /* DMAC10 Address */
+#define DMAC11 (*(volatile struct st_dmac_n *)0xE82004C0) /* DMAC11 Address */
+#define DMAC12 (*(volatile struct st_dmac_n *)0xE8200500) /* DMAC12 Address */
+#define DMAC13 (*(volatile struct st_dmac_n *)0xE8200540) /* DMAC13 Address */
+#define DMAC14 (*(volatile struct st_dmac_n *)0xE8200580) /* DMAC14 Address */
+#define DMAC15 (*(volatile struct st_dmac_n *)0xE82005C0) /* DMAC15 Address */
+
+#define DMAC07 (*(volatile struct st_dmac_07 *)0xE8200300) /* DMAC0-7 Address */
+#define DMAC815 (*(volatile struct st_dmac_815 *)0xE8200700) /* DMAC8-15 Address */
+
+#define DMAC01 (*(volatile struct st_dmac_01 *)0xFCFE1000) /* DMAC0-1 Address */
+#define DMAC23 (*(volatile struct st_dmac_23 *)0xFCFE1004) /* DMAC2-3 Address */
+#define DMAC45 (*(volatile struct st_dmac_45 *)0xFCFE1008) /* DMAC4-5 Address */
+#define DMAC67 (*(volatile struct st_dmac_67 *)0xFCFE100C) /* DMAC6-7 Address */
+#define DMAC89 (*(volatile struct st_dmac_89 *)0xFCFE1010) /* DMAC8-9 Address */
+#define DMAC1011 (*(volatile struct st_dmac_1011 *)0xFCFE1014) /* DMAC10-11 Address */
+#define DMAC1213 (*(volatile struct st_dmac_1213 *)0xFCFE1018) /* DMAC12-13 Address */
+#define DMAC1415 (*(volatile struct st_dmac_1415 *)0xFCFE101C) /* DMAC14-15 Address */
+
+#endif /* __DMAC_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/intc_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/intc_iodefine.h
new file mode 100644
index 000000000..2e6151b94
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/intc_iodefine.h
@@ -0,0 +1,4639 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_iodefine.h
+* Version : 0.01
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.13
+* ARM Complier
+* :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program vecotr.s
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+*******************************************************************************/
+#ifndef __INTC_IODEFINE_H__
+#define __INTC_IODEFINE_H__
+
+#include "typedefine.h"
+
+typedef union { /* ICDxxx0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW0:1; /* SW0 */
+ _UDWORD SW1:1; /* SW1 */
+ _UDWORD SW2:1; /* SW2 */
+ _UDWORD SW3:1; /* SW3 */
+ _UDWORD SW4:1; /* SW4 */
+ _UDWORD SW5:1; /* SW5 */
+ _UDWORD SW6:1; /* SW6 */
+ _UDWORD SW7:1; /* SW7 */
+ _UDWORD SW8:1; /* SW8 */
+ _UDWORD SW9:1; /* SW9 */
+ _UDWORD SW10:1; /* SW10 */
+ _UDWORD SW11:1; /* SW11 */
+ _UDWORD SW12:1; /* SW12 */
+ _UDWORD SW13:1; /* SW13 */
+ _UDWORD SW14:1; /* SW14 */
+ _UDWORD SW15:1; /* SW15 */
+ _UDWORD PMUIRQ0:1; /* PMUIRQ0 */
+ _UDWORD COMMRX0:1; /* COMMRX0 */
+ _UDWORD COMMTX0:1; /* COMMTX0 */
+ _UDWORD CTIIRQ0:1; /* CTIIRQ0 */
+ _UDWORD :12; /* */
+ } BIT; /* */
+} ICDxxx0; /* */
+typedef union { /* ICDxxx1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IRQ0:1; /* IRQ0 */
+ _UDWORD IRQ1:1; /* IRQ1 */
+ _UDWORD IRQ2:1; /* IRQ2 */
+ _UDWORD IRQ3:1; /* IRQ3 */
+ _UDWORD IRQ4:1; /* IRQ4 */
+ _UDWORD IRQ5:1; /* IRQ5 */
+ _UDWORD IRQ6:1; /* IRQ6 */
+ _UDWORD IRQ7:1; /* IRQ7 */
+ _UDWORD PL310ERR:1; /* PL310ERR */
+ _UDWORD DMAINT0:1; /* DMAINT0 */
+ _UDWORD DMAINT1:1; /* DMAINT1 */
+ _UDWORD DMAINT2:1; /* DMAINT2 */
+ _UDWORD DMAINT3:1; /* DMAINT3 */
+ _UDWORD DMAINT4:1; /* DMAINT4 */
+ _UDWORD DMAINT5:1; /* DMAINT5 */
+ _UDWORD DMAINT6:1; /* DMAINT6 */
+ _UDWORD DMAINT7:1; /* DMAINT7 */
+ _UDWORD DMAINT8:1; /* DMAINT8 */
+ _UDWORD DMAINT9:1; /* DMAINT9 */
+ _UDWORD DMAINT10:1; /* DMAINT10 */
+ _UDWORD DMAINT11:1; /* DMAINT11 */
+ _UDWORD DMAINT12:1; /* DMAINT12 */
+ _UDWORD DMAINT13:1; /* DMAINT13 */
+ _UDWORD DMAINT14:1; /* DMAINT14 */
+ _UDWORD DMAINT15:1; /* DMAINT15 */
+ _UDWORD DMAERR:1; /* DMAERR */
+ _UDWORD :6; /* */
+ } BIT; /* */
+} ICDxxx1; /* */
+typedef union { /* ICDxxx2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :9; /* */
+ _UDWORD USBI0:1; /* USBI0 */
+ _UDWORD USBI1:1; /* USBI1 */
+ _UDWORD S0_VI_VSYNC0:1; /* S0_VI_VSYNC0 */
+ _UDWORD S0_LO_VSYNC0:1; /* S0_LO_VSYNC0 */
+ _UDWORD S0_VSYNCERR0:1; /* S0_VSYNCERR0 */
+ _UDWORD GR3_VLINE0:1; /* GR3_VLINE0 */
+ _UDWORD S0_VFIELD0:1; /* S0_VFIELD0 */
+ _UDWORD IV1_VBUFERR0:1; /* IV1_VBUFERR0 */
+ _UDWORD IV3_VBUFERR0:1; /* IV3_VBUFERR0 */
+ _UDWORD IV5_VBUFERR0:1; /* IV5_VBUFERR0 */
+ _UDWORD IV6_VBUFERR0:1; /* IV6_VBUFERR0 */
+ _UDWORD S0_WLINE0:1; /* S0_WLINE0 */
+ _UDWORD S1_VI_VSYNC0:1; /* S1_VI_VSYNC0 */
+ _UDWORD S1_LO_VSYNC0:1; /* S1_LO_VSYNC0 */
+ _UDWORD S1_VSYNCERR0:1; /* S1_VSYNCERR0 */
+ _UDWORD S1_VFIELD0:1; /* S1_VFIELD0 */
+ _UDWORD IV2_VBUFERR0:1; /* IV2_VBUFERR0 */
+ _UDWORD IV4_VBUFERR0:1; /* IV4_VBUFERR0 */
+ _UDWORD S1_WLINE0:1; /* S1_WLINE0 */
+ _UDWORD OIR_VI_VSYNC0:1; /* OIR_VI_VSYNC0 */
+ _UDWORD OIR_LO_VSYNC0:1; /* OIR_LO_VSYNC0 */
+ _UDWORD OIR_VSYNCERR0:1; /* OIR_VSYNCERR0 */
+ _UDWORD OIR_VFIELD0:1; /* OIR_VFIELD0 */
+ } BIT; /* */
+} ICDxxx2; /* */
+typedef union { /* ICDxxx3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV7_VBUFERR0:1; /* IV7_VBUFERR0 */
+ _UDWORD IV8_VBUFERR0:1; /* IV8_VBUFERR0 */
+ _UDWORD OIR_WLINE0:1; /* OIR_WLINE0 */
+ _UDWORD S0_VI_VSYNC1:1; /* S0_VI_VSYNC1 */
+ _UDWORD S0_LO_VSYNC1:1; /* S0_LO_VSYNC1 */
+ _UDWORD S0_VSYNCERR1:1; /* S0_VSYNCERR1 */
+ _UDWORD GR3_VLINE1:1; /* GR3_VLINE1 */
+ _UDWORD S0_VFIELD1:1; /* S0_VFIELD1 */
+ _UDWORD IV1_VBUFERR1:1; /* IV1_VBUFERR1 */
+ _UDWORD IV3_VBUFERR1:1; /* IV3_VBUFERR1 */
+ _UDWORD IV5_VBUFERR1:1; /* IV5_VBUFERR1 */
+ _UDWORD IV6_VBUFERR1:1; /* IV6_VBUFERR1 */
+ _UDWORD S0_WLINE1:1; /* S0_WLINE1 */
+ _UDWORD S1_VI_VSYNC1:1; /* S1_VI_VSYNC1 */
+ _UDWORD S1_LO_VSYNC1:1; /* S1_LO_VSYNC1 */
+ _UDWORD S1_VSYNCERR1:1; /* S1_VSYNCERR1 */
+ _UDWORD S1_VFIELD1:1; /* S1_VFIELD1 */
+ _UDWORD IV2_VBUFERR1:1; /* IV2_VBUFERR1 */
+ _UDWORD IV4_VBUFERR1:1; /* IV4_VBUFERR1 */
+ _UDWORD S1_WLINE1:1; /* S1_WLINE1 */
+ _UDWORD OIR_VI_VSYNC1:1; /* OIR_VI_VSYNC1 */
+ _UDWORD OIR_LO_VSYNC1:1; /* OIR_LO_VSYNC1 */
+ _UDWORD OIR_VLINE1:1; /* OIR_VLINE1 */
+ _UDWORD OIR_VFIELD1:1; /* OIR_VFIELD1 */
+ _UDWORD IV7_VBUFERR1:1; /* IV7_VBUFERR1 */
+ _UDWORD IV8_VBUFERR1:1; /* IV8_VBUFERR1 */
+ _UDWORD OIR_WLINE1:1; /* OIR_WLINE1 */
+ _UDWORD IMRDI:1; /* IMRDI */
+ _UDWORD IMR2I0:1; /* IMR2I0 */
+ _UDWORD IMR2I1:1; /* IMR2I1 */
+ _UDWORD JEDI:1; /* JEDI */
+ _UDWORD JDTI:1; /* JDTI */
+ } BIT; /* */
+} ICDxxx3; /* */
+typedef union { /* ICDxxx4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMP0:1; /* CMP0 */
+ _UDWORD CMP1:1; /* CMP1 */
+ _UDWORD INT0:1; /* INT0 */
+ _UDWORD INT1:1; /* INT1 */
+ _UDWORD INT2:1; /* INT2 */
+ _UDWORD INT3:1; /* INT3 */
+ _UDWORD OSTMI0:1; /* OSTMI0 */
+ _UDWORD OSTMI1:1; /* OSTMI1 */
+ _UDWORD CMI:1; /* CMI */
+ _UDWORD WTOUT:1; /* WTOUT */
+ _UDWORD ITI:1; /* ITI */
+ _UDWORD TGI0A:1; /* TGI0A */
+ _UDWORD TGI0B:1; /* TGI0B */
+ _UDWORD TGI0C:1; /* TGI0C */
+ _UDWORD TGI0D:1; /* TGI0D */
+ _UDWORD TGI0V:1; /* TGI0V */
+ _UDWORD TGI0E:1; /* TGI0E */
+ _UDWORD TGI0F:1; /* TGI0F */
+ _UDWORD TGI1A:1; /* TGI1A */
+ _UDWORD TGI1B:1; /* TGI1B */
+ _UDWORD TGI1V:1; /* TGI1V */
+ _UDWORD TGI1U:1; /* TGI1U */
+ _UDWORD TGI2A:1; /* TGI2A */
+ _UDWORD TGI2B:1; /* TGI2B */
+ _UDWORD TGI2V:1; /* TGI2V */
+ _UDWORD TGI2U:1; /* TGI2U */
+ _UDWORD TGI3A:1; /* TGI3A */
+ _UDWORD TGI3B:1; /* TGI3B */
+ _UDWORD TGI3C:1; /* TGI3C */
+ _UDWORD TGI3D:1; /* TGI3D */
+ _UDWORD TGI3V:1; /* TGI3V */
+ _UDWORD TGI4A:1; /* TGI4A */
+ } BIT; /* */
+} ICDxxx4; /* */
+typedef union { /* ICDxxx5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI4B:1; /* TGI4B */
+ _UDWORD TGI4C:1; /* TGI4C */
+ _UDWORD TGI4D:1; /* TGI4D */
+ _UDWORD TGI4V:1; /* TGI4V */
+ _UDWORD CMI1:1; /* CMI1 */
+ _UDWORD CMI2:1; /* CMI2 */
+ _UDWORD SGDEI0:1; /* SGDEI0 */
+ _UDWORD SGDEI1:1; /* SGDEI1 */
+ _UDWORD SGDEI2:1; /* SGDEI2 */
+ _UDWORD SGDEI3:1; /* SGDEI3 */
+ _UDWORD ADI:1; /* ADI */
+ _UDWORD ADWAR:1; /* ADWAR */
+ _UDWORD SSII0:1; /* SSII0 */
+ _UDWORD SSIRXI0:1; /* SSIRXI0 */
+ _UDWORD SSITXI0:1; /* SSITXI0 */
+ _UDWORD SSII1:1; /* SSII1 */
+ _UDWORD SSIRXI1:1; /* SSIRXI1 */
+ _UDWORD SSITXI1:1; /* SSITXI1 */
+ _UDWORD SSII2:1; /* SSII2 */
+ _UDWORD SSIRTI2:1; /* SSIRTI2 */
+ _UDWORD SSII3:1; /* SSII3 */
+ _UDWORD SSIRXI3:1; /* SSIRXI3 */
+ _UDWORD SSITXI3:1; /* SSITXI3 */
+ _UDWORD SSII4:1; /* SSII4 */
+ _UDWORD SSIRTI4:1; /* SSIRTI4 */
+ _UDWORD SSII5:1; /* SSII5 */
+ _UDWORD SSIRXI5:1; /* SSIRXI5 */
+ _UDWORD SSITXI5:1; /* SSITXI5 */
+ _UDWORD SPDIFI:1; /* SPDIFI */
+ _UDWORD TEI0:1; /* TEI0 */
+ _UDWORD RI0:1; /* RI0 */
+ _UDWORD TI0:1; /* TI0 */
+ } BIT; /* */
+} ICDxxx5; /* */
+typedef union { /* ICDxxx6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI0:1; /* SPI0 */
+ _UDWORD STI0:1; /* STI0 */
+ _UDWORD NAKI0:1; /* NAKI0 */
+ _UDWORD ALI0:1; /* ALI0 */
+ _UDWORD TMOI0:1; /* TMOI0 */
+ _UDWORD TEI1:1; /* TEI1 */
+ _UDWORD RI1:1; /* RI1 */
+ _UDWORD TI1:1; /* TI1 */
+ _UDWORD SPI1:1; /* SPI1 */
+ _UDWORD STI1:1; /* STI1 */
+ _UDWORD NAKI1:1; /* NAKI1 */
+ _UDWORD ALI1:1; /* ALI1 */
+ _UDWORD TMOI1:1; /* TMOI1 */
+ _UDWORD TEI2:1; /* TEI2 */
+ _UDWORD RI2:1; /* RI2 */
+ _UDWORD TI2:1; /* TI2 */
+ _UDWORD SPI2:1; /* SPI2 */
+ _UDWORD STI2:1; /* STI2 */
+ _UDWORD NAKI2:1; /* NAKI2 */
+ _UDWORD ALI2:1; /* ALI2 */
+ _UDWORD TMOI2:1; /* TMOI2 */
+ _UDWORD TEI3:1; /* TEI3 */
+ _UDWORD RI3:1; /* RI3 */
+ _UDWORD TI3:1; /* TI3 */
+ _UDWORD SPI3:1; /* SPI3 */
+ _UDWORD STI3:1; /* STI3 */
+ _UDWORD NAKI3:1; /* NAKI3 */
+ _UDWORD ALI3:1; /* ALI3 */
+ _UDWORD TMOI3:1; /* TMOI3 */
+ _UDWORD BRI0:1; /* BRI0 */
+ _UDWORD ERI0:1; /* ERI0 */
+ _UDWORD RXI0:1; /* RXI0 */
+ } BIT; /* */
+} ICDxxx6; /* */
+typedef union { /* ICDxxx7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI0:1; /* TXI0 */
+ _UDWORD BRI1:1; /* BRI1 */
+ _UDWORD ERI1:1; /* ERI1 */
+ _UDWORD RXI1:1; /* RXI1 */
+ _UDWORD TXI1:1; /* TXI1 */
+ _UDWORD BRI2:1; /* BRI2 */
+ _UDWORD ERI2:1; /* ERI2 */
+ _UDWORD RXI2:1; /* RXI2 */
+ _UDWORD TXI2:1; /* TXI2 */
+ _UDWORD BRI3:1; /* BRI3 */
+ _UDWORD ERI3:1; /* ERI3 */
+ _UDWORD RXI3:1; /* RXI3 */
+ _UDWORD TXI3:1; /* TXI3 */
+ _UDWORD BRI4:1; /* BRI4 */
+ _UDWORD ERI4:1; /* ERI4 */
+ _UDWORD RXI4:1; /* RXI4 */
+ _UDWORD TXI4:1; /* TXI4 */
+ _UDWORD BRI5:1; /* BRI5 */
+ _UDWORD ERI5:1; /* ERI5 */
+ _UDWORD RXI5:1; /* RXI5 */
+ _UDWORD TXI5:1; /* TXI5 */
+ _UDWORD BRI6:1; /* BRI6 */
+ _UDWORD ERI6:1; /* ERI6 */
+ _UDWORD RXI6:1; /* RXI6 */
+ _UDWORD TXI6:1; /* TXI6 */
+ _UDWORD BRI7:1; /* BRI7 */
+ _UDWORD ERI7:1; /* ERI7 */
+ _UDWORD RXI7:1; /* RXI7 */
+ _UDWORD TXI7:1; /* TXI7 */
+ _UDWORD GERI:1; /* GERI */
+ _UDWORD RFI:1; /* RFI */
+ _UDWORD CFRXI0:1; /* CFRXI0 */
+ } BIT; /* */
+} ICDxxx7; /* */
+typedef union { /* ICDxxx8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CERI0:1; /* CERI0 */
+ _UDWORD CTXI0:1; /* CTXI0 */
+ _UDWORD CFRXI1:1; /* CFRXI1 */
+ _UDWORD CERI1:1; /* CERI1 */
+ _UDWORD CTXI1:1; /* CTXI1 */
+ _UDWORD CFRXI2:1; /* CFRXI2 */
+ _UDWORD CERI2:1; /* CERI2 */
+ _UDWORD CTXI2:1; /* CTXI2 */
+ _UDWORD CFRXI3:1; /* CFRXI3 */
+ _UDWORD CERI3:1; /* CERI3 */
+ _UDWORD CTXI3:1; /* CTXI3 */
+ _UDWORD CFRXI4:1; /* CFRXI4 */
+ _UDWORD CERI4:1; /* CERI4 */
+ _UDWORD CTXI4:1; /* CTXI4 */
+ _UDWORD SPEI0:1; /* SPEI0 */
+ _UDWORD SPRI0:1; /* SPRI0 */
+ _UDWORD SPTI0:1; /* SPTI0 */
+ _UDWORD SPEI1:1; /* SPEI1 */
+ _UDWORD SPRI1:1; /* SPRI1 */
+ _UDWORD SPTI1:1; /* SPTI1 */
+ _UDWORD SPEI2:1; /* SPEI2 */
+ _UDWORD SPRI2:1; /* SPRI2 */
+ _UDWORD SPTI2:1; /* SPTI2 */
+ _UDWORD SPEI3:1; /* SPEI3 */
+ _UDWORD SPRI3:1; /* SPRI3 */
+ _UDWORD SPTI3:1; /* SPTI3 */
+ _UDWORD SPEI4:1; /* SPEI4 */
+ _UDWORD SPRI4:1; /* SPRI4 */
+ _UDWORD SPTI4:1; /* SPTI4 */
+ _UDWORD IEBBTD:1; /* IEBBTD */
+ _UDWORD IEBBTERR:1; /* IEBBTERR */
+ _UDWORD IEBBTSTA:1; /* IEBBTSTA */
+ } BIT; /* */
+} ICDxxx8; /* */
+typedef union { /* ICDxxx9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IEBBTV:1; /* IEBBTV */
+ _UDWORD ISY:1; /* ISY */
+ _UDWORD IERR:1; /* IERR */
+ _UDWORD ITARG:1; /* ITARG */
+ _UDWORD ISEC:1; /* ISEC */
+ _UDWORD IBUF:1; /* IBUF */
+ _UDWORD IREADY:1; /* IREADY */
+ _UDWORD FLSTE:1; /* FLSTE */
+ _UDWORD FLTENDI:1; /* FLTENDI */
+ _UDWORD FLTREQ0I:1; /* FLTREQ0I */
+ _UDWORD FLTREQ1I:1; /* FLTREQ1I */
+ _UDWORD MMC0:1; /* MMC0 */
+ _UDWORD MMC1:1; /* MMC1 */
+ _UDWORD MMC2:1; /* MMC2 */
+ _UDWORD SDHI0_3:1; /* SDHI0_3 */
+ _UDWORD SDHI0_0:1; /* SDHI0_0 */
+ _UDWORD SDHI0_1:1; /* SDHI0_1 */
+ _UDWORD SDHI1_3:1; /* SDHI1_3 */
+ _UDWORD SDHI1_0:1; /* SDHI1_0 */
+ _UDWORD SDHI1_1:1; /* SDHI1_1 */
+ _UDWORD ARM:1; /* ARM */
+ _UDWORD PRD:1; /* PRD */
+ _UDWORD CUP:1; /* CUP */
+ _UDWORD SCUAI0:1; /* SCUAI0 */
+ _UDWORD SCUAI1:1; /* SCUAI1 */
+ _UDWORD SCUFDI0:1; /* SCUFDI0 */
+ _UDWORD SCUFDI1:1; /* SCUFDI1 */
+ _UDWORD SCUFDI2:1; /* SCUFDI2 */
+ _UDWORD SCUFDI3:1; /* SCUFDI3 */
+ _UDWORD SCUFUI0:1; /* SCUFUI0 */
+ _UDWORD SCUFUI1:1; /* SCUFUI1 */
+ _UDWORD SCUFUI2:1; /* SCUFUI2 */
+ } BIT; /* */
+} ICDxxx9; /* */
+typedef union { /* ICDxxx10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUFUI3:1; /* SCUFUI3 */
+ _UDWORD SCUDVI0:1; /* SCUDVI0 */
+ _UDWORD SCUDVI1:1; /* SCUDVI1 */
+ _UDWORD SCUDVI2:1; /* SCUDVI2 */
+ _UDWORD SCUDVI3:1; /* SCUDVI3 */
+ _UDWORD MLBCI:1; /* MLBCI */
+ _UDWORD MLBSI:1; /* MLBSI */
+ _UDWORD DRC0:1; /* DRC0 */
+ _UDWORD DRC1:1; /* DRC1 */
+ _UDWORD :2; /* */
+ _UDWORD LINI0_INT_T:1; /* LINI0_INT_T */
+ _UDWORD LINI0_INT_R:1; /* LINI0_INT_R */
+ _UDWORD LINI0_INT_S:1; /* LINI0_INT_S */
+ _UDWORD LINI0_INT_M:1; /* LINI0_INT_M */
+ _UDWORD LINI1_INT_T:1; /* LINI1_INT_T */
+ _UDWORD LINI1_INT_R:1; /* LINI1_INT_R */
+ _UDWORD LINI1_INT_S:1; /* LINI1_INT_S */
+ _UDWORD LINI1_INT_M:1; /* LINI1_INT_M */
+ _UDWORD :8; /* */
+ _UDWORD ERI0:1; /* ERI0 */
+ _UDWORD RXI0:1; /* RXI0 */
+ _UDWORD TXI0:1; /* TXI0 */
+ _UDWORD TEI0:1; /* TEI0 */
+ _UDWORD ERI1:1; /* ERI1 */
+ } BIT; /* */
+} ICDxxx10; /* */
+typedef union { /* ICDxxx11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RXI1:1; /* RXI1 */
+ _UDWORD TXI1:1; /* TXI1 */
+ _UDWORD TEI1:1; /* TEI1 */
+ _UDWORD :4; /* */
+ _UDWORD ETHERI:1; /* ETHERI */
+ _UDWORD :4; /* */
+ _UDWORD CEUI:1; /* CEUI */
+ _UDWORD INT_CSIH0TIR:1; /* INT_CSIH0TIR */
+ _UDWORD INT_CSIH0TIRE:1; /* INT_CSIH0TIRE */
+ _UDWORD INT_CSIH1TIC:1; /* INT_CSIH1TIC */
+ _UDWORD INT_CSIH1TIJC:1; /* INT_CSIH1TIJC */
+ _UDWORD ECCE10:1; /* ECCE10 */
+ _UDWORD ECCE20:1; /* ECCE20 */
+ _UDWORD ECCOVF0:1; /* ECCOVF0 */
+ _UDWORD ECCE11:1; /* ECCE11 */
+ _UDWORD ECCE21:1; /* ECCE21 */
+ _UDWORD ECCOVF1:1; /* ECCOVF1 */
+ _UDWORD ECCE12:1; /* ECCE12 */
+ _UDWORD ECCE22:1; /* ECCE22 */
+ _UDWORD ECCOVF2:1; /* ECCOVF2 */
+ _UDWORD ECCE13:1; /* ECCE13 */
+ _UDWORD ECCE23:1; /* ECCE23 */
+ _UDWORD ECCOVF3:1; /* ECCOVF3 */
+ _UDWORD H2XMLB_ERRINT:1; /* H2XMLB_ERRINT */
+ _UDWORD H2XIC1_ERRINT:1; /* H2XIC1_ERRINT */
+ _UDWORD X2HPERI1_ERRINT:1; /* X2HPERI1_ERRINT */
+ } BIT; /* */
+} ICDxxx11; /* */
+typedef union { /* ICDxxx12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD X2HPERI2_ERRINT:1; /* X2HPERI2_ERRINT */
+ _UDWORD X2HPERI34_ERRINT:1; /* X2HPERI34_ERRINT */
+ _UDWORD X2HPERI5_ERRINT:1; /* X2HPERI5_ERRINT */
+ _UDWORD X2HPERI67_ERRINT:1; /* X2HPERI67_ERRINT */
+ _UDWORD X2HDBGR_ERRINT:1; /* X2HDBGR_ERRINT */
+ _UDWORD PRRI:1; /* PRRI */
+ _UDWORD IFEI0:1; /* IFEI0 */
+ _UDWORD OFFI0:1; /* OFFI0 */
+ _UDWORD PFVEI0:1; /* PFVEI0 */
+ _UDWORD IFEI1:1; /* IFEI1 */
+ _UDWORD OFFI1:1; /* OFFI1 */
+ _UDWORD PFVEI1:1; /* PFVEI1 */
+ _UDWORD :20; /* */
+ } BIT; /* */
+} ICDxxx12; /* */
+typedef union { /* ICDxxx13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT0:1; /* TINT0 */
+ _UDWORD TINT1:1; /* TINT1 */
+ _UDWORD TINT2:1; /* TINT2 */
+ _UDWORD TINT3:1; /* TINT3 */
+ _UDWORD TINT4:1; /* TINT4 */
+ _UDWORD TINT5:1; /* TINT5 */
+ _UDWORD TINT6:1; /* TINT6 */
+ _UDWORD TINT7:1; /* TINT7 */
+ _UDWORD TINT8:1; /* TINT8 */
+ _UDWORD TINT9:1; /* TINT9 */
+ _UDWORD TINT10:1; /* TINT10 */
+ _UDWORD TINT11:1; /* TINT11 */
+ _UDWORD TINT12:1; /* TINT12 */
+ _UDWORD TINT13:1; /* TINT13 */
+ _UDWORD TINT14:1; /* TINT14 */
+ _UDWORD TINT15:1; /* TINT15 */
+ _UDWORD TINT16:1; /* TINT16 */
+ _UDWORD TINT17:1; /* TINT17 */
+ _UDWORD TINT18:1; /* TINT18 */
+ _UDWORD TINT19:1; /* TINT19 */
+ _UDWORD TINT20:1; /* TINT20 */
+ _UDWORD TINT21:1; /* TINT21 */
+ _UDWORD TINT22:1; /* TINT22 */
+ _UDWORD TINT23:1; /* TINT23 */
+ _UDWORD TINT24:1; /* TINT24 */
+ _UDWORD TINT25:1; /* TINT25 */
+ _UDWORD TINT26:1; /* TINT26 */
+ _UDWORD TINT27:1; /* TINT27 */
+ _UDWORD TINT28:1; /* TINT28 */
+ _UDWORD TINT29:1; /* TINT29 */
+ _UDWORD TINT30:1; /* TINT30 */
+ _UDWORD TINT31:1; /* TINT31 */
+ } BIT; /* */
+} ICDxxx13; /* */
+typedef union { /* ICDxxx14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT32:1; /* TINT32 */
+ _UDWORD TINT33:1; /* TINT33 */
+ _UDWORD TINT34:1; /* TINT34 */
+ _UDWORD TINT35:1; /* TINT35 */
+ _UDWORD TINT36:1; /* TINT36 */
+ _UDWORD TINT37:1; /* TINT37 */
+ _UDWORD TINT38:1; /* TINT38 */
+ _UDWORD TINT39:1; /* TINT39 */
+ _UDWORD TINT40:1; /* TINT40 */
+ _UDWORD TINT41:1; /* TINT41 */
+ _UDWORD TINT42:1; /* TINT42 */
+ _UDWORD TINT43:1; /* TINT43 */
+ _UDWORD TINT44:1; /* TINT44 */
+ _UDWORD TINT45:1; /* TINT45 */
+ _UDWORD TINT46:1; /* TINT46 */
+ _UDWORD TINT47:1; /* TINT47 */
+ _UDWORD TINT48:1; /* TINT48 */
+ _UDWORD TINT49:1; /* TINT49 */
+ _UDWORD TINT50:1; /* TINT50 */
+ _UDWORD TINT51:1; /* TINT51 */
+ _UDWORD TINT52:1; /* TINT52 */
+ _UDWORD TINT53:1; /* TINT53 */
+ _UDWORD TINT54:1; /* TINT54 */
+ _UDWORD TINT55:1; /* TINT55 */
+ _UDWORD TINT56:1; /* TINT56 */
+ _UDWORD TINT57:1; /* TINT57 */
+ _UDWORD TINT58:1; /* TINT58 */
+ _UDWORD TINT59:1; /* TINT59 */
+ _UDWORD TINT60:1; /* TINT60 */
+ _UDWORD TINT61:1; /* TINT61 */
+ _UDWORD TINT62:1; /* TINT62 */
+ _UDWORD TINT63:1; /* TINT63 */
+ } BIT; /* */
+} ICDxxx14; /* */
+typedef union { /* ICDxxx15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT64:1; /* TINT64 */
+ _UDWORD TINT65:1; /* TINT65 */
+ _UDWORD TINT66:1; /* TINT66 */
+ _UDWORD TINT67:1; /* TINT67 */
+ _UDWORD TINT68:1; /* TINT68 */
+ _UDWORD TINT69:1; /* TINT69 */
+ _UDWORD TINT70:1; /* TINT70 */
+ _UDWORD TINT71:1; /* TINT71 */
+ _UDWORD TINT72:1; /* TINT72 */
+ _UDWORD TINT73:1; /* TINT73 */
+ _UDWORD TINT74:1; /* TINT74 */
+ _UDWORD TINT75:1; /* TINT75 */
+ _UDWORD TINT76:1; /* TINT76 */
+ _UDWORD TINT77:1; /* TINT77 */
+ _UDWORD TINT78:1; /* TINT78 */
+ _UDWORD TINT79:1; /* TINT79 */
+ _UDWORD TINT80:1; /* TINT80 */
+ _UDWORD TINT81:1; /* TINT81 */
+ _UDWORD TINT82:1; /* TINT82 */
+ _UDWORD TINT83:1; /* TINT83 */
+ _UDWORD TINT84:1; /* TINT84 */
+ _UDWORD TINT85:1; /* TINT85 */
+ _UDWORD TINT86:1; /* TINT86 */
+ _UDWORD TINT87:1; /* TINT87 */
+ _UDWORD TINT88:1; /* TINT88 */
+ _UDWORD TINT89:1; /* TINT89 */
+ _UDWORD TINT90:1; /* TINT90 */
+ _UDWORD TINT91:1; /* TINT91 */
+ _UDWORD TINT92:1; /* TINT92 */
+ _UDWORD TINT93:1; /* TINT93 */
+ _UDWORD TINT94:1; /* TINT94 */
+ _UDWORD TINT95:1; /* TINT95 */
+ } BIT; /* */
+} ICDxxx15; /* */
+typedef union { /* ICDxxx16 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT96:1; /* TINT96 */
+ _UDWORD TINT97:1; /* TINT97 */
+ _UDWORD TINT98:1; /* TINT98 */
+ _UDWORD TINT99:1; /* TINT99 */
+ _UDWORD TINT100:1; /* TINT100 */
+ _UDWORD TINT101:1; /* TINT101 */
+ _UDWORD TINT102:1; /* TINT102 */
+ _UDWORD TINT103:1; /* TINT103 */
+ _UDWORD TINT104:1; /* TINT104 */
+ _UDWORD TINT105:1; /* TINT105 */
+ _UDWORD TINT106:1; /* TINT106 */
+ _UDWORD TINT107:1; /* TINT107 */
+ _UDWORD TINT108:1; /* TINT108 */
+ _UDWORD TINT109:1; /* TINT109 */
+ _UDWORD TINT110:1; /* TINT110 */
+ _UDWORD TINT111:1; /* TINT111 */
+ _UDWORD TINT112:1; /* TINT112 */
+ _UDWORD TINT113:1; /* TINT113 */
+ _UDWORD TINT114:1; /* TINT114 */
+ _UDWORD TINT115:1; /* TINT115 */
+ _UDWORD TINT116:1; /* TINT116 */
+ _UDWORD TINT117:1; /* TINT117 */
+ _UDWORD TINT118:1; /* TINT118 */
+ _UDWORD TINT119:1; /* TINT119 */
+ _UDWORD TINT120:1; /* TINT120 */
+ _UDWORD TINT121:1; /* TINT121 */
+ _UDWORD TINT122:1; /* TINT122 */
+ _UDWORD TINT123:1; /* TINT123 */
+ _UDWORD TINT124:1; /* TINT124 */
+ _UDWORD TINT125:1; /* TINT125 */
+ _UDWORD TINT126:1; /* TINT126 */
+ _UDWORD TINT127:1; /* TINT127 */
+ } BIT; /* */
+} ICDxxx16; /* */
+typedef union { /* ICDxxx17 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT128:1; /* TINT128 */
+ _UDWORD TINT129:1; /* TINT129 */
+ _UDWORD TINT130:1; /* TINT130 */
+ _UDWORD TINT131:1; /* TINT131 */
+ _UDWORD TINT132:1; /* TINT132 */
+ _UDWORD TINT133:1; /* TINT133 */
+ _UDWORD TINT134:1; /* TINT134 */
+ _UDWORD TINT135:1; /* TINT135 */
+ _UDWORD TINT136:1; /* TINT136 */
+ _UDWORD TINT137:1; /* TINT137 */
+ _UDWORD TINT138:1; /* TINT138 */
+ _UDWORD TINT139:1; /* TINT139 */
+ _UDWORD TINT140:1; /* TINT140 */
+ _UDWORD TINT141:1; /* TINT141 */
+ _UDWORD TINT142:1; /* TINT142 */
+ _UDWORD TINT143:1; /* TINT143 */
+ _UDWORD TINT144:1; /* TINT144 */
+ _UDWORD TINT145:1; /* TINT145 */
+ _UDWORD TINT146:1; /* TINT146 */
+ _UDWORD TINT147:1; /* TINT147 */
+ _UDWORD TINT148:1; /* TINT148 */
+ _UDWORD TINT149:1; /* TINT149 */
+ _UDWORD TINT150:1; /* TINT150 */
+ _UDWORD TINT151:1; /* TINT151 */
+ _UDWORD TINT152:1; /* TINT152 */
+ _UDWORD TINT153:1; /* TINT153 */
+ _UDWORD TINT154:1; /* TINT154 */
+ _UDWORD TINT155:1; /* TINT155 */
+ _UDWORD TINT156:1; /* TINT156 */
+ _UDWORD TINT157:1; /* TINT157 */
+ _UDWORD TINT158:1; /* TINT158 */
+ _UDWORD TINT159:1; /* TINT159 */
+ } BIT; /* */
+} ICDxxx17; /* */
+typedef union { /* ICDxxx18 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT160:1; /* TINT160 */
+ _UDWORD TINT161:1; /* TINT161 */
+ _UDWORD TINT162:1; /* TINT162 */
+ _UDWORD :29; /* */
+ } BIT; /* */
+} ICDxxx18; /* */
+
+
+struct st_intc { /* struct INTC */
+ union { /* ICDDCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD Enable:1; /* Enable */
+ _UDWORD :31; /* */
+ } BIT; /* */
+ } ICDDCR; /* */
+ union { /* ICDICTR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ITLinesNumber:5; /* ITLinesNumber */
+ _UDWORD CPUNumber:3; /* CPUNumber */
+ _UDWORD :2; /* */
+ _UDWORD SecurityExtn:1; /* SecurityExtn */
+ _UDWORD LSPI:5; /* LSPI */
+ _UDWORD :16; /* */
+ } BIT; /* */
+ } ICDICTR; /* */
+ union { /* ICDIIDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD Implementer:12; /* Implementer */
+ _UDWORD Revision:4; /* Revision */
+ _UDWORD Variant:4; /* Variant */
+ _UDWORD :4; /* */
+ _UDWORD ProductID:8; /* ProductID */
+ } BIT; /* */
+ } ICDIIDR; /* */
+ _UBYTE wk0[116]; /* */
+ union { /* ICDISR */
+ _UDWORD LONG[19]; /* Long Access */
+ struct { /* ICDISRn */
+ ICDxxx0 ICDISR0; /* ICDISR0 */
+ ICDxxx1 ICDISR1; /* ICDISR1 */
+ ICDxxx2 ICDISR2; /* ICDISR2 */
+ ICDxxx3 ICDISR3; /* ICDISR3 */
+ ICDxxx4 ICDISR4; /* ICDISR4 */
+ ICDxxx5 ICDISR5; /* ICDISR5 */
+ ICDxxx6 ICDISR6; /* ICDISR6 */
+ ICDxxx7 ICDISR7; /* ICDISR7 */
+ ICDxxx8 ICDISR8; /* ICDISR8 */
+ ICDxxx9 ICDISR9; /* ICDISR9 */
+ ICDxxx10 ICDISR10; /* ICDISR10 */
+ ICDxxx11 ICDISR11; /* ICDISR11 */
+ ICDxxx12 ICDISR12; /* ICDISR12 */
+ ICDxxx13 ICDISR13; /* ICDISR13 */
+ ICDxxx14 ICDISR14; /* ICDISR14 */
+ ICDxxx15 ICDISR15; /* ICDISR15 */
+ ICDxxx16 ICDISR16; /* ICDISR16 */
+ ICDxxx17 ICDISR17; /* ICDISR17 */
+ ICDxxx18 ICDISR18; /* ICDISR18 */
+ } n; /* */
+ } ICDISR; /* */
+ _UBYTE wk1[52]; /* */
+ union { /* ICDISER */
+ _UDWORD LONG[19]; /* Long Access */
+ struct { /* ICDISERn */
+ ICDxxx0 ICDISER0; /* ICDISER0 */
+ ICDxxx1 ICDISER1; /* ICDISER1 */
+ ICDxxx2 ICDISER2; /* ICDISER2 */
+ ICDxxx3 ICDISER3; /* ICDISER3 */
+ ICDxxx4 ICDISER4; /* ICDISER4 */
+ ICDxxx5 ICDISER5; /* ICDISER5 */
+ ICDxxx6 ICDISER6; /* ICDISER6 */
+ ICDxxx7 ICDISER7; /* ICDISER7 */
+ ICDxxx8 ICDISER8; /* ICDISER8 */
+ ICDxxx9 ICDISER9; /* ICDISER9 */
+ ICDxxx10 ICDISER10; /* ICDISER10 */
+ ICDxxx11 ICDISER11; /* ICDISER11 */
+ ICDxxx12 ICDISER12; /* ICDISER12 */
+ ICDxxx13 ICDISER13; /* ICDISER13 */
+ ICDxxx14 ICDISER14; /* ICDISER14 */
+ ICDxxx15 ICDISER15; /* ICDISER15 */
+ ICDxxx16 ICDISER16; /* ICDISER16 */
+ ICDxxx17 ICDISER17; /* ICDISER17 */
+ ICDxxx18 ICDISER18; /* ICDISER18 */
+ } n; /* */
+ } ICDISER; /* */
+ _UBYTE wk2[52]; /* */
+ union { /* ICDICER */
+ _UDWORD LONG[19]; /* Long Access */
+ struct { /* ICDICERn */
+ ICDxxx0 ICDICER0; /* ICDICER0 */
+ ICDxxx1 ICDICER1; /* ICDICER1 */
+ ICDxxx2 ICDICER2; /* ICDICER2 */
+ ICDxxx3 ICDICER3; /* ICDICER3 */
+ ICDxxx4 ICDICER4; /* ICDICER4 */
+ ICDxxx5 ICDICER5; /* ICDICER5 */
+ ICDxxx6 ICDICER6; /* ICDICER6 */
+ ICDxxx7 ICDICER7; /* ICDICER7 */
+ ICDxxx8 ICDICER8; /* ICDICER8 */
+ ICDxxx9 ICDICER9; /* ICDICER9 */
+ ICDxxx10 ICDICER10; /* ICDICER10 */
+ ICDxxx11 ICDICER11; /* ICDICER11 */
+ ICDxxx12 ICDICER12; /* ICDICER12 */
+ ICDxxx13 ICDICER13; /* ICDICER13 */
+ ICDxxx14 ICDICER14; /* ICDICER14 */
+ ICDxxx15 ICDICER15; /* ICDICER15 */
+ ICDxxx16 ICDICER16; /* ICDICER16 */
+ ICDxxx17 ICDICER17; /* ICDICER17 */
+ ICDxxx18 ICDICER18; /* ICDICER18 */
+ } n; /* */
+ } ICDICER; /* */
+ _UBYTE wk3[52]; /* */
+ union { /* ICDISPR */
+ _UDWORD LONG[19]; /* Long Access */
+ struct { /* ICDISPRn */
+ ICDxxx0 ICDISPR0; /* ICDISPR0 */
+ ICDxxx1 ICDISPR1; /* ICDISPR1 */
+ ICDxxx2 ICDISPR2; /* ICDISPR2 */
+ ICDxxx3 ICDISPR3; /* ICDISPR3 */
+ ICDxxx4 ICDISPR4; /* ICDISPR4 */
+ ICDxxx5 ICDISPR5; /* ICDISPR5 */
+ ICDxxx6 ICDISPR6; /* ICDISPR6 */
+ ICDxxx7 ICDISPR7; /* ICDISPR7 */
+ ICDxxx8 ICDISPR8; /* ICDISPR8 */
+ ICDxxx9 ICDISPR9; /* ICDISPR9 */
+ ICDxxx10 ICDISPR10; /* ICDISPR10 */
+ ICDxxx11 ICDISPR11; /* ICDISPR11 */
+ ICDxxx12 ICDISPR12; /* ICDISPR12 */
+ ICDxxx13 ICDISPR13; /* ICDISPR13 */
+ ICDxxx14 ICDISPR14; /* ICDISPR14 */
+ ICDxxx15 ICDISPR15; /* ICDISPR15 */
+ ICDxxx16 ICDISPR16; /* ICDISPR16 */
+ ICDxxx17 ICDISPR17; /* ICDISPR17 */
+ ICDxxx18 ICDISPR18; /* ICDISPR18 */
+ } n; /* */
+ } ICDISPR; /* */
+ _UBYTE wk4[52]; /* */
+ union { /* ICDICPR */
+ _UDWORD LONG[19]; /* Long Access */
+ struct { /* ICDICPRn */
+ ICDxxx0 ICDICPR0; /* ICDICPR0 */
+ ICDxxx1 ICDICPR1; /* ICDICPR1 */
+ ICDxxx2 ICDICPR2; /* ICDICPR2 */
+ ICDxxx3 ICDICPR3; /* ICDICPR3 */
+ ICDxxx4 ICDICPR4; /* ICDICPR4 */
+ ICDxxx5 ICDICPR5; /* ICDICPR5 */
+ ICDxxx6 ICDICPR6; /* ICDICPR6 */
+ ICDxxx7 ICDICPR7; /* ICDICPR7 */
+ ICDxxx8 ICDICPR8; /* ICDICPR8 */
+ ICDxxx9 ICDICPR9; /* ICDICPR9 */
+ ICDxxx10 ICDICPR10; /* ICDICPR10 */
+ ICDxxx11 ICDICPR11; /* ICDICPR11 */
+ ICDxxx12 ICDICPR12; /* ICDICPR12 */
+ ICDxxx13 ICDICPR13; /* ICDICPR13 */
+ ICDxxx14 ICDICPR14; /* ICDICPR14 */
+ ICDxxx15 ICDICPR15; /* ICDICPR15 */
+ ICDxxx16 ICDICPR16; /* ICDICPR16 */
+ ICDxxx17 ICDICPR17; /* ICDICPR17 */
+ ICDxxx18 ICDICPR18; /* ICDICPR18 */
+ } n; /* */
+ } ICDICPR; /* */
+ _UBYTE wk5[52]; /* */
+ union { /* ICDABR */
+ _UDWORD LONG[19]; /* Long Access */
+ struct { /* ICDABRn */
+ ICDxxx0 ICDABR0; /* ICDABR0 */
+ ICDxxx1 ICDABR1; /* ICDABR1 */
+ ICDxxx2 ICDABR2; /* ICDABR2 */
+ ICDxxx3 ICDABR3; /* ICDABR3 */
+ ICDxxx4 ICDABR4; /* ICDABR4 */
+ ICDxxx5 ICDABR5; /* ICDABR5 */
+ ICDxxx6 ICDABR6; /* ICDABR6 */
+ ICDxxx7 ICDABR7; /* ICDABR7 */
+ ICDxxx8 ICDABR8; /* ICDABR8 */
+ ICDxxx9 ICDABR9; /* ICDABR9 */
+ ICDxxx10 ICDABR10; /* ICDABR10 */
+ ICDxxx11 ICDABR11; /* ICDABR11 */
+ ICDxxx12 ICDABR12; /* ICDABR12 */
+ ICDxxx13 ICDABR13; /* ICDABR13 */
+ ICDxxx14 ICDABR14; /* ICDABR14 */
+ ICDxxx15 ICDABR15; /* ICDABR15 */
+ ICDxxx16 ICDABR16; /* ICDABR16 */
+ ICDxxx17 ICDABR17; /* ICDABR17 */
+ ICDxxx18 ICDABR18; /* ICDABR18 */
+ } n; /* */
+ } ICDABR; /* */
+ _UBYTE wk6[180]; /* */
+ union { /* ICDIPR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW0:8; /* SW0 */
+ _UDWORD SW1:8; /* SW1 */
+ _UDWORD SW2:8; /* SW2 */
+ _UDWORD SW3:8; /* SW3 */
+ } BIT; /* */
+ } ICDIPR0; /* */
+ union { /* ICDIPR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW4:8; /* SW4 */
+ _UDWORD SW5:8; /* SW5 */
+ _UDWORD SW6:8; /* SW6 */
+ _UDWORD SW7:8; /* SW7 */
+ } BIT; /* */
+ } ICDIPR1; /* */
+ union { /* ICDIPR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW8:8; /* SW8 */
+ _UDWORD SW9:8; /* SW9 */
+ _UDWORD SW10:8; /* SW10 */
+ _UDWORD SW11:8; /* SW11 */
+ } BIT; /* */
+ } ICDIPR2; /* */
+ union { /* ICDIPR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW12:8; /* SW12 */
+ _UDWORD SW13:8; /* SW13 */
+ _UDWORD SW14:8; /* SW14 */
+ _UDWORD SW15:8; /* SW15 */
+ } BIT; /* */
+ } ICDIPR3; /* */
+ union { /* ICDIPR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PMUIRQ0:8; /* PMUIRQ0 */
+ _UDWORD COMMRX0:8; /* COMMRX0 */
+ _UDWORD COMMTX0:8; /* COMMTX0 */
+ _UDWORD CTIIRQ0:8; /* CTIIRQ0 */
+ } BIT; /* */
+ } ICDIPR4; /* */
+ _UBYTE wk7[12]; /* */
+ union { /* ICDIPR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IRQ0:8; /* IRQ0 */
+ _UDWORD IRQ1:8; /* IRQ1 */
+ _UDWORD IRQ2:8; /* IRQ2 */
+ _UDWORD IRQ3:8; /* IRQ3 */
+ } BIT; /* */
+ } ICDIPR8; /* */
+ union { /* ICDIPR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IRQ4:8; /* IRQ4 */
+ _UDWORD IRQ5:8; /* IRQ5 */
+ _UDWORD IRQ6:8; /* IRQ6 */
+ _UDWORD IRQ7:8; /* IRQ7 */
+ } BIT; /* */
+ } ICDIPR9; /* */
+ union { /* ICDIPR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PL310ERR:8; /* PL310ERR */
+ _UDWORD DMAINT0:8; /* DMAINT0 */
+ _UDWORD DMAINT1:8; /* DMAINT1 */
+ _UDWORD DMAINT2:8; /* DMAINT2 */
+ } BIT; /* */
+ } ICDIPR10; /* */
+ union { /* ICDIPR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT3:8; /* DMAINT3 */
+ _UDWORD DMAINT4:8; /* DMAINT4 */
+ _UDWORD DMAINT5:8; /* DMAINT5 */
+ _UDWORD DMAINT6:8; /* DMAINT6 */
+ } BIT; /* */
+ } ICDIPR11; /* */
+ union { /* ICDIPR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT7:8; /* DMAINT7 */
+ _UDWORD DMAINT8:8; /* DMAINT8 */
+ _UDWORD DMAINT9:8; /* DMAINT9 */
+ _UDWORD DMAINT10:8; /* DMAINT10 */
+ } BIT; /* */
+ } ICDIPR12; /* */
+ union { /* ICDIPR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT11:8; /* DMAINT11 */
+ _UDWORD DMAINT12:8; /* DMAINT12 */
+ _UDWORD DMAINT13:8; /* DMAINT13 */
+ _UDWORD DMAINT14:8; /* DMAINT14 */
+ } BIT; /* */
+ } ICDIPR13; /* */
+ union { /* ICDIPR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT15:8; /* DMAINT15 */
+ _UDWORD DMAERR:8; /* DMAERR */
+ _UDWORD :16; /* */
+ } BIT; /* */
+ } ICDIPR14; /* */
+ _UBYTE wk8[12]; /* */
+ union { /* ICDIPR18 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD USBI0:8; /* USBI0 */
+ _UDWORD USBI1:8; /* USBI1 */
+ _UDWORD S0_VI_VSYNC0:8; /* S0_VI_VSYNC0 */
+ } BIT; /* */
+ } ICDIPR18; /* */
+ union { /* ICDIPR19 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_LO_VSYNC0:8; /* S0_LO_VSYNC0 */
+ _UDWORD S0_VSYNCERR0:8; /* S0_VSYNCERR0 */
+ _UDWORD GR3_VLINE0:8; /* GR3_VLINE0 */
+ _UDWORD S0_VFIELD0:8; /* S0_VFIELD0 */
+ } BIT; /* */
+ } ICDIPR19; /* */
+ union { /* ICDIPR20 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV1_VBUFERR0:8; /* IV1_VBUFERR0 */
+ _UDWORD IV3_VBUFERR0:8; /* IV3_VBUFERR0 */
+ _UDWORD IV5_VBUFERR0:8; /* IV5_VBUFERR0 */
+ _UDWORD IV6_VBUFERR0:8; /* IV6_VBUFERR0 */
+ } BIT; /* */
+ } ICDIPR20; /* */
+ union { /* ICDIPR21 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_WLINE0:8; /* S0_WLINE0 */
+ _UDWORD S1_VI_VSYNC0:8; /* S1_VI_VSYNC0 */
+ _UDWORD S1_LO_VSYNC0:8; /* S1_LO_VSYNC0 */
+ _UDWORD S1_VSYNCERR0:8; /* S1_VSYNCERR0 */
+ } BIT; /* */
+ } ICDIPR21; /* */
+ union { /* ICDIPR22 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S1_VFIELD0:8; /* S1_VFIELD0 */
+ _UDWORD IV2_VBUFERR0:8; /* IV2_VBUFERR0 */
+ _UDWORD IV4_VBUFERR0:8; /* IV4_VBUFERR0 */
+ _UDWORD S1_WLINE0:8; /* S1_WLINE0 */
+ } BIT; /* */
+ } ICDIPR22; /* */
+ union { /* ICDIPR23 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OIR_VI_VSYNC0:8; /* OIR_VI_VSYNC0 */
+ _UDWORD OIR_LO_VSYNC0:8; /* OIR_LO_VSYNC0 */
+ _UDWORD OIR_VSYNCERR0:8; /* OIR_VSYNCERR0 */
+ _UDWORD OIR_VFIELD0:8; /* OIR_VFIELD0 */
+ } BIT; /* */
+ } ICDIPR23; /* */
+ union { /* ICDIPR24 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV7_VBUFERR0:8; /* IV7_VBUFERR0 */
+ _UDWORD IV8_VBUFERR0:8; /* IV8_VBUFERR0 */
+ _UDWORD OIR_WLINE0:8; /* OIR_WLINE0 */
+ _UDWORD S0_VI_VSYNC1:8; /* S0_VI_VSYNC1 */
+ } BIT; /* */
+ } ICDIPR24; /* */
+ union { /* ICDIPR25 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_LO_VSYNC1:8; /* S0_LO_VSYNC1 */
+ _UDWORD S0_VSYNCERR1:8; /* S0_VSYNCERR1 */
+ _UDWORD GR3_VLINE1:8; /* GR3_VLINE1 */
+ _UDWORD S0_VFIELD1:8; /* S0_VFIELD1 */
+ } BIT; /* */
+ } ICDIPR25; /* */
+ union { /* ICDIPR26 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV1_VBUFERR1:8; /* IV1_VBUFERR1 */
+ _UDWORD IV3_VBUFERR1:8; /* IV3_VBUFERR1 */
+ _UDWORD IV5_VBUFERR1:8; /* IV5_VBUFERR1 */
+ _UDWORD IV6_VBUFERR1:8; /* IV6_VBUFERR1 */
+ } BIT; /* */
+ } ICDIPR26; /* */
+ union { /* ICDIPR27 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_WLINE1:8; /* S0_WLINE1 */
+ _UDWORD S1_VI_VSYNC1:8; /* S1_VI_VSYNC1 */
+ _UDWORD S1_LO_VSYNC1:8; /* S1_LO_VSYNC1 */
+ _UDWORD S1_VSYNCERR1:8; /* S1_VSYNCERR1 */
+ } BIT; /* */
+ } ICDIPR27; /* */
+ union { /* ICDIPR28 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S1_VFIELD1:8; /* S1_VFIELD1 */
+ _UDWORD IV2_VBUFERR1:8; /* IV2_VBUFERR1 */
+ _UDWORD IV4_VBUFERR1:8; /* IV4_VBUFERR1 */
+ _UDWORD S1_WLINE1:8; /* S1_WLINE1 */
+ } BIT; /* */
+ } ICDIPR28; /* */
+ union { /* ICDIPR29 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OIR_VI_VSYNC1:8; /* OIR_VI_VSYNC1 */
+ _UDWORD OIR_LO_VSYNC1:8; /* OIR_LO_VSYNC1 */
+ _UDWORD OIR_VLINE1:8; /* OIR_VLINE1 */
+ _UDWORD OIR_VFIELD1:8; /* OIR_VFIELD1 */
+ } BIT; /* */
+ } ICDIPR29; /* */
+ union { /* ICDIPR30 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV7_VBUFERR1:8; /* IV7_VBUFERR1 */
+ _UDWORD IV8_VBUFERR1:8; /* IV8_VBUFERR1 */
+ _UDWORD OIR_WLINE1:8; /* OIR_WLINE1 */
+ _UDWORD IMRDI:8; /* IMRDI */
+ } BIT; /* */
+ } ICDIPR30; /* */
+ union { /* ICDIPR31 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IMR2I0:8; /* IMR2I0 */
+ _UDWORD IMR2I1:8; /* IMR2I1 */
+ _UDWORD JEDI:8; /* JEDI */
+ _UDWORD JDTI:8; /* JDTI */
+ } BIT; /* */
+ } ICDIPR31; /* */
+ union { /* ICDIPR32 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMP0:8; /* CMP0 */
+ _UDWORD CMP1:8; /* CMP1 */
+ _UDWORD INT0:8; /* INT0 */
+ _UDWORD INT1:8; /* INT1 */
+ } BIT; /* */
+ } ICDIPR32; /* */
+ union { /* ICDIPR33 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD INT2:8; /* INT2 */
+ _UDWORD INT3:8; /* INT3 */
+ _UDWORD OSTMI0:8; /* OSTMI0 */
+ _UDWORD OSTMI1:8; /* OSTMI1 */
+ } BIT; /* */
+ } ICDIPR33; /* */
+ union { /* ICDIPR34 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMI:8; /* CMI */
+ _UDWORD WTOUT:8; /* WTOUT */
+ _UDWORD ITI:8; /* ITI */
+ _UDWORD TGI0A:8; /* TGI0A */
+ } BIT; /* */
+ } ICDIPR34; /* */
+ union { /* ICDIPR35 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI0B:8; /* TGI0B */
+ _UDWORD TGI0C:8; /* TGI0C */
+ _UDWORD TGI0D:8; /* TGI0D */
+ _UDWORD TGI0V:8; /* TGI0V */
+ } BIT; /* */
+ } ICDIPR35; /* */
+ union { /* ICDIPR36 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI0E:8; /* TGI0E */
+ _UDWORD TGI0F:8; /* TGI0F */
+ _UDWORD TGI1A:8; /* TGI1A */
+ _UDWORD TGI1B:8; /* TGI1B */
+ } BIT; /* */
+ } ICDIPR36; /* */
+ union { /* ICDIPR37 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI1V:8; /* TGI1V */
+ _UDWORD TGI1U:8; /* TGI1U */
+ _UDWORD TGI2A:8; /* TGI2A */
+ _UDWORD TGI2B:8; /* TGI2B */
+ } BIT; /* */
+ } ICDIPR37; /* */
+ union { /* ICDIPR38 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI2V:8; /* TGI2V */
+ _UDWORD TGI2U:8; /* TGI2U */
+ _UDWORD TGI3A:8; /* TGI3A */
+ _UDWORD TGI3B:8; /* TGI3B */
+ } BIT; /* */
+ } ICDIPR38; /* */
+ union { /* ICDIPR39 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI3C:8; /* TGI3C */
+ _UDWORD TGI3D:8; /* TGI3D */
+ _UDWORD TGI3V:8; /* TGI3V */
+ _UDWORD TGI4A:8; /* TGI4A */
+ } BIT; /* */
+ } ICDIPR39; /* */
+ union { /* ICDIPR40 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI4B:8; /* TGI4B */
+ _UDWORD TGI4C:8; /* TGI4C */
+ _UDWORD TGI4D:8; /* TGI4D */
+ _UDWORD TGI4V:8; /* TGI4V */
+ } BIT; /* */
+ } ICDIPR40; /* */
+ union { /* ICDIPR41 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMI1:8; /* CMI1 */
+ _UDWORD CMI2:8; /* CMI2 */
+ _UDWORD SGDEI0:8; /* SGDEI0 */
+ _UDWORD SGDEI1:8; /* SGDEI1 */
+ } BIT; /* */
+ } ICDIPR41; /* */
+ union { /* ICDIPR42 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SGDEI2:8; /* SGDEI2 */
+ _UDWORD SGDEI3:8; /* SGDEI3 */
+ _UDWORD ADI:8; /* ADI */
+ _UDWORD ADWAR:8; /* ADWAR */
+ } BIT; /* */
+ } ICDIPR42; /* */
+ union { /* ICDIPR43 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSII0:8; /* SSII0 */
+ _UDWORD SSIRXI0:8; /* SSIRXI0 */
+ _UDWORD SSITXI0:8; /* SSITXI0 */
+ _UDWORD SSII1:8; /* SSII1 */
+ } BIT; /* */
+ } ICDIPR43; /* */
+ union { /* ICDIPR44 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSIRXI1:8; /* SSIRXI1 */
+ _UDWORD SSITXI1:8; /* SSITXI1 */
+ _UDWORD SSII2:8; /* SSII2 */
+ _UDWORD SSIRTI2:8; /* SSIRTI2 */
+ } BIT; /* */
+ } ICDIPR44; /* */
+ union { /* ICDIPR45 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSII3:8; /* SSII3 */
+ _UDWORD SSIRXI3:8; /* SSIRXI3 */
+ _UDWORD SSITXI3:8; /* SSITXI3 */
+ _UDWORD SSII4:8; /* SSII4 */
+ } BIT; /* */
+ } ICDIPR45; /* */
+ union { /* ICDIPR46 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSIRTI4:8; /* SSIRTI4 */
+ _UDWORD SSII5:8; /* SSII5 */
+ _UDWORD SSIRXI5:8; /* SSIRXI5 */
+ _UDWORD SSITXI5:8; /* SSITXI5 */
+ } BIT; /* */
+ } ICDIPR46; /* */
+ union { /* ICDIPR47 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPDIFI:8; /* SPDIFI */
+ _UDWORD TEI0:8; /* TEI0 */
+ _UDWORD RI0:8; /* RI0 */
+ _UDWORD TI0:8; /* TI0 */
+ } BIT; /* */
+ } ICDIPR47; /* */
+ union { /* ICDIPR48 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI0:8; /* SPI0 */
+ _UDWORD STI0:8; /* STI0 */
+ _UDWORD NAKI0:8; /* NAKI0 */
+ _UDWORD ALI0:8; /* ALI0 */
+ } BIT; /* */
+ } ICDIPR48; /* */
+ union { /* ICDIPR49 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI0:8; /* TMOI0 */
+ _UDWORD TEI1:8; /* TEI1 */
+ _UDWORD RI1:8; /* RI1 */
+ _UDWORD TI1:8; /* TI1 */
+ } BIT; /* */
+ } ICDIPR49; /* */
+ union { /* ICDIPR50 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI1:8; /* SPI1 */
+ _UDWORD STI1:8; /* STI1 */
+ _UDWORD NAKI1:8; /* NAKI1 */
+ _UDWORD ALI1:8; /* ALI1 */
+ } BIT; /* */
+ } ICDIPR50; /* */
+ union { /* ICDIPR51 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI1:8; /* TMOI1 */
+ _UDWORD TEI2:8; /* TEI2 */
+ _UDWORD RI2:8; /* RI2 */
+ _UDWORD TI2:8; /* TI2 */
+ } BIT; /* */
+ } ICDIPR51; /* */
+ union { /* ICDIPR52 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI2:8; /* SPI2 */
+ _UDWORD STI2:8; /* STI2 */
+ _UDWORD NAKI2:8; /* NAKI2 */
+ _UDWORD ALI2:8; /* ALI2 */
+ } BIT; /* */
+ } ICDIPR52; /* */
+ union { /* ICDIPR53 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI2:8; /* TMOI2 */
+ _UDWORD TEI3:8; /* TEI3 */
+ _UDWORD RI3:8; /* RI3 */
+ _UDWORD TI3:8; /* TI3 */
+ } BIT; /* */
+ } ICDIPR53; /* */
+ union { /* ICDIPR54 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI3:8; /* SPI3 */
+ _UDWORD STI3:8; /* STI3 */
+ _UDWORD NAKI3:8; /* NAKI3 */
+ _UDWORD ALI3:8; /* ALI3 */
+ } BIT; /* */
+ } ICDIPR54; /* */
+ union { /* ICDIPR55 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI3:8; /* TMOI3 */
+ _UDWORD BRI0:8; /* BRI0 */
+ _UDWORD ERI0:8; /* ERI0 */
+ _UDWORD RXI0:8; /* RXI0 */
+ } BIT; /* */
+ } ICDIPR55; /* */
+ union { /* ICDIPR56 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI0:8; /* TXI0 */
+ _UDWORD BRI1:8; /* BRI1 */
+ _UDWORD ERI1:8; /* ERI1 */
+ _UDWORD RXI1:8; /* RXI1 */
+ } BIT; /* */
+ } ICDIPR56; /* */
+ union { /* ICDIPR57 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI1:8; /* TXI1 */
+ _UDWORD BRI2:8; /* BRI2 */
+ _UDWORD ERI2:8; /* ERI2 */
+ _UDWORD RXI2:8; /* RXI2 */
+ } BIT; /* */
+ } ICDIPR57; /* */
+ union { /* ICDIPR58 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI2:8; /* TXI2 */
+ _UDWORD BRI3:8; /* BRI3 */
+ _UDWORD ERI3:8; /* ERI3 */
+ _UDWORD RXI3:8; /* RXI3 */
+ } BIT; /* */
+ } ICDIPR58; /* */
+ union { /* ICDIPR59 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI3:8; /* TXI3 */
+ _UDWORD BRI4:8; /* BRI4 */
+ _UDWORD ERI4:8; /* ERI4 */
+ _UDWORD RXI4:8; /* RXI4 */
+ } BIT; /* */
+ } ICDIPR59; /* */
+ union { /* ICDIPR60 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI4:8; /* TXI4 */
+ _UDWORD BRI5:8; /* BRI5 */
+ _UDWORD ERI5:8; /* ERI5 */
+ _UDWORD RXI5:8; /* RXI5 */
+ } BIT; /* */
+ } ICDIPR60; /* */
+ union { /* ICDIPR61 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI5:8; /* TXI5 */
+ _UDWORD BRI6:8; /* BRI6 */
+ _UDWORD ERI6:8; /* ERI6 */
+ _UDWORD RXI6:8; /* RXI6 */
+ } BIT; /* */
+ } ICDIPR61; /* */
+ union { /* ICDIPR62 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI6:8; /* TXI6 */
+ _UDWORD BRI7:8; /* BRI7 */
+ _UDWORD ERI7:8; /* ERI7 */
+ _UDWORD RXI7:8; /* RXI7 */
+ } BIT; /* */
+ } ICDIPR62; /* */
+ union { /* ICDIPR63 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI7:8; /* TXI7 */
+ _UDWORD GERI:8; /* GERI */
+ _UDWORD RFI:8; /* RFI */
+ _UDWORD CFRXI0:8; /* CFRXI0 */
+ } BIT; /* */
+ } ICDIPR63; /* */
+ union { /* ICDIPR64 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CERI0:8; /* CERI0 */
+ _UDWORD CTXI0:8; /* CTXI0 */
+ _UDWORD CFRXI1:8; /* CFRXI1 */
+ _UDWORD CERI1:8; /* CERI1 */
+ } BIT; /* */
+ } ICDIPR64; /* */
+ union { /* ICDIPR65 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CTXI1:8; /* CTXI1 */
+ _UDWORD CFRXI2:8; /* CFRXI2 */
+ _UDWORD CERI2:8; /* CERI2 */
+ _UDWORD CTXI2:8; /* CTXI2 */
+ } BIT; /* */
+ } ICDIPR65; /* */
+ union { /* ICDIPR66 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CFRXI3:8; /* CFRXI3 */
+ _UDWORD CERI3:8; /* CERI3 */
+ _UDWORD CTXI3:8; /* CTXI3 */
+ _UDWORD CFRXI4:8; /* CFRXI4 */
+ } BIT; /* */
+ } ICDIPR66; /* */
+ union { /* ICDIPR67 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CERI4:8; /* CERI4 */
+ _UDWORD CTXI4:8; /* CTXI4 */
+ _UDWORD SPEI0:8; /* SPEI0 */
+ _UDWORD SPRI0:8; /* SPRI0 */
+ } BIT; /* */
+ } ICDIPR67; /* */
+ union { /* ICDIPR68 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPTI0:8; /* SPTI0 */
+ _UDWORD SPEI1:8; /* SPEI1 */
+ _UDWORD SPRI1:8; /* SPRI1 */
+ _UDWORD SPTI1:8; /* SPTI1 */
+ } BIT; /* */
+ } ICDIPR68; /* */
+ union { /* ICDIPR69 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPEI2:8; /* SPEI2 */
+ _UDWORD SPRI2:8; /* SPRI2 */
+ _UDWORD SPTI2:8; /* SPTI2 */
+ _UDWORD SPEI3:8; /* SPEI3 */
+ } BIT; /* */
+ } ICDIPR69; /* */
+ union { /* ICDIPR70 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPRI3:8; /* SPRI3 */
+ _UDWORD SPTI3:8; /* SPTI3 */
+ _UDWORD SPEI4:8; /* SPEI4 */
+ _UDWORD SPRI4:8; /* SPRI4 */
+ } BIT; /* */
+ } ICDIPR70; /* */
+ union { /* ICDIPR71 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPTI4:8; /* SPTI4 */
+ _UDWORD IEBBTD:8; /* IEBBTD */
+ _UDWORD IEBBTERR:8; /* IEBBTERR */
+ _UDWORD IEBBTSTA:8; /* IEBBTSTA */
+ } BIT; /* */
+ } ICDIPR71; /* */
+ union { /* ICDIPR72 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IEBBTV:8; /* IEBBTV */
+ _UDWORD ISY:8; /* ISY */
+ _UDWORD IERR:8; /* IERR */
+ _UDWORD ITARG:8; /* ITARG */
+ } BIT; /* */
+ } ICDIPR72; /* */
+ union { /* ICDIPR73 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ISEC:8; /* ISEC */
+ _UDWORD IBUF:8; /* IBUF */
+ _UDWORD IREADY:8; /* IREADY */
+ _UDWORD FLSTE:8; /* FLSTE */
+ } BIT; /* */
+ } ICDIPR73; /* */
+ union { /* ICDIPR74 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FLTENDI:8; /* FLTENDI */
+ _UDWORD FLTREQ0I:8; /* FLTREQ0I */
+ _UDWORD FLTREQ1I:8; /* FLTREQ1I */
+ _UDWORD MMC0:8; /* MMC0 */
+ } BIT; /* */
+ } ICDIPR74; /* */
+ union { /* ICDIPR75 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD MMC1:8; /* MMC1 */
+ _UDWORD MMC2:8; /* MMC2 */
+ _UDWORD SDHI0_3:8; /* SDHI0_3 */
+ _UDWORD SDHI0_0:8; /* SDHI0_0 */
+ } BIT; /* */
+ } ICDIPR75; /* */
+ union { /* ICDIPR76 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SDHI0_1:8; /* SDHI0_1 */
+ _UDWORD SDHI1_3:8; /* SDHI1_3 */
+ _UDWORD SDHI1_0:8; /* SDHI1_0 */
+ _UDWORD SDHI1_1:8; /* SDHI1_1 */
+ } BIT; /* */
+ } ICDIPR76; /* */
+ union { /* ICDIPR77 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ARM:8; /* ARM */
+ _UDWORD PRD:8; /* PRD */
+ _UDWORD CUP:8; /* CUP */
+ _UDWORD SCUAI0:8; /* SCUAI0 */
+ } BIT; /* */
+ } ICDIPR77; /* */
+ union { /* ICDIPR78 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUAI1:8; /* SCUAI1 */
+ _UDWORD SCUFDI0:8; /* SCUFDI0 */
+ _UDWORD SCUFDI1:8; /* SCUFDI1 */
+ _UDWORD SCUFDI2:8; /* SCUFDI2 */
+ } BIT; /* */
+ } ICDIPR78; /* */
+ union { /* ICDIPR79 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUFDI3:8; /* SCUFDI3 */
+ _UDWORD SCUFUI0:8; /* SCUFUI0 */
+ _UDWORD SCUFUI1:8; /* SCUFUI1 */
+ _UDWORD SCUFUI2:8; /* SCUFUI2 */
+ } BIT; /* */
+ } ICDIPR79; /* */
+ union { /* ICDIPR80 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUFUI3:8; /* SCUFUI3 */
+ _UDWORD SCUDVI0:8; /* SCUDVI0 */
+ _UDWORD SCUDVI1:8; /* SCUDVI1 */
+ _UDWORD SCUDVI2:8; /* SCUDVI2 */
+ } BIT; /* */
+ } ICDIPR80; /* */
+ union { /* ICDIPR81 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUDVI3:8; /* SCUDVI3 */
+ _UDWORD MLBCI:8; /* MLBCI */
+ _UDWORD MLBSI:8; /* MLBSI */
+ _UDWORD DRC0:8; /* DRC0 */
+ } BIT; /* */
+ } ICDIPR81; /* */
+ union { /* ICDIPR82 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DRC1:8; /* DRC1 */
+ _UDWORD :16; /* */
+ _UDWORD LINI0_INT_T:8; /* LINI0_INT_T */
+ } BIT; /* */
+ } ICDIPR82; /* */
+ union { /* ICDIPR83 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD LINI0_INT_R:8; /* LINI0_INT_R */
+ _UDWORD LINI0_INT_S:8; /* LINI0_INT_S */
+ _UDWORD LINI0_INT_M:8; /* LINI0_INT_M */
+ _UDWORD LINI1_INT_T:8; /* LINI1_INT_T */
+ } BIT; /* */
+ } ICDIPR83; /* */
+ union { /* ICDIPR84 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD LINI1_INT_R:8; /* LINI1_INT_R */
+ _UDWORD LINI1_INT_S:8; /* LINI1_INT_S */
+ _UDWORD LINI1_INT_M:8; /* LINI1_INT_M */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDIPR84; /* */
+ _UBYTE wk9[4]; /* */
+ union { /* ICDIPR86 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD ERI0:8; /* ERI0 */
+ } BIT; /* */
+ } ICDIPR86; /* */
+ union { /* ICDIPR87 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RXI0:8; /* RXI0 */
+ _UDWORD TXI0:8; /* TXI0 */
+ _UDWORD TEI0:8; /* TEI0 */
+ _UDWORD ERI1:8; /* ERI1 */
+ } BIT; /* */
+ } ICDIPR87; /* */
+ union { /* ICDIPR88 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RXI1:8; /* RXI1 */
+ _UDWORD TXI1:8; /* TXI1 */
+ _UDWORD TEI1:8; /* TEI1 */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDIPR88; /* */
+ union { /* ICDIPR89 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD ETHERI:8; /* ETHERI */
+ } BIT; /* */
+ } ICDIPR89; /* */
+ _UBYTE wk10[4]; /* */
+ union { /* ICDIPR91 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CEUI:8; /* CEUI */
+ _UDWORD INT_CSIH0TIR:8; /* INT_CSIH0TIR */
+ _UDWORD INT_CSIH0TIRE:8; /* INT_CSIH0TIRE */
+ _UDWORD INT_CSIH1TIC:8; /* INT_CSIH1TIC */
+ } BIT; /* */
+ } ICDIPR91; /* */
+ union { /* ICDIPR92 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD INT_CSIH1TIJC:8; /* INT_CSIH1TIJC */
+ _UDWORD ECCE10:8; /* ECCE10 */
+ _UDWORD ECCE20:8; /* ECCE20 */
+ _UDWORD ECCOVF0:8; /* ECCOVF0 */
+ } BIT; /* */
+ } ICDIPR92; /* */
+ union { /* ICDIPR93 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCE11:8; /* ECCE11 */
+ _UDWORD ECCE21:8; /* ECCE21 */
+ _UDWORD ECCOVF1:8; /* ECCOVF1 */
+ _UDWORD ECCE12:8; /* ECCE12 */
+ } BIT; /* */
+ } ICDIPR93; /* */
+ union { /* ICDIPR94 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCE22:8; /* ECCE22 */
+ _UDWORD ECCOVF2:8; /* ECCOVF2 */
+ _UDWORD ECCE13:8; /* ECCE13 */
+ _UDWORD ECCE23:8; /* ECCE23 */
+ } BIT; /* */
+ } ICDIPR94; /* */
+ union { /* ICDIPR95 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCOVF3:8; /* ECCOVF3 */
+ _UDWORD H2XMLB_ERRINT:8; /* H2XMLB_ERRINT */
+ _UDWORD H2XIC1_ERRINT:8; /* H2XIC1_ERRINT */
+ _UDWORD X2HPERI1_ERRINT:8; /* X2HPERI1_ERRINT */
+ } BIT; /* */
+ } ICDIPR95; /* */
+ union { /* ICDIPR96 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD X2HPERI2_ERRINT:8; /* X2HPERI2_ERRINT */
+ _UDWORD X2HPERI34_ERRINT:8; /* X2HPERI34_ERRINT */
+ _UDWORD X2HPERI5_ERRINT:8; /* X2HPERI5_ERRINT */
+ _UDWORD X2HPERI67_ERRINT:8; /* X2HPERI67_ERRINT */
+ } BIT; /* */
+ } ICDIPR96; /* */
+ union { /* ICDIPR97 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD X2HDBGR_ERRINT:8; /* X2HDBGR_ERRINT */
+ _UDWORD PRRI:8; /* PRRI */
+ _UDWORD IFEI0:8; /* IFEI0 */
+ _UDWORD OFFI0:8; /* OFFI0 */
+ } BIT; /* */
+ } ICDIPR97; /* */
+ union { /* ICDIPR98 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PFVEI0:8; /* PFVEI0 */
+ _UDWORD IFEI1:8; /* IFEI1 */
+ _UDWORD OFFI1:8; /* OFFI1 */
+ _UDWORD PFVEI1:8; /* PFVEI1 */
+ } BIT; /* */
+ } ICDIPR98; /* */
+ _UBYTE wk11[20]; /* */
+ union { /* ICDIPR104 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT0:8; /* TINT0 */
+ _UDWORD TINT1:8; /* TINT1 */
+ _UDWORD TINT2:8; /* TINT2 */
+ _UDWORD TINT3:8; /* TINT3 */
+ } BIT; /* */
+ } ICDIPR104; /* */
+ union { /* ICDIPR105 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT4:8; /* TINT4 */
+ _UDWORD TINT5:8; /* TINT5 */
+ _UDWORD TINT6:8; /* TINT6 */
+ _UDWORD TINT7:8; /* TINT7 */
+ } BIT; /* */
+ } ICDIPR105; /* */
+ union { /* ICDIPR106 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT8:8; /* TINT8 */
+ _UDWORD TINT9:8; /* TINT9 */
+ _UDWORD TINT10:8; /* TINT10 */
+ _UDWORD TINT11:8; /* TINT11 */
+ } BIT; /* */
+ } ICDIPR106; /* */
+ union { /* ICDIPR107 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT12:8; /* TINT12 */
+ _UDWORD TINT13:8; /* TINT13 */
+ _UDWORD TINT14:8; /* TINT14 */
+ _UDWORD TINT15:8; /* TINT15 */
+ } BIT; /* */
+ } ICDIPR107; /* */
+ union { /* ICDIPR108 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT16:8; /* TINT16 */
+ _UDWORD TINT17:8; /* TINT17 */
+ _UDWORD TINT18:8; /* TINT18 */
+ _UDWORD TINT19:8; /* TINT19 */
+ } BIT; /* */
+ } ICDIPR108; /* */
+ union { /* ICDIPR109 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT20:8; /* TINT20 */
+ _UDWORD TINT21:8; /* TINT21 */
+ _UDWORD TINT22:8; /* TINT22 */
+ _UDWORD TINT23:8; /* TINT23 */
+ } BIT; /* */
+ } ICDIPR109; /* */
+ union { /* ICDIPR110 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT24:8; /* TINT24 */
+ _UDWORD TINT25:8; /* TINT25 */
+ _UDWORD TINT26:8; /* TINT26 */
+ _UDWORD TINT27:8; /* TINT27 */
+ } BIT; /* */
+ } ICDIPR110; /* */
+ union { /* ICDIPR111 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT28:8; /* TINT28 */
+ _UDWORD TINT29:8; /* TINT29 */
+ _UDWORD TINT30:8; /* TINT30 */
+ _UDWORD TINT31:8; /* TINT31 */
+ } BIT; /* */
+ } ICDIPR111; /* */
+ union { /* ICDIPR112 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT32:8; /* TINT32 */
+ _UDWORD TINT33:8; /* TINT33 */
+ _UDWORD TINT34:8; /* TINT34 */
+ _UDWORD TINT35:8; /* TINT35 */
+ } BIT; /* */
+ } ICDIPR112; /* */
+ union { /* ICDIPR113 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT36:8; /* TINT36 */
+ _UDWORD TINT37:8; /* TINT37 */
+ _UDWORD TINT38:8; /* TINT38 */
+ _UDWORD TINT39:8; /* TINT39 */
+ } BIT; /* */
+ } ICDIPR113; /* */
+ union { /* ICDIPR114 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT40:8; /* TINT40 */
+ _UDWORD TINT41:8; /* TINT41 */
+ _UDWORD TINT42:8; /* TINT42 */
+ _UDWORD TINT43:8; /* TINT43 */
+ } BIT; /* */
+ } ICDIPR114; /* */
+ union { /* ICDIPR115 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT44:8; /* TINT44 */
+ _UDWORD TINT45:8; /* TINT45 */
+ _UDWORD TINT46:8; /* TINT46 */
+ _UDWORD TINT47:8; /* TINT47 */
+ } BIT; /* */
+ } ICDIPR115; /* */
+ union { /* ICDIPR116 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT48:8; /* TINT48 */
+ _UDWORD TINT49:8; /* TINT49 */
+ _UDWORD TINT50:8; /* TINT50 */
+ _UDWORD TINT51:8; /* TINT51 */
+ } BIT; /* */
+ } ICDIPR116; /* */
+ union { /* ICDIPR117 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT52:8; /* TINT52 */
+ _UDWORD TINT53:8; /* TINT53 */
+ _UDWORD TINT54:8; /* TINT54 */
+ _UDWORD TINT55:8; /* TINT55 */
+ } BIT; /* */
+ } ICDIPR117; /* */
+ union { /* ICDIPR118 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT56:8; /* TINT56 */
+ _UDWORD TINT57:8; /* TINT57 */
+ _UDWORD TINT58:8; /* TINT58 */
+ _UDWORD TINT59:8; /* TINT59 */
+ } BIT; /* */
+ } ICDIPR118; /* */
+ union { /* ICDIPR119 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT60:8; /* TINT60 */
+ _UDWORD TINT61:8; /* TINT61 */
+ _UDWORD TINT62:8; /* TINT62 */
+ _UDWORD TINT63:8; /* TINT63 */
+ } BIT; /* */
+ } ICDIPR119; /* */
+ union { /* ICDIPR120 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT64:8; /* TINT64 */
+ _UDWORD TINT65:8; /* TINT65 */
+ _UDWORD TINT66:8; /* TINT66 */
+ _UDWORD TINT67:8; /* TINT67 */
+ } BIT; /* */
+ } ICDIPR120; /* */
+ union { /* ICDIPR121 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT68:8; /* TINT68 */
+ _UDWORD TINT69:8; /* TINT69 */
+ _UDWORD TINT70:8; /* TINT70 */
+ _UDWORD TINT71:8; /* TINT71 */
+ } BIT; /* */
+ } ICDIPR121; /* */
+ union { /* ICDIPR122 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT72:8; /* TINT72 */
+ _UDWORD TINT73:8; /* TINT73 */
+ _UDWORD TINT74:8; /* TINT74 */
+ _UDWORD TINT75:8; /* TINT75 */
+ } BIT; /* */
+ } ICDIPR122; /* */
+ union { /* ICDIPR123 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT76:8; /* TINT76 */
+ _UDWORD TINT77:8; /* TINT77 */
+ _UDWORD TINT78:8; /* TINT78 */
+ _UDWORD TINT79:8; /* TINT79 */
+ } BIT; /* */
+ } ICDIPR123; /* */
+ union { /* ICDIPR124 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT80:8; /* TINT80 */
+ _UDWORD TINT81:8; /* TINT81 */
+ _UDWORD TINT82:8; /* TINT82 */
+ _UDWORD TINT83:8; /* TINT83 */
+ } BIT; /* */
+ } ICDIPR124; /* */
+ union { /* ICDIPR125 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT84:8; /* TINT84 */
+ _UDWORD TINT85:8; /* TINT85 */
+ _UDWORD TINT86:8; /* TINT86 */
+ _UDWORD TINT87:8; /* TINT87 */
+ } BIT; /* */
+ } ICDIPR125; /* */
+ union { /* ICDIPR126 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT88:8; /* TINT88 */
+ _UDWORD TINT89:8; /* TINT89 */
+ _UDWORD TINT90:8; /* TINT90 */
+ _UDWORD TINT91:8; /* TINT91 */
+ } BIT; /* */
+ } ICDIPR126; /* */
+ union { /* ICDIPR127 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT92:8; /* TINT92 */
+ _UDWORD TINT93:8; /* TINT93 */
+ _UDWORD TINT94:8; /* TINT94 */
+ _UDWORD TINT95:8; /* TINT95 */
+ } BIT; /* */
+ } ICDIPR127; /* */
+ union { /* ICDIPR128 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT96:8; /* TINT96 */
+ _UDWORD TINT97:8; /* TINT97 */
+ _UDWORD TINT98:8; /* TINT98 */
+ _UDWORD TINT99:8; /* TINT99 */
+ } BIT; /* */
+ } ICDIPR128; /* */
+ union { /* ICDIPR129 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT100:8; /* TINT100 */
+ _UDWORD TINT101:8; /* TINT101 */
+ _UDWORD TINT102:8; /* TINT102 */
+ _UDWORD TINT103:8; /* TINT103 */
+ } BIT; /* */
+ } ICDIPR129; /* */
+ union { /* ICDIPR130 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT104:8; /* TINT104 */
+ _UDWORD TINT105:8; /* TINT105 */
+ _UDWORD TINT106:8; /* TINT106 */
+ _UDWORD TINT107:8; /* TINT107 */
+ } BIT; /* */
+ } ICDIPR130; /* */
+ union { /* ICDIPR131 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT108:8; /* TINT108 */
+ _UDWORD TINT109:8; /* TINT109 */
+ _UDWORD TINT110:8; /* TINT110 */
+ _UDWORD TINT111:8; /* TINT111 */
+ } BIT; /* */
+ } ICDIPR131; /* */
+ union { /* ICDIPR132 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT112:8; /* TINT112 */
+ _UDWORD TINT113:8; /* TINT113 */
+ _UDWORD TINT114:8; /* TINT114 */
+ _UDWORD TINT115:8; /* TINT115 */
+ } BIT; /* */
+ } ICDIPR132; /* */
+ union { /* ICDIPR133 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT116:8; /* TINT116 */
+ _UDWORD TINT117:8; /* TINT117 */
+ _UDWORD TINT118:8; /* TINT118 */
+ _UDWORD TINT119:8; /* TINT119 */
+ } BIT; /* */
+ } ICDIPR133; /* */
+ union { /* ICDIPR134 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT120:8; /* TINT120 */
+ _UDWORD TINT121:8; /* TINT121 */
+ _UDWORD TINT122:8; /* TINT122 */
+ _UDWORD TINT123:8; /* TINT123 */
+ } BIT; /* */
+ } ICDIPR134; /* */
+ union { /* ICDIPR135 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT124:8; /* TINT124 */
+ _UDWORD TINT125:8; /* TINT125 */
+ _UDWORD TINT126:8; /* TINT126 */
+ _UDWORD TINT127:8; /* TINT127 */
+ } BIT; /* */
+ } ICDIPR135; /* */
+ union { /* ICDIPR136 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT128:8; /* TINT128 */
+ _UDWORD TINT129:8; /* TINT129 */
+ _UDWORD TINT130:8; /* TINT130 */
+ _UDWORD TINT131:8; /* TINT131 */
+ } BIT; /* */
+ } ICDIPR136; /* */
+ union { /* ICDIPR137 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT132:8; /* TINT132 */
+ _UDWORD TINT133:8; /* TINT133 */
+ _UDWORD TINT134:8; /* TINT134 */
+ _UDWORD TINT135:8; /* TINT135 */
+ } BIT; /* */
+ } ICDIPR137; /* */
+ union { /* ICDIPR138 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT136:8; /* TINT136 */
+ _UDWORD TINT137:8; /* TINT137 */
+ _UDWORD TINT138:8; /* TINT138 */
+ _UDWORD TINT139:8; /* TINT139 */
+ } BIT; /* */
+ } ICDIPR138; /* */
+ union { /* ICDIPR139 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT140:8; /* TINT140 */
+ _UDWORD TINT141:8; /* TINT141 */
+ _UDWORD TINT142:8; /* TINT142 */
+ _UDWORD TINT143:8; /* TINT143 */
+ } BIT; /* */
+ } ICDIPR139; /* */
+ union { /* ICDIPR140 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT144:8; /* TINT144 */
+ _UDWORD TINT145:8; /* TINT145 */
+ _UDWORD TINT146:8; /* TINT146 */
+ _UDWORD TINT147:8; /* TINT147 */
+ } BIT; /* */
+ } ICDIPR140; /* */
+ union { /* ICDIPR141 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT148:8; /* TINT148 */
+ _UDWORD TINT149:8; /* TINT149 */
+ _UDWORD TINT150:8; /* TINT150 */
+ _UDWORD TINT151:8; /* TINT151 */
+ } BIT; /* */
+ } ICDIPR141; /* */
+ union { /* ICDIPR142 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT152:8; /* TINT152 */
+ _UDWORD TINT153:8; /* TINT153 */
+ _UDWORD TINT154:8; /* TINT154 */
+ _UDWORD TINT155:8; /* TINT155 */
+ } BIT; /* */
+ } ICDIPR142; /* */
+ union { /* ICDIPR143 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT156:8; /* TINT156 */
+ _UDWORD TINT157:8; /* TINT157 */
+ _UDWORD TINT158:8; /* TINT158 */
+ _UDWORD TINT159:8; /* TINT159 */
+ } BIT; /* */
+ } ICDIPR143; /* */
+ union { /* ICDIPR144 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT160:8; /* TINT160 */
+ _UDWORD TINT161:8; /* TINT161 */
+ _UDWORD TINT162:8; /* TINT162 */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDIPR144; /* */
+ _UBYTE wk12[444]; /* */
+ union { /* ICDIPTR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW0:8; /* SW0 */
+ _UDWORD SW1:8; /* SW1 */
+ _UDWORD SW2:8; /* SW2 */
+ _UDWORD SW3:8; /* SW3 */
+ } BIT; /* */
+ } ICDIPTR0; /* */
+ union { /* ICDIPTR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW4:8; /* SW4 */
+ _UDWORD SW5:8; /* SW5 */
+ _UDWORD SW6:8; /* SW6 */
+ _UDWORD SW7:8; /* SW7 */
+ } BIT; /* */
+ } ICDIPTR1; /* */
+ union { /* ICDIPTR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW8:8; /* SW8 */
+ _UDWORD SW9:8; /* SW9 */
+ _UDWORD SW10:8; /* SW10 */
+ _UDWORD SW11:8; /* SW11 */
+ } BIT; /* */
+ } ICDIPTR2; /* */
+ union { /* ICDIPTR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW12:8; /* SW12 */
+ _UDWORD SW13:8; /* SW13 */
+ _UDWORD SW14:8; /* SW14 */
+ _UDWORD SW15:8; /* SW15 */
+ } BIT; /* */
+ } ICDIPTR3; /* */
+ union { /* ICDIPTR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PMUIRQ0:8; /* PMUIRQ0 */
+ _UDWORD COMMRX0:8; /* COMMRX0 */
+ _UDWORD COMMTX0:8; /* COMMTX0 */
+ _UDWORD CTIIRQ0:8; /* CTIIRQ0 */
+ } BIT; /* */
+ } ICDIPTR4; /* */
+ _UBYTE wk13[12]; /* */
+ union { /* ICDIPTR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IRQ0:8; /* IRQ0 */
+ _UDWORD IRQ1:8; /* IRQ1 */
+ _UDWORD IRQ2:8; /* IRQ2 */
+ _UDWORD IRQ3:8; /* IRQ3 */
+ } BIT; /* */
+ } ICDIPTR8; /* */
+ union { /* ICDIPTR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IRQ4:8; /* IRQ4 */
+ _UDWORD IRQ5:8; /* IRQ5 */
+ _UDWORD IRQ6:8; /* IRQ6 */
+ _UDWORD IRQ7:8; /* IRQ7 */
+ } BIT; /* */
+ } ICDIPTR9; /* */
+ union { /* ICDIPTR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PL310ERR:8; /* PL310ERR */
+ _UDWORD DMAINT0:8; /* DMAINT0 */
+ _UDWORD DMAINT1:8; /* DMAINT1 */
+ _UDWORD DMAINT2:8; /* DMAINT2 */
+ } BIT; /* */
+ } ICDIPTR10; /* */
+ union { /* ICDIPTR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT3:8; /* DMAINT3 */
+ _UDWORD DMAINT4:8; /* DMAINT4 */
+ _UDWORD DMAINT5:8; /* DMAINT5 */
+ _UDWORD DMAINT6:8; /* DMAINT6 */
+ } BIT; /* */
+ } ICDIPTR11; /* */
+ union { /* ICDIPTR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT7:8; /* DMAINT7 */
+ _UDWORD DMAINT8:8; /* DMAINT8 */
+ _UDWORD DMAINT9:8; /* DMAINT9 */
+ _UDWORD DMAINT10:8; /* DMAINT10 */
+ } BIT; /* */
+ } ICDIPTR12; /* */
+ union { /* ICDIPTR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT11:8; /* DMAINT11 */
+ _UDWORD DMAINT12:8; /* DMAINT12 */
+ _UDWORD DMAINT13:8; /* DMAINT13 */
+ _UDWORD DMAINT14:8; /* DMAINT14 */
+ } BIT; /* */
+ } ICDIPTR13; /* */
+ union { /* ICDIPTR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT15:8; /* DMAINT15 */
+ _UDWORD DMAERR:8; /* DMAERR */
+ _UDWORD :16; /* */
+ } BIT; /* */
+ } ICDIPTR14; /* */
+ _UBYTE wk14[12]; /* */
+ union { /* ICDIPTR18 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD USBI0:8; /* USBI0 */
+ _UDWORD USBI1:8; /* USBI1 */
+ _UDWORD S0_VI_VSYNC0:8; /* S0_VI_VSYNC0 */
+ } BIT; /* */
+ } ICDIPTR18; /* */
+ union { /* ICDIPTR19 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_LO_VSYNC0:8; /* S0_LO_VSYNC0 */
+ _UDWORD S0_VSYNCERR0:8; /* S0_VSYNCERR0 */
+ _UDWORD GR3_VLINE0:8; /* GR3_VLINE0 */
+ _UDWORD S0_VFIELD0:8; /* S0_VFIELD0 */
+ } BIT; /* */
+ } ICDIPTR19; /* */
+ union { /* ICDIPTR20 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV1_VBUFERR0:8; /* IV1_VBUFERR0 */
+ _UDWORD IV3_VBUFERR0:8; /* IV3_VBUFERR0 */
+ _UDWORD IV5_VBUFERR0:8; /* IV5_VBUFERR0 */
+ _UDWORD IV6_VBUFERR0:8; /* IV6_VBUFERR0 */
+ } BIT; /* */
+ } ICDIPTR20; /* */
+ union { /* ICDIPTR21 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_WLINE0:8; /* S0_WLINE0 */
+ _UDWORD S1_VI_VSYNC0:8; /* S1_VI_VSYNC0 */
+ _UDWORD S1_LO_VSYNC0:8; /* S1_LO_VSYNC0 */
+ _UDWORD S1_VSYNCERR0:8; /* S1_VSYNCERR0 */
+ } BIT; /* */
+ } ICDIPTR21; /* */
+ union { /* ICDIPTR22 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S1_VFIELD0:8; /* S1_VFIELD0 */
+ _UDWORD IV2_VBUFERR0:8; /* IV2_VBUFERR0 */
+ _UDWORD IV4_VBUFERR0:8; /* IV4_VBUFERR0 */
+ _UDWORD S1_WLINE0:8; /* S1_WLINE0 */
+ } BIT; /* */
+ } ICDIPTR22; /* */
+ union { /* ICDIPTR23 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OIR_VI_VSYNC0:8; /* OIR_VI_VSYNC0 */
+ _UDWORD OIR_LO_VSYNC0:8; /* OIR_LO_VSYNC0 */
+ _UDWORD OIR_VSYNCERR0:8; /* OIR_VSYNCERR0 */
+ _UDWORD OIR_VFIELD0:8; /* OIR_VFIELD0 */
+ } BIT; /* */
+ } ICDIPTR23; /* */
+ union { /* ICDIPTR24 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV7_VBUFERR0:8; /* IV7_VBUFERR0 */
+ _UDWORD IV8_VBUFERR0:8; /* IV8_VBUFERR0 */
+ _UDWORD OIR_WLINE0:8; /* OIR_WLINE0 */
+ _UDWORD S0_VI_VSYNC1:8; /* S0_VI_VSYNC1 */
+ } BIT; /* */
+ } ICDIPTR24; /* */
+ union { /* ICDIPTR25 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_LO_VSYNC1:8; /* S0_LO_VSYNC1 */
+ _UDWORD S0_VSYNCERR1:8; /* S0_VSYNCERR1 */
+ _UDWORD GR3_VLINE1:8; /* GR3_VLINE1 */
+ _UDWORD S0_VFIELD1:8; /* S0_VFIELD1 */
+ } BIT; /* */
+ } ICDIPTR25; /* */
+ union { /* ICDIPTR26 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV1_VBUFERR1:8; /* IV1_VBUFERR1 */
+ _UDWORD IV3_VBUFERR1:8; /* IV3_VBUFERR1 */
+ _UDWORD IV5_VBUFERR1:8; /* IV5_VBUFERR1 */
+ _UDWORD IV6_VBUFERR1:8; /* IV6_VBUFERR1 */
+ } BIT; /* */
+ } ICDIPTR26; /* */
+ union { /* ICDIPTR27 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S0_WLINE1:8; /* S0_WLINE1 */
+ _UDWORD S1_VI_VSYNC1:8; /* S1_VI_VSYNC1 */
+ _UDWORD S1_LO_VSYNC1:8; /* S1_LO_VSYNC1 */
+ _UDWORD S1_VSYNCERR1:8; /* S1_VSYNCERR1 */
+ } BIT; /* */
+ } ICDIPTR27; /* */
+ union { /* ICDIPTR28 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S1_VFIELD1:8; /* S1_VFIELD1 */
+ _UDWORD IV2_VBUFERR1:8; /* IV2_VBUFERR1 */
+ _UDWORD IV4_VBUFERR1:8; /* IV4_VBUFERR1 */
+ _UDWORD S1_WLINE1:8; /* S1_WLINE1 */
+ } BIT; /* */
+ } ICDIPTR28; /* */
+ union { /* ICDIPTR29 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OIR_VI_VSYNC1:8; /* OIR_VI_VSYNC1 */
+ _UDWORD OIR_LO_VSYNC1:8; /* OIR_LO_VSYNC1 */
+ _UDWORD OIR_VLINE1:8; /* OIR_VLINE1 */
+ _UDWORD OIR_VFIELD1:8; /* OIR_VFIELD1 */
+ } BIT; /* */
+ } ICDIPTR29; /* */
+ union { /* ICDIPTR30 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV7_VBUFERR1:8; /* IV7_VBUFERR1 */
+ _UDWORD IV8_VBUFERR1:8; /* IV8_VBUFERR1 */
+ _UDWORD OIR_WLINE1:8; /* OIR_WLINE1 */
+ _UDWORD IMRDI:8; /* IMRDI */
+ } BIT; /* */
+ } ICDIPTR30; /* */
+ union { /* ICDIPTR31 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IMR2I0:8; /* IMR2I0 */
+ _UDWORD IMR2I1:8; /* IMR2I1 */
+ _UDWORD JEDI:8; /* JEDI */
+ _UDWORD JDTI:8; /* JDTI */
+ } BIT; /* */
+ } ICDIPTR31; /* */
+ union { /* ICDIPTR32 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMP0:8; /* CMP0 */
+ _UDWORD CMP1:8; /* CMP1 */
+ _UDWORD INT0:8; /* INT0 */
+ _UDWORD INT1:8; /* INT1 */
+ } BIT; /* */
+ } ICDIPTR32; /* */
+ union { /* ICDIPTR33 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD INT2:8; /* INT2 */
+ _UDWORD INT3:8; /* INT3 */
+ _UDWORD OSTMI0:8; /* OSTMI0 */
+ _UDWORD OSTMI1:8; /* OSTMI1 */
+ } BIT; /* */
+ } ICDIPTR33; /* */
+ union { /* ICDIPTR34 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMI:8; /* CMI */
+ _UDWORD WTOUT:8; /* WTOUT */
+ _UDWORD ITI:8; /* ITI */
+ _UDWORD TGI0A:8; /* TGI0A */
+ } BIT; /* */
+ } ICDIPTR34; /* */
+ union { /* ICDIPTR35 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI0B:8; /* TGI0B */
+ _UDWORD TGI0C:8; /* TGI0C */
+ _UDWORD TGI0D:8; /* TGI0D */
+ _UDWORD TGI0V:8; /* TGI0V */
+ } BIT; /* */
+ } ICDIPTR35; /* */
+ union { /* ICDIPTR36 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI0E:8; /* TGI0E */
+ _UDWORD TGI0F:8; /* TGI0F */
+ _UDWORD TGI1A:8; /* TGI1A */
+ _UDWORD TGI1B:8; /* TGI1B */
+ } BIT; /* */
+ } ICDIPTR36; /* */
+ union { /* ICDIPTR37 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI1V:8; /* TGI1V */
+ _UDWORD TGI1U:8; /* TGI1U */
+ _UDWORD TGI2A:8; /* TGI2A */
+ _UDWORD TGI2B:8; /* TGI2B */
+ } BIT; /* */
+ } ICDIPTR37; /* */
+ union { /* ICDIPTR38 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI2V:8; /* TGI2V */
+ _UDWORD TGI2U:8; /* TGI2U */
+ _UDWORD TGI3A:8; /* TGI3A */
+ _UDWORD TGI3B:8; /* TGI3B */
+ } BIT; /* */
+ } ICDIPTR38; /* */
+ union { /* ICDIPTR39 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI3C:8; /* TGI3C */
+ _UDWORD TGI3D:8; /* TGI3D */
+ _UDWORD TGI3V:8; /* TGI3V */
+ _UDWORD TGI4A:8; /* TGI4A */
+ } BIT; /* */
+ } ICDIPTR39; /* */
+ union { /* ICDIPTR40 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI4B:8; /* TGI4B */
+ _UDWORD TGI4C:8; /* TGI4C */
+ _UDWORD TGI4D:8; /* TGI4D */
+ _UDWORD TGI4V:8; /* TGI4V */
+ } BIT; /* */
+ } ICDIPTR40; /* */
+ union { /* ICDIPTR41 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMI1:8; /* CMI1 */
+ _UDWORD CMI2:8; /* CMI2 */
+ _UDWORD SGDEI0:8; /* SGDEI0 */
+ _UDWORD SGDEI1:8; /* SGDEI1 */
+ } BIT; /* */
+ } ICDIPTR41; /* */
+ union { /* ICDIPTR42 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SGDEI2:8; /* SGDEI2 */
+ _UDWORD SGDEI3:8; /* SGDEI3 */
+ _UDWORD ADI:8; /* ADI */
+ _UDWORD ADWAR:8; /* ADWAR */
+ } BIT; /* */
+ } ICDIPTR42; /* */
+ union { /* ICDIPTR43 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSII0:8; /* SSII0 */
+ _UDWORD SSIRXI0:8; /* SSIRXI0 */
+ _UDWORD SSITXI0:8; /* SSITXI0 */
+ _UDWORD SSII1:8; /* SSII1 */
+ } BIT; /* */
+ } ICDIPTR43; /* */
+ union { /* ICDIPTR44 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSIRXI1:8; /* SSIRXI1 */
+ _UDWORD SSITXI1:8; /* SSITXI1 */
+ _UDWORD SSII2:8; /* SSII2 */
+ _UDWORD SSIRTI2:8; /* SSIRTI2 */
+ } BIT; /* */
+ } ICDIPTR44; /* */
+ union { /* ICDIPTR45 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSII3:8; /* SSII3 */
+ _UDWORD SSIRXI3:8; /* SSIRXI3 */
+ _UDWORD SSITXI3:8; /* SSITXI3 */
+ _UDWORD SSII4:8; /* SSII4 */
+ } BIT; /* */
+ } ICDIPTR45; /* */
+ union { /* ICDIPTR46 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSIRTI4:8; /* SSIRTI4 */
+ _UDWORD SSII5:8; /* SSII5 */
+ _UDWORD SSIRXI5:8; /* SSIRXI5 */
+ _UDWORD SSITXI5:8; /* SSITXI5 */
+ } BIT; /* */
+ } ICDIPTR46; /* */
+ union { /* ICDIPTR47 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPDIFI:8; /* SPDIFI */
+ _UDWORD TEI0:8; /* TEI0 */
+ _UDWORD RI0:8; /* RI0 */
+ _UDWORD TI0:8; /* TI0 */
+ } BIT; /* */
+ } ICDIPTR47; /* */
+ union { /* ICDIPTR48 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI0:8; /* SPI0 */
+ _UDWORD STI0:8; /* STI0 */
+ _UDWORD NAKI0:8; /* NAKI0 */
+ _UDWORD ALI0:8; /* ALI0 */
+ } BIT; /* */
+ } ICDIPTR48; /* */
+ union { /* ICDIPTR49 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI0:8; /* TMOI0 */
+ _UDWORD TEI1:8; /* TEI1 */
+ _UDWORD RI1:8; /* RI1 */
+ _UDWORD TI1:8; /* TI1 */
+ } BIT; /* */
+ } ICDIPTR49; /* */
+ union { /* ICDIPTR50 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI1:8; /* SPI1 */
+ _UDWORD STI1:8; /* STI1 */
+ _UDWORD NAKI1:8; /* NAKI1 */
+ _UDWORD ALI1:8; /* ALI1 */
+ } BIT; /* */
+ } ICDIPTR50; /* */
+ union { /* ICDIPTR51 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI1:8; /* TMOI1 */
+ _UDWORD TEI2:8; /* TEI2 */
+ _UDWORD RI2:8; /* RI2 */
+ _UDWORD TI2:8; /* TI2 */
+ } BIT; /* */
+ } ICDIPTR51; /* */
+ union { /* ICDIPTR52 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI2:8; /* SPI2 */
+ _UDWORD STI2:8; /* STI2 */
+ _UDWORD NAKI2:8; /* NAKI2 */
+ _UDWORD ALI2:8; /* ALI2 */
+ } BIT; /* */
+ } ICDIPTR52; /* */
+ union { /* ICDIPTR53 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI2:8; /* TMOI2 */
+ _UDWORD TEI3:8; /* TEI3 */
+ _UDWORD RI3:8; /* RI3 */
+ _UDWORD TI3:8; /* TI3 */
+ } BIT; /* */
+ } ICDIPTR53; /* */
+ union { /* ICDIPTR54 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI3:8; /* SPI3 */
+ _UDWORD STI3:8; /* STI3 */
+ _UDWORD NAKI3:8; /* NAKI3 */
+ _UDWORD ALI3:8; /* ALI3 */
+ } BIT; /* */
+ } ICDIPTR54; /* */
+ union { /* ICDIPTR55 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOI3:8; /* TMOI3 */
+ _UDWORD BRI0:8; /* BRI0 */
+ _UDWORD ERI0:8; /* ERI0 */
+ _UDWORD RXI0:8; /* RXI0 */
+ } BIT; /* */
+ } ICDIPTR55; /* */
+ union { /* ICDIPTR56 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI0:8; /* TXI0 */
+ _UDWORD BRI1:8; /* BRI1 */
+ _UDWORD ERI1:8; /* ERI1 */
+ _UDWORD RXI1:8; /* RXI1 */
+ } BIT; /* */
+ } ICDIPTR56; /* */
+ union { /* ICDIPTR57 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI1:8; /* TXI1 */
+ _UDWORD BRI2:8; /* BRI2 */
+ _UDWORD ERI2:8; /* ERI2 */
+ _UDWORD RXI2:8; /* RXI2 */
+ } BIT; /* */
+ } ICDIPTR57; /* */
+ union { /* ICDIPTR58 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI2:8; /* TXI2 */
+ _UDWORD BRI3:8; /* BRI3 */
+ _UDWORD ERI3:8; /* ERI3 */
+ _UDWORD RXI3:8; /* RXI3 */
+ } BIT; /* */
+ } ICDIPTR58; /* */
+ union { /* ICDIPTR59 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI3:8; /* TXI3 */
+ _UDWORD BRI4:8; /* BRI4 */
+ _UDWORD ERI4:8; /* ERI4 */
+ _UDWORD RXI4:8; /* RXI4 */
+ } BIT; /* */
+ } ICDIPTR59; /* */
+ union { /* ICDIPTR60 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI4:8; /* TXI4 */
+ _UDWORD BRI5:8; /* BRI5 */
+ _UDWORD ERI5:8; /* ERI5 */
+ _UDWORD RXI5:8; /* RXI5 */
+ } BIT; /* */
+ } ICDIPTR60; /* */
+ union { /* ICDIPTR61 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI5:8; /* TXI5 */
+ _UDWORD BRI6:8; /* BRI6 */
+ _UDWORD ERI6:8; /* ERI6 */
+ _UDWORD RXI6:8; /* RXI6 */
+ } BIT; /* */
+ } ICDIPTR61; /* */
+ union { /* ICDIPTR62 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI6:8; /* TXI6 */
+ _UDWORD BRI7:8; /* BRI7 */
+ _UDWORD ERI7:8; /* ERI7 */
+ _UDWORD RXI7:8; /* RXI7 */
+ } BIT; /* */
+ } ICDIPTR62; /* */
+ union { /* ICDIPTR63 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI7:8; /* TXI7 */
+ _UDWORD GERI:8; /* GERI */
+ _UDWORD RFI:8; /* RFI */
+ _UDWORD CFRXI0:8; /* CFRXI0 */
+ } BIT; /* */
+ } ICDIPTR63; /* */
+ union { /* ICDIPTR64 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CERI0:8; /* CERI0 */
+ _UDWORD CTXI0:8; /* CTXI0 */
+ _UDWORD CFRXI1:8; /* CFRXI1 */
+ _UDWORD CERI1:8; /* CERI1 */
+ } BIT; /* */
+ } ICDIPTR64; /* */
+ union { /* ICDIPTR65 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CTXI1:8; /* CTXI1 */
+ _UDWORD CFRXI2:8; /* CFRXI2 */
+ _UDWORD CERI2:8; /* CERI2 */
+ _UDWORD CTXI2:8; /* CTXI2 */
+ } BIT; /* */
+ } ICDIPTR65; /* */
+ union { /* ICDIPTR66 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CFRXI3:8; /* CFRXI3 */
+ _UDWORD CERI3:8; /* CERI3 */
+ _UDWORD CTXI3:8; /* CTXI3 */
+ _UDWORD CFRXI4:8; /* CFRXI4 */
+ } BIT; /* */
+ } ICDIPTR66; /* */
+ union { /* ICDIPTR67 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CERI4:8; /* CERI4 */
+ _UDWORD CTXI4:8; /* CTXI4 */
+ _UDWORD SPEI0:8; /* SPEI0 */
+ _UDWORD SPRI0:8; /* SPRI0 */
+ } BIT; /* */
+ } ICDIPTR67; /* */
+ union { /* ICDIPTR68 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPTI0:8; /* SPTI0 */
+ _UDWORD SPEI1:8; /* SPEI1 */
+ _UDWORD SPRI1:8; /* SPRI1 */
+ _UDWORD SPTI1:8; /* SPTI1 */
+ } BIT; /* */
+ } ICDIPTR68; /* */
+ union { /* ICDIPTR69 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPEI2:8; /* SPEI2 */
+ _UDWORD SPRI2:8; /* SPRI2 */
+ _UDWORD SPTI2:8; /* SPTI2 */
+ _UDWORD SPEI3:8; /* SPEI3 */
+ } BIT; /* */
+ } ICDIPTR69; /* */
+ union { /* ICDIPTR70 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPRI3:8; /* SPRI3 */
+ _UDWORD SPTI3:8; /* SPTI3 */
+ _UDWORD SPEI4:8; /* SPEI4 */
+ _UDWORD SPRI4:8; /* SPRI4 */
+ } BIT; /* */
+ } ICDIPTR70; /* */
+ union { /* ICDIPTR71 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPTI4:8; /* SPTI4 */
+ _UDWORD IEBBTD:8; /* IEBBTD */
+ _UDWORD IEBBTERR:8; /* IEBBTERR */
+ _UDWORD IEBBTSTA:8; /* IEBBTSTA */
+ } BIT; /* */
+ } ICDIPTR71; /* */
+ union { /* ICDIPTR72 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IEBBTV:8; /* IEBBTV */
+ _UDWORD ISY:8; /* ISY */
+ _UDWORD IERR:8; /* IERR */
+ _UDWORD ITARG:8; /* ITARG */
+ } BIT; /* */
+ } ICDIPTR72; /* */
+ union { /* ICDIPTR73 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ISEC:8; /* ISEC */
+ _UDWORD IBUF:8; /* IBUF */
+ _UDWORD IREADY:8; /* IREADY */
+ _UDWORD FLSTE:8; /* FLSTE */
+ } BIT; /* */
+ } ICDIPTR73; /* */
+ union { /* ICDIPTR74 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FLTENDI:8; /* FLTENDI */
+ _UDWORD FLTREQ0I:8; /* FLTREQ0I */
+ _UDWORD FLTREQ1I:8; /* FLTREQ1I */
+ _UDWORD MMC0:8; /* MMC0 */
+ } BIT; /* */
+ } ICDIPTR74; /* */
+ union { /* ICDIPTR75 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD MMC1:8; /* MMC1 */
+ _UDWORD MMC2:8; /* MMC2 */
+ _UDWORD SDHI0_3:8; /* SDHI0_3 */
+ _UDWORD SDHI0_0:8; /* SDHI0_0 */
+ } BIT; /* */
+ } ICDIPTR75; /* */
+ union { /* ICDIPTR76 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SDHI0_1:8; /* SDHI0_1 */
+ _UDWORD SDHI1_3:8; /* SDHI1_3 */
+ _UDWORD SDHI1_0:8; /* SDHI1_0 */
+ _UDWORD SDHI1_1:8; /* SDHI1_1 */
+ } BIT; /* */
+ } ICDIPTR76; /* */
+ union { /* ICDIPTR77 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ARM:8; /* ARM */
+ _UDWORD PRD:8; /* PRD */
+ _UDWORD CUP:8; /* CUP */
+ _UDWORD SCUAI0:8; /* SCUAI0 */
+ } BIT; /* */
+ } ICDIPTR77; /* */
+ union { /* ICDIPTR78 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUAI1:8; /* SCUAI1 */
+ _UDWORD SCUFDI0:8; /* SCUFDI0 */
+ _UDWORD SCUFDI1:8; /* SCUFDI1 */
+ _UDWORD SCUFDI2:8; /* SCUFDI2 */
+ } BIT; /* */
+ } ICDIPTR78; /* */
+ union { /* ICDIPTR79 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUFDI3:8; /* SCUFDI3 */
+ _UDWORD SCUFUI0:8; /* SCUFUI0 */
+ _UDWORD SCUFUI1:8; /* SCUFUI1 */
+ _UDWORD SCUFUI2:8; /* SCUFUI2 */
+ } BIT; /* */
+ } ICDIPTR79; /* */
+ union { /* ICDIPTR80 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUFUI3:8; /* SCUFUI3 */
+ _UDWORD SCUDVI0:8; /* SCUDVI0 */
+ _UDWORD SCUDVI1:8; /* SCUDVI1 */
+ _UDWORD SCUDVI2:8; /* SCUDVI2 */
+ } BIT; /* */
+ } ICDIPTR80; /* */
+ union { /* ICDIPTR81 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUDVI3:8; /* SCUDVI3 */
+ _UDWORD MLBCI:8; /* MLBCI */
+ _UDWORD MLBSI:8; /* MLBSI */
+ _UDWORD DRC0:8; /* DRC0 */
+ } BIT; /* */
+ } ICDIPTR81; /* */
+ union { /* ICDIPTR82 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DRC1:8; /* DRC1 */
+ _UDWORD :16; /* */
+ _UDWORD LINI0_INT_T:8; /* LINI0_INT_T */
+ } BIT; /* */
+ } ICDIPTR82; /* */
+ union { /* ICDIPTR83 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD LINI0_INT_R:8; /* LINI0_INT_R */
+ _UDWORD LINI0_INT_S:8; /* LINI0_INT_S */
+ _UDWORD LINI0_INT_M:8; /* LINI0_INT_M */
+ _UDWORD LINI1_INT_T:8; /* LINI1_INT_T */
+ } BIT; /* */
+ } ICDIPTR83; /* */
+ union { /* ICDIPTR84 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD LINI1_INT_R:8; /* LINI1_INT_R */
+ _UDWORD LINI1_INT_S:8; /* LINI1_INT_S */
+ _UDWORD LINI1_INT_M:8; /* LINI1_INT_M */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDIPTR84; /* */
+ _UBYTE wk15[4]; /* */
+ union { /* ICDIPTR86 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD ERI0:8; /* ERI0 */
+ } BIT; /* */
+ } ICDIPTR86; /* */
+ union { /* ICDIPTR87 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RXI0:8; /* RXI0 */
+ _UDWORD TXI0:8; /* TXI0 */
+ _UDWORD TEI0:8; /* TEI0 */
+ _UDWORD ERI1:8; /* ERI1 */
+ } BIT; /* */
+ } ICDIPTR87; /* */
+ union { /* ICDIPTR88 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RXI1:8; /* RXI1 */
+ _UDWORD TXI1:8; /* TXI1 */
+ _UDWORD TEI1:8; /* TEI1 */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDIPTR88; /* */
+ union { /* ICDIPTR89 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :24; /* */
+ _UDWORD ETHERI:8; /* ETHERI */
+ } BIT; /* */
+ } ICDIPTR89; /* */
+ _UBYTE wk16[4]; /* */
+ union { /* ICDIPTR91 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CEUI:8; /* CEUI */
+ _UDWORD INT_CSIH0TIR:8; /* INT_CSIH0TIR */
+ _UDWORD INT_CSIH0TIRE:8; /* INT_CSIH0TIRE */
+ _UDWORD INT_CSIH1TIC:8; /* INT_CSIH1TIC */
+ } BIT; /* */
+ } ICDIPTR91; /* */
+ union { /* ICDIPTR92 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD INT_CSIH1TIJC:8; /* INT_CSIH1TIJC */
+ _UDWORD ECCE10:8; /* ECCE10 */
+ _UDWORD ECCE20:8; /* ECCE20 */
+ _UDWORD ECCOVF0:8; /* ECCOVF0 */
+ } BIT; /* */
+ } ICDIPTR92; /* */
+ union { /* ICDIPTR93 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCE11:8; /* ECCE11 */
+ _UDWORD ECCE21:8; /* ECCE21 */
+ _UDWORD ECCOVF1:8; /* ECCOVF1 */
+ _UDWORD ECCE12:8; /* ECCE12 */
+ } BIT; /* */
+ } ICDIPTR93; /* */
+ union { /* ICDIPTR94 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCE22:8; /* ECCE22 */
+ _UDWORD ECCOVF2:8; /* ECCOVF2 */
+ _UDWORD ECCE13:8; /* ECCE13 */
+ _UDWORD ECCE23:8; /* ECCE23 */
+ } BIT; /* */
+ } ICDIPTR94; /* */
+ union { /* ICDIPTR95 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCOVF3:8; /* ECCOVF3 */
+ _UDWORD H2XMLB_ERRINT:8; /* H2XMLB_ERRINT */
+ _UDWORD H2XIC1_ERRINT:8; /* H2XIC1_ERRINT */
+ _UDWORD X2HPERI1_ERRINT:8; /* X2HPERI1_ERRINT */
+ } BIT; /* */
+ } ICDIPTR95; /* */
+ union { /* ICDIPTR96 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD X2HPERI2_ERRINT:8; /* X2HPERI2_ERRINT */
+ _UDWORD X2HPERI34_ERRINT:8; /* X2HPERI34_ERRINT */
+ _UDWORD X2HPERI5_ERRINT:8; /* X2HPERI5_ERRINT */
+ _UDWORD X2HPERI67_ERRINT:8; /* X2HPERI67_ERRINT */
+ } BIT; /* */
+ } ICDIPTR96; /* */
+ union { /* ICDIPTR97 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD X2HDBGR_ERRINT:8; /* X2HDBGR_ERRINT */
+ _UDWORD PRRI:8; /* PRRI */
+ _UDWORD IFEI0:8; /* IFEI0 */
+ _UDWORD OFFI0:8; /* OFFI0 */
+ } BIT; /* */
+ } ICDIPTR97; /* */
+ union { /* ICDIPTR98 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PFVEI0:8; /* PFVEI0 */
+ _UDWORD IFEI1:8; /* IFEI1 */
+ _UDWORD OFFI1:8; /* OFFI1 */
+ _UDWORD PFVEI1:8; /* PFVEI1 */
+ } BIT; /* */
+ } ICDIPTR98; /* */
+ _UBYTE wk17[20]; /* */
+ union { /* ICDIPTR104 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT0:8; /* TINT0 */
+ _UDWORD TINT1:8; /* TINT1 */
+ _UDWORD TINT2:8; /* TINT2 */
+ _UDWORD TINT3:8; /* TINT3 */
+ } BIT; /* */
+ } ICDIPTR104; /* */
+ union { /* ICDIPTR105 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT4:8; /* TINT4 */
+ _UDWORD TINT5:8; /* TINT5 */
+ _UDWORD TINT6:8; /* TINT6 */
+ _UDWORD TINT7:8; /* TINT7 */
+ } BIT; /* */
+ } ICDIPTR105; /* */
+ union { /* ICDIPTR106 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT8:8; /* TINT8 */
+ _UDWORD TINT9:8; /* TINT9 */
+ _UDWORD TINT10:8; /* TINT10 */
+ _UDWORD TINT11:8; /* TINT11 */
+ } BIT; /* */
+ } ICDIPTR106; /* */
+ union { /* ICDIPTR107 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT12:8; /* TINT12 */
+ _UDWORD TINT13:8; /* TINT13 */
+ _UDWORD TINT14:8; /* TINT14 */
+ _UDWORD TINT15:8; /* TINT15 */
+ } BIT; /* */
+ } ICDIPTR107; /* */
+ union { /* ICDIPTR108 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT16:8; /* TINT16 */
+ _UDWORD TINT17:8; /* TINT17 */
+ _UDWORD TINT18:8; /* TINT18 */
+ _UDWORD TINT19:8; /* TINT19 */
+ } BIT; /* */
+ } ICDIPTR108; /* */
+ union { /* ICDIPTR109 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT20:8; /* TINT20 */
+ _UDWORD TINT21:8; /* TINT21 */
+ _UDWORD TINT22:8; /* TINT22 */
+ _UDWORD TINT23:8; /* TINT23 */
+ } BIT; /* */
+ } ICDIPTR109; /* */
+ union { /* ICDIPTR110 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT24:8; /* TINT24 */
+ _UDWORD TINT25:8; /* TINT25 */
+ _UDWORD TINT26:8; /* TINT26 */
+ _UDWORD TINT27:8; /* TINT27 */
+ } BIT; /* */
+ } ICDIPTR110; /* */
+ union { /* ICDIPTR111 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT28:8; /* TINT28 */
+ _UDWORD TINT29:8; /* TINT29 */
+ _UDWORD TINT30:8; /* TINT30 */
+ _UDWORD TINT31:8; /* TINT31 */
+ } BIT; /* */
+ } ICDIPTR111; /* */
+ union { /* ICDIPTR112 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT32:8; /* TINT32 */
+ _UDWORD TINT33:8; /* TINT33 */
+ _UDWORD TINT34:8; /* TINT34 */
+ _UDWORD TINT35:8; /* TINT35 */
+ } BIT; /* */
+ } ICDIPTR112; /* */
+ union { /* ICDIPTR113 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT36:8; /* TINT36 */
+ _UDWORD TINT37:8; /* TINT37 */
+ _UDWORD TINT38:8; /* TINT38 */
+ _UDWORD TINT39:8; /* TINT39 */
+ } BIT; /* */
+ } ICDIPTR113; /* */
+ union { /* ICDIPTR114 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT40:8; /* TINT40 */
+ _UDWORD TINT41:8; /* TINT41 */
+ _UDWORD TINT42:8; /* TINT42 */
+ _UDWORD TINT43:8; /* TINT43 */
+ } BIT; /* */
+ } ICDIPTR114; /* */
+ union { /* ICDIPTR115 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT44:8; /* TINT44 */
+ _UDWORD TINT45:8; /* TINT45 */
+ _UDWORD TINT46:8; /* TINT46 */
+ _UDWORD TINT47:8; /* TINT47 */
+ } BIT; /* */
+ } ICDIPTR115; /* */
+ union { /* ICDIPTR116 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT48:8; /* TINT48 */
+ _UDWORD TINT49:8; /* TINT49 */
+ _UDWORD TINT50:8; /* TINT50 */
+ _UDWORD TINT51:8; /* TINT51 */
+ } BIT; /* */
+ } ICDIPTR116; /* */
+ union { /* ICDIPTR117 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT52:8; /* TINT52 */
+ _UDWORD TINT53:8; /* TINT53 */
+ _UDWORD TINT54:8; /* TINT54 */
+ _UDWORD TINT55:8; /* TINT55 */
+ } BIT; /* */
+ } ICDIPTR117; /* */
+ union { /* ICDIPTR118 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT56:8; /* TINT56 */
+ _UDWORD TINT57:8; /* TINT57 */
+ _UDWORD TINT58:8; /* TINT58 */
+ _UDWORD TINT59:8; /* TINT59 */
+ } BIT; /* */
+ } ICDIPTR118; /* */
+ union { /* ICDIPTR119 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT60:8; /* TINT60 */
+ _UDWORD TINT61:8; /* TINT61 */
+ _UDWORD TINT62:8; /* TINT62 */
+ _UDWORD TINT63:8; /* TINT63 */
+ } BIT; /* */
+ } ICDIPTR119; /* */
+ union { /* ICDIPTR120 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT64:8; /* TINT64 */
+ _UDWORD TINT65:8; /* TINT65 */
+ _UDWORD TINT66:8; /* TINT66 */
+ _UDWORD TINT67:8; /* TINT67 */
+ } BIT; /* */
+ } ICDIPTR120; /* */
+ union { /* ICDIPTR121 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT68:8; /* TINT68 */
+ _UDWORD TINT69:8; /* TINT69 */
+ _UDWORD TINT70:8; /* TINT70 */
+ _UDWORD TINT71:8; /* TINT71 */
+ } BIT; /* */
+ } ICDIPTR121; /* */
+ union { /* ICDIPTR122 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT72:8; /* TINT72 */
+ _UDWORD TINT73:8; /* TINT73 */
+ _UDWORD TINT74:8; /* TINT74 */
+ _UDWORD TINT75:8; /* TINT75 */
+ } BIT; /* */
+ } ICDIPTR122; /* */
+ union { /* ICDIPTR123 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT76:8; /* TINT76 */
+ _UDWORD TINT77:8; /* TINT77 */
+ _UDWORD TINT78:8; /* TINT78 */
+ _UDWORD TINT79:8; /* TINT79 */
+ } BIT; /* */
+ } ICDIPTR123; /* */
+ union { /* ICDIPTR124 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT80:8; /* TINT80 */
+ _UDWORD TINT81:8; /* TINT81 */
+ _UDWORD TINT82:8; /* TINT82 */
+ _UDWORD TINT83:8; /* TINT83 */
+ } BIT; /* */
+ } ICDIPTR124; /* */
+ union { /* ICDIPTR125 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT84:8; /* TINT84 */
+ _UDWORD TINT85:8; /* TINT85 */
+ _UDWORD TINT86:8; /* TINT86 */
+ _UDWORD TINT87:8; /* TINT87 */
+ } BIT; /* */
+ } ICDIPTR125; /* */
+ union { /* ICDIPTR126 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT88:8; /* TINT88 */
+ _UDWORD TINT89:8; /* TINT89 */
+ _UDWORD TINT90:8; /* TINT90 */
+ _UDWORD TINT91:8; /* TINT91 */
+ } BIT; /* */
+ } ICDIPTR126; /* */
+ union { /* ICDIPTR127 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT92:8; /* TINT92 */
+ _UDWORD TINT93:8; /* TINT93 */
+ _UDWORD TINT94:8; /* TINT94 */
+ _UDWORD TINT95:8; /* TINT95 */
+ } BIT; /* */
+ } ICDIPTR127; /* */
+ union { /* ICDIPTR128 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT96:8; /* TINT96 */
+ _UDWORD TINT97:8; /* TINT97 */
+ _UDWORD TINT98:8; /* TINT98 */
+ _UDWORD TINT99:8; /* TINT99 */
+ } BIT; /* */
+ } ICDIPTR128; /* */
+ union { /* ICDIPTR129 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT100:8; /* TINT100 */
+ _UDWORD TINT101:8; /* TINT101 */
+ _UDWORD TINT102:8; /* TINT102 */
+ _UDWORD TINT103:8; /* TINT103 */
+ } BIT; /* */
+ } ICDIPTR129; /* */
+ union { /* ICDIPTR130 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT104:8; /* TINT104 */
+ _UDWORD TINT105:8; /* TINT105 */
+ _UDWORD TINT106:8; /* TINT106 */
+ _UDWORD TINT107:8; /* TINT107 */
+ } BIT; /* */
+ } ICDIPTR130; /* */
+ union { /* ICDIPTR131 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT108:8; /* TINT108 */
+ _UDWORD TINT109:8; /* TINT109 */
+ _UDWORD TINT110:8; /* TINT110 */
+ _UDWORD TINT111:8; /* TINT111 */
+ } BIT; /* */
+ } ICDIPTR131; /* */
+ union { /* ICDIPTR132 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT112:8; /* TINT112 */
+ _UDWORD TINT113:8; /* TINT113 */
+ _UDWORD TINT114:8; /* TINT114 */
+ _UDWORD TINT115:8; /* TINT115 */
+ } BIT; /* */
+ } ICDIPTR132; /* */
+ union { /* ICDIPTR133 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT116:8; /* TINT116 */
+ _UDWORD TINT117:8; /* TINT117 */
+ _UDWORD TINT118:8; /* TINT118 */
+ _UDWORD TINT119:8; /* TINT119 */
+ } BIT; /* */
+ } ICDIPTR133; /* */
+ union { /* ICDIPTR134 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT120:8; /* TINT120 */
+ _UDWORD TINT121:8; /* TINT121 */
+ _UDWORD TINT122:8; /* TINT122 */
+ _UDWORD TINT123:8; /* TINT123 */
+ } BIT; /* */
+ } ICDIPTR134; /* */
+ union { /* ICDIPTR135 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT124:8; /* TINT124 */
+ _UDWORD TINT125:8; /* TINT125 */
+ _UDWORD TINT126:8; /* TINT126 */
+ _UDWORD TINT127:8; /* TINT127 */
+ } BIT; /* */
+ } ICDIPTR135; /* */
+ union { /* ICDIPTR136 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT128:8; /* TINT128 */
+ _UDWORD TINT129:8; /* TINT129 */
+ _UDWORD TINT130:8; /* TINT130 */
+ _UDWORD TINT131:8; /* TINT131 */
+ } BIT; /* */
+ } ICDIPTR136; /* */
+ union { /* ICDIPTR137 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT132:8; /* TINT132 */
+ _UDWORD TINT133:8; /* TINT133 */
+ _UDWORD TINT134:8; /* TINT134 */
+ _UDWORD TINT135:8; /* TINT135 */
+ } BIT; /* */
+ } ICDIPTR137; /* */
+ union { /* ICDIPTR138 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT136:8; /* TINT136 */
+ _UDWORD TINT137:8; /* TINT137 */
+ _UDWORD TINT138:8; /* TINT138 */
+ _UDWORD TINT139:8; /* TINT139 */
+ } BIT; /* */
+ } ICDIPTR138; /* */
+ union { /* ICDIPTR139 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT140:8; /* TINT140 */
+ _UDWORD TINT141:8; /* TINT141 */
+ _UDWORD TINT142:8; /* TINT142 */
+ _UDWORD TINT143:8; /* TINT143 */
+ } BIT; /* */
+ } ICDIPTR139; /* */
+ union { /* ICDIPTR140 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT144:8; /* TINT144 */
+ _UDWORD TINT145:8; /* TINT145 */
+ _UDWORD TINT146:8; /* TINT146 */
+ _UDWORD TINT147:8; /* TINT147 */
+ } BIT; /* */
+ } ICDIPTR140; /* */
+ union { /* ICDIPTR141 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT148:8; /* TINT148 */
+ _UDWORD TINT149:8; /* TINT149 */
+ _UDWORD TINT150:8; /* TINT150 */
+ _UDWORD TINT151:8; /* TINT151 */
+ } BIT; /* */
+ } ICDIPTR141; /* */
+ union { /* ICDIPTR142 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT152:8; /* TINT152 */
+ _UDWORD TINT153:8; /* TINT153 */
+ _UDWORD TINT154:8; /* TINT154 */
+ _UDWORD TINT155:8; /* TINT155 */
+ } BIT; /* */
+ } ICDIPTR142; /* */
+ union { /* ICDIPTR143 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT156:8; /* TINT156 */
+ _UDWORD TINT157:8; /* TINT157 */
+ _UDWORD TINT158:8; /* TINT158 */
+ _UDWORD TINT159:8; /* TINT159 */
+ } BIT; /* */
+ } ICDIPTR143; /* */
+ union { /* ICDIPTR144 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT160:8; /* TINT160 */
+ _UDWORD TINT161:8; /* TINT161 */
+ _UDWORD TINT162:8; /* TINT162 */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDIPTR144; /* */
+ _UBYTE wk18[444]; /* */
+ union { /* ICDICFR */
+ _UDWORD LONG[36]; /* Long Access */
+ struct { /* ICDICFRn */
+ union { /* ICDICFR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SW0_0:1; /* SW0[0] */
+ _UDWORD SW0_1:1; /* SW0[1] */
+ _UDWORD SW1_0:1; /* SW1[0] */
+ _UDWORD SW1_1:1; /* SW1[1] */
+ _UDWORD SW2_0:1; /* SW2[0] */
+ _UDWORD SW2_1:1; /* SW2[1] */
+ _UDWORD SW3_0:1; /* SW3[0] */
+ _UDWORD SW3_1:1; /* SW3[1] */
+ _UDWORD SW4_0:1; /* SW4[0] */
+ _UDWORD SW4_1:1; /* SW4[1] */
+ _UDWORD SW5_0:1; /* SW5[0] */
+ _UDWORD SW5_1:1; /* SW5[1] */
+ _UDWORD SW6_0:1; /* SW6[0] */
+ _UDWORD SW6_1:1; /* SW6[1] */
+ _UDWORD SW7_0:1; /* SW7[0] */
+ _UDWORD SW7_1:1; /* SW7[1] */
+ _UDWORD SW8_0:1; /* SW8[0] */
+ _UDWORD SW8_1:1; /* SW8[1] */
+ _UDWORD SW9_0:1; /* SW9[0] */
+ _UDWORD SW9_1:1; /* SW9[1] */
+ _UDWORD SW10_0:1; /* SW10[0] */
+ _UDWORD SW10_1:1; /* SW10[1] */
+ _UDWORD SW11_0:1; /* SW11[0] */
+ _UDWORD SW11_1:1; /* SW11[1] */
+ _UDWORD SW12_0:1; /* SW12[0] */
+ _UDWORD SW12_1:1; /* SW12[1] */
+ _UDWORD SW13_0:1; /* SW13[0] */
+ _UDWORD SW13_1:1; /* SW13[1] */
+ _UDWORD SW14_0:1; /* SW14[0] */
+ _UDWORD SW14_1:1; /* SW14[1] */
+ _UDWORD SW15_0:1; /* SW15[0] */
+ _UDWORD SW15_1:1; /* SW15[1] */
+ } BIT; /* */
+ } ICDICFR0; /* */
+ union { /* ICDICFR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PMUIRQ0_0:1; /* PMUIRQ0[0] */
+ _UDWORD PMUIRQ0_1:1; /* PMUIRQ0[1] */
+ _UDWORD COMMRX0_0:1; /* COMMRX0[0] */
+ _UDWORD COMMRX0_1:1; /* COMMRX0[1] */
+ _UDWORD COMMTX0_0:1; /* COMMTX0[0] */
+ _UDWORD COMMTX0_1:1; /* COMMTX0[1] */
+ _UDWORD CTIIRQ0_0:1; /* CTIIRQ0[0] */
+ _UDWORD CTIIRQ0_1:1; /* CTIIRQ0[1] */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } ICDICFR1; /* */
+ union { /* ICDICFR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IRQ0_0:1; /* IRQ0[0] */
+ _UDWORD IRQ0_1:1; /* IRQ0[1] */
+ _UDWORD IRQ1_0:1; /* IRQ1[0] */
+ _UDWORD IRQ1_1:1; /* IRQ1[1] */
+ _UDWORD IRQ2_0:1; /* IRQ2[0] */
+ _UDWORD IRQ2_1:1; /* IRQ2[1] */
+ _UDWORD IRQ3_0:1; /* IRQ3[0] */
+ _UDWORD IRQ3_1:1; /* IRQ3[1] */
+ _UDWORD IRQ4_0:1; /* IRQ4[0] */
+ _UDWORD IRQ4_1:1; /* IRQ4[1] */
+ _UDWORD IRQ5_0:1; /* IRQ5[0] */
+ _UDWORD IRQ5_1:1; /* IRQ5[1] */
+ _UDWORD IRQ6_0:1; /* IRQ6[0] */
+ _UDWORD IRQ6_1:1; /* IRQ6[1] */
+ _UDWORD IRQ7_0:1; /* IRQ7[0] */
+ _UDWORD IRQ7_1:1; /* IRQ7[1] */
+ _UDWORD PL310ERR_0:1; /* PL310ERR[0] */
+ _UDWORD PL310ERR_1:1; /* PL310ERR[1] */
+ _UDWORD DMAINT0_0:1; /* DMAINT0[0] */
+ _UDWORD DMAINT0_1:1; /* DMAINT0[1] */
+ _UDWORD DMAINT1_0:1; /* DMAINT1[0] */
+ _UDWORD DMAINT1_1:1; /* DMAINT1[1] */
+ _UDWORD DMAINT2_0:1; /* DMAINT2[0] */
+ _UDWORD DMAINT2_1:1; /* DMAINT2[1] */
+ _UDWORD DMAINT3_0:1; /* DMAINT3[0] */
+ _UDWORD DMAINT3_1:1; /* DMAINT3[1] */
+ _UDWORD DMAINT4_0:1; /* DMAINT4[0] */
+ _UDWORD DMAINT4_1:1; /* DMAINT4[1] */
+ _UDWORD DMAINT5_0:1; /* DMAINT5[0] */
+ _UDWORD DMAINT5_1:1; /* DMAINT5[1] */
+ _UDWORD DMAINT6_0:1; /* DMAINT6[0] */
+ _UDWORD DMAINT6_1:1; /* DMAINT6[1] */
+ } BIT; /* */
+ } ICDICFR2; /* */
+ union { /* ICDICFR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMAINT7_0:1; /* DMAINT7[0] */
+ _UDWORD DMAINT7_1:1; /* DMAINT7[1] */
+ _UDWORD DMAINT8_0:1; /* DMAINT8[0] */
+ _UDWORD DMAINT8_1:1; /* DMAINT8[1] */
+ _UDWORD DMAINT9_0:1; /* DMAINT9[0] */
+ _UDWORD DMAINT9_1:1; /* DMAINT9[1] */
+ _UDWORD DMAINT10_0:1; /* DMAINT10[0] */
+ _UDWORD DMAINT10_1:1; /* DMAINT10[1] */
+ _UDWORD DMAINT11_0:1; /* DMAINT11[0] */
+ _UDWORD DMAINT11_1:1; /* DMAINT11[1] */
+ _UDWORD DMAINT12_0:1; /* DMAINT12[0] */
+ _UDWORD DMAINT12_1:1; /* DMAINT12[1] */
+ _UDWORD DMAINT13_0:1; /* DMAINT13[0] */
+ _UDWORD DMAINT13_1:1; /* DMAINT13[1] */
+ _UDWORD DMAINT14_0:1; /* DMAINT14[0] */
+ _UDWORD DMAINT14_1:1; /* DMAINT14[1] */
+ _UDWORD DMAINT15_0:1; /* DMAINT15[0] */
+ _UDWORD DMAINT15_1:1; /* DMAINT15[1] */
+ _UDWORD DMAERR_0:1; /* DMAERR[0] */
+ _UDWORD DMAERR_1:1; /* DMAERR[1] */
+ _UDWORD :12; /* */
+ } BIT; /* */
+ } ICDICFR3; /* */
+ union { /* ICDICFR4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :18; /* */
+ _UDWORD USBI0_0:1; /* USBI0[0] */
+ _UDWORD USBI0_1:1; /* USBI0[1] */
+ _UDWORD USBI1_0:1; /* USBI1[0] */
+ _UDWORD USBI1_1:1; /* USBI1[1] */
+ _UDWORD S0_VI_VSYNC0_0:1;/* S0_VI_VSYNC0[0] */
+ _UDWORD S0_VI_VSYNC0_1:1;/* S0_VI_VSYNC0[1] */
+ _UDWORD S0_LO_VSYNC0_0:1;/* S0_LO_VSYNC0[0] */
+ _UDWORD S0_LO_VSYNC0_1:1;/* S0_LO_VSYNC0[1] */
+ _UDWORD S0_VSYNCERR0_0:1;/* S0_VSYNCERR0[0] */
+ _UDWORD S0_VSYNCERR0_1:1;/* S0_VSYNCERR0[1] */
+ _UDWORD GR3_VLINE0_0:1;/* GR3_VLINE0[0] */
+ _UDWORD GR3_VLINE0_1:1;/* GR3_VLINE0[1] */
+ _UDWORD S0_VFIELD0_0:1;/* S0_VFIELD0[0] */
+ _UDWORD S0_VFIELD0_1:1;/* S0_VFIELD0[1] */
+ } BIT; /* */
+ } ICDICFR4; /* */
+ union { /* ICDICFR5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV1_VBUFERR0_0:1;/* IV1_VBUFERR0[0] */
+ _UDWORD IV1_VBUFERR0_1:1;/* IV1_VBUFERR0[1] */
+ _UDWORD IV3_VBUFERR0_0:1;/* IV3_VBUFERR0[0] */
+ _UDWORD IV3_VBUFERR0_1:1;/* IV3_VBUFERR0[1] */
+ _UDWORD IV5_VBUFERR0_0:1;/* IV5_VBUFERR0[0] */
+ _UDWORD IV5_VBUFERR0_1:1;/* IV5_VBUFERR0[1] */
+ _UDWORD IV6_VBUFERR0_0:1;/* IV6_VBUFERR0[0] */
+ _UDWORD IV6_VBUFERR0_1:1;/* IV6_VBUFERR0[1] */
+ _UDWORD S0_WLINE0_0:1;/* S0_WLINE0[0] */
+ _UDWORD S0_WLINE0_1:1;/* S0_WLINE0[1] */
+ _UDWORD S1_VI_VSYNC0_0:1;/* S1_VI_VSYNC0[0] */
+ _UDWORD S1_VI_VSYNC0_1:1;/* S1_VI_VSYNC0[1] */
+ _UDWORD S1_LO_VSYNC0_0:1;/* S1_LO_VSYNC0[0] */
+ _UDWORD S1_LO_VSYNC0_1:1;/* S1_LO_VSYNC0[1] */
+ _UDWORD S1_VSYNCERR0_0:1;/* S1_VSYNCERR0[0] */
+ _UDWORD S1_VSYNCERR0_1:1;/* S1_VSYNCERR0[1] */
+ _UDWORD S1_VFIELD0_0:1;/* S1_VFIELD0[0] */
+ _UDWORD S1_VFIELD0_1:1;/* S1_VFIELD0[1] */
+ _UDWORD IV2_VBUFERR0_0:1;/* IV2_VBUFERR0[0] */
+ _UDWORD IV2_VBUFERR0_1:1;/* IV2_VBUFERR0[1] */
+ _UDWORD IV4_VBUFERR0_0:1;/* IV4_VBUFERR0[0] */
+ _UDWORD IV4_VBUFERR0_1:1;/* IV4_VBUFERR0[1] */
+ _UDWORD S1_WLINE0_0:1;/* S1_WLINE0[0] */
+ _UDWORD S1_WLINE0_1:1;/* S1_WLINE0[1] */
+ _UDWORD OIR_VI_VSYNC0_0:1;/* OIR_VI_VSYNC0[0] */
+ _UDWORD OIR_VI_VSYNC0_1:1;/* OIR_VI_VSYNC0[1] */
+ _UDWORD OIR_LO_VSYNC0_0:1;/* OIR_LO_VSYNC0[0] */
+ _UDWORD OIR_LO_VSYNC0_1:1;/* OIR_LO_VSYNC0[1] */
+ _UDWORD OIR_VSYNCERR0_0:1;/* OIR_VSYNCERR0[0] */
+ _UDWORD OIR_VSYNCERR0_1:1;/* OIR_VSYNCERR0[1] */
+ _UDWORD OIR_VFIELD0_0:1;/* OIR_VFIELD0[0] */
+ _UDWORD OIR_VFIELD0_1:1;/* OIR_VFIELD0[1] */
+ } BIT; /* */
+ } ICDICFR5; /* */
+ union { /* ICDICFR6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IV7_VBUFERR0_0:1;/* IV7_VBUFERR0[0] */
+ _UDWORD IV7_VBUFERR0_1:1;/* IV7_VBUFERR0[1] */
+ _UDWORD IV8_VBUFERR0_0:1;/* IV8_VBUFERR0[0] */
+ _UDWORD IV8_VBUFERR0_1:1;/* IV8_VBUFERR0[1] */
+ _UDWORD OIR_WLINE0_0:1;/* OIR_WLINE0[0] */
+ _UDWORD OIR_WLINE0_1:1;/* OIR_WLINE0[1] */
+ _UDWORD S0_VI_VSYNC1_0:1;/* S0_VI_VSYNC1[0] */
+ _UDWORD S0_VI_VSYNC1_1:1;/* S0_VI_VSYNC1[1] */
+ _UDWORD S0_LO_VSYNC1_0:1;/* S0_LO_VSYNC1[0] */
+ _UDWORD S0_LO_VSYNC1_1:1;/* S0_LO_VSYNC1[1] */
+ _UDWORD S0_VSYNCERR1_0:1;/* S0_VSYNCERR1[0] */
+ _UDWORD S0_VSYNCERR1_1:1;/* S0_VSYNCERR1[1] */
+ _UDWORD GR3_VLINE1_0:1;/* GR3_VLINE1[0] */
+ _UDWORD GR3_VLINE1_1:1;/* GR3_VLINE1[1] */
+ _UDWORD S0_VFIELD1_0:1;/* S0_VFIELD1[0] */
+ _UDWORD S0_VFIELD1_1:1;/* S0_VFIELD1[1] */
+ _UDWORD IV1_VBUFERR1_0:1;/* IV1_VBUFERR1[0] */
+ _UDWORD IV1_VBUFERR1_1:1;/* IV1_VBUFERR1[1] */
+ _UDWORD IV3_VBUFERR1_0:1;/* IV3_VBUFERR1[0] */
+ _UDWORD IV3_VBUFERR1_1:1;/* IV3_VBUFERR1[1] */
+ _UDWORD IV5_VBUFERR1_0:1;/* IV5_VBUFERR1[0] */
+ _UDWORD IV5_VBUFERR1_1:1;/* IV5_VBUFERR1[1] */
+ _UDWORD IV6_VBUFERR1_0:1;/* IV6_VBUFERR1[0] */
+ _UDWORD IV6_VBUFERR1_1:1;/* IV6_VBUFERR1[1] */
+ _UDWORD S0_WLINE1_0:1;/* S0_WLINE1[0] */
+ _UDWORD S0_WLINE1_1:1;/* S0_WLINE1[1] */
+ _UDWORD S1_VI_VSYNC1_0:1;/* S1_VI_VSYNC1[0] */
+ _UDWORD S1_VI_VSYNC1_1:1;/* S1_VI_VSYNC1[1] */
+ _UDWORD S1_LO_VSYNC1_0:1;/* S1_LO_VSYNC1[0] */
+ _UDWORD S1_LO_VSYNC1_1:1;/* S1_LO_VSYNC1[1] */
+ _UDWORD S1_VSYNCERR1_0:1;/* S1_VSYNCERR1[0] */
+ _UDWORD S1_VSYNCERR1_1:1;/* S1_VSYNCERR1[1] */
+ } BIT; /* */
+ } ICDICFR6; /* */
+ union { /* ICDICFR7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD S1_VFIELD1_0:1;/* S1_VFIELD1[0] */
+ _UDWORD S1_VFIELD1_1:1;/* S1_VFIELD1[1] */
+ _UDWORD IV2_VBUFERR1_0:1;/* IV2_VBUFERR1[0] */
+ _UDWORD IV2_VBUFERR1_1:1;/* IV2_VBUFERR1[1] */
+ _UDWORD IV4_VBUFERR1_0:1;/* IV4_VBUFERR1[0] */
+ _UDWORD IV4_VBUFERR1_1:1;/* IV4_VBUFERR1[1] */
+ _UDWORD S1_WLINE1_0:1;/* S1_WLINE1[0] */
+ _UDWORD S1_WLINE1_1:1;/* S1_WLINE1[1] */
+ _UDWORD OIR_VI_VSYNC1_0:1;/* OIR_VI_VSYNC1[0] */
+ _UDWORD OIR_VI_VSYNC1_1:1;/* OIR_VI_VSYNC1[1] */
+ _UDWORD OIR_LO_VSYNC1_0:1;/* OIR_LO_VSYNC1[0] */
+ _UDWORD OIR_LO_VSYNC1_1:1;/* OIR_LO_VSYNC1[1] */
+ _UDWORD OIR_VLINE1_0:1;/* OIR_VLINE1[0] */
+ _UDWORD OIR_VLINE1_1:1;/* OIR_VLINE1[1] */
+ _UDWORD OIR_VFIELD1_0:1;/* OIR_VFIELD1[0] */
+ _UDWORD OIR_VFIELD1_1:1;/* OIR_VFIELD1[1] */
+ _UDWORD IV7_VBUFERR1_0:1;/* IV7_VBUFERR1[0] */
+ _UDWORD IV7_VBUFERR1_1:1;/* IV7_VBUFERR1[1] */
+ _UDWORD IV8_VBUFERR1_0:1;/* IV8_VBUFERR1[0] */
+ _UDWORD IV8_VBUFERR1_1:1;/* IV8_VBUFERR1[1] */
+ _UDWORD OIR_WLINE1_0:1;/* OIR_WLINE1[0] */
+ _UDWORD OIR_WLINE1_1:1;/* OIR_WLINE1[1] */
+ _UDWORD IMRDI_0:1; /* IMRDI[0] */
+ _UDWORD IMRDI_1:1; /* IMRDI[1] */
+ _UDWORD IMR2I0_0:1; /* IMR2I0[0] */
+ _UDWORD IMR2I0_1:1; /* IMR2I0[1] */
+ _UDWORD IMR2I1_0:1; /* IMR2I1[0] */
+ _UDWORD IMR2I1_1:1; /* IMR2I1[1] */
+ _UDWORD JEDI_0:1; /* JEDI[0] */
+ _UDWORD JEDI_1:1; /* JEDI[1] */
+ _UDWORD JDTI_0:1; /* JDTI[0] */
+ _UDWORD JDTI_1:1; /* JDTI[1] */
+ } BIT; /* */
+ } ICDICFR7; /* */
+ union { /* ICDICFR8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CMP0_0:1; /* CMP0[0] */
+ _UDWORD CMP0_1:1; /* CMP0[1] */
+ _UDWORD CMP1_0:1; /* CMP1[0] */
+ _UDWORD CMP1_1:1; /* CMP1[1] */
+ _UDWORD INT0_0:1; /* INT0[0] */
+ _UDWORD INT0_1:1; /* INT0[1] */
+ _UDWORD INT1_0:1; /* INT1[0] */
+ _UDWORD INT1_1:1; /* INT1[1] */
+ _UDWORD INT2_0:1; /* INT2[0] */
+ _UDWORD INT2_1:1; /* INT2[1] */
+ _UDWORD INT3_0:1; /* INT3[0] */
+ _UDWORD INT3_1:1; /* INT3[1] */
+ _UDWORD OSTMI0_0:1; /* OSTMI0[0] */
+ _UDWORD OSTMI0_1:1; /* OSTMI0[1] */
+ _UDWORD OSTMI1_0:1; /* OSTMI1[0] */
+ _UDWORD OSTMI1_1:1; /* OSTMI1[1] */
+ _UDWORD CMI_0:1; /* CMI[0] */
+ _UDWORD CMI_1:1; /* CMI[1] */
+ _UDWORD WTOUT_0:1; /* WTOUT[0] */
+ _UDWORD WTOUT_1:1; /* WTOUT[1] */
+ _UDWORD ITI_0:1; /* ITI[0] */
+ _UDWORD ITI_1:1; /* ITI[1] */
+ _UDWORD TGI0A_0:1; /* TGI0A[0] */
+ _UDWORD TGI0A_1:1; /* TGI0A[1] */
+ _UDWORD TGI0B_0:1; /* TGI0B[0] */
+ _UDWORD TGI0B_1:1; /* TGI0B[1] */
+ _UDWORD TGI0C_0:1; /* TGI0C[0] */
+ _UDWORD TGI0C_1:1; /* TGI0C[1] */
+ _UDWORD TGI0D_0:1; /* TGI0D[0] */
+ _UDWORD TGI0D_1:1; /* TGI0D[1] */
+ _UDWORD TGI0V_0:1; /* TGI0V[0] */
+ _UDWORD TGI0V_1:1; /* TGI0V[1] */
+ } BIT; /* */
+ } ICDICFR8; /* */
+ union { /* ICDICFR9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI0E_0:1; /* TGI0E[0] */
+ _UDWORD TGI0E_1:1; /* TGI0E[1] */
+ _UDWORD TGI0F_0:1; /* TGI0F[0] */
+ _UDWORD TGI0F_1:1; /* TGI0F[1] */
+ _UDWORD TGI1A_0:1; /* TGI1A[0] */
+ _UDWORD TGI1A_1:1; /* TGI1A[1] */
+ _UDWORD TGI1B_0:1; /* TGI1B[0] */
+ _UDWORD TGI1B_1:1; /* TGI1B[1] */
+ _UDWORD TGI1V_0:1; /* TGI1V[0] */
+ _UDWORD TGI1V_1:1; /* TGI1V[1] */
+ _UDWORD TGI1U_0:1; /* TGI1U[0] */
+ _UDWORD TGI1U_1:1; /* TGI1U[1] */
+ _UDWORD TGI2A_0:1; /* TGI2A[0] */
+ _UDWORD TGI2A_1:1; /* TGI2A[1] */
+ _UDWORD TGI2B_0:1; /* TGI2B[0] */
+ _UDWORD TGI2B_1:1; /* TGI2B[1] */
+ _UDWORD TGI2V_0:1; /* TGI2V[0] */
+ _UDWORD TGI2V_1:1; /* TGI2V[1] */
+ _UDWORD TGI2U_0:1; /* TGI2U[0] */
+ _UDWORD TGI2U_1:1; /* TGI2U[1] */
+ _UDWORD TGI3A_0:1; /* TGI3A[0] */
+ _UDWORD TGI3A_1:1; /* TGI3A[1] */
+ _UDWORD TGI3B_0:1; /* TGI3B[0] */
+ _UDWORD TGI3B_1:1; /* TGI3B[1] */
+ _UDWORD TGI3C_0:1; /* TGI3C[0] */
+ _UDWORD TGI3C_1:1; /* TGI3C[1] */
+ _UDWORD TGI3D_0:1; /* TGI3D[0] */
+ _UDWORD TGI3D_1:1; /* TGI3D[1] */
+ _UDWORD TGI3V_0:1; /* TGI3V[0] */
+ _UDWORD TGI3V_1:1; /* TGI3V[1] */
+ _UDWORD TGI4A_0:1; /* TGI4A[0] */
+ _UDWORD TGI4A_1:1; /* TGI4A[1] */
+ } BIT; /* */
+ } ICDICFR9; /* */
+ union { /* ICDICFR10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TGI4B_0:1; /* TGI4B[0] */
+ _UDWORD TGI4B_1:1; /* TGI4B[1] */
+ _UDWORD TGI4C_0:1; /* TGI4C[0] */
+ _UDWORD TGI4C_1:1; /* TGI4C[1] */
+ _UDWORD TGI4D_0:1; /* TGI4D[0] */
+ _UDWORD TGI4D_1:1; /* TGI4D[1] */
+ _UDWORD TGI4V_0:1; /* TGI4V[0] */
+ _UDWORD TGI4V_1:1; /* TGI4V[1] */
+ _UDWORD CMI1_0:1; /* CMI1[0] */
+ _UDWORD CMI1_1:1; /* CMI1[1] */
+ _UDWORD CMI2_0:1; /* CMI2[0] */
+ _UDWORD CMI2_1:1; /* CMI2[1] */
+ _UDWORD SGDEI0_0:1; /* SGDEI0[0] */
+ _UDWORD SGDEI0_1:1; /* SGDEI0[1] */
+ _UDWORD SGDEI1_0:1; /* SGDEI1[0] */
+ _UDWORD SGDEI1_1:1; /* SGDEI1[1] */
+ _UDWORD SGDEI2_0:1; /* SGDEI2[0] */
+ _UDWORD SGDEI2_1:1; /* SGDEI2[1] */
+ _UDWORD SGDEI3_0:1; /* SGDEI3[0] */
+ _UDWORD SGDEI3_1:1; /* SGDEI3[1] */
+ _UDWORD ADI_0:1; /* ADI[0] */
+ _UDWORD ADI_1:1; /* ADI[1] */
+ _UDWORD ADWAR_0:1; /* ADWAR[0] */
+ _UDWORD ADWAR_1:1; /* ADWAR[1] */
+ _UDWORD SSII0_0:1; /* SSII0[0] */
+ _UDWORD SSII0_1:1; /* SSII0[1] */
+ _UDWORD SSIRXI0_0:1; /* SSIRXI0[0] */
+ _UDWORD SSIRXI0_1:1; /* SSIRXI0[1] */
+ _UDWORD SSITXI0_0:1; /* SSITXI0[0] */
+ _UDWORD SSITXI0_1:1; /* SSITXI0[1] */
+ _UDWORD SSII1_0:1; /* SSII1[0] */
+ _UDWORD SSII1_1:1; /* SSII1[1] */
+ } BIT; /* */
+ } ICDICFR10; /* */
+ union { /* ICDICFR11 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSIRXI1_0:1; /* SSIRXI1[0] */
+ _UDWORD SSIRXI1_1:1; /* SSIRXI1[1] */
+ _UDWORD SSITXI1_0:1; /* SSITXI1[0] */
+ _UDWORD SSITXI1_1:1; /* SSITXI1[1] */
+ _UDWORD SSII2_0:1; /* SSII2[0] */
+ _UDWORD SSII2_1:1; /* SSII2[1] */
+ _UDWORD SSIRTI2_0:1; /* SSIRTI2[0] */
+ _UDWORD SSIRTI2_1:1; /* SSIRTI2[1] */
+ _UDWORD SSII3_0:1; /* SSII3[0] */
+ _UDWORD SSII3_1:1; /* SSII3[1] */
+ _UDWORD SSIRXI3_0:1; /* SSIRXI3[0] */
+ _UDWORD SSIRXI3_1:1; /* SSIRXI3[1] */
+ _UDWORD SSITXI3_0:1; /* SSITXI3[0] */
+ _UDWORD SSITXI3_1:1; /* SSITXI3[1] */
+ _UDWORD SSII4_0:1; /* SSII4[0] */
+ _UDWORD SSII4_1:1; /* SSII4[1] */
+ _UDWORD SSIRTI4_0:1; /* SSIRTI4[0] */
+ _UDWORD SSIRTI4_1:1; /* SSIRTI4[1] */
+ _UDWORD SSII5_0:1; /* SSII5[0] */
+ _UDWORD SSII5_1:1; /* SSII5[1] */
+ _UDWORD SSIRXI5_0:1; /* SSIRXI5[0] */
+ _UDWORD SSIRXI5_1:1; /* SSIRXI5[1] */
+ _UDWORD SSITXI5_0:1; /* SSITXI5[0] */
+ _UDWORD SSITXI5_1:1; /* SSITXI5[1] */
+ _UDWORD SPDIFI_0:1; /* SPDIFI[0] */
+ _UDWORD SPDIFI_1:1; /* SPDIFI[1] */
+ _UDWORD TEI0_0:1; /* TEI0[0] */
+ _UDWORD TEI0_1:1; /* TEI0[1] */
+ _UDWORD RI0_0:1; /* RI0[0] */
+ _UDWORD RI0_1:1; /* RI0[1] */
+ _UDWORD TI0_0:1; /* TI0[0] */
+ _UDWORD TI0_1:1; /* TI0[1] */
+ } BIT; /* */
+ } ICDICFR11; /* */
+ union { /* ICDICFR12 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI0_0:1; /* SPI0[0] */
+ _UDWORD SPI0_1:1; /* SPI0[1] */
+ _UDWORD STI0_0:1; /* STI0[0] */
+ _UDWORD STI0_1:1; /* STI0[1] */
+ _UDWORD NAKI0_0:1; /* NAKI0[0] */
+ _UDWORD NAKI0_1:1; /* NAKI0[1] */
+ _UDWORD ALI0_0:1; /* ALI0[0] */
+ _UDWORD ALI0_1:1; /* ALI0[1] */
+ _UDWORD TMOI0_0:1; /* TMOI0[0] */
+ _UDWORD TMOI0_1:1; /* TMOI0[1] */
+ _UDWORD TEI1_0:1; /* TEI1[0] */
+ _UDWORD TEI1_1:1; /* TEI1[1] */
+ _UDWORD RI1_0:1; /* RI1[0] */
+ _UDWORD RI1_1:1; /* RI1[1] */
+ _UDWORD TI1_0:1; /* TI1[0] */
+ _UDWORD TI1_1:1; /* TI1[1] */
+ _UDWORD SPI1_0:1; /* SPI1[0] */
+ _UDWORD SPI1_1:1; /* SPI1[1] */
+ _UDWORD STI1_0:1; /* STI1[0] */
+ _UDWORD STI1_1:1; /* STI1[1] */
+ _UDWORD NAKI1_0:1; /* NAKI1[0] */
+ _UDWORD NAKI1_1:1; /* NAKI1[1] */
+ _UDWORD ALI1_0:1; /* ALI1[0] */
+ _UDWORD ALI1_1:1; /* ALI1[1] */
+ _UDWORD TMOI1_0:1; /* TMOI1[0] */
+ _UDWORD TMOI1_1:1; /* TMOI1[1] */
+ _UDWORD TEI2_0:1; /* TEI2[0] */
+ _UDWORD TEI2_1:1; /* TEI2[1] */
+ _UDWORD RI2_0:1; /* RI2[0] */
+ _UDWORD RI2_1:1; /* RI2[1] */
+ _UDWORD TI2_0:1; /* TI2[0] */
+ _UDWORD TI2_1:1; /* TI2[1] */
+ } BIT; /* */
+ } ICDICFR12; /* */
+ union { /* ICDICFR13 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPI2_0:1; /* SPI2[0] */
+ _UDWORD SPI2_1:1; /* SPI2[1] */
+ _UDWORD STI2_0:1; /* STI2[0] */
+ _UDWORD STI2_1:1; /* STI2[1] */
+ _UDWORD NAKI2_0:1; /* NAKI2[0] */
+ _UDWORD NAKI2_1:1; /* NAKI2[1] */
+ _UDWORD ALI2_0:1; /* ALI2[0] */
+ _UDWORD ALI2_1:1; /* ALI2[1] */
+ _UDWORD TMOI2_0:1; /* TMOI2[0] */
+ _UDWORD TMOI2_1:1; /* TMOI2[1] */
+ _UDWORD TEI3_0:1; /* TEI3[0] */
+ _UDWORD TEI3_1:1; /* TEI3[1] */
+ _UDWORD RI3_0:1; /* RI3[0] */
+ _UDWORD RI3_1:1; /* RI3[1] */
+ _UDWORD TI3_0:1; /* TI3[0] */
+ _UDWORD TI3_1:1; /* TI3[1] */
+ _UDWORD SPI3_0:1; /* SPI3[0] */
+ _UDWORD SPI3_1:1; /* SPI3[1] */
+ _UDWORD STI3_0:1; /* STI3[0] */
+ _UDWORD STI3_1:1; /* STI3[1] */
+ _UDWORD NAKI3_0:1; /* NAKI3[0] */
+ _UDWORD NAKI3_1:1; /* NAKI3[1] */
+ _UDWORD ALI3_0:1; /* ALI3[0] */
+ _UDWORD ALI3_1:1; /* ALI3[1] */
+ _UDWORD TMOI3_0:1; /* TMOI3[0] */
+ _UDWORD TMOI3_1:1; /* TMOI3[1] */
+ _UDWORD BRI0_0:1; /* BRI0[0] */
+ _UDWORD BRI0_1:1; /* BRI0[1] */
+ _UDWORD ERI0_0:1; /* ERI0[0] */
+ _UDWORD ERI0_1:1; /* ERI0[1] */
+ _UDWORD RXI0_0:1; /* RXI0[0] */
+ _UDWORD RXI0_1:1; /* RXI0[1] */
+ } BIT; /* */
+ } ICDICFR13; /* */
+ union { /* ICDICFR14 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI0_0:1; /* TXI0[0] */
+ _UDWORD TXI0_1:1; /* TXI0[1] */
+ _UDWORD BRI1_0:1; /* BRI1[0] */
+ _UDWORD BRI1_1:1; /* BRI1[1] */
+ _UDWORD ERI1_0:1; /* ERI1[0] */
+ _UDWORD ERI1_1:1; /* ERI1[1] */
+ _UDWORD RXI1_0:1; /* RXI1[0] */
+ _UDWORD RXI1_1:1; /* RXI1[1] */
+ _UDWORD TXI1_0:1; /* TXI1[0] */
+ _UDWORD TXI1_1:1; /* TXI1[1] */
+ _UDWORD BRI2_0:1; /* BRI2[0] */
+ _UDWORD BRI2_1:1; /* BRI2[1] */
+ _UDWORD ERI2_0:1; /* ERI2[0] */
+ _UDWORD ERI2_1:1; /* ERI2[1] */
+ _UDWORD RXI2_0:1; /* RXI2[0] */
+ _UDWORD RXI2_1:1; /* RXI2[1] */
+ _UDWORD TXI2_0:1; /* TXI2[0] */
+ _UDWORD TXI2_1:1; /* TXI2[1] */
+ _UDWORD BRI3_0:1; /* BRI3[0] */
+ _UDWORD BRI3_1:1; /* BRI3[1] */
+ _UDWORD ERI3_0:1; /* ERI3[0] */
+ _UDWORD ERI3_1:1; /* ERI3[1] */
+ _UDWORD RXI3_0:1; /* RXI3[0] */
+ _UDWORD RXI3_1:1; /* RXI3[1] */
+ _UDWORD TXI3_0:1; /* TXI3[0] */
+ _UDWORD TXI3_1:1; /* TXI3[1] */
+ _UDWORD BRI4_0:1; /* BRI4[0] */
+ _UDWORD BRI4_1:1; /* BRI4[1] */
+ _UDWORD ERI4_0:1; /* ERI4[0] */
+ _UDWORD ERI4_1:1; /* ERI4[1] */
+ _UDWORD RXI4_0:1; /* RXI4[0] */
+ _UDWORD RXI4_1:1; /* RXI4[1] */
+ } BIT; /* */
+ } ICDICFR14; /* */
+ union { /* ICDICFR15 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TXI4_0:1; /* TXI4[0] */
+ _UDWORD TXI4_1:1; /* TXI4[1] */
+ _UDWORD BRI5_0:1; /* BRI5[0] */
+ _UDWORD BRI5_1:1; /* BRI5[1] */
+ _UDWORD ERI5_0:1; /* ERI5[0] */
+ _UDWORD ERI5_1:1; /* ERI5[1] */
+ _UDWORD RXI5_0:1; /* RXI5[0] */
+ _UDWORD RXI5_1:1; /* RXI5[1] */
+ _UDWORD TXI5_0:1; /* TXI5[0] */
+ _UDWORD TXI5_1:1; /* TXI5[1] */
+ _UDWORD BRI6_0:1; /* BRI6[0] */
+ _UDWORD BRI6_1:1; /* BRI6[1] */
+ _UDWORD ERI6_0:1; /* ERI6[0] */
+ _UDWORD ERI6_1:1; /* ERI6[1] */
+ _UDWORD RXI6_0:1; /* RXI6[0] */
+ _UDWORD RXI6_1:1; /* RXI6[1] */
+ _UDWORD TXI6_0:1; /* TXI6[0] */
+ _UDWORD TXI6_1:1; /* TXI6[1] */
+ _UDWORD BRI7_0:1; /* BRI7[0] */
+ _UDWORD BRI7_1:1; /* BRI7[1] */
+ _UDWORD ERI7_0:1; /* ERI7[0] */
+ _UDWORD ERI7_1:1; /* ERI7[1] */
+ _UDWORD RXI7_0:1; /* RXI7[0] */
+ _UDWORD RXI7_1:1; /* RXI7[1] */
+ _UDWORD TXI7_0:1; /* TXI7[0] */
+ _UDWORD TXI7_1:1; /* TXI7[1] */
+ _UDWORD GERI_0:1; /* GERI[0] */
+ _UDWORD GERI_1:1; /* GERI[1] */
+ _UDWORD RFI_0:1; /* RFI[0] */
+ _UDWORD RFI_1:1; /* RFI[1] */
+ _UDWORD CFRXI0_0:1; /* CFRXI0[0] */
+ _UDWORD CFRXI0_1:1; /* CFRXI0[1] */
+ } BIT; /* */
+ } ICDICFR15; /* */
+ union { /* ICDICFR16 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CERI0_0:1; /* CERI0[0] */
+ _UDWORD CERI0_1:1; /* CERI0[1] */
+ _UDWORD CTXI0_0:1; /* CTXI0[0] */
+ _UDWORD CTXI0_1:1; /* CTXI0[1] */
+ _UDWORD CFRXI1_0:1; /* CFRXI1[0] */
+ _UDWORD CFRXI1_1:1; /* CFRXI1[1] */
+ _UDWORD CERI1_0:1; /* CERI1[0] */
+ _UDWORD CERI1_1:1; /* CERI1[1] */
+ _UDWORD CTXI1_0:1; /* CTXI1[0] */
+ _UDWORD CTXI1_1:1; /* CTXI1[1] */
+ _UDWORD CFRXI2_0:1; /* CFRXI2[0] */
+ _UDWORD CFRXI2_1:1; /* CFRXI2[1] */
+ _UDWORD CERI2_0:1; /* CERI2[0] */
+ _UDWORD CERI2_1:1; /* CERI2[1] */
+ _UDWORD CTXI2_0:1; /* CTXI2[0] */
+ _UDWORD CTXI2_1:1; /* CTXI2[1] */
+ _UDWORD CFRXI3_0:1; /* CFRXI3[0] */
+ _UDWORD CFRXI3_1:1; /* CFRXI3[1] */
+ _UDWORD CERI3_0:1; /* CERI3[0] */
+ _UDWORD CERI3_1:1; /* CERI3[1] */
+ _UDWORD CTXI3_0:1; /* CTXI3[0] */
+ _UDWORD CTXI3_1:1; /* CTXI3[1] */
+ _UDWORD CFRXI4_0:1; /* CFRXI4[0] */
+ _UDWORD CFRXI4_1:1; /* CFRXI4[1] */
+ _UDWORD CERI4_0:1; /* CERI4[0] */
+ _UDWORD CERI4_1:1; /* CERI4[1] */
+ _UDWORD CTXI4_0:1; /* CTXI4[0] */
+ _UDWORD CTXI4_1:1; /* CTXI4[1] */
+ _UDWORD SPEI0_0:1; /* SPEI0[0] */
+ _UDWORD SPEI0_1:1; /* SPEI0[1] */
+ _UDWORD SPRI0_0:1; /* SPRI0[0] */
+ _UDWORD SPRI0_1:1; /* SPRI0[1] */
+ } BIT; /* */
+ } ICDICFR16; /* */
+ union { /* ICDICFR17 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPTI0_0:1; /* SPTI0[0] */
+ _UDWORD SPTI0_1:1; /* SPTI0[1] */
+ _UDWORD SPEI1_0:1; /* SPEI1[0] */
+ _UDWORD SPEI1_1:1; /* SPEI1[1] */
+ _UDWORD SPRI1_0:1; /* SPRI1[0] */
+ _UDWORD SPRI1_1:1; /* SPRI1[1] */
+ _UDWORD SPTI1_0:1; /* SPTI1[0] */
+ _UDWORD SPTI1_1:1; /* SPTI1[1] */
+ _UDWORD SPEI2_0:1; /* SPEI2[0] */
+ _UDWORD SPEI2_1:1; /* SPEI2[1] */
+ _UDWORD SPRI2_0:1; /* SPRI2[0] */
+ _UDWORD SPRI2_1:1; /* SPRI2[1] */
+ _UDWORD SPTI2_0:1; /* SPTI2[0] */
+ _UDWORD SPTI2_1:1; /* SPTI2[1] */
+ _UDWORD SPEI3_0:1; /* SPEI3[0] */
+ _UDWORD SPEI3_1:1; /* SPEI3[1] */
+ _UDWORD SPRI3_0:1; /* SPRI3[0] */
+ _UDWORD SPRI3_1:1; /* SPRI3[1] */
+ _UDWORD SPTI3_0:1; /* SPTI3[0] */
+ _UDWORD SPTI3_1:1; /* SPTI3[1] */
+ _UDWORD SPEI4_0:1; /* SPEI4[0] */
+ _UDWORD SPEI4_1:1; /* SPEI4[1] */
+ _UDWORD SPRI4_0:1; /* SPRI4[0] */
+ _UDWORD SPRI4_1:1; /* SPRI4[1] */
+ _UDWORD SPTI4_0:1; /* SPTI4[0] */
+ _UDWORD SPTI4_1:1; /* SPTI4[1] */
+ _UDWORD IEBBTD_0:1; /* IEBBTD[0] */
+ _UDWORD IEBBTD_1:1; /* IEBBTD[1] */
+ _UDWORD IEBBTERR_0:1; /* IEBBTERR[0] */
+ _UDWORD IEBBTERR_1:1; /* IEBBTERR[1] */
+ _UDWORD IEBBTSTA_0:1; /* IEBBTSTA[0] */
+ _UDWORD IEBBTSTA_1:1; /* IEBBTSTA[1] */
+ } BIT; /* */
+ } ICDICFR17; /* */
+ union { /* ICDICFR18 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IEBBTV_0:1; /* IEBBTV[0] */
+ _UDWORD IEBBTV_1:1; /* IEBBTV[1] */
+ _UDWORD ISY_0:1; /* ISY[0] */
+ _UDWORD ISY_1:1; /* ISY[1] */
+ _UDWORD IERR_0:1; /* IERR[0] */
+ _UDWORD IERR_1:1; /* IERR[1] */
+ _UDWORD ITARG_0:1; /* ITARG[0] */
+ _UDWORD ITARG_1:1; /* ITARG[1] */
+ _UDWORD ISEC_0:1; /* ISEC[0] */
+ _UDWORD ISEC_1:1; /* ISEC[1] */
+ _UDWORD IBUF_0:1; /* IBUF[0] */
+ _UDWORD IBUF_1:1; /* IBUF[1] */
+ _UDWORD IREADY_0:1; /* IREADY[0] */
+ _UDWORD IREADY_1:1; /* IREADY[1] */
+ _UDWORD FLSTE_0:1; /* FLSTE[0] */
+ _UDWORD FLSTE_1:1; /* FLSTE[1] */
+ _UDWORD FLTENDI_0:1; /* FLTENDI[0] */
+ _UDWORD FLTENDI_1:1; /* FLTENDI[1] */
+ _UDWORD FLTREQ0I_0:1; /* FLTREQ0I[0] */
+ _UDWORD FLTREQ0I_1:1; /* FLTREQ0I[1] */
+ _UDWORD FLTREQ1I_0:1; /* FLTREQ1I[0] */
+ _UDWORD FLTREQ1I_1:1; /* FLTREQ1I[1] */
+ _UDWORD MMC0_0:1; /* MMC0[0] */
+ _UDWORD MMC0_1:1; /* MMC0[1] */
+ _UDWORD MMC1_0:1; /* MMC1[0] */
+ _UDWORD MMC1_1:1; /* MMC1[1] */
+ _UDWORD MMC2_0:1; /* MMC2[0] */
+ _UDWORD MMC2_1:1; /* MMC2[1] */
+ _UDWORD SDHI0_3_0:1; /* SDHI0_3[0] */
+ _UDWORD SDHI0_3_1:1; /* SDHI0_3[1] */
+ _UDWORD SDHI0_0_0:1; /* SDHI0_0[0] */
+ _UDWORD SDHI0_0_1:1; /* SDHI0_0[1] */
+ } BIT; /* */
+ } ICDICFR18; /* */
+ union { /* ICDICFR19 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SDHI0_1_0:1; /* SDHI0_1[0] */
+ _UDWORD SDHI0_1_1:1; /* SDHI0_1[1] */
+ _UDWORD SDHI1_3_0:1; /* SDHI1_3[0] */
+ _UDWORD SDHI1_3_1:1; /* SDHI1_3[1] */
+ _UDWORD SDHI1_0_0:1; /* SDHI1_0[0] */
+ _UDWORD SDHI1_0_1:1; /* SDHI1_0[1] */
+ _UDWORD SDHI1_1_0:1; /* SDHI1_1[0] */
+ _UDWORD SDHI1_1_1:1; /* SDHI1_1[1] */
+ _UDWORD ARM_0:1; /* ARM[0] */
+ _UDWORD ARM_1:1; /* ARM[1] */
+ _UDWORD PRD_0:1; /* PRD[0] */
+ _UDWORD PRD_1:1; /* PRD[1] */
+ _UDWORD CUP_0:1; /* CUP[0] */
+ _UDWORD CUP_1:1; /* CUP[1] */
+ _UDWORD SCUAI0_0:1; /* SCUAI0[0] */
+ _UDWORD SCUAI0_1:1; /* SCUAI0[1] */
+ _UDWORD SCUAI1_0:1; /* SCUAI1[0] */
+ _UDWORD SCUAI1_1:1; /* SCUAI1[1] */
+ _UDWORD SCUFDI0_0:1; /* SCUFDI0[0] */
+ _UDWORD SCUFDI0_1:1; /* SCUFDI0[1] */
+ _UDWORD SCUFDI1_0:1; /* SCUFDI1[0] */
+ _UDWORD SCUFDI1_1:1; /* SCUFDI1[1] */
+ _UDWORD SCUFDI2_0:1; /* SCUFDI2[0] */
+ _UDWORD SCUFDI2_1:1; /* SCUFDI2[1] */
+ _UDWORD SCUFDI3_0:1; /* SCUFDI3[0] */
+ _UDWORD SCUFDI3_1:1; /* SCUFDI3[1] */
+ _UDWORD SCUFUI0_0:1; /* SCUFUI0[0] */
+ _UDWORD SCUFUI0_1:1; /* SCUFUI0[1] */
+ _UDWORD SCUFUI1_0:1; /* SCUFUI1[0] */
+ _UDWORD SCUFUI1_1:1; /* SCUFUI1[1] */
+ _UDWORD SCUFUI2_0:1; /* SCUFUI2[0] */
+ _UDWORD SCUFUI2_1:1; /* SCUFUI2[1] */
+ } BIT; /* */
+ } ICDICFR19; /* */
+ union { /* ICDICFR20 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCUFUI3_0:1; /* SCUFUI3[0] */
+ _UDWORD SCUFUI3_1:1; /* SCUFUI3[1] */
+ _UDWORD SCUDVI0_0:1; /* SCUDVI0[0] */
+ _UDWORD SCUDVI0_1:1; /* SCUDVI0[1] */
+ _UDWORD SCUDVI1_0:1; /* SCUDVI1[0] */
+ _UDWORD SCUDVI1_1:1; /* SCUDVI1[1] */
+ _UDWORD SCUDVI2_0:1; /* SCUDVI2[0] */
+ _UDWORD SCUDVI2_1:1; /* SCUDVI2[1] */
+ _UDWORD SCUDVI3_0:1; /* SCUDVI3[0] */
+ _UDWORD SCUDVI3_1:1; /* SCUDVI3[1] */
+ _UDWORD MLBCI_0:1; /* MLBCI[0] */
+ _UDWORD MLBCI_1:1; /* MLBCI[1] */
+ _UDWORD MLBSI_0:1; /* MLBSI[0] */
+ _UDWORD MLBSI_1:1; /* MLBSI[1] */
+ _UDWORD DRC0_0:1; /* DRC0[0] */
+ _UDWORD DRC0_1:1; /* DRC0[1] */
+ _UDWORD DRC1_0:1; /* DRC1[0] */
+ _UDWORD DRC1_1:1; /* DRC1[1] */
+ _UDWORD :4; /* */
+ _UDWORD LINI0_INT_T_0:1;/* LINI0_INT_T[0] */
+ _UDWORD LINI0_INT_T_1:1;/* LINI0_INT_T[1] */
+ _UDWORD LINI0_INT_R_0:1;/* LINI0_INT_R[0] */
+ _UDWORD LINI0_INT_R_1:1;/* LINI0_INT_R[1] */
+ _UDWORD LINI0_INT_S_0:1;/* LINI0_INT_S[0] */
+ _UDWORD LINI0_INT_S_1:1;/* LINI0_INT_S[1] */
+ _UDWORD LINI0_INT_M_0:1;/* LINI0_INT_M[0] */
+ _UDWORD LINI0_INT_M_1:1;/* LINI0_INT_M[1] */
+ _UDWORD LINI1_INT_T_0:1;/* LINI1_INT_T[0] */
+ _UDWORD LINI1_INT_T_1:1;/* LINI1_INT_T[1] */
+ } BIT; /* */
+ } ICDICFR20; /* */
+ union { /* ICDICFR21 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD LINI1_INT_R_0:1;/* LINI1_INT_R[0] */
+ _UDWORD LINI1_INT_R_1:1;/* LINI1_INT_R[1] */
+ _UDWORD LINI1_INT_S_0:1;/* LINI1_INT_S[0] */
+ _UDWORD LINI1_INT_S_1:1;/* LINI1_INT_S[1] */
+ _UDWORD LINI1_INT_M_0:1;/* LINI1_INT_M[0] */
+ _UDWORD LINI1_INT_M_1:1;/* LINI1_INT_M[1] */
+ _UDWORD :16; /* */
+ _UDWORD ERI0_0:1; /* ERI0[0] */
+ _UDWORD ERI0_1:1; /* ERI0[1] */
+ _UDWORD RXI0_0:1; /* RXI0[0] */
+ _UDWORD RXI0_1:1; /* RXI0[1] */
+ _UDWORD TXI0_0:1; /* TXI0[0] */
+ _UDWORD TXI0_1:1; /* TXI0[1] */
+ _UDWORD TEI0_0:1; /* TEI0[0] */
+ _UDWORD TEI0_1:1; /* TEI0[1] */
+ _UDWORD ERI1_0:1; /* ERI1[0] */
+ _UDWORD ERI1_1:1; /* ERI1[1] */
+ } BIT; /* */
+ } ICDICFR21; /* */
+ union { /* ICDICFR22 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RXI1_0:1; /* RXI1[0] */
+ _UDWORD RXI1_1:1; /* RXI1[1] */
+ _UDWORD TXI1_0:1; /* TXI1[0] */
+ _UDWORD TXI1_1:1; /* TXI1[1] */
+ _UDWORD TEI1_0:1; /* TEI1[0] */
+ _UDWORD TEI1_1:1; /* TEI1[1] */
+ _UDWORD :8; /* */
+ _UDWORD ETHERI_0:1; /* ETHERI[0] */
+ _UDWORD ETHERI_1:1; /* ETHERI[1] */
+ _UDWORD :8; /* */
+ _UDWORD CEUI_0:1; /* CEUI[0] */
+ _UDWORD CEUI_1:1; /* CEUI[1] */
+ _UDWORD INT_CSIH0TIR_0:1;/* INT_CSIH0TIR[0] */
+ _UDWORD INT_CSIH0TIR_1:1;/* INT_CSIH0TIR[1] */
+ _UDWORD INT_CSIH0TIRE_0:1;/* INT_CSIH0TIRE[0] */
+ _UDWORD INT_CSIH0TIRE_1:1;/* INT_CSIH0TIRE[1] */
+ _UDWORD INT_CSIH1TIC_0:1;/* INT_CSIH1TIC[0] */
+ _UDWORD INT_CSIH1TIC_1:1;/* INT_CSIH1TIC[1] */
+ } BIT; /* */
+ } ICDICFR22; /* */
+ union { /* ICDICFR23 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD INT_CSIH1TIJC_0:1;/* INT_CSIH1TIJC[0] */
+ _UDWORD INT_CSIH1TIJC_1:1;/* INT_CSIH1TIJC[1] */
+ _UDWORD ECCE10_0:1; /* ECCE10[0] */
+ _UDWORD ECCE10_1:1; /* ECCE10[1] */
+ _UDWORD ECCE20_0:1; /* ECCE20[0] */
+ _UDWORD ECCE20_1:1; /* ECCE20[1] */
+ _UDWORD ECCOVF0_0:1; /* ECCOVF0[0] */
+ _UDWORD ECCOVF0_1:1; /* ECCOVF0[1] */
+ _UDWORD ECCE11_0:1; /* ECCE11[0] */
+ _UDWORD ECCE11_1:1; /* ECCE11[1] */
+ _UDWORD ECCE21_0:1; /* ECCE21[0] */
+ _UDWORD ECCE21_1:1; /* ECCE21[1] */
+ _UDWORD ECCOVF1_0:1; /* ECCOVF1[0] */
+ _UDWORD ECCOVF1_1:1; /* ECCOVF1[1] */
+ _UDWORD ECCE12_0:1; /* ECCE12[0] */
+ _UDWORD ECCE12_1:1; /* ECCE12[1] */
+ _UDWORD ECCE22_0:1; /* ECCE22[0] */
+ _UDWORD ECCE22_1:1; /* ECCE22[1] */
+ _UDWORD ECCOVF2_0:1; /* ECCOVF2[0] */
+ _UDWORD ECCOVF2_1:1; /* ECCOVF2[1] */
+ _UDWORD ECCE13_0:1; /* ECCE13[0] */
+ _UDWORD ECCE13_1:1; /* ECCE13[1] */
+ _UDWORD ECCE23_0:1; /* ECCE23[0] */
+ _UDWORD ECCE23_1:1; /* ECCE23[1] */
+ _UDWORD ECCOVF3_0:1; /* ECCOVF3[0] */
+ _UDWORD ECCOVF3_1:1; /* ECCOVF3[1] */
+ _UDWORD H2XMLB_ERRINT_0:1;/* H2XMLB_ERRINT[0] */
+ _UDWORD H2XMLB_ERRINT_1:1;/* H2XMLB_ERRINT[1] */
+ _UDWORD H2XIC1_ERRINT_0:1;/* H2XIC1_ERRINT[0] */
+ _UDWORD H2XIC1_ERRINT_1:1;/* H2XIC1_ERRINT[1] */
+ _UDWORD X2HPERI1_ERRINT_0:1;/* X2HPERI1_ERRINT[0] */
+ _UDWORD X2HPERI1_ERRINT_1:1;/* X2HPERI1_ERRINT[1] */
+ } BIT; /* */
+ } ICDICFR23; /* */
+ union { /* ICDICFR24 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD X2HPERI2_ERRINT_0:1;/* X2HPERI2_ERRINT[0] */
+ _UDWORD X2HPERI2_ERRINT_1:1;/* X2HPERI2_ERRINT[1] */
+ _UDWORD X2HPERI34_ERRINT_0:1;/* X2HPERI34_ERRINT[0] */
+ _UDWORD X2HPERI34_ERRINT_1:1;/* X2HPERI34_ERRINT[1] */
+ _UDWORD X2HPERI5_ERRINT_0:1;/* X2HPERI5_ERRINT[0] */
+ _UDWORD X2HPERI5_ERRINT_1:1;/* X2HPERI5_ERRINT[1] */
+ _UDWORD X2HPERI67_ERRINT_0:1;/* X2HPERI67_ERRINT[0] */
+ _UDWORD X2HPERI67_ERRINT_1:1;/* X2HPERI67_ERRINT[1] */
+ _UDWORD X2HDBGR_ERRINT_0:1;/* X2HDBGR_ERRINT[0] */
+ _UDWORD X2HDBGR_ERRINT_1:1;/* X2HDBGR_ERRINT[1] */
+ _UDWORD PRRI_0:1; /* PRRI[0] */
+ _UDWORD PRRI_1:1; /* PRRI[1] */
+ _UDWORD IFEI0_0:1; /* IFEI0[0] */
+ _UDWORD IFEI0_1:1; /* IFEI0[1] */
+ _UDWORD OFFI0_0:1; /* OFFI0[0] */
+ _UDWORD OFFI0_1:1; /* OFFI0[1] */
+ _UDWORD PFVEI0_0:1; /* PFVEI0[0] */
+ _UDWORD PFVEI0_1:1; /* PFVEI0[1] */
+ _UDWORD IFEI1_0:1; /* IFEI1[0] */
+ _UDWORD IFEI1_1:1; /* IFEI1[1] */
+ _UDWORD OFFI1_0:1; /* OFFI1[0] */
+ _UDWORD OFFI1_1:1; /* OFFI1[1] */
+ _UDWORD PFVEI1_0:1; /* PFVEI1[0] */
+ _UDWORD PFVEI1_1:1; /* PFVEI1[1] */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } ICDICFR24; /* */
+ union { /* ICDICFR25 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD dummy:32; /* */
+ } BIT; /* */
+ } ICDICFR25; /* */
+ union { /* ICDICFR26 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT0_0:1; /* TINT0[0] */
+ _UDWORD TINT0_1:1; /* TINT0[1] */
+ _UDWORD TINT1_0:1; /* TINT1[0] */
+ _UDWORD TINT1_1:1; /* TINT1[1] */
+ _UDWORD TINT2_0:1; /* TINT2[0] */
+ _UDWORD TINT2_1:1; /* TINT2[1] */
+ _UDWORD TINT3_0:1; /* TINT3[0] */
+ _UDWORD TINT3_1:1; /* TINT3[1] */
+ _UDWORD TINT4_0:1; /* TINT4[0] */
+ _UDWORD TINT4_1:1; /* TINT4[1] */
+ _UDWORD TINT5_0:1; /* TINT5[0] */
+ _UDWORD TINT5_1:1; /* TINT5[1] */
+ _UDWORD TINT6_0:1; /* TINT6[0] */
+ _UDWORD TINT6_1:1; /* TINT6[1] */
+ _UDWORD TINT7_0:1; /* TINT7[0] */
+ _UDWORD TINT7_1:1; /* TINT7[1] */
+ _UDWORD TINT8_0:1; /* TINT8[0] */
+ _UDWORD TINT8_1:1; /* TINT8[1] */
+ _UDWORD TINT9_0:1; /* TINT9[0] */
+ _UDWORD TINT9_1:1; /* TINT9[1] */
+ _UDWORD TINT10_0:1; /* TINT10[0] */
+ _UDWORD TINT10_1:1; /* TINT10[1] */
+ _UDWORD TINT11_0:1; /* TINT11[0] */
+ _UDWORD TINT11_1:1; /* TINT11[1] */
+ _UDWORD TINT12_0:1; /* TINT12[0] */
+ _UDWORD TINT12_1:1; /* TINT12[1] */
+ _UDWORD TINT13_0:1; /* TINT13[0] */
+ _UDWORD TINT13_1:1; /* TINT13[1] */
+ _UDWORD TINT14_0:1; /* TINT14[0] */
+ _UDWORD TINT14_1:1; /* TINT14[1] */
+ _UDWORD TINT15_0:1; /* TINT15[0] */
+ _UDWORD TINT15_1:1; /* TINT15[1] */
+ } BIT; /* */
+ } ICDICFR26; /* */
+ union { /* ICDICFR27 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT16_0:1; /* TINT16[0] */
+ _UDWORD TINT16_1:1; /* TINT16[1] */
+ _UDWORD TINT17_0:1; /* TINT17[0] */
+ _UDWORD TINT17_1:1; /* TINT17[1] */
+ _UDWORD TINT18_0:1; /* TINT18[0] */
+ _UDWORD TINT18_1:1; /* TINT18[1] */
+ _UDWORD TINT19_0:1; /* TINT19[0] */
+ _UDWORD TINT19_1:1; /* TINT19[1] */
+ _UDWORD TINT20_0:1; /* TINT20[0] */
+ _UDWORD TINT20_1:1; /* TINT20[1] */
+ _UDWORD TINT21_0:1; /* TINT21[0] */
+ _UDWORD TINT21_1:1; /* TINT21[1] */
+ _UDWORD TINT22_0:1; /* TINT22[0] */
+ _UDWORD TINT22_1:1; /* TINT22[1] */
+ _UDWORD TINT23_0:1; /* TINT23[0] */
+ _UDWORD TINT23_1:1; /* TINT23[1] */
+ _UDWORD TINT24_0:1; /* TINT24[0] */
+ _UDWORD TINT24_1:1; /* TINT24[1] */
+ _UDWORD TINT25_0:1; /* TINT25[0] */
+ _UDWORD TINT25_1:1; /* TINT25[1] */
+ _UDWORD TINT26_0:1; /* TINT26[0] */
+ _UDWORD TINT26_1:1; /* TINT26[1] */
+ _UDWORD TINT27_0:1; /* TINT27[0] */
+ _UDWORD TINT27_1:1; /* TINT27[1] */
+ _UDWORD TINT28_0:1; /* TINT28[0] */
+ _UDWORD TINT28_1:1; /* TINT28[1] */
+ _UDWORD TINT29_0:1; /* TINT29[0] */
+ _UDWORD TINT29_1:1; /* TINT29[1] */
+ _UDWORD TINT30_0:1; /* TINT30[0] */
+ _UDWORD TINT30_1:1; /* TINT30[1] */
+ _UDWORD TINT31_0:1; /* TINT31[0] */
+ _UDWORD TINT31_1:1; /* TINT31[1] */
+ } BIT; /* */
+ } ICDICFR27; /* */
+ union { /* ICDICFR28 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT32_0:1; /* TINT32[0] */
+ _UDWORD TINT32_1:1; /* TINT32[1] */
+ _UDWORD TINT33_0:1; /* TINT33[0] */
+ _UDWORD TINT33_1:1; /* TINT33[1] */
+ _UDWORD TINT34_0:1; /* TINT34[0] */
+ _UDWORD TINT34_1:1; /* TINT34[1] */
+ _UDWORD TINT35_0:1; /* TINT35[0] */
+ _UDWORD TINT35_1:1; /* TINT35[1] */
+ _UDWORD TINT36_0:1; /* TINT36[0] */
+ _UDWORD TINT36_1:1; /* TINT36[1] */
+ _UDWORD TINT37_0:1; /* TINT37[0] */
+ _UDWORD TINT37_1:1; /* TINT37[1] */
+ _UDWORD TINT38_0:1; /* TINT38[0] */
+ _UDWORD TINT38_1:1; /* TINT38[1] */
+ _UDWORD TINT39_0:1; /* TINT39[0] */
+ _UDWORD TINT39_1:1; /* TINT39[1] */
+ _UDWORD TINT40_0:1; /* TINT40[0] */
+ _UDWORD TINT40_1:1; /* TINT40[1] */
+ _UDWORD TINT41_0:1; /* TINT41[0] */
+ _UDWORD TINT41_1:1; /* TINT41[1] */
+ _UDWORD TINT42_0:1; /* TINT42[0] */
+ _UDWORD TINT42_1:1; /* TINT42[1] */
+ _UDWORD TINT43_0:1; /* TINT43[0] */
+ _UDWORD TINT43_1:1; /* TINT43[1] */
+ _UDWORD TINT44_0:1; /* TINT44[0] */
+ _UDWORD TINT44_1:1; /* TINT44[1] */
+ _UDWORD TINT45_0:1; /* TINT45[0] */
+ _UDWORD TINT45_1:1; /* TINT45[1] */
+ _UDWORD TINT46_0:1; /* TINT46[0] */
+ _UDWORD TINT46_1:1; /* TINT46[1] */
+ _UDWORD TINT47_0:1; /* TINT47[0] */
+ _UDWORD TINT47_1:1; /* TINT47[1] */
+ } BIT; /* */
+ } ICDICFR28; /* */
+ union { /* ICDICFR29 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT48_0:1; /* TINT48[0] */
+ _UDWORD TINT48_1:1; /* TINT48[1] */
+ _UDWORD TINT49_0:1; /* TINT49[0] */
+ _UDWORD TINT49_1:1; /* TINT49[1] */
+ _UDWORD TINT50_0:1; /* TINT50[0] */
+ _UDWORD TINT50_1:1; /* TINT50[1] */
+ _UDWORD TINT51_0:1; /* TINT51[0] */
+ _UDWORD TINT51_1:1; /* TINT51[1] */
+ _UDWORD TINT52_0:1; /* TINT52[0] */
+ _UDWORD TINT52_1:1; /* TINT52[1] */
+ _UDWORD TINT53_0:1; /* TINT53[0] */
+ _UDWORD TINT53_1:1; /* TINT53[1] */
+ _UDWORD TINT54_0:1; /* TINT54[0] */
+ _UDWORD TINT54_1:1; /* TINT54[1] */
+ _UDWORD TINT55_0:1; /* TINT55[0] */
+ _UDWORD TINT55_1:1; /* TINT55[1] */
+ _UDWORD TINT56_0:1; /* TINT56[0] */
+ _UDWORD TINT56_1:1; /* TINT56[1] */
+ _UDWORD TINT57_0:1; /* TINT57[0] */
+ _UDWORD TINT57_1:1; /* TINT57[1] */
+ _UDWORD TINT58_0:1; /* TINT58[0] */
+ _UDWORD TINT58_1:1; /* TINT58[1] */
+ _UDWORD TINT59_0:1; /* TINT59[0] */
+ _UDWORD TINT59_1:1; /* TINT59[1] */
+ _UDWORD TINT60_0:1; /* TINT60[0] */
+ _UDWORD TINT60_1:1; /* TINT60[1] */
+ _UDWORD TINT61_0:1; /* TINT61[0] */
+ _UDWORD TINT61_1:1; /* TINT61[1] */
+ _UDWORD TINT62_0:1; /* TINT62[0] */
+ _UDWORD TINT62_1:1; /* TINT62[1] */
+ _UDWORD TINT63_0:1; /* TINT63[0] */
+ _UDWORD TINT63_1:1; /* TINT63[1] */
+ } BIT; /* */
+ } ICDICFR29; /* */
+ union { /* ICDICFR30 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT64_0:1; /* TINT64[0] */
+ _UDWORD TINT64_1:1; /* TINT64[1] */
+ _UDWORD TINT65_0:1; /* TINT65[0] */
+ _UDWORD TINT65_1:1; /* TINT65[1] */
+ _UDWORD TINT66_0:1; /* TINT66[0] */
+ _UDWORD TINT66_1:1; /* TINT66[1] */
+ _UDWORD TINT67_0:1; /* TINT67[0] */
+ _UDWORD TINT67_1:1; /* TINT67[1] */
+ _UDWORD TINT68_0:1; /* TINT68[0] */
+ _UDWORD TINT68_1:1; /* TINT68[1] */
+ _UDWORD TINT69_0:1; /* TINT69[0] */
+ _UDWORD TINT69_1:1; /* TINT69[1] */
+ _UDWORD TINT70_0:1; /* TINT70[0] */
+ _UDWORD TINT70_1:1; /* TINT70[1] */
+ _UDWORD TINT71_0:1; /* TINT71[0] */
+ _UDWORD TINT71_1:1; /* TINT71[1] */
+ _UDWORD TINT72_0:1; /* TINT72[0] */
+ _UDWORD TINT72_1:1; /* TINT72[1] */
+ _UDWORD TINT73_0:1; /* TINT73[0] */
+ _UDWORD TINT73_1:1; /* TINT73[1] */
+ _UDWORD :12; /* */
+ } BIT; /* */
+ } ICDICFR30; /* */
+ union { /* ICDICFR31 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT80_0:1; /* TINT80[0] */
+ _UDWORD TINT80_1:1; /* TINT80[1] */
+ _UDWORD TINT81_0:1; /* TINT81[0] */
+ _UDWORD TINT81_1:1; /* TINT81[1] */
+ _UDWORD TINT82_0:1; /* TINT82[0] */
+ _UDWORD TINT82_1:1; /* TINT82[1] */
+ _UDWORD TINT83_0:1; /* TINT83[0] */
+ _UDWORD TINT83_1:1; /* TINT83[1] */
+ _UDWORD TINT84_0:1; /* TINT84[0] */
+ _UDWORD TINT84_1:1; /* TINT84[1] */
+ _UDWORD TINT85_0:1; /* TINT85[0] */
+ _UDWORD TINT85_1:1; /* TINT85[1] */
+ _UDWORD TINT86_0:1; /* TINT86[0] */
+ _UDWORD TINT86_1:1; /* TINT86[1] */
+ _UDWORD TINT87_0:1; /* TINT87[0] */
+ _UDWORD TINT87_1:1; /* TINT87[1] */
+ _UDWORD TINT88_0:1; /* TINT88[0] */
+ _UDWORD TINT88_1:1; /* TINT88[1] */
+ _UDWORD TINT89_0:1; /* TINT89[0] */
+ _UDWORD TINT89_1:1; /* TINT89[1] */
+ _UDWORD TINT90_0:1; /* TINT90[0] */
+ _UDWORD TINT90_1:1; /* TINT90[1] */
+ _UDWORD TINT91_0:1; /* TINT91[0] */
+ _UDWORD TINT91_1:1; /* TINT91[1] */
+ _UDWORD TINT92_0:1; /* TINT92[0] */
+ _UDWORD TINT92_1:1; /* TINT92[1] */
+ _UDWORD TINT93_0:1; /* TINT93[0] */
+ _UDWORD TINT93_1:1; /* TINT93[1] */
+ _UDWORD TINT94_0:1; /* TINT94[0] */
+ _UDWORD TINT94_1:1; /* TINT94[1] */
+ _UDWORD TINT95_0:1; /* TINT95[0] */
+ _UDWORD TINT95_1:1; /* TINT95[1] */
+ } BIT; /* */
+ } ICDICFR31; /* */
+ union { /* ICDICFR32 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT96_0:1; /* TINT96[0] */
+ _UDWORD TINT96_1:1; /* TINT96[1] */
+ _UDWORD TINT97_0:1; /* TINT97[0] */
+ _UDWORD TINT97_1:1; /* TINT97[1] */
+ _UDWORD TINT98_0:1; /* TINT98[0] */
+ _UDWORD TINT98_1:1; /* TINT98[1] */
+ _UDWORD TINT99_0:1; /* TINT99[0] */
+ _UDWORD TINT99_1:1; /* TINT99[1] */
+ _UDWORD TINT100_0:1; /* TINT100[0] */
+ _UDWORD TINT100_1:1; /* TINT100[1] */
+ _UDWORD TINT101_0:1; /* TINT101[0] */
+ _UDWORD TINT101_1:1; /* TINT101[1] */
+ _UDWORD TINT102_0:1; /* TINT102[0] */
+ _UDWORD TINT102_1:1; /* TINT102[1] */
+ _UDWORD TINT103_0:1; /* TINT103[0] */
+ _UDWORD TINT103_1:1; /* TINT103[1] */
+ _UDWORD TINT104_0:1; /* TINT104[0] */
+ _UDWORD TINT104_1:1; /* TINT104[1] */
+ _UDWORD TINT105_0:1; /* TINT105[0] */
+ _UDWORD TINT105_1:1; /* TINT105[1] */
+ _UDWORD TINT106_0:1; /* TINT106[0] */
+ _UDWORD TINT106_1:1; /* TINT106[1] */
+ _UDWORD TINT107_0:1; /* TINT107[0] */
+ _UDWORD TINT107_1:1; /* TINT107[1] */
+ _UDWORD TINT108_0:1; /* TINT108[0] */
+ _UDWORD TINT108_1:1; /* TINT108[1] */
+ _UDWORD TINT109_0:1; /* TINT109[0] */
+ _UDWORD TINT109_1:1; /* TINT109[1] */
+ _UDWORD TINT110_0:1; /* TINT110[0] */
+ _UDWORD TINT110_1:1; /* TINT110[1] */
+ _UDWORD TINT111_0:1; /* TINT111[0] */
+ _UDWORD TINT111_1:1; /* TINT111[1] */
+ } BIT; /* */
+ } ICDICFR32; /* */
+ union { /* ICDICFR33 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT112_0:1; /* TINT112[0] */
+ _UDWORD TINT112_1:1; /* TINT112[1] */
+ _UDWORD TINT113_0:1; /* TINT113[0] */
+ _UDWORD TINT113_1:1; /* TINT113[1] */
+ _UDWORD TINT114_0:1; /* TINT114[0] */
+ _UDWORD TINT114_1:1; /* TINT114[1] */
+ _UDWORD TINT115_0:1; /* TINT115[0] */
+ _UDWORD TINT115_1:1; /* TINT115[1] */
+ _UDWORD TINT116_0:1; /* TINT116[0] */
+ _UDWORD TINT116_1:1; /* TINT116[1] */
+ _UDWORD TINT117_0:1; /* TINT117[0] */
+ _UDWORD TINT117_1:1; /* TINT117[1] */
+ _UDWORD TINT118_0:1; /* TINT118[0] */
+ _UDWORD TINT118_1:1; /* TINT118[1] */
+ _UDWORD TINT119_0:1; /* TINT119[0] */
+ _UDWORD TINT119_1:1; /* TINT119[1] */
+ _UDWORD TINT120_0:1; /* TINT120[0] */
+ _UDWORD TINT120_1:1; /* TINT120[1] */
+ _UDWORD TINT121_0:1; /* TINT121[0] */
+ _UDWORD TINT121_1:1; /* TINT121[1] */
+ _UDWORD TINT122_0:1; /* TINT122[0] */
+ _UDWORD TINT122_1:1; /* TINT122[1] */
+ _UDWORD TINT123_0:1; /* TINT123[0] */
+ _UDWORD TINT123_1:1; /* TINT123[1] */
+ _UDWORD TINT124_0:1; /* TINT124[0] */
+ _UDWORD TINT124_1:1; /* TINT124[1] */
+ _UDWORD TINT125_0:1; /* TINT125[0] */
+ _UDWORD TINT125_1:1; /* TINT125[1] */
+ _UDWORD TINT126_0:1; /* TINT126[0] */
+ _UDWORD TINT126_1:1; /* TINT126[1] */
+ _UDWORD TINT127_0:1; /* TINT127[0] */
+ _UDWORD TINT127_1:1; /* TINT127[1] */
+ } BIT; /* */
+ } ICDICFR33; /* */
+ union { /* ICDICFR34 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT128_0:1; /* TINT128[0] */
+ _UDWORD TINT128_1:1; /* TINT128[1] */
+ _UDWORD TINT129_0:1; /* TINT129[0] */
+ _UDWORD TINT129_1:1; /* TINT129[1] */
+ _UDWORD TINT130_0:1; /* TINT130[0] */
+ _UDWORD TINT130_1:1; /* TINT130[1] */
+ _UDWORD TINT131_0:1; /* TINT131[0] */
+ _UDWORD TINT131_1:1; /* TINT131[1] */
+ _UDWORD TINT132_0:1; /* TINT132[0] */
+ _UDWORD TINT132_1:1; /* TINT132[1] */
+ _UDWORD TINT133_0:1; /* TINT133[0] */
+ _UDWORD TINT133_1:1; /* TINT133[1] */
+ _UDWORD TINT134_0:1; /* TINT134[0] */
+ _UDWORD TINT134_1:1; /* TINT134[1] */
+ _UDWORD TINT135_0:1; /* TINT135[0] */
+ _UDWORD TINT135_1:1; /* TINT135[1] */
+ _UDWORD TINT136_0:1; /* TINT136[0] */
+ _UDWORD TINT136_1:1; /* TINT136[1] */
+ _UDWORD TINT137_0:1; /* TINT137[0] */
+ _UDWORD TINT137_1:1; /* TINT137[1] */
+ _UDWORD TINT138_0:1; /* TINT138[0] */
+ _UDWORD TINT138_1:1; /* TINT138[1] */
+ _UDWORD TINT139_0:1; /* TINT139[0] */
+ _UDWORD TINT139_1:1; /* TINT139[1] */
+ _UDWORD TINT140_0:1; /* TINT140[0] */
+ _UDWORD TINT140_1:1; /* TINT140[1] */
+ _UDWORD TINT141_0:1; /* TINT141[0] */
+ _UDWORD TINT141_1:1; /* TINT141[1] */
+ _UDWORD TINT142_0:1; /* TINT142[0] */
+ _UDWORD TINT142_1:1; /* TINT142[1] */
+ _UDWORD TINT143_0:1; /* TINT143[0] */
+ _UDWORD TINT143_1:1; /* TINT143[1] */
+ } BIT; /* */
+ } ICDICFR34; /* */
+ union { /* ICDICFR35 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT144_0:1; /* TINT144[0] */
+ _UDWORD TINT144_1:1; /* TINT144[1] */
+ _UDWORD TINT145_0:1; /* TINT145[0] */
+ _UDWORD TINT145_1:1; /* TINT145[1] */
+ _UDWORD TINT146_0:1; /* TINT146[0] */
+ _UDWORD TINT146_1:1; /* TINT146[1] */
+ _UDWORD TINT147_0:1; /* TINT147[0] */
+ _UDWORD TINT147_1:1; /* TINT147[1] */
+ _UDWORD TINT148_0:1; /* TINT148[0] */
+ _UDWORD TINT148_1:1; /* TINT148[1] */
+ _UDWORD TINT149_0:1; /* TINT149[0] */
+ _UDWORD TINT149_1:1; /* TINT149[1] */
+ _UDWORD TINT150_0:1; /* TINT150[0] */
+ _UDWORD TINT150_1:1; /* TINT150[1] */
+ _UDWORD TINT151_0:1; /* TINT151[0] */
+ _UDWORD TINT151_1:1; /* TINT151[1] */
+ _UDWORD TINT152_0:1; /* TINT152[0] */
+ _UDWORD TINT152_1:1; /* TINT152[1] */
+ _UDWORD TINT153_0:1; /* TINT153[0] */
+ _UDWORD TINT153_1:1; /* TINT153[1] */
+ _UDWORD TINT154_0:1; /* TINT154[0] */
+ _UDWORD TINT154_1:1; /* TINT154[1] */
+ _UDWORD TINT155_0:1; /* TINT155[0] */
+ _UDWORD TINT155_1:1; /* TINT155[1] */
+ _UDWORD TINT156_0:1; /* TINT156[0] */
+ _UDWORD TINT156_1:1; /* TINT156[1] */
+ _UDWORD TINT157_0:1; /* TINT157[0] */
+ _UDWORD TINT157_1:1; /* TINT157[1] */
+ _UDWORD TINT158_0:1; /* TINT158[0] */
+ _UDWORD TINT158_1:1; /* TINT158[1] */
+ _UDWORD TINT159_0:1; /* TINT159[0] */
+ _UDWORD TINT159_1:1; /* TINT159[1] */
+ } BIT; /* */
+ } ICDICFR35; /* */
+ union { /* ICDICFR36 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TINT160_0:1; /* TINT160[0] */
+ _UDWORD TINT160_1:1; /* TINT160[1] */
+ _UDWORD TINT161_0:1; /* TINT161[0] */
+ _UDWORD TINT161_1:1; /* TINT161[1] */
+ _UDWORD TINT162_0:1; /* TINT162[0] */
+ _UDWORD TINT162_1:1; /* TINT162[1] */
+ _UDWORD :26; /* */
+ } BIT; /* */
+ } ICDICFR36; /* */
+ } n; /* */
+ } ICDICFR; /* */
+ _UBYTE wk19[108]; /* */
+ union { /* ppi_status */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :11; /* */
+ _UDWORD ppi_status0:1; /* ppi_status[0] */
+ _UDWORD ppi_status1:1; /* ppi_status[1] */
+ _UDWORD ppi_status2:1; /* ppi_status[2] */
+ _UDWORD ppi_status3:1; /* ppi_status[3] */
+ _UDWORD ppi_status4:1; /* ppi_status[4] */
+ _UDWORD :16; /* */
+ } BIT; /* */
+ } ppi_status; /* */
+ union { /* spi_status */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD spi_status0:1; /* spi_status[0] */
+ _UDWORD spi_status1:1; /* spi_status[1] */
+ _UDWORD spi_status2:1; /* spi_status[2] */
+ _UDWORD spi_status3:1; /* spi_status[3] */
+ _UDWORD spi_status4:1; /* spi_status[4] */
+ _UDWORD spi_status5:1; /* spi_status[5] */
+ _UDWORD spi_status6:1; /* spi_status[6] */
+ _UDWORD spi_status7:1; /* spi_status[7] */
+ _UDWORD spi_status8:1; /* spi_status[8] */
+ _UDWORD spi_status9:1; /* spi_status[9] */
+ _UDWORD spi_status10:1; /* spi_status[10] */
+ _UDWORD spi_status11:1; /* spi_status[11] */
+ _UDWORD spi_status12:1; /* spi_status[12] */
+ _UDWORD spi_status13:1; /* spi_status[13] */
+ _UDWORD spi_status14:1; /* spi_status[14] */
+ _UDWORD spi_status15:1; /* spi_status[15] */
+ _UDWORD spi_status16:1; /* spi_status[16] */
+ _UDWORD spi_status17:1; /* spi_status[17] */
+ _UDWORD spi_status18:1; /* spi_status[18] */
+ _UDWORD spi_status19:1; /* spi_status[19] */
+ _UDWORD spi_status20:1; /* spi_status[20] */
+ _UDWORD spi_status21:1; /* spi_status[21] */
+ _UDWORD spi_status22:1; /* spi_status[22] */
+ _UDWORD spi_status23:1; /* spi_status[23] */
+ _UDWORD spi_status24:1; /* spi_status[24] */
+ _UDWORD spi_status25:1; /* spi_status[25] */
+ _UDWORD spi_status26:1; /* spi_status[26] */
+ _UDWORD spi_status27:1; /* spi_status[27] */
+ _UDWORD spi_status28:1; /* spi_status[28] */
+ _UDWORD spi_status29:1; /* spi_status[29] */
+ _UDWORD spi_status30:1; /* spi_status[30] */
+ _UDWORD spi_status31:1; /* spi_status[31] */
+ } BIT; /* */
+ } spi_status[17]; /* */
+ _UBYTE wk20[440]; /* */
+ union { /* ICDSGIR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SGIINTID:4; /* SGIINTID */
+ _UDWORD :11; /* */
+ _UDWORD SATT:1; /* SATT */
+ _UDWORD CPUTargetList:8; /* CPUTargetList */
+ _UDWORD TargetListFilter:2; /* TargetListFilter */
+ _UDWORD :6; /* */
+ } BIT; /* */
+ } ICDSGIR; /* */
+ _UBYTE wk21[252]; /* */
+ union { /* ICCICR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EnableS:1; /* EnableS */
+ _UDWORD EnableNS:1; /* EnableNS */
+ _UDWORD AckCtl:1; /* AckCtl */
+ _UDWORD FIQEn:1; /* FIQEn */
+ _UDWORD SBPR:1; /* SBPR */
+ _UDWORD :27; /* */
+ } BIT; /* */
+ } ICCICR; /* */
+ union { /* ICCPMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD Priority:8; /* Priority */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } ICCPMR; /* */
+ union { /* ICCBPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD Binarypoint:3; /* Binarypoint */
+ _UDWORD :29; /* */
+ } BIT; /* */
+ } ICCBPR; /* */
+ union { /* ICCIAR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ACKINTID:10; /* ACKINTID */
+ _UDWORD CPUID:3; /* CPUID */
+ _UDWORD :19; /* */
+ } BIT; /* */
+ } ICCIAR; /* */
+ union { /* ICCEOIR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EOIINTID:10; /* EOIINTID */
+ _UDWORD CPUID:3; /* CPUID */
+ _UDWORD :19; /* */
+ } BIT; /* */
+ } ICCEOIR; /* */
+ union { /* ICCRPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD Priority:8; /* Priority */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } ICCRPR; /* */
+ union { /* ICCHPIR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD PENDINTID:10; /* PENDINTID */
+ _UDWORD CPUID:3; /* CPUID */
+ _UDWORD :19; /* */
+ } BIT; /* */
+ } ICCHPIR; /* */
+ union { /* ICCABPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD Binarypoint:3; /* Binarypoint */
+ _UDWORD :29; /* */
+ } BIT; /* */
+ } ICCABPR; /* */
+ _UBYTE wk22[220]; /* */
+ _UDWORD ICCIDR; /* ICCIDR */
+}; /* */
+struct st_intc_2 { /* struct INTC2 */
+ union { /* ICR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :1; /* */
+ _UWORD NMIF:1; /* NMIF */
+ _UWORD :6; /* */
+ _UWORD NMIE:1; /* NMIE */
+ _UWORD :6; /* */
+ _UWORD NMIL:1; /* NMIL */
+ } BIT; /* */
+ } ICR0; /* */
+ union { /* ICR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD IRQ00S:1; /* IRQ00S */
+ _UWORD IRQ01S:1; /* IRQ01S */
+ _UWORD IRQ10S:1; /* IRQ10S */
+ _UWORD IRQ11S:1; /* IRQ11S */
+ _UWORD IRQ20S:1; /* IRQ20S */
+ _UWORD IRQ21S:1; /* IRQ21S */
+ _UWORD IRQ30S:1; /* IRQ30S */
+ _UWORD IRQ31S:1; /* IRQ31S */
+ _UWORD IRQ40S:1; /* IRQ40S */
+ _UWORD IRQ41S:1; /* IRQ41S */
+ _UWORD IRQ50S:1; /* IRQ50S */
+ _UWORD IRQ51S:1; /* IRQ51S */
+ _UWORD IRQ60S:1; /* IRQ60S */
+ _UWORD IRQ61S:1; /* IRQ61S */
+ _UWORD IRQ70S:1; /* IRQ70S */
+ _UWORD IRQ71S:1; /* IRQ71S */
+ } BIT; /* */
+ } ICR1; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* IRQRR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD IRQ0F:1; /* IRQ0F */
+ _UWORD IRQ1F:1; /* IRQ1F */
+ _UWORD IRQ2F:1; /* IRQ2F */
+ _UWORD IRQ3F:1; /* IRQ3F */
+ _UWORD IRQ4F:1; /* IRQ4F */
+ _UWORD IRQ5F:1; /* IRQ5F */
+ _UWORD IRQ6F:1; /* IRQ6F */
+ _UWORD IRQ7F:1; /* IRQ7F */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } IRQRR; /* */
+ _UBYTE wk1[16]; /* */
+ union { /* MXIR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MXI:1; /* MXI */
+ _UWORD :15; /* */
+ } BIT; /* */
+ } MXIR0; /* */
+ union { /* MXIR1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MXI:1; /* MXI */
+ _UWORD :15; /* */
+ } BIT; /* */
+ } MXIR1; /* */
+}; /* */
+
+#ifndef ARM_SIM
+#define INTC (*(volatile struct st_intc *) 0xE8201000) /* INTC Address */
+#define INTC2 (*(volatile struct st_intc_2 *)0xFCFEF800) /* INTC2 Address */
+#else /* ARM_SIM */
+#define INTC (*(volatile struct st_intc *) 0x45201000) /* INTC Address */
+#define INTC2 (*(volatile struct st_intc_2 *)0x49FEF800) /* INTC2 Address */
+#endif /* ARM_SIM */
+
+#endif /* __INTC_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/mtu2_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/mtu2_iodefine.h
new file mode 100644
index 000000000..85cc4dba7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/mtu2_iodefine.h
@@ -0,0 +1,715 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name :
+* File Name : mtu2_iodefine.h
+* Abstract :
+* Version : 1.00.00
+* Device : ARM
+* Tool-Chain :
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : Jan.11,2013 Ver.1.00.00
+*******************************************************************************/
+#ifndef __MTU2_IODEFINE_H__
+#define __MTU2_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_mtu2{ /* struct MTU2 */
+ union { /* TCR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TPSC:3; /* TPSC */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE CCLR:2; /* CCLR */
+ _UBYTE :1;
+ } BIT; /* */
+ } TCR_2; /* */
+ union { /* TMDR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MD:4; /* MD */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } TMDR_2; /* */
+ union { /* TIOR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOA:4; /* IOA */
+ _UBYTE IOB:4; /* IOB */
+ } BIT; /* */
+ } TIOR_2; /* */
+ _UBYTE wk0[1]; /* */
+ union { /* TIER_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGIEA:1; /* TGIEA */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE :2; /* */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE TCIEU:1; /* TCIEU */
+ _UBYTE :1; /* */
+ _UBYTE TTGE:1; /* TTGE */
+ } BIT; /* */
+ } TIER_2; /* */
+ union { /* TSR_2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGFA:1; /* TGFA */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE :1; /* */
+ _UBYTE :1; /* */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TCFU:1; /* TCFU */
+ _UBYTE :1; /* */
+ _UBYTE TCFD:1; /* TCFD */
+ } BIT; /* */
+ } TSR_2; /* */
+ union { /* TCNT_2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_2; /* */
+ union { /* TGRA_2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_2; /* */
+ union { /* TGRB_2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_2; /* */
+ _UBYTE wk1[500]; /* */
+ union { /* TCR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TPSC:3; /* TPSC */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE CCLR:3; /* CCLR */
+ } BIT; /* */
+ } TCR_3; /* */
+ union { /* TCR_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TPSC:3; /* TPSC */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE CCLR:3; /* CCLR */
+ } BIT; /* */
+ } TCR_4; /* */
+ union { /* TMDR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MD:4; /* MD */
+ _UBYTE BFA:1; /* BFA */
+ _UBYTE BFB:1; /* BFB */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } TMDR_3; /* */
+ union { /* TMDR_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MD:4; /* MD */
+ _UBYTE BFA:1; /* BFA */
+ _UBYTE BFB:1; /* BFB */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } TMDR_4; /* */
+ union { /* TIORH_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOA:4; /* IOA */
+ _UBYTE IOB:4; /* IOB */
+ } BIT; /* */
+ } TIORH_3; /* */
+ union { /* TIORL_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOC:4; /* IOC */
+ _UBYTE IOD:4; /* IOD */
+ } BIT; /* */
+ } TIORL_3; /* */
+ union { /* TIORH_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOA:4; /* IOA */
+ _UBYTE IOB:4; /* IOB */
+ } BIT; /* */
+ } TIORH_4; /* */
+ union { /* TIORL_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOC:4; /* IOC */
+ _UBYTE IOD:4; /* IOD */
+ } BIT; /* */
+ } TIORL_4; /* */
+ union { /* TIER_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGIEA:1; /* TGIEA */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEC:1; /* TGIEC */
+ _UBYTE TGIED:1; /* TGIED */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE :2; /* */
+ _UBYTE TTGE:1; /* TTGE */
+ } BIT; /* */
+ } TIER_3; /* */
+ union { /* TIER_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGIEA:1; /* TGIEA */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEC:1; /* TGIEC */
+ _UBYTE TGIED:1; /* TGIED */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE :1; /* */
+ _UBYTE TTGE2:1; /* TTGE2 */
+ _UBYTE TTGE:1; /* TTGE */
+ } BIT; /* */
+ } TIER_4; /* */
+ union { /* TOER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OE3B:1; /* OE3B */
+ _UBYTE OE4A:1; /* OE4A */
+ _UBYTE OE4B:1; /* OE4B */
+ _UBYTE OE3D:1; /* OE3D */
+ _UBYTE OE4C:1; /* OE4C */
+ _UBYTE OE4D:1; /* OE4D */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } TOER; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* TGCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE UF:1; /* UF */
+ _UBYTE VF:1; /* VF */
+ _UBYTE WF:1; /* WF */
+ _UBYTE FB:1; /* FB */
+ _UBYTE P:1; /* P */
+ _UBYTE N:1; /* N */
+ _UBYTE BDC:1; /* BDC */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } TGCR; /* */
+ union { /* TOCR1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OLSP:1; /* OLSP */
+ _UBYTE OLSN:1; /* OLSN */
+ _UBYTE TOCS:1; /* TOCS */
+ _UBYTE TOCL:1; /* TOCL */
+ _UBYTE :2; /* */
+ _UBYTE PSYE:1; /* PSYE */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } TOCR1; /* */
+ union { /* TOCR2 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OLS1P:1; /* OLS1P */
+ _UBYTE OLS1N:1; /* OLS1N */
+ _UBYTE OLS2P:1; /* OLS2P */
+ _UBYTE OLS2N:1; /* OLS2N */
+ _UBYTE OLS3P:1; /* OLS3P */
+ _UBYTE OLS3N:1; /* OLS3N */
+ _UBYTE BF:2; /* BF */
+ } BIT; /* */
+ } TOCR2; /* */
+ union { /* TCNT_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_3; /* */
+ union { /* TCNT_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_4; /* */
+ union { /* TCDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCDR; /* */
+ union { /* TDDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TDDR; /* */
+ union { /* TGRA_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_3; /* */
+ union { /* TGRB_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_3; /* */
+ union { /* TGRA_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_4; /* */
+ union { /* TGRB_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_4; /* */
+ union { /* TCNTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNTS; /* */
+ union { /* TCBR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCBR; /* */
+ union { /* TGRC_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRC_3; /* */
+ union { /* TGRD_3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRD_3; /* */
+ union { /* TGRC_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRC_4; /* */
+ union { /* TGRD_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRD_4; /* */
+ union { /* TSR_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGFA:1; /* TGFA */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE :2; /* */
+ _UBYTE TCFD:1; /* TCFD */
+ } BIT; /* */
+ } TSR_3; /* */
+ union { /* TSR_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGFA:1; /* TGFA */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE :2; /* */
+ _UBYTE TCFD:1; /* TCFD */
+ } BIT; /* */
+ } TSR_4; /* */
+ _UBYTE wk3[2]; /* */
+ union { /* TITCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE _4VCOR:3; /* _4VCOR */
+ _UBYTE T4VEN:1; /* T4VEN */
+ _UBYTE _3ACOR:3; /* _3ACOR */
+ _UBYTE T3AEN:1; /* T3AEN */
+ } BIT; /* */
+ } TITCR; /* */
+ union { /* TITCNT */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE _4VCNT:3; /* _4VCNT */
+ _UBYTE :1; /* */
+ _UBYTE _3ACNT:3; /* _3ACNT */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } TITCNT; /* */
+ union { /* TBTER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE BTE:2; /* BTE */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } TBTER; /* */
+ _UBYTE wk4[1]; /* */
+ union { /* TDER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TDER:1; /* TDER */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } TDER; /* */
+ _UBYTE wk5[1]; /* */
+ union { /* TOLBR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OLS1P:1; /* OLS1P */
+ _UBYTE OLS1N:1; /* OLS1N */
+ _UBYTE OLS2P:1; /* OLS2P */
+ _UBYTE OLS2N:1; /* OLS2N */
+ _UBYTE OLS3P:1; /* OLS3P */
+ _UBYTE OLS3N:1; /* OLS3N */
+ _UBYTE :2; /* */
+ } BIT; /* */
+ } TOLBR; /* */
+ _UBYTE wk6[1]; /* */
+ union { /* TBTM_3 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTSA:1; /* TTSA */
+ _UBYTE TTSB:1; /* TTSB */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } TBTM_3; /* */
+ union { /* TBTM_4 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTSA:1; /* TTSA */
+ _UBYTE TTSB:1; /* TTSB */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } TBTM_4; /* */
+ _UBYTE wk7[6]; /* */
+ union { /* TADCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD ITB4VE:1; /* ITB4VE */
+ _UWORD ITB3AE:1; /* ITB3AE */
+ _UWORD ITA4VE:1; /* ITA4VE */
+ _UWORD ITA3AE:1; /* ITA3AE */
+ _UWORD DT4BE:1; /* DT4BE */
+ _UWORD UT4BE:1; /* UT4BE */
+ _UWORD DT4AE:1; /* DT4AE */
+ _UWORD UT4AE:1; /* UT4AE */
+ _UWORD :6; /* */
+ _UWORD BF:2; /* BF */
+ } BIT; /* */
+ } TADCR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* TADCORA_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCORA_4; /* */
+ union { /* TADCORB_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCORB_4; /* */
+ union { /* TADCOBRA_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCOBRA_4; /* */
+ union { /* TADCOBRB_4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TADCOBRB_4; /* */
+ _UBYTE wk9[20]; /* */
+ union { /* TWCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE WRE:1; /* WRE */
+ _UBYTE :6; /* */
+ _UBYTE CCE:1; /* CCE */
+ } BIT; /* */
+ } TWCR; /* */
+ _UBYTE wk10[31]; /* */
+ union { /* TSTR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE CST0:1; /* CST0 */
+ _UBYTE CST1:1; /* CST1 */
+ _UBYTE CST2:1; /* CST2 */
+ _UBYTE :3; /* */
+ _UBYTE CST3:1; /* CST3 */
+ _UBYTE CST4:1; /* CST4 */
+ } BIT; /* */
+ } TSTR; /* */
+ union { /* TSYR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE SYNC0:1; /* SYNC0 */
+ _UBYTE SYNC1:1; /* SYNC1 */
+ _UBYTE SYNC2:1; /* SYNC2 */
+ _UBYTE :3; /* */
+ _UBYTE SYNC3:1; /* SYNC3 */
+ _UBYTE SYNC4:1; /* SYNC4 */
+ } BIT; /* */
+ } TSYR; /* */
+ _UBYTE wk11[2]; /* */
+ union { /* TRWER */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE RWE:1; /* RWE */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } TRWER; /* */
+ _UBYTE wk12[123]; /* */
+ union { /* TCR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TPSC:3; /* TPSC */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE CCLR:3; /* CCLR */
+ } BIT; /* */
+ } TCR_0; /* */
+ union { /* TMDR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MD:4; /* MD */
+ _UBYTE BFA:1; /* BFA */
+ _UBYTE BFB:1; /* BFB */
+ _UBYTE BFE:1; /* BFE */
+ _UBYTE :1; /* */
+ } BIT; /* */
+ } TMDR_0; /* */
+ union { /* TIORH_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOA:4; /* IOA */
+ _UBYTE IOB:4; /* IOB */
+ } BIT; /* */
+ } TIORH_0; /* */
+ union { /* TIORL_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOC:4; /* IOC */
+ _UBYTE IOD:4; /* IOD */
+ } BIT; /* */
+ } TIORL_0; /* */
+ union { /* TIER_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGIEA:1; /* TGIEA */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE TGIEC:1; /* TGIEC */
+ _UBYTE TGIED:1; /* TGIED */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE :2; /* */
+ _UBYTE TTGE:1; /* TTGE */
+ } BIT; /* */
+ } TIER_0; /* */
+ union { /* TSR_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGFA:1; /* TGFA */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE TGFC:1; /* TGFC */
+ _UBYTE TGFD:1; /* TGFD */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE :3; /* */
+ } BIT; /* */
+ } TSR_0; /* */
+ union { /* TCNT_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_0; /* */
+ union { /* TGRA_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_0; /* */
+ union { /* TGRB_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_0; /* */
+ union { /* TGRC_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRC_0; /* */
+ union { /* TGRD_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRD_0; /* */
+ _UBYTE wk13[16]; /* */
+ union { /* TGRE_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRE_0; /* */
+ union { /* TGRF_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRF_0; /* */
+ union { /* TIER2_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGIEE:1; /* TGIEE */
+ _UBYTE TGIEF:1; /* TGIEF */
+ _UBYTE :5; /* */
+ _UBYTE TTGE2:1; /* TTGE2 */
+ } BIT; /* */
+ } TIER2_0; /* */
+ union { /* TSR2_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGFE:1; /* TGFE */
+ _UBYTE TGFF:1; /* TGFF */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } TSR2_0; /* */
+ union { /* TBTM_0 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TTSA:1; /* TTSA */
+ _UBYTE TTSB:1; /* TTSB */
+ _UBYTE TTSE:1; /* TTSE */
+ _UBYTE :5; /* */
+ } BIT; /* */
+ } TBTM_0; /* */
+ _UBYTE wk14[89]; /* */
+ union { /* TCR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TPSC:3; /* TPSC */
+ _UBYTE CKEG:2; /* CKEG */
+ _UBYTE CCLR:2; /* CCLR */
+ _UBYTE :1;
+ } BIT; /* */
+ } TCR_1; /* */
+ union { /* TMDR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE MD:4; /* MD */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } TMDR_1; /* */
+ union { /* TIOR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE IOA:4; /* IOA */
+ _UBYTE IOB:4; /* IOB */
+ } BIT; /* */
+ } TIOR_1; /* */
+ _UBYTE wk15[1]; /* */
+ union { /* TIER_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGIEA:1; /* TGIEA */
+ _UBYTE TGIEB:1; /* TGIEB */
+ _UBYTE :2; /* */
+ _UBYTE TCIEV:1; /* TCIEV */
+ _UBYTE TCIEU:1; /* TCIEU */
+ _UBYTE :1; /* */
+ _UBYTE TTGE:1; /* TTGE */
+ } BIT; /* */
+ } TIER_1; /* */
+ union { /* TSR_1 */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE TGFA:1; /* TGFA */
+ _UBYTE TGFB:1; /* TGFB */
+ _UBYTE :2; /* */
+ _UBYTE TCFV:1; /* TCFV */
+ _UBYTE TCFU:1; /* TCFU */
+ _UBYTE :1; /* */
+ _UBYTE TCFD:1; /* TCFD */
+ } BIT; /* */
+ } TSR_1; /* */
+ union { /* TCNT_1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TCNT_1; /* */
+ union { /* TGRA_1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRA_1; /* */
+ union { /* TGRB_1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD D:16; /* D */
+ } BIT; /* */
+ } TGRB_1; /* */
+ _UBYTE wk16[4]; /* */
+ union { /* TICCR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE I1AE:1; /* I1AE */
+ _UBYTE I1BE:1; /* I1BE */
+ _UBYTE I2AE:1; /* I2AE */
+ _UBYTE I2BE:1; /* I2BE */
+ _UBYTE :4; /* */
+ } BIT; /* */
+ } TICCR; /* */
+}; /* */
+
+
+#define MTU2 (*(volatile struct st_mtu2 *)0xFCFF0000) /* MTU2 Address */
+
+#endif /* __MTU2_IODEFINE_H__ */
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/ostm_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/ostm_iodefine.h
new file mode 100644
index 000000000..2c3ecf460
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/ostm_iodefine.h
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_iodefine.h
+* Version : 0.01
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* ARM Complier
+* :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program vecotr.s
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 27.07.2012 0.01 ŽQlŽ‘—¿Fsec11_OSTM_120601.pdf
+*******************************************************************************/
+#ifndef __OSTM_IODEFINE_H__
+#define __OSTM_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_ostm_n { /* struct OSTM */
+ _UDWORD OSTMnCMP; /* OSTMnCMP */
+ _UDWORD OSTMnCNT; /* OSTMnCNT */
+ _UBYTE wk0[8]; /* */
+ union { /* OSTMnTE */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OSTMnTE:1; /* OSTMnTE */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } OSTMnTE; /* */
+ _UBYTE wk1[3]; /* */
+ union { /* OSTMnTS */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OSTMnTS:1; /* OSTMnTS */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } OSTMnTS; /* */
+ _UBYTE wk2[3]; /* */
+ union { /* OSTMnTT */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OSTMnTT:1; /* OSTMnTT */
+ _UBYTE :7; /* */
+ } BIT; /* */
+ } OSTMnTT; /* */
+ _UBYTE wk3[7]; /* */
+ union { /* OSTMnCTL */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE OSTMnMD0:1; /* OSTMnMD0 */
+ _UBYTE OSTMnMD1:1; /* OSTMnMD1 */
+ _UBYTE :6; /* */
+ } BIT; /* */
+ } OSTMnCTL; /* */
+}; /* */
+
+#define OSTM0 (*(volatile struct st_ostm_n *)0xFCFEC000) /* OSTM0 Address */
+#define OSTM1 (*(volatile struct st_ostm_n *)0xFCFEC400) /* OSTM1 Address */
+
+
+#endif /* __OSTM_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/pfc_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/pfc_iodefine.h
new file mode 100644
index 000000000..8e66a17b0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/pfc_iodefine.h
@@ -0,0 +1,436 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name :
+* File Name : pfc_iodefine.h
+* Abstract :
+* Version : 1.00.00
+* Device : ARM
+* Tool-Chain :
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : Mar.06,2012 Ver.1.00.00
+*******************************************************************************/
+#ifndef __PFC_IODEFINE_H__
+#define __PFC_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_pfc_n { /* struct PFC */
+ union { /* Pn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD Pn0:1; /* */
+ _UWORD Pn1:1; /* */
+ _UWORD Pn2:1; /* */
+ _UWORD Pn3:1; /* */
+ _UWORD Pn4:1; /* */
+ _UWORD Pn5:1; /* */
+ _UWORD Pn6:1; /* */
+ _UWORD Pn7:1; /* */
+ _UWORD Pn8:1; /* */
+ _UWORD Pn9:1; /* */
+ _UWORD Pn10:1; /* */
+ _UWORD Pn11:1; /* */
+ _UWORD Pn12:1; /* */
+ _UWORD Pn13:1; /* */
+ _UWORD Pn14:1; /* */
+ _UWORD Pn15:1; /* */
+ } BIT; /* */
+ } Pn; /* */
+ _UBYTE wk0[0x100-2]; /* */
+ union { /* PSRn */
+ _UDWORD LONG; /* Long Access */
+ struct { /* WORD Access */
+ _UDWORD ENABLE:16; /* */
+ _UDWORD SET:16; /* */
+ } SET;
+ struct { /* Bit Access */
+ _UDWORD PSRn0:1; /* */
+ _UDWORD PSRn1:1; /* */
+ _UDWORD PSRn2:1; /* */
+ _UDWORD PSRn3:1; /* */
+ _UDWORD PSRn4:1; /* */
+ _UDWORD PSRn5:1; /* */
+ _UDWORD PSRn6:1; /* */
+ _UDWORD PSRn7:1; /* */
+ _UDWORD PSRn8:1; /* */
+ _UDWORD PSRn9:1; /* */
+ _UDWORD PSRn10:1; /* */
+ _UDWORD PSRn11:1; /* */
+ _UDWORD PSRn12:1; /* */
+ _UDWORD PSRn13:1; /* */
+ _UDWORD PSRn14:1; /* */
+ _UDWORD PSRn15:1; /* */
+ _UDWORD PSRn16:1; /* */
+ _UDWORD PSRn17:1; /* */
+ _UDWORD PSRn18:1; /* */
+ _UDWORD PSRn19:1; /* */
+ _UDWORD PSRn20:1; /* */
+ _UDWORD PSRn21:1; /* */
+ _UDWORD PSRn22:1; /* */
+ _UDWORD PSRn23:1; /* */
+ _UDWORD PSRn24:1; /* */
+ _UDWORD PSRn25:1; /* */
+ _UDWORD PSRn26:1; /* */
+ _UDWORD PSRn27:1; /* */
+ _UDWORD PSRn28:1; /* */
+ _UDWORD PSRn29:1; /* */
+ _UDWORD PSRn30:1; /* */
+ _UDWORD PSRn31:1; /* */
+ } BIT; /* */
+ } PSRn; /* */
+ _UBYTE wk1[0x100-4]; /* */
+ union { /* PPRn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PPRn0:1; /* */
+ _UWORD PPRn1:1; /* */
+ _UWORD PPRn2:1; /* */
+ _UWORD PPRn3:1; /* */
+ _UWORD PPRn4:1; /* */
+ _UWORD PPRn5:1; /* */
+ _UWORD PPRn6:1; /* */
+ _UWORD PPRn7:1; /* */
+ _UWORD PPRn8:1; /* */
+ _UWORD PPRn9:1; /* */
+ _UWORD PPRn10:1; /* */
+ _UWORD PPRn11:1; /* */
+ _UWORD PPRn12:1; /* */
+ _UWORD PPRn13:1; /* */
+ _UWORD PPRn14:1; /* */
+ _UWORD PPRn15:1; /* */
+ } BIT; /* */
+ } PPRn; /* */
+ _UBYTE wk2[0x100-2]; /* */
+ union { /* PMn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PMn0:1; /* */
+ _UWORD PMn1:1; /* */
+ _UWORD PMn2:1; /* */
+ _UWORD PMn3:1; /* */
+ _UWORD PMn4:1; /* */
+ _UWORD PMn5:1; /* */
+ _UWORD PMn6:1; /* */
+ _UWORD PMn7:1; /* */
+ _UWORD PMn8:1; /* */
+ _UWORD PMn9:1; /* */
+ _UWORD PMn10:1; /* */
+ _UWORD PMn11:1; /* */
+ _UWORD PMn12:1; /* */
+ _UWORD PMn13:1; /* */
+ _UWORD PMn14:1; /* */
+ _UWORD PMn15:1; /* */
+ } BIT; /* */
+ } PMn; /* */
+ _UBYTE wk3[0x100-2]; /* */
+ union { /* PMCn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PMCn0:1; /* */
+ _UWORD PMCn1:1; /* */
+ _UWORD PMCn2:1; /* */
+ _UWORD PMCn3:1; /* */
+ _UWORD PMCn4:1; /* */
+ _UWORD PMCn5:1; /* */
+ _UWORD PMCn6:1; /* */
+ _UWORD PMCn7:1; /* */
+ _UWORD PMCn8:1; /* */
+ _UWORD PMCn9:1; /* */
+ _UWORD PMCn10:1; /* */
+ _UWORD PMCn11:1; /* */
+ _UWORD PMCn12:1; /* */
+ _UWORD PMCn13:1; /* */
+ _UWORD PMCn14:1; /* */
+ _UWORD PMCn15:1; /* */
+ } BIT; /* */
+ } PMCn; /* */
+ _UBYTE wk4[0x100-2]; /* */
+ union { /* PFCn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PFCn0:1; /* */
+ _UWORD PFCn1:1; /* */
+ _UWORD PFCn2:1; /* */
+ _UWORD PFCn3:1; /* */
+ _UWORD PFCn4:1; /* */
+ _UWORD PFCn5:1; /* */
+ _UWORD PFCn6:1; /* */
+ _UWORD PFCn7:1; /* */
+ _UWORD PFCn8:1; /* */
+ _UWORD PFCn9:1; /* */
+ _UWORD PFCn10:1; /* */
+ _UWORD PFCn11:1; /* */
+ _UWORD PFCn12:1; /* */
+ _UWORD PFCn13:1; /* */
+ _UWORD PFCn14:1; /* */
+ _UWORD PFCn15:1; /* */
+ } BIT; /* */
+ } PFCn; /* */
+ _UBYTE wk5[0x100-2]; /* */
+ union { /* PFCEn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PFCEn0:1; /* */
+ _UWORD PFCEn1:1; /* */
+ _UWORD PFCEn2:1; /* */
+ _UWORD PFCEn3:1; /* */
+ _UWORD PFCEn4:1; /* */
+ _UWORD PFCEn5:1; /* */
+ _UWORD PFCEn6:1; /* */
+ _UWORD PFCEn7:1; /* */
+ _UWORD PFCEn8:1; /* */
+ _UWORD PFCEn9:1; /* */
+ _UWORD PFCEn10:1; /* */
+ _UWORD PFCEn11:1; /* */
+ _UWORD PFCEn12:1; /* */
+ _UWORD PFCEn13:1; /* */
+ _UWORD PFCEn14:1; /* */
+ _UWORD PFCEn15:1; /* */
+ } BIT; /* */
+ } PFCEn; /* */
+ _UBYTE wk6[0x100-2]; /* */
+ union { /* PNOTn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PNOTn0:1; /* */
+ _UWORD PNOTn1:1; /* */
+ _UWORD PNOTn2:1; /* */
+ _UWORD PNOTn3:1; /* */
+ _UWORD PNOTn4:1; /* */
+ _UWORD PNOTn5:1; /* */
+ _UWORD PNOTn6:1; /* */
+ _UWORD PNOTn7:1; /* */
+ _UWORD PNOTn8:1; /* */
+ _UWORD PNOTn9:1; /* */
+ _UWORD PNOTn10:1; /* */
+ _UWORD PNOTn11:1; /* */
+ _UWORD PNOTn12:1; /* */
+ _UWORD PNOTn13:1; /* */
+ _UWORD PNOTn14:1; /* */
+ _UWORD PNOTn15:1; /* */
+ } BIT; /* */
+ } PNOTn; /* */
+ _UBYTE wk7[0x100-2]; /* */
+ union { /* PMSRn */
+ _UDWORD LONG; /* Long Access */
+ struct { /* WORD Access */
+ _UDWORD ENABLE:16; /* */
+ _UDWORD SET:16; /* */
+ } SET;
+ struct { /* Bit Access */
+ _UDWORD PMSRn0:1; /* */
+ _UDWORD PMSRn1:1; /* */
+ _UDWORD PMSRn2:1; /* */
+ _UDWORD PMSRn3:1; /* */
+ _UDWORD PMSRn4:1; /* */
+ _UDWORD PMSRn5:1; /* */
+ _UDWORD PMSRn6:1; /* */
+ _UDWORD PMSRn7:1; /* */
+ _UDWORD PMSRn8:1; /* */
+ _UDWORD PMSRn9:1; /* */
+ _UDWORD PMSRn10:1; /* */
+ _UDWORD PMSRn11:1; /* */
+ _UDWORD PMSRn12:1; /* */
+ _UDWORD PMSRn13:1; /* */
+ _UDWORD PMSRn14:1; /* */
+ _UDWORD PMSRn15:1; /* */
+ _UDWORD PMSRn16:1; /* */
+ _UDWORD PMSRn17:1; /* */
+ _UDWORD PMSRn18:1; /* */
+ _UDWORD PMSRn19:1; /* */
+ _UDWORD PMSRn20:1; /* */
+ _UDWORD PMSRn21:1; /* */
+ _UDWORD PMSRn22:1; /* */
+ _UDWORD PMSRn23:1; /* */
+ _UDWORD PMSRn24:1; /* */
+ _UDWORD PMSRn25:1; /* */
+ _UDWORD PMSRn26:1; /* */
+ _UDWORD PMSRn27:1; /* */
+ _UDWORD PMSRn28:1; /* */
+ _UDWORD PMSRn29:1; /* */
+ _UDWORD PMSRn30:1; /* */
+ _UDWORD PMSRn31:1; /* */
+ } BIT; /* */
+ } PMSRn; /* */
+ _UBYTE wk8[0x100-4]; /* */
+ union { /* PMCSRn */
+ _UDWORD LONG; /* Long Access */
+ struct { /* WORD Access */
+ _UDWORD ENABLE:16; /* */
+ _UDWORD SET:16; /* */
+ } SET;
+ struct { /* Bit Access */
+ _UDWORD PMCSRn0:1; /* */
+ _UDWORD PMCSRn1:1; /* */
+ _UDWORD PMCSRn2:1; /* */
+ _UDWORD PMCSRn3:1; /* */
+ _UDWORD PMCSRn4:1; /* */
+ _UDWORD PMCSRn5:1; /* */
+ _UDWORD PMCSRn6:1; /* */
+ _UDWORD PMCSRn7:1; /* */
+ _UDWORD PMCSRn8:1; /* */
+ _UDWORD PMCSRn9:1; /* */
+ _UDWORD PMCSRn10:1; /* */
+ _UDWORD PMCSRn11:1; /* */
+ _UDWORD PMCSRn12:1; /* */
+ _UDWORD PMCSRn13:1; /* */
+ _UDWORD PMCSRn14:1; /* */
+ _UDWORD PMCSRn15:1; /* */
+ _UDWORD PMCSRn16:1; /* */
+ _UDWORD PMCSRn17:1; /* */
+ _UDWORD PMCSRn18:1; /* */
+ _UDWORD PMCSRn19:1; /* */
+ _UDWORD PMCSRn20:1; /* */
+ _UDWORD PMCSRn21:1; /* */
+ _UDWORD PMCSRn22:1; /* */
+ _UDWORD PMCSRn23:1; /* */
+ _UDWORD PMCSRn24:1; /* */
+ _UDWORD PMCSRn25:1; /* */
+ _UDWORD PMCSRn26:1; /* */
+ _UDWORD PMCSRn27:1; /* */
+ _UDWORD PMCSRn28:1; /* */
+ _UDWORD PMCSRn29:1; /* */
+ _UDWORD PMCSRn30:1; /* */
+ _UDWORD PMCSRn31:1; /* */
+ } BIT; /* */
+ } PMCSRn; /* */
+ _UBYTE wk9[0x100-4]; /* */
+ union { /* PFACEn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PFCAEn0:1; /* */
+ _UWORD PFCAEn1:1; /* */
+ _UWORD PFCAEn2:1; /* */
+ _UWORD PFCAEn3:1; /* */
+ _UWORD PFCAEn4:1; /* */
+ _UWORD PFCAEn5:1; /* */
+ _UWORD PFCAEn6:1; /* */
+ _UWORD PFCAEn7:1; /* */
+ _UWORD PFCAEn8:1; /* */
+ _UWORD PFCAEn9:1; /* */
+ _UWORD PFCAEn10:1; /* */
+ _UWORD PFCAEn11:1; /* */
+ _UWORD PFCAEn12:1; /* */
+ _UWORD PFCAEn13:1; /* */
+ _UWORD PFCAEn14:1; /* */
+ _UWORD PFCAEn15:1; /* */
+ } BIT; /* */
+ } PFCAEn; /* */
+ _UBYTE wk10[0x4000-0xa00-2]; /* */
+ union { /* PIBCn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIBCn0:1; /* */
+ _UWORD PIBCn1:1; /* */
+ _UWORD PIBCn2:1; /* */
+ _UWORD PIBCn3:1; /* */
+ _UWORD PIBCn4:1; /* */
+ _UWORD PIBCn5:1; /* */
+ _UWORD PIBCn6:1; /* */
+ _UWORD PIBCn7:1; /* */
+ _UWORD PIBCn8:1; /* */
+ _UWORD PIBCn9:1; /* */
+ _UWORD PIBCn10:1; /* */
+ _UWORD PIBCn11:1; /* */
+ _UWORD PIBCn12:1; /* */
+ _UWORD PIBCn13:1; /* */
+ _UWORD PIBCn14:1; /* */
+ _UWORD PIBCn15:1; /* */
+ } BIT; /* */
+ } PIBCn; /* */
+ _UBYTE wk11[0x100-2]; /* */
+ union { /* PBDCn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PBDCn0:1; /* */
+ _UWORD PBDCn1:1; /* */
+ _UWORD PBDCn2:1; /* */
+ _UWORD PBDCn3:1; /* */
+ _UWORD PBDCn4:1; /* */
+ _UWORD PBDCn5:1; /* */
+ _UWORD PBDCn6:1; /* */
+ _UWORD PBDCn7:1; /* */
+ _UWORD PBDCn8:1; /* */
+ _UWORD PBDCn9:1; /* */
+ _UWORD PBDCn10:1; /* */
+ _UWORD PBDCn11:1; /* */
+ _UWORD PBDCn12:1; /* */
+ _UWORD PBDCn13:1; /* */
+ _UWORD PBDCn14:1; /* */
+ _UWORD PBDCn15:1; /* */
+ } BIT; /* */
+ } PBDCn; /* */
+ _UBYTE wk12[0x100-2]; /* */
+ union { /* PIPCn */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPCn0:1; /* */
+ _UWORD PIPCn1:1; /* */
+ _UWORD PIPCn2:1; /* */
+ _UWORD PIPCn3:1; /* */
+ _UWORD PIPCn4:1; /* */
+ _UWORD PIPCn5:1; /* */
+ _UWORD PIPCn6:1; /* */
+ _UWORD PIPCn7:1; /* */
+ _UWORD PIPCn8:1; /* */
+ _UWORD PIPCn9:1; /* */
+ _UWORD PIPCn10:1; /* */
+ _UWORD PIPCn11:1; /* */
+ _UWORD PIPCn12:1; /* */
+ _UWORD PIPCn13:1; /* */
+ _UWORD PIPCn14:1; /* */
+ _UWORD PIPCn15:1; /* */
+ } BIT; /* */
+ } PIPCn; /* */
+ _UBYTE wk13[0x100-2]; /* */
+}; /* */
+
+#define PORTn_BASE 0xFCFE3000
+
+#define PORT0 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 0))) /* PORT 0 Address */
+#define PORT1 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 1))) /* PORT 1 Address */
+#define PORT2 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 2))) /* PORT 2 Address */
+#define PORT3 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 3))) /* PORT 3 Address */
+#define PORT4 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 4))) /* PORT 4 Address */
+#define PORT5 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 5))) /* PORT 5 Address */
+#define PORT6 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 6))) /* PORT 6 Address */
+#define PORT7 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 7))) /* PORT 7 Address */
+#define PORT8 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 8))) /* PORT 8 Address */
+#define PORT9 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 9))) /* PORT 9 Address */
+#define PORT10 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 10))) /* PORT 10 Address */
+#define PORT11 (*(volatile struct st_pfc_n *)(PORTn_BASE + (4 * 11))) /* PORT 11 Address */
+
+
+#endif /* __PFC_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/prr_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/prr_iodefine.h
new file mode 100644
index 000000000..3bcd906a5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/prr_iodefine.h
@@ -0,0 +1,469 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : prr_iodefine.h
+* Version : 0.01
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* ARM Complier
+* :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program vecotr.s
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 27.07.2012 0.01 ŽQlŽ‘—¿FAragon_PRR120614.xls !!!BSID‚Ì“à—e‚ªŽd—l‘‚É‚È‚¢!!!
+*******************************************************************************/
+#ifndef __PRR_IODEFINE_H__
+#define __PRR_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_prr { /* struct PRR */
+ union { /* MDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BTMD:3; /* BTMD */
+ _UDWORD :1; /* */
+ _UDWORD BTTEST:1; /* BTTEST */
+ _UDWORD :1; /* */
+ _UDWORD SEC:1; /* SEC */
+ _UDWORD SELFEWP:1; /* SELFEWP */
+ _UDWORD RAMBOOT:1; /* RAMBOOT */
+ _UDWORD :23; /* */
+ } BIT; /* */
+ } MDR; /* */
+ union { /* BSID */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD dummy:32; /* */ /* !!!ƒrƒbƒgŒˆ’莟‘æA’è‹`‚·‚é!!! */
+ } BIT; /* */
+ } BSID; /* */
+ union { /* ECCRR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ECCEN:1; /* ECCEN */
+ _UDWORD :31; /* */
+ } BIT; /* */
+ } ECCRR; /* */
+ _UBYTE wk0[276]; /* */
+ union { /* SEMRn */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SEMF:1; /* SEMF */
+ _UDWORD :31; /* */
+ } BIT; /* */
+ } SEMRn[32]; /* */
+ _UBYTE wk1[96]; /* */
+ union { /* RMPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD AXI64:1; /* AXI64 */
+ _UDWORD AXI128:1; /* AXI128 */
+ _UDWORD :30; /* */
+ } BIT; /* */
+ } RMPR; /* */
+ union { /* AXIBUSCTL0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ETHAWCACHE:4; /* ETHAWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD ETHARCACHE:4; /* ETHARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD JCUAWCACHE:4; /* JCUAWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD JCUARCACHE:4; /* JCUARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL0; /* */
+ union { /* AXIBUSCTL1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD IMR21AWCACHE:4; /* IMR21AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD IMR21ARCACHE:4; /* IMR21ARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD IMR20AWCACHE:4; /* IMR20AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD IMR20ARCACHE:4; /* IMR20ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL1; /* */
+ union { /* AXIBUSCTL2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD CEUAWCACHE:4; /* CEUAWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD CEUARCACHE:4; /* CEUARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD IMRDAWCACHE:4; /* IMRDAWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD IMRDARCACHE:4; /* IMRDARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL2; /* */
+ union { /* AXIBUSCTL3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RGP641AWCACHE:4; /* RGP641AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP641ARCACHE:4; /* RGP641ARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP640AWCACHE:4; /* RGP640AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP640ARCACHE:4; /* RGP640ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL3; /* */
+ union { /* AXIBUSCTL4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD RGP1280AWCACHE:4; /* RGP1280AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP1280ARCACHE:4; /* RGP1280ARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP642AWCACHE:4; /* RGP642AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP642ARCACHE:4; /* RGP642ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL4; /* */
+ union { /* AXIBUSCTL5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD MLB_AxCACHE:2; /* MLB_AxCACHE */
+ _UDWORD :14; /* */
+ _UDWORD RGP1281AWCACHE:4; /* RGP1281AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD RGP1281ARCACHE:4; /* RGP1281ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL5; /* */
+ union { /* AXIBUSCTL6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD VDC502ARCACHE:4; /* VDC502ARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC501AWCACHE:4; /* VDC501AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC501ARCACHE:4; /* VDC501ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL6; /* */
+ union { /* AXIBUSCTL7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD VDC504ARCACHE:4; /* VDC504ARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC503AWCACHE:4; /* VDC503AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC503ARCACHE:4; /* VDC503ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL7; /* */
+ union { /* AXIBUSCTL8 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD VDC511AWCACHE:4; /* VDC511AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC511ARCACHE:4; /* VDC511ARCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC505AWCACHE:4; /* VDC505AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC505ARCACHE:4; /* VDC505ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL8; /* */
+ union { /* AXIBUSCTL9 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD VDC513AWCACHE:4; /* VDC513AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC513ARCACHE:4; /* VDC513ARCACHE */
+ _UDWORD :12; /* */
+ _UDWORD VDC512ARCACHE:4; /* VDC512ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL9; /* */
+ union { /* AXIBUSCTL10 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD VDC515AWCACHE:4; /* VDC515AWCACHE */
+ _UDWORD :4; /* */
+ _UDWORD VDC515ARCACHE:4; /* VDC515ARCACHE */
+ _UDWORD :12; /* */
+ _UDWORD VDC514ARCACHE:4; /* VDC514ARCACHE */
+ _UDWORD :4; /* */
+ } BIT; /* */
+ } AXIBUSCTL10; /* */
+ union { /* AXIRERRCTL0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD CEURERREN:1; /* CEURERREN */
+ _UDWORD :3; /* */
+ _UDWORD IMRDRERREN:1; /* IMRDRERREN */
+ _UDWORD :3; /* */
+ _UDWORD IMR21RERREN:1; /* IMR21RERREN */
+ _UDWORD :3; /* */
+ _UDWORD IMR20RERREN:1; /* IMR20RERREN */
+ _UDWORD :3; /* */
+ _UDWORD ETHRERREN:1; /* ETHRERREN */
+ _UDWORD :3; /* */
+ _UDWORD JCURERREN:1; /* JCURERREN */
+ _UDWORD :3; /* */
+ } BIT; /* */
+ } AXIRERRCTL0; /* */
+ union { /* AXIRERRCTL1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD RGP1281RERREN:1; /* RGP1281RERREN */
+ _UDWORD :3; /* */
+ _UDWORD RGP1280RERREN:1; /* RGP1280RERREN */
+ _UDWORD :3; /* */
+ _UDWORD RGP642RERREN:1; /* RGP642RERREN */
+ _UDWORD :3; /* */
+ _UDWORD RGP641RERREN:1; /* RGP641RERREN */
+ _UDWORD :3; /* */
+ _UDWORD RGP640RERREN:1; /* RGP640RERREN */
+ _UDWORD :3; /* */
+ } BIT; /* */
+ } AXIRERRCTL1; /* */
+ union { /* AXIRERRCTL2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD VDC505RERREN:1; /* VDC505RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC504RERREN:1; /* VDC504RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC503RERREN:1; /* VDC503RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC502RERREN:1; /* VDC502RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC501RERREN:1; /* VDC501RERREN */
+ _UDWORD :3; /* */
+ } BIT; /* */
+ } AXIRERRCTL2; /* */
+ union { /* AXIRERRCTL3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD VDC515RERREN:1; /* VDC515RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC514RERREN:1; /* VDC514RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC513RERREN:1; /* VDC513RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC512RERREN:1; /* VDC512RERREN */
+ _UDWORD :3; /* */
+ _UDWORD VDC511RERREN:1; /* VDC511RERREN */
+ _UDWORD :3; /* */
+ } BIT; /* */
+ } AXIRERRCTL3; /* */
+ union { /* AXIRERRST0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD CEUBRESP:2; /* CEUBRESP */
+ _UDWORD CEURRESP:2; /* CEURRESP */
+ _UDWORD IMRDBRESP:2; /* IMRDBRESP */
+ _UDWORD IMRDRRESP:2; /* IMRDRRESP */
+ _UDWORD IMR21BRESP:2; /* IMR21BRESP */
+ _UDWORD IMR21RRESP:2; /* IMR21RRESP */
+ _UDWORD IMR20BRESP:2; /* IMR20BRESP */
+ _UDWORD IMR20RRESP:2; /* IMR20RRESP */
+ _UDWORD ETHBRESP:2; /* ETHBRESP */
+ _UDWORD ETHRRESP:2; /* ETHRRESP */
+ _UDWORD JCUBRESP:2; /* JCUBRESP */
+ _UDWORD JCURRESP:2; /* JCURRESP */
+ } BIT; /* */
+ } AXIRERRST0; /* */
+ union { /* AXIRERRST1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD RGP1281BRESP:2; /* RGP1281BRESP */
+ _UDWORD RGP1281RRESP:2; /* RGP1281RRESP */
+ _UDWORD RGP1280BRESP:2; /* RGP1280BRESP */
+ _UDWORD RGP1280RRESP:2; /* RGP1280RRESP */
+ _UDWORD RGP642BRESP:2; /* RGP642BRESP */
+ _UDWORD RGP642RRESP:2; /* RGP642RRESP */
+ _UDWORD RGP641BRESP:2; /* RGP641BRESP */
+ _UDWORD RGP641RRESP:2; /* RGP641RRESP */
+ _UDWORD RGP640BRESP:2; /* RGP640BRESP */
+ _UDWORD RGP640RRESP:2; /* RGP640RRESP */
+ } BIT; /* */
+ } AXIRERRST1; /* */
+ union { /* AXIRERRST2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD VDC505BRESP:2; /* VDC505BRESP */
+ _UDWORD VDC505RRESP:2; /* VDC505RRESP */
+ _UDWORD VDC504BRESP:2; /* VDC504BRESP */
+ _UDWORD VDC504RRESP:2; /* VDC504RRESP */
+ _UDWORD VDC503BRESP:2; /* VDC503BRESP */
+ _UDWORD VDC503RRESP:2; /* VDC503RRESP */
+ _UDWORD VDC502BRESP:2; /* VDC502BRESP */
+ _UDWORD VDC502RRESP:2; /* VDC502RRESP */
+ _UDWORD VDC501BRESP:2; /* VDC501BRESP */
+ _UDWORD VDC501RRESP:2; /* VDC501RRESP */
+ } BIT; /* */
+ } AXIRERRST2; /* */
+ union { /* AXIRERRST3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD VDC515BRESP:2; /* VDC515BRESP */
+ _UDWORD VDC515RRESP:2; /* VDC515RRESP */
+ _UDWORD VDC514BRESP:2; /* VDC514BRESP */
+ _UDWORD VDC514RRESP:2; /* VDC514RRESP */
+ _UDWORD VDC513BRESP:2; /* VDC513BRESP */
+ _UDWORD VDC513RRESP:2; /* VDC513RRESP */
+ _UDWORD VDC512BRESP:2; /* VDC512BRESP */
+ _UDWORD VDC512RRESP:2; /* VDC512RRESP */
+ _UDWORD VDC511BRESP:2; /* VDC511BRESP */
+ _UDWORD VDC511RRESP:2; /* VDC511RRESP */
+ } BIT; /* */
+ } AXIRERRST3; /* */
+ union { /* AXIRERRCLR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :8; /* */
+ _UDWORD CEUBRESPCLR:1; /* CEUBRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD CEURRESPCLR:1; /* CEURRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD IMRDBRESPCLR:1; /* IMRDBRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD IMRDRRESPCLR:1; /* IMRDRRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD IMR21BRESPCLR:1; /* IMR21BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD IMR21RRESPCLR:1; /* IMR21RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD IMR20BRESPCLR:1; /* IMR20BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD IMR20RRESPCLR:1; /* IMR20RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD ETHBRESPCLR:1; /* ETHBRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD ETHRRESPCLR:1; /* ETHRRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD JCUBRESPCLR:1; /* JCUBRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD JCURRESPCLR:1; /* JCURRESPCLR */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } AXIRERRCLR0; /* */
+ union { /* AXIRERRCLR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD RGP1281BRESPCLR:1; /* RGP1281BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP1281RRESPCLR:1; /* RGP1281RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP1280BRESPCLR:1; /* RGP1280BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP1280RRESPCLR:1; /* RGP1280RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP642BRESPCLR:1; /* RGP642BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP642RRESPCLR:1; /* RGP642RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP641BRESPCLR:1; /* RGP641BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP641RRESPCLR:1; /* RGP641RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP640BRESPCLR:1; /* RGP640BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD RGP640RRESPCLR:1; /* RGP640RRESPCLR */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } AXIRERRCLR1; /* */
+ union { /* AXIRERRCLR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD VDC505BRESPCLR:1; /* VDC505BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC505RRESPCLR:1; /* VDC505RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC504BRESPCLR:1; /* VDC504BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC504RRESPCLR:1; /* VDC504RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC503BRESPCLR:1; /* VDC503BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC503RRESPCLR:1; /* VDC503RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC502BRESPCLR:1; /* VDC502BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC502RRESPCLR:1; /* VDC502RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC501BRESPCLR:1; /* VDC501BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC501RRESPCLR:1; /* VDC501RRESPCLR */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } AXIRERRCLR2; /* */
+ union { /* AXIRERRCLR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :12; /* */
+ _UDWORD VDC515BRESPCLR:1; /* VDC515BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC515RRESPCLR:1; /* VDC515RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC514BRESPCLR:1; /* VDC514BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC514RRESPCLR:1; /* VDC514RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC513BRESPCLR:1; /* VDC513BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC513RRESPCLR:1; /* VDC513RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC512BRESPCLR:1; /* VDC512BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC512RRESPCLR:1; /* VDC512RRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC511BRESPCLR:1; /* VDC511BRESPCLR */
+ _UDWORD :1; /* */
+ _UDWORD VDC511RRESPCLR:1; /* VDC511RRESPCLR */
+ _UDWORD :1; /* */
+ } BIT; /* */
+ } AXIRERRCLR3; /* */
+}; /* */
+
+#define PRR (*(volatile struct st_prr *)0xFCFE1800) /* PRR Address */
+
+
+#endif /* __PRR_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/riic_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/riic_iodefine.h
new file mode 100644
index 000000000..a6a840056
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/riic_iodefine.h
@@ -0,0 +1,229 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : riic_iodefine.h
+* Version : 0.01
+* Device(s) : Aragon
+* Tool-Chain : DS-5 Ver 5.8
+* ARM Complier
+* :
+* H/W Platform : Aragon CPU Board
+* Description : Aragon Sample Program vecotr.s
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 27.07.2012 0.01 ŽQlŽ‘—¿FRZ_A1H_05J_121010_11.pdf
+*******************************************************************************/
+#ifndef __RIIC_IODEFINE_H__
+#define __RIIC_IODEFINE_H__
+
+#include "typedefine.h"
+
+typedef union { /* RIICnICSARy */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SVA0:1; /* SVA0 */
+ _UDWORD SVA:9; /* SVA */
+ _UDWORD :5; /* */
+ _UDWORD FSy:1; /* FSy */
+ _UDWORD :16; /* */
+ } BIT; /* */
+} RIICnICSARy; /* */
+
+struct st_riic_n { /* struct RIIC */
+ union { /* RIICnICCR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SDAI:1; /* SDAI */
+ _UDWORD SCLI:1; /* SCLI */
+ _UDWORD SDAO:1; /* SDAO */
+ _UDWORD SCLO:1; /* SCLO */
+ _UDWORD SOWP:1; /* SOWP */
+ _UDWORD CLO:1; /* CLO */
+ _UDWORD IICRST:1; /* IICRST */
+ _UDWORD ICE:1; /* ICE */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICCR1; /* */
+ union { /* RIICnICCR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :1; /* */
+ _UDWORD ST:1; /* ST */
+ _UDWORD RS:1; /* RS */
+ _UDWORD SP:1; /* SP */
+ _UDWORD :1; /* */
+ _UDWORD TRS:1; /* TRS */
+ _UDWORD MST:1; /* MST */
+ _UDWORD BBSY:1; /* BBSY */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICCR2; /* */
+ union { /* RIICnICMR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BC:3; /* BC */
+ _UDWORD BCWP:1; /* BCWP */
+ _UDWORD CKS:3; /* CKS */
+ _UDWORD MTWP:1; /* MTWP */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICMR1; /* */
+ union { /* RIICnICMR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOS:1; /* TMOS */
+ _UDWORD TMOL:1; /* TMOL */
+ _UDWORD TMOH:1; /* TMOH */
+ _UDWORD :1; /* */
+ _UDWORD SDDL:3; /* SDDL */
+ _UDWORD DLCS:1; /* DLCS */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICMR2; /* */
+ union { /* RIICnICMR3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD NF:2; /* NF */
+ _UDWORD ACKBR:1; /* ACKBR */
+ _UDWORD ACKBT:1; /* ACKBT */
+ _UDWORD ACKWP:1; /* ACKWP */
+ _UDWORD RDRFS:1; /* RDRFS */
+ _UDWORD WAIT:1; /* WAIT */
+ _UDWORD SMBS:1; /* SMBS */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICMR3; /* */
+ union { /* RIICnICFER */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOE:1; /* TMOE */
+ _UDWORD MALE:1; /* MALE */
+ _UDWORD NALE:1; /* NALE */
+ _UDWORD SALE:1; /* SALE */
+ _UDWORD NACKE:1; /* NACKE */
+ _UDWORD NFE:1; /* NFE */
+ _UDWORD SCLE:1; /* SCLE */
+ _UDWORD FMPE:1; /* FMPE */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICFER; /* */
+ union { /* RIICnICSER */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SAR0E:1; /* SAR0E */
+ _UDWORD SAR1E:1; /* SAR1E */
+ _UDWORD SAR2E:1; /* SAR2E */
+ _UDWORD GCAE:1; /* GCAE */
+ _UDWORD :1; /* */
+ _UDWORD DIDE:1; /* DIDE */
+ _UDWORD :1; /* */
+ _UDWORD HOAE:1; /* HOAE */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICSER; /* */
+ union { /* RIICnICIER */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOIE:1; /* TMOIE */
+ _UDWORD ALIE:1; /* ALIE */
+ _UDWORD STIE:1; /* STIE */
+ _UDWORD SPIE:1; /* SPIE */
+ _UDWORD NAKIE:1; /* NAKIE */
+ _UDWORD RIE:1; /* RIE */
+ _UDWORD TEIE:1; /* TEIE */
+ _UDWORD TIE:1; /* TIE */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICIER; /* */
+ union { /* RIICnICSR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD AAS0:1; /* AAS0 */
+ _UDWORD AAS1:1; /* AAS1 */
+ _UDWORD AAS2:1; /* AAS2 */
+ _UDWORD GCA:1; /* GCA */
+ _UDWORD :1; /* */
+ _UDWORD DID:1; /* DID */
+ _UDWORD :1; /* */
+ _UDWORD HOA:1; /* HOA */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICSR1; /* */
+ union { /* RIICnICSR2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TMOF:1; /* TMOF */
+ _UDWORD AL:1; /* AL */
+ _UDWORD START:1; /* START */
+ _UDWORD STOP:1; /* STOP */
+ _UDWORD NACKF:1; /* NACKF */
+ _UDWORD RDRF:1; /* RDRF */
+ _UDWORD TEND:1; /* TEND */
+ _UDWORD TDRE:1; /* TDRE */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICSR2; /* */
+ RIICnICSARy RIICnICSAR0; /* RIICnICSAR0 */
+ RIICnICSARy RIICnICSAR1; /* RIICnICSAR1 */
+ RIICnICSARy RIICnICSAR2; /* RIICnICSAR2 */
+ union { /* RIICnICBRL */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BRL:5; /* BRL */
+ _UDWORD :27; /* */
+ } BIT; /* */
+ } RIICnICBRL; /* */
+ union { /* RIICnICBRH */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BRH:5; /* BRH */
+ _UDWORD :27; /* */
+ } BIT; /* */
+ } RIICnICBRH; /* */
+ union { /* RIICnICDRT */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ICDRS:8; /* ICDRS */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICDRT; /* */
+ union { /* RIICnICDRR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ICDRR:8; /* ICDRR */
+ _UDWORD :24; /* */
+ } BIT; /* */
+ } RIICnICDRR; /* */
+}; /* */
+
+#define RIIC_0 (*(volatile struct st_riic_n *)0xFCFEE000) /* RIIC_0 Address */
+#define RIIC_1 (*(volatile struct st_riic_n *)0xFCFEE400) /* RIIC_1 Address */
+#define RIIC_2 (*(volatile struct st_riic_n *)0xFCFEE800) /* RIIC_2 Address */
+#define RIIC_3 (*(volatile struct st_riic_n *)0xFCFEEC00) /* RIIC_3 Address */
+
+
+#endif /* __RIIC_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/scif_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/scif_iodefine.h
new file mode 100644
index 000000000..bfddb1ba6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/scif_iodefine.h
@@ -0,0 +1,183 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name :
+* File Name : scif_iodefine.h
+* Abstract :
+* Version : 1.00.00
+* Device : ARM
+* Tool-Chain :
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : Mar.06,2012 Ver.1.00.00
+*******************************************************************************/
+#ifndef __SCIF_IODEFINE_H__
+#define __SCIF_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_scif_n { /* struct SCIF */
+ union { /* SCSMR_0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CKS:2; /* CKS */
+ _UWORD :1; /* */
+ _UWORD STOP:1; /* STOP */
+ _UWORD OE:1; /* O/E */
+ _UWORD PE:1; /* PE */
+ _UWORD CHR:1; /* CHR */
+ _UWORD CA:1; /* C/A */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } SCSMR; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* SCBRR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCBRR; /* */
+ _UBYTE wk1[3]; /* */
+ union { /* SCSCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CKE:2; /* CKE */
+ _UWORD :1; /* */
+ _UWORD REIE:1; /* REIE */
+ _UWORD RE:1; /* RE */
+ _UWORD TE:1; /* TE */
+ _UWORD RIE:1; /* RIE */
+ _UWORD TIE:1; /* TIE */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } SCSCR; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* SCFTDR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCFTDR; /* */
+ _UBYTE wk3[3]; /* */
+ union { /* SCFSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DR:1; /* DR */
+ _UWORD RDF:1; /* RDF */
+ _UWORD PER:1; /* PER */
+ _UWORD FER:1; /* FER */
+ _UWORD BRK:1; /* BRK */
+ _UWORD TDFE:1; /* TDFE */
+ _UWORD TEND:1; /* TEND */
+ _UWORD ER:1; /* ER */
+ _UWORD FERN:4; /* FERN */
+ _UWORD PERN:4; /* PERN */
+ } BIT; /* */
+ } SCFSR; /* */
+ _UBYTE wk4[2]; /* */
+ union { /* SCFRDR */
+ _UBYTE BYTE; /* Byte Access */
+ struct { /* Bit Access */
+ _UBYTE D:8; /* D */
+ } BIT; /* */
+ } SCFRDR; /* */
+ _UBYTE wk5[3]; /* */
+ union { /* SCFCR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD LOOP:1; /* LOOP */
+ _UWORD RFRST:1; /* RFRST */
+ _UWORD TFRST:1; /* TFRST */
+ _UWORD MCE:1; /* MCE */
+ _UWORD TTRG:2; /* TTRG */
+ _UWORD RTRG:2; /* RTRG */
+ _UWORD RSTRG:3; /* RSTRG */
+ _UWORD :5; /* */
+ } BIT; /* */
+ } SCFCR; /* */
+ _UBYTE wk6[2]; /* */
+ union { /* SCFDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD R:5; /* R */
+ _UWORD :3; /* */
+ _UWORD T:5; /* T */
+ _UWORD :3; /* */
+ } BIT; /* */
+ } SCFDR; /* */
+ _UBYTE wk7[2]; /* */
+ union { /* SCSPTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD SPB2DT:1; /* SPB2DT */
+ _UWORD SPB2IO:1; /* SPB2IO */
+ _UWORD SCKDT:1; /* SCKDT */
+ _UWORD SCKIO:1; /* SCKIO */
+ _UWORD CTSDT:1; /* CTSDT */
+ _UWORD CTSIO:1; /* CTSIO */
+ _UWORD RTSDT:1; /* RTSDT */
+ _UWORD RTSIO:1; /* RTSIO */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } SCSPTR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* SCLSR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD ORER:1; /* ORER */
+ _UWORD :15; /* */
+ } BIT; /* */
+ } SCLSR; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* SCEMR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD ABCS:1; /* ABCS */
+ _UWORD :6; /* */
+ _UWORD BGDM:1; /* BGDM */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } SCEMR; /* */
+}; /* */
+
+#define SCIF0 (*(volatile struct st_scif_n *)0xE8007000) /* SCIF0 Address */
+#define SCIF1 (*(volatile struct st_scif_n *)0xE8007800) /* SCIF1 Address */
+#define SCIF2 (*(volatile struct st_scif_n *)0xE8008000) /* SCIF2 Address */
+#define SCIF3 (*(volatile struct st_scif_n *)0xE8008800) /* SCIF3 Address */
+#define SCIF4 (*(volatile struct st_scif_n *)0xE8009000) /* SCIF4 Address */
+#define SCIF5 (*(volatile struct st_scif_n *)0xE8009800) /* SCIF5 Address */
+#define SCIF6 (*(volatile struct st_scif_n *)0xE800A000) /* SCIF6 Address */
+#define SCIF7 (*(volatile struct st_scif_n *)0xE800A800) /* SCIF7 Address */
+
+
+#endif /* __SCIF_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/spibsc_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/spibsc_iodefine.h
new file mode 100644
index 000000000..07baf1cd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/spibsc_iodefine.h
@@ -0,0 +1,326 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spibsc_iodefine.h
+* Version : 0.01
+* Device(s) :
+* Tool-Chain : DS-5 Ver 5.8
+* ARM Complier
+* :
+* H/W Platform : CPU Board
+* Description :
+*******************************************************************************/
+/*******************************************************************************
+* History : 05.11.2012 0.01 Version Description
+*******************************************************************************/
+#ifndef __SPIBSC_IODEFINE_H__
+#define __SPIBSC_IODEFINE_H__
+
+#include "typedefine.h"
+
+
+/****************************************************************/
+/* SPIBSC */
+/****************************************************************/
+struct st_spibsc_n { /* struct SPIBSC*/
+ union { /* CMNCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BSZ:2; /* BSZ */
+ _UDWORD :1; /* */
+ _UDWORD CPOL:1; /* CPOL */
+ _UDWORD SSLP:1; /* SSLP */
+ _UDWORD CPHAR:1; /* CPHAR */
+ _UDWORD CPHAT:1; /* CPHAT */
+ _UDWORD :1; /* */
+ _UDWORD IO0FV:2; /* IO0FV */
+ _UDWORD :2; /* */
+ _UDWORD IO2FV:2; /* IO2FV */
+ _UDWORD IO3FV:2; /* IO3FV */
+ _UDWORD MOIIO0:2; /* MOIIO0 */
+ _UDWORD MOIIO1:2; /* MOIIO1 */
+ _UDWORD MOIIO2:2; /* MOIIO2 */
+ _UDWORD MOIIO3:2; /* MOIIO3 */
+ _UDWORD :7; /* */
+ _UDWORD MD:1; /* MD */
+ } BIT; /* */
+ } CMNCR; /* */
+ union { /* SSLDR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SCKDL:3; /* SCKDL */
+ _UDWORD :5; /* */
+ _UDWORD SLNDL:3; /* SLNDL */
+ _UDWORD :5; /* */
+ _UDWORD SPNDL:3; /* SPNDL */
+ _UDWORD :13; /* */
+ } BIT; /* */
+ } SSLDR; /* */
+ union { /* SPBCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD BRDV:2; /* BRDV */
+ _UDWORD :6; /* */
+ _UDWORD SPBR:8; /* SPBR */
+ _UDWORD :16; /* */
+ } BIT; /* */
+ } SPBCR; /* */
+ union { /* DRCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SSLE:1; /* SSLE */
+ _UDWORD :7; /* */
+ _UDWORD RBE:1; /* RBE */
+ _UDWORD RCF:1; /* RCF */
+ _UDWORD :6; /* */
+ _UDWORD RBURST:4; /* RBURST */
+ _UDWORD :4; /* */
+ _UDWORD SSLN:1; /* SSLN */
+ _UDWORD :7; /* */
+ } BIT; /* */
+ } DRCR; /* */
+ union { /* DRCMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OCMD:8; /* OCMD */
+ _UDWORD :8; /* */
+ _UDWORD CMD:8; /* CMD */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } DRCMR; /* */
+ union { /* DREAR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD EAC:3; /* EAC */
+ _UDWORD :13; /* */
+ _UDWORD EAV:8; /* EAV */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } DREAR; /* */
+ union { /* DROPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OPD0:8; /* OPD0 */
+ _UDWORD OPD1:8; /* OPD1 */
+ _UDWORD OPD2:8; /* OPD2 */
+ _UDWORD OPD3:8; /* OPD3 */
+ } BIT; /* */
+ } DROPR; /* */
+ union { /* DRENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD :4; /* */
+ _UDWORD OPDE:4; /* OPDE */
+ _UDWORD ADE:4; /* ADE */
+ _UDWORD OCDE:1; /* OCDE */
+ _UDWORD :1; /* */
+ _UDWORD CDE:1; /* CDE */
+ _UDWORD DME:1; /* DME */
+ _UDWORD DRDB:2; /* DRDB */
+ _UDWORD :2; /* */
+ _UDWORD OPDB:2; /* OPDB */
+ _UDWORD :2; /* */
+ _UDWORD ADB:2; /* ADB */
+ _UDWORD :2; /* */
+ _UDWORD OCDB:2; /* OCDB */
+ _UDWORD CDB:2; /* CDB */
+ } BIT; /* */
+ } DRENR; /* */
+ union { /* SMCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPIE:1; /* SPIE */
+ _UDWORD SPIWE:1; /* SPIWE */
+ _UDWORD SPIRE:1; /* SPIRE */
+ _UDWORD :5; /* */
+ _UDWORD SSLKP:1; /* SSLKP */
+ _UDWORD :23; /* */
+ } BIT; /* */
+ } SMCR; /* */
+ union { /* SMCMR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OCMD:8; /* OCMD */
+ _UDWORD :8; /* */
+ _UDWORD CMD:8; /* CMD */
+ _UDWORD :8; /* */
+ } BIT; /* */
+ } SMCMR; /* */
+ union { /* SMADR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD ADR:32; /* ADR */
+ } BIT; /* */
+ } SMADR; /* */
+ union { /* SMOPR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD OPD0:8; /* OPD0 */
+ _UDWORD OPD1:8; /* OPD1 */
+ _UDWORD OPD2:8; /* OPD2 */
+ _UDWORD OPD3:8; /* OPD3 */
+ } BIT; /* */
+ } SMOPR; /* */
+ union { /* SMENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPIDE:4; /* SPIDE */
+ _UDWORD OPDE:4; /* OPDE */
+ _UDWORD ADE:4; /* ADE */
+ _UDWORD OCDE:1; /* OCDE */
+ _UDWORD :1; /* */
+ _UDWORD CDE:1; /* CDE */
+ _UDWORD DME:1; /* DME */
+ _UDWORD SPIDB:2; /* SPIDB */
+ _UDWORD :2; /* */
+ _UDWORD OPDB:2; /* OPDB */
+ _UDWORD :2; /* */
+ _UDWORD ADB:2; /* ADB */
+ _UDWORD :2; /* */
+ _UDWORD OCDB:2; /* OCDB */
+ _UDWORD CDB:2; /* CDB */
+ } BIT; /* */
+ } SMENR; /* */
+ _UBYTE wk0[4]; /* */
+ union { /* SMRDR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD L; /* Low */
+ _UWORD H; /* High */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE LL; /* Low, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE HH; /* High, High */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD RDATA0:32; /* RDATA0 */
+ } BIT; /* */
+ } SMRDR0; /* */
+ union { /* SMRDR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD L; /* Low */
+ _UWORD H; /* High */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE LL; /* Low, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE HH; /* High, High */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD RDATA1:32; /* RDATA1 */
+ } BIT; /* */
+ } SMRDR1; /* */
+ union { /* SMWDR0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD L; /* Low */
+ _UWORD H; /* High */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE LL; /* Low, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE HH; /* High, High */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD WDATA0:32; /* WDATA0 */
+ } BIT; /* */
+ } SMWDR0; /* */
+ union { /* SMWDR1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Word Access */
+ _UWORD L; /* Low */
+ _UWORD H; /* High */
+ } WORD; /* */
+ struct { /* Byte Access */
+ _UBYTE LL; /* Low, Low */
+ _UBYTE LH; /* Low, High */
+ _UBYTE HL; /* High, Low */
+ _UBYTE HH; /* High, High */
+ } BYTE; /* */
+ struct { /* Bit Access */
+ _UDWORD WDATA1:32; /* WDATA1 */
+ } BIT; /* */
+ } SMWDR1; /* */
+ union { /* CMNSR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD TEND:1; /* TEND */
+ _UDWORD SSLF:1; /* SSLF */
+ _UDWORD :30; /* */
+ } BIT; /* */
+ } CMNSR; /* */
+ _UBYTE wk1[12]; /* */
+ union { /* DRDMCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMCYC:3; /* */
+ _UDWORD :13; /* */
+ _UDWORD DMDB:2; /* */
+ _UDWORD :14; /* */
+ } BIT; /* */
+ } DRDMCR; /* */
+ union { /* DRDRENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DRDRE:1; /* */
+ _UDWORD :3; /* */
+ _UDWORD OPDRE:1; /* */
+ _UDWORD :3; /* */
+ _UDWORD ADDRE:1; /* */
+ _UDWORD :23; /* */
+ } BIT; /* */
+ } DRDRENR; /* */
+
+ union { /* SMDMCR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD DMCYC:3; /* */
+ _UDWORD :13; /* */
+ _UDWORD DMDB:2; /* */
+ _UDWORD :14; /* */
+ } BIT; /* */
+ } SMDMCR; /* */
+ union { /* SMDRENR */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD SPIDRE:1; /* */
+ _UDWORD :3; /* */
+ _UDWORD OPDRE:1; /* */
+ _UDWORD :3; /* */
+ _UDWORD ADDRE:1; /* */
+ _UDWORD :23; /* */
+ } BIT; /* */
+ } SMDRENR; /* */
+}; /* */
+
+#define SPIBSC0 (*(volatile struct st_spibsc_n *)0x3FEFA000)
+#define SPIBSC1 (*(volatile struct st_spibsc_n *)0x3FEFB000)
+
+
+#endif /* __SPIBSC_IODEFINE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/usb_iodefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/usb_iodefine.h
new file mode 100644
index 000000000..3958fe27e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/usb_iodefine.h
@@ -0,0 +1,1136 @@
+/******************************************************************************
+* DISCLAIMER
+*
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized.
+*
+* This software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
+* DISCLAIMED.
+*
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Renesas reserves the right, without notice, to make changes to this
+* software and to discontinue the availability of this software.
+* By using this software, you agree to the additional terms and
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+********************************************************************************
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+**************************** Technical reference data **************************
+* System Name :
+* File Name : usb_iodefine.h
+* Abstract :
+* Version : 1.00.00
+* Device : ARM
+* Tool-Chain :
+* OS : None
+* H/W Platform:
+* Description :
+********************************************************************************
+* History : Mar.06,2012 Ver.1.00.00
+*******************************************************************************/
+#ifndef __USB_IODEFINE_H__
+#define __USB_IODEFINE_H__
+
+#include "typedefine.h"
+
+struct st_usb_n { /* struct USB */
+ union { /* SYSCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD USBE:1; /* USBE */
+ _UWORD UPLLE:1; /* UPLLE */
+ _UWORD UCKSEL:1; /* UCKSEL */
+ _UWORD :1; /* */
+ _UWORD DPRPU:1; /* DPRPU */
+ _UWORD DRPD:1; /* DRPD */
+ _UWORD DCFM:1; /* DCFM */
+ _UWORD HSE:1; /* HSE */
+ _UWORD :8; /* */
+ } BIT; /* */
+ } SYSCFG; /* */
+ union { /* BUSWAIT */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BWAIT:6; /* BWAIT */
+ _UWORD :10; /* */
+ } BIT; /* */
+ } BUSWAIT; /* */
+ union { /* SYSSTS0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD LNST:2; /* LNST */
+ _UWORD :14; /* */
+ } BIT; /* */
+ } SYSSTS0; /* */
+ _UBYTE wk0[2]; /* */
+ union { /* DVSTCTR0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD RHST:3; /* RHST */
+ _UWORD :1; /* */
+ _UWORD UACT:1; /* UACT */
+ _UWORD RESUME:1; /* RESUME */
+ _UWORD USBRST:1; /* USBRST */
+ _UWORD RWUPE:1; /* RWUPE */
+ _UWORD WKUP:1; /* WKUP */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } DVSTCTR0; /* */
+ _UBYTE wk1[2]; /* */
+ union { /* UTEST */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD UTST:4; /* UTST */
+ _UWORD :12; /* */
+ } BIT; /* */
+ } UTEST; /* */
+ _UBYTE wk2[2]; /* */
+ union { /* D0FBCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD TENDE:1; /* TENDE */
+ _UWORD :7; /* */
+ _UWORD DFACC:2; /* DFACC */
+ _UWORD :2; /* */
+ } BIT; /* */
+ } D0FBCFG; /* */
+ union { /* D1FBCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD TENDE:1; /* TENDE */
+ _UWORD :7; /* */
+ _UWORD DFACC:2; /* DFACC */
+ _UWORD :2; /* */
+ } BIT; /* */
+ } D1FBCFG; /* */
+ union { /* CFIFO */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD[2]; /* Word Access */
+ _UBYTE BYTE[4]; /* Byte Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } CFIFO; /* */
+ union { /* D0FIFO */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD[2]; /* Word Access */
+ _UBYTE BYTE[4]; /* Byte Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFO; /* */
+ union { /* D1FIFO */
+ _UDWORD LONG; /* Long Access */
+ _UWORD WORD[2]; /* Word Access */
+ _UBYTE BYTE[4]; /* Byte Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFO; /* */
+ union { /* CFIFOSEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CURPIPE:4; /* CURPIPE */
+ _UWORD :1; /* */
+ _UWORD ISEL:1; /* ISEL */
+ _UWORD :2; /* */
+ _UWORD BIGEND:1; /* BIGEND */
+ _UWORD :1; /* */
+ _UWORD MBW:2; /* MBW */
+ _UWORD :2; /* */
+ _UWORD REW:1; /* REW */
+ _UWORD RCNT:1; /* RCNT */
+ } BIT; /* */
+ } CFIFOSEL; /* */
+ union { /* CFIFOCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DTLN:12; /* DTLN */
+ _UWORD :1; /* */
+ _UWORD FRDY:1; /* FRDY */
+ _UWORD BCLR:1; /* BCLR */
+ _UWORD BVAL:1; /* BVAL */
+ } BIT; /* */
+ } CFIFOCTR; /* */
+ _UBYTE wk3[4]; /* */
+ union { /* D0FIFOSEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CURPIPE:4; /* CURPIPE */
+ _UWORD :4; /* */
+ _UWORD BIGEND:1; /* BIGEND */
+ _UWORD :1; /* */
+ _UWORD MBW:2; /* MBW */
+ _UWORD DREQE:1; /* DREQE */
+ _UWORD DCLRM:1; /* DCLRM */
+ _UWORD REW:1; /* REW */
+ _UWORD RCNT:1; /* RCNT */
+ } BIT; /* */
+ } D0FIFOSEL; /* */
+ union { /* D0FIFOCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DTLN:12; /* DTLN */
+ _UWORD :1; /* */
+ _UWORD FRDY:1; /* FRDY */
+ _UWORD BCLR:1; /* BCLR */
+ _UWORD BVAL:1; /* BVAL */
+ } BIT; /* */
+ } D0FIFOCTR; /* */
+ union { /* D1FIFOSEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CURPIPE:4; /* CURPIPE */
+ _UWORD :4; /* */
+ _UWORD BIGEND:1; /* BIGEND */
+ _UWORD :1; /* */
+ _UWORD MBW:2; /* MBW */
+ _UWORD DREQE:1; /* DREQE */
+ _UWORD DCLRM:1; /* DCLRM */
+ _UWORD REW:1; /* REW */
+ _UWORD RCNT:1; /* RCNT */
+ } BIT; /* */
+ } D1FIFOSEL; /* */
+ union { /* D1FIFOCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD DTLN:12; /* DTLN */
+ _UWORD :1; /* */
+ _UWORD FRDY:1; /* FRDY */
+ _UWORD BCLR:1; /* BCLR */
+ _UWORD BVAL:1; /* BVAL */
+ } BIT; /* */
+ } D1FIFOCTR; /* */
+ union { /* INTENB0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD BRDYE:1; /* BRDYE */
+ _UWORD NRDYE:1; /* NRDYE */
+ _UWORD BEMPE:1; /* BEMPE */
+ _UWORD CTRE:1; /* CTRE */
+ _UWORD DVSE:1; /* DVSE */
+ _UWORD SOFE:1; /* SOFE */
+ _UWORD RSME:1; /* RSME */
+ _UWORD VBSE:1; /* VBSE */
+ } BIT; /* */
+ } INTENB0; /* */
+ union { /* INTENB1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD SACKE:1; /* SACKE */
+ _UWORD SIGNE:1; /* SIGNE */
+ _UWORD EOFERRE:1; /* EOFERRE */
+ _UWORD :4; /* */
+ _UWORD ATTCHE:1; /* ATTCHE */
+ _UWORD DTCHE:1; /* DTCHE */
+ _UWORD :1; /* */
+ _UWORD BCHGE:1; /* BCHGE */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } INTENB1; /* */
+ _UBYTE wk4[2]; /* */
+ union { /* BRDYENB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPE0BRDYE:1; /* PIPE0BRDYE */
+ _UWORD PIPE1BRDYE:1; /* PIPE1BRDYE */
+ _UWORD PIPE2BRDYE:1; /* PIPE2BRDYE */
+ _UWORD PIPE3BRDYE:1; /* PIPE3BRDYE */
+ _UWORD PIPE4BRDYE:1; /* PIPE4BRDYE */
+ _UWORD PIPE5BRDYE:1; /* PIPE5BRDYE */
+ _UWORD PIPE6BRDYE:1; /* PIPE6BRDYE */
+ _UWORD PIPE7BRDYE:1; /* PIPE7BRDYE */
+ _UWORD PIPE8BRDYE:1; /* PIPE8BRDYE */
+ _UWORD PIPE9BRDYE:1; /* PIPE9BRDYE */
+ _UWORD PIPEABRDYE:1; /* PIPEABRDYE */
+ _UWORD PIPEBBRDYE:1; /* PIPEBBRDYE */
+ _UWORD PIPECBRDYE:1; /* PIPECBRDYE */
+ _UWORD PIPEDBRDYE:1; /* PIPEDBRDYE */
+ _UWORD PIPEEBRDYE:1; /* PIPEEBRDYE */
+ _UWORD PIPEFBRDYE:1; /* PIPEFBRDYE */
+ } BIT; /* */
+ } BRDYENB; /* */
+ union { /* NRDYENB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPE0NRDYE:1; /* PIPE0NRDYE */
+ _UWORD PIPE1NRDYE:1; /* PIPE1NRDYE */
+ _UWORD PIPE2NRDYE:1; /* PIPE2NRDYE */
+ _UWORD PIPE3NRDYE:1; /* PIPE3NRDYE */
+ _UWORD PIPE4NRDYE:1; /* PIPE4NRDYE */
+ _UWORD PIPE5NRDYE:1; /* PIPE5NRDYE */
+ _UWORD PIPE6NRDYE:1; /* PIPE6NRDYE */
+ _UWORD PIPE7NRDYE:1; /* PIPE7NRDYE */
+ _UWORD PIPE8NRDYE:1; /* PIPE8NRDYE */
+ _UWORD PIPE9NRDYE:1; /* PIPE9NRDYE */
+ _UWORD PIPEANRDYE:1; /* PIPEANRDYE */
+ _UWORD PIPEBNRDYE:1; /* PIPEBNRDYE */
+ _UWORD PIPECNRDYE:1; /* PIPECNRDYE */
+ _UWORD PIPEDNRDYE:1; /* PIPEDNRDYE */
+ _UWORD PIPEENRDYE:1; /* PIPEENRDYE */
+ _UWORD PIPEFNRDYE:1; /* PIPEFNRDYE */
+ } BIT; /* */
+ } NRDYENB; /* */
+ union { /* BEMPENB */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPE0BEMPE:1; /* PIPE0BEMPE */
+ _UWORD PIPE1BEMPE:1; /* PIPE1BEMPE */
+ _UWORD PIPE2BEMPE:1; /* PIPE2BEMPE */
+ _UWORD PIPE3BEMPE:1; /* PIPE3BEMPE */
+ _UWORD PIPE4BEMPE:1; /* PIPE4BEMPE */
+ _UWORD PIPE5BEMPE:1; /* PIPE5BEMPE */
+ _UWORD PIPE6BEMPE:1; /* PIPE6BEMPE */
+ _UWORD PIPE7BEMPE:1; /* PIPE7BEMPE */
+ _UWORD PIPE8BEMPE:1; /* PIPE8BEMPE */
+ _UWORD PIPE9BEMPE:1; /* PIPE9BEMPE */
+ _UWORD PIPEABEMPE:1; /* PIPEABEMPE */
+ _UWORD PIPEBBEMPE:1; /* PIPEBBEMPE */
+ _UWORD PIPECBEMPE:1; /* PIPECBEMPE */
+ _UWORD PIPEDBEMPE:1; /* PIPEDBEMPE */
+ _UWORD PIPEEBEMPE:1; /* PIPEEBEMPE */
+ _UWORD PIPEFBEMPE:1; /* PIPEFBEMPE */
+ } BIT; /* */
+ } BEMPENB; /* */
+ union { /* SOFCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD BRDYM:1; /* BRDYM */
+ _UWORD :1; /* */
+ _UWORD TRNENSEL:1; /* TRNENSEL */
+ _UWORD :7; /* */
+ } BIT; /* */
+ } SOFCFG; /* */
+ _UBYTE wk5[2]; /* */
+ union { /* INTSTS0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD CTSQ:3; /* CTSQ */
+ _UWORD VALID:1; /* VALID */
+ _UWORD DVSQ:3; /* DVSQ */
+ _UWORD VBSTS:1; /* VBSTS */
+ _UWORD BRDY:1; /* BRDY */
+ _UWORD NRDY:1; /* NRDY */
+ _UWORD BEMP:1; /* BEMP */
+ _UWORD CTRT:1; /* CTRT */
+ _UWORD DVST:1; /* DVST */
+ _UWORD SOFR:1; /* SOFR */
+ _UWORD RESM:1; /* RESM */
+ _UWORD VBINT:1; /* VBINT */
+ } BIT; /* */
+ } INTSTS0; /* */
+ union { /* INTSTS1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD SACK:1; /* SACK */
+ _UWORD SIGN:1; /* SIGN */
+ _UWORD EOFERR:1; /* EOFERR */
+ _UWORD :4; /* */
+ _UWORD ATTCH:1; /* ATTCH */
+ _UWORD DTCH:1; /* DTCH */
+ _UWORD :1; /* */
+ _UWORD BCHG:1; /* BCHG */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } INTSTS1; /* */
+ _UBYTE wk6[2]; /* */
+ union { /* BRDYSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPE0BRDY:1; /* PIPE0BRDY */
+ _UWORD PIPE1BRDY:1; /* PIPE1BRDY */
+ _UWORD PIPE2BRDY:1; /* PIPE2BRDY */
+ _UWORD PIPE3BRDY:1; /* PIPE3BRDY */
+ _UWORD PIPE4BRDY:1; /* PIPE4BRDY */
+ _UWORD PIPE5BRDY:1; /* PIPE5BRDY */
+ _UWORD PIPE6BRDY:1; /* PIPE6BRDY */
+ _UWORD PIPE7BRDY:1; /* PIPE7BRDY */
+ _UWORD PIPE8BRDY:1; /* PIPE8BRDY */
+ _UWORD PIPE9BRDY:1; /* PIPE9BRDY */
+ _UWORD PIPEABRDY:1; /* PIPEABRDY */
+ _UWORD PIPEBBRDY:1; /* PIPEBBRDY */
+ _UWORD PIPECBRDY:1; /* PIPECBRDY */
+ _UWORD PIPEDBRDY:1; /* PIPEDBRDY */
+ _UWORD PIPEEBRDY:1; /* PIPEEBRDY */
+ _UWORD PIPEFBRDY:1; /* PIPEFBRDY */
+ } BIT; /* */
+ } BRDYSTS; /* */
+ union { /* NRDYSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPE0NRDY:1; /* PIPE0NRDY */
+ _UWORD PIPE1NRDY:1; /* PIPE1NRDY */
+ _UWORD PIPE2NRDY:1; /* PIPE2NRDY */
+ _UWORD PIPE3NRDY:1; /* PIPE3NRDY */
+ _UWORD PIPE4NRDY:1; /* PIPE4NRDY */
+ _UWORD PIPE5NRDY:1; /* PIPE5NRDY */
+ _UWORD PIPE6NRDY:1; /* PIPE6NRDY */
+ _UWORD PIPE7NRDY:1; /* PIPE7NRDY */
+ _UWORD PIPE8NRDY:1; /* PIPE8NRDY */
+ _UWORD PIPE9NRDY:1; /* PIPE9NRDY */
+ _UWORD PIPEANRDY:1; /* PIPEANRDY */
+ _UWORD PIPEBNRDY:1; /* PIPEBNRDY */
+ _UWORD PIPECNRDY:1; /* PIPECNRDY */
+ _UWORD PIPEDNRDY:1; /* PIPEDNRDY */
+ _UWORD PIPEENRDY:1; /* PIPEENRDY */
+ _UWORD PIPEFNRDY:1; /* PIPEFNRDY */
+ } BIT; /* */
+ } NRDYSTS; /* */
+ union { /* BEMPSTS */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPE0BEMP:1; /* PIPE0BEMP */
+ _UWORD PIPE1BEMP:1; /* PIPE1BEMP */
+ _UWORD PIPE2BEMP:1; /* PIPE2BEMP */
+ _UWORD PIPE3BEMP:1; /* PIPE3BEMP */
+ _UWORD PIPE4BEMP:1; /* PIPE4BEMP */
+ _UWORD PIPE5BEMP:1; /* PIPE5BEMP */
+ _UWORD PIPE6BEMP:1; /* PIPE6BEMP */
+ _UWORD PIPE7BEMP:1; /* PIPE7BEMP */
+ _UWORD PIPE8BEMP:1; /* PIPE8BEMP */
+ _UWORD PIPE9BEMP:1; /* PIPE9BEMP */
+ _UWORD PIPEABEMP:1; /* PIPEABEMP */
+ _UWORD PIPEBBEMP:1; /* PIPEBBEMP */
+ _UWORD PIPECBEMP:1; /* PIPECBEMP */
+ _UWORD PIPEDBEMP:1; /* PIPEDBEMP */
+ _UWORD PIPEEBEMP:1; /* PIPEEBEMP */
+ _UWORD PIPEFBEMP:1; /* PIPEFBEMP */
+ } BIT; /* */
+ } BEMPSTS; /* */
+ union { /* FRMNUM */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD FRNM:11; /* FRNM */
+ _UWORD :3; /* */
+ _UWORD CRCE:1; /* CRCE */
+ _UWORD OVRN:1; /* OVRN */
+ } BIT; /* */
+ } FRMNUM; /* */
+ union { /* UFRMNUM */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD UFRNM:3; /* UFRNM */
+ _UWORD :13; /* */
+ } BIT; /* */
+ } UFRMNUM; /* */
+ union { /* USBADDR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD USBADDR:7; /* USBADDR */
+ _UWORD :9; /* */
+ } BIT; /* */
+ } USBADDR; /* */
+ _UBYTE wk7[2]; /* */
+ union { /* USBREQ */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BMREQUESTTYPE:8; /* BMREQUESTTYPE */
+ _UWORD BREQUEST:8; /* BREQUEST */
+ } BIT; /* */
+ } USBREQ; /* */
+ _UWORD USBVAL; /* USBVAL */
+ _UWORD USBINDX; /* USBINDX */
+ _UWORD USBLENG; /* USBLENG */
+ union { /* DCPCFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :4; /* */
+ _UWORD DIR:1; /* DIR */
+ _UWORD :11; /* */
+ } BIT; /* */
+ } DCPCFG; /* */
+ union { /* DCPMAXP */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MXPS:7; /* MXPS */
+ _UWORD :5; /* */
+ _UWORD DEVSEL:4; /* DEVSEL */
+ } BIT; /* */
+ } DCPMAXP; /* */
+ union { /* DCPCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD CCPL:1; /* CCPL */
+ _UWORD :1; /* */
+ _UWORD PINGE:1; /* PINGE */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD :2; /* */
+ _UWORD SUREQCLR:1; /* SUREQCLR */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD SUREQ:1; /* SUREQ */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } DCPCTR; /* */
+ _UBYTE wk8[2]; /* */
+ union { /* PIPESEL */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PIPESEL:4; /* PIPESEL */
+ _UWORD :12; /* */
+ } BIT; /* */
+ } PIPESEL; /* */
+ _UBYTE wk9[2]; /* */
+ union { /* PIPECFG */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD EPNUM:4; /* EPNUM */
+ _UWORD DIR:1; /* DIR */
+ _UWORD :2; /* */
+ _UWORD SHTNAK:1; /* SHTNAK */
+ _UWORD CNTMD:1; /* CNTMD */
+ _UWORD DBLB:1; /* DBLB */
+ _UWORD BFRE:1; /* BFRE */
+ _UWORD :3; /* */
+ _UWORD TYPE:2; /* TYPE */
+ } BIT; /* */
+ } PIPECFG; /* */
+ union { /* PIPEBUF */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD BUFNMB:8; /* BUFNMB */
+ _UWORD :2; /* */
+ _UWORD BUFSIZE:5; /* BUFSIZE */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } PIPEBUF; /* */
+ union { /* PIPEMAXP */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD MXPS:11; /* MXPS */
+ _UWORD :1; /* */
+ _UWORD DEVSEL:4; /* DEVSEL */
+ } BIT; /* */
+ } PIPEMAXP; /* */
+ union { /* PIPEPERI */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD IITV:3; /* IITV */
+ _UWORD :9; /* */
+ _UWORD IFIS:1; /* IFIS */
+ _UWORD :3; /* */
+ } BIT; /* */
+ } PIPEPERI; /* */
+ union { /* PIPE1CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :1; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE1CTR; /* */
+ union { /* PIPE2CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :1; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE2CTR; /* */
+ union { /* PIPE3CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :1; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE3CTR; /* */
+ union { /* PIPE4CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :1; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE4CTR; /* */
+ union { /* PIPE5CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :1; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE5CTR; /* */
+ union { /* PIPE6CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD :2; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD :1; /* */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE6CTR; /* */
+ union { /* PIPE7CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD :2; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD :1; /* */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE7CTR; /* */
+ union { /* PIPE8CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD :2; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD :1; /* */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE8CTR; /* */
+ union { /* PIPE9CTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :1; /* */
+ _UWORD CSSTS:1; /* CSSTS */
+ _UWORD CSCLR:1; /* CSCLR */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPE9CTR; /* */
+ union { /* PIPEACTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :3; /* */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPEACTR; /* */
+ union { /* PIPEBCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :3; /* */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPEBCTR; /* */
+ union { /* PIPECCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :3; /* */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPECCTR; /* */
+ union { /* PIPEDCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :3; /* */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPEDCTR; /* */
+ union { /* PIPEECTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :3; /* */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPEECTR; /* */
+ union { /* PIPEFCTR */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD PID:2; /* PID */
+ _UWORD :3; /* */
+ _UWORD PBUSY:1; /* PBUSY */
+ _UWORD SQMON:1; /* SQMON */
+ _UWORD SQSET:1; /* SQSET */
+ _UWORD SQCLR:1; /* SQCLR */
+ _UWORD ACLRM:1; /* ACLRM */
+ _UWORD ATREPM:1; /* ATREPM */
+ _UWORD :3; /* */
+ _UWORD INBUFM:1; /* INBUFM */
+ _UWORD BSTS:1; /* BSTS */
+ } BIT; /* */
+ } PIPEFCTR; /* */
+ _UBYTE wk10[2]; /* */
+ union { /* PIPE1TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPE1TRE; /* */
+ _UWORD PIPE1TRN; /* PIPE1TRN */
+ union { /* PIPE2TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPE2TRE; /* */
+ _UWORD PIPE2TRN; /* PIPE2TRN */
+ union { /* PIPE3TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPE3TRE; /* */
+ _UWORD PIPE3TRN; /* PIPE3TRN */
+ union { /* PIPE4TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPE4TRE; /* */
+ _UWORD PIPE4TRN; /* PIPE4TRN */
+ union { /* PIPE5TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPE5TRE; /* */
+ _UWORD PIPE5TRN; /* PIPE5TRN */
+ union { /* PIPEBTRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPEBTRE; /* */
+ _UWORD PIPEBTRN; /* PIPEBTRN */
+ union { /* PIPECTRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPECTRE; /* */
+ _UWORD PIPECTRN; /* PIPECTRN */
+ union { /* PIPEDTRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPEDTRE; /* */
+ _UWORD PIPEDTRN; /* PIPEDTRN */
+ union { /* PIPEETRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPEETRE; /* */
+ _UWORD PIPEETRN; /* PIPEETRN */
+ union { /* PIPEFTRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPEFTRE; /* */
+ _UWORD PIPEFTRN; /* PIPEFTRN */
+ union { /* PIPE9TRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPE9TRE; /* */
+ _UWORD PIPE9TRN; /* PIPE9TRN */
+ union { /* PIPEATRE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :8; /* */
+ _UWORD TRCLR:1; /* TRCLR */
+ _UWORD TRENB:1; /* TRENB */
+ _UWORD :6; /* */
+ } BIT; /* */
+ } PIPEATRE; /* */
+ _UWORD PIPEATRN; /* PIPEATRN */
+ _UBYTE wk11[16]; /* */
+ union { /* DEVADD0 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD0; /* */
+ union { /* DEVADD1 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD1; /* */
+ union { /* DEVADD2 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD2; /* */
+ union { /* DEVADD3 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD3; /* */
+ union { /* DEVADD4 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD4; /* */
+ union { /* DEVADD5 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD5; /* */
+ union { /* DEVADD6 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD6; /* */
+ union { /* DEVADD7 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD7; /* */
+ union { /* DEVADD8 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD8; /* */
+ union { /* DEVADD9 */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADD9; /* */
+ union { /* DEVADDA */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :6; /* */
+ _UWORD USBSPD:2; /* USBSPD */
+ _UWORD HUBPORT:3; /* HUBPORT */
+ _UWORD UPPHUB:4; /* UPPHUB */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } DEVADDA; /* */
+ _UBYTE wk12[28]; /* */
+ union { /* SUSPMODE */
+ _UWORD WORD; /* Word Access */
+ struct { /* Bit Access */
+ _UWORD :14; /* */
+ _UWORD SUSPM:1; /* SUSPM */
+ _UWORD :1; /* */
+ } BIT; /* */
+ } SUSPMODE; /* */
+ _UBYTE wk13[92]; /* */
+ union { /* D0FIFOB0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB0; /* */
+ union { /* D0FIFOB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB1; /* */
+ union { /* D0FIFOB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB2; /* */
+ union { /* D0FIFOB3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB3; /* */
+ union { /* D0FIFOB4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB4; /* */
+ union { /* D0FIFOB5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB5; /* */
+ union { /* D0FIFOB6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB6; /* */
+ union { /* D0FIFOB7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D0FIFOB7; /* */
+ union { /* D1FIFOB0 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB0; /* */
+ union { /* D1FIFOB1 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB1; /* */
+ union { /* D1FIFOB2 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB2; /* */
+ union { /* D1FIFOB3 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB3; /* */
+ union { /* D1FIFOB4 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB4; /* */
+ union { /* D1FIFOB5 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB5; /* */
+ union { /* D1FIFOB6 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB6; /* */
+ union { /* D1FIFOB7 */
+ _UDWORD LONG; /* Long Access */
+ struct { /* Bit Access */
+ _UDWORD FIFOPORT:32; /* FIFOPORT */
+ } BIT; /* */
+ } D1FIFOB7; /* */
+}; /* */
+
+#define USB0 (*(volatile struct st_usb_n *)0xE8010000) /* USB0 Address */
+#define USB1 (*(volatile struct st_usb_n *)0xE8207000) /* USB1 Address */
+
+
+#endif /* __USB_IODEFINE_H__ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/main.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/main.h
new file mode 100644
index 000000000..c9b0a5b81
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/main.h
@@ -0,0 +1,57 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : main.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - Main
+******************************************************************************/
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+int_t main(void);
+void Sample_OSTM0_Interrupt(void);
+
+#endif /* _MAIN_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/port_init.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/port_init.h
new file mode 100644
index 000000000..6b8e3debe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/port_init.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : port_init.h
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - SCIF UART sample program
+******************************************************************************/
+#ifndef _PORT_INIT_H_
+#define _PORT_INIT_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void PORT_Init(void);
+
+
+#endif /* _PORT_INIT_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/r_typedefs.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/r_typedefs.h
new file mode 100644
index 000000000..68d659178
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/r_typedefs.h
@@ -0,0 +1,64 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : r_typedefs.h
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : basic type definition
+******************************************************************************/
+#ifndef R_TYPEDEFS_H
+#define R_TYPEDEFS_H
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+#include
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus)
+#define false 0
+#define true 1
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef char char_t;
+typedef unsigned int bool_t;
+typedef int int_t;
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed long int32_t;
+typedef signed long long int64_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned long uint32_t;
+typedef unsigned long long uint64_t;
+typedef float float32_t;
+typedef double float64_t;
+typedef long double float128_t;
+
+#endif /* R_TYPEDEFS_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/resetprg.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/resetprg.h
new file mode 100644
index 000000000..9ad0a92d6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/resetprg.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : resetprg.h
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - Program after reset
+******************************************************************************/
+#ifndef _RESETPRG_H_
+#define _RESETPRG_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void io_init_cache(void);
+int32_t io_cache_writeback(void);
+
+#endif /* _RESETPRG_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sample_main.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sample_main.h
new file mode 100644
index 000000000..f643b52c7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sample_main.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : sample_main.h
+* $Rev: $
+* $Date:: $
+* Description : Aragon Sample Program - RIIC sample program
+******************************************************************************/
+#ifndef _SAMPLE_MAIN_H_
+#define _SAMPLE_MAIN_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void Sample_Main(void);
+
+
+#endif /* _SAMPLE_MAIN_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sio_char.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sio_char.h
new file mode 100644
index 000000000..053cc3bb5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/sio_char.h
@@ -0,0 +1,65 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : sio_char.h
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - Terminal I/O
+******************************************************************************/
+#ifndef _SIO_CHAR_H_
+#define _SIO_CHAR_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+int32_t SioWrite(int32_t file_no, const char_t * buffer, uint32_t writing_b);
+int32_t SioRead(int32_t file_no, char_t * buffer, uint32_t reading_b);
+
+void IoInitScif2(void);
+char_t IoGetchar(void);
+void IoPutchar(char_t buffer);
+
+#endif /* _SIO_CHAR_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/stb_init.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/stb_init.h
new file mode 100644
index 000000000..b68fa9d07
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/stb_init.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name : stb_init.h
+* $Rev: 17531 $
+* $Date:: 2013-04-10 12:58:44 +0100#$
+* Description : Aragon Sample Program - SCIF UART sample program
+******************************************************************************/
+#ifndef _STB_INIT_H_
+#define _STB_INIT_H_
+
+/******************************************************************************
+Includes , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void STB_Init(void);
+
+
+#endif /* _STB_INIT_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/typedefine.h b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/typedefine.h
new file mode 100644
index 000000000..e67923621
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/typedefine.h
@@ -0,0 +1,52 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : typedefine.h
+* Version : 1.00
+* Description : Defines exact width integer types.
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 24.05.2012 1.00 First Release
+*******************************************************************************/
+#ifndef _TYPE_DEFINE_H_
+#define _TYPE_DEFINE_H_
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef signed char _SBYTE;
+typedef unsigned char _UBYTE;
+typedef signed short _SWORD;
+typedef unsigned short _UWORD;
+typedef signed int _SINT;
+typedef unsigned int _UINT;
+typedef signed long _SDWORD;
+typedef unsigned long _UDWORD;
+typedef signed long long _SQWORD;
+typedef unsigned long long _UQWORD;
+
+#endif /* _TYPE_DEFINE_H_ */
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/vector/vector_mirrortable.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/vector/vector_mirrortable.s
new file mode 100644
index 000000000..8b51a557d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/vector/vector_mirrortable.s
@@ -0,0 +1,75 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : vector_mirrortable.s
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.13
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program - Vector mirrortable
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+;==================================================================
+; Entry point for the Reset handler
+;==================================================================
+ PRESERVE8
+ AREA VECTOR_MIRROR_TABLE, CODE, READONLY
+
+; EXPORT vector_table
+
+ IMPORT reset_handler
+ IMPORT undefined_handler
+ IMPORT prefetch_handler
+ IMPORT abort_handler
+ IMPORT reserved_handler
+ IMPORT FreeRTOS_IRQ_Handler
+ IMPORT fiq_handler
+ IMPORT FreeRTOS_SWI_Handler
+
+; ENTRY
+
+; EXPORT Start
+
+;Start
+
+vector_table2
+ LDR pc, =reset_handler ; 0x0000_0000
+ LDR pc, =undefined_handler ; 0x0000_0004
+ LDR pc, =FreeRTOS_SWI_Handler ; 0x0000_0008
+ LDR pc, =prefetch_handler ; 0x0000_000c
+ LDR pc, =abort_handler ; 0x0000_0010
+ LDR pc, =reserved_handler ; 0x0000_0014
+ LDR pc, =FreeRTOS_IRQ_Handler ; 0x0000_0018
+ LDR pc, =fiq_handler ; 0x0000_001c
+
+Literals
+ LTORG
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/vector/vector_table.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/vector/vector_table.s
new file mode 100644
index 000000000..55ad44a3f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/vector/vector_table.s
@@ -0,0 +1,75 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : vector_table.s
+;* Version : 0.01
+;* Device(s) : Aragon - RZ/A1H
+;* Tool-Chain : DS-5 Ver 5.13
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program - Vector table
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+;==================================================================
+; Entry point for the Reset handler
+;==================================================================
+ PRESERVE8
+ AREA VECTOR_TABLE, CODE, READONLY
+
+ EXPORT vector_table
+
+ IMPORT reset_handler
+ IMPORT undefined_handler
+ IMPORT FreeRTOS_SWI_Handler
+ IMPORT prefetch_handler
+ IMPORT abort_handler
+ IMPORT reserved_handler
+ IMPORT FreeRTOS_IRQ_Handler
+ IMPORT fiq_handler
+
+ ENTRY
+
+ EXPORT Start
+
+Start
+
+vector_table
+ LDR pc, =reset_handler ; 0x0000_0000
+ LDR pc, =undefined_handler ; 0x0000_0004
+ LDR pc, =FreeRTOS_SWI_Handler ; 0x0000_0008
+ LDR pc, =prefetch_handler ; 0x0000_000c
+ LDR pc, =abort_handler ; 0x0000_0010
+ LDR pc, =reserved_handler ; 0x0000_0014
+ LDR pc, =FreeRTOS_IRQ_Handler ; 0x0000_0018
+ LDR pc, =fiq_handler ; 0x0000_001c
+
+Literals
+ LTORG
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/main.c b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/main.c
new file mode 100644
index 000000000..e69ebc2c0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/main.c
@@ -0,0 +1,275 @@
+/*
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ * This project provides two demo applications. A simple blinky style project,
+ * and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two. The simply blinky demo is implemented and described
+ * in main_blinky.c. The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.
+ *
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
+ *
+ */
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Standard demo includes. */
+#include "partest.h"
+#include "TimerDemo.h"
+
+/* Renesas includes. */
+#include "r_typedefs.h"
+#include "sio_char.h"
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Configure the hardware as necessary to run this demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+ extern void main_blinky( void );
+#else
+ extern void main_full( void );
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file. */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+extern void vCreateAndVerifySampleFiles( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+ /* Configure the hardware ready to run the demo. */
+ prvSetupHardware();
+
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+ of this file. */
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+ {
+ main_blinky();
+ }
+ #else
+ {
+ main_full();
+ }
+ #endif
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+ /* Initialise the pins used by the LEDs (the obscure [now for historical
+ reasons] name ParTest stands for Parallel Port test). */
+ vParTestInitialise();
+
+ /* Call the Renesas driver that initialises the serial port. P1=66.67MHz
+ CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps. */
+ IoInitScif2();
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* Called if a call to pvPortMalloc() fails because there is insufficient
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called
+ internally by FreeRTOS API functions that create tasks, queues, software
+ timers, and semaphores. The size of the FreeRTOS heap is set by the
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+volatile size_t xFreeHeapSpace;
+
+ /* This is just a trivial example of an idle hook. It is called on each
+ cycle of the idle task. It must *NOT* attempt to block. In this case the
+ idle task just queries the amount of FreeRTOS heap that remains. See the
+ memory management section on the http://www.FreeRTOS.org web site for memory
+ management options. If there is a lot of heap memory free then the
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
+ RAM. */
+ xFreeHeapSpace = xPortGetFreeHeapSize();
+
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */
+ ( void ) xFreeHeapSpace;
+
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1
+ {
+ /* If the file system is only going to be accessed from one task then
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files is
+ created before the RTOS scheduler is started. If the file system is
+ going to be access from more than one task then F_FS_THREAD_AWARE must
+ be set to 1 and the set of sample files are created from the idle task
+ hook function. */
+ #if F_FS_THREAD_AWARE == 1
+ {
+ static portBASE_TYPE xCreatedSampleFiles = pdFALSE;
+
+ /* Initialise the drive and file system, then create a few example
+ files. The output from this function just goes to the stdout window,
+ allowing the output to be viewed when the UDP command console is not
+ connected. */
+ if( xCreatedSampleFiles == pdFALSE )
+ {
+ vCreateAndVerifySampleFiles();
+ xCreatedSampleFiles = pdTRUE;
+ }
+ }
+ #endif
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( const char * pcFile, unsigned long ulLine )
+{
+volatile unsigned long ul = 0;
+
+ ( void ) pcFile;
+ ( void ) ulLine;
+
+ taskENTER_CRITICAL();
+ {
+ /* Set ul to a non-zero value using the debugger to step out of this
+ function. */
+ while( ul == 0 )
+ {
+ portNOP();
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
+ {
+ /* The full demo includes a software timer demo/test that requires
+ prodding periodically from the tick interrupt. */
+ vTimerPeriodicISRTests();
+ }
+ #endif
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/scatter.scat b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/scatter.scat
new file mode 100644
index 000000000..8ab90435c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/scatter.scat
@@ -0,0 +1,82 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;*
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* File Name : scatter.scat
+;* Version : 0.01
+;* Device(s) : Aragon
+;* Tool-Chain : DS-5 Ver 5.8
+;* ARM Complier
+;* :
+;* H/W Platform : Aragon CPU Board
+;* Description : Aragon Sample Program scatter file
+;*******************************************************************************/
+;/*******************************************************************************
+;* History : DD.MM.YYYY Version Description
+;* : 23.05.2012 0.01
+;*******************************************************************************/
+
+LOAD_MODULE3 0x20020000 0x209FFFFF ;; Internal RAM Area (0x20020000-0x2003FFFF)
+{
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; use as RAM Area ;;
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ VECTOR_MIRROR_TABLE 0x20020000 ;; Internal RAM Area (0x20020000-0x200200FF)
+ { * (VECTOR_MIRROR_TABLE) } ;; Vector table
+
+ CODE +0 FIXED
+ { * (+RO-CODE) }
+
+ CONST +0 FIXED
+ { * (+RO-DATA) }
+
+ DATA +0
+ { * (+RW) }
+
+ BSS +0
+ { * (+ZI) }
+
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; use as RAM Area(2) ;;
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ARM_LIB_HEAP 0x20080000 EMPTY 0x00008000 ; Application heap
+ { }
+
+ ARM_LIB_STACK 0x20090000 EMPTY -0x00008000 ; Application stack
+ { }
+
+ IRQ_STACK 0x20092000 EMPTY -0x00002000 ; IRQ mode stack
+ { }
+
+ FIQ_STACK 0x20094000 EMPTY -0x00002000 ; FRQ mode stack
+ { }
+
+ SVC_STACK 0x20096000 EMPTY -0x00002000 ; SVC mode stack
+ { }
+
+ ABT_STACK 0x20098000 EMPTY -0x00002000 ; ABT mode stack
+ { }
+
+ TTB (0x20098000 AND 0xFFFFC000) EMPTY 0x00008000 ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds
new file mode 100644
index 000000000..0f142a813
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds
@@ -0,0 +1,54 @@
+stop
+pause 500
+reset
+stop
+#reset
+
+info memory
+memory S:0x00000000 S:0x07ffffff ro
+memory S:0x3fffff80 S:0x3fffffff nocache noverify
+memory S:0xfcfe0000 S:0xfcfeffff nocache noverify
+
+# USB Register accessed by only 16bit
+memory S:0xe8010000 S:0xe801010f 16
+memory S:0xe8207000 S:0xe820710f 16
+info memory
+
+######################################
+# Release L2 cache standby ##
+######################################
+mem set 0x3fffff80 32 0x00000001
+
+# ;*Writing to On-Chip Data-Retention RAM is enabled.
+# ;SYSCR3.RRAMWE3=RRAMWE2=RRAMWE1=RRAMWE0=1
+mem set 0xfcfe0408 32 0xf
+
+######################################
+# CS0 Port Setting ##
+# CS1 Port Setting ##
+######################################
+# P9_1(A25), P9_0(A24),
+mem set 0xfcfe3424 16 0x0003 # PMC9
+mem set 0xfcfe3A24 16 0x0000 # PFCAE9
+mem set 0xfcfe3624 16 0x0000 # PFCE9
+mem set 0xfcfe3524 16 0x0000 # PFC9
+mem set 0xfcfe7224 16 0x0003 # PIPC9
+# P8_15(A23), P8_14(A22), P8_13(A21),
+mem set 0xfcfe3420 16 0xffff # PMC8
+mem set 0xfcfe3A20 16 0x0000 # PFCAE8
+mem set 0xfcfe3620 16 0x0000 # PFCE8
+mem set 0xfcfe3520 16 0x0000 # PFC8
+mem set 0xfcfe7220 16 0xffff # PIPC8
+# P7_6(WE0#), P7_8(RD#), P7_0(CS0#),
+mem set 0xfcfe341c 16 0xff41 # PMC7
+mem set 0xfcfe3A1c 16 0x0000 # PFCAE7
+mem set 0xfcfe361c 16 0x0000 # PFCE7
+mem set 0xfcfe351c 16 0x0000 # PFC7
+mem set 0xfcfe721c 16 0xff41 # PIPC7
+# P3_7(CS1#),
+mem set 0xfcfe340c 16 0x0080 # PMC3
+mem set 0xfcfe3A0c 16 0x0080 # PFCAE3
+mem set 0xfcfe360c 16 0x0080 # PFCE3
+mem set 0xfcfe350c 16 0x0000 # PFC3
+mem set 0xfcfe720c 16 0x0080 # PIPC3
+