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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS port header for AVR32 UC3.
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*
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* - Compiler: IAR EWAVR32
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* - Supported devices: All AVR32 devices can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/*
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FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS eBook *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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#include <avr32/io.h>
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#include "intc.h"
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#include "compiler.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE unsigned portLONG
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#define portBASE_TYPE portLONG
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#define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
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#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
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#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
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#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef unsigned portSHORT portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffff
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#else
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typedef unsigned portLONG portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffffffff
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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|
#define portSTACK_GROWTH ( -1 )
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|
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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|
#define portBYTE_ALIGNMENT 4
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|
#define portNOP() {__asm__ __volatile__ ("nop");}
|
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|
|
/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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|
|
/* INTC-specific. */
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|
#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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|
#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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|
#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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|
|
#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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|
|
#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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|
#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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|
|
/*
|
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|
|
* Debug trace.
|
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|
|
* Activated if and only if configDBG is nonzero.
|
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|
|
* Prints a formatted string to stdout.
|
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|
|
* The current source file name and line number are output with a colon before
|
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|
|
* the formatted string.
|
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|
|
* A carriage return and a linefeed are appended to the output.
|
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|
|
* stdout is redirected to the USART configured by configDBG_USART.
|
|
|
|
|
* The parameters are the same as for the standard printf function.
|
|
|
|
|
* There is no return value.
|
|
|
|
|
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
|
|
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|
|
* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
|
|
|
|
|
*/
|
|
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|
|
#if configDBG
|
|
|
|
|
#define portDBG_TRACE(...) \
|
|
|
|
|
{ \
|
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|
|
fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
|
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|
|
printf(__VA_ARGS__); \
|
|
|
|
|
fputs("\r\n", stdout); \
|
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|
|
}
|
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|
|
#else
|
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|
|
|
#define portDBG_TRACE(...)
|
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|
|
#endif
|
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|
|
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|
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|
|
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|
|
|
/* Critical section management. */
|
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|
|
|
#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
|
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|
|
#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
|
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|
|
extern void vPortEnterCritical( void );
|
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|
|
extern void vPortExitCritical( void );
|
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|
|
#define portENTER_CRITICAL() vPortEnterCritical();
|
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|
|
#define portEXIT_CRITICAL() vPortExitCritical();
|
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|
|
|
|
|
|
|
|
|
|
/* Added as there is no such function in FreeRTOS. */
|
|
|
|
|
extern void *pvPortRealloc( void *pv, size_t xSize );
|
|
|
|
|
/*-----------------------------------------------------------*/
|
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|
|
|
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|
|
|
|
|
|
|
|
|
/*=============================================================================================*/
|
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|
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|
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|
|
|
|
/*
|
|
|
|
|
* Restore Context for cases other than INTi.
|
|
|
|
|
*/
|
|
|
|
|
#define portRESTORE_CONTEXT() \
|
|
|
|
|
{ \
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|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
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|
|
extern volatile void *volatile pxCurrentTCB; \
|
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|
|
\
|
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|
|
__asm__ __volatile__ ( \
|
|
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|
|
/* Set SP to point to new stack */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
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|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"ld.w sp, r0[0] \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Restore ulCriticalNesting variable */ \
|
|
|
|
|
"ld.w r0, sp++ \n\t"\
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"st.w r8[0], r0 \n\t"\
|
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|
|
\
|
|
|
|
|
/* Restore R0..R7 */ \
|
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|
|
"ldm sp++, r0-r7 \n\t"\
|
|
|
|
|
/* R0-R7 should not be used below this line */ \
|
|
|
|
|
/* Skip PC and SR (will do it at the end) */ \
|
|
|
|
|
"sub sp, -2*4 \n\t"\
|
|
|
|
|
/* Restore R8..R12 and LR */ \
|
|
|
|
|
"ldm sp++, r8-r12, lr \n\t"\
|
|
|
|
|
/* Restore SR */ \
|
|
|
|
|
"ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
|
|
|
|
|
"mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
|
|
|
|
|
/* Restore r0 */ \
|
|
|
|
|
"ld.w r0, sp[-9*4] \n\t"\
|
|
|
|
|
/* Restore PC */ \
|
|
|
|
|
"ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Force import of global symbols from assembly */ \
|
|
|
|
|
ulCriticalNesting; \
|
|
|
|
|
pxCurrentTCB; \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
|
|
|
|
|
* portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
|
|
|
|
|
*
|
|
|
|
|
* Had to make different versions because registers saved on the system stack
|
|
|
|
|
* are not the same between INT0..3 exceptions and the scall exception.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
// Task context stack layout:
|
|
|
|
|
// R8 (*)
|
|
|
|
|
// R9 (*)
|
|
|
|
|
// R10 (*)
|
|
|
|
|
// R11 (*)
|
|
|
|
|
// R12 (*)
|
|
|
|
|
// R14/LR (*)
|
|
|
|
|
// R15/PC (*)
|
|
|
|
|
// SR (*)
|
|
|
|
|
// R0
|
|
|
|
|
// R1
|
|
|
|
|
// R2
|
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|
|
// R3
|
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|
|
|
// R4
|
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|
|
|
// R5
|
|
|
|
|
// R6
|
|
|
|
|
// R7
|
|
|
|
|
// ulCriticalNesting
|
|
|
|
|
// (*) automatically done for INT0..INT3, but not for SCALL
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The ISR used for the scheduler tick depends on whether the cooperative or
|
|
|
|
|
* the preemptive scheduler is being used.
|
|
|
|
|
*/
|
|
|
|
|
#if configUSE_PREEMPTION == 0
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
|
|
|
|
*/
|
|
|
|
|
#define portSAVE_CONTEXT_OS_INT() \
|
|
|
|
|
{ \
|
|
|
|
|
/* Save R0..R7 */ \
|
|
|
|
|
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
|
|
|
|
\
|
|
|
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
|
|
|
|
/* there is also no context save. */ \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
|
|
|
|
*/
|
|
|
|
|
#define portRESTORE_CONTEXT_OS_INT() \
|
|
|
|
|
{ \
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Restore R0..R7 */ \
|
|
|
|
|
"ldm sp++, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
|
|
|
|
/* there is also no context restore. */ \
|
|
|
|
|
"rete" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
|
|
|
|
*/
|
|
|
|
|
#define portSAVE_CONTEXT_OS_INT() \
|
|
|
|
|
{ \
|
|
|
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
|
|
|
extern volatile void *volatile pxCurrentTCB; \
|
|
|
|
|
\
|
|
|
|
|
/* When we come here */ \
|
|
|
|
|
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
|
|
|
|
\
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Save R0..R7 */ \
|
|
|
|
|
"stm --sp, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"st.w --sp, r0 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
|
|
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
|
|
|
|
/* level and allow other lower interrupt level to occur). */ \
|
|
|
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
|
|
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
|
|
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
|
|
|
|
/* will just be restoring the interrupt handler, no way!!! */ \
|
|
|
|
|
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
|
|
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
|
|
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
|
|
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
|
|
|
|
"brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
|
|
|
|
/* NOTE: we don't enter a critical section here because all interrupt handlers */ \
|
|
|
|
|
/* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
|
|
|
|
|
/* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
|
|
|
|
|
/* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"st.w r0[0], sp \n"\
|
|
|
|
|
\
|
|
|
|
|
"LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
|
|
|
|
*/
|
|
|
|
|
#define portRESTORE_CONTEXT_OS_INT() \
|
|
|
|
|
{ \
|
|
|
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
|
|
|
extern volatile void *volatile pxCurrentTCB; \
|
|
|
|
|
\
|
|
|
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
|
|
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
|
|
|
|
/* level and allow other lower interrupt level to occur). */ \
|
|
|
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
|
|
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
|
|
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
|
|
|
|
/* will just be restoring the interrupt handler, no way!!! */ \
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
|
|
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
|
|
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
|
|
|
|
"brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Else */ \
|
|
|
|
|
/* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
|
|
|
|
|
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
|
|
|
|
|
portENTER_CRITICAL(); \
|
|
|
|
|
vTaskSwitchContext(); \
|
|
|
|
|
portEXIT_CRITICAL(); \
|
|
|
|
|
\
|
|
|
|
|
/* Restore all registers */ \
|
|
|
|
|
\
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Set SP to point to new stack */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"ld.w sp, r0[0] \n"\
|
|
|
|
|
\
|
|
|
|
|
"LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Restore ulCriticalNesting variable */ \
|
|
|
|
|
"ld.w r0, sp++ \n\t"\
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"st.w r8[0], r0 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Restore R0..R7 */ \
|
|
|
|
|
"ldm sp++, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
|
|
|
|
"rete" \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Force import of global symbols from assembly */ \
|
|
|
|
|
ulCriticalNesting; \
|
|
|
|
|
pxCurrentTCB; \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
|
|
|
|
|
*
|
|
|
|
|
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
#define portSAVE_CONTEXT_SCALL() \
|
|
|
|
|
{ \
|
|
|
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
|
|
|
extern volatile void *volatile pxCurrentTCB; \
|
|
|
|
|
\
|
|
|
|
|
/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
|
|
|
|
|
/* If SR[M2:M0] == 001 */ \
|
|
|
|
|
/* PC and SR are on the stack. */ \
|
|
|
|
|
/* Else (other modes) */ \
|
|
|
|
|
/* Nothing on the stack. */ \
|
|
|
|
|
\
|
|
|
|
|
/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
|
|
|
|
|
/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
|
|
|
|
|
/* in an interrupt|exception handler. */ \
|
|
|
|
|
\
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* in order to save R0-R7 */ \
|
|
|
|
|
"sub sp, 6*4 \n\t"\
|
|
|
|
|
/* Save R0..R7 */ \
|
|
|
|
|
"stm --sp, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* in order to save R8-R12 and LR */ \
|
|
|
|
|
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
|
|
|
|
"sub r7, sp,-16*4 \n\t"\
|
|
|
|
|
/* Copy PC and SR in other places in the stack. */ \
|
|
|
|
|
"ld.w r0, r7[-2*4] \n\t" /* Read SR */\
|
|
|
|
|
"st.w r7[-8*4], r0 \n\t" /* Copy SR */\
|
|
|
|
|
"ld.w r0, r7[-1*4] \n\t" /* Read PC */\
|
|
|
|
|
"st.w r7[-7*4], r0 \n\t" /* Copy PC */\
|
|
|
|
|
\
|
|
|
|
|
/* Save R8..R12 and LR on the stack. */ \
|
|
|
|
|
"stm --r7, r8-r12, lr \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Arriving here we have the following stack organizations: */ \
|
|
|
|
|
/* R8..R12, LR, PC, SR, R0..R7. */ \
|
|
|
|
|
\
|
|
|
|
|
/* Now we can finalize the save. */ \
|
|
|
|
|
\
|
|
|
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"st.w --sp, r0" \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Disable the its which may cause a context switch (i.e. cause a change of */ \
|
|
|
|
|
/* pxCurrentTCB). */ \
|
|
|
|
|
/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
|
|
|
|
|
/* critical section because it is a global structure. */ \
|
|
|
|
|
portENTER_CRITICAL(); \
|
|
|
|
|
\
|
|
|
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"st.w r0[0], sp" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* portRESTORE_CONTEXT() for SupervisorCALL exception.
|
|
|
|
|
*/
|
|
|
|
|
#define portRESTORE_CONTEXT_SCALL() \
|
|
|
|
|
{ \
|
|
|
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
|
|
|
extern volatile void *volatile pxCurrentTCB; \
|
|
|
|
|
\
|
|
|
|
|
/* Restore all registers */ \
|
|
|
|
|
\
|
|
|
|
|
/* Set SP to point to new stack */ \
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"ld.w sp, r0[0]" \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Leave pxCurrentTCB variable access critical section */ \
|
|
|
|
|
portEXIT_CRITICAL(); \
|
|
|
|
|
\
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Restore ulCriticalNesting variable */ \
|
|
|
|
|
"ld.w r0, sp++ \n\t"\
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"st.w r8[0], r0 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* skip PC and SR */ \
|
|
|
|
|
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
|
|
|
|
"sub r7, sp, -10*4 \n\t"\
|
|
|
|
|
/* Restore r8-r12 and LR */ \
|
|
|
|
|
"ldm r7++, r8-r12, lr \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* RETS will take care of the extra PC and SR restore. */ \
|
|
|
|
|
/* So, we have to prepare the stack for this. */ \
|
|
|
|
|
"ld.w r0, r7[-8*4] \n\t" /* Read SR */\
|
|
|
|
|
"st.w r7[-2*4], r0 \n\t" /* Copy SR */\
|
|
|
|
|
"ld.w r0, r7[-7*4] \n\t" /* Read PC */\
|
|
|
|
|
"st.w r7[-1*4], r0 \n\t" /* Copy PC */\
|
|
|
|
|
\
|
|
|
|
|
/* Restore R0..R7 */ \
|
|
|
|
|
"ldm sp++, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
"sub sp, -6*4 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
"rets" \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Force import of global symbols from assembly */ \
|
|
|
|
|
ulCriticalNesting; \
|
|
|
|
|
pxCurrentTCB; \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The ISR used depends on whether the cooperative or
|
|
|
|
|
* the preemptive scheduler is being used.
|
|
|
|
|
*/
|
|
|
|
|
#if configUSE_PREEMPTION == 0
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ISR entry and exit macros. These are only required if a task switch
|
|
|
|
|
* is required from the ISR.
|
|
|
|
|
*/
|
|
|
|
|
#define portENTER_SWITCHING_ISR() \
|
|
|
|
|
{ \
|
|
|
|
|
/* Save R0..R7 */ \
|
|
|
|
|
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
|
|
|
|
\
|
|
|
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
|
|
|
|
/* there is also no context save. */ \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
|
|
|
|
*/
|
|
|
|
|
#define portEXIT_SWITCHING_ISR() \
|
|
|
|
|
{ \
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Restore R0..R7 */ \
|
|
|
|
|
"ldm sp++, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
|
|
|
|
/* there is also no context restore. */ \
|
|
|
|
|
"rete" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ISR entry and exit macros. These are only required if a task switch
|
|
|
|
|
* is required from the ISR.
|
|
|
|
|
*/
|
|
|
|
|
#define portENTER_SWITCHING_ISR() \
|
|
|
|
|
{ \
|
|
|
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
|
|
|
extern volatile void *volatile pxCurrentTCB; \
|
|
|
|
|
\
|
|
|
|
|
/* When we come here */ \
|
|
|
|
|
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
|
|
|
|
\
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Save R0..R7 */ \
|
|
|
|
|
"stm --sp, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"st.w --sp, r0 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
|
|
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
|
|
|
|
/* level and allow other lower interrupt level to occur). */ \
|
|
|
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
|
|
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
|
|
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
|
|
|
|
/* will just be restoring the interrupt handler, no way!!! */ \
|
|
|
|
|
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
|
|
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
|
|
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
|
|
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
|
|
|
|
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"st.w r0[0], sp \n"\
|
|
|
|
|
\
|
|
|
|
|
"LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
|
|
|
|
*/
|
|
|
|
|
#define portEXIT_SWITCHING_ISR() \
|
|
|
|
|
{ \
|
|
|
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
|
|
|
|
extern volatile void *volatile pxCurrentTCB; \
|
|
|
|
|
\
|
|
|
|
|
__asm__ __volatile__ ( \
|
|
|
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
|
|
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
|
|
|
|
/* level and allow other lower interrupt level to occur). */ \
|
|
|
|
|
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
|
|
|
|
|
/* did not previously save SP in its TCB. */ \
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"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
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|
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"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
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|
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"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
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|
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"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
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\
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/* If a switch is required then we just need to call */ \
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|
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/* vTaskSwitchContext() as the context has already been */ \
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/* saved. */ \
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|
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"cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
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|
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|
"brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
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|
|
|
); \
|
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|
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|
\
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|
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|
|
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
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|
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portENTER_CRITICAL(); \
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vTaskSwitchContext(); \
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portEXIT_CRITICAL(); \
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\
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|
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__asm__ __volatile__ ( \
|
|
|
|
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"LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
|
|
|
|
|
/* Restore the context of which ever task is now the highest */ \
|
|
|
|
|
/* priority that is ready to run. */ \
|
|
|
|
|
\
|
|
|
|
|
/* Restore all registers */ \
|
|
|
|
|
\
|
|
|
|
|
/* Set SP to point to new stack */ \
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
|
|
|
|
"ld.w r0, r8[0] \n\t"\
|
|
|
|
|
"ld.w sp, r0[0] \n"\
|
|
|
|
|
\
|
|
|
|
|
"LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Restore ulCriticalNesting variable */ \
|
|
|
|
|
"ld.w r0, sp++ \n\t"\
|
|
|
|
|
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
|
|
|
|
"st.w r8[0], r0 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Restore R0..R7 */ \
|
|
|
|
|
"ldm sp++, r0-r7 \n\t"\
|
|
|
|
|
\
|
|
|
|
|
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
|
|
|
|
"rete" \
|
|
|
|
|
); \
|
|
|
|
|
\
|
|
|
|
|
/* Force import of global symbols from assembly */ \
|
|
|
|
|
ulCriticalNesting; \
|
|
|
|
|
pxCurrentTCB; \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define portYIELD() {__asm__ __volatile__ ("scall");}
|
|
|
|
|
|
|
|
|
|
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
|
|
|
|
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
|
|
|
|
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* PORTMACRO_H */
|
