Add AVR32 port and demo files.
Richard Barry
18 years ago
parent
45d8ca15b5
commit
504382bcb8
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/******************************************************************************
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* Exception and interrupt vectors.
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*
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* This file has been built from the Newlib exception.S. It maps all events
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* supported by a UC3.
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*
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* - Compiler: GNU GCC for AVR32
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* - Supported devices: All AVR32A devices with an INTC module can be used.
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* - AppNote:
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*
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* - author Atmel Corporation: http://www.atmel.com \n
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* Support email: avr32@atmel.com
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*
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******************************************************************************/
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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of ATMEL may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <avr32/io.h>
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#include "intc.h"
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.section .exception, "ax"
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// Start of Exception Vector Table.
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// EVBA must be aligned with a power of two strictly greater than the EVBA-
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// relative offset of the last vector.
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.balign 0x200
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// Export symbol.
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.global _evba
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_evba:
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.org 0x000
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// Unrecoverable Exception.
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_handle_Unrecoverable_Exception:
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rjmp $
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.org 0x004
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// TLB Multiple Hit: UNUSED IN AVR32A.
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_handle_TLB_Multiple_Hit:
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rjmp $
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.org 0x008
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// Bus Error Data Fetch.
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_handle_Bus_Error_Data_Fetch:
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rjmp $
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.org 0x00C
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// Bus Error Instruction Fetch.
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_handle_Bus_Error_Instruction_Fetch:
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rjmp $
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.org 0x010
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// NMI.
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_handle_NMI:
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rjmp $
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.org 0x014
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// Instruction Address.
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_handle_Instruction_Address:
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rjmp $
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.org 0x018
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// ITLB Protection.
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_handle_ITLB_Protection:
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rjmp $
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.org 0x01C
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// Breakpoint.
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_handle_Breakpoint:
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rjmp $
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.org 0x020
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// Illegal Opcode.
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_handle_Illegal_Opcode:
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rjmp $
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.org 0x024
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// Unimplemented Instruction.
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_handle_Unimplemented_Instruction:
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rjmp $
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.org 0x028
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// Privilege Violation.
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_handle_Privilege_Violation:
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rjmp $
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.org 0x02C
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// Floating-Point: UNUSED IN AVR32A.
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_handle_Floating_Point:
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rjmp $
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.org 0x030
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// Coprocessor Absent: UNUSED IN AVR32A.
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_handle_Coprocessor_Absent:
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rjmp $
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.org 0x034
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// Data Address (Read).
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_handle_Data_Address_Read:
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rjmp $
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.org 0x038
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// Data Address (Write).
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_handle_Data_Address_Write:
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rjmp $
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.org 0x03C
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// DTLB Protection (Read).
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_handle_DTLB_Protection_Read:
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rjmp $
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.org 0x040
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// DTLB Protection (Write).
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_handle_DTLB_Protection_Write:
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rjmp $
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.org 0x044
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// DTLB Modified: UNUSED IN AVR32A.
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_handle_DTLB_Modified:
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rjmp $
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.org 0x050
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// ITLB Miss: UNUSED IN AVR32A.
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_handle_ITLB_Miss:
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rjmp $
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.org 0x060
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// DTLB Miss (Read): UNUSED IN AVR32A.
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_handle_DTLB_Miss_Read:
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rjmp $
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.org 0x070
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// DTLB Miss (Write): UNUSED IN AVR32A.
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_handle_DTLB_Miss_Write:
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rjmp $
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.org 0x100
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// Supervisor Call.
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_handle_Supervisor_Call:
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lda.w pc, SCALLYield
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// Interrupt support.
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// The interrupt controller must provide the offset address relative to EVBA.
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// Important note:
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// All interrupts call a C function named _get_interrupt_handler.
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// This function will read group and interrupt line number to then return in
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// R12 a pointer to a user-provided interrupt handler.
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.balign 4
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_int0:
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// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
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// CPU upon interrupt entry.
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#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
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mfsr r12, AVR32_SR
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bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
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cp.w r12, 0b110
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brlo _int0_normal
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lddsp r12, sp[0 * 4]
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stdsp sp[6 * 4], r12
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lddsp r12, sp[1 * 4]
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stdsp sp[7 * 4], r12
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lddsp r12, sp[3 * 4]
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sub sp, -6 * 4
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rete
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_int0_normal:
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#endif
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mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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_int1:
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// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
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// CPU upon interrupt entry.
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#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
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mfsr r12, AVR32_SR
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bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
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cp.w r12, 0b110
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brlo _int1_normal
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lddsp r12, sp[0 * 4]
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stdsp sp[6 * 4], r12
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lddsp r12, sp[1 * 4]
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stdsp sp[7 * 4], r12
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lddsp r12, sp[3 * 4]
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sub sp, -6 * 4
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rete
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_int1_normal:
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#endif
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mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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_int2:
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// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
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// CPU upon interrupt entry.
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#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
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mfsr r12, AVR32_SR
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bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
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cp.w r12, 0b110
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brlo _int2_normal
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lddsp r12, sp[0 * 4]
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stdsp sp[6 * 4], r12
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lddsp r12, sp[1 * 4]
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stdsp sp[7 * 4], r12
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lddsp r12, sp[3 * 4]
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sub sp, -6 * 4
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rete
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_int2_normal:
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#endif
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mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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_int3:
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// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
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// CPU upon interrupt entry.
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#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
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mfsr r12, AVR32_SR
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bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
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cp.w r12, 0b110
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brlo _int3_normal
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lddsp r12, sp[0 * 4]
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stdsp sp[6 * 4], r12
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lddsp r12, sp[1 * 4]
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stdsp sp[7 * 4], r12
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lddsp r12, sp[3 * 4]
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sub sp, -6 * 4
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rete
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_int3_normal:
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#endif
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mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
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call _get_interrupt_handler
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cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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// Constant data area.
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.balign 4
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// Values to store in the interrupt priority registers for the various interrupt priority levels.
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// The interrupt priority registers contain the interrupt priority level and
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// the EVBA-relative interrupt vector offset.
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.global ipr_val
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ipr_val:
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.word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
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(INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
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(INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
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(INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
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@ -0,0 +1,401 @@
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS port source for AVR32 UC3.
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*
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* - Compiler: GNU GCC for AVR32
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* - Supported devices: All AVR32 devices can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support email: avr32@atmel.com
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*
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*****************************************************************************/
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/*
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FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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/* Standard includes. */
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#include <sys/cpu.h>
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#include <sys/usart.h>
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#include <malloc.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* AVR32 UC3 includes. */
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#include <avr32/io.h>
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#include "gpio.h"
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#if( configTICK_USE_TC==1 )
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#include "tc.h"
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#endif
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/* Constants required to setup the task context. */
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#define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
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/* Each task maintains its own critical nesting variable. */
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#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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volatile unsigned portLONG ulCriticalNesting = 9999UL;
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#if( configTICK_USE_TC==0 )
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static void prvScheduleNextTick( void );
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#endif
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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/*-----------------------------------------------------------*/
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/*
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* Low-level initialization routine called during Newlib's startup.
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* This version comes in replacement to the default one provided by Newlib.
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* Newlib's _init_startup only calls init_exceptions, but Newlib's exception
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* vectors are not compatible with the SCALL management in the current FreeRTOS
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* port. More low-level initializations are besides added here.
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*/
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void _init_startup(void)
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{
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/* Import the Exception Vector Base Address. */
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extern void _evba;
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#if configHEAP_INIT
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extern void __heap_start__;
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extern void __heap_end__;
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portBASE_TYPE *pxMem;
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#endif
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/* Load the Exception Vector Base Address in the corresponding system register. */
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Set_system_register( AVR32_EVBA, ( int ) &_evba );
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/* Enable exceptions. */
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ENABLE_ALL_EXCEPTIONS();
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/* Initialize interrupt handling. */
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INTC_init_interrupts();
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#if configHEAP_INIT
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/* Initialize the heap used by malloc. */
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for( pxMem = &__heap_start__; pxMem < ( portBASE_TYPE * )&__heap_end__; )
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{
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*pxMem++ = 0xA5A5A5A5;
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}
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#endif
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/* Give the used CPU clock frequency to Newlib, so it can work properly. */
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set_cpu_hz( configCPU_CLOCK_HZ );
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/* Code section present if and only if the debug trace is activated. */
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#if configDBG
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/* Initialize the USART used for the debug trace with the configured parameters. */
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set_usart_base( ( void * ) configDBG_USART );
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gpio_enable_module_pin( configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION );
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gpio_enable_module_pin( configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION );
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usart_init( configDBG_USART_BAUDRATE );
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#endif
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}
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/*-----------------------------------------------------------*/
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/*
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* malloc, realloc and free are meant to be called through respectively
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* pvPortMalloc, pvPortRealloc and vPortFree.
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* The latter functions call the former ones from within sections where tasks
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* are suspended, so the latter functions are task-safe. __malloc_lock and
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* __malloc_unlock use the same mechanism to also keep the former functions
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* task-safe as they may be called directly from Newlib's functions.
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* However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
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* CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
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* not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
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* interrupts during memory allocation management as this may be a very time-
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* consuming process.
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*/
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/*
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* Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
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* safe section as memory allocation management uses global data.
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* See the aforementioned details.
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*/
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void __malloc_lock(struct _reent *ptr)
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{
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vTaskSuspendAll();
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}
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/*
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* Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
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* a safe section as memory allocation management uses global data.
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* See the aforementioned details.
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*/
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void __malloc_unlock(struct _reent *ptr)
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{
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xTaskResumeAll();
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}
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/*-----------------------------------------------------------*/
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/* Added as there is no such function in FreeRTOS. */
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void *pvPortRealloc( void *pv, size_t xWantedSize )
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{
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void *pvReturn;
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vTaskSuspendAll();
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{
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pvReturn = realloc( pv, xWantedSize );
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}
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xTaskResumeAll();
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return pvReturn;
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}
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/*-----------------------------------------------------------*/
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/* The cooperative scheduler requires a normal IRQ service routine to
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simply increment the system tick. */
|
||||
/* The preemptive scheduler is defined as "naked" as the full context is saved
|
||||
on entry as part of the context switch. */
|
||||
__attribute__((__naked__)) static void vTick( void )
|
||||
{
|
||||
/* Save the context of the interrupted task. */
|
||||
portSAVE_CONTEXT_OS_INT();
|
||||
|
||||
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
|
||||
clock cycles from now. */
|
||||
#if( configTICK_USE_TC==1 )
|
||||
/* Clear the interrupt flag. */
|
||||
AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
|
||||
#else
|
||||
prvScheduleNextTick();
|
||||
#endif
|
||||
|
||||
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
|
||||
calls in a critical section . */
|
||||
portENTER_CRITICAL();
|
||||
vTaskIncrementTick();
|
||||
portEXIT_CRITICAL();
|
||||
|
||||
/* Restore the context of the "elected task". */
|
||||
portRESTORE_CONTEXT_OS_INT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__attribute__((__naked__)) void SCALLYield( void )
|
||||
{
|
||||
/* Save the context of the interrupted task. */
|
||||
portSAVE_CONTEXT_SCALL();
|
||||
vTaskSwitchContext();
|
||||
portRESTORE_CONTEXT_SCALL();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The code generated by the GCC compiler uses the stack in different ways at
|
||||
different optimisation levels. The interrupt flags can therefore not always
|
||||
be saved to the stack. Instead the critical section nesting level is stored
|
||||
in a variable, which is then saved as part of the stack context. */
|
||||
void vPortEnterCritical( void )
|
||||
{
|
||||
/* Disable interrupts */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Now interrupts are disabled ulCriticalNesting can be accessed
|
||||
directly. Increment ulCriticalNesting to keep a count of how many times
|
||||
portENTER_CRITICAL() has been called. */
|
||||
ulCriticalNesting++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExitCritical( void )
|
||||
{
|
||||
if(ulCriticalNesting > portNO_CRITICAL_NESTING)
|
||||
{
|
||||
ulCriticalNesting--;
|
||||
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Enable all interrupt/exception. */
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/*
|
||||
* Initialise the stack of a task to look exactly as if a call to
|
||||
* portSAVE_CONTEXT had been called.
|
||||
*
|
||||
* See header file for description.
|
||||
*/
|
||||
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
|
||||
{
|
||||
/* Setup the initial stack of the task. The stack is set exactly as
|
||||
expected by the portRESTORE_CONTEXT() macro. */
|
||||
|
||||
/* When the task starts, it will expect to find the function parameter in R12. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
|
||||
*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portBASE_TYPE xPortStartScheduler( void )
|
||||
{
|
||||
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
||||
here already. */
|
||||
prvSetupTimerInterrupt();
|
||||
|
||||
/* Start the first task. */
|
||||
portRESTORE_CONTEXT();
|
||||
|
||||
/* Should not get here! */
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* It is unlikely that the AVR32 port will require this function as there
|
||||
is nothing to return to. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
|
||||
clock cycles from now. */
|
||||
#if( configTICK_USE_TC==0 )
|
||||
static void prvScheduleNextTick(void)
|
||||
{
|
||||
unsigned long lCountVal, lCompareVal;
|
||||
|
||||
lCountVal = Get_system_register(AVR32_COUNT);
|
||||
lCompareVal = lCountVal + (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
|
||||
Set_system_register(AVR32_COMPARE, lCompareVal);
|
||||
}
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Setup the timer to generate the tick interrupts. */
|
||||
static void prvSetupTimerInterrupt(void)
|
||||
{
|
||||
#if( configTICK_USE_TC==1 )
|
||||
|
||||
volatile avr32_tc_t *tc = &AVR32_TC;
|
||||
|
||||
// Options for waveform genration.
|
||||
tc_waveform_opt_t waveform_opt =
|
||||
{
|
||||
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
|
||||
|
||||
.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
|
||||
.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
|
||||
.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
|
||||
.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
|
||||
|
||||
.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
|
||||
.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
|
||||
.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
|
||||
.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
|
||||
|
||||
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
|
||||
.enetrg = FALSE, /* External event trigger enable. */
|
||||
.eevt = 0, /* External event selection. */
|
||||
.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
|
||||
.cpcdis = FALSE, /* Counter disable when RC compare. */
|
||||
.cpcstop = FALSE, /* Counter clock stopped with RC compare. */
|
||||
|
||||
.burst = FALSE, /* Burst signal selection. */
|
||||
.clki = FALSE, /* Clock inversion. */
|
||||
.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
|
||||
};
|
||||
|
||||
tc_interrupt_t tc_interrupt =
|
||||
{
|
||||
.etrgs=0,
|
||||
.ldrbs=0,
|
||||
.ldras=0,
|
||||
.cpcs =1,
|
||||
.cpbs =0,
|
||||
.cpas =0,
|
||||
.lovrs=0,
|
||||
.covfs=0,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* Disable all interrupt/exception. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Register the compare interrupt handler to the interrupt controller and
|
||||
enable the compare interrupt. */
|
||||
|
||||
#if( configTICK_USE_TC==1 )
|
||||
{
|
||||
INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
|
||||
|
||||
/* Initialize the timer/counter. */
|
||||
tc_init_waveform(tc, &waveform_opt);
|
||||
|
||||
/* Set the compare triggers.
|
||||
Remember TC counter is 16-bits, so counting second is not possible!
|
||||
That's why we configure it to count ms. */
|
||||
tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ/ 4) / 1000 );
|
||||
|
||||
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
|
||||
|
||||
/* Start the timer/counter. */
|
||||
tc_start(tc, configTICK_TC_CHANNEL);
|
||||
}
|
||||
#else
|
||||
{
|
||||
INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
|
||||
prvScheduleNextTick();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -0,0 +1,661 @@
|
||||
/*This file has been prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief FreeRTOS port header for AVR32 UC3.
|
||||
*
|
||||
* - Compiler: GNU GCC for AVR32
|
||||
* - Supported devices: All AVR32 devices can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
#include <avr32/io.h>
|
||||
#include "intc.h"
|
||||
#include "compiler.h"
|
||||
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE unsigned portLONG
|
||||
#define portBASE_TYPE portLONG
|
||||
|
||||
#define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
|
||||
#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
|
||||
#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
|
||||
|
||||
#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef unsigned portSHORT portTickType;
|
||||
#define portMAX_DELAY ( portTickType ) 0xffff
|
||||
#else
|
||||
typedef unsigned portLONG portTickType;
|
||||
#define portMAX_DELAY ( portTickType ) 0xffffffff
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 4
|
||||
#define portNOP() {__asm__ __volatile__ ("nop");}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* INTC-specific. */
|
||||
#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
|
||||
#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
|
||||
|
||||
#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
|
||||
#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
|
||||
|
||||
#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
|
||||
#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
|
||||
|
||||
|
||||
/*
|
||||
* Debug trace.
|
||||
* Activated if and only if configDBG is nonzero.
|
||||
* Prints a formatted string to stdout.
|
||||
* The current source file name and line number are output with a colon before
|
||||
* the formatted string.
|
||||
* A carriage return and a linefeed are appended to the output.
|
||||
* stdout is redirected by Newlib to the USART configured by configDBG_USART.
|
||||
* The parameters are the same as for the standard printf function.
|
||||
* There is no return value.
|
||||
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
|
||||
* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
|
||||
*/
|
||||
#if configDBG
|
||||
#define portDBG_TRACE(...) \
|
||||
{\
|
||||
fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
|
||||
printf(__VA_ARGS__);\
|
||||
fputs("\r\n", stdout);\
|
||||
}
|
||||
#else
|
||||
#define portDBG_TRACE(...)
|
||||
#endif
|
||||
|
||||
|
||||
/* Critical section management. */
|
||||
#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
|
||||
#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
|
||||
|
||||
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
|
||||
#define portENTER_CRITICAL() vPortEnterCritical();
|
||||
#define portEXIT_CRITICAL() vPortExitCritical();
|
||||
|
||||
|
||||
/* Added as there is no such function in FreeRTOS. */
|
||||
extern void *pvPortRealloc( void *pv, size_t xSize );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/*=============================================================================================*/
|
||||
|
||||
/*
|
||||
* Restore Context for cases other than INTi.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0] \n\t"\
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
/* R0-R7 should not be used below this line */ \
|
||||
/* Skip PC and SR (will do it at the end) */ \
|
||||
"sub sp, -2*4 \n\t"\
|
||||
/* Restore R8..R12 and LR */ \
|
||||
"ldm sp++, r8-r12, lr \n\t"\
|
||||
/* Restore SR */ \
|
||||
"ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
|
||||
"mtsr %[SR], r0 \n\t"\
|
||||
/* Restore r0 */ \
|
||||
"ld.w r0, sp[-9*4] \n\t"\
|
||||
/* Restore PC */ \
|
||||
"ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
||||
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
||||
[SR] "i" (AVR32_SR) \
|
||||
); \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
|
||||
* portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
|
||||
*
|
||||
* Had to make different versions because registers saved on the system stack
|
||||
* are not the same between INT0..3 exceptions and the scall exception.
|
||||
*/
|
||||
|
||||
// Task context stack layout:
|
||||
// R8 (*)
|
||||
// R9 (*)
|
||||
// R10 (*)
|
||||
// R11 (*)
|
||||
// R12 (*)
|
||||
// R14/LR (*)
|
||||
// R15/PC (*)
|
||||
// SR (*)
|
||||
// R0
|
||||
// R1
|
||||
// R2
|
||||
// R3
|
||||
// R4
|
||||
// R5
|
||||
// R6
|
||||
// R7
|
||||
// ulCriticalNesting
|
||||
// (*) automatically done for INT0..INT3, but not for SCALL
|
||||
|
||||
/*
|
||||
* The ISR used for the scheduler tick depends on whether the cooperative or
|
||||
* the preemptive scheduler is being used.
|
||||
*/
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
||||
*/
|
||||
#define portSAVE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
/* Save R0..R7 */ \
|
||||
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context save. */ \
|
||||
}
|
||||
|
||||
/*
|
||||
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7\n\t" \
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context restore. */ \
|
||||
"rete" \
|
||||
); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
||||
*/
|
||||
#define portSAVE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* When we come here */ \
|
||||
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LO(%[ulCriticalNesting])\n\t" \
|
||||
"orh r8, HI(%[ulCriticalNesting])\n\t" \
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0 \n\t"\
|
||||
\
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
||||
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
||||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
||||
"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
|
||||
"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
|
||||
"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
|
||||
"brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
|
||||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
/* NOTE: we don't enter a critical section here because all interrupt handlers */ \
|
||||
/* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
|
||||
/* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
|
||||
/* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
|
||||
"mov r8, LO(%[pxCurrentTCB])\n\t" \
|
||||
"orh r8, HI(%[pxCurrentTCB])\n\t" \
|
||||
"ld.w r0, r8[0]\n\t" \
|
||||
"st.w r0[0], sp\n" \
|
||||
\
|
||||
"LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
||||
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
||||
[LINE] "i" (__LINE__) \
|
||||
); \
|
||||
}
|
||||
|
||||
/*
|
||||
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
||||
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
||||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
|
||||
"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
|
||||
"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
|
||||
"brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
|
||||
: \
|
||||
: [LINE] "i" (__LINE__) \
|
||||
); \
|
||||
\
|
||||
/* Else */ \
|
||||
/* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
|
||||
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
|
||||
portENTER_CRITICAL(); \
|
||||
vTaskSwitchContext(); \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0] \n"\
|
||||
\
|
||||
"LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t" \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
||||
"rete" \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
||||
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
||||
[LINE] "i" (__LINE__) \
|
||||
); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
|
||||
*
|
||||
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
|
||||
*
|
||||
*/
|
||||
#define portSAVE_CONTEXT_SCALL() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
|
||||
/* If SR[M2:M0] == 001 */ \
|
||||
/* PC and SR are on the stack. */ \
|
||||
/* Else (other modes) */ \
|
||||
/* Nothing on the stack. */ \
|
||||
\
|
||||
/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
|
||||
/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
|
||||
/* in an interrupt|exception handler. */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* in order to save R0-R7 */ \
|
||||
"sub sp, 6*4 \n\t"\
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* in order to save R8-R12 and LR */ \
|
||||
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
||||
"sub r7, sp,-16*4 \n\t"\
|
||||
/* Copy PC and SR in other places in the stack. */ \
|
||||
"ld.w r0, r7[-2*4] \n\t" /* Read SR */\
|
||||
"st.w r7[-8*4], r0 \n\t" /* Copy SR */\
|
||||
"ld.w r0, r7[-1*4] \n\t" /* Read PC */\
|
||||
"st.w r7[-7*4], r0 \n\t" /* Copy PC */\
|
||||
\
|
||||
/* Save R8..R12 and LR on the stack. */ \
|
||||
"stm --r7, r8-r12, lr \n\t"\
|
||||
\
|
||||
/* Arriving here we have the following stack organizations: */ \
|
||||
/* R8..R12, LR, PC, SR, R0..R7. */ \
|
||||
\
|
||||
/* Now we can finalize the save. */ \
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0" \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting) \
|
||||
); \
|
||||
\
|
||||
/* Disable the its which may cause a context switch (i.e. cause a change of */ \
|
||||
/* pxCurrentTCB). */ \
|
||||
/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
|
||||
/* critical section because it is a global structure. */ \
|
||||
portENTER_CRITICAL(); \
|
||||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w r0[0], sp" \
|
||||
: \
|
||||
: [pxCurrentTCB] "i" (&pxCurrentTCB) \
|
||||
); \
|
||||
}
|
||||
|
||||
/*
|
||||
* portRESTORE_CONTEXT() for SupervisorCALL exception.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT_SCALL() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0]" \
|
||||
: \
|
||||
: [pxCurrentTCB] "i" (&pxCurrentTCB) \
|
||||
); \
|
||||
\
|
||||
/* Leave pxCurrentTCB variable access critical section */ \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* skip PC and SR */ \
|
||||
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
||||
"sub r7, sp, -10*4 \n\t"\
|
||||
/* Restore r8-r12 and LR */ \
|
||||
"ldm r7++, r8-r12, lr \n\t"\
|
||||
\
|
||||
/* RETS will take care of the extra PC and SR restore. */ \
|
||||
/* So, we have to prepare the stack for this. */ \
|
||||
"ld.w r0, r7[-8*4] \n\t" /* Read SR */\
|
||||
"st.w r7[-2*4], r0 \n\t" /* Copy SR */\
|
||||
"ld.w r0, r7[-7*4] \n\t" /* Read PC */\
|
||||
"st.w r7[-1*4], r0 \n\t" /* Copy PC */\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
"sub sp, -6*4 \n\t"\
|
||||
\
|
||||
"rets" \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting) \
|
||||
); \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* The ISR used depends on whether the cooperative or
|
||||
* the preemptive scheduler is being used.
|
||||
*/
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
||||
/*
|
||||
* ISR entry and exit macros. These are only required if a task switch
|
||||
* is required from the ISR.
|
||||
*/
|
||||
#define portENTER_SWITCHING_ISR() \
|
||||
{ \
|
||||
/* Save R0..R7 */ \
|
||||
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context save. */ \
|
||||
}
|
||||
|
||||
/*
|
||||
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
||||
*/
|
||||
#define portEXIT_SWITCHING_ISR() \
|
||||
{ \
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context restore. */ \
|
||||
"rete" \
|
||||
); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* ISR entry and exit macros. These are only required if a task switch
|
||||
* is required from the ISR.
|
||||
*/
|
||||
#define portENTER_SWITCHING_ISR() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* When we come here */ \
|
||||
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0 \n\t"\
|
||||
\
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
||||
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
||||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
||||
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
|
||||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w r0[0], sp \n"\
|
||||
\
|
||||
"LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
||||
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
||||
[LINE] "i" (__LINE__) \
|
||||
); \
|
||||
}
|
||||
|
||||
/*
|
||||
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
||||
*/
|
||||
#define portEXIT_SWITCHING_ISR() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
|
||||
/* did not previously save SP in its TCB. */ \
|
||||
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
|
||||
\
|
||||
/* If a switch is required then we just need to call */ \
|
||||
/* vTaskSwitchContext() as the context has already been */ \
|
||||
/* saved. */ \
|
||||
"cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
|
||||
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
|
||||
: \
|
||||
: [LINE] "i" (__LINE__) \
|
||||
); \
|
||||
\
|
||||
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
|
||||
portENTER_CRITICAL(); \
|
||||
vTaskSwitchContext(); \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
"LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
|
||||
/* Restore the context of which ever task is now the highest */ \
|
||||
/* priority that is ready to run. */ \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
||||
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0] \n"\
|
||||
\
|
||||
"LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
||||
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
||||
"rete" \
|
||||
: \
|
||||
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
||||
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
||||
[LINE] "i" (__LINE__) \
|
||||
); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define portYIELD() {__asm__ __volatile__ ("scall");}
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
@ -0,0 +1,302 @@
|
||||
/******************************************************************************
|
||||
* Exception and interrupt vectors.
|
||||
*
|
||||
* This file has been built from the Newlib exception.S. It maps all events
|
||||
* supported by a UC3.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32
|
||||
* - Supported devices: All AVR32A devices with an INTC module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* - author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include <avr32/iouc3a0512.h>
|
||||
#include <avr32/uc3a0512.h>
|
||||
#include "intc.h"
|
||||
|
||||
|
||||
// Start of Exception Vector Table.
|
||||
|
||||
// EVBA must be aligned with a power of two strictly greater than the EVBA-
|
||||
// relative offset of the last vector.
|
||||
COMMON EVTAB:CODE:ROOT(9)
|
||||
|
||||
|
||||
// Force EVBA initialization.
|
||||
EXTERN ??init_EVBA
|
||||
REQUIRE ??init_EVBA
|
||||
|
||||
// Export symbol.
|
||||
PUBLIC ??EVBA
|
||||
PUBLIC _evba
|
||||
??EVBA:
|
||||
_evba:
|
||||
|
||||
ORG 0x000
|
||||
// Unrecoverable Exception.
|
||||
_handle_Unrecoverable_Exception:
|
||||
rjmp $
|
||||
|
||||
ORG 0x004
|
||||
// TLB Multiple Hit: UNUSED IN AVR32A.
|
||||
_handle_TLB_Multiple_Hit:
|
||||
rjmp $
|
||||
|
||||
ORG 0x008
|
||||
// Bus Error Data Fetch.
|
||||
_handle_Bus_Error_Data_Fetch:
|
||||
rjmp $
|
||||
|
||||
ORG 0x00C
|
||||
// Bus Error Instruction Fetch.
|
||||
_handle_Bus_Error_Instruction_Fetch:
|
||||
rjmp $
|
||||
|
||||
ORG 0x010
|
||||
// NMI.
|
||||
_handle_NMI:
|
||||
rjmp $
|
||||
|
||||
ORG 0x014
|
||||
// Instruction Address.
|
||||
_handle_Instruction_Address:
|
||||
rjmp $
|
||||
|
||||
ORG 0x018
|
||||
// ITLB Protection.
|
||||
_handle_ITLB_Protection:
|
||||
rjmp $
|
||||
|
||||
ORG 0x01C
|
||||
// Breakpoint.
|
||||
_handle_Breakpoint:
|
||||
rjmp $
|
||||
|
||||
ORG 0x020
|
||||
// Illegal Opcode.
|
||||
_handle_Illegal_Opcode:
|
||||
rjmp $
|
||||
|
||||
ORG 0x024
|
||||
// Unimplemented Instruction.
|
||||
_handle_Unimplemented_Instruction:
|
||||
rjmp $
|
||||
|
||||
ORG 0x028
|
||||
// Privilege Violation.
|
||||
_handle_Privilege_Violation:
|
||||
rjmp $
|
||||
|
||||
ORG 0x02C
|
||||
// Floating-Point: UNUSED IN AVR32A.
|
||||
_handle_Floating_Point:
|
||||
rjmp $
|
||||
|
||||
ORG 0x030
|
||||
// Coprocessor Absent: UNUSED IN AVR32A.
|
||||
_handle_Coprocessor_Absent:
|
||||
rjmp $
|
||||
|
||||
ORG 0x034
|
||||
// Data Address (Read).
|
||||
_handle_Data_Address_Read:
|
||||
rjmp $
|
||||
|
||||
ORG 0x038
|
||||
// Data Address (Write).
|
||||
_handle_Data_Address_Write:
|
||||
rjmp $
|
||||
|
||||
ORG 0x03C
|
||||
// DTLB Protection (Read).
|
||||
_handle_DTLB_Protection_Read:
|
||||
rjmp $
|
||||
|
||||
ORG 0x040
|
||||
// DTLB Protection (Write).
|
||||
_handle_DTLB_Protection_Write:
|
||||
rjmp $
|
||||
|
||||
ORG 0x044
|
||||
// DTLB Modified: UNUSED IN AVR32A.
|
||||
_handle_DTLB_Modified:
|
||||
rjmp $
|
||||
|
||||
ORG 0x050
|
||||
// ITLB Miss: UNUSED IN AVR32A.
|
||||
_handle_ITLB_Miss:
|
||||
rjmp $
|
||||
|
||||
ORG 0x060
|
||||
// DTLB Miss (Read): UNUSED IN AVR32A.
|
||||
_handle_DTLB_Miss_Read:
|
||||
rjmp $
|
||||
|
||||
ORG 0x070
|
||||
// DTLB Miss (Write): UNUSED IN AVR32A.
|
||||
_handle_DTLB_Miss_Write:
|
||||
rjmp $
|
||||
|
||||
ORG 0x100
|
||||
// Supervisor Call.
|
||||
_handle_Supervisor_Call:
|
||||
lddpc pc, __SCALLYield
|
||||
|
||||
|
||||
// Interrupt support.
|
||||
// The interrupt controller must provide the offset address relative to EVBA.
|
||||
// Important note:
|
||||
// All interrupts call a C function named _get_interrupt_handler.
|
||||
// This function will read group and interrupt line number to then return in
|
||||
// R12 a pointer to a user-provided interrupt handler.
|
||||
|
||||
ALIGN 2
|
||||
|
||||
_int0:
|
||||
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
|
||||
// CPU upon interrupt entry.
|
||||
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
|
||||
mfsr r12, AVR32_SR
|
||||
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
|
||||
cp.w r12, 110b
|
||||
brlo _int0_normal
|
||||
lddsp r12, sp[0 * 4]
|
||||
stdsp sp[6 * 4], r12
|
||||
lddsp r12, sp[1 * 4]
|
||||
stdsp sp[7 * 4], r12
|
||||
lddsp r12, sp[3 * 4]
|
||||
sub sp, -6 * 4
|
||||
rete
|
||||
_int0_normal:
|
||||
#endif
|
||||
mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
|
||||
mcall __get_interrupt_handler
|
||||
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
|
||||
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
|
||||
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
|
||||
|
||||
_int1:
|
||||
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
|
||||
// CPU upon interrupt entry.
|
||||
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
|
||||
mfsr r12, AVR32_SR
|
||||
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
|
||||
cp.w r12, 110b
|
||||
brlo _int1_normal
|
||||
lddsp r12, sp[0 * 4]
|
||||
stdsp sp[6 * 4], r12
|
||||
lddsp r12, sp[1 * 4]
|
||||
stdsp sp[7 * 4], r12
|
||||
lddsp r12, sp[3 * 4]
|
||||
sub sp, -6 * 4
|
||||
rete
|
||||
_int1_normal:
|
||||
#endif
|
||||
mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
|
||||
mcall __get_interrupt_handler
|
||||
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
|
||||
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
|
||||
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
|
||||
|
||||
_int2:
|
||||
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
|
||||
// CPU upon interrupt entry.
|
||||
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
|
||||
mfsr r12, AVR32_SR
|
||||
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
|
||||
cp.w r12, 110b
|
||||
brlo _int2_normal
|
||||
lddsp r12, sp[0 * 4]
|
||||
stdsp sp[6 * 4], r12
|
||||
lddsp r12, sp[1 * 4]
|
||||
stdsp sp[7 * 4], r12
|
||||
lddsp r12, sp[3 * 4]
|
||||
sub sp, -6 * 4
|
||||
rete
|
||||
_int2_normal:
|
||||
#endif
|
||||
mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
|
||||
mcall __get_interrupt_handler
|
||||
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
|
||||
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
|
||||
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
|
||||
|
||||
_int3:
|
||||
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
|
||||
// CPU upon interrupt entry.
|
||||
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
|
||||
mfsr r12, AVR32_SR
|
||||
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
|
||||
cp.w r12, 110b
|
||||
brlo _int3_normal
|
||||
lddsp r12, sp[0 * 4]
|
||||
stdsp sp[6 * 4], r12
|
||||
lddsp r12, sp[1 * 4]
|
||||
stdsp sp[7 * 4], r12
|
||||
lddsp r12, sp[3 * 4]
|
||||
sub sp, -6 * 4
|
||||
rete
|
||||
_int3_normal:
|
||||
#endif
|
||||
mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
|
||||
mcall __get_interrupt_handler
|
||||
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
|
||||
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
|
||||
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
|
||||
|
||||
|
||||
// Constant data area.
|
||||
|
||||
ALIGN 2
|
||||
|
||||
// Import symbols.
|
||||
EXTERN SCALLYield
|
||||
EXTERN _get_interrupt_handler
|
||||
__SCALLYield:
|
||||
DC32 SCALLYield
|
||||
__get_interrupt_handler:
|
||||
DC32 _get_interrupt_handler
|
||||
|
||||
// Values to store in the interrupt priority registers for the various interrupt priority levels.
|
||||
// The interrupt priority registers contain the interrupt priority level and
|
||||
// the EVBA-relative interrupt vector offset.
|
||||
PUBLIC ipr_val
|
||||
ipr_val:
|
||||
DC32 (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
|
||||
(INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
|
||||
(INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
|
||||
(INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,370 @@
|
||||
/*This file has been prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief FreeRTOS port source for AVR32 UC3.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32
|
||||
* - Supported devices: All AVR32 devices can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* Get rid of inline in task.h. */
|
||||
#include "task.h"
|
||||
|
||||
/* AVR32 UC3 includes. */
|
||||
#include <avr32/iouc3a0512.h>
|
||||
#include <intrinsics.h>
|
||||
#include "gpio.h"
|
||||
|
||||
#if configDBG
|
||||
#include "usart.h"
|
||||
#endif
|
||||
|
||||
#if( configTICK_USE_TC==1 )
|
||||
#include "tc.h"
|
||||
#endif
|
||||
|
||||
|
||||
/* Constants required to setup the task context. */
|
||||
#define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
|
||||
#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
|
||||
|
||||
/* Each task maintains its own critical nesting variable. */
|
||||
#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
|
||||
volatile unsigned portLONG ulCriticalNesting = 9999UL;
|
||||
|
||||
#if( configTICK_USE_TC==0 )
|
||||
static void prvScheduleNextTick( void );
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Low-level initialization routine called during startup, before the main
|
||||
* function.
|
||||
*/
|
||||
int __low_level_init(void)
|
||||
{
|
||||
#if configHEAP_INIT
|
||||
#pragma segment = "HEAP"
|
||||
portBASE_TYPE *pxMem;
|
||||
#endif
|
||||
|
||||
/* Enable exceptions. */
|
||||
ENABLE_ALL_EXCEPTIONS();
|
||||
|
||||
/* Initialize interrupt handling. */
|
||||
INTC_init_interrupts();
|
||||
|
||||
#if configHEAP_INIT
|
||||
{
|
||||
/* Initialize the heap used by malloc. */
|
||||
for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); )
|
||||
{
|
||||
*pxMem++ = 0xA5A5A5A5;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Code section present if and only if the debug trace is activated. */
|
||||
#if configDBG
|
||||
{
|
||||
static const usart_options_t usart_opt =
|
||||
{
|
||||
.baudrate = configDBG_USART_BAUDRATE,
|
||||
.charlength = 8,
|
||||
.paritytype = USART_NO_PARITY,
|
||||
.stopbits = USART_1_STOPBIT,
|
||||
.channelmode = USART_MODE_NORMAL
|
||||
};
|
||||
|
||||
/* Initialize the USART used for the debug trace with the configured parameters. */
|
||||
extern volatile avr32_usart_t *volatile stdio_usart_base;
|
||||
stdio_usart_base = configDBG_USART;
|
||||
gpio_enable_module_pin(configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION);
|
||||
gpio_enable_module_pin(configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION);
|
||||
usart_init_rs232(configDBG_USART, &usart_opt, configCPU_CLOCK_HZ);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Request initialization of data segments. */
|
||||
return 1;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Added as there is no such function in FreeRTOS. */
|
||||
void *pvPortRealloc( void *pv, size_t xWantedSize )
|
||||
{
|
||||
void *pvReturn;
|
||||
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
pvReturn = realloc( pv, xWantedSize );
|
||||
}
|
||||
xTaskResumeAll();
|
||||
|
||||
return pvReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The cooperative scheduler requires a normal IRQ service routine to
|
||||
simply increment the system tick. */
|
||||
/* The preemptive scheduler is defined as "naked" as the full context is saved
|
||||
on entry as part of the context switch. */
|
||||
#pragma shadow_registers = full // Naked.
|
||||
static void vTick( void )
|
||||
{
|
||||
/* Save the context of the interrupted task. */
|
||||
portSAVE_CONTEXT_OS_INT();
|
||||
|
||||
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
|
||||
clock cycles from now. */
|
||||
#if( configTICK_USE_TC==1 )
|
||||
/* Clear the interrupt flag. */
|
||||
AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
|
||||
#else
|
||||
prvScheduleNextTick();
|
||||
#endif
|
||||
|
||||
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
|
||||
calls in a critical section . */
|
||||
portENTER_CRITICAL();
|
||||
vTaskIncrementTick();
|
||||
portEXIT_CRITICAL();
|
||||
|
||||
/* Restore the context of the "elected task". */
|
||||
portRESTORE_CONTEXT_OS_INT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#pragma shadow_registers = full // Naked.
|
||||
void SCALLYield( void )
|
||||
{
|
||||
/* Save the context of the interrupted task. */
|
||||
portSAVE_CONTEXT_SCALL();
|
||||
vTaskSwitchContext();
|
||||
portRESTORE_CONTEXT_SCALL();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The code generated by the GCC compiler uses the stack in different ways at
|
||||
different optimisation levels. The interrupt flags can therefore not always
|
||||
be saved to the stack. Instead the critical section nesting level is stored
|
||||
in a variable, which is then saved as part of the stack context. */
|
||||
void vPortEnterCritical( void )
|
||||
{
|
||||
/* Disable interrupts */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Now interrupts are disabled ulCriticalNesting can be accessed
|
||||
directly. Increment ulCriticalNesting to keep a count of how many times
|
||||
portENTER_CRITICAL() has been called. */
|
||||
ulCriticalNesting++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExitCritical( void )
|
||||
{
|
||||
if(ulCriticalNesting > portNO_CRITICAL_NESTING)
|
||||
{
|
||||
ulCriticalNesting--;
|
||||
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Enable all interrupt/exception. */
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Setup the timer to generate the tick interrupts. */
|
||||
static void prvSetupTimerInterrupt( void );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Initialise the stack of a task to look exactly as if a call to
|
||||
* portSAVE_CONTEXT had been called.
|
||||
*
|
||||
* See header file for description.
|
||||
*/
|
||||
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
|
||||
{
|
||||
/* Setup the initial stack of the task. The stack is set exactly as
|
||||
expected by the portRESTORE_CONTEXT() macro. */
|
||||
|
||||
/* When the task starts, it will expect to find the function parameter in R12. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
|
||||
*pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
|
||||
*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portBASE_TYPE xPortStartScheduler( void )
|
||||
{
|
||||
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
||||
here already. */
|
||||
prvSetupTimerInterrupt();
|
||||
|
||||
/* Start the first task. */
|
||||
portRESTORE_CONTEXT();
|
||||
|
||||
/* Should not get here! */
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* It is unlikely that the AVR32 port will require this function as there
|
||||
is nothing to return to. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
|
||||
clock cycles from now. */
|
||||
#if( configTICK_USE_TC==0 )
|
||||
static void prvScheduleNextTick(void)
|
||||
{
|
||||
unsigned long lCountVal, lCompareVal;
|
||||
|
||||
lCountVal = Get_system_register(AVR32_COUNT);
|
||||
lCompareVal = lCountVal + (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
|
||||
Set_system_register(AVR32_COMPARE, lCompareVal);
|
||||
}
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Setup the timer to generate the tick interrupts. */
|
||||
static void prvSetupTimerInterrupt(void)
|
||||
{
|
||||
#if( configTICK_USE_TC==1 )
|
||||
|
||||
volatile avr32_tc_t *tc = &AVR32_TC;
|
||||
|
||||
// Options for waveform genration.
|
||||
tc_waveform_opt_t waveform_opt =
|
||||
{
|
||||
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
|
||||
|
||||
.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
|
||||
.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
|
||||
.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
|
||||
.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
|
||||
|
||||
.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
|
||||
.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
|
||||
.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
|
||||
.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
|
||||
|
||||
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
|
||||
.enetrg = FALSE, /* External event trigger enable. */
|
||||
.eevt = 0, /* External event selection. */
|
||||
.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
|
||||
.cpcdis = FALSE, /* Counter disable when RC compare. */
|
||||
.cpcstop = FALSE, /* Counter clock stopped with RC compare. */
|
||||
|
||||
.burst = FALSE, /* Burst signal selection. */
|
||||
.clki = FALSE, /* Clock inversion. */
|
||||
.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
|
||||
};
|
||||
|
||||
tc_interrupt_t tc_interrupt =
|
||||
{
|
||||
.etrgs=0,
|
||||
.ldrbs=0,
|
||||
.ldras=0,
|
||||
.cpcs =1,
|
||||
.cpbs =0,
|
||||
.cpas =0,
|
||||
.lovrs=0,
|
||||
.covfs=0,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* Disable all interrupt/exception. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Register the compare interrupt handler to the interrupt controller and
|
||||
enable the compare interrupt. */
|
||||
|
||||
#if( configTICK_USE_TC==1 )
|
||||
{
|
||||
INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
|
||||
|
||||
/* Initialize the timer/counter. */
|
||||
tc_init_waveform(tc, &waveform_opt);
|
||||
|
||||
/* Set the compare triggers.
|
||||
Remember TC counter is 16-bits, so counting second is not possible!
|
||||
That's why we configure it to count ms. */
|
||||
tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / 1000 );
|
||||
|
||||
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
|
||||
|
||||
/* Start the timer/counter. */
|
||||
tc_start(tc, configTICK_TC_CHANNEL);
|
||||
}
|
||||
#else
|
||||
{
|
||||
INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
|
||||
prvScheduleNextTick();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -0,0 +1,648 @@
|
||||
/*This file has been prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief FreeRTOS port header for AVR32 UC3.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32
|
||||
* - Supported devices: All AVR32 devices can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
#include <avr32/iouc3a0512.h>
|
||||
#include "intc.h"
|
||||
#include "compiler.h"
|
||||
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE unsigned portLONG
|
||||
#define portBASE_TYPE portLONG
|
||||
|
||||
#define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
|
||||
#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
|
||||
#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
|
||||
|
||||
#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef unsigned portSHORT portTickType;
|
||||
#define portMAX_DELAY ( portTickType ) 0xffff
|
||||
#else
|
||||
typedef unsigned portLONG portTickType;
|
||||
#define portMAX_DELAY ( portTickType ) 0xffffffff
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 4
|
||||
#define portNOP() {__asm__ __volatile__ ("nop");}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* INTC-specific. */
|
||||
#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
|
||||
#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
|
||||
|
||||
#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
|
||||
#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
|
||||
|
||||
#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
|
||||
#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
|
||||
|
||||
|
||||
/*
|
||||
* Debug trace.
|
||||
* Activated if and only if configDBG is nonzero.
|
||||
* Prints a formatted string to stdout.
|
||||
* The current source file name and line number are output with a colon before
|
||||
* the formatted string.
|
||||
* A carriage return and a linefeed are appended to the output.
|
||||
* stdout is redirected by Newlib to the USART configured by configDBG_USART.
|
||||
* The parameters are the same as for the standard printf function.
|
||||
* There is no return value.
|
||||
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
|
||||
* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
|
||||
*/
|
||||
#if configDBG
|
||||
#define portDBG_TRACE(...) \
|
||||
{ \
|
||||
fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
|
||||
printf(__VA_ARGS__); \
|
||||
fputs("\r\n", stdout); \
|
||||
}
|
||||
#else
|
||||
#define portDBG_TRACE(...)
|
||||
#endif
|
||||
|
||||
|
||||
/* Critical section management. */
|
||||
#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
|
||||
#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
|
||||
|
||||
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
|
||||
#define portENTER_CRITICAL() vPortEnterCritical();
|
||||
#define portEXIT_CRITICAL() vPortExitCritical();
|
||||
|
||||
|
||||
/* Added as there is no such function in FreeRTOS. */
|
||||
extern void *pvPortRealloc( void *pv, size_t xSize );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/*=============================================================================================*/
|
||||
|
||||
/*
|
||||
* Restore Context for cases other than INTi.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0] \n\t"\
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
/* R0-R7 should not be used below this line */ \
|
||||
/* Skip PC and SR (will do it at the end) */ \
|
||||
"sub sp, -2*4 \n\t"\
|
||||
/* Restore R8..R12 and LR */ \
|
||||
"ldm sp++, r8-r12, lr \n\t"\
|
||||
/* Restore SR */ \
|
||||
"ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
|
||||
"mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
|
||||
/* Restore r0 */ \
|
||||
"ld.w r0, sp[-9*4] \n\t"\
|
||||
/* Restore PC */ \
|
||||
"ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
|
||||
); \
|
||||
\
|
||||
/* Force import of global symbols from assembly */ \
|
||||
ulCriticalNesting; \
|
||||
pxCurrentTCB; \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
|
||||
* portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
|
||||
*
|
||||
* Had to make different versions because registers saved on the system stack
|
||||
* are not the same between INT0..3 exceptions and the scall exception.
|
||||
*/
|
||||
|
||||
// Task context stack layout:
|
||||
// R8 (*)
|
||||
// R9 (*)
|
||||
// R10 (*)
|
||||
// R11 (*)
|
||||
// R12 (*)
|
||||
// R14/LR (*)
|
||||
// R15/PC (*)
|
||||
// SR (*)
|
||||
// R0
|
||||
// R1
|
||||
// R2
|
||||
// R3
|
||||
// R4
|
||||
// R5
|
||||
// R6
|
||||
// R7
|
||||
// ulCriticalNesting
|
||||
// (*) automatically done for INT0..INT3, but not for SCALL
|
||||
|
||||
/*
|
||||
* The ISR used for the scheduler tick depends on whether the cooperative or
|
||||
* the preemptive scheduler is being used.
|
||||
*/
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
||||
*/
|
||||
#define portSAVE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
/* Save R0..R7 */ \
|
||||
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context save. */ \
|
||||
}
|
||||
|
||||
/*
|
||||
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context restore. */ \
|
||||
"rete" \
|
||||
); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
||||
*/
|
||||
#define portSAVE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* When we come here */ \
|
||||
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0 \n\t"\
|
||||
\
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
||||
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
||||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
||||
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
|
||||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
/* NOTE: we don't enter a critical section here because all interrupt handlers */ \
|
||||
/* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
|
||||
/* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
|
||||
/* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w r0[0], sp \n"\
|
||||
\
|
||||
"LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
|
||||
); \
|
||||
}
|
||||
|
||||
/*
|
||||
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT_OS_INT() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
||||
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
||||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
|
||||
); \
|
||||
\
|
||||
/* Else */ \
|
||||
/* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
|
||||
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
|
||||
portENTER_CRITICAL(); \
|
||||
vTaskSwitchContext(); \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0] \n"\
|
||||
\
|
||||
"LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
||||
"rete" \
|
||||
); \
|
||||
\
|
||||
/* Force import of global symbols from assembly */ \
|
||||
ulCriticalNesting; \
|
||||
pxCurrentTCB; \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
|
||||
*
|
||||
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
|
||||
*
|
||||
*/
|
||||
#define portSAVE_CONTEXT_SCALL() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
|
||||
/* If SR[M2:M0] == 001 */ \
|
||||
/* PC and SR are on the stack. */ \
|
||||
/* Else (other modes) */ \
|
||||
/* Nothing on the stack. */ \
|
||||
\
|
||||
/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
|
||||
/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
|
||||
/* in an interrupt|exception handler. */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* in order to save R0-R7 */ \
|
||||
"sub sp, 6*4 \n\t"\
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* in order to save R8-R12 and LR */ \
|
||||
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
||||
"sub r7, sp,-16*4 \n\t"\
|
||||
/* Copy PC and SR in other places in the stack. */ \
|
||||
"ld.w r0, r7[-2*4] \n\t" /* Read SR */\
|
||||
"st.w r7[-8*4], r0 \n\t" /* Copy SR */\
|
||||
"ld.w r0, r7[-1*4] \n\t" /* Read PC */\
|
||||
"st.w r7[-7*4], r0 \n\t" /* Copy PC */\
|
||||
\
|
||||
/* Save R8..R12 and LR on the stack. */ \
|
||||
"stm --r7, r8-r12, lr \n\t"\
|
||||
\
|
||||
/* Arriving here we have the following stack organizations: */ \
|
||||
/* R8..R12, LR, PC, SR, R0..R7. */ \
|
||||
\
|
||||
/* Now we can finalize the save. */ \
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0" \
|
||||
); \
|
||||
\
|
||||
/* Disable the its which may cause a context switch (i.e. cause a change of */ \
|
||||
/* pxCurrentTCB). */ \
|
||||
/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
|
||||
/* critical section because it is a global structure. */ \
|
||||
portENTER_CRITICAL(); \
|
||||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w r0[0], sp" \
|
||||
); \
|
||||
}
|
||||
|
||||
/*
|
||||
* portRESTORE_CONTEXT() for SupervisorCALL exception.
|
||||
*/
|
||||
#define portRESTORE_CONTEXT_SCALL() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
__asm__ __volatile__ ( \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0]" \
|
||||
); \
|
||||
\
|
||||
/* Leave pxCurrentTCB variable access critical section */ \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* skip PC and SR */ \
|
||||
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
||||
"sub r7, sp, -10*4 \n\t"\
|
||||
/* Restore r8-r12 and LR */ \
|
||||
"ldm r7++, r8-r12, lr \n\t"\
|
||||
\
|
||||
/* RETS will take care of the extra PC and SR restore. */ \
|
||||
/* So, we have to prepare the stack for this. */ \
|
||||
"ld.w r0, r7[-8*4] \n\t" /* Read SR */\
|
||||
"st.w r7[-2*4], r0 \n\t" /* Copy SR */\
|
||||
"ld.w r0, r7[-7*4] \n\t" /* Read PC */\
|
||||
"st.w r7[-1*4], r0 \n\t" /* Copy PC */\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
"sub sp, -6*4 \n\t"\
|
||||
\
|
||||
"rets" \
|
||||
); \
|
||||
\
|
||||
/* Force import of global symbols from assembly */ \
|
||||
ulCriticalNesting; \
|
||||
pxCurrentTCB; \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* The ISR used depends on whether the cooperative or
|
||||
* the preemptive scheduler is being used.
|
||||
*/
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
||||
/*
|
||||
* ISR entry and exit macros. These are only required if a task switch
|
||||
* is required from the ISR.
|
||||
*/
|
||||
#define portENTER_SWITCHING_ISR() \
|
||||
{ \
|
||||
/* Save R0..R7 */ \
|
||||
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context save. */ \
|
||||
}
|
||||
|
||||
/*
|
||||
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
||||
*/
|
||||
#define portEXIT_SWITCHING_ISR() \
|
||||
{ \
|
||||
__asm__ __volatile__ ( \
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
||||
/* there is also no context restore. */ \
|
||||
"rete" \
|
||||
); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* ISR entry and exit macros. These are only required if a task switch
|
||||
* is required from the ISR.
|
||||
*/
|
||||
#define portENTER_SWITCHING_ISR() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
/* When we come here */ \
|
||||
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Save R0..R7 */ \
|
||||
"stm --sp, r0-r7 \n\t"\
|
||||
\
|
||||
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w --sp, r0 \n\t"\
|
||||
\
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
||||
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
||||
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
||||
/* will just be restoring the interrupt handler, no way!!! */ \
|
||||
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
||||
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
|
||||
\
|
||||
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"st.w r0[0], sp \n"\
|
||||
\
|
||||
"LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
|
||||
); \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
||||
*/
|
||||
#define portEXIT_SWITCHING_ISR() \
|
||||
{ \
|
||||
extern volatile unsigned portLONG ulCriticalNesting; \
|
||||
extern volatile void *volatile pxCurrentTCB; \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
||||
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
||||
/* level and allow other lower interrupt level to occur). */ \
|
||||
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
|
||||
/* did not previously save SP in its TCB. */ \
|
||||
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
||||
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
||||
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
||||
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
|
||||
\
|
||||
/* If a switch is required then we just need to call */ \
|
||||
/* vTaskSwitchContext() as the context has already been */ \
|
||||
/* saved. */ \
|
||||
"cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
|
||||
"brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
|
||||
); \
|
||||
\
|
||||
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
|
||||
portENTER_CRITICAL(); \
|
||||
vTaskSwitchContext(); \
|
||||
portEXIT_CRITICAL(); \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
"LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
|
||||
/* Restore the context of which ever task is now the highest */ \
|
||||
/* priority that is ready to run. */ \
|
||||
\
|
||||
/* Restore all registers */ \
|
||||
\
|
||||
/* Set SP to point to new stack */ \
|
||||
"mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
|
||||
"ld.w r0, r8[0] \n\t"\
|
||||
"ld.w sp, r0[0] \n"\
|
||||
\
|
||||
"LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
|
||||
\
|
||||
/* Restore ulCriticalNesting variable */ \
|
||||
"ld.w r0, sp++ \n\t"\
|
||||
"mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
|
||||
"st.w r8[0], r0 \n\t"\
|
||||
\
|
||||
/* Restore R0..R7 */ \
|
||||
"ldm sp++, r0-r7 \n\t"\
|
||||
\
|
||||
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
||||
"rete" \
|
||||
); \
|
||||
\
|
||||
/* Force import of global symbols from assembly */ \
|
||||
ulCriticalNesting; \
|
||||
pxCurrentTCB; \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define portYIELD() {__asm__ __volatile__ ("scall");}
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
#define inline
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
@ -0,0 +1,95 @@
|
||||
/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
|
||||
|
||||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief System-specific implementation of the \ref __read function used by
|
||||
the standard library.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32
|
||||
* - Supported devices: All AVR32 devices with a USART module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include <yfuns.h>
|
||||
#include <avr32/iouc3a0512.h>
|
||||
#include "usart.h"
|
||||
|
||||
|
||||
_STD_BEGIN
|
||||
|
||||
|
||||
#pragma module_name = "?__read"
|
||||
|
||||
|
||||
extern volatile avr32_usart_t *volatile stdio_usart_base;
|
||||
|
||||
|
||||
/*! \brief Reads a number of bytes, at most \a size, into the memory area
|
||||
* pointed to by \a buffer.
|
||||
*
|
||||
* \param handle File handle to read from.
|
||||
* \param buffer Pointer to buffer to write read bytes to.
|
||||
* \param size Number of bytes to read.
|
||||
*
|
||||
* \return The number of bytes read, \c 0 at the end of the file, or
|
||||
* \c _LLIO_ERROR on failure.
|
||||
*/
|
||||
size_t __read(int handle, unsigned char *buffer, size_t size)
|
||||
{
|
||||
int nChars = 0;
|
||||
|
||||
// This implementation only reads from stdin.
|
||||
// For all other file handles, it returns failure.
|
||||
if (handle != _LLIO_STDIN)
|
||||
{
|
||||
return _LLIO_ERROR;
|
||||
}
|
||||
|
||||
for (; size > 0; --size)
|
||||
{
|
||||
int c = usart_getchar(stdio_usart_base);
|
||||
if (c < 0)
|
||||
break;
|
||||
|
||||
*buffer++ = c;
|
||||
++nChars;
|
||||
}
|
||||
|
||||
return nChars;
|
||||
}
|
||||
|
||||
|
||||
_STD_END
|
||||
@ -0,0 +1,105 @@
|
||||
/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
|
||||
|
||||
/*This file is prepared for Doxygen automatic documentation generation.*/
|
||||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief System-specific implementation of the \ref __write function used by
|
||||
the standard library.
|
||||
*
|
||||
* - Compiler: IAR EWAVR32
|
||||
* - Supported devices: All AVR32 devices with a USART module can be used.
|
||||
* - AppNote:
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
* Support email: avr32@atmel.com
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of ATMEL may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
|
||||
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include <yfuns.h>
|
||||
#include <avr32/iouc3a0512.h>
|
||||
#include "usart.h"
|
||||
|
||||
|
||||
_STD_BEGIN
|
||||
|
||||
|
||||
#pragma module_name = "?__write"
|
||||
|
||||
|
||||
//! Pointer to the base of the USART module instance to use for stdio.
|
||||
__no_init volatile avr32_usart_t *volatile stdio_usart_base;
|
||||
|
||||
|
||||
/*! \brief Writes a number of bytes, at most \a size, from the memory area
|
||||
* pointed to by \a buffer.
|
||||
*
|
||||
* If \a buffer is zero then \ref __write performs flushing of internal buffers,
|
||||
* if any. In this case, \a handle can be \c -1 to indicate that all handles
|
||||
* should be flushed.
|
||||
*
|
||||
* \param handle File handle to write to.
|
||||
* \param buffer Pointer to buffer to read bytes to write from.
|
||||
* \param size Number of bytes to write.
|
||||
*
|
||||
* \return The number of bytes written, or \c _LLIO_ERROR on failure.
|
||||
*/
|
||||
size_t __write(int handle, const unsigned char *buffer, size_t size)
|
||||
{
|
||||
size_t nChars = 0;
|
||||
|
||||
if (buffer == 0)
|
||||
{
|
||||
// This means that we should flush internal buffers.
|
||||
return 0;
|
||||
}
|
||||
|
||||
// This implementation only writes to stdout and stderr.
|
||||
// For all other file handles, it returns failure.
|
||||
if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
|
||||
{
|
||||
return _LLIO_ERROR;
|
||||
}
|
||||
|
||||
for (; size != 0; --size)
|
||||
{
|
||||
if (usart_putchar(stdio_usart_base, *buffer++) < 0)
|
||||
{
|
||||
return _LLIO_ERROR;
|
||||
}
|
||||
|
||||
++nChars;
|
||||
}
|
||||
|
||||
return nChars;
|
||||
}
|
||||
|
||||
|
||||
_STD_END
|
||||
Loading…
Reference in New Issue