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512 lines
14 KiB
ArmAsm
512 lines
14 KiB
ArmAsm
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/* If user disable the ASM, such as avoiding bugs in ASM, donot compile it. */
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#if !defined(MD_ST_NO_ASM)
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/*
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* Portions created by SGI are Copyright (C) 2000 Silicon Graphics, Inc.
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* All Rights Reserved.
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*/
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#if defined(__ia64__)
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/****************************************************************/
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/*
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* The internal __jmp_buf layout is different from one used
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* by setjmp()/longjmp().
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*
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* Offset Description
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* ------ -----------
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* 0x000 stack pointer (r12)
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* 0x008 gp (r1)
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* 0x010 caller's unat
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* 0x018 fpsr
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* 0x020 r4
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* 0x028 r5
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* 0x030 r6
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* 0x038 r7
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* 0x040 rp (b0)
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* 0x048 b1
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* 0x050 b2
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* 0x058 b3
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* 0x060 b4
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* 0x068 b5
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* 0x070 ar.pfs
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* 0x078 ar.lc
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* 0x080 pr
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* 0x088 ar.bsp
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* 0x090 ar.unat
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* 0x098 &__jmp_buf
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* 0x0a0 ar.rsc
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* 0x0a8 ar.rnat
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* 0x0b0 f2
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* 0x0c0 f3
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* 0x0d0 f4
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* 0x0e0 f5
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* 0x0f0 f16
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* 0x100 f17
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* 0x110 f18
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* 0x120 f19
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* 0x130 f20
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* 0x130 f21
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* 0x140 f22
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* 0x150 f23
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* 0x160 f24
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* 0x170 f25
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* 0x180 f26
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* 0x190 f27
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* 0x1a0 f28
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* 0x1b0 f29
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* 0x1c0 f30
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* 0x1d0 f31
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*
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* Note that the address of __jmp_buf is saved but not used: we assume
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* that the jmp_buf data structure is never moved around in memory.
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*/
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/*
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* Implemented according to "IA-64 Software Conventions and Runtime
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* Architecture Guide", Chapter 10: "Context Management".
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*/
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.text
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.psr abi64
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.psr lsb
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.lsb
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/* _st_md_cxt_save(__jmp_buf env) */
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.align 32
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.global _st_md_cxt_save
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.proc _st_md_cxt_save
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_st_md_cxt_save:
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alloc r14 = ar.pfs,1,0,0,0
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mov r16 = ar.unat
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;;
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mov r17 = ar.fpsr
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mov r2 = in0
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add r3 = 8,in0
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;;
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st8.spill.nta [r2] = sp,16 // r12 (sp)
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;;
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st8.spill.nta [r3] = gp,16 // r1 (gp)
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;;
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st8.nta [r2] = r16,16 // save caller's unat
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st8.nta [r3] = r17,16 // save fpsr
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add r8 = 0xb0,in0
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;;
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st8.spill.nta [r2] = r4,16 // r4
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;;
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st8.spill.nta [r3] = r5,16 // r5
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add r9 = 0xc0,in0
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;;
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stf.spill.nta [r8] = f2,32
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stf.spill.nta [r9] = f3,32
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mov r15 = rp
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;;
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stf.spill.nta [r8] = f4,32
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stf.spill.nta [r9] = f5,32
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mov r17 = b1
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;;
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stf.spill.nta [r8] = f16,32
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stf.spill.nta [r9] = f17,32
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mov r18 = b2
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;;
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stf.spill.nta [r8] = f18,32
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stf.spill.nta [r9] = f19,32
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mov r19 = b3
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;;
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stf.spill.nta [r8] = f20,32
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stf.spill.nta [r9] = f21,32
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mov r20 = b4
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;;
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stf.spill.nta [r8] = f22,32
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stf.spill.nta [r9] = f23,32
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mov r21 = b5
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;;
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stf.spill.nta [r8] = f24,32
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stf.spill.nta [r9] = f25,32
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mov r22 = ar.lc
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;;
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stf.spill.nta [r8] = f26,32
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stf.spill.nta [r9] = f27,32
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mov r24 = pr
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;;
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stf.spill.nta [r8] = f28,32
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stf.spill.nta [r9] = f29,32
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;;
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stf.spill.nta [r8] = f30
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stf.spill.nta [r9] = f31
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st8.spill.nta [r2] = r6,16 // r6
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;;
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st8.spill.nta [r3] = r7,16 // r7
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;;
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mov r23 = ar.bsp
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mov r25 = ar.unat
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st8.nta [r2] = r15,16 // b0
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st8.nta [r3] = r17,16 // b1
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;;
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st8.nta [r2] = r18,16 // b2
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st8.nta [r3] = r19,16 // b3
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mov r26 = ar.rsc
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;;
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st8.nta [r2] = r20,16 // b4
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st8.nta [r3] = r21,16 // b5
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;;
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st8.nta [r2] = r14,16 // ar.pfs
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st8.nta [r3] = r22,16 // ar.lc
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;;
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st8.nta [r2] = r24,16 // pr
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st8.nta [r3] = r23,16 // ar.bsp
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;;
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st8.nta [r2] = r25,16 // ar.unat
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st8.nta [r3] = in0,16 // &__jmp_buf (just in case)
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;;
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st8.nta [r2] = r26 // ar.rsc
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;;
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flushrs // flush dirty regs to backing store
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;;
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and r27 = ~0x3,r26 // clear ar.rsc.mode
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;;
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mov ar.rsc = r27 // put RSE in enforced lazy mode
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;;
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mov r28 = ar.rnat
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;;
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st8.nta [r3] = r28 // ar.rnat
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mov ar.rsc = r26 // restore ar.rsc
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;;
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mov r8 = 0
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br.ret.sptk.few b0
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.endp _st_md_cxt_save
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/****************************************************************/
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/* _st_md_cxt_restore(__jmp_buf env, int val) */
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.global _st_md_cxt_restore
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.proc _st_md_cxt_restore
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_st_md_cxt_restore:
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alloc r8 = ar.pfs,2,0,0,0
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add r2 = 0x88,in0 // r2 <- &jmpbuf.ar_bsp
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mov r16 = ar.rsc
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;;
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flushrs // flush dirty regs to backing store
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;;
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and r17 = ~0x3,r16 // clear ar.rsc.mode
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;;
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mov ar.rsc = r17 // put RSE in enforced lazy mode
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;;
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invala // invalidate the ALAT
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;;
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ld8 r23 = [r2],8 // r23 <- jmpbuf.ar_bsp
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;;
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mov ar.bspstore = r23 // write BSPSTORE
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ld8 r25 = [r2],24 // r25 <- jmpbuf.ar_unat
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;;
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ld8 r26 = [r2],-8 // r26 <- jmpbuf.ar_rnat
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;;
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mov ar.rnat = r26 // write RNAT
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ld8 r27 = [r2] // r27 <- jmpbuf.ar_rsc
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;;
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mov ar.rsc = r27 // write RSE control
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mov r2 = in0
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;;
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mov ar.unat = r25 // write ar.unat
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add r3 = 8,in0
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;;
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ld8.fill.nta sp = [r2],16 // r12 (sp)
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ld8.fill.nta gp = [r3],16 // r1 (gp)
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;;
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ld8.nta r16 = [r2],16 // caller's unat
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ld8.nta r17 = [r3],16 // fpsr
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;;
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ld8.fill.nta r4 = [r2],16 // r4
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ld8.fill.nta r5 = [r3],16 // r5
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;;
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ld8.fill.nta r6 = [r2],16 // r6
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ld8.fill.nta r7 = [r3],16 // r7
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;;
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mov ar.unat = r16 // restore caller's unat
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mov ar.fpsr = r17 // restore fpsr
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;;
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ld8.nta r16 = [r2],16 // b0
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ld8.nta r17 = [r3],16 // b1
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;;
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ld8.nta r18 = [r2],16 // b2
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ld8.nta r19 = [r3],16 // b3
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;;
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ld8.nta r20 = [r2],16 // b4
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ld8.nta r21 = [r3],16 // b5
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;;
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ld8.nta r11 = [r2],16 // ar.pfs
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ld8.nta r22 = [r3],72 // ar.lc
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;;
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ld8.nta r24 = [r2],48 // pr
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mov b0 = r16
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;;
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ldf.fill.nta f2 = [r2],32
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ldf.fill.nta f3 = [r3],32
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mov b1 = r17
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;;
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ldf.fill.nta f4 = [r2],32
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ldf.fill.nta f5 = [r3],32
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mov b2 = r18
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;;
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ldf.fill.nta f16 = [r2],32
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ldf.fill.nta f17 = [r3],32
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mov b3 = r19
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;;
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ldf.fill.nta f18 = [r2],32
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ldf.fill.nta f19 = [r3],32
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mov b4 = r20
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;;
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ldf.fill.nta f20 = [r2],32
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ldf.fill.nta f21 = [r3],32
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mov b5 = r21
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;;
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ldf.fill.nta f22 = [r2],32
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ldf.fill.nta f23 = [r3],32
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mov ar.lc = r22
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;;
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ldf.fill.nta f24 = [r2],32
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ldf.fill.nta f25 = [r3],32
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cmp.eq p6,p7 = 0,in1
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;;
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ldf.fill.nta f26 = [r2],32
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ldf.fill.nta f27 = [r3],32
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mov ar.pfs = r11
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;;
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ldf.fill.nta f28 = [r2],32
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ldf.fill.nta f29 = [r3],32
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;;
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ldf.fill.nta f30 = [r2]
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ldf.fill.nta f31 = [r3]
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(p6) mov r8 = 1
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(p7) mov r8 = in1
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mov pr = r24,-1
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br.ret.sptk.few b0
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.endp _st_md_cxt_restore
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/****************************************************************/
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#elif defined(__i386__)
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/****************************************************************/
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/*
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* Internal __jmp_buf layout
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*/
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#define JB_BX 0
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#define JB_SI 1
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#define JB_DI 2
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#define JB_BP 3
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#define JB_SP 4
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#define JB_PC 5
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.file "md.S"
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.text
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/* _st_md_cxt_save(__jmp_buf env) */
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.globl _st_md_cxt_save
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.type _st_md_cxt_save, @function
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.align 16
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_st_md_cxt_save:
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movl 4(%esp), %eax
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/*
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* Save registers.
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*/
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movl %ebx, (JB_BX*4)(%eax)
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movl %esi, (JB_SI*4)(%eax)
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movl %edi, (JB_DI*4)(%eax)
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/* Save SP */
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leal 4(%esp), %ecx
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movl %ecx, (JB_SP*4)(%eax)
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/* Save PC we are returning to */
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movl 0(%esp), %ecx
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movl %ecx, (JB_PC*4)(%eax)
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/* Save caller frame pointer */
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movl %ebp, (JB_BP*4)(%eax)
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xorl %eax, %eax
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ret
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.size _st_md_cxt_save, .-_st_md_cxt_save
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/****************************************************************/
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/* _st_md_cxt_restore(__jmp_buf env, int val) */
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.globl _st_md_cxt_restore
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.type _st_md_cxt_restore, @function
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.align 16
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_st_md_cxt_restore:
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/* First argument is jmp_buf */
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movl 4(%esp), %ecx
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/* Second argument is return value */
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movl 8(%esp), %eax
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/* Set the return address */
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movl (JB_PC*4)(%ecx), %edx
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/*
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* Restore registers.
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*/
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movl (JB_BX*4)(%ecx), %ebx
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movl (JB_SI*4)(%ecx), %esi
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movl (JB_DI*4)(%ecx), %edi
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movl (JB_BP*4)(%ecx), %ebp
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movl (JB_SP*4)(%ecx), %esp
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testl %eax, %eax
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jnz 1f
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incl %eax
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/* Jump to saved PC */
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1: jmp *%edx
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.size _st_md_cxt_restore, .-_st_md_cxt_restore
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/****************************************************************/
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#elif defined(__amd64__) || defined(__x86_64__)
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/****************************************************************/
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/*
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* Internal __jmp_buf layout
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*/
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#define JB_RBX 0
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#define JB_RBP 1
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#define JB_R12 2
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#define JB_R13 3
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#define JB_R14 4
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#define JB_R15 5
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#define JB_RSP 6
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#define JB_PC 7
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.file "md.S"
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.text
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/* _st_md_cxt_save(__jmp_buf env) */
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.globl _st_md_cxt_save
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.type _st_md_cxt_save, @function
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.align 16
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_st_md_cxt_save:
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/*
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* Save registers.
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*/
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movq %rbx, (JB_RBX*8)(%rdi)
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movq %rbp, (JB_RBP*8)(%rdi)
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movq %r12, (JB_R12*8)(%rdi)
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movq %r13, (JB_R13*8)(%rdi)
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movq %r14, (JB_R14*8)(%rdi)
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movq %r15, (JB_R15*8)(%rdi)
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/* Save SP */
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leaq 8(%rsp), %rdx
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movq %rdx, (JB_RSP*8)(%rdi)
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/* Save PC we are returning to */
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movq (%rsp), %rax
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movq %rax, (JB_PC*8)(%rdi)
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xorq %rax, %rax
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ret
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.size _st_md_cxt_save, .-_st_md_cxt_save
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/****************************************************************/
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/* _st_md_cxt_restore(__jmp_buf env, int val) */
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.globl _st_md_cxt_restore
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.type _st_md_cxt_restore, @function
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.align 16
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_st_md_cxt_restore:
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/*
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* Restore registers.
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*/
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movq (JB_RBX*8)(%rdi), %rbx
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movq (JB_RBP*8)(%rdi), %rbp
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movq (JB_R12*8)(%rdi), %r12
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movq (JB_R13*8)(%rdi), %r13
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movq (JB_R14*8)(%rdi), %r14
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movq (JB_R15*8)(%rdi), %r15
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/* Set return value */
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test %esi, %esi
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mov $01, %eax
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cmove %eax, %esi
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mov %esi, %eax
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movq (JB_PC*8)(%rdi), %rdx
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movq (JB_RSP*8)(%rdi), %rsp
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/* Jump to saved PC */
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jmpq *%rdx
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.size _st_md_cxt_restore, .-_st_md_cxt_restore
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/****************************************************************/
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#elif defined(__arm__)
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/****************************************************************/
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.globl _st_md_cxt_save
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.type _st_md_cxt_save, %function
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.align 2
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_st_md_cxt_save:
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mov ip, r0 // r0 is the param jmpbuf ptr address.
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// Save registers like
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// *ip++ = v1
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// *ip++ = ...
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// *ip++ = v6
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// *ip++ = sl
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// *ip++ = fp
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stmia ip!, {v1-v6, sl, fp} // TODO: compatible with other ARM version.
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movs r2, sp
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stmia ip!, {r2, lr}
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mov r0, #0 // r0 save the return value(0) of setjmp.
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bx lr // return
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.size _st_md_cxt_save, .-_st_md_cxt_save
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/****************************************************************/
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.globl _st_md_cxt_restore
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.type _st_md_cxt_restore, %function
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.align 2
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_st_md_cxt_restore:
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mov ip, r0 // r0 -> jmp_buf
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movs r0, r1 // r1 -> return value
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// The bellow is a group, that is:
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// if (r0 == 0) r0 =1;
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ITT eq
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moveq r0, #1 // long_jmp should never return 0
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ldmia ip!, {v1-v6, sl, fp} // restore registers.
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ldr sp, [ip], #4 // restore sp, like: sp=*ip; ip+=4;
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ldr lr, [ip], #4
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bx lr
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.size _st_md_cxt_restore, .-_st_md_cxt_restore
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/****************************************************************/
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#endif
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#endif
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