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243 lines
8.9 KiB
ArmAsm
243 lines
8.9 KiB
ArmAsm
;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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;* File Name : 91x_init.s
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;* Author : MCD Application Team
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;* Date First Issued : 05/18/2006 : Version 1.0
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;* Description : This module performs:
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;* - FLASH/RAM initialization,
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;* - Stack pointer initialization for each mode ,
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;* - Branches to ?main in the C library (which eventually
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;* calls main()).
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;*
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;* On reset, the ARM core starts up in Supervisor (SVC) mode,
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;* in ARM state,with IRQ and FIQ disabled.
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;*******************************************************************************
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;* History:
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;* 05/22/2007 : Version 1.2
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;* 05/24/2006 : Version 1.1
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;* 05/18/2006 : Version 1.0
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;*******************************************************************************
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;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
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;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;******************************************************************************/
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; At power up, the CPU defaults to run on the oscillator clock, so Depending
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; of your Application, Disable or Enable the following Define
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#define PLL_Clock ; Use PLL as the default clock source @ 96 MHz only with
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; Bank 0 @ 0x0 and Bank 1 @ 0x80000
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; #define RTC_Clock ; Use RTC as the default clock source
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; #define OSC_Clock ; Use OSC as the default clock source
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; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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; --- STR9X SCU specific definitions
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SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address
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SCU_CLKCNTR_OFST EQU 0x00000000 ; Clock Control register Offset
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SCU_PLLCONF_OFST EQU 0x00000004 ; PLL Configuration register Offset
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SCU_SYSSTATUS_OFST EQU 0x00000008 ; System Status Register Offset
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SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset
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; --- STR9X FMI specific definitions
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FMI_BASE_Address EQU 0x54000000 ; FMI Base Address
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FMI_BBSR_OFST EQU 0x00000000 ; Boot Bank Size Register
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FMI_NBBSR_OFST EQU 0x00000004 ; Non-boot Bank Size Register
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FMI_BBADR_OFST EQU 0x0000000C ; Boot Bank Base Address Register
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FMI_NBBADR_OFST EQU 0x00000010 ; Non-boot Bank Base Address Register
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FMI_CR_OFST EQU 0x00000018 ; Control Register
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;---------------------------------------------------------------
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; ?program_start
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;---------------------------------------------------------------
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MODULE ?program_start
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .icode:CODE:NOROOT(2)
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PUBLIC __iar_program_start
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EXTERN ?main
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CODE32
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__iar_program_start:
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LDR pc, =NextInst
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NextInst
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NOP ; execute some instructions to access CPU registers after wake
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NOP ; up from Reset, while waiting for OSC stabilization
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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; BUFFERED_Mode
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; ------------------------------------------------------------------------------
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; Description : Enable the Buffered mode.
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; Just enable the buffered define on the 91x_conf.h
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; http://www.arm.com/pdfs/DDI0164A_966E_S.pdf
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; ------------------------------------------------------------------------------
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MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0
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ORR r0, r0, #0x8 ; Enable Write Buffer on AHB
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MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1
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; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
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; when the bank 0 is the boot bank, then enable the Bank 1.
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LDR R6, =FMI_BASE_Address
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LDR R7, = 0x4 ; BOOT BANK Size = 512KB
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STR R7, [R6, #FMI_BBSR_OFST] ; (2^4) * 32 = 512KB
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LDR R7, = 0x2 ; NON BOOT BANK Size = 32KB
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STR R7, [R6, #FMI_NBBSR_OFST] ; (2^2) * 8 = 32KB
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LDR R7, = 0x0 ; BOOT BANK Address = 0x0
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STR R7, [R6, #FMI_BBADR_OFST]
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LDR R7, = 0x20000 ; NON BOOT BANK Address = 0x80000
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STR R7, [R6, #FMI_NBBADR_OFST] ; need to put 0x20000 because FMI
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; bus on A[25:2] of CPU bus
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LDR R7, = 0x18 ; Enable CS on both banks
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STR R7, [R6, #FMI_CR_OFST] ; LDR R7, = 0x19 ;in RevD
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; to enable 8 words PFQ deepth
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; --- Enable 96K RAM, PFQBC enabled, DTCM & AHB wait-states disabled
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LDR R0, = SCU_BASE_Address
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LDR R1, = 0x0191
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STR R1, [R0, #SCU_SCR0_OFST]
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; ------------------------------------------------------------------------------
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; --- System clock configuration
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; ------------------------------------------------------------------------------
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#ifdef PLL_Clock ; Use 96 MHZ PLL clock as the default frequency
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; --- wait states Flash confguration
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LDR R6, = 0x00080000 ;Write a Write Flash Configuration
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LDR R7, =0x60 ;Register command (60h) to any word
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STRH R7, [R6] ;address in Bank 1.
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LDR R6, = 0x00083040 ;Write a Write Flash Configuration
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LDR R7, = 0x3 ;Register Confirm command (03h)
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STRH R7, [R6] ;2Wstaites in read,PWD,LVD enabled,
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;High BUSCFG.
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; --- PLL configuration
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LDR R1, = 0x00020002 ;Set OSC as clock source
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STR R1, [R0, #SCU_CLKCNTR_OFST ]
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NOP ; Wait for OSC stabilization
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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LDR R1, = 0x000ac019 ;Set PLL ENABLE, to 96Mhz
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STR R1, [R0, #SCU_PLLCONF_OFST]
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Wait_Loop
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LDR R1,[R0, #SCU_SYSSTATUS_OFST] ;Wait until PLL is Locked
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ANDS R1, R1, #0x01
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BEQ Wait_Loop
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LDR R1, = 0x00020080 ;Set PLL as clock source after pll
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STR R1, [R0, #SCU_CLKCNTR_OFST ] ;is locked and FMICLK=RCLK,
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;PCLK=RCLK/2
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#endif
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#ifdef RTC_Clock ;Use RTC as the default clock source
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LDR R1, = 0x00020001 ;Set RTC as clock source and
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STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK
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#endif
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#ifdef OSC_Clock ;Use Osc as the default clock source
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LDR R1, = 0x00020002 ;Set OSC as clock source and
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STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK
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#endif
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; --- Initialize Stack pointer registers
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; Enter each mode in turn and set up the stack pointer
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MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
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LDR SP, =SFE(FIQ_STACK)
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MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
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LDR SP, = SFE(IRQ_STACK)
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MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
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LDR SP, = SFE(ABT_STACK)
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MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
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LDR SP, = SFE(UND_STACK)
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MSR CPSR_c, #Mode_SYS ; IRQs & FIQs are now enabled
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LDR SP, = SFE(CSTACK)
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MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
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LDR SP, = SFE(SVC_STACK)
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; --- Set bits 17-18(DTCM/ITCM order bits)of the Core Configuration Control
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; Register
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MOV r0, #0x60000
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MCR p15,0x1,r0,c15,c1,0
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; --- Now enter the C code
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B ?main ; Note : use B not BL, because an application will
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; never return this way
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LTORG
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END
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;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****
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