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334 lines
8.5 KiB
ArmAsm
334 lines
8.5 KiB
ArmAsm
/*
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FreeRTOS.org V4.6.1 - Copyright (C) 2003-2007 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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Also see http://www.SafeRTOS.com a version that has been certified for use
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in safety critical systems, plus commercial licensing, development and
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support options.
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***************************************************************************
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*/
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#include <p32xxxx.h>
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#include <sys/asm.h>
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.set nomips16
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.set noreorder
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.global vRegTest1
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.global vRegTest2
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/* .section .FreeRTOS, ax, @progbits */
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.set noreorder
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.set noat
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.ent vRegTest1
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/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */
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vRegTest1:
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addiu $1, $0, 0x11
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addiu $2, $0, 0x12
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addiu $3, $0, 0x13
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addiu $5, $0, 0x15
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addiu $6, $0, 0x16
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addiu $7, $0, 0x17
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addiu $8, $0, 0x18
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addiu $9, $0, 0x19
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addiu $10, $0, 0x110
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addiu $11, $0, 0x111
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addiu $12, $0, 0x112
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addiu $13, $0, 0x113
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addiu $14, $0, 0x114
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addiu $15, $0, 0x115
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addiu $16, $0, 0x116
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addiu $17, $0, 0x117
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addiu $18, $0, 0x118
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addiu $19, $0, 0x119
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addiu $20, $0, 0x120
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addiu $21, $0, 0x121
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addiu $22, $0, 0x122
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addiu $23, $0, 0x123
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addiu $24, $0, 0x124
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addiu $25, $0, 0x125
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addiu $30, $0, 0x130
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#if configUSE_PREEMPTION == 0
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syscall 0
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#endif
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addiu $1, $1, -0x11
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beq $1, $0, .+12
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nop
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sw $0, 0($4)
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addiu $2, $2, -0x12
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beq $2, $0, .+12
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nop
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sw $0, 0($4)
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addiu $3, $3, -0x13
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beq $3, $0, .+12
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nop
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sw $0, 0($4)
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addiu $5, $5, -0x15
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beq $5, $0, .+12
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nop
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sw $0, 0($4)
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addiu $6, $6, -0x16
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beq $6, $0, .+12
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nop
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sw $0, 0($4)
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addiu $7, $7, -0x17
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beq $7, $0, .+12
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nop
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sw $0, 0($4)
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addiu $8, $8, -0x18
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beq $8, $0, .+12
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nop
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sw $0, 0($4)
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addiu $9, $9, -0x19
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beq $9, $0, .+12
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nop
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sw $0, 0($4)
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addiu $10, $10, -0x110
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beq $10, $0, .+12
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nop
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sw $0, 0($4)
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addiu $11, $11, -0x111
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beq $11, $0, .+12
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nop
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sw $0, 0($4)
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addiu $12, $12, -0x112
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beq $12, $0, .+12
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nop
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sw $0, 0($4)
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addiu $13, $13, -0x113
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beq $13, $0, .+12
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nop
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sw $0, 0($4)
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addiu $14, $14, -0x114
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beq $14, $0, .+12
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nop
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sw $0, 0($4)
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addiu $15, $15, -0x115
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beq $15, $0, .+12
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nop
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sw $0, 0($4)
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addiu $16, $16, -0x116
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beq $16, $0, .+12
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nop
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sw $0, 0($4)
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addiu $17, $17, -0x117
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beq $17, $0, .+12
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nop
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sw $0, 0($4)
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addiu $18, $18, -0x118
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beq $18, $0, .+12
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nop
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sw $0, 0($4)
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addiu $19, $19, -0x119
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beq $19, $0, .+12
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nop
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sw $0, 0($4)
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addiu $20, $20, -0x120
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beq $20, $0, .+12
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nop
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sw $0, 0($4)
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addiu $21, $21, -0x121
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beq $21, $0, .+12
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nop
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sw $0, 0($4)
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addiu $22, $22, -0x122
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beq $22, $0, .+12
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nop
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sw $0, 0($4)
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addiu $23, $23, -0x123
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beq $23, $0, .+12
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nop
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sw $0, 0($4)
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addiu $24, $24, -0x124
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beq $24, $0, .+12
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nop
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sw $0, 0($4)
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addiu $25, $25, -0x125
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beq $25, $0, .+12
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nop
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sw $0, 0($4)
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addiu $30, $30, -0x130
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beq $30, $0, .+12
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nop
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sw $0, 0($4)
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jr $31
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nop
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.end vRegTest1
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/* .section .FreeRTOS, ax, @progbits */
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.set noreorder
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.set noat
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.ent vRegTest2
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vRegTest2:
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addiu $1, $0, 0x10
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addiu $2, $0, 0x20
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addiu $3, $0, 0x30
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addiu $5, $0, 0x50
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addiu $6, $0, 0x60
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addiu $7, $0, 0x70
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addiu $8, $0, 0x80
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addiu $9, $0, 0x90
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addiu $10, $0, 0x100
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addiu $11, $0, 0x110
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addiu $12, $0, 0x120
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addiu $13, $0, 0x130
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addiu $14, $0, 0x140
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addiu $15, $0, 0x150
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addiu $16, $0, 0x160
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addiu $17, $0, 0x170
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addiu $18, $0, 0x180
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addiu $19, $0, 0x190
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addiu $20, $0, 0x200
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addiu $21, $0, 0x210
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addiu $22, $0, 0x220
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addiu $23, $0, 0x230
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addiu $24, $0, 0x240
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addiu $25, $0, 0x250
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addiu $30, $0, 0x300
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#if configUSE_PREEMPTION == 0
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syscall 0
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#endif
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addiu $1, $1, -0x10
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beq $1, $0, .+12
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nop
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sw $0, 0($4)
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addiu $2, $2, -0x20
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beq $2, $0, .+12
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nop
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sw $0, 0($4)
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addiu $3, $3, -0x30
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beq $3, $0, .+12
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nop
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sw $0, 0($4)
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addiu $5, $5, -0x50
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beq $5, $0, .+12
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nop
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sw $0, 0($4)
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addiu $6, $6, -0x60
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beq $6, $0, .+12
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nop
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sw $0, 0($4)
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addiu $7, $7, -0x70
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beq $7, $0, .+12
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nop
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sw $0, 0($4)
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addiu $8, $8, -0x80
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beq $8, $0, .+12
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nop
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sw $0, 0($4)
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addiu $9, $9, -0x90
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beq $9, $0, .+12
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nop
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sw $0, 0($4)
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addiu $10, $10, -0x100
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beq $10, $0, .+12
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nop
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sw $0, 0($4)
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addiu $11, $11, -0x110
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beq $11, $0, .+12
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nop
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sw $0, 0($4)
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addiu $12, $12, -0x120
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beq $12, $0, .+12
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nop
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sw $0, 0($4)
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addiu $13, $13, -0x130
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beq $13, $0, .+12
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nop
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sw $0, 0($4)
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addiu $14, $14, -0x140
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beq $14, $0, .+12
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nop
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sw $0, 0($4)
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addiu $15, $15, -0x150
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beq $15, $0, .+12
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nop
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sw $0, 0($4)
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addiu $16, $16, -0x160
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beq $16, $0, .+12
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nop
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sw $0, 0($4)
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addiu $17, $17, -0x170
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beq $17, $0, .+12
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nop
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sw $0, 0($4)
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addiu $18, $18, -0x180
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beq $18, $0, .+12
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nop
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sw $0, 0($4)
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addiu $19, $19, -0x190
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beq $19, $0, .+12
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nop
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sw $0, 0($4)
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addiu $20, $20, -0x200
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beq $20, $0, .+12
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nop
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sw $0, 0($4)
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addiu $21, $21, -0x210
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beq $21, $0, .+12
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nop
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sw $0, 0($4)
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addiu $22, $22, -0x220
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beq $22, $0, .+12
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nop
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sw $0, 0($4)
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addiu $23, $23, -0x230
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beq $23, $0, .+12
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nop
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sw $0, 0($4)
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addiu $24, $24, -0x240
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beq $24, $0, .+12
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nop
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sw $0, 0($4)
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addiu $25, $25, -0x250
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beq $25, $0, .+12
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nop
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sw $0, 0($4)
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addiu $30, $30, -0x300
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beq $30, $0, .+12
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nop
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sw $0, 0($4)
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jr $31
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nop
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.end vRegTest2
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