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163 lines
7.2 KiB
ArmAsm
163 lines
7.2 KiB
ArmAsm
;/*****************************************************************************/
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;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */
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;/*****************************************************************************/
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;/* <<< Use Configuration Wizard in Context Menu >>> */
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;/*****************************************************************************/
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;/* This file is part of the uVision/ARM development tools. */
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;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
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;/* This software may only be used under the terms of a valid, current, */
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;/* end user licence from KEIL for a compatible version of KEIL software */
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;/* development tools. Nothing else gives you the right to use this software. */
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;/*****************************************************************************/
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;/*
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; * The STARTUP.S code is executed after CPU Reset.
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; */
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;// <h> Stack Configuration
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;// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;// </h>
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Stack_Size EQU 51
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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;// <h> Heap Configuration
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;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;// </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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Heap_Mem SPACE Heap_Size
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; System Control Register Addresses
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SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address
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PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control
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LDOPC_OFS EQU 0x0034 ; LDO Power
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SRCR0_OFS EQU 0x0040 ; Software Reset Control 0
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SRCR1_OFS EQU 0x0044 ; Software Reset Control 1
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SRCR2_OFS EQU 0x0048 ; Software Reset Control 2
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RCC_OFS EQU 0x0060 ; Run-Mode Clock Control
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RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0
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RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1
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RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2
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SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0
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SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1
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SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2
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DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0
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DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1
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DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2
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PRESERVE8
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; Area Definition and Entry Point
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; Startup Code must be linked first at Address 0.
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AREA RESET, CODE, READONLY
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THUMB
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IMPORT xPortPendSVHandler
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IMPORT xPortSysTickHandler
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IMPORT vUART_ISR
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; Vector Table
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Vectors DCD Stack_Mem + Stack_Size ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NmiSR ; NMI Handler
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DCD DefaultISR ; Hard Fault Handler
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DCD DefaultISR ; MPU Fault Handler
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DCD DefaultISR ; Bus Fault Handler
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DCD DefaultISR ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; SVCall Handler
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DCD DefaultISR ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD xPortPendSVHandler ; PendSV Handler
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DCD xPortSysTickHandler ; SysTick Handler
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DCD DefaultISR ; GPIO Port A Handler
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DCD DefaultISR ; GPIO Port B Handler
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DCD DefaultISR ; GPIO Port C Handler
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DCD DefaultISR ; GPIO Port D Handler
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DCD DefaultISR ; GPIO Port E Handler
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DCD vUART_ISR ; UART0 Rx/Tx Handler
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DCD DefaultISR ; UART1 Rx/Tx Handler
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DCD DefaultISR ; SSI Rx/Tx Handler
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DCD DefaultISR ; I2C Master/Slave Handler
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DCD DefaultISR ; PWM Fault Handler
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DCD DefaultISR ; PWM Generator 0 Handler
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DCD DefaultISR ; PWM Generator 1 Handler
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DCD DefaultISR ; PWM Generator 2 Handler
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DCD DefaultISR ; Quadrature Encoder Handler
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DCD DefaultISR ; ADC Sequence 0 Handler
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DCD DefaultISR ; ADC Sequence 1 Handler
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DCD DefaultISR ; ADC Sequence 2 Handler
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DCD DefaultISR ; ADC Sequence 3 Handler
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DCD DefaultISR ; Watchdog Timer Handler
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DCD DefaultISR ; Timer 0 Subtimer A Handler
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DCD DefaultISR ; Timer 0 Subtimer B Handler
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DCD DefaultISR ; Timer 1 Subtimer A Handler
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DCD DefaultISR ; Timer 1 Subtimer B Handler
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DCD DefaultISR ; Timer 2 Subtimer A Handler
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DCD DefaultISR ; Timer 2 Subtimer B Handler
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DCD DefaultISR ; Analog Comparator 0 Handler
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DCD DefaultISR ; Analog Comparator 1 Handler
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DCD DefaultISR ; Analog Comparator 2 Handler
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DCD DefaultISR ; System Control Handler
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DCD DefaultISR ; Flash Control Handler
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; Dummy Handlers are implemented as infinite loops which can be modified.
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NmiSR B NmiSR
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FaultISR B FaultISR
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EXPORT FaultISR
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DefaultISR B DefaultISR
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; Reset Handler
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EXPORT Reset_Handler
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Reset_Handler
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; Enable Clock Gating for Peripherals
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; LDR R0, =SYSCTL_BASE ; System Control Base Address
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; MVN R1, #0 ; Value 0xFFFFFFFF
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; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0
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; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1
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; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2
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; Enter the C code
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IMPORT __main
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LDR R0, =__main
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BX R0
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; User Initial Stack & Heap
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AREA |.text|, CODE, READONLY
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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END
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