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822 lines
25 KiB
C
822 lines
25 KiB
C
//*****************************************************************************
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//
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// uart.c - Driver for the UART.
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 991 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup uart_api
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//! @{
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//
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//*****************************************************************************
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#include "../hw_ints.h"
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#include "../hw_memmap.h"
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#include "../hw_types.h"
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#include "../hw_uart.h"
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#include "debug.h"
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#include "interrupt.h"
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#include "sysctl.h"
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#include "uart.h"
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//*****************************************************************************
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//
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//! Sets the type of parity.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param ulParity specifies the type of parity to use.
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//!
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//! Sets the type of parity to use for transmitting and expect when receiving.
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//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
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//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
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//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
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//! parity bit; it will always be either be one or zero based on the mode.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
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(ulParity == UART_CONFIG_PAR_EVEN) ||
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(ulParity == UART_CONFIG_PAR_ODD) ||
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(ulParity == UART_CONFIG_PAR_ONE) ||
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(ulParity == UART_CONFIG_PAR_ZERO));
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//
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// Set the parity mode.
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//
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HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) &
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~(UART_LCR_H_SPS | UART_LCR_H_EPS |
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UART_LCR_H_PEN)) | ulParity);
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}
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#endif
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//*****************************************************************************
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//
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//! Gets the type of parity currently being used.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! \return The current parity settings, specified as one of
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//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
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//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
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//
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//*****************************************************************************
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#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN)
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unsigned long
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UARTParityModeGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Return the current parity setting.
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//
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return(HWREG(ulBase + UART_O_LCR_H) &
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(UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN));
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}
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#endif
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//*****************************************************************************
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//
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//! Sets the configuration of a UART.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param ulBaud is the desired baud rate.
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//! \param ulConfig is the data format for the port (number of data bits,
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//! number of stop bits, and parity).
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//!
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//! This function will configure the UART for operation in the specified data
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//! format. The baud rate is provided in the \e ulBaud parameter and the
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//! data format in the \e ulConfig parameter.
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//!
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//! The \e ulConfig parameter is the logical OR of three values: the number of
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//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
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//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
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//! select from eight to five data bits per byte (respectively).
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//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
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//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
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//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
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//! select the parity mode (no parity bit, even parity bit, odd parity bit,
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//! parity bit always one, and parity bit always zero, respectively).
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//!
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//! The baud rate is dependent upon the system clock rate returned by
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//! SysCtlClockGet(); if it does not return the correct system clock rate then
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//! the baud rate will be incorrect.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,
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unsigned long ulConfig)
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{
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unsigned long ulUARTClk, ulInt, ulFrac;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Stop the UART.
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//
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UARTDisable(ulBase);
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//
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// Determine the UART clock rate.
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//
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ulUARTClk = SysCtlClockGet();
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//
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// Compute the fractional baud rate divider.
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//
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ulInt = ulUARTClk / (16 * ulBaud);
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ulFrac = ulUARTClk % (16 * ulBaud);
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ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2);
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//
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// Set the baud rate.
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//
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HWREG(ulBase + UART_O_IBRD) = ulInt;
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HWREG(ulBase + UART_O_FBRD) = ulFrac;
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//
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// Set parity, data length, and number of stop bits.
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//
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HWREG(ulBase + UART_O_LCR_H) = ulConfig;
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//
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// Clear the flags register.
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//
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HWREG(ulBase + UART_O_FR) = 0;
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//
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// Start the UART.
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//
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UARTEnable(ulBase);
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}
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#endif
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//*****************************************************************************
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//
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//! Gets the current configuration of a UART.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param pulBaud is a pointer to storage for the baud rate.
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//! \param pulConfig is a pointer to storage for the data format.
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//!
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//! The baud rate and data format for the UART is determined. The returned
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//! baud rate is the actual baud rate; it may not be the exact baud rate
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//! requested or an ``official'' baud rate. The data format returned in
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//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
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//! UARTConfigSet().
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//!
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//! The baud rate is dependent upon the system clock rate returned by
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//! SysCtlClockGet(); if it does not return the correct system clock rate then
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//! the baud rate will be computed incorrectly.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,
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unsigned long *pulConfig)
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{
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unsigned long ulInt, ulFrac;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Compute the baud rate.
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//
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ulInt = HWREG(ulBase + UART_O_IBRD);
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ulFrac = HWREG(ulBase + UART_O_FBRD);
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*pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac);
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//
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// Get the parity, data length, and number of stop bits.
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//
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*pulConfig = (HWREG(ulBase + UART_O_LCR_H) &
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(UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 |
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UART_LCR_H_EPS | UART_LCR_H_PEN));
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}
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#endif
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//*****************************************************************************
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//
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//! Enables transmitting and receiving.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
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//! FIFOs.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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UARTEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Enable the FIFO.
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//
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HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN;
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//
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// Enable RX, TX, and the UART.
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//
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HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
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UART_CTL_RXE);
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}
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#endif
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//*****************************************************************************
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//
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//! Disables transmitting and receiving.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
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//! transmission of the current character, and flushes the transmit FIFO.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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UARTDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Wait for end of TX.
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//
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while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
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{
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}
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//
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// Disable the FIFO.
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//
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HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN);
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//
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// Disable the UART.
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//
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HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
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UART_CTL_RXE);
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}
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#endif
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//*****************************************************************************
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//
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//! Determines if there are any characters in the receive FIFO.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! This function returns a flag indicating whether or not there is data
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//! available in the receive FIFO.
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//!
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//! \return Returns \b true if there is data in the receive FIFO, and \b false
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//! if there is no data in the receive FIFO.
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//
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//*****************************************************************************
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#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN)
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tBoolean
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UARTCharsAvail(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Return the availability of characters.
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//
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return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
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}
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#endif
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//*****************************************************************************
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//
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//! Determines if there is any space in the transmit FIFO.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! This function returns a flag indicating whether or not there is space
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//! available in the transmit FIFO.
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//!
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//! \return Returns \b true if there is space available in the transmit FIFO,
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//! and \b false if there is no space available in the transmit FIFO.
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//
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//*****************************************************************************
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#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN)
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tBoolean
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UARTSpaceAvail(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// Return the availability of space.
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//
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return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
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}
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#endif
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//*****************************************************************************
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//
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//! Receives a character from the specified port.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! Gets a character from the receive FIFO for the specified port.
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//!
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//! \return Returns the character read from the specified port, cast as a
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//! \e long. A \b -1 will be returned if there are no characters present in
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//! the receive FIFO. The UARTCharsAvail() function should be called before
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//! attempting to call this function.
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//
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//*****************************************************************************
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#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN)
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long
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UARTCharNonBlockingGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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//
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// See if there are any characters in the receive FIFO.
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//
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if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
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{
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//
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// Read and return the next character.
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//
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return(HWREG(ulBase + UART_O_DR));
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}
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else
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{
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//
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// There are no characters, so return a failure.
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//
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return(-1);
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}
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}
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#endif
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//*****************************************************************************
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//
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//! Waits for a character from the specified port.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! Gets a character from the receive FIFO for the specified port. If there
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//! are no characters available, this function will wait until a character is
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//! received before returning.
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//!
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//! \return Returns the character read from the specified port, cast as an
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//! \e int.
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//
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//*****************************************************************************
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#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN)
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long
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UARTCharGet(unsigned long ulBase)
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{
|
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//
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// Check the arguments.
|
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//
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ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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|
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//
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// Wait until a char is available.
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//
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while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
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{
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}
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//
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// Now get the char.
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//
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return(HWREG(ulBase + UART_O_DR));
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}
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|
#endif
|
|
|
|
//*****************************************************************************
|
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//
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//! Sends a character to the specified port.
|
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//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ucData is the character to be transmitted.
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//!
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//! Writes the character \e ucData to the transmit FIFO for the specified port.
|
|
//! This function does not block, so if there is no space available, then a
|
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//! \b false is returned, and the application will have to retry the function
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//! later.
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//!
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//! \return Returns \b true if the character was successfully placed in the
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//! transmit FIFO, and \b false if there was no space available in the transmit
|
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//! FIFO.
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//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
tBoolean
|
|
UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// See if there is space in the transmit FIFO.
|
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//
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if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
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{
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//
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|
// Write this character to the transmit FIFO.
|
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//
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HWREG(ulBase + UART_O_DR) = ucData;
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|
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//
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// Success.
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//
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return(true);
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}
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|
else
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{
|
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//
|
|
// There is no space in the transmit FIFO, so return a failure.
|
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//
|
|
return(false);
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|
}
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|
}
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|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Waits to send a character from the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ucData is the character to be transmitted.
|
|
//!
|
|
//! Sends the character \e ucData to the transmit FIFO for the specified port.
|
|
//! If there is no space available in the transmit FIFO, this function will
|
|
//! wait until there is space available before returning.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTCharPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Wait until space is available.
|
|
//
|
|
while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Send the char.
|
|
//
|
|
HWREG(ulBase + UART_O_DR) = ucData;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Causes a BREAK to be sent.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param bBreakState controls the output level.
|
|
//!
|
|
//! Calling this function with \e bBreakState set to \b true will assert a
|
|
//! break condition on the UART. Calling this function with \e bBreakState set
|
|
//! to \b false will remove the break condition. For proper transmission of a
|
|
//! break command, the break must be asserted for at least two complete frames.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Set the break condition as requested.
|
|
//
|
|
HWREG(ulBase + UART_O_LCR_H) =
|
|
(bBreakState ?
|
|
(HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) :
|
|
(HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK)));
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Registers an interrupt handler for a UART interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param pfnHandler is a pointer to the function to be called when the
|
|
//! UART interrupt occurs.
|
|
//!
|
|
//! This function does the actual registering of the interrupt handler. This
|
|
//! will enable the global interrupt in the interrupt controller; specific UART
|
|
//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
|
|
//! handler's responsibility to clear the interrupt source.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
|
|
{
|
|
unsigned long ulInt;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Determine the interrupt number based on the UART port.
|
|
//
|
|
ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;
|
|
|
|
//
|
|
// Register the interrupt handler.
|
|
//
|
|
IntRegister(ulInt, pfnHandler);
|
|
|
|
//
|
|
// Enable the UART interrupt.
|
|
//
|
|
IntEnable(ulInt);
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unregisters an interrupt handler for a UART interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function does the actual unregistering of the interrupt handler. It
|
|
//! will clear the handler to be called when a UART interrupt occurs. This
|
|
//! will also mask off the interrupt in the interrupt controller so that the
|
|
//! interrupt handler no longer is called.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTIntUnregister(unsigned long ulBase)
|
|
{
|
|
unsigned long ulInt;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Determine the interrupt number based on the UART port.
|
|
//
|
|
ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;
|
|
|
|
//
|
|
// Disable the interrupt.
|
|
//
|
|
IntDisable(ulInt);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
IntUnregister(ulInt);
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual UART interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
|
|
//!
|
|
//! Enables the indicated UART interrupt sources. Only the sources that are
|
|
//! enabled can be reflected to the processor interrupt; disabled sources have
|
|
//! no effect on the processor.
|
|
//!
|
|
//! The parameter \e ulIntFlags is the logical OR of any of the following:
|
|
//!
|
|
//! - UART_INT_OE - Overrun Error interrupt
|
|
//! - UART_INT_BE - Break Error interrupt
|
|
//! - UART_INT_PE - Parity Error interrupt
|
|
//! - UART_INT_FE - Framing Error interrupt
|
|
//! - UART_INT_RT - Receive Timeout interrupt
|
|
//! - UART_INT_TX - Transmit interrupt
|
|
//! - UART_INT_RX - Receive interrupt
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Enable the specified interrupts.
|
|
//
|
|
HWREG(ulBase + UART_O_IM) |= ulIntFlags;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual UART interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
|
|
//!
|
|
//! Disables the indicated UART interrupt sources. Only the sources that are
|
|
//! enabled can be reflected to the processor interrupt; disabled sources have
|
|
//! no effect on the processor.
|
|
//!
|
|
//! The parameter \e ulIntFlags has the same definition as the same parameter
|
|
//! to UARTIntEnable().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Disable the specified interrupts.
|
|
//
|
|
HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current interrupt status.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param bMasked is false if the raw interrupt status is required and true
|
|
//! if the masked interrupt status is required.
|
|
//!
|
|
//! This returns the interrupt status for the specified UART. Either the raw
|
|
//! interrupt status or the status of interrupts that are allowed to reflect to
|
|
//! the processor can be returned.
|
|
//!
|
|
//! \return The current interrupt status, enumerated as a bit field of
|
|
//! values described in UARTIntEnable().
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
unsigned long
|
|
UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return(HWREG(ulBase + UART_O_MIS));
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(ulBase + UART_O_RIS));
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears UART interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
|
|
//!
|
|
//! The specified UART interrupt sources are cleared, so that they no longer
|
|
//! assert. This must be done in the interrupt handler to keep it from being
|
|
//! called again immediately upon exit.
|
|
//!
|
|
//! The parameter \e ulIntFlags has the same definition as the same parameter
|
|
//! to UARTIntEnable().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
|
|
|
|
//
|
|
// Clear the requested interrupt sources.
|
|
//
|
|
HWREG(ulBase + UART_O_ICR) = ulIntFlags;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|