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250 lines
5.4 KiB
ArmAsm
250 lines
5.4 KiB
ArmAsm
/*
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* Lowest level routines for all ColdFire processors. Based on the
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* MCF523x examples from Freescale.
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*
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* Freescale explicitly grants the redistribution and modification
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* of these source files. The complete licensing information is
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* available in the file LICENSE_FREESCALE.TXT.
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*
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* Modifications Copyright (c) 2006 Christian Walter <wolti@sil.at>
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*
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* File: $Id: mcf5xxx.S,v 1.3 2006/09/24 22:50:23 wolti Exp $
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*/
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.global asm_set_ipl
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.global _asm_set_ipl
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.global mcf5xxx_wr_cacr
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.global _mcf5xxx_wr_cacr
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.global mcf5xxx_wr_acr0
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.global _mcf5xxx_wr_acr0
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.global mcf5xxx_wr_acr1
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.global _mcf5xxx_wr_acr1
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.global mcf5xxx_wr_acr2
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.global _mcf5xxx_wr_acr2
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.global mcf5xxx_wr_acr3
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.global _mcf5xxx_wr_acr3
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.global mcf5xxx_wr_other_sp
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.global _mcf5xxx_wr_other_sp
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.global mcf5xxx_wr_other_a7
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.global _mcf5xxx_wr_other_a7
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.global mcf5xxx_wr_vbr
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.global _mcf5xxx_wr_vbr
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.global mcf5xxx_wr_macsr
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.global _mcf5xxx_wr_macsr
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.global mcf5xxx_wr_mask
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.global _mcf5xxx_wr_mask
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.global mcf5xxx_wr_acc0
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.global _mcf5xxx_wr_acc0
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.global mcf5xxx_wr_accext01
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.global _mcf5xxx_wr_accext01
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.global mcf5xxx_wr_accext23
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.global _mcf5xxx_wr_accext23
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.global mcf5xxx_wr_acc1
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.global _mcf5xxx_wr_acc1
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.global mcf5xxx_wr_acc2
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.global _mcf5xxx_wr_acc2
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.global mcf5xxx_wr_acc3
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.global _mcf5xxx_wr_acc3
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.global mcf5xxx_wr_sr
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.global _mcf5xxx_wr_sr
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.global mcf5xxx_wr_rambar0
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.global _mcf5xxx_wr_rambar0
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.global mcf5xxx_wr_rambar1
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.global _mcf5xxx_wr_rambar1
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.global mcf5xxx_wr_mbar
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.global _mcf5xxx_wr_mbar
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.global mcf5xxx_wr_mbar0
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.global _mcf5xxx_wr_mbar0
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.global mcf5xxx_wr_mbar1
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.global _mcf5xxx_wr_mbar1
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.text
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/********************************************************************/
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/*
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* This routines changes the IPL to the value passed into the routine.
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* It also returns the old IPL value back.
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* Calling convention from C:
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* old_ipl = asm_set_ipl(new_ipl);
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* For the Diab Data C compiler, it passes return value thru D0.
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* Note that only the least significant three bits of the passed
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* value are used.
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*/
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asm_set_ipl:
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_asm_set_ipl:
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link a6,#-8
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movem.l d6-d7,(sp)
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move.w sr,d7 /* current sr */
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move.l d7,d0 /* prepare return value */
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andi.l #0x0700,d0 /* mask out IPL */
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lsr.l #8,d0 /* IPL */
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move.l 8(a6),d6 /* get argument */
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andi.l #0x07,d6 /* least significant three bits */
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lsl.l #8,d6 /* move over to make mask */
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andi.l #0x0000F8FF,d7 /* zero out current IPL */
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or.l d6,d7 /* place new IPL in sr */
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move.w d7,sr
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movem.l (sp),d6-d7
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lea 8(sp),sp
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unlk a6
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rts
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/********************************************************************/
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/*
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* These routines write to the special purpose registers in the ColdFire
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* core. Since these registers are write-only in the supervisor model,
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* no corresponding read routines exist.
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*/
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mcf5xxx_wr_cacr:
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_mcf5xxx_wr_cacr:
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move.l 4(sp),d0
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.long 0x4e7b0002 /* movec d0,cacr */
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nop
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rts
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mcf5xxx_wr_acr0:
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_mcf5xxx_wr_acr0:
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move.l 4(sp),d0
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.long 0x4e7b0004 /* movec d0,ACR0 */
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nop
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rts
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mcf5xxx_wr_acr1:
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_mcf5xxx_wr_acr1:
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move.l 4(sp),d0
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.long 0x4e7b0005 /* movec d0,ACR1 */
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nop
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rts
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mcf5xxx_wr_acr2:
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_mcf5xxx_wr_acr2:
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move.l 4(sp),d0
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.long 0x4e7b0006 /* movec d0,ACR2 */
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nop
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rts
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mcf5xxx_wr_acr3:
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_mcf5xxx_wr_acr3:
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move.l 4(sp),d0
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.long 0x4e7b0007 /* movec d0,ACR3 */
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nop
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rts
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mcf5xxx_wr_other_sp:
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_mcf5xxx_wr_other_sp:
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mcf5xxx_wr_other_a7:
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_mcf5xxx_wr_other_a7:
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move.l 4(sp),d0
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.long 0x4e7b0800 /* movec d0,OTHER_A7 */
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nop
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rts
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mcf5xxx_wr_vbr:
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_mcf5xxx_wr_vbr:
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move.l 4(sp),d0
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.long 0x4e7b0801 /* movec d0,VBR */
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nop
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rts
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mcf5xxx_wr_macsr:
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_mcf5xxx_wr_macsr:
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move.l 4(sp),d0
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.long 0x4e7b0804 /* movec d0,MACSR */
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nop
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rts
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mcf5xxx_wr_mask:
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_mcf5xxx_wr_mask:
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move.l 4(sp),d0
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.long 0x4e7b0805 /* movec d0,MASK */
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nop
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rts
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mcf5xxx_wr_acc0:
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_mcf5xxx_wr_acc0:
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move.l 4(sp),d0
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.long 0x4e7b0806 /* movec d0,ACC0 */
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nop
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rts
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mcf5xxx_wr_accext01:
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_mcf5xxx_wr_accext01:
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move.l 4(sp),d0
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.long 0x4e7b0807 /* movec d0,ACCEXT01 */
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nop
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rts
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mcf5xxx_wr_accext23:
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_mcf5xxx_wr_accext23:
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move.l 4(sp),d0
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.long 0x4e7b0808 /* movec d0,ACCEXT23 */
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nop
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rts
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mcf5xxx_wr_acc1:
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_mcf5xxx_wr_acc1:
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move.l 4(sp),d0
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.long 0x4e7b0809 /* movec d0,ACC1 */
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nop
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rts
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mcf5xxx_wr_acc2:
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_mcf5xxx_wr_acc2:
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move.l 4(sp),d0
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.long 0x4e7b080A /* movec d0,ACC2 */
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nop
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rts
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mcf5xxx_wr_acc3:
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_mcf5xxx_wr_acc3:
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move.l 4(sp),d0
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.long 0x4e7b080B /* movec d0,ACC3 */
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nop
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rts
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mcf5xxx_wr_sr:
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_mcf5xxx_wr_sr:
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move.l 4(sp),d0
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move.w d0,SR
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rts
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mcf5xxx_wr_rambar0:
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_mcf5xxx_wr_rambar0:
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move.l 4(sp),d0
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.long 0x4e7b0C04 /* movec d0,RAMBAR0 */
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nop
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rts
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mcf5xxx_wr_rambar1:
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_mcf5xxx_wr_rambar1:
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move.l 4(sp),d0
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.long 0x4e7b0C05 /* movec d0,RAMBAR1 */
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nop
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rts
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mcf5xxx_wr_mbar:
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_mcf5xxx_wr_mbar:
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mcf5xxx_wr_mbar0:
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_mcf5xxx_wr_mbar0:
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move.l 4(sp),d0
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.long 0x4e7b0C0F /* movec d0,MBAR0 */
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nop
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rts
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mcf5xxx_wr_mbar1:
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_mcf5xxx_wr_mbar1:
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move.l 4(sp),d0
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.long 0x4e7b0C0E /* movec d0,MBAR1 */
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nop
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rts
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.end
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/********************************************************************/
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