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973 lines
28 KiB
C
973 lines
28 KiB
C
//*****************************************************************************
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//
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// i2c.c - Driver for Inter-IC (I2C) bus block.
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 991 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup i2c_api
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//! @{
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//
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//*****************************************************************************
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#include "../hw_i2c.h"
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#include "../hw_ints.h"
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#include "../hw_memmap.h"
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#include "../hw_types.h"
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#include "debug.h"
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#include "i2c.h"
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#include "interrupt.h"
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#include "sysctl.h"
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//*****************************************************************************
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//
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//! Initializes the I2C Master block.
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//!
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//! \param ulBase base address of the I2C Master module
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//! \param bFast set up for fast data transfers
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//!
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//! This function initializes operation of the I2C Master block. Upon
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//! successful initialization of the I2C block, this function will have
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//! set the bus speed for the master, and will have enabled the I2C Master
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//! block.
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//!
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//! If the parameter \e bFast is \b true, then the master block will be
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//! set up to transfer data at 400 kbps; otherwise, it will be set up to
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//! transfer data at 100 kbps.
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//!
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//! The I2C clocking is dependent upon the system clock rate returned by
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//! SysCtlClockGet(); if it does not return the correct system clock rate then
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//! the I2C clock rate will be incorrect.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CMasterInit(unsigned long ulBase, tBoolean bFast)
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{
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unsigned long ulSysClk;
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unsigned long ulSCLFreq;
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unsigned long ulTPR;
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Must enable the device before doing anything else.
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//
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I2CMasterEnable(ulBase);
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//
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// Get the system clock speed.
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//
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ulSysClk = SysCtlClockGet();
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//
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// Get the desired SCL speed.
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//
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if(bFast == true)
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{
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ulSCLFreq = I2C_SCL_FAST;
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}
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else
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{
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ulSCLFreq = I2C_SCL_STANDARD;
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}
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//
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// Compute the clock divider that achieves the fastest speed less than or
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// equal to the desired speed. The numerator is biases to favor a larger
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// clock divider so that the resulting clock is always less than or equal
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// to the desired clock, never greater.
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//
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ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) /
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(2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1);
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HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR;
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}
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#endif
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//*****************************************************************************
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//
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//! Initializes the I2C Slave block.
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//!
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//! \param ulBase base address of the I2C Slave module
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//! \param ucSlaveAddr 7-bit slave address
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//!
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//! This function initializes operation of the I2C Slave block. Upon
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//! successful initialization of the I2C blocks, this function will have
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//! set the slave address and have enabled the I2C Slave block.
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//!
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//! The parameter \e ucSlaveAddr is the value that will be compared
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//! against the slave address sent by an I2C master.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_SLAVE_BASE);
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ASSERT(!(ucSlaveAddr & 0x80));
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//
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// Must enable the device before doing anything else.
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//
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I2CSlaveEnable(ulBase);
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//
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// Set up the slave address.
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//
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HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr;
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}
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#endif
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//*****************************************************************************
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//
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//! Enables the I2C Master block.
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//!
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//! \param ulBase base address of the I2C Master module
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//!
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//! This will enable operation of the I2C Master block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CMasterEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Enable the master block.
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//
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HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE;
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}
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#endif
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//*****************************************************************************
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//
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//! Enables the I2C Slave block.
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//!
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//! \param ulBase base address of the I2C Slave module
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//!
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//! This will enable operation of the I2C Slave block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CSlaveEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_SLAVE_BASE);
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//
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// Enable the clock to the slave block.
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//
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HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE;
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//
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// Enable the slave.
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//
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HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA;
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}
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#endif
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//*****************************************************************************
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//
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//! Disables the I2C master block.
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//!
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//! \param ulBase base address of the I2C Master module
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//!
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//! This will disable operation of the I2C master block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CMasterDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Disable the master block.
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//
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HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE);
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}
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#endif
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//*****************************************************************************
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//
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//! Disables the I2C slave block.
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//!
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//! \param ulBase base address of the I2C Slave module
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//!
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//! This will disable operation of the I2C slave block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CSlaveDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_SLAVE_BASE);
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//
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// Disable the slave.
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//
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HWREG(ulBase + I2C_SLAVE_O_CSR) = 0;
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//
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// Disable the clock to the slave block.
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//
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HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE);
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}
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#endif
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//*****************************************************************************
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//
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//! Registers an interrupt handler for the I2C module
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//!
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//! \param ulBase base address of the I2C module
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//! \param pfnHandler is a pointer to the function to be called when the
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//! synchronous serial interface interrupt occurs.
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//!
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//! This sets the handler to be called when an I2C interrupt occurs. This
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//! will enable the global interrupt in the interrupt controller; specific I2C
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//! interrupts must be enabled via I2CMasterIntEnable() and
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//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
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//! responsibility to clear the interrupt source via I2CMasterIntClear() and
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//! I2CSlaveIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Register the interrupt handler, returning an error if an error occurs.
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//
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IntRegister(INT_I2C, pfnHandler);
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//
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// Enable the I2C interrupt.
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//
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IntEnable(INT_I2C);
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}
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#endif
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//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the I2C module.
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//!
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//! \param ulBase base address of the I2C module
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//!
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//! This function will clear the handler to be called when an I2C
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//! interrupt occurs. This will also mask off the interrupt in the interrupt
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//! controller so that the interrupt handler no longer is called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CIntUnregister(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Disable the interrupt.
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//
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IntDisable(INT_I2C);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(INT_I2C);
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}
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#endif
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//*****************************************************************************
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//
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//! Enables the I2C Master interrupt.
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//!
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//! \param ulBase base address of the I2C Master module
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//!
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//! Enables the I2C Master interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CMasterIntEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Enable the master interrupt.
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//
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HWREG(ulBase + I2C_MASTER_O_IMR) = 1;
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}
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#endif
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//*****************************************************************************
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//
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//! Enables the I2C Slave interrupt.
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//!
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//! \param ulBase base address of the I2C Slave module
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//!
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//! Enables the I2C Slave interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CSlaveIntEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_SLAVE_BASE);
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//
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// Enable the slave interrupt.
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//
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HWREG(ulBase + I2C_SLAVE_O_IM) = 1;
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}
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#endif
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//*****************************************************************************
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//
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//! Disables the I2C Master interrupt.
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//!
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//! \param ulBase base address of the I2C Master module
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//!
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//! Disables the I2C Master interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CMasterIntDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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//
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// Disable the master interrupt.
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//
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HWREG(ulBase + I2C_MASTER_O_IMR) = 0;
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}
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#endif
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//*****************************************************************************
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//
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//! Disables the I2C Slave interrupt.
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//!
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//! \param ulBase base address of the I2C Slave module
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//!
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//! Disables the I2C Slave interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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I2CSlaveIntDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == I2C_SLAVE_BASE);
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//
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// Disable the slave interrupt.
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//
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HWREG(ulBase + I2C_SLAVE_O_IM) = 0;
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}
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#endif
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//*****************************************************************************
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//
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//! Gets the current I2C Master interrupt status.
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//!
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//! \param ulBase base address of the I2C Master module
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//! \param bMasked is false if the raw interrupt status is requested and
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//! true if the masked interrupt status is requested.
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//!
|
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//! This returns the interrupt status for the I2C Master module.
|
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//! Either the raw interrupt status or the status of interrupts that are
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//! allowed to reflect to the processor can be returned.
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//!
|
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//! \return The current interrupt status, returned as \b true if active
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//! or \b false if not active.
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//
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//*****************************************************************************
|
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#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
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|
tBoolean
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I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
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{
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//
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// Check the arguments.
|
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//
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ASSERT(ulBase == I2C_MASTER_BASE);
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|
|
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//
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|
// Return either the interrupt status or the raw interrupt status as
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// requested.
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//
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|
if(bMasked)
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{
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|
return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false);
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|
}
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else
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|
{
|
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return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current I2C Slave interrupt status.
|
|
//!
|
|
//! \param ulBase base address of the I2C Slave module
|
|
//! \param bMasked is false if the raw interrupt status is requested and
|
|
//! true if the masked interrupt status is requested.
|
|
//!
|
|
//! This returns the interrupt status for the I2C Slave module.
|
|
//! Either the raw interrupt status or the status of interrupts that are
|
|
//! allowed to reflect to the processor can be returned.
|
|
//!
|
|
//! \return The current interrupt status, returned as \b true if active
|
|
//! or \b false if not active.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
tBoolean
|
|
I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_SLAVE_BASE);
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false);
|
|
}
|
|
else
|
|
{
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return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears I2C Master interrupt sources.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//!
|
|
//! The I2C Master interrupt source is cleared, so that it no longer asserts.
|
|
//! This must be done in the interrupt handler to keep it from being called
|
|
//! again immediately upon exit.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
I2CMasterIntClear(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
|
|
//
|
|
// Clear the I2C master interrupt source.
|
|
//
|
|
HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC;
|
|
|
|
//
|
|
// Workaround for I2C master interrupt clear errata for rev B Stellaris
|
|
// devices. For later devices, this write is ignored and therefore
|
|
// harmless (other than the slight performance hit).
|
|
//
|
|
HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears I2C Slave interrupt sources.
|
|
//!
|
|
//! \param ulBase base address of the I2C Slave module
|
|
//!
|
|
//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
|
|
//! This must be done in the interrupt handler to keep it from being called
|
|
//! again immediately upon exit.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
I2CSlaveIntClear(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_SLAVE_BASE);
|
|
|
|
//
|
|
// Clear the I2C slave interrupt source.
|
|
//
|
|
HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the address that the I2C Master will place on the bus.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//! \param ucSlaveAddr 7-bit slave address
|
|
//! \param bReceive flag indicating the type of communication with the slave
|
|
//!
|
|
//! This function will set the address that the I2C Master will place on the
|
|
//! bus when initiating a transaction. When the parameter \e bReceive is set
|
|
//! to \b true, the address will indicate that the I2C Master is initiating
|
|
//! a read from the slave; otherwise the address will indicate that the I2C
|
|
//! Master is initiating a write to the slave.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
|
|
tBoolean bReceive)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
ASSERT(!(ucSlaveAddr & 0x80));
|
|
|
|
//
|
|
// Set the address of the slave with which the master will communicate.
|
|
//
|
|
HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Indicates whether or not the I2C Master is busy.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//!
|
|
//! This function returns an indication of whether or not the I2C Master is
|
|
//! busy transmitting or receiving data.
|
|
//!
|
|
//! \return Returns \b true if the I2C Master is busy; otherwise, returns
|
|
//! \b false.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
tBoolean
|
|
I2CMasterBusy(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
|
|
//
|
|
// Return the busy status.
|
|
//
|
|
if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY)
|
|
{
|
|
return(true);
|
|
}
|
|
else
|
|
{
|
|
return(false);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Indicates whether or not the I2C bus is busy.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//!
|
|
//! This function returns an indication of whether or not the I2C bus is
|
|
//! busy. This function can be used in a multi-master environment to
|
|
//! determine if another master is currently using the bus.
|
|
//!
|
|
//! \return Returns \b true if the I2C bus is busy; otherwise, returns
|
|
//! \b false.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
tBoolean
|
|
I2CMasterBusBusy(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
|
|
//
|
|
// Return the bus busy status.
|
|
//
|
|
if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY)
|
|
{
|
|
return(true);
|
|
}
|
|
else
|
|
{
|
|
return(false);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Controls the state of the I2C Master module.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//! \param ulCmd command to be issued to the I2C Master module
|
|
//!
|
|
//! This function is used to control the state of the Master module send and
|
|
//! receive operations. The parameter \e ucCmd can be one of the following
|
|
//! values:
|
|
//!
|
|
//! - I2C_MASTER_CMD_SINGLE_SEND
|
|
//! - I2C_MASTER_CMD_SINGLE_RECEIVE
|
|
//! - I2C_MASTER_CMD_BURST_SEND_START
|
|
//! - I2C_MASTER_CMD_BURST_SEND_CONT
|
|
//! - I2C_MASTER_CMD_BURST_SEND_FINISH
|
|
//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
|
|
//! - I2C_MASTER_CMD_BURST_RECEIVE_START
|
|
//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT
|
|
//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH
|
|
//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
|
|
(ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
|
|
|
|
//
|
|
// Send the command.
|
|
//
|
|
HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the error status of the I2C Master module.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//!
|
|
//! This function is used to obtain the error status of the Master module
|
|
//! send and receive operations. It returns one of the following values:
|
|
//!
|
|
//! - I2C_MASTER_ERR_NONE
|
|
//! - I2C_MASTER_ERR_ADDR_ACK
|
|
//! - I2C_MASTER_ERR_DATA_ACK
|
|
//! - I2C_MASTER_ERR_ARB_LOST
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
unsigned long
|
|
I2CMasterErr(unsigned long ulBase)
|
|
{
|
|
unsigned long ulErr;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
|
|
//
|
|
// Get the raw error state
|
|
//
|
|
ulErr = HWREG(ulBase + I2C_MASTER_O_CS);
|
|
|
|
//
|
|
// If the I2C master is busy, then all the other bit are invalid, and
|
|
// don't have an error to report.
|
|
//
|
|
if(ulErr & I2C_MASTER_CS_BUSY)
|
|
{
|
|
return(I2C_MASTER_ERR_NONE);
|
|
}
|
|
|
|
//
|
|
// Check for errors.
|
|
//
|
|
if(ulErr & I2C_MASTER_CS_ERROR)
|
|
{
|
|
return(ulErr & (I2C_MASTER_CS_ERR_MASK));
|
|
}
|
|
else
|
|
{
|
|
return(I2C_MASTER_ERR_NONE);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Transmits a byte from the I2C Master.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//! \param ucData data to be transmitted from the I2C Master
|
|
//!
|
|
//! This function will place the supplied data into I2C Master Data Register.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
|
|
//
|
|
// Write the byte.
|
|
//
|
|
HWREG(ulBase + I2C_MASTER_O_DR) = ucData;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Receives a byte that has been sent to the I2C Master.
|
|
//!
|
|
//! \param ulBase base address of the I2C Master module
|
|
//!
|
|
//! This function reads a byte of data from the I2C Master Data Register.
|
|
//!
|
|
//! \return Returns the byte received from by the I2C Master, cast as an
|
|
//! unsigned long.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
unsigned long
|
|
I2CMasterDataGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_MASTER_BASE);
|
|
|
|
//
|
|
// Read a byte.
|
|
//
|
|
return(HWREG(ulBase + I2C_MASTER_O_DR));
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the I2C Slave module status
|
|
//!
|
|
//! \param ulBase base address of the I2C Slave module
|
|
//!
|
|
//! This function will return the action requested from a master, if any. The
|
|
//! possible values returned are:
|
|
//!
|
|
//! - I2C_SLAVE_ACT_NONE
|
|
//! - I2C_SLAVE_ACT_RREQ
|
|
//! - I2C_SLAVE_ACT_TREQ
|
|
//!
|
|
//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the
|
|
//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent
|
|
//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C
|
|
//! master has requested that the I2C Slave module send data.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
unsigned long
|
|
I2CSlaveStatus(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_SLAVE_BASE);
|
|
|
|
//
|
|
// Return the slave status.
|
|
//
|
|
return(HWREG(ulBase + I2C_SLAVE_O_CSR));
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Transmits a byte from the I2C Slave.
|
|
//!
|
|
//! \param ulBase base address of the I2C Slave module
|
|
//! \param ucData data to be transmitted from the I2C Slave
|
|
//!
|
|
//! This function will place the supplied data into I2C Slave Data Register.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
void
|
|
I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_SLAVE_BASE);
|
|
|
|
//
|
|
// Write the byte.
|
|
//
|
|
HWREG(ulBase + I2C_SLAVE_O_DR) = ucData;
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Receives a byte that has been sent to the I2C Slave.
|
|
//!
|
|
//! \param ulBase base address of the I2C Slave module
|
|
//!
|
|
//! This function reads a byte of data from the I2C Slave Data Register.
|
|
//!
|
|
//! \return Returns the byte received from by the I2C Slave, cast as an
|
|
//! unsigned long.
|
|
//
|
|
//*****************************************************************************
|
|
#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN)
|
|
unsigned long
|
|
I2CSlaveDataGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulBase == I2C_SLAVE_BASE);
|
|
|
|
//
|
|
// Read a byte.
|
|
//
|
|
return(HWREG(ulBase + I2C_SLAVE_O_DR));
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|