EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_RS232_Uart_RX_pin I 1 fpga_0_RS232_Uart_RX fpga_0_RS232_Uart_TX_pin O 1 fpga_0_RS232_Uart_TX fpga_0_LEDs_4Bit_GPIO_IO_pin IO 0:3 fpga_0_LEDs_4Bit_GPIO_IO fpga_0_LEDs_Positions_GPIO_IO_pin IO 0:4 fpga_0_LEDs_Positions_GPIO_IO fpga_0_SRAM_Mem_A_pin O 9:29 fpga_0_SRAM_Mem_A fpga_0_SRAM_Mem_BEN_pin O 0:3 fpga_0_SRAM_Mem_BEN fpga_0_SRAM_Mem_WEN_pin O 1 fpga_0_SRAM_Mem_WEN fpga_0_SRAM_Mem_DQ_pin IO 0:31 fpga_0_SRAM_Mem_DQ fpga_0_SRAM_Mem_OEN_pin O 0:0 fpga_0_SRAM_Mem_OEN fpga_0_SRAM_Mem_CEN_pin O 0:0 fpga_0_SRAM_Mem_CEN fpga_0_SRAM_Mem_ADV_LDN_pin O 1 fpga_0_SRAM_Mem_ADV_LDN fpga_0_SRAM_CLOCK O 1 sys_clk_s sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET