Commit Graph

2952 Commits (ac1578d871590fe048994f8ffad42b13f6f07385)
 

Author SHA1 Message Date
Richard Barry 11c391dfb3 Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo.
Richard Barry 343fbe795f Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently.
Richard Barry ef31243396 Add some asserts into the common demo tasks to catch scenarios where the tasks are not being used but the part of the demo/test that gets called from the tick hook is called resultant in an access to objects that were not created.
Richard Barry 61a003088d Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time.
Richard Barry a83244a37e Add the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools.
Richard Barry c7c60cff15 Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio.
Richard Barry f78ccd077a Recreate the RISC-V-Qemu demo using Vanilla Eclipse in place of Freedom Studio as there is not a new Freedom Studio project that targets the HiFive1 board, and the updated Freedom Studio version didn't work with this project any more anyway.
Richard Barry d435a7b62d Move the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns.
Richard Barry 4922cff4ce Add IAR demo for the SiFive RISC-V HiFive Rev B board.
Richard Barry f6edf4adf9 Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.
Richard Barry 96e61a10a5 Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release.
Richard Barry d4216903d9 Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress.
Richard Barry 71d9450836 RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress.
Richard Barry dbac79045c Formatting changes only.
Richard Barry dbbebbfcbc RISC-V-RV32_SiFive_HiFive1_GCC project is now also building the FreeRTOS kernel code - but not using it yet - still a work in progress.
Richard Barry 9bb072a2ab Base project to replace existing Freedom Studio project using latest Freedom Studio project format - builds and executes but does not yet include RTOS code.
Richard Barry fd118f1888 Minor formatting change in comment only.
Yuhui.Zheng eb5c60c60b Update FreeRTOS.h with the version in GitHub. This is also to test submodule.
Yuhui.Zheng 0fe36e497d Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.
Yuhui.Zheng 35bc9d7938 Revert 2728. Not because the files are still needed, but because we want to test out submodule.
Before further updating project files in GitHub, keeping an additional copy.
Yuhui.Zheng f001126ea8 Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.
Yuhui.Zheng 9052882500 Adding tickless hooks to GCC/ARM_CRx_No_GIC port.
Richard Barry 80c1cb5de1 Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR.
Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
Yuhui.Zheng c217b68d38 sync from github to svn: this version of atomic.h does not have compiler specific symbols. compiler specific optimization is to be merged in each port/<compiler>/<arch> directory.
Yuhui.Zheng 6f958bbf80 sync from github to svn: Xtensa GCC as-is.
Yuhui.Zheng 1c5fcc7f05 sync from github to svn: Wiced_CY for AFR Cypress ports.
Yuhui.Zheng 74df636c78 sync from github to svn: documentation for RISC-V. This may be a temporary parking location.
Yuhui.Zheng cc0aee651e sync from github to svn: Renasas/RX100 #pragma _VECT()
Richard Barry da3d370ff7 RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
Richard Barry 96bad0f6c3 Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL.
Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks.
Richard Barry ab41d89285 Add IAR RISC-V port to SVN - a work in progress.
Yuhui Zheng 2b546b1984 Atollic project update for CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC, GCC port.
Richard Barry 973a4f9869 Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
Richard Barry 7d285f3dcb + Moved the History.txt file from the website git repo into the source code SVN repo.
+ Added xTaskCatchUpTicks() which corrects the tick count value after the application code has held interrupts disabled for an extended period.
+ Updated the xTaskResumeAll() implementation so it uses the new xTaskCatchUpTicks() function mentioned above to unwind ticks that were pended while the scheduler was suspended.
+ Various maintenance on the message buffer, stream buffer and abort delay demos.
+ Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it has same type as variables it is compared to, and therefore also rename the variable xPendingTicks.
+ Correct spelling mistake within a comment that was common to all the ARMv7-M ports.
Richard Barry 72af51cd86 Starting point for IAR RISC-V project created some time ago - checking in now so it can be completed - currently work in progress.
Richard Barry 5352cb4f45 Tidy up Win32 port layer - include addition of new variable that prevents recursive attempts to obtain a mutex when the trace recorder is used inside an interrupt.
Gaurav Aggarwal b1e35551c4 Update the FreeRTOS version number in task.h
Gaurav Aggarwal 6bad7d2055 Add the default definition of configPRECONDITION to FreeRTOS.h.
This is needed for CBMC proofs.
Richard Barry b4c06085e1 Files as per 190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview interim release.
Richard Barry b24ab46d39 Delete obsolete makefiles that were causing confusion from RISC-V-Qemu-sifive_e-FreedomStudio demo.
Richard Barry 10b7b52995 Remove unnecessary include path from the MQTT demo.
Gaurav Aggarwal 38b6553abd Cosmetic changes in the MQTT demo - mostly comment updates.
Richard Barry fe4511b35e Continued to work on the MQTT demo project.
A few review comments added into the MQTT implementation.
Richard Barry 53842d4cac Remove the simple UDP client/server tasks from the MQTT demo as the demo's network connection can be tested more easily just by pinging it.
Tidy up the iot_config.h header files a little.
Gaurav Aggarwal 95f60318d5 Cosmetic changes in the MQTT demo
- Fix warnings in the MQTT code.
- Update comments in the iot_config.h.
Richard Barry 17b18c8b7e Reduce warning level in Visual Studio project as it generates lots of warnings in the library files.
Richard Barry d1dd8da12e Revert a couple of changes in Win32 demo that should not have been checked in.
Gaurav Aggarwal 05e7d9cc08 Remove dependency on secure sockets
Network interface implementation for FreeRTOS now directly calls into
FreeRTOS+TCP instead of going via secure sockets.
Gaurav Aggarwal 68fd276886 Remove IotMqtt_Assert( pTaskPool == IOT_SYSTEM_TASKPOOL ) from MQTT code
The cut down version of the task pool has only one task pool, namely,
system task pool. All the task pool API functions accept NULL as a
valid parameter for IotTaskPool_t and use the system task pool when
NULL is passed for the system task pool.

IOT_SYSTEM_TASKPOOL is defined to NULL to use system task pool and
therefore the above assert is no longer valid.
Gaurav Aggarwal 8ea501ef11 Update projects to use the new directory name
IotTaskPool_GetSystemTaskPool has been removed from the cut down version
of the task pool. define IOT_SYSTEM_TASKPOOL to NULL so that the MQTT library
builds successfully.

Use the new #defines in the iot_config.h.