diff --git a/.github/scripts/core_checker.py b/.github/scripts/core_checker.py index fadf7b5154..10f15a5b0b 100755 --- a/.github/scripts/core_checker.py +++ b/.github/scripts/core_checker.py @@ -48,6 +48,7 @@ FREERTOS_IGNORED_EXTENSIONS = [ '.config', '.cpp', '.cproj', + '.cproject', '.crun', '.css', '.csv', @@ -120,6 +121,7 @@ FREERTOS_IGNORED_EXTENSIONS = [ '.la', '.launch', '.lcf', + '.ld', '.lds', '.lib', '.lk1', @@ -172,6 +174,7 @@ FREERTOS_IGNORED_EXTENSIONS = [ '.pref', '.prefs', '.prj', + '.project', '.properties', '.ps1', '.ptf', @@ -254,12 +257,16 @@ FREERTOS_IGNORED_PATTERNS = [ r'.*CMSIS.*', r'.*/makefile', r'.*/Makefile', + r'.*/printf-stdarg\.c.*', + r'.*/startup.*', r'.*/trcConfig\.h.*', r'.*/trcConfig\.c.*', r'.*/trcSnapshotConfig\.h.*' ] FREERTOS_IGNORED_FILES = [ + '.cproject', + '.project', 'fyi-another-way-to-ignore-file.txt', 'mbedtls_config.h', 'requirements.txt', diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.ewt deleted file mode 100644 index b3df2a49f8..0000000000 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.ewt +++ /dev/null @@ -1,1363 +0,0 @@ - - - 3 - - Debug - - ARM - - 1 - - C-STAT - 262 - - 262 - - 0 - - 1 - 600 - 1 - 2 - 0 - 1 - 100 - - - 1.6.2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - Blinky Demo - - $PROJ_DIR$\main_blinky.c - - - - FreeRTOS Kernel - - include - - $PROJ_DIR$\..\..\Source\include\event_groups.h - - - $PROJ_DIR$\..\..\Source\include\message_buffer.h - - - $PROJ_DIR$\..\..\Source\include\queue.h - - - $PROJ_DIR$\..\..\Source\include\semphr.h - - - $PROJ_DIR$\..\..\Source\include\stream_buffer.h - - - $PROJ_DIR$\..\..\Source\include\task.h - - - $PROJ_DIR$\..\..\Source\include\timers.h - - - - Portable - - IAR - - ARM_CM3 - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - - - MemMang - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c - - - - - $PROJ_DIR$\..\..\Source\event_groups.c - - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\stream_buffer.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - $PROJ_DIR$\..\..\Source\timers.c - - - - Full Demo - - Standard Demo Tasks - - $PROJ_DIR$\..\Common\Minimal\AbortDelay.c - - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\blocktim.c - - - $PROJ_DIR$\..\Common\Minimal\countsem.c - - - $PROJ_DIR$\..\Common\Minimal\death.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c - - - $PROJ_DIR$\..\Common\Minimal\GenQTest.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\..\Common\Minimal\IntQueue.c - - - $PROJ_DIR$\IntQueueTimer.c - - - $PROJ_DIR$\..\Common\Minimal\IntSemTest.c - - - $PROJ_DIR$\..\Common\Minimal\MessageBufferAMP.c - - - $PROJ_DIR$\..\Common\Minimal\MessageBufferDemo.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\..\Common\Minimal\QPeek.c - - - $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c - - - $PROJ_DIR$\..\Common\Minimal\QueueSet.c - - - $PROJ_DIR$\..\Common\Minimal\QueueSetPolling.c - - - $PROJ_DIR$\..\Common\Minimal\recmutex.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\..\Common\Minimal\StaticAllocation.c - - - $PROJ_DIR$\..\Common\Minimal\StreamBufferDemo.c - - - $PROJ_DIR$\..\Common\Minimal\StreamBufferInterrupt.c - - - $PROJ_DIR$\..\Common\Minimal\TaskNotify.c - - - $PROJ_DIR$\..\Common\Minimal\TaskNotifyArray.c - - - $PROJ_DIR$\..\Common\Minimal\TimerDemo.c - - - - $PROJ_DIR$\main_full.c - - - - System files - - $PROJ_DIR$\startup_ewarm.c - - - - $PROJ_DIR$\FreeRTOSConfig.h - - - $PROJ_DIR$\main.c - - diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/CMSDK_CM3.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/CMSDK_CM3.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/CMSDK_CM3.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/CMSDK_CM3.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/SMM_MPS2.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/SMM_MPS2.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/SMM_MPS2.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/SMM_MPS2.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis_compiler.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_compiler.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis_compiler.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_compiler.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000000..77f8fdbb2f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_gcc.h @@ -0,0 +1,2126 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_iccarm.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis_iccarm.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_iccarm.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis_version.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_version.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/cmsis_version.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/cmsis_version.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/core_cm3.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/core_cm3.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/core_cm3.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/core_cm3.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/mpu_armv7.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/mpu_armv7.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/CMSIS/mpu_armv7.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/CMSIS/mpu_armv7.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/FreeRTOSConfig.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h index 20468bb8b8..fc705e6b3d 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h @@ -45,7 +45,7 @@ #define configCPU_CLOCK_HZ ( ( unsigned long ) 25000000 ) #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 60 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 12 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 @@ -54,7 +54,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configCHECK_FOR_STACK_OVERFLOW 2 -#define configMALLOC_FAILED_HOOK 1 +#define configUSE_MALLOC_FAILED_HOOK 1 #define configUSE_QUEUE_SETS 1 #define configUSE_COUNTING_SEMAPHORES 1 @@ -116,7 +116,7 @@ allowable margin of error on slower processors (slower than the Win32 machine on which the test is developed). */ #define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 4 -#ifdef __ICCARM__ /* Prevent C code being included in asm files. */ +#ifndef __IASMARM__ /* Prevent C code being included in IAR asm files. */ void vAssertCalled( const char *pcFileName, uint32_t ulLine ); #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); #endif diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Instructions.url b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Instructions.url new file mode 100644 index 0000000000..c9cd124767 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/Instructions.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/IntQueueTimer.c rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/IntQueueTimer.h rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.cproject b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.cproject new file mode 100644 index 0000000000..ab98394712 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.cproject @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project new file mode 100644 index 0000000000..da12b7d9b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.project @@ -0,0 +1,109 @@ + + + FreeRTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + CommonDemoSource + 2 + FREERTOS_ROOT/Demo/Common/Minimal + + + FreeRTOS_kernel + 2 + FREERTOS_ROOT/Source + + + Source + 2 + virtual:/virtual + + + Source/FreeRTOSConfig.h + 1 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/FreeRTOSConfig.h + + + Source/IntQueueTimer.c + 1 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.c + + + Source/IntQueueTimer.h + 1 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/IntQueueTimer.h + + + Source/main.c + 1 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c + + + Source/main_blinky.c + 1 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c + + + Source/main_full.c + 1 + FREERTOS_ROOT/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c + + + + + 1638931119117 + FreeRTOS_kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1638931119125 + FreeRTOS_kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1638931142581 + FreeRTOS_kernel/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CM3 + + + + + + FREERTOS_ROOT + $%7BPARENT-4-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.settings/language.settings.xml b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.settings/language.settings.xml new file mode 100644 index 0000000000..461e08f2f2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/FreeRTOSDemo Default.launch b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/FreeRTOSDemo Default.launch new file mode 100644 index 0000000000..8a009ddf80 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/FreeRTOSDemo Default.launch @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile new file mode 100644 index 0000000000..33e0cdde62 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile @@ -0,0 +1,123 @@ +OUTPUT_DIR := ./output +IMAGE := RTOSDemo.out +SUB_MAKEFILE_DIR = ./library-makefiles + +# The directory that contains the /source and /demo sub directories. +FREERTOS_ROOT = ./../../../../ + +CC = arm-none-eabi-gcc +LD = arm-none-eabi-gcc +SIZE = arm-none-eabi-size +MAKE = make + + +CFLAGS += $(INCLUDE_DIRS) -nostartfiles -ffreestanding -mthumb -mcpu=cortex-m3 \ + -Wall -Wextra -g3 -O0 -ffunction-sections -fdata-sections \ + -MMD -MP -MF"$(@:%.o=%.d)" -MT $@ + +# +# Kernel build. +# +KERNEL_DIR = $(FREERTOS_ROOT)/Source +KERNEL_PORT_DIR += $(KERNEL_DIR)/portable/GCC/ARM_CM3 +INCLUDE_DIRS += -I$(KERNEL_DIR)/include \ + -I$(KERNEL_PORT_DIR) +VPATH += $(KERNEL_DIR) $(KERNEL_PORT_DIR) $(KERNEL_DIR)/portable/MemMang +SOURCE_FILES += $(KERNEL_DIR)/tasks.c +SOURCE_FILES += $(KERNEL_DIR)/list.c +SOURCE_FILES += $(KERNEL_DIR)/queue.c +SOURCE_FILES += $(KERNEL_DIR)/timers.c +SOURCE_FILES += $(KERNEL_DIR)/event_groups.c +SOURCE_FILES += $(KERNEL_DIR)/stream_buffer.c +SOURCE_FILES += $(KERNEL_DIR)/portable/MemMang/heap_4.c +SOURCE_FILES += $(KERNEL_DIR)/portable/GCC/ARM_CM3/port.c + +# +# Common demo files for the "full" build, as opposed to the "blinky" build - +# these files are build by all the FreeRTOS kernel demos. +# +DEMO_ROOT = $(FREERTOS_ROOT)/Demo +COMMON_DEMO_FILES = $(DEMO_ROOT)/Common/Minimal +INCLUDE_DIRS += -I$(DEMO_ROOT)/Common/include +VPATH += $(COMMON_DEMO_FILES) +SOURCE_FILES += (COMMON_DEMO_FILES)/AbortDelay.c +SOURCE_FILES += (COMMON_DEMO_FILES)/BlockQ.c +SOURCE_FILES += (COMMON_DEMO_FILES)/blocktim.c +SOURCE_FILES += (COMMON_DEMO_FILES)/countsem.c +SOURCE_FILES += (COMMON_DEMO_FILES)/death.c +SOURCE_FILES += (COMMON_DEMO_FILES)/dynamic.c +SOURCE_FILES += (COMMON_DEMO_FILES)/EventGroupsDemo.c +SOURCE_FILES += (COMMON_DEMO_FILES)/GenQTest.c +SOURCE_FILES += (COMMON_DEMO_FILES)/integer.c +SOURCE_FILES += (COMMON_DEMO_FILES)/IntQueue.c +SOURCE_FILES += (COMMON_DEMO_FILES)/IntQueueTimer.c +SOURCE_FILES += (COMMON_DEMO_FILES)/IntSemTest.c +SOURCE_FILES += (COMMON_DEMO_FILES)/MessageBufferAMP.c +SOURCE_FILES += (COMMON_DEMO_FILES)/MessageBufferDemo.c +SOURCE_FILES += (COMMON_DEMO_FILES)/PollQ.c +SOURCE_FILES += (COMMON_DEMO_FILES)/QPeek.c +SOURCE_FILES += (COMMON_DEMO_FILES)/QueueOverwrite.c +SOURCE_FILES += (COMMON_DEMO_FILES)/QueueSet.c +SOURCE_FILES += (COMMON_DEMO_FILES)/QueueSetPolling.c +SOURCE_FILES += (COMMON_DEMO_FILES)/recmutex.c +SOURCE_FILES += (COMMON_DEMO_FILES)/semtest.c +SOURCE_FILES += (COMMON_DEMO_FILES)/StaticAllocation.c +SOURCE_FILES += (COMMON_DEMO_FILES)/StreamBufferDemo.c +SOURCE_FILES += (COMMON_DEMO_FILES)/StreamBufferInterrupt.c +SOURCE_FILES += (COMMON_DEMO_FILES)/TaskNotify.c +SOURCE_FILES += (COMMON_DEMO_FILES)/TaskNotifyArray.c +SOURCE_FILES += (COMMON_DEMO_FILES)/TimerDemo.c + +# +# Application entry point. main_blinky is self contained. main_full builds +# the above common demo (and test) files too. +# +DEMO_PROJECT = $(DEMO_ROOT)/CORTEX_MPS2_QEMU_IAR_GCC +VPATH += $(DEMO_PROJECT) +INCLUDE_DIRS += -I$(DEMO_PROJECT) -I$(DEMO_PROJECT)/CMSIS +SOURCE_FILES += (DEMO_PROJECT)/main.c +SOURCE_FILES += (DEMO_PROJECT)/main_blinky.c +SOURCE_FILES += (DEMO_PROJECT)/main_full.c +SOURCE_FILES += ./startup_gcc.c +# Lightweight print formatting to use in place of the heavier GCC equivalent. +SOURCE_FILES += ./printf-stdarg.c + +#Create a list of object files with the desired output directory path. +OBJS = $(SOURCE_FILES:%.c=%.o) +OBJS_NO_PATH = $(notdir $(OBJS)) +OBJS_OUTPUT = $(OBJS_NO_PATH:%.o=$(OUTPUT_DIR)/%.o) + +#Create a list of dependency files with the desired output directory path. +DEP_FILES := $(SOURCE_FILES:%.c=$(OUTPUT_DIR)/%.d) +DEP_FILES_NO_PATH = $(notdir $(DEP_FILES)) +DEP_OUTPUT = $(DEP_FILES_NO_PATH:%.d=$(OUTPUT_DIR)/%.d) + +all: $(OUTPUT_DIR)/$(IMAGE) + +%.o : %.c +$(OUTPUT_DIR)/%.o : %.c $(OUTPUT_DIR)/%.d Makefile + $(CC) $(CFLAGS) -c $< -o $@ + +$(OUTPUT_DIR)/$(IMAGE): ./mps2_m3.ld $(OBJS_OUTPUT) Makefile + @echo "" + @echo "" + @echo "--- Final linking ---" + @echo "" + $(LD) $(OBJS_OUTPUT) $(CFLAGS) -Xlinker --gc-sections -Xlinker -T ./mps2_m3.ld \ + -Xlinker -Map=$(OUTPUT_DIR)/RTOSDemo.map -specs=nano.specs \ + -specs=nosys.specs -specs=rdimon.specs -o $(OUTPUT_DIR)/$(IMAGE) + $(SIZE) $(OUTPUT_DIR)/$(IMAGE) + +$(DEP_OUTPUT): +include $(wildcard $(DEP_OUTPUT)) + +clean: + rm -f $(OUTPUT_DIR)/$(IMAGE) $(OUTPUT_DIR)/*.o $(OUTPUT_DIR)/*.d + +#use "make print-[VARIABLE_NAME] to print the value of a variable generated by +#this makefile. +print-% : ; @echo $* = $($*) + +.PHONY: all clean + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/mps2_m3.ld b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/mps2_m3.ld new file mode 100644 index 0000000000..1b0c4a34c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/mps2_m3.ld @@ -0,0 +1,98 @@ +/* + * FreeRTOS V202111.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +MEMORY +{ + FLASH (xr) : ORIGIN = 0x00000000, LENGTH = 4M /* to 0x00003FFF = 0x007FFFFF*/ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 4M /* to 0x21FFFFFF = 0xFFFFFF */ +} +ENTRY(Reset_Handler) + +_Min_Heap_Size = 0x8 ; /* Not used as building heap_4.c */ +_Min_Stack_Size = 0x400 ; /* Required amount of stack. Used by main(), then re-used as the interrupt stack after the kernel starts. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.isr_vector)) + . = ALIGN(4); + } > FLASH + + .text : + { + *(.text) + *(.rodata*) + *(.constdata*) + _etext = .; + _sidata = .; + } > FLASH + + .data : + { + . = ALIGN(8); + _data = .; + _sdata = .; + *(vtable) + *(.data) + _edata = .; + } > RAM + + .bss : + { + . = ALIGN(8); + _bss = .; + _sbss = .; + *(.bss) + _ebss = .; + } > RAM + + .heap : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + _heap_bottom = .; + . = . + _Min_Heap_Size; + _heap_top = .; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - _Min_Stack_Size; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _heap_top, "region RAM overflowed with stack") + +} diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/output/placeholder.txt b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/output/placeholder.txt new file mode 100644 index 0000000000..a3fb3f1613 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/output/placeholder.txt @@ -0,0 +1,3 @@ +File included to ensure the "output" directory is not empty, and can therefore +be checked into Git. This prevents the necessity to have a cross platform +method of creating the directory from within the makefile. diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/printf-stdarg.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/printf-stdarg.c new file mode 100644 index 0000000000..e7fc1c742d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/printf-stdarg.c @@ -0,0 +1,312 @@ +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* + putchar is the only external dependency for this file, + if you have a working putchar, leave it commented out. + If not, uncomment the define below and + replace outbyte(c) by your own function call. + +*/ + +#include + +#define UART0_ADDRESS ( 0x40004000UL ) +#define UART0_DATA ( * ( ( ( volatile unsigned int * )( UART0_ADDRESS + 0UL ) ) ) ) +#define putchar(c) UART0_DATA = c + +static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen ); + +static void printchar(char **str, int c, char *buflimit) +{ + if (str) { + if( buflimit == ( char * ) 0 ) { + /* Limit of buffer not known, write charater to buffer. */ + **str = (char)c; + ++(*str); + } + else if( ( ( unsigned long ) *str ) < ( ( unsigned long ) buflimit ) ) { + /* Within known limit of buffer, write character. */ + **str = (char)c; + ++(*str); + } + } + else + { + putchar(c); + } +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad, char *buflimit) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar, buflimit); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string, buflimit); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar, buflimit); + ++pc; + } + + return pc; +} + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 + +static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase, char *buflimit) +{ + char print_buf[PRINT_BUF_LEN]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned int u = (unsigned int)i; + + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad, buflimit); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + u = (unsigned int)-i; + } + + s = print_buf + PRINT_BUF_LEN-1; + *s = '\0'; + + while (u) { + t = (unsigned int)u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = (char)(t + '0'); + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-', buflimit); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad, buflimit); +} + +static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen ) +{ + register int width, pad; + register int pc = 0; + char scr[2], *buflimit; + + if( buflen == 0 ){ + buflimit = ( char * ) 0; + } + else { + /* Calculate the last valid buffer space, leaving space for the NULL + terminator. */ + buflimit = ( *out ) + ( buflen - 1 ); + } + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad, buflimit); + continue; + } + if( *format == 'd' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a', buflimit); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a', buflimit); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A', buflimit); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a', buflimit); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad, buflimit); + continue; + } + } + else { + out: + printchar (out, *format, buflimit); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} + +int printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return tiny_print( 0, format, args, 0 ); +} + +int sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return tiny_print( &out, format, args, 0 ); +} + + +int snprintf( char *buf, unsigned int count, const char *format, ... ) +{ + va_list args; + + ( void ) count; + + va_start( args, format ); + return tiny_print( &buf, format, args, count ); +} + + +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]; + + mi = (1 << (bs-1)) + 1; + printf("%s\n", ptr); + printf("printf test\n"); + printf("%s is null pointer\n", np); + printf("%d = 5\n", i); + printf("%d = - max int\n", mi); + printf("char %c = 'a'\n", 'a'); + printf("hex %x = ff\n", 0xff); + printf("hex %02x = 00\n", 0); + printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf("%d %s(s)%", 0, "message"); + printf("\n"); + printf("%d %s(s) with %%\n", 0, "message"); + sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); + sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); + sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); + sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); + sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); + sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); + sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); + sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif + + +/* To keep linker happy. */ +int write( int i, char* c, int n) +{ + (void)i; + (void)n; + (void)c; + return 0; +} + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c new file mode 100644 index 0000000000..7a51bccb09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c @@ -0,0 +1,168 @@ +/* + * FreeRTOS V202111.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include +#include + +/* UART peripheral register addresses and bits. */ +#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) +#define UART_DR( baseaddr ) ( *( uint32_t * ) ( baseaddr ) ) +#define UART_STATE( baseaddr ) ( *( uint32_t * ) ( baseaddr + 4 ) ) +#define UART_STATE_TXFULL ( 1 << 0 ) + +typedef struct UART_t +{ + volatile uint32_t DATA; + volatile uint32_t STATE; + volatile uint32_t CTRL; + volatile uint32_t INTSTATUS; + volatile uint32_t BAUDDIV; +} UART_t; + + +/* FreeRTOS interrupt handlers. */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); +extern void xPortSysTickHandler( void ); +extern void TIMER0_Handler( void ); +extern void TIMER1_Handler( void ); + +/* Exception handlers. */ +static void HardFault_Handler( void ) __attribute__( ( naked ) ); +static void Default_Handler( void ) __attribute__( ( naked ) ); +void Reset_Handler( void ); + +extern int main( void ); +extern uint32_t _estack; + +/* Vector table. */ +const uint32_t* isr_vector[] __attribute__((section(".isr_vector"))) = +{ + ( uint32_t * ) &_estack, + ( uint32_t * ) &Reset_Handler, // Reset -15 + ( uint32_t * ) &Default_Handler, // NMI_Handler -14 + ( uint32_t * ) &HardFault_Handler, // HardFault_Handler -13 + ( uint32_t * ) &Default_Handler, // MemManage_Handler -12 + ( uint32_t * ) &Default_Handler, // BusFault_Handler -11 + ( uint32_t * ) &Default_Handler, // UsageFault_Handler -10 + 0, // reserved + 0, // reserved + 0, // reserved + 0, // reserved -6 + ( uint32_t * ) &vPortSVCHandler, // SVC_Handler -5 + ( uint32_t * ) &Default_Handler, // DebugMon_Handler -4 + 0, // reserved + ( uint32_t * ) &xPortPendSVHandler, // PendSV handler -2 + ( uint32_t * ) &xPortSysTickHandler,// SysTick_Handler -1 + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ( uint32_t * ) TIMER0_Handler, // Timer 0 + ( uint32_t * ) TIMER1_Handler, // Timer 1 + 0, + 0, + 0, + 0, // Ethernet 13 +}; + +void Reset_Handler( void ) +{ + main(); +} + +/* Variables used to store the value of registers at the time a hardfault + * occurs. These are volatile to try and prevent the compiler/linker optimising + * them away as the variables never actually get used. */ +volatile uint32_t r0; +volatile uint32_t r1; +volatile uint32_t r2; +volatile uint32_t r3; +volatile uint32_t r12; +volatile uint32_t lr; /* Link register. */ +volatile uint32_t pc; /* Program counter. */ +volatile uint32_t psr;/* Program status register. */ + +/* Called from the hardfault handler to provide information on the processor + * state at the time of the fault. + */ +void prvGetRegistersFromStack( uint32_t *pulFaultStackAddress ) +{ + r0 = pulFaultStackAddress[ 0 ]; + r1 = pulFaultStackAddress[ 1 ]; + r2 = pulFaultStackAddress[ 2 ]; + r3 = pulFaultStackAddress[ 3 ]; + + r12 = pulFaultStackAddress[ 4 ]; + lr = pulFaultStackAddress[ 5 ]; + pc = pulFaultStackAddress[ 6 ]; + psr = pulFaultStackAddress[ 7 ]; + + printf( "Calling prvGetRegistersFromStack() from fault handler" ); + fflush( stdout ); + + /* When the following line is hit, the variables contain the register values. */ + for( ;; ); +} + + +void Default_Handler( void ) +{ + __asm volatile + ( + ".align 8 \n" + " ldr r3, NVIC_INT_CTRL_CONST \n" /* Load the address of the interrupt control register into r3. */ + " ldr r2, [r3, #0] \n" /* Load the value of the interrupt control register into r2. */ + " uxtb r2, r2 \n" /* The interrupt number is in the least significant byte - clear all other bits. */ + "Infinite_Loop: \n" /* Sit in an infinite loop - the number of the executing interrupt is held in r2. */ + " b Infinite_Loop \n" + ".align 4 \n" + "NVIC_INT_CTRL_CONST: .word 0xe000ed04 \n" + ); +} + +void HardFault_Handler( void ) +{ + __asm volatile + ( + ".align 8 \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, [r0, #24] \n" + " ldr r2, handler2_address_const \n" + " bx r2 \n" + " handler2_address_const: .word prvGetRegistersFromStack \n" + ); +} + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/MPS2.icf b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/MPS2.icf similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/MPS2.icf rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/MPS2.icf diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewd similarity index 95% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.ewd rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewd index e9f2df2f89..eb404c3fa8 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewd @@ -88,7 +88,7 @@ - - BILINK - 0 - - Blinky Demo - $PROJ_DIR$\main_blinky.c + $PROJ_DIR$\..\..\main_blinky.c @@ -1071,25 +1058,25 @@ include - $PROJ_DIR$\..\..\Source\include\event_groups.h + $PROJ_DIR$\..\..\..\..\Source\include\event_groups.h - $PROJ_DIR$\..\..\Source\include\message_buffer.h + $PROJ_DIR$\..\..\..\..\Source\include\message_buffer.h - $PROJ_DIR$\..\..\Source\include\queue.h + $PROJ_DIR$\..\..\..\..\Source\include\queue.h - $PROJ_DIR$\..\..\Source\include\semphr.h + $PROJ_DIR$\..\..\..\..\Source\include\semphr.h - $PROJ_DIR$\..\..\Source\include\stream_buffer.h + $PROJ_DIR$\..\..\..\..\Source\include\stream_buffer.h - $PROJ_DIR$\..\..\Source\include\task.h + $PROJ_DIR$\..\..\..\..\Source\include\task.h - $PROJ_DIR$\..\..\Source\include\timers.h + $PROJ_DIR$\..\..\..\..\Source\include\timers.h @@ -1099,37 +1086,37 @@ ARM_CM3 - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM3\port.c - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM3\portasm.s MemMang - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + $PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_4.c - $PROJ_DIR$\..\..\Source\event_groups.c + $PROJ_DIR$\..\..\..\..\Source\event_groups.c - $PROJ_DIR$\..\..\Source\list.c + $PROJ_DIR$\..\..\..\..\Source\list.c - $PROJ_DIR$\..\..\Source\queue.c + $PROJ_DIR$\..\..\..\..\Source\queue.c - $PROJ_DIR$\..\..\Source\stream_buffer.c + $PROJ_DIR$\..\..\..\..\Source\stream_buffer.c - $PROJ_DIR$\..\..\Source\tasks.c + $PROJ_DIR$\..\..\..\..\Source\tasks.c - $PROJ_DIR$\..\..\Source\timers.c + $PROJ_DIR$\..\..\..\..\Source\timers.c @@ -1137,89 +1124,89 @@ Standard Demo Tasks - $PROJ_DIR$\..\Common\Minimal\AbortDelay.c + $PROJ_DIR$\..\..\..\Common\Minimal\AbortDelay.c - $PROJ_DIR$\..\Common\Minimal\BlockQ.c + $PROJ_DIR$\..\..\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\..\Common\Minimal\blocktim.c + $PROJ_DIR$\..\..\..\Common\Minimal\blocktim.c - $PROJ_DIR$\..\Common\Minimal\countsem.c + $PROJ_DIR$\..\..\..\Common\Minimal\countsem.c - $PROJ_DIR$\..\Common\Minimal\death.c + $PROJ_DIR$\..\..\..\Common\Minimal\death.c - $PROJ_DIR$\..\Common\Minimal\dynamic.c + $PROJ_DIR$\..\..\..\Common\Minimal\dynamic.c - $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\EventGroupsDemo.c - $PROJ_DIR$\..\Common\Minimal\GenQTest.c + $PROJ_DIR$\..\..\..\Common\Minimal\GenQTest.c - $PROJ_DIR$\..\Common\Minimal\integer.c + $PROJ_DIR$\..\..\..\Common\Minimal\integer.c - $PROJ_DIR$\..\Common\Minimal\IntQueue.c + $PROJ_DIR$\..\..\..\Common\Minimal\IntQueue.c - $PROJ_DIR$\IntQueueTimer.c + $PROJ_DIR$\..\..\IntQueueTimer.c - $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + $PROJ_DIR$\..\..\..\Common\Minimal\IntSemTest.c - $PROJ_DIR$\..\Common\Minimal\MessageBufferAMP.c + $PROJ_DIR$\..\..\..\Common\Minimal\MessageBufferAMP.c - $PROJ_DIR$\..\Common\Minimal\MessageBufferDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\MessageBufferDemo.c - $PROJ_DIR$\..\Common\Minimal\PollQ.c + $PROJ_DIR$\..\..\..\Common\Minimal\PollQ.c - $PROJ_DIR$\..\Common\Minimal\QPeek.c + $PROJ_DIR$\..\..\..\Common\Minimal\QPeek.c - $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + $PROJ_DIR$\..\..\..\Common\Minimal\QueueOverwrite.c - $PROJ_DIR$\..\Common\Minimal\QueueSet.c + $PROJ_DIR$\..\..\..\Common\Minimal\QueueSet.c - $PROJ_DIR$\..\Common\Minimal\QueueSetPolling.c + $PROJ_DIR$\..\..\..\Common\Minimal\QueueSetPolling.c - $PROJ_DIR$\..\Common\Minimal\recmutex.c + $PROJ_DIR$\..\..\..\Common\Minimal\recmutex.c - $PROJ_DIR$\..\Common\Minimal\semtest.c + $PROJ_DIR$\..\..\..\Common\Minimal\semtest.c - $PROJ_DIR$\..\Common\Minimal\StaticAllocation.c + $PROJ_DIR$\..\..\..\Common\Minimal\StaticAllocation.c - $PROJ_DIR$\..\Common\Minimal\StreamBufferDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\StreamBufferDemo.c - $PROJ_DIR$\..\Common\Minimal\StreamBufferInterrupt.c + $PROJ_DIR$\..\..\..\Common\Minimal\StreamBufferInterrupt.c - $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + $PROJ_DIR$\..\..\..\Common\Minimal\TaskNotify.c - $PROJ_DIR$\..\Common\Minimal\TaskNotifyArray.c + $PROJ_DIR$\..\..\..\Common\Minimal\TaskNotifyArray.c - $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + $PROJ_DIR$\..\..\..\Common\Minimal\TimerDemo.c - $PROJ_DIR$\main_full.c + $PROJ_DIR$\..\..\main_full.c @@ -1229,9 +1216,9 @@ - $PROJ_DIR$\FreeRTOSConfig.h + $PROJ_DIR$\..\..\FreeRTOSConfig.h - $PROJ_DIR$\main.c + $PROJ_DIR$\..\..\main.c diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt new file mode 100644 index 0000000000..5e4ad93a2a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.ewt @@ -0,0 +1,1597 @@ + + + 3 + + Debug + + ARM + + 1 + + C-STAT + 515 + + 515 + + 0 + + 1 + 600 + 1 + 2 + 0 + 1 + 100 + Debug\C-STAT + + + 2.3.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RuntimeChecking + 0 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + Blinky Demo + + $PROJ_DIR$\main_blinky.c + + + + FreeRTOS Kernel + + include + + $PROJ_DIR$\..\..\Source\include\event_groups.h + + + $PROJ_DIR$\..\..\Source\include\message_buffer.h + + + $PROJ_DIR$\..\..\Source\include\queue.h + + + $PROJ_DIR$\..\..\Source\include\semphr.h + + + $PROJ_DIR$\..\..\Source\include\stream_buffer.h + + + $PROJ_DIR$\..\..\Source\include\task.h + + + $PROJ_DIR$\..\..\Source\include\timers.h + + + + Portable + + IAR + + ARM_CM3 + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\stream_buffer.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + Full Demo + + Standard Demo Tasks + + $PROJ_DIR$\..\Common\Minimal\AbortDelay.c + + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\countsem.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\IntQueueTimer.c + + + $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + + + $PROJ_DIR$\..\Common\Minimal\MessageBufferAMP.c + + + $PROJ_DIR$\..\Common\Minimal\MessageBufferDemo.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\QPeek.c + + + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\QueueSet.c + + + $PROJ_DIR$\..\Common\Minimal\QueueSetPolling.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\..\Common\Minimal\StaticAllocation.c + + + $PROJ_DIR$\..\Common\Minimal\StreamBufferDemo.c + + + $PROJ_DIR$\..\Common\Minimal\StreamBufferInterrupt.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotifyArray.c + + + $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + + + + $PROJ_DIR$\main_full.c + + + + System files + + $PROJ_DIR$\startup_ewarm.c + + + + $PROJ_DIR$\FreeRTOSConfig.h + + + $PROJ_DIR$\main.c + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.eww similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/RTOSDemo.eww rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/RTOSDemo.eww diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/startup_ewarm.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/startup_ewarm.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/startup_ewarm.c rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/startup_ewarm.c index 96c804e53e..d10cd6aec9 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/startup_ewarm.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/iar/startup_ewarm.c @@ -60,7 +60,6 @@ extern void __iar_program_start(void); extern void xPortPendSVHandler(void); extern void xPortSysTickHandler(void); extern void vPortSVCHandler(void); -extern void vDualTimer1Handler( void ); extern void TIMER0_Handler( void ); extern void TIMER1_Handler( void ); diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main.c rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c index ac80f00671..80b1d47692 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main.c @@ -26,6 +26,9 @@ /****************************************************************************** + * See https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html for + * instructions. + * * This project provides two demo applications. A simple blinky style project, * and a more comprehensive test and demo application. The * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY constant, defined in this file, is used to @@ -36,10 +39,11 @@ * This file implements the code that is not demo specific, including the * hardware setup and FreeRTOS hook functions. * - * Use the following command to start the application running in a way that - * enables the IAR IDE to connect and debug: + * Running in QEMU: + * Use the following commands to start the application running in a way that + * enables the debugger to connect, omit the "-s -S" to run the project without + * the debugger: * qemu-system-arm -machine mps2-an385 -cpu cortex-m3 -kernel [path-to]/RTOSDemo.out -nographic -serial stdio -semihosting -semihosting-config enable=on,target=native -s -S - * and set IAR connect GDB server to "localhost,1234" in project debug options. */ /* FreeRTOS includes. */ @@ -94,6 +98,10 @@ static void prvUARTInit( void ); void main( void ) { + /* See https://www.freertos.org/freertos-on-qemu-mps2-an385-model.html for + instructions. */ + + /* Hardware initialisation. printf() output uses the UART for IO. */ prvUARTInit(); @@ -126,7 +134,9 @@ void vApplicationMallocFailedHook( void ) (although it does not provide information on how the remaining heap might be fragmented). See http://www.freertos.org/a00111.html for more information. */ - vAssertCalled( __FILE__, __LINE__ ); + printf( "\r\n\r\nMalloc failed\r\n" ); + portDISABLE_INTERRUPTS(); + for( ;; ); } /*-----------------------------------------------------------*/ @@ -152,7 +162,9 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ - vAssertCalled( __FILE__, __LINE__ ); + printf( "\r\n\r\nStack overflow in %s\r\n", pcTaskName ); + portDISABLE_INTERRUPTS(); + for( ;; ); } /*-----------------------------------------------------------*/ @@ -266,13 +278,13 @@ static void prvUARTInit( void ) int __write( int iFile, char *pcString, int iStringLength ) { - uint32_t ulNextChar; + int iNextChar; /* Avoid compiler warnings about unused parameters. */ ( void ) iFile; /* Output the formatted string to the UART. */ - for( ulNextChar = 0; ulNextChar < iStringLength; ulNextChar++ ) + for( iNextChar = 0; iNextChar < iStringLength; iNextChar++ ) { while( ( UART0_STATE & TX_BUFFER_MASK ) != 0 ); UART0_DATA = *pcString; @@ -281,4 +293,20 @@ int __write( int iFile, char *pcString, int iStringLength ) return iStringLength; } +/*-----------------------------------------------------------*/ + +void *malloc( size_t size ) +{ + ( void ) size; + + /* This project uses heap_4 so doesn't set up a heap for use by the C + library - but something is calling the C library malloc(). See + https://freertos.org/a00111.html for more information. */ + printf( "\r\n\r\nUnexpected call to malloc() - should be usine pvPortMalloc()\r\n" ); + portDISABLE_INTERRUPTS(); + for( ;; ); + +} + + diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main_blinky.c rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_blinky.c diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main_full.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main_full.c rename to FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c index e60c74e873..0ef388341e 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR/main_full.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/main_full.c @@ -104,6 +104,11 @@ #define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) #define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) +/* Stack sizes are defined relative to configMINIMAL_STACK_SIZE so they scale +across projects that have that constant set differently - in this case the +constant is different depending on the compiler in use. */ +#define mainMESSAGE_BUFFER_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) +#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) /*-----------------------------------------------------------*/ /* The task that checks the operation of all the other standard demo tasks, as @@ -124,7 +129,7 @@ void main_full( void ) vStartQueuePeekTasks(); vStartQueueSetTasks(); vStartEventGroupTasks(); - vStartMessageBufferTasks( configMINIMAL_STACK_SIZE ); + vStartMessageBufferTasks( mainMESSAGE_BUFFER_STACK_SIZE ); vStartStreamBufferTasks(); vCreateAbortDelayTasks(); vStartCountingSemaphoreTasks(); @@ -144,7 +149,7 @@ void main_full( void ) or not the correct/expected number of tasks are running at any given time. */ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); /* Start the scheduler. */ vTaskStartScheduler(); @@ -165,6 +170,9 @@ const TickType_t xTaskPeriod = pdMS_TO_TICKS( 5000UL ); TickType_t xPreviousWakeTime; extern uint32_t ulNestCount; + /* Avoid warning about unused parameter. */ + ( void ) pvParameters; + xPreviousWakeTime = xTaskGetTickCount(); for( ;; ) @@ -271,7 +279,7 @@ extern uint32_t ulNestCount; /* It is normally not good to call printf() from an embedded system, although it is ok in this simulated case. */ - printf( "%s : %d (%d)\r\n", pcMessage, (int) xTaskGetTickCount(), ulNestCount ); + printf( "%s : %d (%d)\r\n", pcMessage, (int) xTaskGetTickCount(), ( int ) ulNestCount ); } } /*-----------------------------------------------------------*/ diff --git a/lexicon.txt b/lexicon.txt index e3852c0035..de02056cc2 100644 --- a/lexicon.txt +++ b/lexicon.txt @@ -2937,6 +2937,7 @@ uxtaskgetsystemstate uxtaskgettasknumber uxtaskpriority uxtaskpriorityget +uxtb uxtick uxtxstackbuffer uxvariabletoincrement