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./ +SET_PREFERENCE workingdirectory ./ +SET_PREFERENCE subworkingdirectory ./ +SET_PREFERENCE InputParamsFile param_input.xml +SET_PREFERENCE OutputParamsFile param_output.xml diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_output.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_output.txt new file mode 100644 index 0000000000..ed2bda49c6 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/mig_output.txt @@ -0,0 +1,4 @@ +SET_ERROR_CODE 0 +SET_XMDF_PATH ./MCB_DDR3_xmdf.tcl +SET_PARAMETER component_name MCB_DDR3 +SET_PARAMETER xml_input_file ./MCB_DDR3/user_design/mig.prj diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml new file mode 100644 index 0000000000..2424c81199 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml @@ -0,0 +1,953 @@ + + + + + + + + + + + + + + + C_ARB_ALGORITHM + "0" + + + C_ARB_NUM_TIME_SLOTS + "12" + + + C_ARB_TIME_SLOT_0 + "0b000000000001010011" + + + C_ARB_TIME_SLOT_1 + "0b000000001010011000" + + + C_ARB_TIME_SLOT_2 + "0b000000010011000001" + + + C_ARB_TIME_SLOT_3 + "0b000000011000001010" + + + C_ARB_TIME_SLOT_4 + "0b000000000001010011" + + + C_ARB_TIME_SLOT_5 + "0b000000001010011000" + + + C_ARB_TIME_SLOT_6 + "0b000000010011000001" + + + C_ARB_TIME_SLOT_7 + "0b000000011000001010" + + + C_ARB_TIME_SLOT_8 + "0b000000000001010011" + + + C_ARB_TIME_SLOT_9 + "0b000000001010011000" + + + C_ARB_TIME_SLOT_10 + "0b000000010011000001" + + + C_ARB_TIME_SLOT_11 + "0b000000011000001010" + + + C_BYPASS_CORE_UCF + "0" + + + C_INTERCONNECT_S0_AXI_ACLK_RATIO + "100000000" + + + C_INTERCONNECT_S0_AXI_AR_REGISTER + "1" + + + C_INTERCONNECT_S0_AXI_AW_REGISTER + "1" + + + C_INTERCONNECT_S0_AXI_B_REGISTER + "1" + + + C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC + "0" + + + C_INTERCONNECT_S0_AXI_MASTERS + "ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM" + + + C_INTERCONNECT_S0_AXI_R_REGISTER + "1" + + + C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE + "4" + + + C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S0_AXI_SECURE + "0" + + + C_INTERCONNECT_S0_AXI_W_REGISTER + "1" + + + C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE + "4" + + + C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S1_AXI_ACLK_RATIO + "1" + + + C_INTERCONNECT_S1_AXI_AR_REGISTER + "0" + + + C_INTERCONNECT_S1_AXI_AW_REGISTER + "0" + + + C_INTERCONNECT_S1_AXI_B_REGISTER + "0" + + + C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC + "0" + + + C_INTERCONNECT_S1_AXI_MASTERS + "none" + + + C_INTERCONNECT_S1_AXI_R_REGISTER + "0" + + + C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE + "4" + + + C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S1_AXI_SECURE + "0" + + + C_INTERCONNECT_S1_AXI_W_REGISTER + "0" + + + C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE + "4" + + + C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S2_AXI_ACLK_RATIO + "1" + + + C_INTERCONNECT_S2_AXI_AR_REGISTER + "0" + + + C_INTERCONNECT_S2_AXI_AW_REGISTER + "0" + + + C_INTERCONNECT_S2_AXI_B_REGISTER + "0" + + + C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC + "0" + + + C_INTERCONNECT_S2_AXI_MASTERS + "none" + + + C_INTERCONNECT_S2_AXI_R_REGISTER + "0" + + + C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE + "4" + + + C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S2_AXI_SECURE + "0" + + + C_INTERCONNECT_S2_AXI_W_REGISTER + "0" + + + C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE + "4" + + + C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S3_AXI_ACLK_RATIO + "1" + + + C_INTERCONNECT_S3_AXI_AR_REGISTER + "0" + + + C_INTERCONNECT_S3_AXI_AW_REGISTER + "0" + + + C_INTERCONNECT_S3_AXI_B_REGISTER + "0" + + + C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC + "0" + + + C_INTERCONNECT_S3_AXI_MASTERS + "none" + + + C_INTERCONNECT_S3_AXI_R_REGISTER + "0" + + + C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE + "4" + + + C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S3_AXI_SECURE + "0" + + + C_INTERCONNECT_S3_AXI_W_REGISTER + "0" + + + C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE + "4" + + + C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S4_AXI_ACLK_RATIO + "1" + + + C_INTERCONNECT_S4_AXI_AR_REGISTER + "0" + + + C_INTERCONNECT_S4_AXI_AW_REGISTER + "0" + + + C_INTERCONNECT_S4_AXI_B_REGISTER + "0" + + + C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC + "0" + + + C_INTERCONNECT_S4_AXI_MASTERS + "none" + + + C_INTERCONNECT_S4_AXI_R_REGISTER + "0" + + + C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE + "4" + + + C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S4_AXI_SECURE + "0" + + + C_INTERCONNECT_S4_AXI_W_REGISTER + "0" + + + C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE + "4" + + + C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S5_AXI_ACLK_RATIO + "1" + + + C_INTERCONNECT_S5_AXI_AR_REGISTER + "0" + + + C_INTERCONNECT_S5_AXI_AW_REGISTER + "0" + + + C_INTERCONNECT_S5_AXI_B_REGISTER + "0" + + + C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC + "0" + + + C_INTERCONNECT_S5_AXI_MASTERS + "none" + + + C_INTERCONNECT_S5_AXI_R_REGISTER + "0" + + + C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE + "4" + + + C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH + "0" + + + C_INTERCONNECT_S5_AXI_SECURE + "0" + + + C_INTERCONNECT_S5_AXI_W_REGISTER + "0" + + + C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE + "4" + + + C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH + "0" + + + C_MCB_LOC + "MEMC3" + + + C_MCB_PERFORMANCE + "STANDARD" + + + C_MCB_RZQ_LOC + "K7" + + + C_MCB_USE_EXTERNAL_BUFPLL + "0" + + + C_MCB_ZIO_LOC + "R7" + + + C_MEM_ADDR_ORDER + "ROW_BANK_COLUMN" + + + C_MEM_ADDR_WIDTH + "13" + + + C_MEM_BANKADDR_WIDTH + "3" + + + C_MEM_BASEPARTNO + "" + + + C_MEM_CAS_LATENCY + "6" + + + C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS + "CLASS_II" + + + C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS + "CLASS_II" + + + C_MEM_DDR1_2_ODS + "FULL" + + + C_MEM_DDR2_3_HIGH_TEMP_SR + "NORMAL" + + + C_MEM_DDR2_3_PA_SR + "FULL" + + + C_MEM_DDR2_DIFF_DQS_EN + "YES" + + + C_MEM_DDR2_RTT + "150OHMS" + + + C_MEM_DDR3_AUTO_SR + "ENABLED" + + + C_MEM_DDR3_CAS_LATENCY + "6" + + + C_MEM_DDR3_CAS_WR_LATENCY + "5" + + + C_MEM_DDR3_ODS + "DIV6" + + + C_MEM_DDR3_RTT + "DIV4" + + + C_MEM_MDDR_ODS + "FULL" + + + C_MEM_MOBILE_PA_SR + "FULL" + + + C_MEM_NUM_COL_BITS + "10" + + + C_MEM_PARTNO + "MT41J64M16XX-187E" + + + C_MEM_TRAS + "-1" + + + C_MEM_TRCD + "-1" + + + C_MEM_TREFI + "-1" + + + C_MEM_TRFC + "-1" + + + C_MEM_TRP + "-1" + + + C_MEM_TRTP + "-1" + + + C_MEM_TWR + "-1" + + + C_MEM_TWTR + "-1" + + + C_MEM_TYPE + "DDR3" + + + C_MEM_TZQINIT_MAXCNT + "512" + + + C_MEMCLK_PERIOD + "0" + + + C_NUM_DQ_PINS + "16" + + + C_PORT_CONFIG + "B32_B32_B32_B32" + + + C_S0_AXI_ADDED_AXI_PARAMS + "TRUE" + + + C_S0_AXI_ADDR_WIDTH + "32" + + + C_S0_AXI_AXI_VER + "1.02.a" + + + C_S0_AXI_BASEADDR + "0x80000000" + + + C_S0_AXI_DATA_WIDTH + "32" + + + C_S0_AXI_ENABLE + "1" + + + C_S0_AXI_ENABLE_AP + "0" + + + C_S0_AXI_HIGHADDR + "0x87ffffff" + + + C_S0_AXI_ID_WIDTH + "2" + + + C_S0_AXI_PROTOCOL + "AXI4" + + + C_S0_AXI_REG_EN0 + "0x00000" + + + C_S0_AXI_REG_EN1 + "0x01000" + + + C_S0_AXI_STRICT_COHERENCY + "1" + + + C_S0_AXI_SUPPORTS_NARROW_BURST + "Auto" + + + C_S0_AXI_SUPPORTS_READ + "1" + + + C_S0_AXI_SUPPORTS_WRITE + "1" + + + C_S1_AXI_ADDED_AXI_PARAMS + "TRUE" + + + C_S1_AXI_ADDR_WIDTH + "32" + + + C_S1_AXI_AXI_VER + "1.01.a" + + + C_S1_AXI_BASEADDR + "0xFFFFFFFF" + + + C_S1_AXI_DATA_WIDTH + "32" + + + C_S1_AXI_ENABLE + "0" + + + C_S1_AXI_ENABLE_AP + "0" + + + C_S1_AXI_HIGHADDR + "0x00000000" + + + C_S1_AXI_ID_WIDTH + "4" + + + C_S1_AXI_PROTOCOL + "AXI4" + + + C_S1_AXI_REG_EN0 + "0x00000" + + + C_S1_AXI_REG_EN1 + "0x01000" + + + C_S1_AXI_STRICT_COHERENCY + "1" + + + C_S1_AXI_SUPPORTS_NARROW_BURST + "Auto" + + + C_S1_AXI_SUPPORTS_READ + "1" + + + C_S1_AXI_SUPPORTS_WRITE + "1" + + + C_S2_AXI_ADDED_AXI_PARAMS + "TRUE" + + + C_S2_AXI_ADDR_WIDTH + "32" + + + C_S2_AXI_AXI_VER + "1.01.a" + + + C_S2_AXI_BASEADDR + "0xFFFFFFFF" + + + C_S2_AXI_DATA_WIDTH + "32" + + + C_S2_AXI_ENABLE + "0" + + + C_S2_AXI_ENABLE_AP + "0" + + + C_S2_AXI_HIGHADDR + "0x00000000" + + + C_S2_AXI_ID_WIDTH + "4" + + + C_S2_AXI_PROTOCOL + "AXI4" + + + C_S2_AXI_REG_EN0 + "0x00000" + + + C_S2_AXI_REG_EN1 + "0x01000" + + + C_S2_AXI_STRICT_COHERENCY + "1" + + + C_S2_AXI_SUPPORTS_NARROW_BURST + "Auto" + + + C_S2_AXI_SUPPORTS_READ + "1" + + + C_S2_AXI_SUPPORTS_WRITE + "1" + + + C_S3_AXI_ADDED_AXI_PARAMS + "TRUE" + + + C_S3_AXI_ADDR_WIDTH + "32" + + + C_S3_AXI_AXI_VER + "1.01.a" + + + C_S3_AXI_BASEADDR + "0xFFFFFFFF" + + + C_S3_AXI_DATA_WIDTH + "32" + + + C_S3_AXI_ENABLE + "0" + + + C_S3_AXI_ENABLE_AP + "0" + + + C_S3_AXI_HIGHADDR + "0x00000000" + + + C_S3_AXI_ID_WIDTH + "4" + + + C_S3_AXI_PROTOCOL + "AXI4" + + + C_S3_AXI_REG_EN0 + "0x00000" + + + C_S3_AXI_REG_EN1 + "0x01000" + + + C_S3_AXI_STRICT_COHERENCY + "1" + + + C_S3_AXI_SUPPORTS_NARROW_BURST + "Auto" + + + C_S3_AXI_SUPPORTS_READ + "1" + + + C_S3_AXI_SUPPORTS_WRITE + "1" + + + C_S4_AXI_ADDED_AXI_PARAMS + "TRUE" + + + C_S4_AXI_ADDR_WIDTH + "32" + + + C_S4_AXI_AXI_VER + "1.01.a" + + + C_S4_AXI_BASEADDR + "0xFFFFFFFF" + + + C_S4_AXI_DATA_WIDTH + "32" + + + C_S4_AXI_ENABLE + "0" + + + C_S4_AXI_ENABLE_AP + "0" + + + C_S4_AXI_HIGHADDR + "0x00000000" + + + C_S4_AXI_ID_WIDTH + "4" + + + C_S4_AXI_PROTOCOL + "AXI4" + + + C_S4_AXI_REG_EN0 + "0x00000" + + + C_S4_AXI_REG_EN1 + "0x01000" + + + C_S4_AXI_STRICT_COHERENCY + "1" + + + C_S4_AXI_SUPPORTS_NARROW_BURST + "Auto" + + + C_S4_AXI_SUPPORTS_READ + "1" + + + C_S4_AXI_SUPPORTS_WRITE + "1" + + + C_S5_AXI_ADDED_AXI_PARAMS + "TRUE" + + + C_S5_AXI_ADDR_WIDTH + "32" + + + C_S5_AXI_AXI_VER + "1.01.a" + + + C_S5_AXI_BASEADDR + "0xFFFFFFFF" + + + C_S5_AXI_DATA_WIDTH + "32" + + + C_S5_AXI_ENABLE + "0" + + + C_S5_AXI_ENABLE_AP + "0" + + + C_S5_AXI_HIGHADDR + "0x00000000" + + + C_S5_AXI_ID_WIDTH + "4" + + + C_S5_AXI_PROTOCOL + "AXI4" + + + C_S5_AXI_REG_EN0 + "0x00000" + + + C_S5_AXI_REG_EN1 + "0x01000" + + + C_S5_AXI_STRICT_COHERENCY + "1" + + + C_S5_AXI_SUPPORTS_NARROW_BURST + "Auto" + + + C_S5_AXI_SUPPORTS_READ + "1" + + + C_S5_AXI_SUPPORTS_WRITE + "1" + + + C_SIMULATION + "FALSE" + + + C_SKIP_IN_TERM_CAL + "0" + + + C_SKIP_IN_TERM_CAL_VALUE + "NONE" + + + C_SYS_RST_PRESENT + "1" + + + HW_VER + "1.02.a" + + + INSTANCE + "MCB_DDR3" + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log new file mode 100644 index 0000000000..250c330b76 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log @@ -0,0 +1,567 @@ +========================================================================= +Time: Fri Aug 26 20:58:58 GMT Daylight Time 2011 +Running: run_batch_mode 74543544 +{COLLECTING: INSTANCE MCB_DDR3 } +{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} +{COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } +{COLLECTING: C_INTERCONNECT_S0_AXI_ACLK_RATIO 100000000 UPDATE integer 1 } +{COLLECTING: C_INTERCONNECT_S0_AXI_SECURE 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S0_AXI_AW_REGISTER 1 OPTIONAL integer 0 1} +{COLLECTING: C_INTERCONNECT_S0_AXI_AR_REGISTER 1 OPTIONAL integer 0 1} +{COLLECTING: C_INTERCONNECT_S0_AXI_W_REGISTER 1 OPTIONAL integer 0 1} +{COLLECTING: C_INTERCONNECT_S0_AXI_R_REGISTER 1 OPTIONAL integer 0 1} +{COLLECTING: C_INTERCONNECT_S0_AXI_B_REGISTER 1 OPTIONAL integer 0 1} +{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_S0_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } +{COLLECTING: C_S0_AXI_AXI_VER 1.02.a CONSTANT } +{COLLECTING: C_INTERCONNECT_S1_AXI_MASTERS none OPTIONAL string none } +{COLLECTING: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_ACLK_RATIO 1 UPDATE integer 1 } +{COLLECTING: C_INTERCONNECT_S1_AXI_SECURE 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_AW_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_AR_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_W_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_R_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_B_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_S1_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } +{COLLECTING: C_S1_AXI_AXI_VER 1.01.a CONSTANT } +{COLLECTING: C_INTERCONNECT_S2_AXI_MASTERS none OPTIONAL string none } +{COLLECTING: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_ACLK_RATIO 1 UPDATE integer 1 } +{COLLECTING: C_INTERCONNECT_S2_AXI_SECURE 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_AW_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_AR_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_W_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_R_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_B_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_S2_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } +{COLLECTING: C_S2_AXI_AXI_VER 1.01.a CONSTANT } +{COLLECTING: C_INTERCONNECT_S3_AXI_MASTERS none OPTIONAL string none } +{COLLECTING: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_ACLK_RATIO 1 UPDATE integer 1 } +{COLLECTING: C_INTERCONNECT_S3_AXI_SECURE 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_AW_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_AR_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_W_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_R_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_B_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_S3_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } +{COLLECTING: C_S3_AXI_AXI_VER 1.01.a CONSTANT } +{COLLECTING: C_INTERCONNECT_S4_AXI_MASTERS none OPTIONAL string none } +{COLLECTING: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_ACLK_RATIO 1 UPDATE integer 1 } +{COLLECTING: C_INTERCONNECT_S4_AXI_SECURE 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_AW_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_AR_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_W_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_R_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_B_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_S4_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } +{COLLECTING: C_S4_AXI_AXI_VER 1.01.a CONSTANT } +{COLLECTING: C_INTERCONNECT_S5_AXI_MASTERS none OPTIONAL string none } +{COLLECTING: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_ACLK_RATIO 1 UPDATE integer 1 } +{COLLECTING: C_INTERCONNECT_S5_AXI_SECURE 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_AW_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_AR_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_W_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_R_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_B_REGISTER 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 } +{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 } +{COLLECTING: C_S5_AXI_ADDED_AXI_PARAMS TRUE CONSTANT } +{COLLECTING: C_S5_AXI_AXI_VER 1.01.a CONSTANT } +{COLLECTING: C_MCB_LOC MEMC3 OPTIONAL MEMC3 } +{COLLECTING: C_MCB_RZQ_LOC K7 OPTIONAL STRING NOT_SET K7} +{COLLECTING: C_MCB_ZIO_LOC R7 OPTIONAL STRING NOT_SET R7} +{COLLECTING: C_MCB_PERFORMANCE STANDARD OPTIONAL STRING STANDARD } +{COLLECTING: C_BYPASS_CORE_UCF 0 OPTIONAL 0 } +{COLLECTING: C_S0_AXI_BASEADDR 0x80000000 OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF 0x80000000} +{COLLECTING: C_S0_AXI_HIGHADDR 0x87ffffff OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x87ffffff} +{COLLECTING: C_S1_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } +{COLLECTING: C_S1_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } +{COLLECTING: C_S2_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } +{COLLECTING: C_S2_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } +{COLLECTING: C_S3_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } +{COLLECTING: C_S3_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } +{COLLECTING: C_S4_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } +{COLLECTING: C_S4_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } +{COLLECTING: C_S5_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } +{COLLECTING: C_S5_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } +{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 DDR3} +{COLLECTING: C_MEM_PARTNO MT41J64M16XX-187E REQUIRE STRING NOT_SET MT41J64M16XX-187E} +{COLLECTING: C_MEM_BASEPARTNO NOT_SET OPTIONAL STRING NOT_SET } +{COLLECTING: C_NUM_DQ_PINS 16 OPTIONAL_UPDATE INTEGER 16 } +{COLLECTING: C_MEM_ADDR_WIDTH 13 OPTIONAL_UPDATE INTEGER 13 } +{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 3} +{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 10} +{COLLECTING: C_MEM_TRAS -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TRCD -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TREFI -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TRFC -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TRP -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TWR -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TRTP -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_MEM_TWTR -1 OPTIONAL_UPDATE INTEGER -1 } +{COLLECTING: C_PORT_CONFIG B32_B32_B32_B32 OPTIONAL STRING B32_B32_B32_B32 } +{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 0} +{COLLECTING: C_SKIP_IN_TERM_CAL_VALUE NONE OPTIONAL STRING NONE } +{COLLECTING: C_MEMCLK_PERIOD 0 OPTIONAL_UPDATE INTEGER 0 } +{COLLECTING: C_MEM_ADDR_ORDER ROW_BANK_COLUMN OPTIONAL STRING ROW_BANK_COLUMN } +{COLLECTING: C_MEM_TZQINIT_MAXCNT 512 UPDATE INTEGER 512 } +{COLLECTING: C_MEM_CAS_LATENCY 6 UPDATE INTEGER 6 } +{COLLECTING: C_SIMULATION FALSE OPTIONAL STRING FALSE } +{COLLECTING: C_MEM_DDR1_2_ODS FULL OPTIONAL STRING FULL } +{COLLECTING: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II } +{COLLECTING: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II } +{COLLECTING: C_MEM_DDR2_RTT 150OHMS OPTIONAL STRING 150OHMS } +{COLLECTING: C_MEM_DDR2_DIFF_DQS_EN YES OPTIONAL STRING YES } +{COLLECTING: C_MEM_DDR2_3_PA_SR FULL OPTIONAL STRING FULL } +{COLLECTING: C_MEM_DDR2_3_HIGH_TEMP_SR NORMAL OPTIONAL STRING NORMAL } +{COLLECTING: C_MEM_DDR3_CAS_WR_LATENCY 5 UPDATE INTEGER 5 } +{COLLECTING: C_MEM_DDR3_CAS_LATENCY 6 UPDATE INTEGER 6 } +{COLLECTING: C_MEM_DDR3_ODS DIV6 OPTIONAL STRING DIV6 } +{COLLECTING: C_MEM_DDR3_RTT DIV4 OPTIONAL STRING DIV4 } +{COLLECTING: C_MEM_DDR3_AUTO_SR ENABLED OPTIONAL STRING ENABLED } +{COLLECTING: C_MEM_MOBILE_PA_SR FULL OPTIONAL STRING FULL } +{COLLECTING: C_MEM_MDDR_ODS FULL OPTIONAL STRING FULL } +{COLLECTING: C_ARB_ALGORITHM 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_ARB_NUM_TIME_SLOTS 12 OPTIONAL INTEGER 12 } +{COLLECTING: C_ARB_TIME_SLOT_0 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } +{COLLECTING: C_ARB_TIME_SLOT_1 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } +{COLLECTING: C_ARB_TIME_SLOT_2 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } +{COLLECTING: C_ARB_TIME_SLOT_3 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } +{COLLECTING: C_ARB_TIME_SLOT_4 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } +{COLLECTING: C_ARB_TIME_SLOT_5 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } +{COLLECTING: C_ARB_TIME_SLOT_6 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } +{COLLECTING: C_ARB_TIME_SLOT_7 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } +{COLLECTING: C_ARB_TIME_SLOT_8 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 } +{COLLECTING: C_ARB_TIME_SLOT_9 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 } +{COLLECTING: C_ARB_TIME_SLOT_10 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 } +{COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } +{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 1} +{COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } +{COLLECTING: C_S0_AXI_ID_WIDTH 2 UPDATE INTEGER 4 } +{COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S0_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } +{COLLECTING: C_S0_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S0_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S0_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S0_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } +{COLLECTING: C_S0_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } +{COLLECTING: C_S0_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S0_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S1_AXI_ENABLE 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S1_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } +{COLLECTING: C_S1_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } +{COLLECTING: C_S1_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S1_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } +{COLLECTING: C_S1_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S1_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S1_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S1_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } +{COLLECTING: C_S1_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } +{COLLECTING: C_S1_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S1_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S2_AXI_ENABLE 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S2_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } +{COLLECTING: C_S2_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } +{COLLECTING: C_S2_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S2_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S2_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S2_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S2_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S2_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } +{COLLECTING: C_S2_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } +{COLLECTING: C_S2_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S2_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S3_AXI_ENABLE 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S3_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } +{COLLECTING: C_S3_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } +{COLLECTING: C_S3_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S3_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S3_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S3_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S3_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S3_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } +{COLLECTING: C_S3_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } +{COLLECTING: C_S3_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S3_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S4_AXI_ENABLE 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S4_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } +{COLLECTING: C_S4_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } +{COLLECTING: C_S4_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S4_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S4_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S4_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S4_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S4_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } +{COLLECTING: C_S4_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } +{COLLECTING: C_S4_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S4_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S5_AXI_ENABLE 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_S5_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } +{COLLECTING: C_S5_AXI_ID_WIDTH 4 UPDATE INTEGER 4 } +{COLLECTING: C_S5_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S5_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 } +{COLLECTING: C_S5_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S5_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S5_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S5_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 } +{COLLECTING: C_S5_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 } +{COLLECTING: C_S5_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 } +{COLLECTING: C_S5_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_MCB_USE_EXTERNAL_BUFPLL 0 OPTIONAL INTEGER 0 } +{COLLECTING: C_SYS_RST_PRESENT 1 UPDATE INTEGER 0 } +{COLLECTING: HW_VER 1.02.a } +{SENDING PARAMETER: C_ARB_ALGORITHM : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_ARB_NUM_TIME_SLOTS : 12 INTEGER OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_0 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_1 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_2 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_3 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_4 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_5 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_6 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_7 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_8 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_9 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_10 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_ARB_TIME_SLOT_11 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_BYPASS_CORE_UCF : 0 {} OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_ACLK_RATIO : 100000000 integer UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AR_REGISTER : 1 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AW_REGISTER : 1 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_B_REGISTER : 1 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_R_REGISTER : 1 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_SECURE : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_W_REGISTER : 1 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_ACLK_RATIO : 1 integer UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AR_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AW_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_B_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_MASTERS : none string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_R_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_SECURE : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_W_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_ACLK_RATIO : 1 integer UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AR_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AW_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_B_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_MASTERS : none string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_R_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_SECURE : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_W_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_ACLK_RATIO : 1 integer UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AR_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AW_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_B_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_MASTERS : none string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_R_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_SECURE : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_W_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_ACLK_RATIO : 1 integer UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AR_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AW_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_B_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_MASTERS : none string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_R_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_SECURE : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_W_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_ACLK_RATIO : 1 integer UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AR_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AW_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_B_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_MASTERS : none string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_R_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_SECURE : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_W_REGISTER : 0 integer OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL} +{SENDING PARAMETER: C_MCB_LOC : MEMC3 {} OPTIONAL} +{SENDING PARAMETER: C_MCB_PERFORMANCE : STANDARD STRING OPTIONAL} +{SENDING PARAMETER: C_MCB_RZQ_LOC : K7 STRING OPTIONAL} +{SENDING PARAMETER: C_MCB_USE_EXTERNAL_BUFPLL : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_MCB_ZIO_LOC : R7 STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_ADDR_ORDER : ROW_BANK_COLUMN STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_ADDR_WIDTH : 13 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_BANKADDR_WIDTH : 3 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_BASEPARTNO : NOT_SET STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_CAS_LATENCY : 6 INTEGER UPDATE} +{SENDING PARAMETER: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR1_2_ODS : FULL STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR2_3_HIGH_TEMP_SR : NORMAL STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR2_3_PA_SR : FULL STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR2_DIFF_DQS_EN : YES STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR2_RTT : 150OHMS STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR3_AUTO_SR : ENABLED STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR3_CAS_LATENCY : 6 INTEGER UPDATE} +{SENDING PARAMETER: C_MEM_DDR3_CAS_WR_LATENCY : 5 INTEGER UPDATE} +{SENDING PARAMETER: C_MEM_DDR3_ODS : DIV6 STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_DDR3_RTT : DIV4 STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_MDDR_ODS : FULL STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_MOBILE_PA_SR : FULL STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_NUM_COL_BITS : 10 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_PARTNO : MT41J64M16XX-187E STRING REQUIRE} +{SENDING PARAMETER: C_MEM_TRAS : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TRCD : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TREFI : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TRFC : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TRP : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TRTP : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TWR : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TWTR : -1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_MEM_TYPE : DDR3 STRING OPTIONAL} +{SENDING PARAMETER: C_MEM_TZQINIT_MAXCNT : 512 INTEGER UPDATE} +{SENDING PARAMETER: C_MEMCLK_PERIOD : 0 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_NUM_DQ_PINS : 16 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_PORT_CONFIG : B32_B32_B32_B32 STRING OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} +{SENDING PARAMETER: C_S0_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S0_AXI_AXI_VER : 1.02.a {} CONSTANT} +{SENDING PARAMETER: C_S0_AXI_BASEADDR : 0x80000000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_ENABLE : 1 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x87ffffff STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 2 INTEGER UPDATE} +{SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT} +{SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S0_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S0_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S0_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S1_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} +{SENDING PARAMETER: C_S1_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S1_AXI_AXI_VER : 1.01.a {} CONSTANT} +{SENDING PARAMETER: C_S1_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S1_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S1_AXI_ENABLE : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S1_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S1_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S1_AXI_ID_WIDTH : 4 INTEGER UPDATE} +{SENDING PARAMETER: C_S1_AXI_PROTOCOL : AXI4 STRING CONSTANT} +{SENDING PARAMETER: C_S1_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S1_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S1_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S1_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S1_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S1_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S2_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} +{SENDING PARAMETER: C_S2_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S2_AXI_AXI_VER : 1.01.a {} CONSTANT} +{SENDING PARAMETER: C_S2_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S2_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S2_AXI_ENABLE : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S2_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S2_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S2_AXI_ID_WIDTH : 4 INTEGER UPDATE} +{SENDING PARAMETER: C_S2_AXI_PROTOCOL : AXI4 STRING CONSTANT} +{SENDING PARAMETER: C_S2_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S2_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S2_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S2_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S2_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S2_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S3_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} +{SENDING PARAMETER: C_S3_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S3_AXI_AXI_VER : 1.01.a {} CONSTANT} +{SENDING PARAMETER: C_S3_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S3_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S3_AXI_ENABLE : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S3_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S3_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S3_AXI_ID_WIDTH : 4 INTEGER UPDATE} +{SENDING PARAMETER: C_S3_AXI_PROTOCOL : AXI4 STRING CONSTANT} +{SENDING PARAMETER: C_S3_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S3_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S3_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S3_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S3_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S3_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S4_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} +{SENDING PARAMETER: C_S4_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S4_AXI_AXI_VER : 1.01.a {} CONSTANT} +{SENDING PARAMETER: C_S4_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S4_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S4_AXI_ENABLE : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S4_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S4_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S4_AXI_ID_WIDTH : 4 INTEGER UPDATE} +{SENDING PARAMETER: C_S4_AXI_PROTOCOL : AXI4 STRING CONSTANT} +{SENDING PARAMETER: C_S4_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S4_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S4_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S4_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S4_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S4_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S5_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT} +{SENDING PARAMETER: C_S5_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S5_AXI_AXI_VER : 1.01.a {} CONSTANT} +{SENDING PARAMETER: C_S5_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S5_AXI_DATA_WIDTH : 32 INTEGER CONSTANT} +{SENDING PARAMETER: C_S5_AXI_ENABLE : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S5_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_S5_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S5_AXI_ID_WIDTH : 4 INTEGER UPDATE} +{SENDING PARAMETER: C_S5_AXI_PROTOCOL : AXI4 STRING CONSTANT} +{SENDING PARAMETER: C_S5_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S5_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S5_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S5_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S5_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_S5_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE} +{SENDING PARAMETER: C_SIMULATION : FALSE STRING OPTIONAL} +{SENDING PARAMETER: C_SKIP_IN_TERM_CAL : 0 INTEGER OPTIONAL} +{SENDING PARAMETER: C_SKIP_IN_TERM_CAL_VALUE : NONE STRING OPTIONAL} +{SENDING PARAMETER: C_SYS_RST_PRESENT : 1 INTEGER UPDATE} +{SENDING PARAMETER: HW_VER : 1.02.a {} {}} +{SENDING PARAMETER: INSTANCE : MCB_DDR3 {} {}} +{Executing C:/devtools/Xilinx/13.1/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_7/bin/nt/mig.exe -cg_exc_inp mig_input.txt -cg_exc_out mig_output.txt} +{SET: IGNORE C_MCB_LOC = MEMC3 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MEM_DDR3_ODS = DIV6 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MCB_ZIO_LOC = R7 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: UPDATE C_S4_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_S0_AXI_BASEADDR = 0x80000000 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_MEM_MDDR_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MEM_DDR2_DIFF_DQS_EN = YES (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_S2_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_S0_AXI_DATA_WIDTH = 32 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MHS:MPDVAL)} +{SET: IGNORE C_MEM_DDR3_RTT = DIV4 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDREM C_MEM_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} +{SET: UPDATE C_MEM_TRFC = 160000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: UPDATE C_S3_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_S0_AXI_SUPPORTS_NARROW_BURST = Auto (BATCH:OPTIONAL_UPDATE::MPD:DEFVAL)} +{SET: UPDREM C_S0_AXI_STRICT_COHERENCY = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_10 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_SECURE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_11 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_ARB_NUM_TIME_SLOTS = 12 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_S5_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_S2_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDATE C_MEM_TRTP = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDATE C_MEM_TREFI = 7800000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MHS:MPDVAL)} +{SET: IGNORE C_MEM_MOBILE_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MHS:MPDVAL)} +{SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} +{SET: IGNORE C_S0_AXI_HIGHADDR = 0x87ffffff (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MHS:MPDVAL)} +{SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} +{SET: UPDATE C_S5_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDATE C_S4_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_S0_AXI_ENABLE_AP = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_MEM_TWR = 15000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_S3_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDREM C_S0_AXI_SUPPORTS_WRITE = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} +{SET: IGNORE C_S0_AXI_ADDR_WIDTH = 32 (BATCH:CONSTANT::MPD:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDREM C_MEM_DDR3_CAS_WR_LATENCY = 5 (BATCH:UPDATE::MPD:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_W_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_MEM_DDR2_RTT = 150OHMS (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MCB_PERFORMANCE = STANDARD (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MHS:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_B_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_SIMULATION = FALSE (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_S1_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDATE C_MEM_TWTR = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDATE C_S3_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDATE C_MEM_TRAS = 37500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: UPDREM C_MEM_DDR3_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)} +{SET: UPDATE C_S5_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_S1_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_MEM_TRCD = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_0 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_ARB_ALGORITHM = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_MEM_TRP = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_1 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_2 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_3 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_MEM_DDR3_AUTO_SR = ENABLED (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_4 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_5 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_6 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_7 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_MEMCLK_PERIOD = 0 (BATCH:OPTIONAL_UPDATE:SKIP_BATCH:MPD:MPDVAL)} +{SET: IGNORE C_MCB_RZQ_LOC = K7 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_8 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_MEM_ADDR_ORDER = ROW_BANK_COLUMN (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MCB_USE_EXTERNAL_BUFPLL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_R_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_ARB_TIME_SLOT_9 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)} +{SET: IGNORE C_S4_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_S1_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_SKIP_IN_TERM_CAL_VALUE = NONE (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: UPDATE C_S2_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)} +{SET: IGNORE C_MEM_DDR2_3_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_PORT_CONFIG = B32_B32_B32_B32 (BATCH:OPTIONAL::MPD:MPDVAL)} +{SET: IGNORE C_MEM_PARTNO = MT41J64M16XX-187E (BATCH:REQUIRE::MHS:COMPVAL)} +{SET: CHECK C_NUM_DQ_PINS = 16 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} +RETURN: 0 +========================================================================= +Time: Fri Aug 26 20:59:03 GMT Daylight Time 2011 +Running: generate_corelevel_constraints 74543544 +RETURN: diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/bitinit.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/bitinit.opt new file mode 100644 index 0000000000..7d88d37d76 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/bitinit.opt @@ -0,0 +1 @@ + -p xc6slx45tfgg484-3 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_globals.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_globals.xsl new file mode 100644 index 0000000000..9249c08a9e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_globals.xsl @@ -0,0 +1,263 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> + + + + + + + + + + + document($P_SYSTEM_XML) + / + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + document($P_GROUPS_XML) + / + + + + + + + + + + + + + + + + + + + FOCUSED MASTERS SPECIFIED + + + + + FOCUSED MASTER BIF . = + + + + + + + + + + FOCUSED PERIPHERAL BRIDGE + + + + + + FOCUSED PERIPHERAL BRIDGE + + + + + + + + + + + FOCUSED PERIPHERAL has memory ranges + + + + FOCUSED PERIPHERAL BUS + + + + + + + + + + FOCUSED BUSSES SPECIFIED + + + + + + FOCUSED BUS + + + + + + + + TRUE + FALSE + + + + + + + + Bus + Debug + Memory + Memory Controller + Interrupt Controller + Peripheral + Processor + Bus Bridge + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + FALSE + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view.xsl b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view.xsl new file mode 100644 index 0000000000..b0fee7aa91 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/edw2xtl_sav_view.xsl @@ -0,0 +1,245 @@ + + + + + + + + + + + + +]> + + + + + + + + + + + + + + + + + + + + + + + + + + + SAV VIEW + SAV MODE + SAV SCOPE + + + + + EDW2SAV XTELLER ERROR: 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b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/gensav_cmd.xml new file mode 100644 index 0000000000..42f1efa6ce --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/gensav_cmd.xml @@ -0,0 +1,2 @@ + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport new file mode 100644 index 0000000000..475832950c --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport @@ -0,0 +1,218 @@ + + +
+ 2011-08-26T20:58:42 + system + 2011-08-26T20:58:42 + C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport + filter.filter + C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise + 2011-08-26T19:44:45 + false +
+ + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/xmsgprops.lst b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/xmsgprops.lst new file mode 100644 index 0000000000..10c9bb7ac5 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/xmsgprops.lst @@ -0,0 +1,3 @@ +MessageCaptureEnabled: TRUE +MessageFilteringEnabled: FALSE +IncrementalMessagingEnabled: TRUE diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/platgen.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/platgen.opt new file mode 100644 index 0000000000..14ffabbc85 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/platgen.opt @@ -0,0 +1,2 @@ + -p xc6slx45tfgg484-3 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst +ethernet Hardware_Evaluation diff --git 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b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/data/system.ucf @@ -0,0 +1,356 @@ +# +# pin constraints +# +NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET ETHERNET_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_MII_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG; +NET ETHERNET_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[4] LOC = "W20" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[5] LOC = "V22" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[6] LOC = "V21" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RXD[7] LOC = "U22" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[4] LOC = "AB9" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[5] LOC = "Y9" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[6] LOC = "Y12" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TXD[7] LOC = "W12" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TX_CLK LOC = "AB7" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25"; +NET ETHERNET_TX_ER LOC = "U8" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25"; +NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG; +NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25"; +NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25"; +# +# additional constraints +# + +NET "CLK" TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; +###### Soft ETHERNET +# This is a GMII system +# AXI_STR_*_ACLK is not the same as S_AXI_ACLK from clock generator +# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods +# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency +# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, +# the constraints are over constrained. Relaxing them for your system may reduce build time. + +NET "*ETHERNET*/S_AXI_ACLK" TNM_NET = "axi4lite_clk"; +NET "*ETHERNET*/AXI_STR_TXD_ACLK" TNM_NET = "axistream_clk"; +NET "*ETHERNET*/AXI_STR_TXC_ACLK" TNM_NET = "axistream_clk"; +NET "*ETHERNET*/AXI_STR_RXD_ACLK" TNM_NET = "axistream_clk"; +NET "*ETHERNET*/AXI_STR_RXS_ACLK" TNM_NET = "axistream_clk"; + +############################################################ +# Clock Period Constraints # +############################################################ + +############################################################ +# RX Clock period Constraints # +############################################################ +# Ethernet GMII PHY-side receive clock +# __________ +# | | +# --- GMII_RX_CLK-----| BUFR |---Rx_Client_Clk +# |__________| +# +# Receiver clock period constraints: please do not relax +# Changed NET name +# Changed TNM_NET name from CoreGen name to be consistent in +# EDK constraints +# NET "*/rx_gmii_clk_int" TNM_NET = "clk_rx"; +NET "*/GMII_RX_CLK" TNM_NET = "phy_clk_rx"; +# Added TIMEGRP for later DATAPATHONLY constraint +TIMEGRP "rx_clock" = "phy_clk_rx"; +TIMESPEC "TS_rx_clk" = PERIOD "rx_clock" 8000 ps HIGH 50 %; + +############################################################ +# TX Clock period Constraints # +############################################################ +############################################################ +# TIG for BUFGMUX SPEED CLK: please do not edit # +############################################################ +# Want to TIG any timing paths to the select of the TX clock BUFGMUXs +# at this point and subsequent constraints can override. MII_TX_CLK +# will remained TIG so that path is not used in any setup/hold timing +# analysis. +# Changed net name in synthesis of axi_ethernet +# PIN "*clock_inst*BUFGMUX*.I?" TNM="clk_bufgmux"; +PIN "*I_CLOCK_INST*/*BUFGMUX_SPEED_CLK.I?" TNM="clk_bufgmux"; +TIMESPEC "TS_bufgmux" = FROM "async_config" TO "clk_bufgmux" TIG; + +############################################################################### +# The following two TimeSpecs are from CoreGen Ethernet Core Example Design UCF +# file. In systems GTX_CLK is driven by clock generator core, then the derived +# period constraint will override these TimeSpecs. +############################################################################### +# Ethernet GTX_CLK high quality 125 MHz reference clock +# __________ +# -GTX_CLK------------| | +# | BUFGMUX |---Tx_Client_Clk +# -MII_TX_CLK---------|__________| +# +# Depending on system configuration, the analysis tool may use either gtx_clk +# or tx_client_clk so both nets are used in defining PERIOD constraint and +# TNM_NETS for subsequent constraints. +# The PERIOD constraints may not be analyzed if inferred clock generator +# constraints are generated for the system. + +# Transmitter clock period constraints: please do not relax +# Changed NET name +# NET "gtx_clk*" TNM_NET = "clk_gtx"; +NET "*/GTX_CLK" TNM_NET = "clk_gtx"; +# Added TIMEGRP for later DATAPATHONLY constraint +TIMEGRP "gtx_clock" = "clk_gtx"; +TIMESPEC "TS_gtx_clk" = PERIOD "gtx_clock" 8000 ps HIGH 50 %; + +# Changed NET name +# Changed TNM_NET name from CoreGen name to be consistent in +# EDK constraints +# NET "*tx_gmii_clk" TNM_NET = "clk_tx_gmii"; +NET "*/GMII.tx_gmii_clk_int" TNM_NET = "phy_clk_tx"; +TIMEGRP "tx_clock_gmii" = "phy_clk_tx"; +TIMESPEC "TS_tx_clk_gmii" = PERIOD "tx_clock_gmii" 8000 ps HIGH 50 %; + +############################################################ +# Host Clock period Constraint # +############################################################ +# Management Clock period constraints: relax as required +# Changed NET name +# NET "host_clk" TNM_NET = "host"; +NET "*/S_AXI_ACLK" TNM_NET = "host_clk"; +TIMEGRP "host" = "host_clk" EXCEPT "mdio_logic"; +TIMESPEC "TS_host_clk" = PERIOD "host" 10000 ps HIGH 50 % PRIORITY 10; + +############################################################ +# External GMII Constraints # +############################################################ +# GMII Transmitter Constraints: place flip-flops in IOB +# Changed 'true' to 'force' +# Shortened INST names to remove internal hierarchy +# INST "*trimac_block*gmii_interface*gmii_txd*" IOB = true; +# INST "*trimac_block*gmii_interface*gmii_tx_en" IOB = true; +# INST "*trimac_block*gmii_interface*gmii_tx_er" IOB = true; +INST "*gmii_txd*" IOB = force; +INST "*gmii_tx_en" IOB = force; +INST "*gmii_tx_er" IOB = force; + +# GMII Receiver Constraints: place flip-flops in IOB +# Changed 'true' to 'force' +# Shortened INST names to remove internal hierarchy +# INST "*trimac_block*gmii_interface*rxd_to_mac*" IOB = true; +# INST "*trimac_block*gmii_interface*rx_dv_to_mac" IOB = true; +# INST "*trimac_block*gmii_interface*rx_er_to_mac" IOB = true; +INST "*rxd_to_mac*" IOB = force; +INST "*rx_dv_to_mac" IOB = force; +INST "*rx_er_to_mac" IOB = force; + +############################################################ +# The following are required to maximize setup/hold # +############################################################ +# Changed to add Drive strength and INST Name +# INST "gmii_txd" SLEW = FAST; +# INST "gmii_tx_en" SLEW = FAST; +# INST "gmii_tx_er" SLEW = FAST; +# INST "gmii_tx_clk" SLEW = FAST; +INST "ETHERNET_TXD_?_OBUF" SLEW = FAST; +INST "ETHERNET_TX_EN_OBUF" SLEW = FAST; +INST "ETHERNET_TX_ER_OBUF" SLEW = FAST; +INST "ETHERNET_TX_CLK_OBUF" SLEW = FAST; + +############################################################ +# GMII: IODELAY Constraints # +############################################################ +# Please modify the value of the IDELAY_VALUE +# according to your design. +# For more information on IDELAYCTRL and IODELAY, please +# refer to the Spartan-6 User Guide. +# +INST "*delay_gmii_rx_dv" IDELAY_VALUE = 6; +INST "*delay_gmii_rx_er" IDELAY_VALUE = 6; +INST "*data_bus[0].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[1].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[2].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[3].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[4].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[5].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[6].delay_gmii_rxd" IDELAY_VALUE = 6; +INST "*data_bus[7].delay_gmii_rxd" IDELAY_VALUE = 6; + +# Group IODELAY and IDELAYCTRL components to aid placement +# INST "*delay_gmii_rx_clk" IODELAY_GROUP = "grp1"; +INST "*delay_gmii_rx_dv" IODELAY_GROUP = "grp1"; +INST "*delay_gmii_rx_er" IODELAY_GROUP = "grp1"; +INST "*delay_gmii_rxd" IODELAY_GROUP = "grp1"; +# INST "*dlyctrl" IODELAY_GROUP = "grp1"; + +# Changed to let the tools pick the LOC +# INST *trimac_block*clock_inst*BUFGMUX_SPEED_CLK LOC = BUFGMUX_X3Y13; + +############################################################ +# For Setup and Hold time analysis on GMII inputs # +############################################################ +# Identify GMII Rx Pads only. +# This prevents setup/hold analysis being performed on false inputs, +# eg, the configuration_vector inputs. +# Changed to remove TNM and changed INST Names +# INST "gmii_rxd" TNM = IN_GMII; +# INST "gmii_rx_er" TNM = IN_GMII; +# INST "gmii_rx_dv" TNM = IN_GMII; + +# Define data valid window with respect to the clock. +# The spec states that, worst case, the data is valid 2 ns before the clock edge. +# The worst case it to provide zero hold time (a 2ns window in total) +# Changed to remove TIMEGRP +# TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_rx_clk"; +# Set to allow for 100ps setup/hold trace delay difference in relation to clock +OFFSET = IN 2.4 ns VALID 2.8 ns BEFORE "ETHERNET_RX_CLK"; + +############################################################ +# Crossing of Clock Domain Constraints: please do not edit # +############################################################ +# Flow Control logic reclocking - control signal is synchronised +# Changed net name in synthesis of axi_ethernet +# INST "*trimac_core*FLOW?RX_PAUSE?PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx"; +# INST "*trimac_core*FLOW?RX_PAUSE?PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx"; +INST "*/I_FLOW/I_RX_PAUSE/PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx"; +INST "*/I_FLOW/I_RX_PAUSE/PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx"; +TIMESPEC "TS_flow_rx_to_tx" = FROM "flow_rx_to_tx" TO phy_clk_tx 8000 ps DATAPATHONLY; + +# Generate a group of all flops NOT in the host clock domain +TIMEGRP "all_ffs" = FFS; +TIMEGRP "ffs_except_host" = "all_ffs" EXCEPT "host"; + +# Configuration Register reclocking +# Changed net name in synthesis of axi_ethernet +# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?RX0_OUT*" TNM="async_config"; +# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?RX1_OUT*" TNM="async_config"; +# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?FC_OUT_29" TNM="async_config"; +INST "*/MANIFGEN.I_MANAGEN/I_CONF/RX0_OUT*" TNM="async_config"; +INST "*/MANIFGEN.I_MANAGEN/I_CONF/RX1_OUT*" TNM="async_config"; +INST "*/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_29" TNM="async_config"; + +# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?TX_OUT*" TNM="async_config"; +# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?FC_OUT_30" TNM="async_config"; +INST "*/MANIFGEN.I_MANAGEN/I_CONF/TX_OUT*" TNM="async_config"; +INST "*/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_30" TNM="async_config"; + +# Speed change config +# Changed net name in synthesis of axi_ethernet +# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?CNFG_SPEED*" TNM="async_config"; +# INST "*trimac_core*SPEED_IS*" TNM="async_config"; +INST "*/MANIFGEN.I_MANAGEN/I_CONF/CNFG_SPEED*" TNM="async_config"; +INST "*/I_?XGEN/*SPEED*" TNM="async_config"; + +# Changed to comment out. +# In BSB systems the Host_clk = S_AXI_ACLK. Since the CORE Gen TIG'd constraints below +# are affecting axi_ethernet DATAPATHONLY constraints above (at start of Soft_Ethernet_MAC constraints) +# these paths are commented out in favor of using the DATAPATHONLY constraints. The constraints are: +# "TS_axi4lite_clk_clk_2_TX_CLIENT_CLK" and "TS_TX_CLIENT_CLK_2_axi4lite_clk_clk" +# TIMESPEC "TS_host_clk_to_rx_clk" = FROM "host" TO "rx_clock" TIG; +# TIMESPEC "TS_host_clk_to_tx_clk" = FROM "host" TO "tx_clock_gmii" TIG; + +TIMESPEC "TS_config_to_all" = FROM "async_config" TO "ffs_except_host" TIG; + +# Address filter specific cross clocking +# Changed net name in synthesis of axi_ethernet +# INST "*trimac_core*addr_filter_top/dynamic_af_gen.dynamic_config/unicast_addr_*" TNM="addr_config_to_rx"; +INST "*/I_ADDR_FILTER_TOP/dynamic_af_gen.I_DYNAMIC_CONFIG/unicast_addr_*" TNM="addr_config_to_rx"; +TIMESPEC "TS_addr_config_to_rx" = FROM "addr_config_to_rx" TO "ffs_except_host" TIG; + +############################################################ +# Ignore paths to resync flops # +############################################################ +# Changed to replace TIG with DATAPATHONLY constraints +# INST "*data_sync" TNM = "resync_reg"; +# TIMESPEC "ts_resync_flops" = TO "resync_reg" TIG; + +###################################################################### +# MDIO Constraints: please do not edit unless TS_host_clk is relaxed # +# in which case the multiplier needs to be adjusted to give the # +# required 400ns (or faster) # +###################################################################### + +# Place the MDIO logic in it's own timing groups +# Changed net name in synthesis of axi_ethernet +# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?ENABLE_REG" TNM = "mdio_logic"; +# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?READY_INT" TNM = "mdio_logic"; +# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?STATE_COUNT*" TNM = FFS "mdio_logic"; +# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?MDIO_TRISTATE" TNM = "mdio_logic"; +# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?MDIO_OUT" TNM = "mdio_logic"; +INST "*/I_RXGEN/ENABLE_REG" TNM = "mdio_logic"; +INST "*/MANIFGEN.I_MANAGEN/MIIM_READY_INT" TNM = "mdio_logic"; +INST "*/MANIFGEN.I_MANAGEN/I_PHY/STATE_COUNT*" TNM = FFS "mdio_logic"; +INST "*/MANIFGEN.I_MANAGEN/I_PHY/MDIO_TRISTATE" TNM = "mdio_logic"; +INST "*/MANIFGEN.I_MANAGEN/I_PHY/MDIO_OUT" TNM = "mdio_logic"; + +# The MDIO logic is constrained to a 400ns period. this is generated by relating the required +# period to that specified for host_clk. This ensures the two clocks are related timed +# correctly. +TIMESPEC "TS_mdio" = PERIOD "mdio_logic" "TS_host_clk" * 40 PRIORITY 0; + +############################################################ +# Crossing of Clock Domain Constraints: please do not edit # +# In addition to CoreGen constraints # +############################################################ + +# The following TimeSpecs are required only when AXILite clock differs from AXI-Stream clock +# Data path timing depends on the destination clock period +TIMESPEC "TS_axistreamclks_2_axi4liteclks" = FROM axistream_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz +TIMESPEC "TS_axi4liteclks_2_axistreamclks" = FROM axi4lite_clk TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz + +# TNM_NET phy_clk_rx is rx_client_clk +# TIMESPECs for AXI streaming clock crossing to/from rx_client_clk +TIMESPEC "TS_axistreamclks_2_RX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz +TIMESPEC "TS_RX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_rx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz +# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk +TIMESPEC "TS_axi4liteclks_2_RX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz +TIMESPEC "TS_RX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_rx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz + +# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx +# or TNM_NET phy_clk_tx so only one set will be analyzed +# TNM_NET phy_clk_tx is tx_client_clk +# TIMESPECs for AXI streaming clock crossing to/from tx_client_clk +TIMESPEC "TS_axistreamclks_2_TX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz +TIMESPEC "TS_TX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_tx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz +# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk +TIMESPEC "TS_axi4liteclks_2_TX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz +TIMESPEC "TS_TX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_tx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz + +# TNM_NET clk_gtx is */GTX_CLK +# TIMESPECs for AXI Streaming clock crossing to/from */GTX_CLK +TIMESPEC "TS_axistreamclks_2_GTX_CLK" = FROM axistream_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz +TIMESPEC "TS_GTX_CLK_2_axistreamclks" = FROM clk_gtx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz +# TIMESPECs for AXI-Lite clock crossing to/from */GTX_CLK +TIMESPEC "TS_axi4lite_clk_2_GTX_CLK" = FROM axi4lite_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz +TIMESPEC "TS_GTX_CLK_2_axi4lite_clk" = FROM clk_gtx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz + +# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx +# or TNM_NET phy_clk_tx so only one set will be analyzed +# Rx Clock crossings - Some paths are analyzed by the TS_flow_rx_to_tx constraint also +# Needed since ts_resync_flops is commented out +TIMESPEC "TS_RX_CLIENT_CLK_2_TX_CLIENT_CLK" = FROM phy_clk_rx TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz +TIMESPEC "TS_TX_CLIENT_CLK_2_RX_CLIENT_CLK" = FROM phy_clk_tx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz +TIMESPEC "TS_RX_CLIENT_CLK_2_GTX_CLK" = FROM phy_clk_rx TO clk_gtx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz +TIMESPEC "TS_GTX_CLK_2_RX_CLIENT_CLK" = FROM clk_gtx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/bitgen.ut b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/bitgen.ut new file mode 100644 index 0000000000..bca21c81b1 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/bitgen.ut @@ -0,0 +1,3 @@ +-g TdoPin:PULLNONE +-g StartUpClk:JTAGCLK +#add other options here. diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/download.cmd b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/download.cmd new file mode 100644 index 0000000000..da4d7717e1 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 2 -file implementation/download.bit +program -p 2 +quit diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/fast_runtime.opt b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/fast_runtime.opt new file mode 100644 index 0000000000..994a6d2f85 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/fast_runtime.opt @@ -0,0 +1,84 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-w; # Overwrite output files. +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +-detail; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters new file mode 100644 index 0000000000..d4000c0c30 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui new file mode 100644 index 0000000000..0f1452183c --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui @@ -0,0 +1,218 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html new file mode 100644 index 0000000000..c14fba7dd3 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/implementation/system_summary.html @@ -0,0 +1,565 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + +
Project Status (08/27/2011 - 07:43:24)
Project File:system.xmpImplementation State:Programming File Generated
Module Name:system
  • Errors:
 +No Errors
Product Version:EDK 13.1
  • Warnings:
238 Warnings (237 new)
+ + + + 
+ + + + + + + + +
XPS Reports [-]
Report NameGeneratedErrorsWarningsInfos
Platgen Log FileFri 26. Aug 21:18:30 2011019 Warnings (19 new)35 Infos (35 new)
Libgen Log File    
Simgen Log File    
BitInit Log File    
System Log FileFri 26. Aug 21:36:10 2011   
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemFri 26. Aug 21:19:20 20111469614249420
axi_timer_0_wrapperFri 26. Aug 21:17:55 2011260272 0
microblaze_0_intc_wrapperFri 26. Aug 21:17:45 201186115 0
ethernet_dma_wrapperFri 26. Aug 21:17:37 201137283798 0
ethernet_dma_wrapper_fifo_generator_v8_1_6_fifo_generator_v8_1_xst_1Fri 26. Aug 21:16:56 2011107109 0
ethernet_dma_wrapper_fifo_generator_v8_1_7_fifo_generator_v8_1_xst_1Fri 26. Aug 21:15:53 201198100 0
ethernet_dma_wrapper_fifo_generator_v8_1_2_fifo_generator_v8_1_xst_1Fri 26. Aug 21:14:50 2011684910
ethernet_dma_wrapper_fifo_generator_v8_1_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:13:47 2011745910
ethernet_dma_wrapper_fifo_generator_v8_1_5_fifo_generator_v8_1_xst_1Fri 26. Aug 21:12:44 2011694910
ethernet_dma_wrapper_fifo_generator_v8_1_4_fifo_generator_v8_1_xst_1Fri 26. Aug 21:11:41 201199103 0
ethernet_dma_wrapper_fifo_generator_v8_1_3_fifo_generator_v8_1_xst_1Fri 26. Aug 21:10:39 20119798 0
ethernet_wrapperFri 26. Aug 21:09:24 201131663264 0
ethernet_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:08:27 2011104148 0
ethernet_wrapper_blk_mem_gen_v5_2_2_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:07:29 2011  10
ethernet_wrapper_blk_mem_gen_v5_2_1_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:07:03 2011  20
ethernet_wrapper_blk_mem_gen_v5_2_4_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:06:36 2011  10
ethernet_wrapper_blk_mem_gen_v5_2_3_blk_mem_gen_v5_2_xst_1Fri 26. Aug 21:06:10 201124920
mcb_ddr3_wrapperFri 26. Aug 21:04:44 2011373691 0
push_buttons_4bits_wrapperFri 26. Aug 21:04:24 20117285 0
leds_4bits_wrapperFri 26. Aug 21:04:14 20113341 0
rs232_uart_1_wrapperFri 26. Aug 21:04:05 201184102 0
debug_module_wrapperFri 26. Aug 21:03:57 2011131142 0
clock_generator_0_wrapperFri 26. Aug 21:03:48 2011 1 0
proc_sys_reset_0_wrapperFri 26. Aug 21:03:43 20116955 0
microblaze_0_bram_block_wrapperFri 26. Aug 21:03:37 2011  320
microblaze_0_d_bram_ctrl_wrapperFri 26. Aug 21:03:30 201126 0
microblaze_0_i_bram_ctrl_wrapperFri 26. Aug 21:03:25 201126 0
microblaze_0_dlmb_wrapperFri 26. Aug 21:03:19 201111 0
microblaze_0_ilmb_wrapperFri 26. Aug 21:03:15 201111 0
microblaze_0_wrapperFri 26. Aug 21:03:10 201113011703 0
axi4lite_0_wrapperFri 26. Aug 21:02:41 201129051828 0
axi4_0_wrapperFri 26. Aug 21:02:14 201114881083 0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_2_fifo_generator_v8_1_xst_1Fri 26. Aug 21:01:57 2011909720
axi4_0_wrapper_FIFO_GENERATOR_V8_1_1_fifo_generator_v8_1_xst_1Fri 26. Aug 21:00:49 2011899610
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary (actual values) [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers12,06054,57622% 
    Number used as Flip Flops12,052   
    Number used as Latches0   
    Number used as Latch-thrus0   
    Number used as AND/OR logics8   
Number of Slice LUTs10,97327,28840% 
    Number used as logic9,64127,28835% 
        Number using O6 output only6,887   
        Number using O5 output only261   
        Number using O5 and O62,493   
        Number used as ROM0   
    Number used as Memory6936,40810% 
        Number used as Dual Port RAM250   
            Number using O6 output only10   
            Number using O5 output only4   
            Number using O5 and O6236   
        Number used as Single Port RAM1   
            Number using O6 output only1   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Shift Register442   
            Number using O6 output only205   
            Number using O5 output only7   
            Number using O5 and O6230   
    Number used exclusively as route-thrus639   
        Number with same-slice register load597   
        Number with same-slice carry load37   
        Number with other load5   
Number of occupied Slices4,5206,82266% 
Number of LUT Flip Flop pairs used13,731   
    Number with an unused Flip Flop3,68613,73126% 
    Number with an unused LUT2,75813,73120% 
    Number of fully used LUT-FF pairs7,28713,73153% 
    Number of unique control sets697   
    Number of slice register sites lost
        to control set restrictions		2,54154,5764% 
Number of bonded IOBs8729629% 
    Number of LOCed IOBs8787100% 
    IOB Flip Flops27   
Number of RAMB16BWERs4011634% 
Number of RAMB8BWERs42321% 
Number of BUFIO2/BUFIO2_2CLKs3329% 
    Number used as BUFIO2s3   
    Number used as BUFIO2_2CLKs0   
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs61637% 
    Number used as BUFGs5   
    Number used as BUFGMUX1   
Number of DCM/DCM_CLKGENs080% 
Number of ILOGIC2/ISERDES2s123763% 
    Number used as ILOGIC2s12   
    Number used as ISERDES2s0   
Number of IODELAY2/IODRP2/IODRP2_MCBs343769% 
    Number used as IODELAY2s10   
    Number used as IODRP2s2   
    Number used as IODRP2_MCBs22   
Number of OLOGIC2/OSERDES2s6037615% 
    Number used as OLOGIC2s14   
    Number used as OSERDES2s46   
Number of BSCANs1425% 
Number of BUFHs02560% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs1425% 
Number of DSP48A1s3585% 
Number of GTPA1_DUALs020% 
Number of ICAPs010% 
Number of MCBs1250% 
Number of PCIE_A1s010% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs2450% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets3.95   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0, Component Switching Limit: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +All Constraints Met  
+ + + + 
+ + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Translation ReportCurrentFri 26. Aug 21:20:32 2011087 Warnings (86 new)13 Infos (13 new)
Map ReportCurrentFri 26. Aug 21:30:17 2011050 Warnings (50 new)1134 Infos (1134 new)
Place and Route ReportCurrentFri 26. Aug 21:33:52 2011051 Warnings (51 new)3 Infos (3 new)
Post-PAR Static Timing ReportCurrentFri 26. Aug 21:34:50 201103 Warnings (3 new)3 Infos (3 new)
Bitgen ReportCurrentFri 26. Aug 21:36:07 2011047 Warnings (47 new)0
+ 
+ + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentFri 26. Aug 21:36:10 2011
+ + +
Date Generated: 08/27/2011 - 07:43:25
+ \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.bsb b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.bsb new file mode 100644 index 0000000000..85c9d79947 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.bsb @@ -0,0 +1 @@ +Įtt@Dbb\b\`bDv*Įtt@D\D@Dl`jD@DDv.Įttʄ@DD@DlDv.Įttʄ@DD@DlhjDv'Įttʄ@DD@DhphDv'Įttʄ@DD@DbDv&Įttʄ@DD@DZfDv%Įtt@DľҾbD@Db\`Dv;Įttʦ@D־D@Dd````````D@Dʾ`Dv@ĮttȠ@Dʾ`D@DD@Dʾ`DvHĮttʆ@Dʾ`D@D¾ʾھD@DfDv@Įttʆ@Dʾ`D@D¾ʾD@DpbrdDvIĮttʆ@Dʾ`D@DʾھD@DfDvAĮttʆ@Dʾ`D@DʾD@DpbrdDvHĮttʆ@Dʾ`D@Dľ־D@Db````````Dv>Įttʆ@Dʾ`D@DľD@DDvFĮttʆ@Dʾ`D@DľؾD@DljjflDv?ĮttȠ@DD@DҾD@Dʾ`Dv;Įttʆ@DD@D¾`D@DDv=Įttʆ@DD@DʾD@DDv=ĮttȠ@DhD@DҾD@Dʾ`Dv@Įttʆ@DhD@DʾD@DDv>ĮttȠ@DfD@DҾlD@Dʾ`DvEĮttȠ@DоhD@DҾD@Dʾ`DvHĮttʆ@DоhD@DʾD@DDvCĮttȠ@DdfdbD@DҾD@Dʾ`DvAĮttʆ@DdfdbD@D`ȾD@Drl``Dv>Įttʆ@DdfdbD@D`D@DpDv>Įttʆ@DdfdbD@D`D@DDvBĮttʆ@DdfdbD@DʾD@DDv \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.make b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.make new file mode 100644 index 0000000000..87c158c232 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.make @@ -0,0 +1,216 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetFull\PlatformStudioProject\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetFull\PlatformStudioProject\system.mhs + +include system_incl.make + +################################################################# +# PHONY TARGETS +################################################################# +.PHONY: dummy +.PHONY: netlistclean +.PHONY: bitsclean +.PHONY: simclean +.PHONY: exporttosdk + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " exporttosdk: Export files to SDK" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " simclean : Deletes simulation dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +exporttosdk: $(SYSTEM_HW_HANDOFF_DEP) + +netlist: $(POSTSYN_NETLIST) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral & \ + system_fuse.cmd + cd simulation/behavioral & \ + start /B $(SIM_CMD) -gui -tclbatch system_setup.tcl + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +clean: hwclean simclean + rm -f _impact.cmd + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + rm -f __xps/ise/_xmsgs/bitinit.xmsgs + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f platgen.log + rm -f __xps/ise/_xmsgs/platgen.xmsgs + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + rm -f implementation/$(SYSTEM)_map.ncd + rm -f implementation/download.bit + rm -f __xps/$(SYSTEM)_routed + +simclean: + rm -rf simulation/behavioral + rm -f simgen.log + rm -f __xps/ise/_xmsgs/simgen.xmsgs + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + +$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP_LE) + IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)" + cp -f $(MICROBLAZE_BOOTLOOP_LE) $(MICROBLAZE_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + cd synthesis & synthesis.cmd + +__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + @cp -f etc/fast_runtime.opt implementation/xflow.opt + xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc + touch __xps/$(SYSTEM)_routed + +$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE) + xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par + @echo "*********************************************" + @echo "Running Bitgen.." + @echo "*********************************************" + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd .. + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt + @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): + @echo "In order to generate ace file, you must have:-" + @echo "- exactly one processor." + @echo "- opb_mdm, if using microblaze." + +################################################################# +# EXPORT_TO_SDK FLOW +################################################################# + +$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt + IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)" + psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT) + xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local + +$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT) + @rm -rf $(SYSTEM_HW_HANDOFF_BIT) + @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR) + +$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm + @rm -rf $(SYSTEM_HW_HANDOFF_BMM) + @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed + +$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs new file mode 100644 index 0000000000..37a4f5b4ce --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs @@ -0,0 +1,458 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d +# Fri Aug 26 19:44:08 2011 +# Target Board: xilinx.com sp605 Rev C +# Family: spartan6 +# Device: xc6slx45t +# Package: fgg484 +# Speed Grade: -3 +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 + PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 + PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 + PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O + PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I + PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [3:0] + PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [3:0] + PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O + PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O + PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O + PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O + PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O + PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O + PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O + PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O + PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O + PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0] + PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0] + PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O + PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0] + PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO + PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO + PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO + PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO + PORT rzq = rzq, DIR = IO + PORT zio = zio, DIR = IO + PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO + PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O + PORT ETHERNET_TX_ER = ETHERNET_TX_ER, DIR = O + PORT ETHERNET_TXD = ETHERNET_TXD, DIR = O, VEC = [7:0] + PORT ETHERNET_TX_EN = ETHERNET_TX_EN, DIR = O + PORT ETHERNET_MII_TX_CLK = ETHERNET_MII_TX_CLK, DIR = I + PORT ETHERNET_TX_CLK = ETHERNET_TX_CLK, DIR = O + PORT ETHERNET_RXD = ETHERNET_RXD, DIR = I, VEC = [7:0] + PORT ETHERNET_RX_ER = ETHERNET_RX_ER, DIR = I + PORT ETHERNET_RX_CLK = ETHERNET_RX_CLK, DIR = I + PORT ETHERNET_RX_DV = ETHERNET_RX_DV, DIR = I + PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O + + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4_0 + PARAMETER HW_VER = 1.02.a + PORT interconnect_aclk = clk_100_0000MHzPLL0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4lite_0 + PARAMETER HW_VER = 1.02.a + PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn + PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0 +END + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_0 + PARAMETER HW_VER = 8.10.a + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_BARREL = 1 + PARAMETER C_USE_FPU = 0 + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_ICACHE_BASEADDR = 0xc0000000 + PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff + PARAMETER C_USE_ICACHE = 0 + PARAMETER C_ICACHE_ALWAYS_USED = 1 + PARAMETER C_DCACHE_BASEADDR = 0xc0000000 + PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff + PARAMETER C_USE_DCACHE = 0 + PARAMETER C_DCACHE_ALWAYS_USED = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 7 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2 + BUS_INTERFACE M_AXI_DP = axi4lite_0 + BUS_INTERFACE DEBUG = microblaze_0_debug + BUS_INTERFACE DLMB = microblaze_0_dlmb + BUS_INTERFACE ILMB = microblaze_0_ilmb + PORT MB_RESET = proc_sys_reset_0_MB_Reset + PORT CLK = clk_100_0000MHzPLL0 + PORT INTERRUPT = microblaze_0_interrupt +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_ilmb + PARAMETER HW_VER = 2.00.a + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzPLL0 +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_dlmb + PARAMETER HW_VER = 2.00.a + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzPLL0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_i_bram_ctrl + PARAMETER HW_VER = 3.00.a + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = microblaze_0_ilmb + BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_d_bram_ctrl + PARAMETER HW_VER = 3.00.a + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = microblaze_0_dlmb + BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN bram_block + PARAMETER INSTANCE = microblaze_0_bram_block + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block + BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER HW_VER = 3.00.a + PARAMETER C_EXT_RESET_HIGH = 1 + PORT Ext_Reset_In = RESET + PORT MB_Reset = proc_sys_reset_0_MB_Reset + PORT Slowest_sync_clk = clk_50_0000MHzPLL0 + PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn + PORT Dcm_locked = proc_sys_reset_0_Dcm_locked + PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst + PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER HW_VER = 4.01.a + PARAMETER C_CLKIN_FREQ = 200000000 + PARAMETER C_CLKOUT0_FREQ = 600000000 + PARAMETER C_CLKOUT0_GROUP = PLL0 + PARAMETER C_CLKOUT0_BUF = FALSE + PARAMETER C_CLKOUT1_FREQ = 600000000 + PARAMETER C_CLKOUT1_PHASE = 180 + PARAMETER C_CLKOUT1_GROUP = PLL0 + PARAMETER C_CLKOUT1_BUF = FALSE + PARAMETER C_CLKOUT2_FREQ = 100000000 + PARAMETER C_CLKOUT2_GROUP = PLL0 + PARAMETER C_CLKOUT3_FREQ = 125000000 + PARAMETER C_CLKOUT3_GROUP = NONE + PARAMETER C_CLKOUT4_FREQ = 200000000 + PARAMETER C_CLKOUT4_GROUP = PLL0 + PARAMETER C_CLKOUT5_FREQ = 50000000 + PARAMETER C_CLKOUT5_GROUP = PLL0 + PORT RST = RESET + PORT CLKIN = CLK + PORT CLKOUT2 = clk_100_0000MHzPLL0 + PORT CLKOUT5 = clk_50_0000MHzPLL0 + PORT CLKOUT3 = clk_125_0000MHz + PORT CLKOUT4 = clk_200_0000MHzPLL0 + PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf + PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf + PORT LOCKED = proc_sys_reset_0_Dcm_locked +END + +BEGIN mdm + PARAMETER INSTANCE = debug_module + PARAMETER HW_VER = 2.00.b + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_UART = 1 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x74800000 + PARAMETER C_HIGHADDR = 0x7480ffff + BUS_INTERFACE S_AXI = axi4lite_0 + BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst +END + +BEGIN axi_uartlite + PARAMETER INSTANCE = RS232_Uart_1 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BAUDRATE = 115200 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_ODD_PARITY = 1 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT TX = RS232_Uart_1_sout + PORT RX = RS232_Uart_1_sin + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Interrupt = RS232_Uart_1_Interrupt +END + +BEGIN axi_gpio + PARAMETER INSTANCE = LEDs_4Bits + PARAMETER HW_VER = 1.01.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40020000 + PARAMETER C_HIGHADDR = 0x4002ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT GPIO_IO_O = LEDs_4Bits_TRI_O + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 +END + +BEGIN axi_gpio + PARAMETER INSTANCE = Push_Buttons_4Bits + PARAMETER HW_VER = 1.01.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_INTERRUPT_PRESENT = 1 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40000000 + PARAMETER C_HIGHADDR = 0x4000ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT IP2INTC_Irpt = Push_Buttons_4Bits_IP2INTC_Irpt +END + +BEGIN axi_s6_ddrx + PARAMETER INSTANCE = MCB_DDR3 + PARAMETER HW_VER = 1.02.a + PARAMETER C_MCB_RZQ_LOC = K7 + PARAMETER C_MCB_ZIO_LOC = R7 + PARAMETER C_MEM_TYPE = DDR3 + PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E + PARAMETER C_MEM_BANKADDR_WIDTH = 3 + PARAMETER C_MEM_NUM_COL_BITS = 10 + PARAMETER C_SKIP_IN_TERM_CAL = 0 + PARAMETER C_S0_AXI_ENABLE = 1 + PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM + PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1 + PARAMETER C_S0_AXI_BASEADDR = 0x80000000 + PARAMETER C_S0_AXI_HIGHADDR = 0x87ffffff + BUS_INTERFACE S0_AXI = axi4_0 + PORT mcbx_dram_clk = mcbx_dram_clk + PORT mcbx_dram_clk_n = mcbx_dram_clk_n + PORT mcbx_dram_cke = mcbx_dram_cke + PORT mcbx_dram_odt = mcbx_dram_odt + PORT mcbx_dram_ras_n = mcbx_dram_ras_n + PORT mcbx_dram_cas_n = mcbx_dram_cas_n + PORT mcbx_dram_we_n = mcbx_dram_we_n + PORT mcbx_dram_udm = mcbx_dram_udm + PORT mcbx_dram_ldm = mcbx_dram_ldm + PORT mcbx_dram_ba = mcbx_dram_ba + PORT mcbx_dram_addr = mcbx_dram_addr + PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst + PORT mcbx_dram_dq = mcbx_dram_dq + PORT mcbx_dram_dqs = mcbx_dram_dqs + PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n + PORT mcbx_dram_udqs = mcbx_dram_udqs + PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n + PORT rzq = rzq + PORT zio = zio + PORT s0_axi_aclk = clk_100_0000MHzPLL0 + PORT ui_clk = clk_100_0000MHzPLL0 + PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf + PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked +END + +BEGIN axi_ethernet + PARAMETER INSTANCE = ETHERNET + PARAMETER HW_VER = 2.01.a + PARAMETER C_PHYADDR = 0B00001 + PARAMETER C_INCLUDE_IO = 1 + PARAMETER C_TYPE = 1 + PARAMETER C_PHY_TYPE = 1 + PARAMETER C_HALFDUP = 0 + PARAMETER C_TXMEM = 4096 + PARAMETER C_RXMEM = 4096 + PARAMETER C_TXCSUM = 0 + PARAMETER C_RXCSUM = 0 + PARAMETER C_TXVLAN_TRAN = 0 + PARAMETER C_RXVLAN_TRAN = 0 + PARAMETER C_TXVLAN_TAG = 0 + PARAMETER C_RXVLAN_TAG = 0 + PARAMETER C_TXVLAN_STRP = 0 + PARAMETER C_RXVLAN_STRP = 0 + PARAMETER C_MCAST_EXTEND = 0 + PARAMETER C_STATS = 0 + PARAMETER C_AVB = 0 + PARAMETER C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41240000 + PARAMETER C_HIGHADDR = 0x4127ffff + BUS_INTERFACE S_AXI = axi4lite_0 + BUS_INTERFACE AXI_STR_TXD = ETHERNET_dma_txd + BUS_INTERFACE AXI_STR_TXC = ETHERNET_dma_txc + BUS_INTERFACE AXI_STR_RXS = ETHERNET_dma_rxs + BUS_INTERFACE AXI_STR_RXD = ETHERNET_dma_rxd + PORT MDIO = ETHERNET_MDIO + PORT MDC = ETHERNET_MDC + PORT GMII_TX_ER = ETHERNET_TX_ER + PORT GMII_TXD = ETHERNET_TXD + PORT GMII_TX_EN = ETHERNET_TX_EN + PORT MII_TX_CLK = ETHERNET_MII_TX_CLK + PORT GMII_TX_CLK = ETHERNET_TX_CLK + PORT GMII_RXD = ETHERNET_RXD + PORT GMII_RX_ER = ETHERNET_RX_ER + PORT GMII_RX_CLK = ETHERNET_RX_CLK + PORT GMII_RX_DV = ETHERNET_RX_DV + PORT PHY_RST_N = ETHERNET_PHY_RST_N + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT GTX_CLK = clk_125_0000MHz + PORT REF_CLK = clk_200_0000MHzPLL0 + PORT AXI_STR_TXD_ACLK = clk_100_0000MHzPLL0 + PORT AXI_STR_TXC_ACLK = clk_100_0000MHzPLL0 + PORT AXI_STR_RXD_ACLK = clk_100_0000MHzPLL0 + PORT AXI_STR_RXS_ACLK = clk_100_0000MHzPLL0 + PORT AXI_STR_TXD_ARESETN = AXI_STR_TXD_ARESETN + PORT AXI_STR_TXC_ARESETN = AXI_STR_TXC_ARESETN + PORT AXI_STR_RXD_ARESETN = AXI_STR_RXD_ARESETN + PORT AXI_STR_RXS_ARESETN = AXI_STR_RXS_ARESETN + PORT INTERRUPT = ETHERNET_INTERRUPT +END + +BEGIN axi_dma + PARAMETER INSTANCE = ETHERNET_dma + PARAMETER HW_VER = 3.00.a + PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1 + PARAMETER C_SG_USE_STSAPP_LENGTH = 1 + PARAMETER C_INCLUDE_MM2S_DRE = 1 + PARAMETER C_INCLUDE_S2MM_DRE = 1 + PARAMETER C_DLYTMR_RESOLUTION = 1250 + PARAMETER C_PRMRY_IS_ACLK_ASYNC = 0 + PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 1 + PARAMETER C_SG_LENGTH_WIDTH = 16 + PARAMETER C_INCLUDE_MM2S = 1 + PARAMETER C_INCLUDE_S2MM = 1 + PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41e00000 + PARAMETER C_HIGHADDR = 0x41e0ffff + BUS_INTERFACE S_AXI_LITE = axi4lite_0 + BUS_INTERFACE M_AXI_SG = axi4_0 + BUS_INTERFACE M_AXI_MM2S = axi4_0 + BUS_INTERFACE M_AXI_S2MM = axi4_0 + BUS_INTERFACE M_AXIS_MM2S = ETHERNET_dma_txd + BUS_INTERFACE M_AXIS_CNTRL = ETHERNET_dma_txc + BUS_INTERFACE S_AXIS_STS = ETHERNET_dma_rxs + BUS_INTERFACE S_AXIS_S2MM = ETHERNET_dma_rxd + PORT s_axi_lite_aclk = clk_100_0000MHzPLL0 + PORT m_axi_sg_aclk = clk_100_0000MHzPLL0 + PORT m_axi_mm2s_aclk = clk_100_0000MHzPLL0 + PORT m_axi_s2mm_aclk = clk_100_0000MHzPLL0 + PORT mm2s_prmry_reset_out_n = AXI_STR_TXD_ARESETN + PORT mm2s_cntrl_reset_out_n = AXI_STR_TXC_ARESETN + PORT s2mm_prmry_reset_out_n = AXI_STR_RXD_ARESETN + PORT s2mm_sts_reset_out_n = AXI_STR_RXS_ARESETN + PORT mm2s_introut = ETHERNET_dma_mm2s_introut + PORT s2mm_introut = ETHERNET_dma_s2mm_introut +END + +BEGIN axi_intc + PARAMETER INSTANCE = microblaze_0_intc + PARAMETER HW_VER = 1.01.a + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT IRQ = microblaze_0_interrupt + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT INTR = ETHERNET_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut & Push_Buttons_4Bits_IP2INTC_Irpt & RS232_Uart_1_Interrupt & axi_timer_0_Interrupt +END + +BEGIN axi_timer + PARAMETER INSTANCE = axi_timer_0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Interrupt = axi_timer_0_Interrupt +END + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp new file mode 100644 index 0000000000..3862cd3d63 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp @@ -0,0 +1,38 @@ +#Please do not modify this file by hand +XmpVersion: 13.1 +VerMgmt: 13.1 +IntStyle: default +MHS File: system.mhs +Architecture: spartan6 +Device: xc6slx45t +Package: fgg484 +SpeedGrade: -3 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +GenSimTB: 0 +SdkExportBmmBit: 1 +SdkExportDir: SDK/SDK_Export +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +SimModel: BEHAVIORAL +UcfFile: data/system.ucf +EnableParTimingError: 1 +ShowLicenseDialog: 1 +ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR +Processor: microblaze_0 +ElfImp: +ElfSim: diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system_incl.make b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system_incl.make new file mode 100644 index 0000000000..b73b933aa6 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system_incl.make @@ -0,0 +1,111 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetFull\PlatformStudioProject\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +SHELL = CMD + +XILINX_EDK_DIR = C:/devtools/Xilinx/13.1/ISE_DS/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +FPGA_ARCH = spartan6 + +DEVICE = xc6slx45tfgg484-3 + +LANGUAGE = vhdl +GLOBAL_SEARCHPATHOPT = +PROJECT_SEARCHPATHOPT = + +SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst + +OBSERVE_PAR_OPTIONS = -error yes + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf +BOOTLOOP_DIR = bootloops + +MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf + +BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP) +BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) + +BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP) +BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) + +SIM_CMD = isim_system + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s isim + + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/axi4_0_wrapper.ngc \ +implementation/axi4lite_0_wrapper.ngc \ +implementation/microblaze_0_wrapper.ngc \ +implementation/microblaze_0_ilmb_wrapper.ngc \ +implementation/microblaze_0_dlmb_wrapper.ngc \ +implementation/microblaze_0_i_bram_ctrl_wrapper.ngc \ +implementation/microblaze_0_d_bram_ctrl_wrapper.ngc \ +implementation/microblaze_0_bram_block_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/debug_module_wrapper.ngc \ +implementation/rs232_uart_1_wrapper.ngc \ +implementation/leds_4bits_wrapper.ngc \ +implementation/push_buttons_4bits_wrapper.ngc \ +implementation/mcb_ddr3_wrapper.ngc \ +implementation/ethernet_wrapper.ngc \ +implementation/ethernet_dma_wrapper.ngc \ +implementation/microblaze_0_intc_wrapper.ngc \ +implementation/axi_timer_0_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +BITGEN_UT_FILE = etc/bitgen.ut + +XFLOW_OPT_FILE = etc/fast_runtime.opt +XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) + +XPLORER_DEPENDENCY = __xps/xplorer.opt +XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 + +FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY) + +SDK_EXPORT_DIR = SDK\SDK_Export\hw +SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml +SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit +SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm +SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)