Add IAR MPU project for STM32L475 Discovery Kit IoT Node
Gaurav Aggarwal
5 years ago
parent
96b6746364
commit
ce7e8b87d8
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<?xml version="1.0" encoding="UTF-8"?>
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<workspace>
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<project>
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<path>$WS_DIR$\MPUDemo.ewp</path>
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</project>
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<batchBuild />
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</workspace>
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@ -0,0 +1,43 @@
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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EXTERN vHandleMemoryFault
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PUBLIC MemManage_Handler
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SECTION .text:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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MemManage_Handler:
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tst lr, #4
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ite eq
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mrseq r0, msp
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mrsne r0, psp
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b vHandleMemoryFault
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/*-----------------------------------------------------------*/
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END
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@ -0,0 +1,630 @@
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;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
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;* File Name : startup_stm32l475xx.s
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;* Author : MCD Application Team
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;* Description : STM32L475xx Ultra Low Power Devices vector
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == _iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;*******************************************************************************
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;
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_2_IRQHandler ; ADC1, ADC2
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DCD CAN1_TX_IRQHandler ; CAN1 TX
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DCD CAN1_RX0_IRQHandler ; CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
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DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
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DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
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DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
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DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
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DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
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DCD ADC3_IRQHandler ; ADC3 global Interrupt
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DCD FMC_IRQHandler ; FMC
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DCD SDMMC1_IRQHandler ; SDMMC1
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD UART5_IRQHandler ; UART5
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
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DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
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DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
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DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
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DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
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DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
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DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
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DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
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DCD COMP_IRQHandler ; COMP Interrupt
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DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
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DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
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DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
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DCD LPUART1_IRQHandler ; LP UART 1 interrupt
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DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
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DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
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DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
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DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; RNG global interrupt
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DCD FPU_IRQHandler ; FPU
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK PVD_PVM_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PVD_PVM_IRQHandler
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B PVD_PVM_IRQHandler
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PUBWEAK TAMP_STAMP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TAMP_STAMP_IRQHandler
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B TAMP_STAMP_IRQHandler
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PUBWEAK RTC_WKUP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RTC_WKUP_IRQHandler
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B RTC_WKUP_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI0_IRQHandler
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B EXTI0_IRQHandler
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PUBWEAK EXTI1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI1_IRQHandler
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B EXTI1_IRQHandler
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PUBWEAK EXTI2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI2_IRQHandler
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B EXTI2_IRQHandler
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PUBWEAK EXTI3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI3_IRQHandler
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B EXTI3_IRQHandler
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PUBWEAK EXTI4_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI4_IRQHandler
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B EXTI4_IRQHandler
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PUBWEAK DMA1_Channel1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel1_IRQHandler
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B DMA1_Channel1_IRQHandler
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PUBWEAK DMA1_Channel2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel2_IRQHandler
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B DMA1_Channel2_IRQHandler
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PUBWEAK DMA1_Channel3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel3_IRQHandler
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B DMA1_Channel3_IRQHandler
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PUBWEAK DMA1_Channel4_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel4_IRQHandler
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B DMA1_Channel4_IRQHandler
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PUBWEAK DMA1_Channel5_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel5_IRQHandler
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B DMA1_Channel5_IRQHandler
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PUBWEAK DMA1_Channel6_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel6_IRQHandler
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B DMA1_Channel6_IRQHandler
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PUBWEAK DMA1_Channel7_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel7_IRQHandler
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B DMA1_Channel7_IRQHandler
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PUBWEAK ADC1_2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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ADC1_2_IRQHandler
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B ADC1_2_IRQHandler
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PUBWEAK CAN1_TX_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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CAN1_TX_IRQHandler
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B CAN1_TX_IRQHandler
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PUBWEAK CAN1_RX0_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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CAN1_RX0_IRQHandler
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B CAN1_RX0_IRQHandler
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PUBWEAK CAN1_RX1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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CAN1_RX1_IRQHandler
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B CAN1_RX1_IRQHandler
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PUBWEAK CAN1_SCE_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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CAN1_SCE_IRQHandler
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B CAN1_SCE_IRQHandler
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PUBWEAK EXTI9_5_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI9_5_IRQHandler
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B EXTI9_5_IRQHandler
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PUBWEAK TIM1_BRK_TIM15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_BRK_TIM15_IRQHandler
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B TIM1_BRK_TIM15_IRQHandler
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PUBWEAK TIM1_UP_TIM16_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_UP_TIM16_IRQHandler
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B TIM1_UP_TIM16_IRQHandler
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PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_TRG_COM_TIM17_IRQHandler
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B TIM1_TRG_COM_TIM17_IRQHandler
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PUBWEAK TIM1_CC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_CC_IRQHandler
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B TIM1_CC_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK TIM3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM3_IRQHandler
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B TIM3_IRQHandler
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PUBWEAK TIM4_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM4_IRQHandler
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B TIM4_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_EV_IRQHandler
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B I2C1_EV_IRQHandler
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PUBWEAK I2C1_ER_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_ER_IRQHandler
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B I2C1_ER_IRQHandler
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PUBWEAK I2C2_EV_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C2_EV_IRQHandler
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B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT3_IRQHandler
|
||||
B DFSDM1_FLT3_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_BRK_IRQHandler
|
||||
B TIM8_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_UP_IRQHandler
|
||||
B TIM8_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
B TIM8_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK ADC3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC3_IRQHandler
|
||||
B ADC3_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC1_IRQHandler
|
||||
B SDMMC1_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_DAC_IRQHandler
|
||||
B TIM6_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT0_IRQHandler
|
||||
B DFSDM1_FLT0_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT1_IRQHandler
|
||||
B DFSDM1_FLT1_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT2_IRQHandler
|
||||
B DFSDM1_FLT2_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_IRQHandler
|
||||
B SAI2_IRQHandler
|
||||
|
||||
PUBWEAK SWPMI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SWPMI1_IRQHandler
|
||||
B SWPMI1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,96 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/* Flash Organization
|
||||
* 1. Privileged Code:
|
||||
* Start : 0x08000000
|
||||
* End : 0x08007FFF
|
||||
* Size : 32 Kbytes
|
||||
* 2. System calls:
|
||||
* Start : 0x08008000
|
||||
* End : 0x08008FFF
|
||||
* Size : 4 Kbytes
|
||||
* 3. Unprivileged Code:
|
||||
* Start : 0x08009000
|
||||
* End : 0x080FFFFF
|
||||
* Size : 988 Kbytes
|
||||
*/
|
||||
define symbol __reigon_ROM_privileged_start__ = __ICFEDIT_region_ROM_start__;
|
||||
define symbol __reigon_ROM_privileged_end__ = 0x08007FFF;
|
||||
define symbol __reigon_ROM_system_calls_start__ = 0x08008000;
|
||||
define symbol __reigon_ROM_system_calls_end__ = 0x08008FFF;
|
||||
define symbol __reigon_ROM_unprivileged_start__ = 0x08009000;
|
||||
define symbol __reigon_ROM_unprivileged_end__ = __ICFEDIT_region_ROM_end__;
|
||||
|
||||
/* RAM Organization
|
||||
* 1. Privileged Data:
|
||||
* Start : 0x20000000
|
||||
* End : 0x200003FF
|
||||
* Size : 1 Kbytes
|
||||
* 2. Unprivileged Data:
|
||||
* Start : 0x20000400
|
||||
* End : 0x20017FFF
|
||||
* Size : 95 Kbytes
|
||||
*/
|
||||
define symbol __region_RAM_privileged_start__ = __ICFEDIT_region_RAM_start__;
|
||||
define symbol __region_RAM_privileged_end__ = 0x200003FF;
|
||||
define symbol __region_RAM_unprivileged_start__ = 0x20000400;
|
||||
define symbol __region_RAM_unprivileged_end__ = __ICFEDIT_region_RAM_end__;
|
||||
define symbol __region_SRAM2_start__ = 0x10000000;
|
||||
define symbol __region_SRAM2_end__ = 0x10007FFF;
|
||||
|
||||
/* Memory regions. */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region_privileged = mem:[from __reigon_ROM_privileged_start__ to __reigon_ROM_privileged_end__];
|
||||
define region ROM_region_system_calls = mem:[from __reigon_ROM_system_calls_start__ to __reigon_ROM_system_calls_end__];
|
||||
define region ROM_region_unprivileged = mem:[from __reigon_ROM_unprivileged_start__ to __reigon_ROM_unprivileged_end__];
|
||||
define region RAM_region_privileged = mem:[from __region_RAM_privileged_start__ to __region_RAM_privileged_end__];
|
||||
define region RAM_region_unprivileged = mem:[from __region_RAM_unprivileged_start__ to __region_RAM_unprivileged_end__];
|
||||
define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
|
||||
|
||||
/* Stack and Heap. */
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* Initialization. */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
/* Exported symbols. */
|
||||
define exported symbol __FLASH_segment_start__ = __ICFEDIT_region_ROM_start__;
|
||||
define exported symbol __FLASH_segment_end__ = __ICFEDIT_region_ROM_end__;
|
||||
define exported symbol __SRAM_segment_start__ = __ICFEDIT_region_RAM_start__;
|
||||
define exported symbol __SRAM_segment_end__ = __ICFEDIT_region_RAM_end__;
|
||||
|
||||
define exported symbol __privileged_functions_start__ = __reigon_ROM_privileged_start__;
|
||||
define exported symbol __privileged_functions_end__ = __reigon_ROM_privileged_end__;
|
||||
define exported symbol __privileged_data_start__ = __region_RAM_privileged_start__;
|
||||
define exported symbol __privileged_data_end__ = __region_RAM_privileged_end__;
|
||||
|
||||
define exported symbol __syscalls_flash_start__ = __reigon_ROM_system_calls_start__;
|
||||
define exported symbol __syscalls_flash_end__ = __reigon_ROM_system_calls_end__;
|
||||
|
||||
/* Placements. */
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region_privileged { readonly section privileged_functions };
|
||||
place in ROM_region_system_calls { readonly section freertos_system_calls };
|
||||
place in ROM_region_unprivileged { readonly };
|
||||
|
||||
place in RAM_region_privileged { readwrite section privileged_data };
|
||||
place in RAM_region_unprivileged { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in SRAM2_region { };
|
||||
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.2.1
|
||||
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base;
|
||||
extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit;
|
||||
|
||||
/* Memory map needed for MPU setup. Must must match the one defined in
|
||||
* the scatter-loading file (MPUDemo.sct). */
|
||||
const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000;
|
||||
const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08100000;
|
||||
const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000;
|
||||
const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20018000;
|
||||
|
||||
const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000;
|
||||
const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000;
|
||||
const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000;
|
||||
const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20000400;
|
||||
|
||||
const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base );
|
||||
const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Mem fault handler.
|
||||
*/
|
||||
void MemManage_Handler( void ) __attribute__ (( naked ));
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void MemManage_Handler( void )
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" tst lr, #4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0, msp \n"
|
||||
" mrsne r0, psp \n"
|
||||
" ldr r1, handler_address_const \n"
|
||||
" bx r1 \n"
|
||||
" \n"
|
||||
" handler_address_const: .word vHandleMemoryFault \n"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.2.1
|
||||
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Mem fault handler.
|
||||
*/
|
||||
void MemManage_Handler( void ) __attribute__ (( naked ));
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void MemManage_Handler( void )
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" tst lr, #4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0, msp \n"
|
||||
" mrsne r0, psp \n"
|
||||
" ldr r1, handler_address_const \n"
|
||||
" bx r1 \n"
|
||||
" \n"
|
||||
" handler_address_const: .word vHandleMemoryFault \n"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
Loading…
Reference in New Issue