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Very first demo for the Energy Micro EFM32 added.

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Richard Barry 15 years ago
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commit c981185506
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784
Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.c
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/CoreSupport/core_cm3.h
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Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32.h
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/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 Gxxx Device series
*
* This is a convenience header file for defining the EFM32 part number on the
* build command line, instead of specifying the part specific header file.
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "EFM32G.h" to your source files
* @endverbatim
* @author Energy Micro AS
* @version 1.0.2
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __EFM32_H
#define __EFM32_H
#if defined(EFM32G200F16)
#include "efm32g200f16.h"
#elif defined(EFM32G200F32)
#include "efm32g200f32.h"
#elif defined(EFM32G200F64)
#include "efm32g200f64.h"
#elif defined(EFM32G210F128)
#include "efm32g210f128.h"
#elif defined(EFM32G230F128)
#include "efm32g230f128.h"
#elif defined(EFM32G230F32)
#include "efm32g230f32.h"
#elif defined(EFM32G230F64)
#include "efm32g230f64.h"
#elif defined(EFM32G280F128)
#include "efm32g280f128.h"
#elif defined(EFM32G280F32)
#include "efm32g280f32.h"
#elif defined(EFM32G280F64)
#include "efm32g280f64.h"
#elif defined(EFM32G290F128)
#include "efm32g290f128.h"
#elif defined(EFM32G290F32)
#include "efm32g290f32.h"
#elif defined(EFM32G290F64)
#include "efm32g290f64.h"
#elif defined(EFM32G840F128)
#include "efm32g840f128.h"
#elif defined(EFM32G840F32)
#include "efm32g840f32.h"
#elif defined(EFM32G840F64)
#include "efm32g840f64.h"
#elif defined(EFM32G880F128)
#include "efm32g880f128.h"
#elif defined(EFM32G880F32)
#include "efm32g880f32.h"
#elif defined(EFM32G880F64)
#include "efm32g880f64.h"
#elif defined(EFM32G890F128)
#include "efm32g890f128.h"
#elif defined(EFM32G890F32)
#include "efm32g890f32.h"
#elif defined(EFM32G890F64)
#include "efm32g890f64.h"
#else
#error "efm32.h: PART NUMBER undefined"
#endif
#endif

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Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/efm32g890f128.h
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Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c
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/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices
*
* @author Energy Micro AS
* @version 1.0.2
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#include <stdint.h>
#include "efm32.h"
uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
#ifndef EFM32_HFXO_FREQ
#define EFM32_HFXO_FREQ 32000000
#endif
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ 32768
#endif
#ifndef EFM32_LFRCO_FREQ
#define EFM32_LFRCO_FREQ 32768
#endif
/**************************************************************************//**
* @brief Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*****************************************************************************/
void SystemInit(void)
{
#if EFM32_AUXHFROCO_ENABLE
CMU_TypeDef *cmu = CMU;
/* Enable clocks to debug modules in Cortex */
/* This will enable Debug Trace and MSC Flash programming clocks */
cmu->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
#endif
}
/**************************************************************************//**
* @brief Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*****************************************************************************/
void SystemCoreClockUpdate(void)
{
CMU_TypeDef *cmu = CMU;
uint32_t inputClock;
/* Check source for core clock */
switch (cmu->STATUS &
(CMU_STATUS_HFRCOSEL |
CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL |
CMU_STATUS_LFXOSEL))
{
case CMU_STATUS_HFXOSEL:
inputClock = EFM32_HFXO_FREQ;
break;
case CMU_STATUS_LFRCOSEL:
inputClock = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_LFXOSEL:
inputClock = EFM32_LFXO_FREQ;
break;
case CMU_STATUS_HFRCOSEL:
default:
switch ((cmu->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >> _CMU_HFRCOCTRL_BAND_SHIFT)
{
case _CMU_HFRCOCTRL_BAND_28MHZ:
inputClock = 28000000;
break;
case _CMU_HFRCOCTRL_BAND_21MHZ:
inputClock = 21000000;
break;
case _CMU_HFRCOCTRL_BAND_14MHZ:
inputClock = 14000000;
break;
case _CMU_HFRCOCTRL_BAND_11MHZ:
inputClock = 11000000;
break;
case _CMU_HFRCOCTRL_BAND_7MHZ:
inputClock = 7000000;
break;
case _CMU_HFRCOCTRL_BAND_1MHZ:
inputClock = 1500000;
break;
default:
inputClock = 0;
break;
}
break;
}
/* Adjust according to clock divisor */
SystemCoreClock = inputClock / (1<<((cmu->HFCORECLKDIV & _CMU_HFCORECLKDIV_MASK)>>_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT));
}

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/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices
*
* @author Energy Micro AS
* @version 1.0.2
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __SYSTEM_EFM32_H
#define __SYSTEM_EFM32_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
/**************************************************************************//**
* @brief Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*****************************************************************************/
extern void SystemInit(void);
/**************************************************************************//**
* @brief Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*****************************************************************************/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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<html>
<head>
<title>CMSIS Changes</title>
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<body>
<h1>Changes to CMSIS version V1.20</h1>
<hr>
<h2>1. Removed CMSIS Middelware packages</h2>
<p>
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
</p>
<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h2>3. Changed startup concept</h2>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h3>Changed startup concept</h3>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h2>4. Advanced Debug Functions</h2>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h2>5. Core Register Bit Definitions</h2>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
<h2>7. DoxyGen Tags</h2>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h2>8. Folder Structure</h2>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2>9. Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
<li>
<p>
Removing core_cm3.c and core_cm0.c.
</p>
<p>
On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
appropriate compiler intrinsics.
</p>
</li>
</ul>
<h2>10. Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> for ARM toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for GNU toolchain are provided.
</li>
<li>
No <strong>C startup files</strong> for IAR toolchain are provided.
</li>
<li>
No <strong>Tasking</strong> projects are provided yet.
</li>
</ul>

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<html>
<head>
<title>CMSIS Debug Support</title>
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<body>
<h1>CMSIS Debug Support</h1>
<hr>
<h2>Cortex-M3 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<h2>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a globel variable is used. A simple mechansim detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
</p>
<pre>
extern volatile int ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<h2>ITM Debug Support in uVision</h2>
<p>
uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
display the debug data.
</p>
<p>Direction microcontroller system -&gt; uVision:</p>
<ul>
<li>
Characters received via ITM communication channel 0 are written in a printf style
to <strong>Debug (printf) Viewer</strong> window.
</li>
</ul>
<p>Direction uVision -&gt; microcontroller system:</p>
<ul>
<li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
<li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
<li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
</li>
</ul>
<h2>RTX Kernel awareness in uVision</h2>
<p>
uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
No format overhead is necessary.<br>
uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
to ITM communication channel 31.
</p>
<p>Following RTX events are traced:</p>
<ul>
<li>Task Create / Delete event
<ol>
<li>32 bit access. Task start address is transmitted</li>
<li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
High byte holds Create/Delete flag, Low byte holds TASK ID.
</li>
</ol>
</li>
<li>Task switch event
<ol>
<li>8 bit access. Task ID of current task is transmitted</li>
</ol>
</li>
</ul>
<p class="Note">Note</p>
<ul>
<li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
</li>
</ul>
<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>
<hr>
<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
All rights reserved.<br>
Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
</p>
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/*
FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd.
***************************************************************************
* *
* If you are: *
* *
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* *
* then take a look at the FreeRTOS eBook *
* *
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License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( 14000000UL )
#define configTICK_RATE_HZ ( ( portTickType ) 100 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configUSE_MUTEXES 1
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
#define configUSE_COUNTING_SEMAPHORES 0
#define configUSE_ALTERNATIVE_API 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configGENERATE_RUN_TIME_STATS 0
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */
#endif /* FREERTOS_CONFIG_H */

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/*
FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd.
***************************************************************************
* *
* If you are: *
* *
* + New to FreeRTOS, *
* + Wanting to learn FreeRTOS or multitasking in general quickly *
* + Looking for basic training, *
* + Wanting to improve your FreeRTOS skills and productivity *
* *
* then take a look at the FreeRTOS eBook *
* *
* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
* http://www.FreeRTOS.org/Documentation *
* *
* A pdf reference manual is also available. Both are usually delivered *
* to your inbox within 20 minutes to two hours when purchased between 8am *
* and 8pm GMT (although please allow up to 24 hours in case of *
* exceptional circumstances). Thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
***NOTE*** The exception to the GPL is included to allow you to distribute
a combined work that includes FreeRTOS without being obliged to provide the
source code for proprietary components outside of the FreeRTOS kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo app includes. */
#include "partest.h"
/* Library includes. */
#include "dvk.h"
void vParTestInitialise( void )
{
DVK_init();
DVK_setLEDs( 0 );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned long ulLEDs;
/* Suspend all other tasks, in order to make sure no other tasks excecutes
this code at the same time. */
vTaskSuspendAll();
{
ulLEDs = DVK_getLEDs();
if( xValue == pdTRUE )
{
/* Turn the LED on if xValue is true. */
ulLEDs = ulLEDs | ( 1 << uxLED );
}
else
{
/* Turn the LED off if xValue is not true. */
ulLEDs &= ~( 1 << uxLED );
}
DVK_setLEDs( ulLEDs );
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned long ulLEDs;
vTaskSuspendAll();
{
ulLEDs = DVK_getLEDs();
ulLEDs = ulLEDs ^ ( 1 << uxLED );
DVK_setLEDs( ulLEDs );
}
xTaskResumeAll();
}

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo.ewp</path>
</project>
<batchBuild/>
</workspace>

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/**************************************************************************//**
* @file
* @brief Chip initialization, SW workarounds for chip errata issues
* @author Energy Micro AS
* @version 1.1.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __CHIP_H
#define __CHIP_H
#include <stdint.h>
/**************************************************************************//**
* @brief Chip errata workarounds
*****************************************************************************/
static inline void CHIP_init(void)
{
uint32_t rev;
volatile uint32_t *reg;
rev = *(volatile uint32_t *)(0x0FE081FC);
/* Engineering Sample calibration setup */
if ((rev >> 24) == 0)
{
reg = (volatile uint32_t *) 0x400CA00C;
*reg &= ~(0x70UL);
/* DREG */
reg = (volatile uint32_t *) 0x400C6020;
*reg &= ~(0xE0000000UL);
*reg |= ~(7 << 25);
}
if ((rev >> 24) <= 1)
{
/* DREG */
reg = (volatile uint32_t *) 0x400C6020;
*reg &= ~(0x00001F80UL);
/* Update CMU reset values */
reg = (volatile uint32_t *) 0x400C8040;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8044;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8058;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8060;
*reg = 0;
reg = (volatile uint32_t *) 0x400C8078;
*reg = 0;
}
}
#endif

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/**************************************************************************//**
* @file
* @brief DVK board support package, initialization
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#include "efm32.h"
#include "dvk.h"
/**************************************************************************//**
* @brief Initializes DVK, configures board control access
*****************************************************************************/
void DVK_init(void)
{
#ifdef DVK_EBI_CONTROL
DVK_EBI_init();
#endif
#ifdef DVK_SPI_CONTROL
DVK_SPI_init();
#endif
/* Inform AEM application that we are in Energy Mode 0 by default */
DVK_setEnergyMode(0);
}
/**************************************************************************//**
* @brief Disables DVK, free up resources
*****************************************************************************/
void DVK_disable(void)
{
#ifdef DVK_EBI_CONTROL
/* Handover bus control */
DVK_disableBus();
/* Disable EBI interface */
DVK_EBI_disable();
#endif
#ifdef DVK_SPI_CONTROL
DVK_SPI_disable();
#endif
}

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/**************************************************************************//**
* @file
* @brief DVK Board Support, master header file
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __DVK_H
#define __DVK_H
#include <stdint.h>
#include "dvk_boardcontrol.h"
#include "dvk_bcregisters.h"
/* IF not user overrides default, try to decide DVK access interface based on
* part number */
#ifndef DVK_SPI_CONTROL
#ifndef DVK_EBI_CONTROL
#if defined(EFM32G200F16)
#define DVK_SPI_CONTROL
#elif defined(EFM32G200F32)
#define DVK_SPI_CONTROL
#elif defined(EFM32G200F64)
#define DVK_SPI_CONTROL
#elif defined(EFM32G210F128)
#define DVK_SPI_CONTROL
#elif defined(EFM32G230F128)
#define DVK_SPI_CONTROL
#elif defined(EFM32G230F32)
#define DVK_SPI_CONTROL
#elif defined(EFM32G230F64)
#define DVK_SPI_CONTROL
#elif defined(EFM32G280F128)
#define DVK_EBI_CONTROL
#elif defined(EFM32G280F32)
#define DVK_EBI_CONTROL
#elif defined(EFM32G280F64)
#define DVK_EBI_CONTROL
#elif defined(EFM32G290F128)
#define DVK_EBI_CONTROL
#elif defined(EFM32G290F32)
#define DVK_EBI_CONTROL
#elif defined(EFM32G290F64)
#define DVK_EBI_CONTROL
#elif defined(EFM32G840F128)
#define DVK_SPI_CONTROL
#elif defined(EFM32G840F32)
#define DVK_SPI_CONTROL
#elif defined(EFM32G840F64)
#define DVK_SPI_CONTROL
#elif defined(EFM32G880F128)
#define DVK_SPI_CONTROL
#elif defined(EFM32G880F32)
#define DVK_SPI_CONTROL
#elif defined(EFM32G880F64)
#define DVK_SPI_CONTROL
#elif defined(EFM32G890F128)
#define DVK_SPI_CONTROL
#elif defined(EFM32G890F32)
#define DVK_SPI_CONTROL
#elif defined(EFM32G890F64)
#define DVK_SPI_CONTROL
#else
#define DVK_SPI_CONTROL
#endif
#endif
#endif
/* EBI access */
void DVK_EBI_init(void);
void DVK_EBI_disable(void);
void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data);
uint16_t DVK_EBI_readRegister(volatile uint16_t *addr);
/* SPI access */
void DVK_SPI_init(void);
void DVK_SPI_disable(void);
void DVK_SPI_writeRegister(volatile uint16_t *addr, uint16_t data);
uint16_t DVK_SPI_readRegister(volatile uint16_t *addr);
/* Accodring to configuration, use either SPI or EBI */
#ifdef DVK_EBI_CONTROL
#define DVK_writeRegister(A, B) DVK_EBI_writeRegister(A, B)
#define DVK_readRegister(A) DVK_EBI_readRegister(A)
#endif
#ifdef DVK_SPI_CONTROL
#define DVK_writeRegister(A, B) DVK_SPI_writeRegister(A, B)
#define DVK_readRegister(A) DVK_SPI_readRegister(A)
#endif
/* General initialization routines */
void DVK_init(void);
void DVK_disable(void);
#endif

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/**************************************************************************//**
* @file
* @brief Board Control register definitions
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __DVK_BCREGISTERS_H
#define __DVK_BCREGISTERS_H
#include <stdint.h>
/**************************************************************************//**
* Defines FPGA register bank for Energy Micro Development Kit (DVK) board,
* i.e. board control registers
*****************************************************************************/
#define BC_REGISTER_BASE 0x8c000000
#define BC_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x00))
#define BC_EM ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x01))
#define BC_MAGIC ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x02))
#define BC_LED ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x03))
#define BC_PUSHBUTTON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x04))
#define BC_DIPSWITCH ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x05))
#define BC_JOYSTICK ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x06))
#define BC_AEM ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x07))
#define BC_DISPLAY_CTRL ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x08))
#define BC_EBI_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x09))
#define BC_BUS_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0a))
#define BC_PERCTRL ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0c))
#define BC_AEMSTATE ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0d))
#define BC_SPI_CFG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0e))
#define BC_RESET ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x0f))
#define BC_ADC_START ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x10))
#define BC_ADC_STATUS ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x11))
#define BC_ADC_DATA ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x12))
#define BC_HW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x14))
#define BC_FW_BUILDNO ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x15))
#define BC_FW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x16))
#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17))
#define BC_SCRATCH_EFM0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x18))
#define BC_SCRATCH_EFM1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x19))
#define BC_SCRATCH_EFM2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1A))
#define BC_SCRATCH_EFM3 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1B))
#define BC_SCRATCH_BC0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1C))
#define BC_SCRATCH_BC1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1D))
#define BC_SCRATCH_BC2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1E))
#define BC_SCRATCH_BC3 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1f))
#define BC_INTFLAG ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x20))
#define BC_INTEN ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x21))
/**************************************************************************//**
* Defines bit fields for board control registers
*****************************************************************************/
#define BC_PERCTRL_ACCEL (1 << 0)
#define BC_PERCTRL_AMBIENT (1 << 1)
#define BC_PERCTRL_POTMETER (1 << 2)
#define BC_PERCTRL_RS232A (1 << 3)
#define BC_PERCTRL_RS232B (1 << 4)
#define BC_PERCTRL_SPI (1 << 5)
#define BC_PERCTRL_I2C (1 << 6)
#define BC_PERCTRL_IRDA (1 << 7)
#define BC_PERCTRL_ANALOG_SE (1 << 8)
#define BC_PERCTRL_ANALOG_DIFF (1 << 9)
#define BC_PERCTRL_AUDIO_OUT (1 << 10)
#define BC_PERCTRL_AUDIO_IN (1 << 11)
#define BC_PERCTRL_ACCEL_GSEL (1 << 12)
#define BC_PERCTRL_ACCEL_SELFTEST (1 << 13)
#define BC_PERCTRL_RS232_SHUTDOWN (1 << 14)
#define BC_PERCTRL_IRDA_SHUTDOWN (1 << 15)
#define BC_INTEN_PB (1 << 0)
#define BC_INTEN_DIP (1 << 1)
#define BC_INTEN_JOYSTICK (1 << 2)
#define BC_INTEN_AEM (1 << 3)
#define BC_CFG_SPI (0)
#define BC_CFG_EBI (1)
#define BC_MAGIC_VALUE (0xef32)
#endif

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/**************************************************************************//**
* @file
* @brief DVK Peripheral Board Control API implementation
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#include "efm32.h"
#include "dvk.h"
#include "dvk_boardcontrol.h"
#include "dvk_bcregisters.h"
/**************************************************************************//**
* @brief Enable EFM32 access to periheral on DVK board
* @param peri Peripheral to enable
*****************************************************************************/
void DVK_enablePeripheral(DVKPeripheral peri)
{
uint16_t bit;
uint16_t tmp;
/* Calculate which bit to set */
bit = (uint16_t) peri;
/* Read peripheral control register */
tmp = DVK_readRegister(BC_PERCTRL);
/* Enable peripheral */
tmp |= bit;
/* Special case for RS232, if enabled disable shutdown */
if ((peri == DVK_RS232A) || (peri == DVK_RS232B))
{
/* clear shutdown bit */
tmp &= ~(BC_PERCTRL_RS232_SHUTDOWN);
}
/* Special case for IRDA if enabled disable shutdown */
if (peri == DVK_IRDA)
{
/* clear shutdown bit */
tmp &= ~(BC_PERCTRL_IRDA_SHUTDOWN);
}
DVK_writeRegister(BC_PERCTRL, tmp);
}
/**************************************************************************//**
* @brief Disable EFM32 access to peripheral on DVK board
* @param peri Peripheral to disable
*****************************************************************************/
void DVK_disablePeripheral(DVKPeripheral peri)
{
uint16_t bit;
uint16_t tmp;
/* Calculate which bit to set */
bit = (uint16_t) peri;
/* Read peripheral control register */
tmp = DVK_readRegister(BC_PERCTRL);
/* Disable peripheral */
tmp &= ~(bit);
/* Special case for RS232, if enabled disable shutdown */
if ((peri == DVK_RS232A) || (peri == DVK_RS232B))
{
/* Set shutdown bit */
tmp |= (BC_PERCTRL_RS232_SHUTDOWN);
}
/* Special case for IRDA */
if (peri == DVK_IRDA)
{
/* Set shutdown bit */
tmp |= (BC_PERCTRL_IRDA_SHUTDOWN);
}
DVK_writeRegister(BC_PERCTRL, tmp);
}
/**************************************************************************//**
* @brief Enable BUS access
*****************************************************************************/
void DVK_enableBus(void)
{
/* Enable bus access */
DVK_writeRegister(BC_BUS_CFG, 1);
}
/**************************************************************************//**
* @brief Disable BUS access
*****************************************************************************/
void DVK_disableBus(void)
{
DVK_writeRegister(BC_BUS_CFG, 0);
}
/**************************************************************************//**
* @brief Inform AEM about current energy mode
* @param energyMode What energy mode we are going to use next
*****************************************************************************/
void DVK_setEnergyMode(uint16_t energyMode)
{
DVK_writeRegister(BC_EM, energyMode);
}
/**************************************************************************//**
* @brief Get status of bush buttons
* @return Status of push buttons
*****************************************************************************/
uint16_t DVK_getPushButtons(void)
{
uint16_t tmp;
tmp = (~(DVK_readRegister(BC_PUSHBUTTON))) & 0x000f;
return tmp;
}
/**************************************************************************//**
* @brief Get joystick button status
* @return Joystick controller status
*****************************************************************************/
uint16_t DVK_getJoystick(void)
{
uint16_t tmp;
tmp = (~(DVK_readRegister(BC_JOYSTICK))) & 0x001f;
return tmp;
}
/**************************************************************************//**
* @brief Get dipswitch status
* The DIP switches are free for user programmable purposes
* @return Joystick controller status
*****************************************************************************/
uint16_t DVK_getDipSwitch(void)
{
uint16_t tmp;
tmp = (~(DVK_readRegister(BC_DIPSWITCH))) & 0x00ff;
return tmp;
}
/**************************************************************************//**
* @brief Sets user leds
* @param leds 16-bits which enables or disables the board "User leds"
*****************************************************************************/
void DVK_setLEDs(uint16_t leds)
{
DVK_writeRegister(BC_LED, leds);
}
/**************************************************************************//**
* @brief Get status of user LEDs
* @return Status of 16 user leds, bit 1 = on, bit 0 = off
*****************************************************************************/
uint16_t DVK_getLEDs(void)
{
return DVK_readRegister(BC_LED);
}
/**************************************************************************//**
* @brief Enable "Control" buttons/joystick/dip switch interrupts
* @param flags Board control interrupt flags, BC_INTEN_<something>
*****************************************************************************/
void DVK_enableInterrupt(uint16_t flags)
{
uint16_t tmp;
/* Add flags to interrupt enable register */
tmp = DVK_readRegister(BC_INTEN);
tmp |= flags;
DVK_writeRegister(BC_INTEN, tmp);
}
/**************************************************************************//**
* @brief Disable "Control" buttons/joystick/dip switch interrupts
* @param flags Board control interrupt flags, BC_INTEN_<something>
*****************************************************************************/
void DVK_disableInterrupt(uint16_t flags)
{
uint16_t tmp;
/* Clear flags from interrupt enable register */
tmp = DVK_readRegister(BC_INTEN);
flags = ~(flags);
tmp &= flags;
DVK_writeRegister(BC_INTEN, tmp);
}
/**************************************************************************//**
* @brief Clear interrupts
* @param flags Board control interrupt flags, BC_INTEN_<something>
*****************************************************************************/
void DVK_clearInterruptFlags(uint16_t flags)
{
DVK_writeRegister(BC_INTFLAG, flags);
}
/**************************************************************************//**
* @brief Read interrupt flags
* @return Returns currently triggered interrupts
*****************************************************************************/
uint16_t DVK_getInterruptFlags(void)
{
return DVK_readRegister(BC_INTFLAG);
}

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Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_boardcontrol.h
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/**************************************************************************//**
* @file
* @brief DVK Peripheral Board Control, prototypes and definitions
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __DVK_BOARDCONTROL_H
#define __DVK_BOARDCONTROL_H
#include <stdint.h>
#include "dvk_bcregisters.h"
/** Periperhal access switches */
typedef enum
{
DVK_ACCEL = BC_PERCTRL_ACCEL,
DVK_AMBIENT = BC_PERCTRL_AMBIENT,
DVK_POTMETER = BC_PERCTRL_POTMETER,
DVK_RS232A = BC_PERCTRL_RS232A,
DVK_RS232B = BC_PERCTRL_RS232B,
DVK_SPI = BC_PERCTRL_SPI,
DVK_I2C = BC_PERCTRL_I2C,
DVK_IRDA = BC_PERCTRL_IRDA,
DVK_ANALOG_SE = BC_PERCTRL_ANALOG_SE,
DVK_ANALOG_DIFF = BC_PERCTRL_ANALOG_DIFF,
DVK_AUDIO_OUT = BC_PERCTRL_AUDIO_OUT,
DVK_AUDIO_IN = BC_PERCTRL_AUDIO_IN,
DVK_ACCEL_GSEL = BC_PERCTRL_ACCEL_GSEL,
DVK_ACCEL_SELFTEST = BC_PERCTRL_ACCEL_SELFTEST,
DVK_RS232_SHUTDOWN = BC_PERCTRL_RS232_SHUTDOWN,
DVK_IRDA_SHUTDOWN = BC_PERCTRL_IRDA_SHUTDOWN,
} DVKPeripheral;
/* Peripheral Control */
void DVK_enablePeripheral(DVKPeripheral peri);
void DVK_disablePeripheral(DVKPeripheral peri);
void DVK_enableBus(void);
void DVK_disableBus(void);
/* Read board controllers */
uint16_t DVK_getPushButtons(void);
uint16_t DVK_getJoystick(void);
uint16_t DVK_getDipSwitch(void);
/* Report AEM status */
void DVK_setEnergyMode(uint16_t energyMode);
/* User LEDs */
void DVK_setLEDs(uint16_t leds);
uint16_t DVK_getLEDs(void);
/* Interrupt callback */
void DVK_enableInterrupt(uint16_t flags);
void DVK_disableInterrupt(uint16_t flags);
uint16_t DVK_getInterruptFlags(void);
void DVK_clearInterruptFlags(uint16_t flags);
#endif

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/**************************************************************************//**
* @file
* @brief EBI implementation of Board Control interface
* This implementation works for devices w/o LCD display on the
* MCU module, specifically the EFM32_G2xx_DK development board
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#include "efm32.h"
#include "dvk.h"
#include "dvk_bcregisters.h"
/**************************************************************************//**
* @brief Configure EBI (external bus interface) for Board Control register
* access
*****************************************************************************/
void DVK_EBI_configure(void)
{
GPIO_TypeDef *gpio = GPIO;
EBI_TypeDef *ebi = EBI;
CMU_TypeDef *cmu = CMU;
/* Run time check if we have EBI on-chip capability on this device */
switch ((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) >>
_DEVINFO_PART_DEVICE_NUMBER_SHIFT)
{
/* Only device types EFM32G 280/290/880 and 890 have EBI capability */
case 280:
case 290:
case 880:
case 890:
break;
default:
/* This device do not have EBI capability - use SPI to interface DVK */
/* With high probability your project has been configured for an */
/* incorrect part number. */
while (1) ;
}
/* Enable clocks */
cmu->HFCORECLKEN0 |= CMU_HFCORECLKEN0_EBI;
cmu->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
/* Configure bus connect PC bit 12 active low */
gpio->P[2].MODEH |=
GPIO_P_MODEH_MODE12_PUSHPULL;
gpio->P[2].DOUT &= ~(1UL << 12);
/* Configure GPIO pins as push pull */
/* EBI AD9..15 */
gpio->P[0].MODEL |=
(GPIO_P_MODEL_MODE0_PUSHPULL |
GPIO_P_MODEL_MODE1_PUSHPULL |
GPIO_P_MODEL_MODE2_PUSHPULL |
GPIO_P_MODEL_MODE3_PUSHPULL |
GPIO_P_MODEL_MODE4_PUSHPULL |
GPIO_P_MODEL_MODE5_PUSHPULL |
GPIO_P_MODEL_MODE6_PUSHPULL);
/* EBI AD8 */
gpio->P[0].MODEH |=
GPIO_P_MODEH_MODE15_PUSHPULL;
/* EBI CS0-CS3 */
gpio->P[3].MODEH |=
(GPIO_P_MODEH_MODE9_PUSHPULL |
GPIO_P_MODEH_MODE10_PUSHPULL |
GPIO_P_MODEH_MODE11_PUSHPULL |
GPIO_P_MODEH_MODE12_PUSHPULL);
/* EBI AD0..7 */
gpio->P[4].MODEH |=
(GPIO_P_MODEH_MODE8_PUSHPULL |
GPIO_P_MODEH_MODE9_PUSHPULL |
GPIO_P_MODEH_MODE10_PUSHPULL |
GPIO_P_MODEH_MODE11_PUSHPULL |
GPIO_P_MODEH_MODE12_PUSHPULL |
GPIO_P_MODEH_MODE13_PUSHPULL |
GPIO_P_MODEH_MODE14_PUSHPULL |
GPIO_P_MODEH_MODE15_PUSHPULL);
/* EBI ARDY/ALEN/Wen/Ren */
gpio->P[5].MODEL |=
(GPIO_P_MODEL_MODE2_PUSHPULL |
GPIO_P_MODEL_MODE3_PUSHPULL |
GPIO_P_MODEL_MODE4_PUSHPULL |
GPIO_P_MODEL_MODE5_PUSHPULL);
/* Configure EBI controller */
/* 16 bit address, 16 bit data mode */
/* Enable bank 0 address map 0x80000000, FPGA Flash */
/* Enable bank 1 address map 0x84000000, FPGA SRAM */
/* Enable bank 2 address map 0x88000000, FPGA TFT Display (SSD2119) */
/* Enable bank 3 address map 0x8c000000, FPGA Board Control Registers */
ebi->CTRL =
EBI_CTRL_MODE_D16A16ALE |
EBI_CTRL_BANK0EN |
EBI_CTRL_BANK1EN |
EBI_CTRL_BANK2EN |
EBI_CTRL_BANK3EN;
/* Setup and hold time */
ebi->ADDRTIMING = 3 << _EBI_ADDRTIMING_ADDRHOLD_SHIFT | 3 << _EBI_ADDRTIMING_ADDRSET_SHIFT;
/* Default values for all write timing registers, read timing conservative */
ebi->RDTIMING = 7 << _EBI_RDTIMING_RDSTRB_SHIFT | 3 << _EBI_RDTIMING_RDHOLD_SHIFT | 3 << _EBI_RDTIMING_RDSETUP_SHIFT;
ebi->WRTIMING = 7 << _EBI_WRTIMING_WRSTRB_SHIFT | 3 << _EBI_WRTIMING_WRHOLD_SHIFT | 3 << _EBI_WRTIMING_WRSETUP_SHIFT;
ebi->POLARITY = _EBI_POLARITY_RESETVALUE;
/* Toggle on all chip selects for all banks */
ebi->ROUTE =
EBI_ROUTE_CS0PEN |
EBI_ROUTE_CS1PEN |
EBI_ROUTE_CS2PEN |
EBI_ROUTE_CS3PEN |
EBI_ROUTE_ALEPEN |
EBI_ROUTE_EBIPEN;
}
/**************************************************************************//**
* @brief Initialize EBI
* access
*****************************************************************************/
void DVK_EBI_init(void)
{
uint16_t ebiMagic;
int ctr;
volatile int i;
/* Configure EBI */
DVK_EBI_configure();
/* Verify that EBI access is working, if not kit is in SPI mode and needs to
* be configured for EBI access */
ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
if (ebiMagic != BC_MAGIC_VALUE)
{
/* Disable EBI */
DVK_EBI_disable();
/* Enable SPI interface */
DVK_SPI_init();
/* Set EBI mode - after this SPI access will no longer be available */
DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI);
/* Disable SPI */
DVK_SPI_disable();
/* Now setup EBI again */
DVK_EBI_configure();
/* Wait until ready */
ctr = 0;
do {
/* Check if FPGA responds */
ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
ctr++;
DVK_EBI_writeRegister(BC_LED, ctr);
} while (ebiMagic != BC_MAGIC_VALUE);
}
}
/**************************************************************************//**
* @brief Disable EBI interface, free all GPIO pins
*****************************************************************************/
void DVK_EBI_disable(void)
{
GPIO_TypeDef *gpio = GPIO;
EBI_TypeDef *ebi = EBI;
CMU_TypeDef *cmu = CMU;
/* Toggle off all chip selects for all banks */
ebi->ROUTE = _EBI_ROUTE_RESETVALUE;
/* Disable EBI controller */
ebi->CTRL = _EBI_CTRL_RESETVALUE;
/* Disable EBI clock */
cmu->HFCORECLKEN0 &= ~(CMU_HFCORECLKEN0_EBI);
/* Disable EBI _BC_BUS_CONNECT */
gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE12_MASK);
/* Configure GPIO pins as disabled */
gpio->P[0].MODEL &= ~(
_GPIO_P_MODEL_MODE0_MASK |
_GPIO_P_MODEL_MODE1_MASK |
_GPIO_P_MODEL_MODE2_MASK |
_GPIO_P_MODEL_MODE3_MASK |
_GPIO_P_MODEL_MODE4_MASK |
_GPIO_P_MODEL_MODE5_MASK |
_GPIO_P_MODEL_MODE6_MASK);
gpio->P[0].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
gpio->P[3].MODEH &= ~(
_GPIO_P_MODEH_MODE9_MASK|
_GPIO_P_MODEH_MODE10_MASK|
_GPIO_P_MODEH_MODE11_MASK|
_GPIO_P_MODEH_MODE12_MASK
);
gpio->P[4].MODEH &= ~(
_GPIO_P_MODEH_MODE8_MASK |
_GPIO_P_MODEH_MODE9_MASK |
_GPIO_P_MODEH_MODE10_MASK |
_GPIO_P_MODEH_MODE11_MASK |
_GPIO_P_MODEH_MODE12_MASK |
_GPIO_P_MODEH_MODE13_MASK |
_GPIO_P_MODEH_MODE14_MASK |
_GPIO_P_MODEH_MODE15_MASK);
gpio->P[5].MODEL &= ~(
_GPIO_P_MODEL_MODE2_MASK |
_GPIO_P_MODEL_MODE3_MASK |
_GPIO_P_MODEL_MODE4_MASK |
_GPIO_P_MODEL_MODE5_MASK);
}
/**************************************************************************//**
* @brief Write data into 16-bit board control register
* @param addr Address to board control register
* @param data Data to write into register
*****************************************************************************/
void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data)
{
*addr = data;
}
/**************************************************************************//**
* @brief Write data into 16-bit board control register
* @param addr Register to read from
*****************************************************************************/
uint16_t DVK_EBI_readRegister(volatile uint16_t *addr)
{
return *addr;
}

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Demo/CORTEX_EFMG890F128_IAR/bsp/dvk_spi.c
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/**************************************************************************//**
* @file
* @brief SPI implementation of Board Control interface
* This implementation use the USART2 SPI interface to control board
* control registers. It works
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#include "efm32.h"
#include "dvk.h"
#include "dvk_bcregisters.h"
#define clear_bit(reg, bit) (reg &= ~(1 << bit))
static volatile uint16_t *lastAddr = 0;
/**************************************************************************//**
* @brief Initializes USART2 SPI interface for access to FPGA registers
* for board control
*****************************************************************************/
static void spiInit(void)
{
USART_TypeDef *usart = USART2;
GPIO_TypeDef *gpio = GPIO;
uint32_t clk, spidiv;
const uint32_t baudrate = 7000000;
const uint32_t div = (2 * baudrate / 256);
/* Configure SPI bus connect pins */
gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE13_MASK);
gpio->P[2].MODEH |= (GPIO_P_MODEH_MODE13_PUSHPULL);
gpio->P[2].DOUT &= ~(1UL << 13);
/* Configure SPI pins */
gpio->P[2].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK |
_GPIO_P_MODEL_MODE3_MASK |
_GPIO_P_MODEL_MODE4_MASK |
_GPIO_P_MODEL_MODE5_MASK);
gpio->P[2].MODEL |= (GPIO_P_MODEL_MODE2_PUSHPULL |
GPIO_P_MODEL_MODE3_PUSHPULL |
GPIO_P_MODEL_MODE4_PUSHPULL |
GPIO_P_MODEL_MODE5_PUSHPULL);
gpio->P[2].DOUT |= (1UL << 5);
/* Configure USART2 as SPI master with manual CS */
/* Get peripheral clock - ensure updated SystemCoreClock */
SystemCoreClockUpdate();
clk = (SystemCoreClock >> ((CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>
_CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT));
/* Drive spi at max 7Mhz or half clockrate if core freq < 14Mhz */
if (clk < 14000000)
{
spidiv = 0;
}
else
{
spidiv = (clk) / (div) - 256;
}
/* Never allow higher frequency than specified, round up 1/4 div */
if (spidiv & 0x3f) spidiv += 0x40;
usart->CLKDIV = spidiv;
usart->CTRL = USART_CTRL_SYNC;
usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX;
usart->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN;
usart->CMD = USART_CMD_MASTEREN | USART_CMD_TXEN | USART_CMD_RXEN;
}
/**************************************************************************//**
* @brief Disables GPIO pins and USART2 from FPGA register access
*****************************************************************************/
static void spiDisable(void)
{
USART_TypeDef *usart = USART2;
GPIO_TypeDef *gpio = GPIO;
/* Disable USART2 */
usart->CTRL = _USART_CTRL_RESETVALUE;
usart->ROUTE = _USART_ROUTE_RESETVALUE;
usart->CMD = USART_CMD_MASTERDIS | USART_CMD_TXDIS | USART_CMD_RXDIS;
/* Disable SPI pins */
gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE13_MASK);
gpio->P[2].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK |
_GPIO_P_MODEL_MODE3_MASK |
_GPIO_P_MODEL_MODE4_MASK |
_GPIO_P_MODEL_MODE5_MASK);
}
/**************************************************************************//**
* @brief Performs USART2 SPI Transfer
*****************************************************************************/
static uint16_t spiAccess(uint8_t spiadr, uint8_t rw, uint16_t spidata)
{
USART_TypeDef *usart = USART2;
GPIO_TypeDef *gpio = GPIO;
uint16_t tmp;
clear_bit(gpio->P[2].DOUT, 5);
/* SPI address */
usart->TXDATA = (spiadr & 0x3) | rw << 3;
while (!(usart->STATUS & USART_STATUS_TXC)) ;
tmp = (usart->RXDATA) << 0;
/* SPI data LSB */
usart->TXDATA = spidata & 0xFF;
while (!(usart->STATUS & USART_STATUS_TXC)) ;
tmp = (usart->RXDATA);
/* SPI data MSB */
usart->TXDATA = spidata >> 8;
while (!(usart->STATUS & USART_STATUS_TXC)) ;
tmp |= (usart->RXDATA) << 8;
gpio->P[2].DOUT |= (1 << 5);
return tmp;
}
/**************************************************************************//**
* @brief Performs USART2 SPI write to FPGA register
* @param spiadr Address of register
* @param spidata Data to write
*****************************************************************************/
static void spiWrite(uint8_t spiadr, uint16_t spidata)
{
spiAccess(spiadr, 0, spidata);
}
/**************************************************************************//**
* @brief Performs USART2 SPI read from FPGA register
* @param spiadr Address of register
* @param spidata Dummy data
*****************************************************************************/
static uint16_t spiRead(uint8_t spiadr, uint16_t spidata)
{
return spiAccess(spiadr, 1, spidata);
}
/**************************************************************************//**
* @brief Initializes DVK register access
*****************************************************************************/
void DVK_SPI_init(void)
{
uint16_t spiMagic;
spiInit();
/* Read "board control Magic" register to verify SPI is up and running */
/* if not FPGA is configured to be in EBI mode */
spiMagic = DVK_SPI_readRegister(BC_MAGIC);
if (spiMagic != BC_MAGIC_VALUE)
{
/* Development Kit is configured to use EBI mode, restart of kit required */
/* to use USART2-SPI for configuration */
spiDisable();
while (1) ;
}
}
/**************************************************************************//**
* @brief Disable and free up resources used by SPI board control access
*****************************************************************************/
void DVK_SPI_disable(void)
{
spiDisable();
}
/**************************************************************************//**
* @brief Perform read from DVK board control register
* @param addr Address of register to read from
*****************************************************************************/
uint16_t DVK_SPI_readRegister(volatile uint16_t *addr)
{
uint16_t data;
if (addr != lastAddr)
{
spiWrite(0x00, 0xFFFF & ((uint32_t) addr)); /*LSBs of address*/
spiWrite(0x01, 0xFF & ((uint32_t) addr >> 16)); /*MSBs of address*/
spiWrite(0x02, (0x0C000000 & (uint32_t) addr) >> 26); /*Chip select*/
}
/* Read twice */
data = spiRead(0x03, 0);
data = spiRead(0x03, 0);
lastAddr = addr;
return data;
}
/**************************************************************************//**
* @brief Perform write to DVK board control register
* @param addr Address of register to write to
* @param data 16-bit to write into register
*****************************************************************************/
void DVK_SPI_writeRegister(volatile uint16_t *addr, uint16_t data)
{
if (addr != lastAddr)
{
spiWrite(0x00, 0xFFFF & ((uint32_t) addr)); /*LSBs of address*/
spiWrite(0x01, 0xFF & ((uint32_t) addr >> 16)); /*MSBs of address*/
spiWrite(0x02, (0x0C000000 & (uint32_t) addr) >> 26); /*Chip select*/
}
spiWrite(0x03, data); /*Data*/
lastAddr = addr;
}

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Demo/CORTEX_EFMG890F128_IAR/cspycomm.log
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Logging started @ 2010-03-13 15:06
DLL Compiled: Jan 25 2010 14:43:57
Firmware: Energy Micro EFM32 compiled Nov 17 2009 17:38:20
Hardware: V7.00 returns O.K. (0190ms, 0001ms total)
T0134 000:214 JLINKARM_GetDLLVersion() returns 41009 (0000ms, 0191ms total)
T0134 000:214 JLINKARM_GetCompileDateTime() (0000ms, 0191ms total)
T0134 000:214 JLINKARM_GetFirmwareString(...) (0000ms, 0191ms total)
T0134 000:215 JLINKARM_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0000ms, 0191ms total)
T0134 000:215 JLINKARM_SelectDeviceFamily(3) (0000ms, 0191ms total)
T0134 000:215 JLINKARM_SetSpeed(32) (0001ms, 0191ms total)
T0134 000:216 JLINKARM_SetResetDelay(0) (0000ms, 0192ms total)
T0134 000:216 JLINKARM_ResetPullsRESET(ON) (0000ms, 0192ms total)
T0134 000:216 JLINKARM_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x66 TIF> >0x66 TIF> >0x35 TIF> >0x16D TIF> >0xD0 TIF> >0x16D TIF> >0xD0 TIF>TPIU fitted. >0xD0 TIF> >0xD0 TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0xD0 TIF> (0438ms, 0192ms total)
T0134 000:654 JLINKARM_Halt() returns 0x00 (0012ms, 0630ms total)
T0134 000:669 JLINKARM_IsHalted() returns TRUE (0013ms, 0643ms total)
T0134 000:682 JLINKARM_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) -- Data: 30 C2 2F 41 returns 0x01 (0014ms, 0643ms total)
T0134 000:696 JLINKARM_GetEmuCaps() returns 0x8AEA5833 (0000ms, 0657ms total)
T0134 000:696 JLINKARM_GetEmuCaps() returns 0x8AEA5833 (0000ms, 0657ms total)
T0134 000:700 JLINKARM_SWO_Control(JLINKARM_SWO_CMD_GET_SPEED_INFO, ...) returns 0x00 (0003ms, 0657ms total)
T0134 000:739 JLINKARM_GetSpeed() returns 0x20 (0000ms, 0660ms total)
T0134 000:739 JLINKARM_SetMaxSpeed() (0001ms, 0660ms total)
T0134 000:767 JLINKARM_BeginDownload(Flags = 0x03) (0000ms, 0661ms total)
T0134 000:879 JLINKARM_WriteMem(0x20000000, 0x0008 Bytes, ...) -- Data: 00 20 00 20 55 02 00 20 -- CPU_WriteMem(8 bytes @ 0x20000000) returns 0x08 (0001ms, 0661ms total)
T0134 000:880 JLINKARM_WriteMem(0x20000080, 0x0280 Bytes, ...) -- Data: D9 02 00 20 04 00 00 00 7C 1E 00 20 00 00 00 00 ... -- CPU_WriteMem(640 bytes @ 0x20000080) returns 0x280 (0009ms, 0662ms total)
T0134 000:893 JLINKARM_EndDownload() (0000ms, 0671ms total)
T0134 001:251 JLINKARM_ReadMemU32(0x20000000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x20000000) -- Data: 00 20 00 20 returns 0x01 (0002ms, 0671ms total)
T0134 001:253 JLINKARM_ReadMemU32(0x20000004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x20000004) -- Data: 55 02 00 20 returns 0x01 (0002ms, 0673ms total)
T0134 001:255 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 0675ms total)
T0134 001:255 JLINKARM_WriteReg(R15, 0x20000254) returns 0x00 (0000ms, 0675ms total)
T0134 001:255 JLINKARM_ReadReg(MSP) returns 0x20000400 (0000ms, 0675ms total)
T0134 001:255 JLINKARM_ReadReg(PSP) returns 0x00000000 (0000ms, 0675ms total)
T0134 001:255 JLINKARM_ReadReg(CFBP) returns 0x00000000 (0000ms, 0675ms total)
T0134 001:255 JLINKARM_WriteReg(MSP, 0x20002000) returns 0x00 (0000ms, 0675ms total)
T0134 001:255 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 00 returns 0x01 (0003ms, 0675ms total)
T0134 001:258 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0678ms total)
T0134 001:260 JLINKARM_ReadReg(R15) returns 0x20000254 (0000ms, 0679ms total)
T0134 001:260 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x05 (0002ms, 0679ms total)
T0134 001:307 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000250) -- Data: FE E7 returns 0x01 (0002ms, 0681ms total)
T0134 001:309 JLINKARM_SetBPEx(Addr = 0x20000250, Type = 0xFFFFFFF2) -- CPU_ReadMem(4 bytes @ 0x20000250) -- CPU_WriteMem(4 bytes @ 0x20000250) -- CPU_ReadMem(4 bytes @ 0x20000250) -- CPU_WriteMem(4 bytes @ 0x20000250) -- CPU_ReadMem(2 bytes @ 0x20000250) returns 0x00000001 (0009ms, 0683ms total)
T0134 001:318 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 0692ms total)
T0134 001:325 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0699ms total)
T0134 001:325 JLINKARM_WriteMem(0x20001E24, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(2 bytes @ 0x20000250) -- CPU_WriteMem(4 bytes @ 0x20001E24) returns 0x04 (0001ms, 0699ms total)
T0134 001:326 JLINKARM_EndDownload() (0000ms, 0700ms total)
T0134 001:326 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0700ms total)
T0134 001:326 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0001ms, 0700ms total)
T0134 001:327 JLINKARM_EndDownload() (0000ms, 0701ms total)
T0A20 001:328 JLINKARM_ReadReg(R15) returns 0x20000254 (0000ms, 0701ms total)
T0A20 001:328 JLINKARM_ReadMemU16(0x20000254, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000254) -- Data: FF F7 returns 0x01 (0003ms, 0701ms total)
T0A20 001:331 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 0704ms total)
T0A20 001:338 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0711ms total)
T0A20 001:340 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0713ms total)
T0A20 001:341 JLINKARM_ReadMemU32(0xE0002000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0002000) -- Data: 60 02 00 00 returns 0x01 (0002ms, 0714ms total)
T0A20 001:343 JLINKARM_ReadMemU32(0xE0002000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0002000) -- Data: 60 02 00 00 returns 0x01 (0002ms, 0716ms total)
T0A20 001:345 JLINKARM_ReadMemU32(0xE0001000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- Data: 00 00 00 40 returns 0x01 (0002ms, 0718ms total)
T0A20 001:347 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0720ms total)
T0A20 001:349 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0722ms total)
T0A20 001:350 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0723ms total)
T0A20 001:351 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0724ms total)
T0A20 001:352 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0725ms total)
T0A20 001:353 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0726ms total)
T0A20 001:354 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0010ms, 0727ms total)
T0A20 001:366 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0009ms, 0737ms total)
T0A20 001:375 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0737ms total)
T0A20 001:377 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0739ms total)
T0A20 001:378 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0740ms total)
T0A20 001:384 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0746ms total)
T0A20 001:385 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0747ms total)
T0A20 001:386 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0748ms total)
T0A20 001:387 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0749ms total)
T0A20 001:388 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0750ms total)
T0A20 001:388 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0750ms total)
T0A20 001:388 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0750ms total)
T0A20 001:391 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0752ms total)
T0A20 001:391 JLINKARM_WriteMem(0x20000300, 0x0068 Bytes, ...) -- Data: 00 00 00 00 00 02 00 00 00 02 00 00 00 02 00 00 ... -- CPU_WriteMem(104 bytes @ 0x20000300) returns 0x68 (0002ms, 0752ms total)
T0A20 001:393 JLINKARM_EndDownload() (0000ms, 0754ms total)
T0A20 001:394 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0754ms total)
T0A20 001:394 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 0D 00 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0001ms, 0754ms total)
T0A20 001:395 JLINKARM_EndDownload() (0000ms, 0755ms total)
T0A20 001:395 JLINKARM_WriteReg(R15, 0x20000264) returns 0x00 (0000ms, 0755ms total)
T0A20 001:396 JLINKARM_ReadReg(R15) returns 0x20000264 (0000ms, 0756ms total)
T0A20 001:396 JLINKARM_ReadMemU16(0x20000264, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000264) -- Data: FF F7 returns 0x01 (0003ms, 0756ms total)
T0A20 001:399 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0759ms total)
T0A20 001:405 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0765ms total)
T0A20 001:407 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0767ms total)
T0A20 001:408 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0768ms total)
T0A20 001:409 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0000ms, 0769ms total)
T0A20 001:409 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0769ms total)
T0A20 001:410 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0770ms total)
T0A20 001:411 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0010ms, 0771ms total)
T0A20 001:423 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:425 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:427 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:429 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:431 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:433 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:435 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:437 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:439 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:442 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:445 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:448 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:450 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:453 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:456 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:459 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:462 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:465 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:467 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:469 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:471 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:473 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:475 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:477 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:479 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:481 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:484 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:487 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:490 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:492 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:495 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:498 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:501 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:504 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:507 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:509 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:511 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:513 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:515 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:517 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:519 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:521 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:523 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:526 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:529 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:532 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:534 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:537 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:540 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:543 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:546 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:549 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:551 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:553 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:555 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:557 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:559 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:561 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:563 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:565 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:568 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:571 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:574 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:576 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:579 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:582 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:585 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:587 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:590 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:593 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:595 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:597 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:599 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:601 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:603 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:605 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:607 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:610 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:613 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:616 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:618 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:621 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:624 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:627 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:630 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:633 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:635 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:637 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:639 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:641 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:643 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:645 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:647 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:650 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:653 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:656 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:659 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:661 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:664 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:667 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:670 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:673 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:675 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:677 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:679 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:681 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:683 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:685 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:687 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:689 JLINKARM_IsHalted() returns FALSE (0000ms, 0781ms total)
T0A20 001:692 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:695 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:698 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:700 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:703 JLINKARM_IsHalted() returns FALSE (0001ms, 0781ms total)
T0A20 001:706 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 0781ms total)
T0A20 001:716 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0781ms total)
T0A20 001:718 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0783ms total)
T0A20 001:719 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 0784ms total)
T0A20 001:726 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0791ms total)
T0A20 001:727 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0792ms total)
T0A20 001:728 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0793ms total)
T0A20 001:729 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0794ms total)
T0A20 001:731 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0795ms total)
T0A20 001:731 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0795ms total)
T0A20 001:731 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0795ms total)
T0A20 001:733 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0797ms total)
T0A20 001:733 JLINKARM_WriteMem(0x20000300, 0x1A00 Bytes, ...) -- Data: 00 04 00 20 09 1D 00 00 CB 1D 00 00 CF 1D 00 00 ... -- CPU_WriteMem(6656 bytes @ 0x20000300) returns 0x1A00 (0080ms, 0797ms total)
T0A20 001:814 JLINKARM_EndDownload() (0000ms, 0878ms total)
T0A20 001:814 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0878ms total)
T0A20 001:814 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 00 1A 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0002ms, 0878ms total)
T0A20 001:816 JLINKARM_EndDownload() (0000ms, 0880ms total)
T0A20 001:816 JLINKARM_WriteReg(R15, 0x2000025C) returns 0x00 (0000ms, 0880ms total)
T0A20 001:816 JLINKARM_ReadReg(R15) returns 0x2000025C (0000ms, 0880ms total)
T0A20 001:816 JLINKARM_ReadMemU16(0x2000025C, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x2000025C) -- Data: FF F7 returns 0x01 (0003ms, 0880ms total)
T0A20 001:819 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0883ms total)
T0A20 001:825 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0001ms, 0889ms total)
T0A20 001:826 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0890ms total)
T0A20 001:827 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0891ms total)
T0A20 001:828 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0892ms total)
T0A20 001:829 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0893ms total)
T0A20 001:830 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0894ms total)
T0A20 001:831 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0008ms, 0895ms total)
T0A20 001:841 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:843 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:845 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:847 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:849 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:851 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:853 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:855 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:858 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:861 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:864 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:867 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:869 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:872 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:875 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:878 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:881 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:883 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:885 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:887 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:889 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:891 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:893 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:895 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:897 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:900 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:903 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:906 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:909 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:911 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:914 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:917 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:920 JLINKARM_IsHalted() returns FALSE (0001ms, 0903ms total)
T0A20 001:923 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:925 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:927 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:929 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:931 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:933 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:935 JLINKARM_IsHalted() returns FALSE (0000ms, 0903ms total)
T0A20 001:937 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 0903ms total)
T0A20 001:947 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0903ms total)
T0A20 001:949 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0905ms total)
T0A20 001:950 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0906ms total)
T0A20 001:956 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0912ms total)
T0A20 001:957 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0913ms total)
T0A20 001:958 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0914ms total)
T0A20 001:959 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0915ms total)
T0A20 001:960 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0916ms total)
T0A20 001:960 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0916ms total)
T0A20 001:960 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0916ms total)
T0A20 001:962 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0918ms total)
T0A20 001:962 JLINKARM_WriteMem(0x20000300, 0x0028 Bytes, ...) -- Data: 00 1A 00 00 00 02 00 00 00 1C 00 00 00 02 00 00 ... -- CPU_WriteMem(40 bytes @ 0x20000300) returns 0x28 (0001ms, 0918ms total)
T0A20 001:963 JLINKARM_EndDownload() (0000ms, 0919ms total)
T0A20 001:963 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0919ms total)
T0A20 001:963 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 00 00 00 05 00 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0002ms, 0919ms total)
T0A20 001:965 JLINKARM_EndDownload() (0000ms, 0921ms total)
T0A20 001:965 JLINKARM_WriteReg(R15, 0x20000264) returns 0x00 (0000ms, 0921ms total)
T0A20 001:965 JLINKARM_ReadReg(R15) returns 0x20000264 (0000ms, 0921ms total)
T0A20 001:965 JLINKARM_ReadMemU16(0x20000264, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x20000264) -- Data: FF F7 returns 0x01 (0003ms, 0921ms total)
T0A20 001:968 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0924ms total)
T0A20 001:974 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0930ms total)
T0A20 001:976 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0932ms total)
T0A20 001:977 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0933ms total)
T0A20 001:978 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0934ms total)
T0A20 001:979 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0935ms total)
T0A20 001:981 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0937ms total)
T0A20 001:982 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0008ms, 0938ms total)
T0A20 001:992 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 001:994 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total)
T0A20 001:997 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total)
T0A20 002:000 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total)
T0A20 002:003 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:005 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:007 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:009 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:011 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:013 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:015 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:017 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:019 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:021 JLINKARM_IsHalted() returns FALSE (0000ms, 0946ms total)
T0A20 002:023 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total)
T0A20 002:027 JLINKARM_IsHalted() returns FALSE (0001ms, 0946ms total)
T0A20 002:030 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:033 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:035 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:038 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:041 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:044 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:047 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:049 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:051 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:055 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:057 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:059 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:061 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:063 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:066 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:069 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:072 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:075 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:077 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:080 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:083 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:085 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:088 JLINKARM_IsHalted() returns FALSE (0001ms, 0947ms total)
T0A20 002:091 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:093 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:095 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:097 JLINKARM_IsHalted() returns FALSE (0000ms, 0947ms total)
T0A20 002:099 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 0947ms total)
T0A20 002:109 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 0947ms total)
T0A20 002:111 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 0949ms total)
T0A20 002:112 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 0950ms total)
T0A20 002:118 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 0956ms total)
T0A20 002:119 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 0957ms total)
T0A20 002:120 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 0958ms total)
T0A20 002:121 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 0959ms total)
T0A20 002:122 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 0960ms total)
T0A20 002:122 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 0960ms total)
T0A20 002:122 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0002ms, 0960ms total)
T0A20 002:124 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0962ms total)
T0A20 002:124 JLINKARM_WriteMem(0x20000300, 0x0928 Bytes, ...) -- Data: 01 3B 52 1E 00 F8 01 3B 03 B1 F8 D1 11 00 1C BF ... -- CPU_WriteMem(2344 bytes @ 0x20000300) returns 0x928 (0030ms, 0962ms total)
T0A20 002:154 JLINKARM_EndDownload() (0000ms, 0992ms total)
T0A20 002:154 JLINKARM_BeginDownload(Flags = 0x01) (0000ms, 0992ms total)
T0A20 002:154 JLINKARM_WriteMem(0x20001E10, 0x0014 Bytes, ...) -- Data: 00 1A 00 00 28 09 00 00 00 00 00 00 00 03 00 20 ... -- CPU_WriteMem(20 bytes @ 0x20001E10) returns 0x14 (0001ms, 0992ms total)
T0A20 002:155 JLINKARM_EndDownload() (0000ms, 0993ms total)
T0A20 002:155 JLINKARM_WriteReg(R15, 0x2000025C) returns 0x00 (0000ms, 0993ms total)
T0A20 002:155 JLINKARM_ReadReg(R15) returns 0x2000025C (0000ms, 0993ms total)
T0A20 002:155 JLINKARM_ReadMemU16(0x2000025C, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x2000025C) -- Data: FF F7 returns 0x01 (0002ms, 0993ms total)
T0A20 002:157 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0005ms, 0995ms total)
T0A20 002:162 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 1000ms total)
T0A20 002:164 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1002ms total)
T0A20 002:165 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 1003ms total)
T0A20 002:166 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 1004ms total)
T0A20 002:167 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 1005ms total)
T0A20 002:168 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 1006ms total)
T0A20 002:169 JLINKARM_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0009ms, 1007ms total)
T0A20 002:180 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:183 JLINKARM_IsHalted() returns FALSE (0000ms, 1016ms total)
T0A20 002:185 JLINKARM_IsHalted() returns FALSE (0000ms, 1016ms total)
T0A20 002:187 JLINKARM_IsHalted() returns FALSE (0000ms, 1016ms total)
T0A20 002:189 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:192 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:195 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:198 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:200 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:203 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:206 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:209 JLINKARM_IsHalted() returns FALSE (0001ms, 1016ms total)
T0A20 002:212 JLINKARM_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000250) returns TRUE (0010ms, 1016ms total)
T0A20 002:222 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 1016ms total)
T0A20 002:224 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1018ms total)
T0A20 002:225 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0008ms, 1019ms total)
T0A20 002:233 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 1027ms total)
T0A20 002:234 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 1028ms total)
T0A20 002:235 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 1029ms total)
T0A20 002:236 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0002ms, 1030ms total)
T0A20 002:238 JLINKARM_ReadReg(R15) returns 0x20000250 (0000ms, 1032ms total)
T0A20 002:238 JLINKARM_ReadMemU16(0x20000250, 0x0001 Items, ...) -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Merging existing BP[0]: 0xE7FE @ 0x20000250 -- Data: FE E7 returns 0x01 (0000ms, 1032ms total)
T0A20 002:238 JLINKARM_ReadMemU32(0x20001E10, 0x0005 Items, ...) -- CPU_ReadMem(20 bytes @ 0x20001E10) -- Data: 00 1A 00 00 00 00 00 00 00 00 00 00 00 03 00 20 ... returns 0x05 (0003ms, 1032ms total)
T0134 002:243 JLINKARM_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 1035ms total)
T0134 002:243 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 1035ms total)
T0134 002:253 JLINKARM_SetResetDelay(0) (0000ms, 1042ms total)
T0134 002:253 JLINKARM_ResetPullsRESET(ON) (0000ms, 1042ms total)
T0134 002:253 JLINKARM_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x66 TIF> >0x66 TIF> >0x35 TIF> >0x16D TIF> >0xD0 TIF> >0xD0 TIF>TPIU fitted. >0xD0 TIF> >0xD0 TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0xD0 TIF> (0056ms, 1042ms total)
T0134 002:310 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 1098ms total)
T0134 002:310 JLINKARM_WriteReg(R15, 0x20000254) returns 0x00 (0000ms, 1098ms total)
T0134 002:310 JLINKARM_ReadReg(MSP) returns 0x20000400 (0000ms, 1098ms total)
T0134 002:310 JLINKARM_ReadReg(PSP) returns 0x00000000 (0000ms, 1098ms total)
T0134 002:310 JLINKARM_ReadReg(CFBP) returns 0x00000000 (0001ms, 1098ms total)
T0134 002:311 JLINKARM_WriteReg(MSP, 0x20002000) returns 0x00 (0000ms, 1099ms total)
T0134 002:311 JLINKARM_IsHalted() returns TRUE (0000ms, 1099ms total)
T0134 002:311 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 00 returns 0x01 (0002ms, 1099ms total)
T0134 002:314 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1102ms total)
T0134 002:318 JLINKARM_BeginDownload(Flags = 0x03) (0000ms, 1103ms total)
T0134 002:786 JLINKARM_ReadMemU32(0x00000000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000000) -- Data: 00 04 00 20 returns 0x01 (0003ms, 1103ms total)
T0134 002:789 JLINKARM_ReadMemU32(0x00000004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000004) -- Data: 09 1D 00 00 returns 0x01 (0002ms, 1106ms total)
T0134 002:791 JLINKARM_ResetPullsRESET(OFF) (0000ms, 1108ms total)
T0134 002:791 JLINKARM_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x66 TIF> >0x66 TIF> >0x35 TIF> >0x16D TIF> >0xD0 TIF> >0xD0 TIF>TPIU fitted. >0xD0 TIF> >0xD0 TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0xD0 TIF> (0051ms, 1108ms total)
T0134 002:842 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 1159ms total)
T0134 002:842 JLINKARM_ReadReg(MSP) returns 0x20000400 (0000ms, 1159ms total)
T0134 002:842 JLINKARM_ReadReg(PSP) returns 0x00000000 (0000ms, 1159ms total)
T0134 002:842 JLINKARM_ReadReg(CFBP) returns 0x00000000 (0000ms, 1159ms total)
T0134 002:842 JLINKARM_IsHalted() returns TRUE (0001ms, 1159ms total)
T0134 002:843 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 00 returns 0x01 (0002ms, 1159ms total)
T0134 002:845 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0001ms, 1161ms total)
T0134 003:676 JLINKARM_ReadMemU32(0x00000008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000008) -- Data: CB 1D 00 00 returns 0x01 (0003ms, 1162ms total)
T0134 003:679 JLINKARM_ReadMemU32(0x0000000C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x0000000C) -- Data: CF 1D 00 00 returns 0x01 (0002ms, 1165ms total)
T0134 003:681 JLINKARM_ReadMemU32(0x00000010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000010) -- Data: D3 1D 00 00 returns 0x01 (0002ms, 1167ms total)
T0134 003:683 JLINKARM_ReadMemU32(0x00000014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000014) -- Data: D7 1D 00 00 returns 0x01 (0002ms, 1169ms total)
T0134 003:685 JLINKARM_ReadMemU32(0x00000018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000018) -- Data: DB 1D 00 00 returns 0x01 (0003ms, 1171ms total)
T0134 003:688 JLINKARM_ReadMemU32(0x0000002C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x0000002C) -- Data: 0D 19 00 00 returns 0x01 (0002ms, 1174ms total)
T0134 003:690 JLINKARM_ReadMemU32(0x00000030, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000030) -- Data: E3 1D 00 00 returns 0x01 (0002ms, 1176ms total)
T0134 003:692 JLINKARM_ReadMemU32(0x00000038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x00000038) -- Data: BB 18 00 00 returns 0x01 (0002ms, 1178ms total)
T0134 003:694 JLINKARM_ReadMemU32(0x0000003C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x0000003C) -- Data: 81 16 00 00 returns 0x01 (0002ms, 1180ms total)
T0134 003:697 JLINKARM_ReadReg(R15) returns 0x00001D08 (0000ms, 1182ms total)
T0134 003:698 JLINKARM_ReadMemU16(0x0000156C, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x0000156C) -- Data: 00 B5 returns 0x01 (0002ms, 1182ms total)
T0134 003:700 JLINKARM_SetBPEx(Addr = 0x0000156C, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 1184ms total)
T0134 003:700 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0006ms, 1184ms total)
T0A20 004:578 JLINKARM_ReadMemU16(0x00001D08, 0x0001 Items, ...) -- CPU_ReadMem(2 bytes @ 0x00001D08) -- Data: 01 48 returns 0x01 (0003ms, 1190ms total)
T0A20 004:581 JLINKARM_WriteVectorCatch(0x00000000) >0x35 TIF> >0xD0 TIF> >0x16D TIF> returns 0x00 (0007ms, 1193ms total)
T0A20 004:588 JLINKARM_ReadMemU32(0xE000EDFC, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- Data: 00 00 00 01 returns 0x01 (0002ms, 1200ms total)
T0A20 004:590 JLINKARM_WriteMem(0xE000EDFC, 0x0004 Bytes, ...) -- Data: 00 00 00 01 -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x04 (0002ms, 1202ms total)
T0A20 004:592 JLINKARM_WriteMem(0xE0001028, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 1204ms total)
T0A20 004:593 JLINKARM_WriteMem(0xE0001038, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 1205ms total)
T0A20 004:594 JLINKARM_WriteMem(0xE0001048, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 1206ms total)
T0A20 004:595 JLINKARM_WriteMem(0xE0001058, 0x0004 Bytes, ...) -- Data: 00 00 00 00 -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0003ms, 1207ms total)
T0A20 004:598 JLINKARM_SWO_Control(JLINKARM_SWO_CMD_START, ...) -- UART -- 2250000bps
***** Error: USB communication timed out: Requested 4 bytes, received 0 bytes ! returns 0x00 (7094ms, 1210ms total)

542
Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.c
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/**************************************************************************//**
* @file
* @brief LCD Controller driver
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#include "FreeRTOS.h"
#include "task.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "efm32.h"
#include "lcdcontroller.h"
#include "lcddisplay.h"
/** Counts every n'th frame */
int frameCounter = 0;
/**************************************************************************//**
* @brief LCD Interrupt Handler, triggers on frame counter, every n'th frame
*****************************************************************************/
void LCD_IRQHandler(void)
{
LCD_TypeDef *lcd = LCD;
/* clear interrupt */
lcd->IFC = 0xFFFFFFFF;
frameCounter++;
}
/**************************************************************************//**
* @brief Enables a segment on the LCD display
* @param lcd Pointer to LCD register block
* @param com COM segment number
* @param bitvalue Bit value for segment
*****************************************************************************/
static void LCD_enableSegment(LCD_TypeDef * lcd, int com, int bitvalue)
{
switch (com)
{
case 0:
lcd->SEGD0L |= bitvalue;
break;
case 1:
lcd->SEGD1L |= bitvalue;
break;
case 2:
lcd->SEGD2L |= bitvalue;
break;
case 3:
lcd->SEGD3L |= bitvalue;
break;
case 4:
lcd->SEGD0H |= bitvalue;
break;
case 5:
lcd->SEGD1H |= bitvalue;
break;
case 6:
lcd->SEGD2H |= bitvalue;
break;
case 7:
lcd->SEGD3H |= bitvalue;
break;
}
}
/**************************************************************************//**
* @brief Disables a segment on the LCD Display
* @param lcd Pointer to LCD register structure
* @param com COM segment number
* @param bitvalue Bit value for segment
*****************************************************************************/
static void LCD_disableSegment(LCD_TypeDef * lcd, int com, int bitvalue)
{
switch (com)
{
case 0:
lcd->SEGD0L &= ~bitvalue;
break;
case 1:
lcd->SEGD1L &= ~bitvalue;
break;
case 2:
lcd->SEGD2L &= ~bitvalue;
break;
case 3:
lcd->SEGD3L &= ~bitvalue;
break;
case 4:
lcd->SEGD0H &= ~bitvalue;
break;
case 5:
lcd->SEGD1H &= ~bitvalue;
break;
case 6:
lcd->SEGD2H &= ~bitvalue;
break;
case 7:
lcd->SEGD3H &= ~bitvalue;
break;
}
}
/**************************************************************************//**
* @brief Write number on numeric part on LCD display
* @param lcd Pointer to LCD control block
* @param value Numeric value to put on display, in range -999 to +9999
*****************************************************************************/
void LCD_Number(LCD_TypeDef *lcd, int value)
{
int num, i, com, bit, digit, div, neg;
uint16_t bitpattern;
/* Parameter consistancy check */
if (value >= 9999)
{
value = 9999;
}
if (value <= -1000)
{
value = -999;
}
if (value < 0)
{
value = abs(value);
neg = 1;
}
else
{
neg = 0;
}
/* Extract useful digits */
div = 1;
for (digit = 0; digit < 4; digit++)
{
num = (value / div) % 10;
if ((neg == 1) && (digit == 3)) num = 10;
bitpattern = EM_Numbers[num];
for (i = 0; i < 7; i++)
{
bit = EFMDisplay.Number[digit].bit[i];
com = EFMDisplay.Number[digit].com[i];
if (bitpattern & (1 << i))
{
LCD_enableSegment(lcd, com, 1 << bit);
}
else
{
LCD_disableSegment(lcd, com, 1 << bit);
}
}
div = div * 10;
}
}
/**************************************************************************//**
* @brief Turn all segments on numeric display off
* @param lcd Pointer to LCD register structure
*****************************************************************************/
void LCD_NumberOff(LCD_TypeDef *lcd)
{
int digit, i, bit, com;
/* Turn off all segments */
for (digit = 0; digit < 4; digit++)
{
for (i = 0; i < 7; i++)
{
bit = EFMDisplay.Number[digit].bit[i];
com = EFMDisplay.Number[digit].com[i];
LCD_disableSegment(lcd, com, 1 << bit);
}
}
return;
}
/**************************************************************************//**
* @brief Write text on LCD display
* @param lcd Pointer to LCD register structure
* @param string Text string to show on display
*****************************************************************************/
void LCD_Write(LCD_TypeDef *lcd, char *string)
{
int data, length, index;
uint16_t bitfield;
uint32_t value;
uint32_t com, bit;
int i;
length = strlen(string);
index = 0;
/* fill out all characters on display */
for (index = 0; index < 7; index++)
{
if (index < length)
{
data = (int) *string;
}
else /* padding with space */
{
data = 0x20; /* SPACE */
}
/* defined letters currently starts at "SPACE" - 0x20; */
data = data - 0x20;
bitfield = EM_alphabet[data];
for (i = 0; i < 14; i++)
{
bit = EFMDisplay.Text[index].bit[i];
com = EFMDisplay.Text[index].com[i];
value = (1 << bit);
if (bitfield & (1 << i))
{
/* Turn on segment */
LCD_enableSegment(lcd, com, value);
}
else
{
/* Turn off segment */
LCD_disableSegment(lcd, com, value);
}
}
string++;
}
while (lcd->SYNCBUSY) ;
}
/**************************************************************************//**
* @brief LCD Disable all segments
* @param lcd Pointer to LCD register block
*****************************************************************************/
void LCD_AllOff(LCD_TypeDef *lcd)
{
lcd->SEGD0L = 0x00000000;
lcd->SEGD0H = 0x00000000;
lcd->SEGD1L = 0x00000000;
lcd->SEGD1H = 0x00000000;
lcd->SEGD2L = 0x00000000;
lcd->SEGD2H = 0x00000000;
lcd->SEGD3L = 0x00000000;
lcd->SEGD3H = 0x00000000;
while (lcd->SYNCBUSY) ;
}
/**************************************************************************//**
* @brief LCD Enable all segments
* @param lcd Pointer to LCD register block
*****************************************************************************/
void LCD_AllOn(LCD_TypeDef *lcd)
{
lcd->SEGD0L = 0xffffffff;
lcd->SEGD0H = 0xffffffff;
lcd->SEGD1L = 0xffffffff;
lcd->SEGD1H = 0xffffffff;
lcd->SEGD2L = 0xffffffff;
lcd->SEGD2H = 0xffffffff;
lcd->SEGD3L = 0xffffffff;
lcd->SEGD3H = 0xffffffff;
while (lcd->SYNCBUSY) ;
}
/**************************************************************************//**
* @brief LCD Light up or shut off Energy Mode indicator
* @param lcd Pointer to LCD register block
* @pararm em Energy Mode numer 0 to 4
* @param on Zero is off, non-zero is on
*****************************************************************************/
void LCD_EnergyMode(LCD_TypeDef *lcd, int em, int on)
{
uint32_t com, bitvalue;
com = EFMDisplay.EMode.com[em];
bitvalue = 1 << EFMDisplay.EMode.bit[em];
if (on)
{
LCD_enableSegment(lcd, com, bitvalue);
}
else
{
LCD_disableSegment(lcd, com, bitvalue);
}
}
/**************************************************************************//**
* @brief LCD Light up or shut off Ring of Indicators
* @param lcd Pointer to LCD register block
* @param anum "Segment number" on "Ring", range 0 - 7
* @param on Zero is off, non-zero is on
*****************************************************************************/
void LCD_ARing(LCD_TypeDef *lcd, int anum, int on)
{
uint32_t com, bitvalue;
com = EFMDisplay.ARing.com[anum];
bitvalue = 1 << EFMDisplay.ARing.bit[anum];
if (on)
{
LCD_enableSegment(lcd, com, bitvalue);
}
else
{
LCD_disableSegment(lcd, com, bitvalue);
}
}
/**************************************************************************//**
* @brief LCD Light up or shut off various symbols on LCD Display
* @param lcd Pointer to LCD register block
* @param s Which symbol to turn on or off
* @param on Zero is off, non-zero is on
*****************************************************************************/
void LCD_Symbol(LCD_TypeDef *lcd, lcdSymbol s, int on)
{
int com, bit;
switch (s)
{
case LCD_SYMBOL_GECKO:
com = 3; bit = 8;
break;
case LCD_SYMBOL_ANT:
com = 3; bit = 1;
break;
case LCD_SYMBOL_PAD0:
com = 1; bit = 8;
break;
case LCD_SYMBOL_PAD1:
com = 2; bit = 8;
break;
case LCD_SYMBOL_AM:
com = 4; bit = 0;
break;
case LCD_SYMBOL_PM:
com = 4; bit = 3;
break;
case LCD_SYMBOL_EFM32:
com = 0; bit = 8;
break;
case LCD_SYMBOL_MINUS:
com = 0; bit = 9;
break;
case LCD_SYMBOL_COL3:
com = 0; bit = 16;
break;
case LCD_SYMBOL_COL5:
com = 0; bit = 24;
break;
case LCD_SYMBOL_COL10:
com = 4; bit = 7;
break;
case LCD_SYMBOL_DP2:
com = 4; bit = 2;
break;
case LCD_SYMBOL_DP3:
com = 5; bit = 2;
break;
case LCD_SYMBOL_DP4:
com = 6; bit = 2;
break;
case LCD_SYMBOL_DP5:
com = 7; bit = 2;
break;
case LCD_SYMBOL_DP6:
com = 0; bit = 21;
break;
case LCD_SYMBOL_DP10:
com = 4; bit = 5;
break;
}
if (on)
{
LCD_enableSegment(lcd, com, 1 << bit);
}
else
{
LCD_disableSegment(lcd, com, 1 << bit);
}
}
/**************************************************************************//**
* @brief LCD Light up or shut off Battery Indicator
* @param lcd Pointer to LCD register block
* @param batteryLevel Battery Level, 0 to 4 (0 turns all off)
*****************************************************************************/
void LCD_Battery(LCD_TypeDef *lcd, int batteryLevel)
{
uint32_t com, bitvalue;
int i, on;
for (i = 0; i < 4; i++)
{
if (i < batteryLevel)
{
on = 1;
}
else
{
on = 0;
}
com = EFMDisplay.Battery.com[i];
bitvalue = 1 << EFMDisplay.Battery.bit[i];
if (on)
{
LCD_enableSegment(lcd, com, bitvalue);
}
else
{
LCD_disableSegment(lcd, com, bitvalue);
}
}
}
/**************************************************************************//**
* @brief LCD Initialization routine for EFM32 DVK display
* @param lcd Pointer to LCD register block
*****************************************************************************/
void LCD_Init(LCD_TypeDef *lcd)
{
CMU_TypeDef *cmu = CMU;
/* Enable LFXO oscillator */
cmu->OSCENCMD |= CMU_OSCENCMD_LFXOEN;
while (!(cmu->STATUS & CMU_STATUS_LFXORDY)) ;
/* Enable LCD clock in CMU */
cmu->LFACLKEN0 |= CMU_LFACLKEN0_LCD;
/* Select LFXO for LCD */
cmu->LFCLKSEL = CMU_LFCLKSEL_LFA_LFXO | CMU_LFCLKSEL_LFB_LFXO;
/* LCD Controller Prescaler (divide by 1) */
/* CLKlcd = 0.25 kHz */
cmu->LFAPRESC0 &= ~_CMU_LFAPRESC0_LCD_MASK;
cmu->LFAPRESC0 |= _CMU_LFAPRESC0_LCD_DIV128 << _CMU_LFAPRESC0_LCD_SHIFT;
/* Set up interrupt handler */
lcd->IEN = 0;
while (lcd->SYNCBUSY) ;
/* Clear pending interrupts */
lcd->IFC = ~0;
/* Enable interrupt */
NVIC_EnableIRQ(LCD_IRQn);
lcd->IEN = LCD_IEN_FC;
/* Frame rate is 32Hz, 0.25Khz LFCLK128, QUADRUPLEX mode, FDIV=0 */
lcd->DISPCTRL = LCD_DISPCTRL_MUX_QUADRUPLEX |
LCD_DISPCTRL_BIAS_ONETHIRD |
LCD_DISPCTRL_WAVE_LOWPOWER |
LCD_DISPCTRL_CONLEV_MAX |
LCD_DISPCTRL_VLCDSEL_VDD |
LCD_DISPCTRL_VBLEV_3V00;
/* No voltage boost, framerate 32Hz */
cmu->LCDCTRL = 0;
/* Turn all segments off */
LCD_AllOff(lcd);
/* Enable all segment registers */
lcd->SEGEN = 0x000003FF;
lcd->CTRL = LCD_CTRL_EN | LCD_CTRL_UDCTRL_FRAMESTART;
while (lcd->SYNCBUSY) ;
/* Configure LCD to give a frame counter interrupt every 8th frame. */
lcd->BACTRL = LCD_BACTRL_FCEN | (7 << _LCD_BACTRL_FCTOP_SHIFT) | (0 << _LCD_BACTRL_FCPRESC_SHIFT);
while (lcd->SYNCBUSY) ;
lcd->IFC = LCD_IFC_FC;
lcd->IEN = LCD_IEN_FC;
}
/**************************************************************************//**
* @brief Disables LCD controller
* @param lcd Pointer to LCD register block
*****************************************************************************/
void LCD_Disable(LCD_TypeDef *lcd)
{
CMU_TypeDef *cmu = CMU;
/* Turn off interrupts */
lcd->IEN = 0x00000000;
lcd->IFC = LCD_IFC_FC;
NVIC_DisableIRQ(LCD_IRQn);
/* Disable LCD */
lcd->CTRL = 0;
/* Turn off LCD clock */
cmu->LFACLKEN0 &= ~(CMU_LFACLKEN0_LCD);
/* Turn off voltage boost if enabled */
cmu->LCDCTRL = 0;
}
/**************************************************************************//**
* @brief LCD scrolls a text over the display, sort of "polled printf"
* @param lcd Pointer to LCD register block
*****************************************************************************/
void LCD_ScrollText(LCD_TypeDef *lcd, char *scrolltext)
{
int i, len;
char buffer[8];
buffer[7] = 0x00;
len = strlen(scrolltext);
if (len < 7) return;
for (i = 0; i < (len - 7); i++)
{
memcpy(buffer, scrolltext + i, 7);
LCD_Write(lcd, buffer);
vTaskDelay(100/portTICK_RATE_MS);
}
}

73
Demo/CORTEX_EFMG890F128_IAR/lcd/lcdcontroller.h
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/**************************************************************************//**
* @file
* @brief LCD Controller header file
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef _LCDCONTROLLER_H
#define _LCDCONTROLLER_H
#include "efm32.h"
/* Range of symbols available on display */
typedef enum
{
LCD_SYMBOL_GECKO,
LCD_SYMBOL_ANT,
LCD_SYMBOL_PAD0,
LCD_SYMBOL_PAD1,
LCD_SYMBOL_AM,
LCD_SYMBOL_PM,
LCD_SYMBOL_EFM32,
LCD_SYMBOL_MINUS,
LCD_SYMBOL_COL3,
LCD_SYMBOL_COL5,
LCD_SYMBOL_COL10,
LCD_SYMBOL_DP2,
LCD_SYMBOL_DP3,
LCD_SYMBOL_DP4,
LCD_SYMBOL_DP5,
LCD_SYMBOL_DP6,
LCD_SYMBOL_DP10,
} lcdSymbol;
/* Regular functions */
void LCD_Init(LCD_TypeDef *lcd);
void LCD_IRQHandler(void);
void LCD_Disable(LCD_TypeDef *lcd);
void LCD_AllOff(LCD_TypeDef *lcd);
void LCD_AllOn(LCD_TypeDef *lcd);
void LCD_ARing(LCD_TypeDef *lcd, int anum, int on);
void LCD_Battery(LCD_TypeDef *lcd, int batteryLevel);
void LCD_EnergyMode(LCD_TypeDef *lcd, int em, int on);
void LCD_Number(LCD_TypeDef *lcd, int value);
void LCD_NumberOff(LCD_TypeDef *lcd);
void LCD_Symbol(LCD_TypeDef *lcd, lcdSymbol s, int on);
void LCD_Write(LCD_TypeDef *lcd, char *string);
void LCD_ScrollText(LCD_TypeDef *lcd, char *scrolltext);
#endif

391
Demo/CORTEX_EFMG890F128_IAR/lcd/lcddisplay.h
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/**************************************************************************//**
* @file
* @brief LCD Controller font and display layout for EFM32 development MCU
* module
* @author Energy Micro AS
* @version 1.0.1
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
****************************************************************************/
#ifndef _LCDDISPLAY_H
#define _LCDDISPLAY_H
#include <stdint.h>
/**************************************************************************//**
* @brief
* Defines each text symbol's segment in terms of COM and BIT numbers,
* in a way that we can enumerate each bit for each text segment in the
* following bit pattern:
* @verbatim
* -------0------
*
* | \7 |8 /9 |
* |5 \ | / |1
*
* --6--- ---10--
*
* | / | \11 |
* |4 /13 |12 \ |2
*
* -------3------
* @endverbatim
* E.g.: First text character bit pattern #3 (above) is
* Segment 1D for Display
* Location COM 3, BIT 0
*****************************************************************************/
typedef struct
{
uint32_t com[14]; /**< LCD COM line (for multiplexing) */
uint32_t bit[14]; /**< LCD bit number */
} CHAR_TypeDef;
/**************************************************************************//**
* @brief Defines segment COM and BIT fields numeric display
*****************************************************************************/
typedef struct
{
uint32_t com[7];
uint32_t bit[7];
} NUMBER_TypeDef;
/**************************************************************************//**
* @brief Defines segment COM and BIT fields for Energy Modes on display
*****************************************************************************/
typedef struct
{
uint32_t com[5]; /**< LCD COM line (for multiplexing) */
uint32_t bit[5]; /**< LCD bit number */
} EM_TypeDef;
/**************************************************************************//**
* @brief Defines segment COM and BIT fields for A-wheel (suited for Anim)
*****************************************************************************/
typedef struct
{
uint32_t com[8]; /**< LCD COM line (for multiplexing) */
uint32_t bit[8]; /**< LCD bit number */
} ARING_TypeDef;
/**************************************************************************//**
* @brief Defines segment COM and BIT fields for A-wheel (suited for Anim)
*****************************************************************************/
typedef struct
{
uint32_t com[4]; /**< LCD COM line (for multiplexing) */
uint32_t bit[4]; /**< LCD bit number */
} BATTERY_TypeDef;
/**************************************************************************//**
* @brief Defines prototype for all segments in display
*****************************************************************************/
typedef struct
{
CHAR_TypeDef Text[7];
NUMBER_TypeDef Number[4];
EM_TypeDef EMode;
ARING_TypeDef ARing;
BATTERY_TypeDef Battery;
} MCU_DISPLAY;
/**************************************************************************//**
* @brief Working instance of LCD display
*****************************************************************************/
MCU_DISPLAY EFMDisplay = {
.Text = {
{ /* 1 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 10, .bit[1] = 12, .bit[2] = 12, .bit[3] = 10,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 9, .bit[5] = 9, .bit[6] = 9, .bit[7] = 10,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 11, .bit[9] = 11, .bit[10] = 12, .bit[11] = 11,
.com[12] = 1, .com[13] = 1,
.bit[12] = 11, .bit[13] = 10
},
{ /* 2 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 14, .bit[1] = 16, .bit[2] = 16, .bit[3] = 14,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 13, .bit[5] = 13, .bit[6] = 13, .bit[7] = 14,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 15, .bit[9] = 15, .bit[10] = 16, .bit[11] = 15,
.com[12] = 1, .com[13] = 1,
.bit[12] = 15, .bit[13] = 14
},
{ /* 3 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 18, .bit[1] = 20, .bit[2] = 20, .bit[3] = 18,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 17, .bit[5] = 17, .bit[6] = 17, .bit[7] = 18,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 19, .bit[9] = 19, .bit[10] = 20, .bit[11] = 19,
.com[12] = 1, .com[13] = 1,
.bit[12] = 19, .bit[13] = 18
},
{ /* 4 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 22, .bit[1] = 24, .bit[2] = 24, .bit[3] = 22,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 21, .bit[5] = 21, .bit[6] = 21, .bit[7] = 22,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 23, .bit[9] = 23, .bit[10] = 24, .bit[11] = 23,
.com[12] = 1, .com[13] = 1,
.bit[12] = 23, .bit[13] = 22
},
{ /* 5 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 25, .bit[1] = 6, .bit[2] = 6, .bit[3] = 25,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 7, .bit[5] = 7, .bit[6] = 7, .bit[7] = 25,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 26, .bit[9] = 26, .bit[10] = 6, .bit[11] = 26,
.com[12] = 1, .com[13] = 1,
.bit[12] = 26, .bit[13] = 25
},
{ /* 6 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 27, .bit[1] = 04, .bit[2] = 04, .bit[3] = 27,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 5, .bit[5] = 5, .bit[6] = 5, .bit[7] = 27,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 28, .bit[9] = 28, .bit[10] = 4, .bit[11] = 28,
.com[12] = 1, .com[13] = 1,
.bit[12] = 28, .bit[13] = 27
},
{ /* 7 */
.com[0] = 3, .com[1] = 3, .com[2] = 1, .com[3] = 0,
.bit[0] = 29, .bit[1] = 2, .bit[2] = 2, .bit[3] = 29,
.com[4] = 1, .com[5] = 3, .com[6] = 2, .com[7] = 2,
.bit[4] = 03, .bit[5] = 3, .bit[6] = 3, .bit[7] = 29,
.com[8] = 2, .com[9] = 3, .com[10] = 2, .com[11] = 0,
.bit[8] = 30, .bit[9] = 30, .bit[10] = 2, .bit[11] = 30,
.com[12] = 1, .com[13] = 1,
.bit[12] = 30, .bit[13] = 29
}
},
.Number = {
{
.com[0] = 3, .com[1] = 2, .com[2] = 1, .com[3] = 0,
.bit[0] = 31, .bit[1] = 31, .bit[2] = 31, .bit[3] = 31,
.com[4] = 5, .com[5] = 7, .com[6] = 6,
.bit[4] = 0, .bit[5] = 0, .bit[6] = 0,
},
{
.com[0] = 7, .com[1] = 6, .com[2] = 5, .com[3] = 4,
.bit[0] = 1, .bit[1] = 1, .bit[2] = 1, .bit[3] = 1,
.com[4] = 5, .com[5] = 7, .com[6] = 6,
.bit[4] = 3, .bit[5] = 3, .bit[6] = 3,
},
{
.com[0] = 7, .com[1] = 6, .com[2] = 5, .com[3] = 4,
.bit[0] = 4, .bit[1] = 4, .bit[2] = 4, .bit[3] = 4,
.com[4] = 5, .com[5] = 7, .com[6] = 6,
.bit[4] = 5, .bit[5] = 5, .bit[6] = 5,
},
{
.com[0] = 7, .com[1] = 6, .com[2] = 5, .com[3] = 4,
.bit[0] = 6, .bit[1] = 6, .bit[2] = 6, .bit[3] = 6,
.com[4] = 5, .com[5] = 7, .com[6] = 6,
.bit[4] = 7, .bit[5] = 7, .bit[6] = 7,
},
},
.EMode = {
.com[0] = 1, .bit[0] = 1,
.com[1] = 2, .bit[1] = 1,
.com[2] = 1, .bit[2] = 0,
.com[3] = 2, .bit[3] = 0,
.com[4] = 3, .bit[4] = 0,
},
.ARing = {
.com[0] = 0, .bit[0] = 0,
.com[1] = 0, .bit[1] = 1,
.com[2] = 0, .bit[2] = 2,
.com[3] = 0, .bit[3] = 3,
.com[4] = 0, .bit[4] = 4,
.com[5] = 0, .bit[5] = 5,
.com[6] = 0, .bit[6] = 6,
.com[7] = 0, .bit[7] = 7,
},
.Battery = {
.com[0] = 0, .bit[0] = 12,
.com[1] = 0, .bit[1] = 17,
.com[2] = 0, .bit[2] = 20,
.com[3] = 0, .bit[3] = 13,
}
};
/**************************************************************************//**
* @brief
* Defines higlighted segments for the alphabet, starting from "blank" (SPACE)
* Uses bit pattern as defined for text segments above.
* E.g. a capital O, would have bits 0 1 2 3 4 5 => 0x003f defined
*****************************************************************************/
uint16_t EM_alphabet[] = {
0x0000, /* space */
0x1100, /* ! */
0x0280, /* " */
0x0000, /* # */
0x0000, /* $ */
0x0000, /* % */
0x0000, /* & */
0x0000, /* £ */
0x0039, /* ( */
0x000f, /* ) */
0x0000, /* * */
0x1540, /* + */
0x0000, /* , */
0x0440, /* - */
0x0000, /* . */
0x2200, /* / */
0x003f, /* 0 */
0x0006, /* 1 */
0x045b, /* 2 */
0x044f, /* 3 */
0x0466, /* 4 */
0x046d, /* 5 */
0x047d, /* 6 */
0x0007, /* 7 */
0x047f, /* 8 */
0x046f, /* 9 */
0x0000, /* : */
0x0000, /* ; */
0x0a00, /* < */
0x0000, /* = */
0x2080, /* > */
0x0000, /* ? */
0xffff, /* @ */
0x0477, /* A */
0x0a79, /* B */
0x0039, /* C */
0x20b0, /* D */
0x0079, /* E */
0x0071, /* F */
0x047d, /* G */
0x0476, /* H */
0x0006, /* I */
0x000e, /* J */
0x0a70, /* K */
0x0038, /* L */
0x02b6, /* M */
0x08b6, /* N */
0x003f, /* O */
0x0473, /* P */
0x083f, /* Q */
0x0c73, /* R */
0x046d, /* S */
0x1101, /* T */
0x003e, /* U */
0x2230, /* V */
0x2836, /* W */
0x2a80, /* X */
0x046e, /* Y */
0x2209, /* Z */
0x0039, /* [ */
0x0880, /* backslash */
0x000f, /* ] */
0x0001, /* ^ */
0x0008, /* _ */
0x0100, /* ` */
0x1058, /* a */
0x047c, /* b */
0x0058, /* c */
0x045e, /* d */
0x2058, /* e */
0x0471, /* f */
0x0c0c, /* g */
0x0474, /* h */
0x0004, /* i */
0x000e, /* j */
0x0c70, /* k */
0x0038, /* l */
0x1454, /* m */
0x0454, /* n */
0x045c, /* o */
0x0473, /* p */
0x0467, /* q */
0x0450, /* r */
0x0c08, /* s */
0x0078, /* t */
0x001c, /* u */
0x2010, /* v */
0x2814, /* w */
0x2a80, /* x */
0x080c, /* y */
0x2048, /* z */
0x0000,
};
/**************************************************************************//**
* @brief
* Defines higlighted segments for the numeric display
*****************************************************************************/
uint16_t EM_Numbers[] =
{
0x003f, /* 0 */
0x0006, /* 1 */
0x005b, /* 2 */
0x004f, /* 3 */
0x0066, /* 4 */
0x006d, /* 5 */
0x007d, /* 6 */
0x0007, /* 7 */
0x007f, /* 8 */
0x006f, /* 9 */
0x0040, /* - */
};
#endif

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/*
FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd.
***************************************************************************
* *
* If you are: *
* *
* + New to FreeRTOS, *
* + Wanting to learn FreeRTOS or multitasking in general quickly *
* + Looking for basic training, *
* + Wanting to improve your FreeRTOS skills and productivity *
* *
* then take a look at the FreeRTOS eBook *
* *
* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
* http://www.FreeRTOS.org/Documentation *
* *
* A pdf reference manual is also available. Both are usually delivered *
* to your inbox within 20 minutes to two hours when purchased between 8am *
* and 8pm GMT (although please allow up to 24 hours in case of *
* exceptional circumstances). Thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
***NOTE*** The exception to the GPL is included to allow you to distribute
a combined work that includes FreeRTOS without being obliged to provide the
source code for proprietary components outside of the FreeRTOS kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo includes. */
#include "lcdtest.h"
#define lcdSHORT_DELAY ( 60 / portTICK_RATE_MS )
#define lcdQUARTER_SECOND ( 250 / portTICK_RATE_MS )
#define lcdONE_SECOND ( 1000 / portTICK_RATE_MS )
void vLCDTask( void *pvParameters )
{
long x;
LCD_TypeDef *xLCD = LCD;
char *pcScrollText = "FreeRTOS Energy Micro ";
/* Loop through various different displays. */
for( ;; )
{
/* Start by scrolling some text. */
LCD_ScrollText( xLCD, pcScrollText );
LCD_AllOff( xLCD );
/* Count down from 100 on the number section of the LCD display. */
for( x = 100; x > 0; x--)
{
LCD_Number( xLCD, x );
vTaskDelay( 10 );
}
LCD_NumberOff( xLCD );
/* Turn on gecko and EFM32 symbol. */
LCD_Symbol( xLCD, LCD_SYMBOL_GECKO, 1 );
LCD_Symbol( xLCD, LCD_SYMBOL_EFM32, 1 );
LCD_Write( xLCD, " Gecko " );
vTaskDelay( lcdONE_SECOND );
LCD_AllOn( xLCD);
vTaskDelay( lcdONE_SECOND );
LCD_AllOff( xLCD);
LCD_Write( xLCD, "OOOOOOO" );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, "XXXXXXX" );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, "+++++++" );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, "@@@@@@@" );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, "ENERGY " );
vTaskDelay( lcdQUARTER_SECOND );
LCD_Write( xLCD, "@@ERGY " );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " @@RGY " );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " M@@GY " );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " MI@@Y " );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " MIC@@ " );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " MICR@@" );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " MICRO@" );
vTaskDelay( lcdSHORT_DELAY );
LCD_Write( xLCD, " MICRO " );
vTaskDelay( lcdQUARTER_SECOND );
LCD_Write( xLCD, "-EFM32-" );
vTaskDelay( lcdQUARTER_SECOND );
}
}

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Demo/CORTEX_EFMG890F128_IAR/lcdtest.h
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#ifndef _LCDTEST_H
#define _LCDTEST_H
#include "FreeRTOS.h"
#include "task.h"
#include "lcdcontroller.h"
/*
* The task that writes to the LCD.
*/
void vLCDTask( void *pvParameters );
#endif

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Demo/CORTEX_EFMG890F128_IAR/ledtest.c
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/*
FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd.
***************************************************************************
* *
* If you are: *
* *
* + New to FreeRTOS, *
* + Wanting to learn FreeRTOS or multitasking in general quickly *
* + Looking for basic training, *
* + Wanting to improve your FreeRTOS skills and productivity *
* *
* then take a look at the FreeRTOS eBook *
* *
* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
* http://www.FreeRTOS.org/Documentation *
* *
* A pdf reference manual is also available. Both are usually delivered *
* to your inbox within 20 minutes to two hours when purchased between 8am *
* and 8pm GMT (although please allow up to 24 hours in case of *
* exceptional circumstances). Thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
***NOTE*** The exception to the GPL is included to allow you to distribute
a combined work that includes FreeRTOS without being obliged to provide the
source code for proprietary components outside of the FreeRTOS kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo app includes. */
#include "ledtest.h"
#define lLEDOnE_SECOND ( 1000UL / portTICK_RATE_MS )
void vLEDTask( void *pvParameters )
{
long lLEDOn = pdTRUE, x;
for( ;; )
{
for( x = 8; x < 16; x++ )
{
/*Depending on if lLEDOn is true or false, turn on or off led number i*/
vParTestSetLED( x,lLEDOn );
/*Delay for 1000 ms*/
vTaskDelay( lLEDOnE_SECOND );
}
/*After the for loop, we flip lLEDOn. On the next run through the
for loop above, the leds will be flipped.*/
lLEDOn = ~lLEDOn;
}
}

66
Demo/CORTEX_EFMG890F128_IAR/ledtest.h
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/*
FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd.
***************************************************************************
* *
* If you are: *
* *
* + New to FreeRTOS, *
* + Wanting to learn FreeRTOS or multitasking in general quickly *
* + Looking for basic training, *
* + Wanting to improve your FreeRTOS skills and productivity *
* *
* then take a look at the FreeRTOS eBook *
* *
* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
* http://www.FreeRTOS.org/Documentation *
* *
* A pdf reference manual is also available. Both are usually delivered *
* to your inbox within 20 minutes to two hours when purchased between 8am *
* and 8pm GMT (although please allow up to 24 hours in case of *
* exceptional circumstances). Thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
***NOTE*** The exception to the GPL is included to allow you to distribute
a combined work that includes FreeRTOS without being obliged to provide the
source code for proprietary components outside of the FreeRTOS kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef LEDTEST_H
#define LEDTEST_H
#include "FreeRTOS.h"
#include "task.h"
#include "partest.h"
/*
* A task that writes to the LEDs.
*/
void vLEDTask( void *pvParamters );
#endif /* LEDTEST_H */

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Demo/CORTEX_EFMG890F128_IAR/main.c
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/*
FreeRTOS V6.0.3 - Copyright (C) 2010 Real Time Engineers Ltd.
***************************************************************************
* *
* If you are: *
* *
* + New to FreeRTOS, *
* + Wanting to learn FreeRTOS or multitasking in general quickly *
* + Looking for basic training, *
* + Wanting to improve your FreeRTOS skills and productivity *
* *
* then take a look at the FreeRTOS eBook *
* *
* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
* http://www.FreeRTOS.org/Documentation *
* *
* A pdf reference manual is also available. Both are usually delivered *
* to your inbox within 20 minutes to two hours when purchased between 8am *
* and 8pm GMT (although please allow up to 24 hours in case of *
* exceptional circumstances). Thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
***NOTE*** The exception to the GPL is included to allow you to distribute
a combined work that includes FreeRTOS without being obliged to provide the
source code for proprietary components outside of the FreeRTOS kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the standard demo application tasks.
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "LCD test" task - the LCD task writes a continually repeating series of patterns
* to the LCD display.
*
* "LED test" task - This is a very simple task that just turns on user LEDs
* 8 to 15 in turn, before turning them off again.
*
* "Check task" - The check task only runs every five seconds but has the highest
* priority so is guaranteed to get processing time. Its main job is to inspect
* all the other standard demo tasks to ensure they are executing without error.
* The Check task will toggle LED 0 every five seconds while no errors exist,
* with the toggle frequency increasing to 200ms should an error be detected in
* any other task.
*
* Both the check task and the idle task place the processor into energy saving
* mode 1, which will be exited following each tick interrupt. The check task
* is the highest priority task in the system, so while it is executing no other
* task will execute. If the check task places the processor into a low power
* mode without blocking then the energy consumption as viewed on the Energy
* Micro Gecko board will go down noticibly as in effect no tasks will be running.
* The check task places the processor into low power mode for two out of every
* five seconds. The current use of low power modes is very basic. Future
* FreeRTOS releases will aim to make significant improvements.
*
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "croutine.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Common demo application includes. */
#include "partest.h"
#include "GenQTest.h"
#include "QPeek.h"
#include "recmutex.h"
#include "semtest.h"
/* Demo application includes. */
#include "lcdcontroller.h"
#include "ledtest.h"
#include "lcdtest.h"
#include "chip.h"
/* Task priorities. */
#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainGEN_Q_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
/* A period of two seconds, adjusted to use the tick frequency. */
#define mainTWO_SECONDS ( 2000 / portTICK_RATE_MS )
/* The length of the delay between each cycle of the check task when an error
has / has not been detected. */
#define mainNO_ERROR_CHECK_FREQUENCY ( 5000 / portTICK_RATE_MS )
#define mainERROR_CHECK_FREQUENCY ( 200 / portTICK_RATE_MS )
/* The LED that is toggled by the check task. The rate of the toggle indicates
whether or not an error has been found, as defined by the
mainNO_ERROR_CHECK_FREQUENCY and mainERROR_CHECK_FREQUENCY definitions above. */
#define mainCHECK_LED ( 0 )
/*-----------------------------------------------------------*/
/*
* Configure the hardware as required by the demo.
*/
static void prvSetupHardware( void );
/*
* The check task as described at the top of this file.
*/
static void prvCheckTask( void *pvParameters );
/*
* Put the CPU into the least low power low power mode.
*/
static void prvLowPowerMode1( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* Perform the necessary hardware configuration. */
prvSetupHardware();
/* Create the task that writes various text and patterns to the LCD. */
xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );
/* Create a task that writes to LEDs 8 to 15. */
xTaskCreate( vLEDTask, "LCDTask", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL );
/* Create some of the standard demo tasks. These just test the port and
demonstrate how the FreeRTOS API can be used. They do not provide any
specific functionality. */
vStartGenericQueueTasks( mainGEN_Q_TASK_PRIORITY );
vStartQueuePeekTasks();
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY );
/* Create the check task as described at the top of this file. */
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* The scheduler should now be running the tasks so the following code should
never be reached. If it is reached then there was insufficient heap space
for the idle task to be created. In this case the heap size is set by
configTOTAL_HEAP_SIZE in FreeRTOSConfig.h. */
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* Use the idle task to place the CPU into a low power mode. Greater power
saving could be achieved by not including any demo tasks that never block. */
prvLowPowerMode1();
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )
{
/* This function will be called if a task overflows its stack, if
configCHECK_FOR_STACK_OVERFLOW != 0. It might be that the function
parameters have been corrupted, depending on the severity of the stack
overflow. When this is the case pxCurrentTCB can be inspected in the
debugger to find the offending task. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
portTickType xLastExecutionTime, xFrequency = mainNO_ERROR_CHECK_FREQUENCY;
long lCount;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
for( ;; )
{
/* Perform this check at a frequency that indicates whether or not an
error has been found. */
vTaskDelayUntil( &xLastExecutionTime, xFrequency );
/* Check all the other tasks are running without error. */
if( xAreGenericQueueTasksStillRunning() != pdPASS )
{
xFrequency = mainERROR_CHECK_FREQUENCY;
}
if( xAreQueuePeekTasksStillRunning() != pdPASS )
{
xFrequency = mainERROR_CHECK_FREQUENCY;
}
if( xAreRecursiveMutexTasksStillRunning() != pdPASS )
{
xFrequency = mainERROR_CHECK_FREQUENCY;
}
if( xAreSemaphoreTasksStillRunning() != pdPASS )
{
xFrequency = mainERROR_CHECK_FREQUENCY;
}
/* Toggle the LED to show that the check hook function is running.
The toggle freequency will increase if an error has been found in any
task. */
vParTestToggleLED( mainCHECK_LED );
/* Just loop around putting the processor into low power mode 1 for
a while. This is the highest priority task, and this loop does not
cause it to block, so it will remain as the running task. Each time it
runs for the next two seconds it will simply put the processor to sleep.
No other task will run so nothing else will happen. This periodic two
seconds of lower power should be viewable using the Advanced Energy
Monitor on the Energy Micro Gecko board. */
for( lCount = 0; lCount < mainTWO_SECONDS; lCount++ )
{
prvLowPowerMode1();
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Initialise the LEDs. */
vParTestInitialise();
/* Configure the LCD. */
LCD_Init( LCD );
}
/*-----------------------------------------------------------*/
static void prvLowPowerMode1( void )
{
/* Clear SLEEPDEEP for EM1 */
SCB->SCR &= ~( 1 << SCB_SCR_SLEEPDEEP_Pos );
/* Power down. */
__WFI();
}

33
Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.cspy.bat
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@REM C-SPY interactive debugger,as an aid to preparing a command
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@REM After making some adjustments to this file, you can launch cspybat
@REM by typing the name of this file followed by the name of the debug
@REM file (usually an ubrof file). Note that this file is generated
@REM every time a new debug session is initialized, so you may want to
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@REM Note: some command line arguments cannot be properly generated
@REM by this process. Specifically, the plugin which is responsible
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@REM Loaded plugins:
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Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dbgdt
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Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.dni
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Checksum=-346520476
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Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo.wsdt
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Demo/CORTEX_EFMG890F128_IAR/settings/RTOSDemo_Debug.jlink
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[FLASH]
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323
Demo/CORTEX_EFMG890F128_IAR/startup_efm32.s
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;/*************************************************************************//**
; * @file: startup_efm32.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Energy Micro 'EFM32G' Device Series
; * @version 1.0.2
; * @date: 10. September 2009
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD vPortSVCHandler
DCD DebugMon_Handler
DCD 0
DCD xPortPendSVHandler
DCD xPortSysTickHandler
; External Interrupts
DCD DMA_IRQHandler ; 0: DMA Interrupt
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
DCD TIMER2_IRQHandler ; 11: TIMER2 Interrupt
DCD USART1_RX_IRQHandler ; 12: USART1_RX Interrupt
DCD USART1_TX_IRQHandler ; 13: USART1_TX Interrupt
DCD USART2_RX_IRQHandler ; 14: USART2_RX Interrupt
DCD USART2_TX_IRQHandler ; 15: USART2_TX Interrupt
DCD UART0_RX_IRQHandler ; 16: UART0_RX Interrupt
DCD UART0_TX_IRQHandler ; 17: UART0_TX Interrupt
DCD LEUART0_IRQHandler ; 18: LEUART0 Interrupt
DCD LEUART1_IRQHandler ; 19: LEUART1 Interrupt
DCD LETIMER0_IRQHandler ; 20: LETIMER0 Interrupt
DCD PCNT0_IRQHandler ; 21: PCNT0 Interrupt
DCD PCNT1_IRQHandler ; 22: PCNT1 Interrupt
DCD PCNT2_IRQHandler ; 23: PCNT2 Interrupt
DCD SYSTICCK_IRQHandler;DCD RTC_IRQHandler ; 24: RTC Interrupt
DCD CMU_IRQHandler ; 25: CMU Interrupt
DCD VCMP_IRQHandler ; 26: VCMP Interrupt
DCD LCD_IRQHandler ; 27: LCD Interrupt
DCD MSC_IRQHandler ; 28: MSC Interrupt
DCD AES_IRQHandler ; 29: AES Interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK vPortSVCHandler
SECTION .text:CODE:REORDER(1)
vPortSVCHandler
B vPortSVCHandler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK xPortPendSVHandler
SECTION .text:CODE:REORDER(1)
xPortPendSVHandler
B xPortPendSVHandler
PUBWEAK SYSTICCK_IRQHandler
SECTION .text:CODE:REORDER(1)
SYSTICCK_IRQHandler
B SYSTICCK_IRQHandler
; EFM32G specific interrupt handlers
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK GPIO_EVEN_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_EVEN_IRQHandler
B GPIO_EVEN_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK USART0_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART0_RX_IRQHandler
B USART0_RX_IRQHandler
PUBWEAK USART0_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART0_TX_IRQHandler
B USART0_TX_IRQHandler
PUBWEAK ACMP0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACMP0_IRQHandler
B ACMP0_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK DAC0_IRQHandler
SECTION .text:CODE:REORDER(1)
DAC0_IRQHandler
B DAC0_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK GPIO_ODD_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_ODD_IRQHandler
B GPIO_ODD_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK USART1_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_RX_IRQHandler
B USART1_RX_IRQHandler
PUBWEAK USART1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_TX_IRQHandler
B USART1_TX_IRQHandler
PUBWEAK USART2_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_RX_IRQHandler
B USART2_RX_IRQHandler
PUBWEAK USART2_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_TX_IRQHandler
B USART2_TX_IRQHandler
PUBWEAK UART0_RX_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_RX_IRQHandler
B UART0_RX_IRQHandler
PUBWEAK UART0_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_TX_IRQHandler
B UART0_TX_IRQHandler
PUBWEAK LEUART0_IRQHandler
SECTION .text:CODE:REORDER(1)
LEUART0_IRQHandler
B LEUART0_IRQHandler
PUBWEAK LEUART1_IRQHandler
SECTION .text:CODE:REORDER(1)
LEUART1_IRQHandler
B LEUART1_IRQHandler
PUBWEAK LETIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
LETIMER0_IRQHandler
B LETIMER0_IRQHandler
PUBWEAK PCNT0_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT0_IRQHandler
B PCNT0_IRQHandler
PUBWEAK PCNT1_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT1_IRQHandler
B PCNT1_IRQHandler
PUBWEAK PCNT2_IRQHandler
SECTION .text:CODE:REORDER(1)
PCNT2_IRQHandler
B PCNT2_IRQHandler
PUBWEAK xPortSysTickHandler
SECTION .text:CODE:REORDER(1)
xPortSysTickHandler
B xPortSysTickHandler
PUBWEAK CMU_IRQHandler
SECTION .text:CODE:REORDER(1)
CMU_IRQHandler
B CMU_IRQHandler
PUBWEAK VCMP_IRQHandler
SECTION .text:CODE:REORDER(1)
VCMP_IRQHandler
B VCMP_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK MSC_IRQHandler
SECTION .text:CODE:REORDER(1)
MSC_IRQHandler
B MSC_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
END
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