Work in progress for backup only.
Richard Barry
15 years ago
parent
dbb3361ed9
commit
bc0e754d87
@ -0,0 +1,132 @@
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/*
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FreeRTOS V6.0.1 - Copyright (C) 2009 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
|
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* *
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* then take a look at the FreeRTOS eBook *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
|
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a combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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||||
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/*-----------------------------------------------------------
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* Simple IO routines to control the LEDs.
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*-----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Demo includes. */
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#include "partest.h"
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#define partestNUM_LEDS ( 6 )
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#define partestALL_LEDS ( usLEDMasks[ 0 ] | usLEDMasks[ 1 ] | usLEDMasks[ 2 ] | usLEDMasks[ 3 ] | usLEDMasks[ 4 ] | usLEDMasks[ 5 ] )
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static const unsigned short usLEDMasks[ partestNUM_LEDS ] = { ( 1 << 9 ), ( 1 << 11 ), ( 1 << 12 ), ( 1 << 13 ), ( 1 << 14 ), ( 1 << 15 ) };
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/*-----------------------------------------------------------*/
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void vParTestInitialise( void )
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{
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/* Select port functions for PE9 to PE15. */
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PFC.PECRL3.WORD &= ~partestALL_LEDS;
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/* Turn all LEDs off. */
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PE.DR.WORD &= ~partestALL_LEDS;
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/* Set all LEDs to output. */
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PFC.PEIORL.WORD |= partestALL_LEDS;
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}
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/*-----------------------------------------------------------*/
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void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
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{
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if( uxLED < partestNUM_LEDS )
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{
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if( xValue )
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{
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/* Turn the LED on. */
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taskENTER_CRITICAL();
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{
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PE.DR.WORD |= usLEDMasks[ uxLED ];
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}
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taskEXIT_CRITICAL();
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}
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else
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{
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/* Turn the LED off. */
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taskENTER_CRITICAL();
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{
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PE.DR.WORD &= ~usLEDMasks[ uxLED ];
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}
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taskEXIT_CRITICAL();
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}
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}
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}
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/*-----------------------------------------------------------*/
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void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
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{
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if( uxLED < partestNUM_LEDS )
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{
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taskENTER_CRITICAL();
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{
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if( ( PE.DR.WORD & usLEDMasks[ uxLED ] ) != 0x00 )
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{
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PE.DR.WORD &= ~usLEDMasks[ uxLED ];
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}
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else
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{
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PE.DR.WORD |= usLEDMasks[ uxLED ];
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}
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}
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taskEXIT_CRITICAL();
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}
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}
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Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -1,15 +1,160 @@
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/*
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FreeRTOS V6.0.1 - Copyright (C) 2009 Real Time Engineers Ltd.
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void main(void);
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
|
||||
* + Wanting to learn FreeRTOS or multitasking in general quickly *
|
||||
* + Looking for basic training, *
|
||||
* + Wanting to improve your FreeRTOS skills and productivity *
|
||||
* *
|
||||
* then take a look at the FreeRTOS eBook *
|
||||
* *
|
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
|
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
|
||||
* to your inbox within 20 minutes to two hours when purchased between 8am *
|
||||
* and 8pm GMT (although please allow up to 24 hours in case of *
|
||||
* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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|
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FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
***NOTE*** The exception to the GPL is included to allow you to distribute
|
||||
a combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
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critical systems.
|
||||
|
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http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
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*/
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#include "FreeRTOS.h"
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#include "task.h"
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#include "partest.h"
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#define mainFRQCR_VALUE ( 0x0303 ) /* Input = 12.5MHz, I Clock = 200MHz, B Clock = 50MHz, P Clock = 50MHz */
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void vApplicationMallocFailedHook( void );
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void vApplicationIdleHook( void );
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static void prvSetupHardware( void );
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/*-----------------------------------------------------------*/
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void main(void)
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{
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prvSetupHardware();
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vTaskStartScheduler();
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taskENABLE_INTERRUPTS();
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for( ;; );
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}
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/*-----------------------------------------------------------*/
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void vApplicationMallocFailedHook( void )
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{
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/* A call to vPortMalloc() failed, probably during the creation of a task,
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queue or semaphore. Inspect pxCurrentTCB to find which task is currently
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executing. */
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for( ;; );
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}
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/*-----------------------------------------------------------*/
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void vApplicationIdleHook( void )
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{
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/* Code can be added to the idle task here. This function must *NOT* attempt
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to block. Also, if the application uses the vTaskDelete() API function then
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this function must return regularly to ensure the idle task gets a chance to
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clean up the memory used by deleted tasks. */
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}
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/*-----------------------------------------------------------*/
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static void prvSetupHardware( void )
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{
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volatile unsigned long ul;
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for( ;; )
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/* Set the CPU and peripheral clocks. */
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CPG.FRQCR.WORD = mainFRQCR_VALUE;
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/* Wait for the clock to settle. */
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for( ul = 0; ul < 99; ul++ )
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{
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ul++;
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ul++;
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nop();
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}
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/* Initialise the ports used to toggle LEDs. */
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vParTestInitialise();
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}
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/*-----------------------------------------------------------*/
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void vApplicationSetupTimerInterrupt( void )
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{
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/* The peripheral clock is divided by 32 before feeding the compare match
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periphersl (CMT). */
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unsigned long ulCompareMatch = ( configPERIPHERAL_CLOCK_HZ / ( configTICK_RATE_HZ * 32 ) ) + 1;
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/* Configure a timer to create the RTOS tick interrupt. This example uses
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the compare match timer, but the multi function timer or possible even the
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watchdog timer could also be used. Ensure vPortTickInterrupt() is installed
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as the interrupt handler for whichever peripheral is used. */
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/* Turn the CMT on. */
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STB.CR4.BIT._CMT = 0;
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/* Set the compare match value for the required tick frequency. */
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CMT0.CMCOR = ( unsigned short ) ulCompareMatch;
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/* Divide the peripheral clock by 32. */
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CMT0.CMCSR.BIT.CKS = 0x01;
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/* Set the CMT interrupt priority - the interrupt priority must be
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configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to generate
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the tick interrupt. */
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INTC.IPR08.BIT._CMT0 = configKERNEL_INTERRUPT_PRIORITY;
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/* Clear the interrupt flag. */
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CMT0.CMCSR.BIT.CMF = 0;
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/* Enable the compare match interrupt. */
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CMT0.CMCSR.BIT.CMIE = 0x01;
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/* Start the timer. */
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CMT.CMSTR.BIT.STR0 = 0x01;
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}
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/*-----------------------------------------------------------*/
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//#pragma interrupt (vTempISR)
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//void vTempISR( void );
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void xINT_CMT_CMI0( void )
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{
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CMT0.CMCSR.BIT.CMF = 0;
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}
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@ -1,37 +1,902 @@
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/***********************************************************************/
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/* */
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/* FILE :vect.h */
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/* DATE :Sun, Dec 27, 2009 */
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/* DESCRIPTION :Definition of Vector */
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/* CPU TYPE :Other */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.16). */
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/* */
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/***********************************************************************/
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/******************************************************************************
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* DISCLAIMER
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*
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* This software is supplied by Renesas Technology Corp. and is only
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* intended for use with Renesas products. No other uses are authorized.
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*
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* This software is owned by Renesas Technology Corp. and is protected under
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* all applicable laws, including copyright laws.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
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* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
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* DISCLAIMED.
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*
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
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* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS
|
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* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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*
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* Renesas reserves the right, without notice, to make changes to this
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* software and to discontinue the availability of this software.
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* By using this software, you agree to the additional terms and
|
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* conditions found by accessing the following link:
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* http://www.renesas.com/disclaimer
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********************************************************************************
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* Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved.
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*""FILE COMMENT""*********** Technical reference data **************************
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* System Name : SH7216 Sample Program
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* File Name : vect.h
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* Abstract : Definition of Vector
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* Version : 0.02.00
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* Device : SH7216
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* Tool-Chain : High-performance Embedded Workshop (Ver.4.05.01).
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* : C/C++ compiler package for the SuperH RISC engine family
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* : (Ver.9.03 Release00).
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* OS : None
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* H/W Platform: R0K572167 (CPU board)
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* Description :
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********************************************************************************
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* History : Mar.30,2009 Ver.0.02.00
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*""FILE COMMENT END""**********************************************************/
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#ifndef VECT_H
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#define VECT_H
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//;<<VECTOR DATA START (POWER ON RESET)>>
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//;0 Power On Reset PC
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extern void PowerON_Reset_PC(void);
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// 0 Power On Reset PC
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extern void PowerON_Reset_PC(void);
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//;<<VECTOR DATA END (POWER ON RESET)>>
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// 1 Power On Reset SP
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//;<<VECTOR DATA START (MANUAL RESET)>>
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//;2 Manual Reset PC
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extern void Manual_Reset_PC(void);
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// 2 Manual Reset PC
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extern void Manual_Reset_PC(void);
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//;<<VECTOR DATA END (MANUAL RESET)>>
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// 3 Manual Reset SP
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// 4 Illegal code
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#pragma interrupt INT_Illegal_code
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extern void INT_Illegal_code(void);
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// 5 Reserved
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// 6 Illegal slot
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#pragma interrupt INT_Illegal_slot
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extern void INT_Illegal_slot(void);
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// 7 Reserved
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// 8 Reserved
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// 9 CPU Address error
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#pragma interrupt INT_CPU_Address
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extern void INT_CPU_Address(void);
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// 10 DMAC Address error
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#pragma interrupt INT_DMAC_Address
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extern void INT_DMAC_Address(void);
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// 11 NMI
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#pragma interrupt INT_NMI
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extern void INT_NMI(void);
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// 12 User breakpoint trap
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#pragma interrupt INT_User_Break
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extern void INT_User_Break(void);
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// 13 Reserved
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// 14 H-UDI
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#pragma interrupt INT_HUDI
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extern void INT_HUDI(void);
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// 15 Register bank over
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#pragma interrupt INT_Bank_Overflow
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extern void INT_Bank_Overflow(void);
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// 16 Register bank under
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#pragma interrupt INT_Bank_Underflow
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extern void INT_Bank_Underflow(void);
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// 17 ZERO_DIV
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#pragma interrupt INT_Divide_by_Zero
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extern void INT_Divide_by_Zero(void);
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// 18 OVER_DIV
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#pragma interrupt INT_Divide_Overflow
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extern void INT_Divide_Overflow(void);
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// 19 Reserved
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// 20 Reserved
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// 21 Reserved
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// 22 Reserved
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// 23 Reserved
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// 24 Reserved
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// 25 Reserved
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// 26 Reserved
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// 27 Reserved
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// 28 Reserved
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// 29 Reserved
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// 30 Reserved
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// 31 Reserved
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// 32 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA32
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extern void INT_TRAPA32(void);
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// 33 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA33
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extern void INT_TRAPA33(void);
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// 34 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA34
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extern void INT_TRAPA34(void);
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// 35 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA35
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extern void INT_TRAPA35(void);
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// 36 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA36
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extern void INT_TRAPA36(void);
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// 37 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA37
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extern void INT_TRAPA37(void);
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// 38 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA38
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extern void INT_TRAPA38(void);
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// 39 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA39
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extern void INT_TRAPA39(void);
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// 40 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA40
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extern void INT_TRAPA40(void);
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// 41 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA41
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extern void INT_TRAPA41(void);
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// 42 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA42
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extern void INT_TRAPA42(void);
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// 43 TRAPA (User Vecter)
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||||
#pragma interrupt INT_TRAPA43
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extern void INT_TRAPA43(void);
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|
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// 44 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA44
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extern void INT_TRAPA44(void);
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// 45 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA45
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extern void INT_TRAPA45(void);
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// 46 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA46
|
||||
extern void INT_TRAPA46(void);
|
||||
|
||||
// 47 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA47
|
||||
extern void INT_TRAPA47(void);
|
||||
|
||||
// 48 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA48
|
||||
extern void INT_TRAPA48(void);
|
||||
|
||||
// 49 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA49
|
||||
extern void INT_TRAPA49(void);
|
||||
|
||||
// 50 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA50
|
||||
extern void INT_TRAPA50(void);
|
||||
|
||||
// 51 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA51
|
||||
extern void INT_TRAPA51(void);
|
||||
|
||||
// 52 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA52
|
||||
extern void INT_TRAPA52(void);
|
||||
|
||||
// 53 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA53
|
||||
extern void INT_TRAPA53(void);
|
||||
|
||||
// 54 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA54
|
||||
extern void INT_TRAPA54(void);
|
||||
|
||||
// 55 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA55
|
||||
extern void INT_TRAPA55(void);
|
||||
|
||||
// 56 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA56
|
||||
extern void INT_TRAPA56(void);
|
||||
|
||||
// 57 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA57
|
||||
extern void INT_TRAPA57(void);
|
||||
|
||||
// 58 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA58
|
||||
extern void INT_TRAPA58(void);
|
||||
|
||||
// 59 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA59
|
||||
extern void INT_TRAPA59(void);
|
||||
|
||||
// 60 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA60
|
||||
extern void INT_TRAPA60(void);
|
||||
|
||||
// 61 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA61
|
||||
extern void INT_TRAPA61(void);
|
||||
|
||||
// 62 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA62
|
||||
extern void INT_TRAPA62(void);
|
||||
|
||||
// 63 TRAPA (User Vecter)
|
||||
#pragma interrupt INT_TRAPA63
|
||||
extern void INT_TRAPA63(void);
|
||||
|
||||
// 64 Interrupt IRQ0
|
||||
#pragma interrupt INT_IRQ0(resbank)
|
||||
extern void INT_IRQ0(void);
|
||||
|
||||
// 65 Interrupt IRQ1
|
||||
#pragma interrupt INT_IRQ1(resbank)
|
||||
extern void INT_IRQ1(void);
|
||||
|
||||
// 66 Interrupt IRQ2
|
||||
#pragma interrupt INT_IRQ2(resbank)
|
||||
extern void INT_IRQ2(void);
|
||||
|
||||
// 67 Interrupt IRQ3
|
||||
#pragma interrupt INT_IRQ3(resbank)
|
||||
extern void INT_IRQ3(void);
|
||||
|
||||
// 68 Interrupt IRQ4
|
||||
#pragma interrupt INT_IRQ4(resbank)
|
||||
extern void INT_IRQ4(void);
|
||||
|
||||
// 69 Interrupt IRQ5
|
||||
#pragma interrupt INT_IRQ5(resbank)
|
||||
extern void INT_IRQ5(void);
|
||||
|
||||
// 70 Interrupt IRQ6
|
||||
#pragma interrupt INT_IRQ6(resbank)
|
||||
extern void INT_IRQ6(void);
|
||||
|
||||
// 71 Interrupt IRQ7
|
||||
#pragma interrupt INT_IRQ7(resbank)
|
||||
extern void INT_IRQ7(void);
|
||||
|
||||
// 72 Reserved
|
||||
|
||||
// 73 Reserved
|
||||
|
||||
// 74 Reserved
|
||||
|
||||
// 75 Reserved
|
||||
|
||||
// 76 Reserved
|
||||
|
||||
// 77 Reserved
|
||||
|
||||
// 78 Reserved
|
||||
|
||||
// 79 Reserved
|
||||
|
||||
// 80 Interrupt PINT0
|
||||
#pragma interrupt INT_PINT0(resbank)
|
||||
extern void INT_PINT0(void);
|
||||
|
||||
// 81 Interrupt PINT1
|
||||
#pragma interrupt INT_PINT1(resbank)
|
||||
extern void INT_PINT1(void);
|
||||
|
||||
// 82 Interrupt PINT2
|
||||
#pragma interrupt INT_PINT2(resbank)
|
||||
extern void INT_PINT2(void);
|
||||
|
||||
// 83 Interrupt PINT3
|
||||
#pragma interrupt INT_PINT3(resbank)
|
||||
extern void INT_PINT3(void);
|
||||
|
||||
// 84 Interrupt PINT4
|
||||
#pragma interrupt INT_PINT4(resbank)
|
||||
extern void INT_PINT4(void);
|
||||
|
||||
// 85 Interrupt PINT5
|
||||
#pragma interrupt INT_PINT5(resbank)
|
||||
extern void INT_PINT5(void);
|
||||
|
||||
// 86 Interrupt PINT6
|
||||
#pragma interrupt INT_PINT6(resbank)
|
||||
extern void INT_PINT6(void);
|
||||
|
||||
// 87 Interrupt PINT7
|
||||
#pragma interrupt INT_PINT7(resbank)
|
||||
extern void INT_PINT7(void);
|
||||
|
||||
// 88 Reserved
|
||||
|
||||
// 89 Reserved
|
||||
|
||||
// 90 Reserved
|
||||
|
||||
// 91 ROM FIFE
|
||||
#pragma interrupt INT_ROM_FIFE(resbank)
|
||||
extern void INT_ROM_FIFE(void);
|
||||
|
||||
// 92 A/D ADI0
|
||||
#pragma interrupt INT_AD_ADI0(resbank)
|
||||
extern void INT_AD_ADI0(void);
|
||||
|
||||
// 93 Reserved
|
||||
|
||||
// 94 Reserved
|
||||
|
||||
// 95 Reserved
|
||||
|
||||
// 96 A/D ADI1
|
||||
#pragma interrupt INT_AD_ADI1(resbank)
|
||||
extern void INT_AD_ADI1(void);
|
||||
|
||||
// 97 Reserved
|
||||
|
||||
// 98 Reserved
|
||||
|
||||
// 99 Reserved
|
||||
|
||||
// 100 Reserved
|
||||
|
||||
// 101 Reserved
|
||||
|
||||
// 102 Reserved
|
||||
|
||||
// 103 Reserved
|
||||
|
||||
// 104 RCANET0 ERS_0
|
||||
#pragma interrupt INT_RCANET0_ERS_0
|
||||
extern void INT_RCANET0_ERS_0(void);
|
||||
|
||||
// 105 RCANET0 OVR_0
|
||||
#pragma interrupt INT_RCANET0_OVR_0
|
||||
extern void INT_RCANET0_OVR_0(void);
|
||||
|
||||
// 106 RCANET0 RM01_0
|
||||
#pragma interrupt INT_RCANET0_RM01_0
|
||||
extern void INT_RCANET0_RM01_0(void);
|
||||
|
||||
// 107 RCANET0 SLE_0
|
||||
#pragma interrupt INT_RCANET0_SLE_0
|
||||
extern void INT_RCANET0_SLE_0(void);
|
||||
|
||||
// 108 DMAC0 DEI0
|
||||
#pragma interrupt INT_DMAC0_DEI0(resbank)
|
||||
extern void INT_DMAC0_DEI0(void);
|
||||
|
||||
// 109 DMAC0 HEI0
|
||||
#pragma interrupt INT_DMAC0_HEI0(resbank)
|
||||
extern void INT_DMAC0_HEI0(void);
|
||||
|
||||
// 110 Reserved
|
||||
|
||||
// 111 Reserved
|
||||
|
||||
// 112 DMAC1 DEI1
|
||||
#pragma interrupt INT_DMAC1_DEI1(resbank)
|
||||
extern void INT_DMAC1_DEI1(void);
|
||||
|
||||
// 113 DMAC1 HEI1
|
||||
#pragma interrupt INT_DMAC1_HEI1(resbank)
|
||||
extern void INT_DMAC1_HEI1(void);
|
||||
|
||||
// 114 Reserved
|
||||
|
||||
// 115 Reserved
|
||||
|
||||
// 116 DMAC2 DEI2
|
||||
#pragma interrupt INT_DMAC2_DEI2(resbank)
|
||||
extern void INT_DMAC2_DEI2(void);
|
||||
|
||||
// 117 DMAC2 HEI2
|
||||
#pragma interrupt INT_DMAC2_HEI2(resbank)
|
||||
extern void INT_DMAC2_HEI2(void);
|
||||
|
||||
// 118 Reserved
|
||||
|
||||
// 119 Reserved
|
||||
|
||||
// 120 DMAC3 DEI3
|
||||
#pragma interrupt INT_DMAC3_DEI3(resbank)
|
||||
extern void INT_DMAC3_DEI3(void);
|
||||
|
||||
// 121 DMAC3 HEI3
|
||||
#pragma interrupt INT_DMAC3_HEI3(resbank)
|
||||
extern void INT_DMAC3_HEI3(void);
|
||||
|
||||
// 122 Reserved
|
||||
|
||||
// 123 Reserved
|
||||
|
||||
// 124 DMAC4 DEI4
|
||||
#pragma interrupt INT_DMAC4_DEI4(resbank)
|
||||
extern void INT_DMAC4_DEI4(void);
|
||||
|
||||
// 125 DMAC4 HEI4
|
||||
#pragma interrupt INT_DMAC4_HEI4(resbank)
|
||||
extern void INT_DMAC4_HEI4(void);
|
||||
|
||||
// 126 Reserved
|
||||
|
||||
// 127 Reserved
|
||||
|
||||
// 128 DMAC5 DEI5
|
||||
#pragma interrupt INT_DMAC5_DEI5(resbank)
|
||||
extern void INT_DMAC5_DEI5(void);
|
||||
|
||||
// 129 DMAC5 HEI5
|
||||
#pragma interrupt INT_DMAC5_HEI5(resbank)
|
||||
extern void INT_DMAC5_HEI5(void);
|
||||
|
||||
// 130 Reserved
|
||||
|
||||
// 131 Reserved
|
||||
|
||||
// 132 DMAC6 DEI6
|
||||
#pragma interrupt INT_DMAC6_DEI6(resbank)
|
||||
extern void INT_DMAC6_DEI6(void);
|
||||
|
||||
// 133 DMAC6 HEI6
|
||||
#pragma interrupt INT_DMAC6_HEI6(resbank)
|
||||
extern void INT_DMAC6_HEI6(void);
|
||||
|
||||
// 134 Reserved
|
||||
|
||||
// 135 Reserved
|
||||
|
||||
// 136 DMAC7 DEI7
|
||||
#pragma interrupt INT_DMAC7_DEI7(resbank)
|
||||
extern void INT_DMAC7_DEI7(void);
|
||||
|
||||
// 137 DMAC7 HEI7
|
||||
#pragma interrupt INT_DMAC7_HEI7(resbank)
|
||||
extern void INT_DMAC7_HEI7(void);
|
||||
|
||||
// 138 Reserved
|
||||
|
||||
// 139 Reserved
|
||||
|
||||
// 140 CMT CMI0
|
||||
#pragma interrupt INT_CMT_CMI0(resbank)
|
||||
extern void INT_CMT_CMI0(void);
|
||||
|
||||
// 141 Reserved
|
||||
|
||||
// 142 Reserved
|
||||
|
||||
// 143 Reserved
|
||||
|
||||
// 144 CMT CMI1
|
||||
#pragma interrupt INT_CMT_CMI1(resbank)
|
||||
extern void INT_CMT_CMI1(void);
|
||||
|
||||
// 145 Reserved
|
||||
|
||||
// 146 Reserved
|
||||
|
||||
// 147 Reserved
|
||||
|
||||
// 148 BSC CMTI
|
||||
#pragma interrupt INT_BSC_CMTI(resbank)
|
||||
extern void INT_BSC_CMTI(void);
|
||||
|
||||
// 149 Reserved
|
||||
|
||||
// 150 USB EP4FULL
|
||||
#pragma interrupt INT_USB_EP4FULL(resbank)
|
||||
extern void INT_USB_EP4FULL(void);
|
||||
|
||||
// 151 USB EP5EMPTY
|
||||
#pragma interrupt INT_USB_EP5EMPTY(resbank)
|
||||
extern void INT_USB_EP5EMPTY(void);
|
||||
|
||||
// 152 WDT ITI
|
||||
#pragma interrupt INT_WDT_ITI(resbank)
|
||||
extern void INT_WDT_ITI(void);
|
||||
|
||||
// 153 E-DMAC EINT0
|
||||
#pragma interrupt INT_EDMAC_EINT0(resbank)
|
||||
extern void INT_EDMAC_EINT0(void);
|
||||
|
||||
// 154 USB EP1FULL
|
||||
#pragma interrupt INT_USB_EP1FULL(resbank)
|
||||
extern void INT_USB_EP1FULL(void);
|
||||
|
||||
// 155 USB EP2EMPTY
|
||||
#pragma interrupt INT_USB_EP2EMPTY(resbank)
|
||||
extern void INT_USB_EP2EMPTY(void);
|
||||
|
||||
// 156 MTU2 MTU0 TGI0A
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0A(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0A(void);
|
||||
|
||||
// 157 MTU2 MTU0 TGI0B
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0B(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0B(void);
|
||||
|
||||
// 158 MTU2 MTU0 TGI0C
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0C(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0C(void);
|
||||
|
||||
// 159 MTU2 MTU0 TGI0D
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0D(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0D(void);
|
||||
|
||||
// 160 MTU2 MTU0 TGI0V
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0V(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0V(void);
|
||||
|
||||
// 161 MTU2 MTU0 TGI0E
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0E(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0E(void);
|
||||
|
||||
// 162 MTU2 MTU0 TGI0F
|
||||
#pragma interrupt INT_MTU2_MTU0_TGI0F(resbank)
|
||||
extern void INT_MTU2_MTU0_TGI0F(void);
|
||||
|
||||
// 163 Reserved
|
||||
|
||||
// 164 MTU2 MTU1 TGI1A
|
||||
#pragma interrupt INT_MTU2_MTU1_TGI1A(resbank)
|
||||
extern void INT_MTU2_MTU1_TGI1A(void);
|
||||
|
||||
// 165 MTU2 MTU1 TGI1B
|
||||
#pragma interrupt INT_MTU2_MTU1_TGI1B(resbank)
|
||||
extern void INT_MTU2_MTU1_TGI1B(void);
|
||||
|
||||
// 166 Reserved
|
||||
|
||||
// 167 Reserved
|
||||
|
||||
// 168 MTU2 MTU1 TGI1V
|
||||
#pragma interrupt INT_MTU2_MTU1_TGI1V(resbank)
|
||||
extern void INT_MTU2_MTU1_TGI1V(void);
|
||||
|
||||
// 169 MTU2 MTU1 TGI1U
|
||||
#pragma interrupt INT_MTU2_MTU1_TGI1U(resbank)
|
||||
extern void INT_MTU2_MTU1_TGI1U(void);
|
||||
|
||||
// 170 Reserved
|
||||
|
||||
// 171 Reserved
|
||||
|
||||
// 172 MTU2 MTU2 TGI2A
|
||||
#pragma interrupt INT_MTU2_MTU2_TGI2A(resbank)
|
||||
extern void INT_MTU2_MTU2_TGI2A(void);
|
||||
|
||||
// 173 MTU2 MTU2 TGI2B
|
||||
#pragma interrupt INT_MTU2_MTU2_TGI2B(resbank)
|
||||
extern void INT_MTU2_MTU2_TGI2B(void);
|
||||
|
||||
// 174 Reserved
|
||||
|
||||
// 175 Reserved
|
||||
|
||||
// 176 MTU2 MTU2 TGI2V
|
||||
#pragma interrupt INT_MTU2_MTU2_TGI2V(resbank)
|
||||
extern void INT_MTU2_MTU2_TGI2V(void);
|
||||
|
||||
// 177 MTU2 MTU2 TGI2U
|
||||
#pragma interrupt INT_MTU2_MTU2_TGI2U(resbank)
|
||||
extern void INT_MTU2_MTU2_TGI2U(void);
|
||||
|
||||
// 178 Reserved
|
||||
|
||||
// 179 Reserved
|
||||
|
||||
// 180 MTU2 MTU3 TGI3A
|
||||
#pragma interrupt INT_MTU2_MTU3_TGI3A(resbank)
|
||||
extern void INT_MTU2_MTU3_TGI3A(void);
|
||||
|
||||
// 181 MTU2 MTU3 TGI3B
|
||||
#pragma interrupt INT_MTU2_MTU3_TGI3B(resbank)
|
||||
extern void INT_MTU2_MTU3_TGI3B(void);
|
||||
|
||||
// 182 MTU2 MTU3 TGI3C
|
||||
#pragma interrupt INT_MTU2_MTU3_TGI3C(resbank)
|
||||
extern void INT_MTU2_MTU3_TGI3C(void);
|
||||
|
||||
// 183 MTU2 MTU3 TGI3D
|
||||
#pragma interrupt INT_MTU2_MTU3_TGI3D(resbank)
|
||||
extern void INT_MTU2_MTU3_TGI3D(void);
|
||||
|
||||
// 184 MTU2 MTU3 TGI3V
|
||||
#pragma interrupt INT_MTU2_MTU3_TGI3V(resbank)
|
||||
extern void INT_MTU2_MTU3_TGI3V(void);
|
||||
|
||||
// 185 Reserved
|
||||
|
||||
// 186 Reserved
|
||||
|
||||
// 187 Reserved
|
||||
|
||||
// 188 MTU2 MTU4 TGI4A
|
||||
#pragma interrupt INT_MTU2_MTU4_TGI4A(resbank)
|
||||
extern void INT_MTU2_MTU4_TGI4A(void);
|
||||
|
||||
// 189 MTU2 MTU4 TGI4B
|
||||
#pragma interrupt INT_MTU2_MTU4_TGI4B(resbank)
|
||||
extern void INT_MTU2_MTU4_TGI4B(void);
|
||||
|
||||
// 190 MTU2 MTU4 TGI4C
|
||||
#pragma interrupt INT_MTU2_MTU4_TGI4C(resbank)
|
||||
extern void INT_MTU2_MTU4_TGI4C(void);
|
||||
|
||||
// 191 MTU2 MTU4 TGI4D
|
||||
#pragma interrupt INT_MTU2_MTU4_TGI4D(resbank)
|
||||
extern void INT_MTU2_MTU4_TGI4D(void);
|
||||
|
||||
// 192 MTU2 MTU4 TGI4V
|
||||
#pragma interrupt INT_MTU2_MTU4_TGI4V(resbank)
|
||||
extern void INT_MTU2_MTU4_TGI4V(void);
|
||||
|
||||
// 193 Reserved
|
||||
|
||||
// 194 Reserved
|
||||
|
||||
// 195 Reserved
|
||||
|
||||
// 196 MTU2 MTU5 TGI5U
|
||||
#pragma interrupt INT_MTU2_MTU5_TGI5U(resbank)
|
||||
extern void INT_MTU2_MTU5_TGI5U(void);
|
||||
|
||||
// 197 MTU2 MTU5 TGI5V
|
||||
#pragma interrupt INT_MTU2_MTU5_TGI5V(resbank)
|
||||
extern void INT_MTU2_MTU5_TGI5V(void);
|
||||
|
||||
// 198 MTU2 MTU5 TGI5W
|
||||
#pragma interrupt INT_MTU2_MTU5_TGI5W(resbank)
|
||||
extern void INT_MTU2_MTU5_TGI5W(void);
|
||||
|
||||
// 199 Reserved
|
||||
|
||||
// 200 POE2 OEI1
|
||||
#pragma interrupt INT_POE2_OEI1(resbank)
|
||||
extern void INT_POE2_OEI1(void);
|
||||
|
||||
// 201 POE2 OEI2
|
||||
#pragma interrupt INT_POE2_OEI2(resbank)
|
||||
extern void INT_POE2_OEI2(void);
|
||||
|
||||
// 202 Reserved
|
||||
|
||||
// 203 Reserved
|
||||
|
||||
// 204 MTU2S MTU3S TGI3A
|
||||
#pragma interrupt INT_MTU2S_MTU3S_TGI3A(resbank)
|
||||
extern void INT_MTU2S_MTU3S_TGI3A(void);
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||||
|
||||
// 205 MTU2S MTU3S TGI3B
|
||||
#pragma interrupt INT_MTU2S_MTU3S_TGI3B(resbank)
|
||||
extern void INT_MTU2S_MTU3S_TGI3B(void);
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||||
|
||||
// 206 MTU2S MTU3S TGI3C
|
||||
#pragma interrupt INT_MTU2S_MTU3S_TGI3C(resbank)
|
||||
extern void INT_MTU2S_MTU3S_TGI3C(void);
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||||
|
||||
// 207 MTU2S MTU3S TGI3D
|
||||
#pragma interrupt INT_MTU2S_MTU3S_TGI3D(resbank)
|
||||
extern void INT_MTU2S_MTU3S_TGI3D(void);
|
||||
|
||||
// 208 MTU2S MTU3S TGI3V
|
||||
#pragma interrupt INT_MTU2S_MTU3S_TGI3V(resbank)
|
||||
extern void INT_MTU2S_MTU3S_TGI3V(void);
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||||
|
||||
// 209 Reserved
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||||
|
||||
// 210 Reserved
|
||||
|
||||
// 211 Reserved
|
||||
|
||||
// 212 MTU2S MTU4S TGI4A
|
||||
#pragma interrupt INT_MTU2S_MTU4S_TGI4A(resbank)
|
||||
extern void INT_MTU2S_MTU4S_TGI4A(void);
|
||||
|
||||
// 213 MTU2S MTU4S TGI4B
|
||||
#pragma interrupt INT_MTU2S_MTU4S_TGI4B(resbank)
|
||||
extern void INT_MTU2S_MTU4S_TGI4B(void);
|
||||
|
||||
// 214 MTU2S MTU4S TGI4C
|
||||
#pragma interrupt INT_MTU2S_MTU4S_TGI4C(resbank)
|
||||
extern void INT_MTU2S_MTU4S_TGI4C(void);
|
||||
|
||||
// 215 MTU2S MTU4S TGI4D
|
||||
#pragma interrupt INT_MTU2S_MTU4S_TGI4D(resbank)
|
||||
extern void INT_MTU2S_MTU4S_TGI4D(void);
|
||||
|
||||
// 216 MTU2S MTU4S TGI4V
|
||||
#pragma interrupt INT_MTU2S_MTU4S_TGI4V(resbank)
|
||||
extern void INT_MTU2S_MTU4S_TGI4V(void);
|
||||
|
||||
// 217 Reserved
|
||||
|
||||
// 218 Reserved
|
||||
|
||||
// 219 Reserved
|
||||
|
||||
// 220 MTU2S MTU5S TGI5U
|
||||
#pragma interrupt INT_MTU2S_MTU5S_TGI5U(resbank)
|
||||
extern void INT_MTU2S_MTU5S_TGI5U(void);
|
||||
|
||||
// 221 MTU2S MTU5S TGI5V
|
||||
#pragma interrupt INT_MTU2S_MTU5S_TGI5V(resbank)
|
||||
extern void INT_MTU2S_MTU5S_TGI5V(void);
|
||||
|
||||
// 222 MTU2S MTU5S TGI5W
|
||||
#pragma interrupt INT_MTU2S_MTU5S_TGI5W(resbank)
|
||||
extern void INT_MTU2S_MTU5S_TGI5W(void);
|
||||
|
||||
// 223 Reserved
|
||||
|
||||
// 224 POE2 OEI3
|
||||
#pragma interrupt INT_POE2_OEI3(resbank)
|
||||
extern void INT_POE2_OEI3(void);
|
||||
|
||||
// 225 Reserved
|
||||
|
||||
// 226 USB USI0
|
||||
#pragma interrupt INT_USB_USI0(resbank)
|
||||
extern void INT_USB_USI0(void);
|
||||
|
||||
// 227 USB USI1
|
||||
#pragma interrupt INT_USB_USI1(resbank)
|
||||
extern void INT_USB_USI1(void);
|
||||
|
||||
// 228 IIC3 STPI
|
||||
#pragma interrupt INT_IIC3_STPI(resbank)
|
||||
extern void INT_IIC3_STPI(void);
|
||||
|
||||
// 229 IIC3 NAKI
|
||||
#pragma interrupt INT_IIC3_NAKI(resbank)
|
||||
extern void INT_IIC3_NAKI(void);
|
||||
|
||||
// 230 IIC3 RXI
|
||||
#pragma interrupt INT_IIC3_RXI(resbank)
|
||||
extern void INT_IIC3_RXI(void);
|
||||
|
||||
// 231 IIC3 TXI
|
||||
#pragma interrupt INT_IIC3_TXI(resbank)
|
||||
extern void INT_IIC3_TXI(void);
|
||||
|
||||
// 232 IIC3 TEI
|
||||
#pragma interrupt INT_IIC3_TEI(resbank)
|
||||
extern void INT_IIC3_TEI(void);
|
||||
|
||||
// 233 RSPI SPERI
|
||||
#pragma interrupt INT_RSPI_SPERI(resbank)
|
||||
extern void INT_RSPI_SPERI(void);
|
||||
|
||||
// 234 RSPI SPRXI
|
||||
#pragma interrupt INT_RSPI_SPRXI(resbank)
|
||||
extern void INT_RSPI_SPRXI(void);
|
||||
|
||||
// 235 RSPI SPTXI
|
||||
#pragma interrupt INT_RSPI_SPTXI(resbank)
|
||||
extern void INT_RSPI_SPTXI(void);
|
||||
|
||||
// 236 SCI SCI4 ERI4
|
||||
#pragma interrupt INT_SCI_SCI4_ERI4(resbank)
|
||||
extern void INT_SCI_SCI4_ERI4(void);
|
||||
|
||||
// 237 SCI SCI4 RXI4
|
||||
#pragma interrupt INT_SCI_SCI4_RXI4(resbank)
|
||||
extern void INT_SCI_SCI4_RXI4(void);
|
||||
|
||||
// 238 SCI SCI4 TXI4
|
||||
#pragma interrupt INT_SCI_SCI4_TXI4(resbank)
|
||||
extern void INT_SCI_SCI4_TXI4(void);
|
||||
|
||||
// 239 SCI SCI4 TEI4
|
||||
#pragma interrupt INT_SCI_SCI4_TEI4(resbank)
|
||||
extern void INT_SCI_SCI4_TEI4(void);
|
||||
|
||||
// 240 SCI SCI0 ERI0
|
||||
#pragma interrupt INT_SCI_SCI0_ERI0(resbank)
|
||||
extern void INT_SCI_SCI0_ERI0(void);
|
||||
|
||||
// 241 SCI SCI0 RXI0
|
||||
#pragma interrupt INT_SCI_SCI0_RXI0(resbank)
|
||||
extern void INT_SCI_SCI0_RXI0(void);
|
||||
|
||||
// 242 SCI SCI0 TXI0
|
||||
#pragma interrupt INT_SCI_SCI0_TXI0(resbank)
|
||||
extern void INT_SCI_SCI0_TXI0(void);
|
||||
|
||||
// 243 SCI SCI0 TEI0
|
||||
#pragma interrupt INT_SCI_SCI0_TEI0(resbank)
|
||||
extern void INT_SCI_SCI0_TEI0(void);
|
||||
|
||||
// 244 SCI SCI1 ERI1
|
||||
#pragma interrupt INT_SCI_SCI1_ERI1(resbank)
|
||||
extern void INT_SCI_SCI1_ERI1(void);
|
||||
|
||||
// 245 SCI SCI1 RXI1
|
||||
#pragma interrupt INT_SCI_SCI1_RXI1(resbank)
|
||||
extern void INT_SCI_SCI1_RXI1(void);
|
||||
|
||||
// 246 SCI SCI1 TXI1
|
||||
#pragma interrupt INT_SCI_SCI1_TXI1(resbank)
|
||||
extern void INT_SCI_SCI1_TXI1(void);
|
||||
|
||||
// 247 SCI SCI1 TEI1
|
||||
#pragma interrupt INT_SCI_SCI1_TEI1(resbank)
|
||||
extern void INT_SCI_SCI1_TEI1(void);
|
||||
|
||||
// 248 SCI SCI2 ERI2
|
||||
#pragma interrupt INT_SCI_SCI2_ERI2(resbank)
|
||||
extern void INT_SCI_SCI2_ERI2(void);
|
||||
|
||||
// 249 SCI SCI2 RXI2
|
||||
#pragma interrupt INT_SCI_SCI2_RXI2(resbank)
|
||||
extern void INT_SCI_SCI2_RXI2(void);
|
||||
|
||||
// 250 SCI SCI2 TXI2
|
||||
#pragma interrupt INT_SCI_SCI2_TXI2(resbank)
|
||||
extern void INT_SCI_SCI2_TXI2(void);
|
||||
|
||||
// 251 SCI SCI2 TEI2
|
||||
#pragma interrupt INT_SCI_SCI2_TEI2(resbank)
|
||||
extern void INT_SCI_SCI2_TEI2(void);
|
||||
|
||||
// 252 SCIF SCIF3 BRI3
|
||||
#pragma interrupt INT_SCIF_SCIF3_BRI3(resbank)
|
||||
extern void INT_SCIF_SCIF3_BRI3(void);
|
||||
|
||||
// 253 SCIF SCIF3 ERI3
|
||||
#pragma interrupt INT_SCIF_SCIF3_ERI3(resbank)
|
||||
extern void INT_SCIF_SCIF3_ERI3(void);
|
||||
|
||||
// 254 SCIF SCIF3 RXI3
|
||||
#pragma interrupt INT_SCIF_SCIF3_RXI3(resbank)
|
||||
extern void INT_SCIF_SCIF3_RXI3(void);
|
||||
|
||||
// 255 SCIF SCIF3 TXI3
|
||||
#pragma interrupt INT_SCIF_SCIF3_TXI3(resbank)
|
||||
extern void INT_SCIF_SCIF3_TXI3(void);
|
||||
|
||||
// Dummy
|
||||
#pragma interrupt Dummy
|
||||
#pragma interrupt Dummy(resbank)
|
||||
extern void Dummy(void);
|
||||
|
||||
#endif /* VECT_H */
|
||||
|
||||
/* End of File */
|
||||
|
||||
Loading…
Reference in New Issue