diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject
index 393dc4ad67..b6ac7fa6a4 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject
@@ -48,7 +48,6 @@
-
@@ -92,7 +91,7 @@
-
+
@@ -144,8 +143,11 @@
+
+
+
-
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project
index dd91917029..46213b5457 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project
@@ -42,6 +42,15 @@
+
+ 1442133034715
+ System
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-GCC
+
+ 1440591358527src/FreeRTOS_Source/portable
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm
index 3d80adf6ee..3725c0cf07 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm
@@ -44,7 +44,6 @@
.code 32
.global undefined_handler
- .global FreeRTOS_SVC_Handler
.global prefetch_handler
.global abort_handler
.global reserved_handler
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/ascii.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/ascii.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/lcd_pmod.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/lcd_pmod.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/logo_data.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/logo_data.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_atcm_init.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_bsc.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_ram_init.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_reset.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_system.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_typedefs.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/siochar.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/siochar.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_atcm_init.c
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_ram_init.c
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_reset.c
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c
index 9c21394e5e..60fc61523b 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_reset.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c
@@ -75,14 +75,14 @@ Private variables and functions
***********************************************************************************************************************/
-/***********************************************************************************************************************
+/*******************************************************************************
* Function Name : r_rst_write_enable
* Description : Enables writing to the registers related to RESET and Low-
* Power function. And dummy read the register in order to fix
* the register value.
* Arguments : none
* Return Value : none
-***********************************************************************************************************************/
+*******************************************************************************/
void r_rst_write_enable(void)
{
volatile uint32_t dummy=0;
@@ -95,18 +95,18 @@ void r_rst_write_enable(void)
}
-/***********************************************************************************************************************
+/*******************************************************************************
End of function r_rst_write_enable
-***********************************************************************************************************************/
+*******************************************************************************/
-/***********************************************************************************************************************
+/*******************************************************************************
* Function Name : r_rst_write_disable
* Description : Disables writing to the registers related to RESET and Low-
* Power function. And dummy read the register in order to fix
* the register value.
* Arguments : none
* Return Value : none
-***********************************************************************************************************************/
+*******************************************************************************/
void r_rst_write_disable(void)
{
volatile uint32_t dummy=0;
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/syscalls.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/syscalls.c
deleted file mode 100644
index d4eabd0e8e..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/syscalls.c
+++ /dev/null
@@ -1,717 +0,0 @@
-/* Support files for GNU libc. Files in the system namespace go here.
- Files in the C namespace (ie those that do not start with an
- underscore) go in .c. */
-
-#include <_ansi.h>
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "r_typedefs.h"
-#include "siochar.h"
-#include "swi.h"
-
-
-#ifndef NULL
-#define NULL (0)
-#endif
-
-/* Forward prototypes. */
-int _system _PARAMS ((const char *));
-int _rename _PARAMS ((const char *, const char *));
-int _isatty _PARAMS ((int));
-clock_t _times _PARAMS ((struct tms *));
-int _gettimeofday _PARAMS ((struct timeval *, void *));
-void _raise _PARAMS ((void));
-int _unlink _PARAMS ((const char *));
-int _link _PARAMS ((void));
-int _stat _PARAMS ((const char *, struct stat *));
-int _fstat _PARAMS ((int, struct stat *));
-caddr_t _sbrk _PARAMS ((int));
-int _getpid _PARAMS ((int));
-int _kill _PARAMS ((int, int));
-void _exit _PARAMS ((int));
-int _close _PARAMS ((int));
-int _swiclose _PARAMS ((int));
-int _open _PARAMS ((const char *, int, ...));
-int _swiopen _PARAMS ((const char *, int));
-int _write _PARAMS ((int, const char *, unsigned int));
-
-int _swiwrite _PARAMS ((int, char *, int));
-int _lseek _PARAMS ((int, int, int));
-int _swilseek _PARAMS ((int, int, int));
-int _read _PARAMS ((int, char *, unsigned int));
-
-int _swiread _PARAMS ((int, char *, int));
-void initialise_monitor_handles _PARAMS ((void));
-
-static int wrap _PARAMS ((int));
-static int error _PARAMS ((int));
-static int get_errno _PARAMS ((void));
-static int remap_handle _PARAMS ((int));
-
-#ifdef ARM_RDI_MONITOR
-static int do_AngelSWI _PARAMS ((int, void *));
-#endif
-
-static int findslot _PARAMS ((int));
-
-/* Register name faking - works in collusion with the linker. */
-register char * stack_ptr __asm ("sp");
-
-
-/* following is copied from libc/stdio/local.h to check std streams */
-extern void _EXFUN(__sinit,(struct _reent *));
-#define CHECK_INIT(ptr) \
- do \
- { \
- if ((ptr) && !(ptr)->__sdidinit) \
- __sinit (ptr); \
- } \
- while (0)
-
-/* Adjust our internal handles to stay away from std* handles. */
-#define FILE_HANDLE_OFFSET (0x20)
-
-static int monitor_stdin;
-static int monitor_stdout;
-static int monitor_stderr;
-
-/* Struct used to keep track of the file position, just so we
- can implement fseek(fh,x,SEEK_CUR). */
-typedef struct
-{
- int handle;
- int pos;
-}
-poslog;
-
-#define MAX_OPEN_FILES (20)
-static poslog openfiles [MAX_OPEN_FILES];
-
-static int
-findslot (int fh)
-{
- int i;
- for (i = 0; i < MAX_OPEN_FILES; i ++)
- if (openfiles[i].handle == fh)
- {
- break;
- }
- return (i);
-}
-
-#ifdef ARM_RDI_MONITOR
-
-static inline int
-do_AngelSWI (int reason, void * arg)
-{
- int value;
- asm volatile ("mov r0, %1; mov r1, %2; " AngelSWIInsn " %a3; mov %0, r0"
- : "=r" (value) /* Outputs */
- : "r" (reason), "r" (arg), "i" (AngelSWI) /* Inputs */
- : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
- /* Clobbers r0 and r1, and lr if in supervisor mode */);
- /* Accordingly to page 13-77 of ARM DUI 0040D other registers
- can also be clobbered. Some memory positions may also be
- changed by a system call, so they should not be kept in
- registers. Note: we are assuming the manual is right and
- Angel is respecting the APCS. */
- return value;
-}
-#endif /* ARM_RDI_MONITOR */
-
-/* Function to convert std(in|out|err) handles to internal versions. */
-static int
-remap_handle (int fh)
-{
- CHECK_INIT(_REENT);
-
- if (STDIN_FILENO == fh)
- {
- return (monitor_stdin);
- }
- if (STDOUT_FILENO == fh)
- {
- return (monitor_stdout);
- }
- if (STDERR_FILENO == fh)
- {
- return (monitor_stderr);
- }
-
- return (fh - FILE_HANDLE_OFFSET);
-}
-
-void
-initialise_monitor_handles (void)
-{
- int i;
-
-#ifdef ARM_RDI_MONITOR
- int volatile block[3];
-
- block[0] = (int) ":tt";
- block[2] = 3; /* length of filename */
- block[1] = 0; /* mode "r" */
- monitor_stdin = do_AngelSWI (AngelSWI_Reason_Open, (void *) block);
-
- block[0] = (int) ":tt";
- block[2] = 3; /* length of filename */
- block[1] = 4; /* mode "w" */
- monitor_stdout = monitor_stderr = do_AngelSWI (AngelSWI_Reason_Open, (void *) block);
-#else
- int fh;
- const char * pname;
-
- pname = ":tt";
- __asm ("mov r0,%2; mov r1, #0; swi %a1; mov %0, r0"
- : "=r"(fh)
- : "i" (SWI_Open),"r"(pname)
- : "r0","r1");
- monitor_stdin = fh;
-
- pname = ":tt";
- __asm ("mov r0,%2; mov r1, #4; swi %a1; mov %0, r0"
- : "=r"(fh)
- : "i" (SWI_Open),"r"(pname)
- : "r0","r1");
- monitor_stdout = (monitor_stderr = fh);
-#endif
-
- for (i = 0; i < MAX_OPEN_FILES; i ++)
- {
- openfiles[i].handle = (-1);
- }
-
- openfiles[0].handle = monitor_stdin;
- openfiles[0].pos = 0;
- openfiles[1].handle = monitor_stdout;
- openfiles[1].pos = 0;
-}
-
-static int
-get_errno (void)
-{
-#ifdef ARM_RDI_MONITOR
- return do_AngelSWI (AngelSWI_Reason_Errno, NULL);
-#else
- __asm ("swi %a0" :: "i" (SWI_GetErrno));
- return (0);
-#endif
-}
-
-static int
-error (int result)
-{
- errno = get_errno ();
- return (result);
-}
-
-static int
-wrap (int result)
-{
- if ((-1) == result)
- {
- return (error(-1));
- }
- return (result);
-}
-
-/* Returns # chars not! written. */
-int
-_swiread (int file,
- char * ptr,
- int len)
-{
- int fh = remap_handle (file);
-#ifdef ARM_RDI_MONITOR
- int block[3];
-
- block[0] = fh;
- block[1] = (int) ptr;
- block[2] = len;
-
- return do_AngelSWI (AngelSWI_Reason_Read, block);
-#else
- __asm ("mov r0, %1; mov r1, %2;mov r2, %3; swi %a0"
- : /* No outputs */
- : "i"(SWI_Read), "r"(fh), "r"(ptr), "r"(len)
- : "r0","r1","r2");
- return (0);
-#endif
-}
-
-/******************************************************************************
-* Function Name: _read
-* Description : GNU interface to low-level I/O read
-* Arguments : int file_no
-* : const char *buffer
-* : unsigned int n
-* Return Value : none
-******************************************************************************/
-int _read(int file_no , char *buffer , unsigned int n)
-{
- return (sio_read(file_no , buffer , n));
-}
-
-int
-_swilseek (int file,
- int ptr,
- int dir)
-{
- int res;
- int fh = remap_handle (file);
- int slot = findslot (fh);
-#ifdef ARM_RDI_MONITOR
- int block[2];
-#endif
-
- if (SEEK_CUR == dir)
- {
- if (MAX_OPEN_FILES == slot)
- {
- return (-1);
- }
- ptr = (openfiles[slot].pos + ptr);
- dir = SEEK_SET;
- }
-
-#ifdef ARM_RDI_MONITOR
- if (dir == SEEK_END)
- {
- block[0] = fh;
- ptr += do_AngelSWI (AngelSWI_Reason_FLen, block);
- }
-
- /* This code only does absolute seeks. */
- block[0] = remap_handle (file);
- block[1] = ptr;
- res = do_AngelSWI (AngelSWI_Reason_Seek, block);
-#else
- if (SEEK_END == dir)
- {
- __asm ("mov r0, %2; swi %a1; mov %0, r0"
- : "=r" (res)
- : "i" (SWI_Flen), "r" (fh)
- : "r0");
- ptr += res;
- }
-
- /* This code only does absolute seeks. */
- __asm ("mov r0, %2; mov r1, %3; swi %a1; mov %0, r0"
- : "=r" (res)
- : "i" (SWI_Seek), "r" (fh), "r" (ptr)
- : "r0", "r1");
-#endif
-
- if ((MAX_OPEN_FILES != slot) && (0 == res))
- {
- openfiles[slot].pos = ptr;
- }
-
- /* This is expected to return the position in the file. */
- return ((0 == res) ? ptr : (-1));
-}
-
-int
-_lseek (int file,
- int ptr,
- int dir)
-{
- return (wrap (_swilseek (file, ptr, dir)));
-}
-
-/* Returns #chars not! written. */
-int
-_swiwrite (
- int file,
- char * ptr,
- int len)
-{
- int fh = remap_handle (file);
-#ifdef ARM_RDI_MONITOR
- int block[3];
-
- block[0] = fh;
- block[1] = (int) ptr;
- block[2] = len;
-
- return do_AngelSWI (AngelSWI_Reason_Write, block);
-#else
- __asm ("mov r0, %1; mov r1, %2;mov r2, %3; swi %a0"
- : /* No outputs */
- : "i"(SWI_Write), "r"(fh), "r"(ptr), "r"(len)
- : "r0","r1","r2");
- return (0);
-#endif
-}
-
-/******************************************************************************
-* Function Name: _write
-* Description : GNU interface to low-level I/O write
-* Arguments : int file_no
-* : const char *buffer
-* : unsigned int n
-* Return Value : none
-******************************************************************************/
-int _write(int file_no , const char *buffer , unsigned int n)
-{
- return (sio_write(file_no , buffer , n));
-}
-
-int
-_swiopen (const char * path,
- int flags)
-{
- int aflags = 0, fh;
-#ifdef ARM_RDI_MONITOR
- int block[3];
-#endif
-
- int i = findslot (-1);
-
- if (MAX_OPEN_FILES == i)
- {
- return (-1);
- }
-
- /* The flags are Unix-style, so we need to convert them. */
-#ifdef O_BINARY
- if (flags & O_BINARY)
- {
- aflags |= 1;
- }
-#endif
-
- if (flags & O_RDWR)
- {
- aflags |= 2;
- }
-
- if (flags & O_CREAT)
- {
- aflags |= 4;
- }
-
- if (flags & O_TRUNC)
- {
- aflags |= 4;
- }
-
- if (flags & O_APPEND)
- {
- aflags &= (~4); /* Can't ask for w AND a; means just 'a'. */
- aflags |= 8;
- }
-
-#ifdef ARM_RDI_MONITOR
- block[0] = (int) path;
- block[2] = strlen (path);
- block[1] = aflags;
-
- fh = do_AngelSWI (AngelSWI_Reason_Open, block);
-
-#else
- __asm ("mov r0,%2; mov r1, %3; swi %a1; mov %0, r0"
- : "=r"(fh)
- : "i" (SWI_Open),"r"(path),"r"(aflags)
- : "r0","r1");
-#endif
-
- if (fh >= 0)
- {
- openfiles[i].handle = fh;
- openfiles[i].pos = 0;
- }
-
- return ((fh >= 0) ? (fh + FILE_HANDLE_OFFSET) : error (fh));
-}
-
-int
-_open (const char * path,
- int flags,
- ...)
-{
- return (wrap (_swiopen (path, flags)));
-}
-
-int
-_swiclose (int file)
-{
- int myhan = remap_handle (file);
- int slot = findslot (myhan);
-
- if (MAX_OPEN_FILES != slot)
- {
- openfiles[slot].handle = (-1);
- }
-
-#ifdef ARM_RDI_MONITOR
- return do_AngelSWI (AngelSWI_Reason_Close, & myhan);
-#else
- __asm ("mov r0, %1; swi %a0" :: "i" (SWI_Close),"r"(myhan):"r0");
- return (0);
-#endif
-}
-
-int
-_close (int file)
-{
- return (wrap (_swiclose (file)));
-}
-
-int
-_kill (int pid, int sig)
-{
- (void)pid; (void)sig;
-#ifdef ARM_RDI_MONITOR
- /* Note: The pid argument is thrown away. */
- switch (sig) {
- case SIGABRT:
- return do_AngelSWI (AngelSWI_Reason_ReportException,
- (void *) ADP_Stopped_RunTimeError);
- default:
- return do_AngelSWI (AngelSWI_Reason_ReportException,
- (void *) ADP_Stopped_ApplicationExit);
- }
-#else
- __asm ("swi %a0" :: "i" (SWI_Exit));
- return (0);
-#endif
-}
-
-void
-_exit (int status)
-{
- /* There is only one SWI for both _exit and _kill. For _exit, call
- the SWI with the second argument set to -1, an invalid value for
- signum, so that the SWI handler can distinguish the two calls.
- Note: The RDI implementation of _kill throws away both its
- arguments. */
- _kill(status, -1);
- while(1)
- {
- /* exit occurred */
- };
-}
-
-int
-_getpid (int n)
-{
- (void)(n);
- return (1);
-}
-
-caddr_t
-_sbrk (int incr)
-{
- extern char end __asm ("end"); /* Defined by the linker. */
- static char * pheap_end;
- char * prev_heap_end;
-
- if (NULL == pheap_end)
- {
- pheap_end = (&end);
- }
-
- prev_heap_end = pheap_end;
-
- if ((pheap_end + incr) > stack_ptr)
- {
- /* Some of the libstdc++-v3 tests rely upon detecting
- out of memory errors, so do not abort here. */
-#if 0
- extern void abort (void);
-
- _write (1, "_sbrk: Heap and stack collision\n", 32);
-
- abort ();
-#else
- errno = ENOMEM;
- return ((caddr_t) (-1));
-#endif
- }
-
- pheap_end += incr;
-
- return ((caddr_t) prev_heap_end);
-}
-
-int
-_fstat (int file, struct stat * st)
-{
- (void)file;
- memset (st, 0, sizeof (* st));
- st->st_mode = S_IFCHR;
- st->st_blksize = 1024;
- return (0);
-}
-
-int _stat (const char *fname, struct stat *st)
-{
- int file;
-
- /* The best we can do is try to open the file read-only. If it exists,
- then we can guess a few things about it. */
- if ((file = _open (fname, O_RDONLY)) < 0)
- {
- return (-1);
- }
-
- memset (st, 0, sizeof (* st));
- st->st_mode = (S_IFREG | S_IREAD);
- st->st_blksize = 1024;
- _swiclose (file); /* Not interested in the error. */
- return (0);
-}
-
-int
-_link (void)
-{
- return (-1);
-}
-
-int
-_unlink (const char *path)
-{
-#ifdef ARM_RDI_MONITOR
- int block[2];
- block[0] = path;
- block[1] = strlen(path);
- return wrap (do_AngelSWI (AngelSWI_Reason_Remove, block)) ? -1 : 0;
-#else
- return -1;
-#endif
-}
-
-void
-_raise (void)
-{
- return;
-}
-
-int
-_gettimeofday (struct timeval * tp, void * tzvp)
-{
- struct timezone * ptzp = tzvp;
- if (tp)
- {
- /* Ask the host for the seconds since the Unix epoch. */
-#ifdef ARM_RDI_MONITOR
- tp->tv_sec = do_AngelSWI (AngelSWI_Reason_Time,NULL);
-#else
- {
- int value;
- __asm ("swi %a1; mov %0, r0" : "=r" (value): "i" (SWI_Time) : "r0");
- tp->tv_sec = value;
- }
-#endif
- tp->tv_usec = 0;
- }
-
- /* Return fixed data for the time-zone. */
- if (ptzp)
- {
- ptzp->tz_minuteswest = 0;
- ptzp->tz_dsttime = 0;
- }
-
- return (0);
-}
-
-/* Return a clock that ticks at 100Hz. */
-clock_t
-_times (struct tms * tp)
-{
- clock_t timeval;
-
-#ifdef ARM_RDI_MONITOR
- timeval = do_AngelSWI (AngelSWI_Reason_Clock,NULL);
-#else
- __asm ("swi %a1; mov %0, r0" : "=r" (timeval): "i" (SWI_Clock) : "r0");
-#endif
-
- if (tp)
- {
- tp->tms_utime = timeval; /* user time */
- tp->tms_stime = 0; /* system time */
- tp->tms_cutime = 0; /* user time, children */
- tp->tms_cstime = 0; /* system time, children */
- }
-
- return (timeval);
-};
-
-
-int
-_isatty (int fd)
-{
-#ifdef ARM_RDI_MONITOR
- int fh = remap_handle (fd);
- return wrap (do_AngelSWI (AngelSWI_Reason_IsTTY, &fh));
-#else
- return ((fd <= 2) ? 1 : 0); /* one of stdin, stdout, stderr */
-#endif
-}
-
-int
-_system (const char *s)
-{
-#ifdef ARM_RDI_MONITOR
- int block[2];
- int e;
-
- /* Hmmm. The ARM debug interface specification doesn't say whether
- SYS_SYSTEM does the right thing with a null argument, or assign any
- meaning to its return value. Try to do something reasonable.... */
- if (!s)
- return 1; /* maybe there is a shell available? we can hope. :-P */
- block[0] = s;
- block[1] = strlen (s);
- e = wrap (do_AngelSWI (AngelSWI_Reason_System, block));
- if ((e >= 0) && (e < 256))
- {
- /* We have to convert e, an exit status to the encoded status of
- the command. To avoid hard coding the exit status, we simply
- loop until we find the right position. */
- int exit_code;
-
- for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1)
- continue;
- }
- return e;
-#else
- if (NULL == s)
- {
- return (0);
- }
- errno = ENOSYS;
- return (-1);
-#endif
-}
-
-int
-_rename (const char * oldpath, const char * newpath)
-{
-#ifdef ARM_RDI_MONITOR
- int block[4];
- block[0] = oldpath;
- block[1] = strlen(oldpath);
- block[2] = newpath;
- block[3] = strlen(newpath);
- return wrap (do_AngelSWI (AngelSWI_Reason_Rename, block)) ? -1 : 0;
-#else
- errno = ENOSYS;
- return (-1);
-#endif
-}
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm
new file mode 100644
index 0000000000..4668654ac3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm
@@ -0,0 +1,117 @@
+/*
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ ***************************************************************************
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+ ***************************************************************************
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following
+ link: http://www.freertos.org/a00114.html
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that is more than just the market leader, it *
+ * is the industry's de facto standard. *
+ * *
+ * Help yourself get started quickly while simultaneously helping *
+ * to support the FreeRTOS project by purchasing a FreeRTOS *
+ * tutorial book, reference manual, or both: *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
+ the FAQ page "My application does not run, what could be wrong?". Have you
+ defined configASSERT()?
+
+ http://www.FreeRTOS.org/support - In return for receiving this top quality
+ embedded software for free we request you assist our global community by
+ participating in the support forum.
+
+ http://www.FreeRTOS.org/training - Investing in training allows your team to
+ be as productive as possible as early as possible. Now you can receive
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ Ltd, and the world's leading authority on the world's leading RTOS.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and commercial middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+ SECTION intvec:CODE:ROOT(2)
+ ARM
+
+ EXTERN pxISRFunction
+ EXTERN FreeRTOS_Tick_Handler
+ EXTERN FreeRTOS_IRQ_Handler
+ EXTERN vCMT_1_Channel_0_ISR
+ EXTERN vCMT_1_Channel_1_ISR
+
+ PUBLIC FreeRTOS_Tick_Handler_Entry
+ PUBLIC vCMT_1_Channel_0_ISR_Entry
+ PUBLIC vCMT_1_Channel_1_ISR_Entry
+
+FreeRTOS_Tick_Handler_Entry:
+ /* Save used registers (probably not necessary). */
+ PUSH {r0-r1}
+ /* Save the address of the C portion of this handler in pxISRFunction. */
+ LDR r0, =pxISRFunction
+ LDR R1, =FreeRTOS_Tick_Handler
+ STR R1, [r0]
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */
+ POP {r0-r1}
+ B FreeRTOS_IRQ_Handler
+/*-----------------------------------------------------------*/
+
+vCMT_1_Channel_0_ISR_Entry:
+ /* Save used registers (probably not necessary). */
+ PUSH {r0-r1}
+ /* Save the address of the C portion of this handler in pxISRFunction. */
+ LDR r0, =pxISRFunction
+ LDR R1, =vCMT_1_Channel_0_ISR
+ STR R1, [r0]
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */
+ POP {r0-r1}
+ B FreeRTOS_IRQ_Handler
+/*-----------------------------------------------------------*/
+
+vCMT_1_Channel_1_ISR_Entry:
+ /* Save used registers (probably not necessary). */
+ PUSH {r0-r1}
+ /* Save the address of the C portion of this handler in pxISRFunction. */
+ LDR r0, =pxISRFunction
+ LDR R1, =vCMT_1_Channel_1_ISR
+ STR R1, [r0]
+ /* Restore used registers then branch to the FreeRTOS IRQ handler. */
+ POP {r0-r1}
+ B FreeRTOS_IRQ_Handler
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac
new file mode 100644
index 0000000000..795e779e89
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac
@@ -0,0 +1,81 @@
+/*
+ *
+ * C-SPY macro information
+ *
+ * __jtagCP15ReadReg(CRn, CRm, op1, op2)
+ * __jtagCP15WriteReg(CRn, CRm, op1, op2, value)
+ * __readMemory8(address, zone)
+ * __writeMemory8(value, address, zone)
+ * __writeMemory32(value, address, zone)
+ *
+ *
+ */
+
+__init_TCM()
+{
+__var v_reg;
+
+ __message "Initialize ATCM";
+ /*
+ MRC p15, 0, , c1, c0, 1 ; Read ACTLR
+ MCR p15, 0, , c1, c0, 1 ; Write ACTLR
+ */
+
+ /* enable ECC in ACTLR */
+ v_reg = __jtagCP15ReadReg(1, 0, 0, 1);
+ v_reg = v_reg | 0x06000000; // set 26 and 25 bits for enabling ECC
+ __message "ACTRL: ", v_reg:%x; // output ACTRL value for check
+ __jtagCP15WriteReg(1, 0, 0, 1, v_reg);
+
+ __fillMemory32(0x0, 0x00000000, "Memory", 0x20000, "Copy");
+ __message "ATCM initialization finished";
+}
+
+
+__init_VIC_ProvideHandler()
+{
+__var v_reg;
+
+ __message "Initialize VIC provide handler \n";
+ /*
+ MRC p15, 0, , c1, c0, 0 ; Read SCTLR
+ MCR p15, 0, , c1, c0, 0 ; Write SCTLR
+ */
+
+ /* Set VIC to provide handler address */
+ v_reg = __jtagCP15ReadReg(1, 0, 0, 0);
+ v_reg = v_reg | 0x01000000; // set 24 bit for setting VE bit
+ __jtagCP15WriteReg(1, 0, 0, 0, v_reg);
+
+}
+
+execUserPreload()
+{
+__var t ;
+
+ __message "Executing execUserPreload() function";
+
+ __hwReset(0);
+ __delay(100);
+ __init_TCM();
+
+ __message "FINISH Executing execUserPreload() function";
+}
+
+
+execUserReset()
+{
+__var t;
+ __message "Executing execUserReset() function";
+
+ __init_VIC_ProvideHandler();
+
+ t = #CPSR; // Clear CPSR.F bit
+ __message "CPSR ",t:%x;
+ t = t & 0xFFFFFFBF;
+ #CPSR = t;
+ t = #CPSR;
+ __message "CPSR ",t:%x;
+
+ __message "FINISH Executing execUserReset() function";
+}
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf
new file mode 100644
index 0000000000..2e86388b67
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf
@@ -0,0 +1,163 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x40020040;
+define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x00070000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_svcstack__ = 0x200;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define symbol __region_USER_PRG_start__ = 0x00000040;
+define symbol __region_USER_PRG_end__ = 0x0006FFFF;
+
+define symbol __region_D_LDR_DATA_start__ = 0x00800000;
+define symbol __region_D_LDR_DATA_end__ = 0x00801FFF;
+define symbol __region_D_LDR_PRG_start__ = 0x00802000;
+define symbol __region_D_LDR_PRG_end__ = 0x00807FFF;
+
+define symbol __region_D_LDR_M3PRG_start__ = 0x04000000;
+define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF;
+
+define symbol __region_S_LDR_M3PRG_start__ = 0x00050000;
+define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF;
+
+define symbol __region_EXT_RAM1_start__ = 0x22000000;
+define symbol __region_EXT_RAM1_end__ = 0x2207FFFF;
+define symbol __region_EXT_RAM2_start__ = 0x24000000;
+define symbol __region_EXT_RAM2_end__ = 0x2407FFFF;
+define symbol __region_SPIBSC_start__ = 0x30000000;
+define symbol __region_SPIBSC_end__ = 0x33FFFFFF;
+
+define symbol __region_CS0_start__ = 0x40000000;
+define symbol __region_CS0_end__ = 0x43FFFFFF;
+define symbol __region_CS1_start__ = 0x44000000;
+define symbol __region_CS1_end__ = 0x47FFFFFF;
+define symbol __region_CS2_start__ = 0x48000000;
+define symbol __region_CS2_end__ = 0x4BFFFFFF;
+define symbol __region_CS3_start__ = 0x4C000000;
+define symbol __region_CS3_end__ = 0x4FFFFFFF;
+define symbol __region_CS4_start__ = 0x50000000;
+define symbol __region_CS4_end__ = 0x53FFFFFF;
+define symbol __region_CS5_start__ = 0x54000000;
+define symbol __region_CS5_end__ = 0x57FFFFFF;
+
+define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__];
+define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__];
+define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__];
+
+define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__];
+define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__];
+
+define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__];
+define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__];
+define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__];
+define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__];
+define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__];
+define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__];
+define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__];
+define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__];
+define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+
+define block LDR_PRG_RBLOCK with fixed order
+ { ro code object loader_init.o,
+ ro code object loader_init2.o,
+ ro code object r_atcm_init.o,
+ ro code object r_cpg.o,
+ ro code object r_ram_init.o,
+ ro code object r_mpc.o,
+ ro code object r_reset.o,
+ ro code object data_init.o,
+ ro code object copy_init3.o };
+define block LDR_DATA_ZBLOCK { section .bss object loader_init.o,
+ section .bss object loader_init2.o,
+ section .bss object r_atcm_init.o,
+ section .bss object r_cpg.o,
+ section .bss object r_ram_init.o,
+ section .bss object r_mpc.o,
+ section .bss object r_reset.o,
+ section .bss object data_init.o,
+ section .bss object copy_init3.o };
+define block LDR_DATA_RBLOCK { section .data_init object loader_init.o,
+ section .data_init object loader_init2.o,
+ section .data_init object r_atcm_init.o,
+ section .data_init object r_cpg.o,
+ section .data_init object r_ram_init.o,
+ section .data_init object r_mpc.o,
+ section .data_init object r_reset.o,
+ section .data_init object data_init.o,
+ section .data_init object copy_init3.o };
+define block LDR_DATA_WBLOCK { section .data object loader_init.o,
+ section .data object loader_init2.o,
+ section .data object r_atcm_init.o,
+ section .data object r_cpg.o,
+ section .data object r_ram_init.o,
+ section .data object r_mpc.o,
+ section .data object r_reset.o,
+ section .data object data_init.o,
+ section .data object copy_init3.o };
+define block VECTOR_RBLOCK { ro code object vector.o };
+define block USER_PRG_RBLOCK { ro code };
+define block USER_DATA_ZBLOCK { section .bss };
+define block USER_DATA_RBLOCK { section .data_init };
+define block USER_DATA_WBLOCK { section .data };
+
+define block M3_PRG_RBLOCK { section __M3prg_init };
+define block M3_PRG_WBLOCK { section __M3prg };
+
+initialize by copy { readwrite };
+
+do not initialize { section .noinit, section .bss };
+
+initialize manually { section __M3prg };
+
+place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK };
+
+place in USER_PRG_region { block USER_PRG_RBLOCK,
+ block USER_DATA_RBLOCK,
+ readonly };
+place in RAM_region { readwrite };
+place in RAM_region { block USER_DATA_WBLOCK,
+ block USER_DATA_ZBLOCK,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK };
+place in D_LDR_PRG_region { block LDR_PRG_RBLOCK,
+ block LDR_DATA_RBLOCK };
+
+place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK };
+place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK };
+
+place in EXT_RAM1_region {};
+place in EXT_RAM2_region {};
+place in SPIBSC_region {};
+place in CS0_region {};
+place in CS1_region {};
+place in CS2_region {};
+place in CS3_region {};
+place in CS4_region {};
+place in CS5_region {};
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h
new file mode 100644
index 0000000000..977d508fc3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h
@@ -0,0 +1,64 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_atcm.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for ATCM function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : ATCM access wait setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_ATCM_HEADER_
+#define _R_ATCM_HEADER_
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define ATCM_WAIT_1_OPT (0)
+#define ATCM_WAIT_1 (1)
+#define ATCM_WAIT_0 (2)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void R_ATCM_WaitSet(uint32_t atcm_wait);
+
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h
new file mode 100644
index 0000000000..926c3aaef6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h
@@ -0,0 +1,186 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_cpg.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for CPG function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : BSC setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_BSC_HEADER_
+#define _R_BSC_HEADER_
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define BSC_IDLE_CYCLE_0 (0)
+#define BSC_IDLE_CYCLE_1 (1)
+#define BSC_IDLE_CYCLE_2 (2)
+#define BSC_IDLE_CYCLE_4 (3)
+#define BSC_IDLE_CYCLE_6 (4)
+#define BSC_IDLE_CYCLE_8 (5)
+#define BSC_IDLE_CYCLE_10 (6)
+#define BSC_IDLE_CYCLE_12 (7)
+
+#define BSC_TYPE_NORMAL (0)
+#define BSC_TYPE_BURST_ROM_ASYNC (1)
+#define BSC_TYPE_MPX_IO (2)
+#define BSC_TYPE_SRAM_BYTE (3)
+#define BSC_TYPE_SDRAM (4)
+#define BSC_TYPE_BURST_ROM_SYNC (7)
+
+#define BSC_WIDTH_8_BIT (1)
+#define BSC_WIDTH_16_BIT (2)
+#define BSC_WIDTH_32_BIT (3)
+
+#define BSC_DELAY_STATE_CYCLE_0_5 (0)
+#define BSC_DELAY_STATE_CYCLE_1_5 (1)
+#define BSC_DELAY_STATE_CYCLE_2_5 (2)
+#define BSC_DELAY_STATE_CYCLE_3_5 (3)
+
+#define BSC_EXT_WAIT_VALID (0)
+#define BSC_EXT_WAIT_IGNORED (1)
+
+#define BSC_ACCESS_WAIT_0 (0)
+#define BSC_ACCESS_WAIT_1 (1)
+#define BSC_ACCESS_WAIT_2 (2)
+#define BSC_ACCESS_WAIT_3 (3)
+#define BSC_ACCESS_WAIT_4 (4)
+#define BSC_ACCESS_WAIT_5 (5)
+#define BSC_ACCESS_WAIT_6 (6)
+#define BSC_ACCESS_WAIT_8 (7)
+#define BSC_ACCESS_WAIT_10 (8)
+#define BSC_ACCESS_WAIT_12 (9)
+#define BSC_ACCESS_WAIT_14 (10)
+#define BSC_ACCESS_WAIT_18 (11)
+#define BSC_ACCESS_WAIT_24 (12)
+
+#define BSC_WRITE_ACCESS_WAIT_SAME (0) // Set same settings of WR[3:0]bit
+#define BSC_WRITE_ACCESS_WAIT_0 (1)
+#define BSC_WRITE_ACCESS_WAIT_1 (2)
+#define BSC_WRITE_ACCESS_WAIT_2 (3)
+#define BSC_WRITE_ACCESS_WAIT_3 (4)
+#define BSC_WRITE_ACCESS_WAIT_4 (5)
+#define BSC_WRITE_ACCESS_WAIT_5 (6)
+#define BSC_WRITE_ACCESS_WAIT_6 (7)
+
+#define BSC_BYTE_ENABLE_RD_WR (0)
+#define BSC_BYTE_ENABLE_WE (1)
+
+#define BSC_CAS_LATENCY_1 (0)
+#define BSC_CAS_LATENCY_2 (1)
+#define BSC_CAS_LATENCY_3 (2)
+#define BSC_CAS_LATENCY_4 (3)
+
+#define BSC_WTRC_IDLE_2 (0)
+#define BSC_WTRC_IDLE_3 (1)
+#define BSC_WTRC_IDLE_5 (2)
+#define BSC_WTRC_IDLE_8 (3)
+
+#define BSC_TRWL_CYCLE_0 (0)
+#define BSC_TRWL_CYCLE_1 (1)
+#define BSC_TRWL_CYCLE_2 (2)
+#define BSC_TRWL_CYCLE_3 (3)
+
+#define BSC_PRECHARGE_0 (0x00000000)
+#define BSC_PRECHARGE_1 (0x00000008)
+#define BSC_PRECHARGE_2 (0x00000010)
+#define BSC_PRECHARGE_3 (0x00000018)
+
+#define BSC_WTRCD_WAIT_0 (0)
+#define BSC_WTRCD_WAIT_1 (1)
+#define BSC_WTRCD_WAIT_2 (2)
+#define BSC_WTRCD_WAIT_3 (3)
+
+#define BSC_WTRP_WAIT_0 (0)
+#define BSC_WTRP_WAIT_1 (1)
+#define BSC_WTRP_WAIT_2 (2)
+#define BSC_WTRP_WAIT_3 (3)
+
+#define BSC_ROW_11_BIT (0)
+#define BSC_ROW_12_BIT (1)
+#define BSC_ROW_13_BIT (2)
+
+#define BSC_COL_8_BIT (0)
+#define BSC_COL_9_BIT (1)
+#define BSC_COL_10_BIT (2)
+
+#define BSC_BACTV_AUTO (0)
+#define BSC_BACTV_BANK (1)
+
+#define BSC_PDOWN_INVALID (0)
+#define BSC_PDOWN_VALID (1)
+
+#define BSC_RMODE_AUTO (0)
+#define BSC_RMODE_SELF (1)
+
+#define BSC_RFSH_NONE (0)
+#define BSC_RFSH_DONE (1)
+
+#define BSC_DEEP_SELF (0)
+#define BSC_DEEP_DEEP (1)
+
+#define BSC_PROTECT_KEY (0xA55A0000)
+
+#define BSC_RFSH_TIME_1 (0)
+#define BSC_RFSH_TIME_2 (1)
+#define BSC_RFSH_TIME_4 (2)
+#define BSC_RFSH_TIME_6 (3)
+#define BSC_RFSH_TIME_8 (4)
+
+#define BSC_CKS_DIV_STOP (0x00000000)
+#define BSC_CKS_DIV_4 (0x00000008)
+#define BSC_CKS_DIV_16 (0x00000010)
+#define BSC_CKS_DIV_64 (0x00000018)
+#define BSC_CKS_DIV_256 (0x00000020)
+#define BSC_CKS_DIV_1024 (0x00000028)
+#define BSC_CKS_DIV_2048 (0x00000030)
+#define BSC_CKS_DIV_4096 (0x00000038)
+
+#define BSC_CMIE_DISABLE (0x00000000)
+#define BSC_CMIE_ENABLE (0x00000040)
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h
new file mode 100644
index 0000000000..5dd55d6055
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h
@@ -0,0 +1,83 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_cpg.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for CPG function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : CPG setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_CPG_HEADER_
+#define _R_CPG_HEADER_
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define CPG_CPUCLK_150_MHz (0)
+#define CPG_CPUCLK_300_MHz (1)
+#define CPG_CPUCLK_450_MHz (2)
+#define CPG_CPUCLK_600_MHz (3)
+
+#define CPG_PLL1_OFF (0)
+#define CPG_PLL1_ON (1)
+
+#define CPG_SELECT_PLL0 (0)
+#define CPG_SELECT_PLL1 (1)
+
+#define CPG_CKIO_75_MHz (0)
+#define CPG_CKIO_50_MHz (1)
+#define CPG_CKIO_37_5_MHz (2)
+#define CPG_CKIO_30_MHz (3)
+#define CPG_CKIO_25_MHz (4)
+#define CPG_CKIO_21_43_MHz (5)
+#define CPG_CKIO_18_75_MHz (6)
+
+#define CPG_LOCO_ENABLE (0x00000000)
+#define CPG_LOCO_DISABLE (0x00000001)
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void R_CPG_WriteEnable(void);
+void R_CPG_WriteDisable(void);
+void R_CPG_PLL_Wait(void);
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h
new file mode 100644
index 0000000000..be645eec2d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_ecm.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for ecm function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : ecm function API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_ECM_HEADER_
+#define _R_ECM_HEADER_
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define ECM_COMMAND_KEY (0x000000A5)
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef enum
+{
+ ECM_MASTER,
+ ECM_CHECKER,
+ ECM_COMMON,
+ ECM_TYPE_MAX
+} ecm_reg_type_t;
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void R_ECM_Init(void);
+void R_ECM_CompareError_Wait(void);
+uint8_t R_ECM_Write_Reg8(uint8_t reg_type, volatile unsigned char *reg, uint8_t value);
+uint8_t R_ECM_Write_Reg32(uint8_t reg_type, volatile unsigned long *reg, uint32_t value);
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h
new file mode 100644
index 0000000000..be11be7332
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h
@@ -0,0 +1,389 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_icu_init.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for ICU init
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : Initialize interrupt controller unit.
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_ICU_INIT_HEADER_
+#define _R_ICU_INIT_HEADER_
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+#define ICU_EXT_PIN_0 (0)
+#define ICU_EXT_PIN_1 (1)
+#define ICU_EXT_PIN_2 (2)
+#define ICU_EXT_PIN_3 (3)
+#define ICU_EXT_PIN_4 (4)
+#define ICU_EXT_PIN_5 (5)
+#define ICU_EXT_PIN_6 (6)
+#define ICU_EXT_PIN_7 (7)
+#define ICU_EXT_PIN_8 (8)
+#define ICU_EXT_PIN_9 (9)
+#define ICU_EXT_PIN_10 (10)
+#define ICU_EXT_PIN_11 (11)
+#define ICU_EXT_PIN_12 (12)
+#define ICU_EXT_PIN_13 (13)
+#define ICU_EXT_PIN_14 (14)
+#define ICU_EXT_PIN_15 (15)
+
+#define ICU_DETECT_LOW (0x00)
+#define ICU_DETECT_FALL (0x04)
+#define ICU_DETECT_RISE (0x08)
+#define ICU_DETECT_RISE_FALL (0x0C)
+
+#define ICU_DNF_DIVISION_1 (0)
+#define ICU_DNF_DIVISION_8 (1)
+#define ICU_DNF_DIVISION_32 (2)
+#define ICU_DNF_DIVISION_64 (3)
+#define ICU_DNF_NO_USE (4)
+
+#define ICU_VEC_NUM_1 (1)
+#define ICU_VEC_NUM_2 (2)
+#define ICU_VEC_NUM_3 (3)
+#define ICU_VEC_NUM_4 (4)
+#define ICU_VEC_NUM_5 (5)
+#define ICU_VEC_NUM_6 (6)
+#define ICU_VEC_NUM_7 (7)
+#define ICU_VEC_NUM_8 (8)
+#define ICU_VEC_NUM_9 (9)
+#define ICU_VEC_NUM_10 (10)
+#define ICU_VEC_NUM_11 (11)
+#define ICU_VEC_NUM_12 (12)
+#define ICU_VEC_NUM_13 (13)
+#define ICU_VEC_NUM_14 (14)
+#define ICU_VEC_NUM_15 (15)
+#define ICU_VEC_NUM_16 (16)
+#define ICU_VEC_NUM_17 (17)
+#define ICU_VEC_NUM_18 (18)
+#define ICU_VEC_NUM_19 (19)
+#define ICU_VEC_NUM_20 (20)
+#define ICU_VEC_NUM_21 (21)
+#define ICU_VEC_NUM_22 (22)
+#define ICU_VEC_NUM_23 (23)
+#define ICU_VEC_NUM_24 (24)
+#define ICU_VEC_NUM_25 (25)
+#define ICU_VEC_NUM_26 (26)
+#define ICU_VEC_NUM_27 (27)
+#define ICU_VEC_NUM_28 (28)
+#define ICU_VEC_NUM_29 (29)
+#define ICU_VEC_NUM_30 (30)
+#define ICU_VEC_NUM_31 (31)
+#define ICU_VEC_NUM_32 (32)
+#define ICU_VEC_NUM_33 (33)
+#define ICU_VEC_NUM_34 (34)
+#define ICU_VEC_NUM_35 (35)
+#define ICU_VEC_NUM_36 (36)
+#define ICU_VEC_NUM_37 (37)
+#define ICU_VEC_NUM_38 (38)
+#define ICU_VEC_NUM_39 (39)
+#define ICU_VEC_NUM_40 (40)
+#define ICU_VEC_NUM_41 (41)
+#define ICU_VEC_NUM_42 (42)
+#define ICU_VEC_NUM_43 (43)
+#define ICU_VEC_NUM_44 (44)
+#define ICU_VEC_NUM_45 (45)
+#define ICU_VEC_NUM_46 (46)
+#define ICU_VEC_NUM_47 (47)
+#define ICU_VEC_NUM_48 (48)
+#define ICU_VEC_NUM_49 (49)
+#define ICU_VEC_NUM_50 (50)
+#define ICU_VEC_NUM_51 (51)
+#define ICU_VEC_NUM_52 (52)
+#define ICU_VEC_NUM_53 (53)
+#define ICU_VEC_NUM_54 (54)
+#define ICU_VEC_NUM_55 (55)
+#define ICU_VEC_NUM_56 (56)
+#define ICU_VEC_NUM_57 (57)
+#define ICU_VEC_NUM_58 (58)
+#define ICU_VEC_NUM_59 (59)
+#define ICU_VEC_NUM_60 (60)
+#define ICU_VEC_NUM_61 (61)
+#define ICU_VEC_NUM_62 (62)
+#define ICU_VEC_NUM_63 (63)
+#define ICU_VEC_NUM_64 (64)
+#define ICU_VEC_NUM_65 (65)
+#define ICU_VEC_NUM_66 (66)
+#define ICU_VEC_NUM_67 (67)
+#define ICU_VEC_NUM_68 (68)
+#define ICU_VEC_NUM_69 (69)
+#define ICU_VEC_NUM_70 (70)
+#define ICU_VEC_NUM_73 (73)
+#define ICU_VEC_NUM_74 (74)
+#define ICU_VEC_NUM_75 (75)
+#define ICU_VEC_NUM_76 (76)
+#define ICU_VEC_NUM_77 (77)
+#define ICU_VEC_NUM_78 (78)
+#define ICU_VEC_NUM_79 (79)
+#define ICU_VEC_NUM_80 (80)
+#define ICU_VEC_NUM_81 (81)
+#define ICU_VEC_NUM_82 (82)
+#define ICU_VEC_NUM_83 (83)
+#define ICU_VEC_NUM_84 (84)
+#define ICU_VEC_NUM_85 (85)
+#define ICU_VEC_NUM_86 (86)
+#define ICU_VEC_NUM_87 (87)
+#define ICU_VEC_NUM_88 (88)
+#define ICU_VEC_NUM_89 (89)
+#define ICU_VEC_NUM_90 (90)
+#define ICU_VEC_NUM_91 (91)
+#define ICU_VEC_NUM_92 (92)
+#define ICU_VEC_NUM_93 (93)
+#define ICU_VEC_NUM_94 (94)
+#define ICU_VEC_NUM_95 (95)
+#define ICU_VEC_NUM_96 (96)
+#define ICU_VEC_NUM_97 (97)
+#define ICU_VEC_NUM_98 (98)
+#define ICU_VEC_NUM_99 (99)
+#define ICU_VEC_NUM_100 (100)
+#define ICU_VEC_NUM_101 (101)
+#define ICU_VEC_NUM_102 (102)
+#define ICU_VEC_NUM_103 (103)
+#define ICU_VEC_NUM_104 (104)
+#define ICU_VEC_NUM_105 (105)
+#define ICU_VEC_NUM_106 (106)
+#define ICU_VEC_NUM_107 (107)
+#define ICU_VEC_NUM_108 (108)
+#define ICU_VEC_NUM_109 (109)
+#define ICU_VEC_NUM_110 (110)
+#define ICU_VEC_NUM_111 (111)
+#define ICU_VEC_NUM_112 (112)
+#define ICU_VEC_NUM_113 (113)
+#define ICU_VEC_NUM_114 (114)
+#define ICU_VEC_NUM_115 (115)
+#define ICU_VEC_NUM_116 (116)
+#define ICU_VEC_NUM_117 (117)
+#define ICU_VEC_NUM_118 (118)
+#define ICU_VEC_NUM_119 (119)
+#define ICU_VEC_NUM_120 (120)
+#define ICU_VEC_NUM_121 (121)
+#define ICU_VEC_NUM_122 (122)
+#define ICU_VEC_NUM_123 (123)
+#define ICU_VEC_NUM_124 (124)
+#define ICU_VEC_NUM_125 (125)
+#define ICU_VEC_NUM_126 (126)
+#define ICU_VEC_NUM_127 (127)
+#define ICU_VEC_NUM_128 (128)
+#define ICU_VEC_NUM_145 (145)
+#define ICU_VEC_NUM_146 (146)
+#define ICU_VEC_NUM_147 (147)
+#define ICU_VEC_NUM_148 (148)
+#define ICU_VEC_NUM_149 (149)
+#define ICU_VEC_NUM_150 (150)
+#define ICU_VEC_NUM_151 (151)
+#define ICU_VEC_NUM_152 (152)
+#define ICU_VEC_NUM_153 (153)
+#define ICU_VEC_NUM_154 (154)
+#define ICU_VEC_NUM_155 (155)
+#define ICU_VEC_NUM_156 (156)
+#define ICU_VEC_NUM_157 (157)
+#define ICU_VEC_NUM_158 (158)
+#define ICU_VEC_NUM_159 (159)
+#define ICU_VEC_NUM_160 (160)
+#define ICU_VEC_NUM_161 (161)
+#define ICU_VEC_NUM_162 (162)
+#define ICU_VEC_NUM_163 (163)
+#define ICU_VEC_NUM_164 (164)
+#define ICU_VEC_NUM_165 (165)
+#define ICU_VEC_NUM_166 (166)
+#define ICU_VEC_NUM_167 (167)
+#define ICU_VEC_NUM_168 (168)
+#define ICU_VEC_NUM_169 (169)
+#define ICU_VEC_NUM_170 (170)
+#define ICU_VEC_NUM_171 (171)
+#define ICU_VEC_NUM_172 (172)
+#define ICU_VEC_NUM_173 (173)
+#define ICU_VEC_NUM_174 (174)
+#define ICU_VEC_NUM_175 (175)
+#define ICU_VEC_NUM_176 (176)
+#define ICU_VEC_NUM_177 (177)
+#define ICU_VEC_NUM_178 (178)
+#define ICU_VEC_NUM_179 (179)
+#define ICU_VEC_NUM_180 (180)
+#define ICU_VEC_NUM_181 (181)
+#define ICU_VEC_NUM_182 (182)
+#define ICU_VEC_NUM_183 (183)
+#define ICU_VEC_NUM_184 (184)
+#define ICU_VEC_NUM_185 (185)
+#define ICU_VEC_NUM_186 (186)
+#define ICU_VEC_NUM_187 (187)
+#define ICU_VEC_NUM_188 (188)
+#define ICU_VEC_NUM_189 (189)
+#define ICU_VEC_NUM_190 (190)
+#define ICU_VEC_NUM_191 (191)
+#define ICU_VEC_NUM_192 (192)
+#define ICU_VEC_NUM_193 (193)
+#define ICU_VEC_NUM_194 (194)
+#define ICU_VEC_NUM_195 (195)
+#define ICU_VEC_NUM_196 (196)
+#define ICU_VEC_NUM_197 (197)
+#define ICU_VEC_NUM_198 (198)
+#define ICU_VEC_NUM_199 (199)
+#define ICU_VEC_NUM_200 (200)
+#define ICU_VEC_NUM_201 (201)
+#define ICU_VEC_NUM_202 (202)
+#define ICU_VEC_NUM_203 (203)
+#define ICU_VEC_NUM_204 (204)
+#define ICU_VEC_NUM_205 (205)
+#define ICU_VEC_NUM_206 (206)
+#define ICU_VEC_NUM_207 (207)
+#define ICU_VEC_NUM_208 (208)
+#define ICU_VEC_NUM_209 (209)
+#define ICU_VEC_NUM_210 (210)
+#define ICU_VEC_NUM_211 (211)
+#define ICU_VEC_NUM_212 (212)
+#define ICU_VEC_NUM_213 (213)
+#define ICU_VEC_NUM_214 (214)
+#define ICU_VEC_NUM_215 (215)
+#define ICU_VEC_NUM_216 (216)
+#define ICU_VEC_NUM_217 (217)
+#define ICU_VEC_NUM_218 (218)
+#define ICU_VEC_NUM_219 (219)
+#define ICU_VEC_NUM_220 (220)
+#define ICU_VEC_NUM_221 (221)
+#define ICU_VEC_NUM_222 (222)
+#define ICU_VEC_NUM_223 (223)
+#define ICU_VEC_NUM_224 (224)
+#define ICU_VEC_NUM_225 (225)
+#define ICU_VEC_NUM_226 (226)
+#define ICU_VEC_NUM_227 (227)
+#define ICU_VEC_NUM_228 (228)
+#define ICU_VEC_NUM_229 (229)
+#define ICU_VEC_NUM_230 (230)
+#define ICU_VEC_NUM_231 (231)
+#define ICU_VEC_NUM_232 (232)
+#define ICU_VEC_NUM_233 (233)
+#define ICU_VEC_NUM_234 (234)
+#define ICU_VEC_NUM_235 (235)
+#define ICU_VEC_NUM_236 (236)
+#define ICU_VEC_NUM_237 (237)
+#define ICU_VEC_NUM_238 (238)
+#define ICU_VEC_NUM_239 (239)
+#define ICU_VEC_NUM_240 (240)
+#define ICU_VEC_NUM_241 (241)
+#define ICU_VEC_NUM_242 (242)
+#define ICU_VEC_NUM_243 (243)
+#define ICU_VEC_NUM_246 (246)
+#define ICU_VEC_NUM_247 (247)
+#define ICU_VEC_NUM_248 (248)
+#define ICU_VEC_NUM_249 (249)
+#define ICU_VEC_NUM_250 (250)
+#define ICU_VEC_NUM_251 (251)
+#define ICU_VEC_NUM_252 (252)
+#define ICU_VEC_NUM_254 (254)
+#define ICU_VEC_NUM_256 (256)
+#define ICU_VEC_NUM_257 (257)
+#define ICU_VEC_NUM_258 (258)
+#define ICU_VEC_NUM_259 (259)
+#define ICU_VEC_NUM_260 (260)
+#define ICU_VEC_NUM_261 (261)
+#define ICU_VEC_NUM_262 (262)
+#define ICU_VEC_NUM_263 (263)
+#define ICU_VEC_NUM_264 (264)
+#define ICU_VEC_NUM_265 (265)
+#define ICU_VEC_NUM_266 (266)
+#define ICU_VEC_NUM_267 (267)
+#define ICU_VEC_NUM_268 (268)
+#define ICU_VEC_NUM_269 (269)
+#define ICU_VEC_NUM_270 (270)
+#define ICU_VEC_NUM_271 (271)
+#define ICU_VEC_NUM_272 (272)
+#define ICU_VEC_NUM_273 (273)
+#define ICU_VEC_NUM_274 (274)
+#define ICU_VEC_NUM_275 (275)
+#define ICU_VEC_NUM_276 (276)
+#define ICU_VEC_NUM_277 (277)
+#define ICU_VEC_NUM_278 (278)
+#define ICU_VEC_NUM_279 (279)
+#define ICU_VEC_NUM_280 (280)
+#define ICU_VEC_NUM_281 (281)
+#define ICU_VEC_NUM_282 (282)
+#define ICU_VEC_NUM_283 (283)
+#define ICU_VEC_NUM_284 (284)
+#define ICU_VEC_NUM_285 (285)
+#define ICU_VEC_NUM_286 (286)
+#define ICU_VEC_NUM_287 (287)
+#define ICU_VEC_NUM_288 (288)
+#define ICU_VEC_NUM_289 (289)
+#define ICU_VEC_NUM_290 (290)
+#define ICU_VEC_NUM_291 (291)
+#define ICU_VEC_NUM_292 (292)
+#define ICU_VEC_NUM_293 (293)
+#define ICU_VEC_NUM_294 (294)
+
+#define ICU_TYPE_LEVEL (0)
+#define ICU_TYPE_EDGE (1)
+
+#define ICU_PRIORITY_0 (0)
+#define ICU_PRIORITY_1 (1)
+#define ICU_PRIORITY_2 (2)
+#define ICU_PRIORITY_3 (3)
+#define ICU_PRIORITY_4 (4)
+#define ICU_PRIORITY_5 (5)
+#define ICU_PRIORITY_6 (6)
+#define ICU_PRIORITY_7 (7)
+#define ICU_PRIORITY_8 (8)
+#define ICU_PRIORITY_9 (9)
+#define ICU_PRIORITY_10 (10)
+#define ICU_PRIORITY_11 (11)
+#define ICU_PRIORITY_12 (12)
+#define ICU_PRIORITY_13 (13)
+#define ICU_PRIORITY_14 (14)
+#define ICU_PRIORITY_15 (15)
+
+#define ICU_IEC_MASK_SET (1)
+
+#define ICU_PIC_EDGE_CLEAR (1)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void R_ICU_Disable(uint32_t vec_num);
+void R_ICU_Enable(uint32_t vec_num);
+void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set);
+void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr);
+void R_ICU_Disable(uint32_t vec_num);
+void R_ICU_Enable(uint32_t vec_num);
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h
new file mode 100644
index 0000000000..cd9d589b87
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h
@@ -0,0 +1,118 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_mpc.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for MPC function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : MPC setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_MPC_HEADER_
+#define _R_MPC_HEADER_
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define MPC_IRQ_DISABLE (0)
+#define MPC_IRQ_ENABLE (1)
+
+#define MPC_PSEL_PT6_A21 (0x23)
+#define MPC_PSEL_PT7_A22 (0x23)
+#define MPC_PSEL_PK2_A23 (0x23)
+#define MPC_PSEL_PK3_A24 (0x23)
+#define MPC_PSEL_P97_A25 (0x23)
+#define MPC_PSEL_P36_WE0_DQMLL (0x22)
+#define MPC_PSEL_P37_WE1_DQMLU (0x22)
+#define MPC_PSEL_PD1_CS1 (0x23)
+#define MPC_PSEL_P45_CS2 (0x22)
+#define MPC_PSEL_PT4_CS3 (0x23)
+#define MPC_PSEL_P90_RAS (0x23)
+#define MPC_PSEL_PK0_CAS (0x23)
+#define MPC_PSEL_P24_RD_WR (0x22)
+#define MPC_PSEL_P46_CKE (0x22)
+#define MPC_PSEL_P10_CKIO (0x22)
+#define MPC_PSEL_P23_A0 (0x22)
+#define MPC_PSEL_PG0_A1 (0x22)
+#define MPC_PSEL_PG1_A2 (0x22)
+#define MPC_PSEL_PG2_A3 (0x22)
+#define MPC_PSEL_PG3_A4 (0x22)
+#define MPC_PSEL_PG4_A5 (0x22)
+#define MPC_PSEL_PG5_A6 (0x22)
+#define MPC_PSEL_PG6_A7 (0x22)
+#define MPC_PSEL_PG7_A8 (0x22)
+#define MPC_PSEL_PH0_A9 (0x22)
+#define MPC_PSEL_PH1_A10 (0x22)
+#define MPC_PSEL_PH2_A11 (0x22)
+#define MPC_PSEL_PH3_A12 (0x22)
+#define MPC_PSEL_PH4_A13 (0x22)
+#define MPC_PSEL_PH5_A14 (0x22)
+#define MPC_PSEL_PH6_A15 (0x22)
+#define MPC_PSEL_PH7_A16 (0x22)
+#define MPC_PSEL_P20_A17 (0x22)
+#define MPC_PSEL_P25_A18 (0x22)
+#define MPC_PSEL_P26_A19 (0x22)
+#define MPC_PSEL_P27_A20 (0x22)
+#define MPC_PSEL_P00_D0 (0x22)
+#define MPC_PSEL_P01_D1 (0x22)
+#define MPC_PSEL_P02_D2 (0x22)
+#define MPC_PSEL_P03_D3 (0x22)
+#define MPC_PSEL_P04_D4 (0x22)
+#define MPC_PSEL_P05_D5 (0x22)
+#define MPC_PSEL_P06_D6 (0x22)
+#define MPC_PSEL_P07_D7 (0x22)
+#define MPC_PSEL_PE0_D8 (0x22)
+#define MPC_PSEL_PE1_D9 (0x22)
+#define MPC_PSEL_PE2_D10 (0x22)
+#define MPC_PSEL_PE3_D11 (0x22)
+#define MPC_PSEL_PE4_D12 (0x22)
+#define MPC_PSEL_PE5_D13 (0x22)
+#define MPC_PSEL_PE6_D14 (0x22)
+#define MPC_PSEL_PE7_D15 (0x22)
+#define MPC_PSEL_P22_RD (0x22)
+#define MPC_PSEL_P21_CS0 (0x22)
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void R_MPC_WriteEnable(void);
+void R_MPC_WriteDisable(void);
+
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h
new file mode 100644
index 0000000000..0142e53091
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h
@@ -0,0 +1,76 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_port.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for PORT function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : PORT setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_PORT_HEADER_
+#define _R_PORT_HEADER_
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define PORT_DIRECTION_HIZ (0)
+#define PORT_DIRECTION_INPUT (2)
+#define PORT_DIRECTION_OUTPUT (3)
+
+#define PORT_OUTPUT_LOW (0)
+#define PORT_OUTPUT_HIGH (1)
+
+#define PORT_MODE_GENERAL (0)
+#define PORT_MODE_PERIPHERAL (1)
+
+#define PORT_PULL_UPDOWN_DISABLE (0)
+#define PORT_PULL_DOWN (1)
+#define PORT_PULL_UP (2)
+
+#define PORT_P10_NORMAL_DRIVE (0)
+#define PORT_P10_HIGH_DRIVE (1)
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h
new file mode 100644
index 0000000000..abcf59702e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h
@@ -0,0 +1,64 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_ram.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for internal extended RAM function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : Internal extended RAM setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_RAM_HEADER_
+#define _R_RAM_HEADER_
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void R_RAM_Init(void);
+void R_RAM_ECC_Enable(void);
+void R_RAM_WriteEnable(void);
+void R_RAM_WriteDisable(void);
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h
new file mode 100644
index 0000000000..06f6e3438f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h
@@ -0,0 +1,64 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_reset.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for reset function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : Reset function API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_RESET_HEADER_
+#define _R_RESET_HEADER_
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define RST_SOURCE_RES (0x00000002)
+#define RST_SOURCE_ECM (0x00000004)
+#define RST_SOURCE_SWR1 (0x00000008)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void r_rst_write_enable(void);
+void r_rst_write_disable(void);
+
+#endif
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h
new file mode 100644
index 0000000000..9278ef210c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_system.h
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : Definition for System
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : Define the system settings ans value.
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+#ifndef _R_SYSTEM_HEADER_
+#define _R_SYSTEM_HEADER_
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0
+#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1
+#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4
+#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5
+#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6
+#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7
+#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8
+#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11
+
+#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1
+#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3
+#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5
+#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6
+#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7
+#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8
+#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9
+#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10
+#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11
+#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13
+#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14
+#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15
+#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16
+#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17
+#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18
+#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19
+
+#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1
+#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2
+#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3
+#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4
+#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5
+#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6
+#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7
+#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8
+#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9
+#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10
+#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11
+#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12
+#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13
+#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14
+
+#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2
+
+#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4
+#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5
+
+#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0
+
+#define __MSTP( x ) MSTP ## x
+#define _MSTP( x ) __MSTP( x )
+#define MSTP( x ) _MSTP( _ ## x )
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+#endif // End _R_SYSTEM_HEADER_
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/gnu_io.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h
similarity index 54%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/gnu_io.c
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h
index 3d46282fe1..a4a339423d 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/gnu_io.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h
@@ -19,86 +19,61 @@
* following link:
* http://www.renesas.com/disclaimer
*
-****************************************************************************************************************************************************************/
-/****************************************************************************************************************************************************************
-* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
-****************************************************************************************************************************************************************/
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
/***********************************************************************************************************************
-* File Name : gnu_io.c
-* Device(s) : RZ/A1H RSK+T1
+* File Name : r_typedefs.h
+* Device(s) : RZ/A1H (R7S910018)
* Tool-Chain : GNUARM-NONEv14.02-EABI
* H/W Platform : RSK+T1 CPU Board
-* Description : Sample Program - GCC support for serial I/O
-* : Variants of this file can be created for each compiler
+* Description : basic type definition
***********************************************************************************************************************/
/***********************************************************************************************************************
* History : DD.MM.YYYY Version Description
-* : 21.05.2015 1.00
+* : 21.10.2014 1.00
***********************************************************************************************************************/
-/***********************************************************************************************************************
-Includes , "Project Includes"
-***********************************************************************************************************************/
-/* Standard IO header */
-#include
-/* Default type definition header */
-#include "r_typedefs.h"
-/* Character I/O header */
-#include "siochar.h"
-/* I/O Register root header */
-#include "iodefine.h"
-/* Compiler specific UART i/O support header */
-#include "gnu_io.h"
-
/***********************************************************************************************************************
-* Function Name: put_string
-* Description : GNU interface to low-level I/O putchar replacement
-* Arguments : char * pString
-* Return Value : none
+Includes , "Project Includes"
***********************************************************************************************************************/
-void put_string (char *pString)
-{
- while(0 != (*pString))
- {
- io_put_char(*pString++);
- }
-}
+#include
+/* Multiple inclusion prevention macro */
+#ifndef R_TYPEDEFS_H
+#define R_TYPEDEFS_H
-/***********************************************************************************************************************
- End of function put_string
-***********************************************************************************************************************/
+
+/* in case has defined it. */
+#ifndef NULL
+#define NULL (0)
+#endif
/***********************************************************************************************************************
-* Function Name: get_string
-* Description : GNU interface to low-level I/O getchar replacement
-* Arguments : char * pString
-* Return Value : none
+Macro definitions
***********************************************************************************************************************/
-void get_string (char * pString)
-{
- char * ptr = pString;
+#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus)
- do
- {
- (*ptr) = io_get_char();
+#define FALSE (0)
+#define TRUE (1)
- io_put_char(*ptr);
+#endif
- if('\r' == (*ptr))
- {
- (*ptr) = 0;
-
- /* This is intentional since no more input is expected */
- break;
- }
- }
- while('\0' != (*ptr++));
- io_put_char('\r');
- io_put_char('\n');
-}
+/* These two macros are used to suppress warnings generated by unused variables.
+ Writing to some registers require a read instruction following the write.
+ A dummy variable is declared and used to read the register written to. */
+#define UNUSED_PARAM(param) ((void)(param))
+#define UNUSED_VARIABLE(param) ((void)(param))
/***********************************************************************************************************************
- End of function get_string
+Typedef definitions
***********************************************************************************************************************/
+typedef char char_t;
+typedef unsigned int bool_t;
+typedef int int_t;
+typedef float float32_t;
+typedef double float64_t;
+typedef long double float128_t;
+
+/* R_TYPEDEFS_H */
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf
new file mode 100644
index 0000000000..2e86388b67
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf
@@ -0,0 +1,163 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x40020040;
+define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x00070000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_svcstack__ = 0x200;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define symbol __region_USER_PRG_start__ = 0x00000040;
+define symbol __region_USER_PRG_end__ = 0x0006FFFF;
+
+define symbol __region_D_LDR_DATA_start__ = 0x00800000;
+define symbol __region_D_LDR_DATA_end__ = 0x00801FFF;
+define symbol __region_D_LDR_PRG_start__ = 0x00802000;
+define symbol __region_D_LDR_PRG_end__ = 0x00807FFF;
+
+define symbol __region_D_LDR_M3PRG_start__ = 0x04000000;
+define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF;
+
+define symbol __region_S_LDR_M3PRG_start__ = 0x00050000;
+define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF;
+
+define symbol __region_EXT_RAM1_start__ = 0x22000000;
+define symbol __region_EXT_RAM1_end__ = 0x2207FFFF;
+define symbol __region_EXT_RAM2_start__ = 0x24000000;
+define symbol __region_EXT_RAM2_end__ = 0x2407FFFF;
+define symbol __region_SPIBSC_start__ = 0x30000000;
+define symbol __region_SPIBSC_end__ = 0x33FFFFFF;
+
+define symbol __region_CS0_start__ = 0x40000000;
+define symbol __region_CS0_end__ = 0x43FFFFFF;
+define symbol __region_CS1_start__ = 0x44000000;
+define symbol __region_CS1_end__ = 0x47FFFFFF;
+define symbol __region_CS2_start__ = 0x48000000;
+define symbol __region_CS2_end__ = 0x4BFFFFFF;
+define symbol __region_CS3_start__ = 0x4C000000;
+define symbol __region_CS3_end__ = 0x4FFFFFFF;
+define symbol __region_CS4_start__ = 0x50000000;
+define symbol __region_CS4_end__ = 0x53FFFFFF;
+define symbol __region_CS5_start__ = 0x54000000;
+define symbol __region_CS5_end__ = 0x57FFFFFF;
+
+define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__];
+define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__];
+define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__];
+
+define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__];
+define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__];
+
+define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__];
+define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__];
+define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__];
+define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__];
+define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__];
+define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__];
+define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__];
+define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__];
+define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+
+define block LDR_PRG_RBLOCK with fixed order
+ { ro code object loader_init.o,
+ ro code object loader_init2.o,
+ ro code object r_atcm_init.o,
+ ro code object r_cpg.o,
+ ro code object r_ram_init.o,
+ ro code object r_mpc.o,
+ ro code object r_reset.o,
+ ro code object data_init.o,
+ ro code object copy_init3.o };
+define block LDR_DATA_ZBLOCK { section .bss object loader_init.o,
+ section .bss object loader_init2.o,
+ section .bss object r_atcm_init.o,
+ section .bss object r_cpg.o,
+ section .bss object r_ram_init.o,
+ section .bss object r_mpc.o,
+ section .bss object r_reset.o,
+ section .bss object data_init.o,
+ section .bss object copy_init3.o };
+define block LDR_DATA_RBLOCK { section .data_init object loader_init.o,
+ section .data_init object loader_init2.o,
+ section .data_init object r_atcm_init.o,
+ section .data_init object r_cpg.o,
+ section .data_init object r_ram_init.o,
+ section .data_init object r_mpc.o,
+ section .data_init object r_reset.o,
+ section .data_init object data_init.o,
+ section .data_init object copy_init3.o };
+define block LDR_DATA_WBLOCK { section .data object loader_init.o,
+ section .data object loader_init2.o,
+ section .data object r_atcm_init.o,
+ section .data object r_cpg.o,
+ section .data object r_ram_init.o,
+ section .data object r_mpc.o,
+ section .data object r_reset.o,
+ section .data object data_init.o,
+ section .data object copy_init3.o };
+define block VECTOR_RBLOCK { ro code object vector.o };
+define block USER_PRG_RBLOCK { ro code };
+define block USER_DATA_ZBLOCK { section .bss };
+define block USER_DATA_RBLOCK { section .data_init };
+define block USER_DATA_WBLOCK { section .data };
+
+define block M3_PRG_RBLOCK { section __M3prg_init };
+define block M3_PRG_WBLOCK { section __M3prg };
+
+initialize by copy { readwrite };
+
+do not initialize { section .noinit, section .bss };
+
+initialize manually { section __M3prg };
+
+place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK };
+
+place in USER_PRG_region { block USER_PRG_RBLOCK,
+ block USER_DATA_RBLOCK,
+ readonly };
+place in RAM_region { readwrite };
+place in RAM_region { block USER_DATA_WBLOCK,
+ block USER_DATA_ZBLOCK,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP };
+place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK };
+place in D_LDR_PRG_region { block LDR_PRG_RBLOCK,
+ block LDR_DATA_RBLOCK };
+
+place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK };
+place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK };
+
+place in EXT_RAM1_region {};
+place in EXT_RAM2_region {};
+place in SPIBSC_region {};
+place in CS0_region {};
+place in CS1_region {};
+place in CS2_region {};
+place in CS3_region {};
+place in CS4_region {};
+place in CS5_region {};
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c
new file mode 100644
index 0000000000..19b107e4bd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : exit.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : exit program
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : exit sequence from main function
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+
+/*******************************************************************************
+* Outline : exit processing
+* Function Name: __exit
+* Description : exit sequence from main function.
+* Arguments : code
+* The return value of main function.
+* Return Value : none
+*******************************************************************************/
+void __exit(int code)
+{
+
+ while (1)
+ {
+ /* Please describe the exit sequence */
+ }
+
+}
+/*******************************************************************************
+ End of function __exit
+*******************************************************************************/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm
new file mode 100644
index 0000000000..fe8b0fe71d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm
@@ -0,0 +1,371 @@
+;*******************************************************************************
+; DISCLAIMER
+; This software is supplied by Renesas Electronics Corporation and is only
+; intended for use with Renesas products. No other uses are authorized. This
+; software is owned by Renesas Electronics Corporation and is protected under
+; all applicable laws, including copyright laws.
+; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; Renesas reserves the right, without notice, to make changes to this software
+; and to discontinue the availability of this software. By using this software,
+; you agree to the additional terms and conditions found by accessing the
+; following link:
+; http://www.renesas.com/disclaimer
+;
+; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+;******************************************************************************
+;*******************************************************************************
+; System Name : RZ/T1 Init program
+; File Name : loader_init.asm
+; Version : 0.1
+; Device : R7S9100xx
+; Abstract : Loader program 1
+; Tool-Chain : IAR Embedded Workbench Ver.7.20
+; OS : not use
+; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+; Description : Description interrupt service routine of RZ/T1
+; Limitation : none
+;******************************************************************************
+;*******************************************************************************
+; History : DD.MM.YYYY Version Description
+; : First Release
+;******************************************************************************
+
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION LDR_DATA_RBLOCK:DATA:ROOT(2)
+ SECTION LDR_DATA_WBLOCK:DATA:ROOT(2)
+
+ SECTION M3_PRG_RBLOCK:DATA:ROOT(2)
+ SECTION M3_PRG_WBLOCK:DATA:ROOT(2)
+
+; This program is allocated to section "d_ldr_prg"
+ SECTION d_ldr_prg:CODE:ROOT(2)
+
+ ARM
+
+ PUBLIC loader_init1
+ PUBLIC set_low_vec
+ PUBLIC cache_init
+ PUBLIC mpu_init
+ IMPORT loader_init2
+
+
+;***********************************************************************
+; Function Name : loader_init1
+; Description : Initialize sysytem by loader program
+; Arguments : none
+; Return Value : none
+;***********************************************************************
+loader_init1:
+
+stack_init:
+ ; Stack setting
+ cps #17 ; FIQ mode
+ ldr sp, =SFE(FIQ_STACK)
+ cps #18 ; IRQ mode
+ ldr sp, =SFE(IRQ_STACK)
+ cps #23 ; Abort mode
+ ldr sp, =SFE(ABT_STACK)
+ cps #27 ; Undef mode
+ ldr sp, =SFE(UND_STACK)
+ cps #31 ; System mode
+ ldr sp, =SFE(CSTACK)
+ cps #19 ; SVC mode
+ ldr sp, =SFE(SVC_STACK)
+
+vfp_init:
+ ; Initialize VFP setting
+ mrc p15, #0, r0, c1, c0, #2 ; Enables cp10 and cp11 accessing
+ orr r0, r0, #0xF00000
+ mcr p15, #0, r0, c1, c0, #2
+ isb ; Ensuring Context-changing
+
+ mov r0, #0x40000000 ; Enables VFP operation
+ vmsr fpexc, r0
+
+data_init:
+ ; Initialize variables has initialized value of loader_init2.
+ ; Variables has no initialized value already be initialized to zero
+ ; in boot sequence(Clear ATCM and BTCM).
+ ldr r0, =SFB(LDR_DATA_RBLOCK)
+ ldr r1, =SFB(LDR_DATA_WBLOCK)
+ ldr r2, =SIZEOF(LDR_DATA_WBLOCK)
+ cmp r2, #0
+#ifdef DUAL_CORE
+ beq m3_init
+#else
+ beq jump_loader_init2
+#endif
+
+copy_to_LDR_DATA:
+ ldrb r3, [r0], #1
+ strb r3, [r1], #1
+ subs r2, r2, #1
+ bne copy_to_LDR_DATA
+ dsb ; Ensuring data-changing
+
+#ifdef DUAL_CORE
+
+m3_init:
+ ; Initialize image for Cortex-M3 core
+ ldr r0, =SFB(M3_PRG_RBLOCK)
+ ldr r1, =SFB(M3_PRG_WBLOCK)
+ ldr r2, =SIZEOF(M3_PRG_WBLOCK)
+ cmp r2, #0
+ beq jump_loader_init2
+
+copy_to_M3_PRG:
+ ldrb r3, [r0], #1
+ strb r3, [r1], #1
+ subs r2, r2, #1
+ bne copy_to_M3_PRG
+ dsb ; Ensuring data-changing
+
+#endif
+
+ ; Jump to loader_init2
+jump_loader_init2:
+ ldr r0, =loader_init2
+ bx r0
+
+;***********************************************************************
+; Function Name : cache_init
+; Description : Initialize I1, D1 cache and MPU settings
+; Arguments : none
+; Return Value : none
+;***********************************************************************
+
+;*******************************************************************************
+; Macro definitions
+;*******************************************************************************
+
+SCTLR_BR: dcd 0x00020000
+SCTLR_M: dcd 0x00000001
+SCTLR_I_C: dcd 0x00001004
+
+DRBAR_REGION_0: dcd 0x04000000 ; Base address = 0400_0000h
+DRACR_REGION_0: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
+DRSR_REGION_0: dcd 0x00000025 ; Size 512KB, MPU enable
+
+DRBAR_REGION_1: dcd 0x10000000 ; Base address = 1000_0000h
+DRACR_REGION_1: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
+DRSR_REGION_1: dcd 0x00000033 ; Size 64MB, MPU enable
+
+DRBAR_REGION_2: dcd 0x20000000 ; Base address = 2000_0000h
+DRACR_REGION_2: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
+DRSR_REGION_2: dcd 0x00000025 ; Size 512KB, MPU enable
+
+DRBAR_REGION_3: dcd 0x22000000 ; Base address = 2200_0000h
+DRACR_REGION_3: dcd 0x00000307 ; R/W(full), Normal, Write-back no allocate, share
+DRSR_REGION_3: dcd 0x00000033 ; Size 64MB, MPU enable
+
+DRBAR_REGION_4: dcd 0x30000000 ; Base address = 3000_0000h
+DRACR_REGION_4: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share
+DRSR_REGION_4: dcd 0x00000033 ; Size 64MB, MPU enable
+
+DRBAR_REGION_5: dcd 0x40000000 ; Base address = 4000_0000h
+DRACR_REGION_5: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share
+DRSR_REGION_5: dcd 0x00000035 ; Size 128MB, MPU enable
+
+DRBAR_REGION_6: dcd 0x48000000 ; Base address = 4800_0000h
+DRACR_REGION_6: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share
+DRSR_REGION_6: dcd 0x00000035 ; Size 128MB, MPU enable
+
+DRBAR_REGION_7: dcd 0x50000000 ; Base address = 5000_0000h
+DRACR_REGION_7: dcd 0x00001305 ; R/W(full), XN, Device, share
+DRSR_REGION_7: dcd 0x00000035 ; Size 128MB, MPU enable
+
+DRBAR_REGION_8: dcd 0x60000000 ; Base address = 6000_0000h
+DRACR_REGION_8: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
+DRSR_REGION_8: dcd 0x00000035 ; Size 128MB, MPU enable
+
+DRBAR_REGION_9: dcd 0x68000000 ; Base address = 6800_0000h
+DRACR_REGION_9: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share
+DRSR_REGION_9: dcd 0x00000035 ; Size 128MB, MPU enable
+
+DRBAR_REGION_10: dcd 0x70000000 ; Base address = 7000_0000h
+DRACR_REGION_10: dcd 0x00001305 ; R/W(full), XN, Device, share
+DRSR_REGION_10: dcd 0x00000035 ; Size 128MB, MPU enable
+
+DRBAR_REGION_11: dcd 0x80000000 ; Base address = 8000_0000h
+DRACR_REGION_11: dcd 0x00001305 ; R/W(full), XN, Device, share
+DRSR_REGION_11: dcd 0x0000003D ; Size 2GB, MPU enable
+
+cache_init:
+ push {lr}
+
+cache_invalidate:
+ ; Invalidate the I1, D1 cache
+ mov r0, #0
+ mcr p15, #0, r0, c7, c5, #0 ; Invalidate all Instruction Caches (Write-value is Ignored)
+ isb ; Ensuring Context-changing
+ mcr p15, #0, r0, c15, c5, #0 ; Invalidate all Data Caches (Write-value is Ignored)
+ isb ; Ensuring Context-changing
+
+ ; Adopt default memory map as background map.
+ ldr r0, SCTLR_BR ; Set SCTLR.BR bit to 1
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, r0
+ dsb
+ mcr p15, 0, r1, c1, c0, 0
+ isb ; Ensuring Context-changing
+
+ ; Initialize MPU settings (region 0 to 11)
+ ; Define region 0
+ mov r0, #0
+ ldr r1, DRBAR_REGION_0
+ ldr r2, DRACR_REGION_0
+ ldr r3, DRSR_REGION_0
+ bl mpu_init
+
+ ; Define region 1
+ mov r0, #1
+ ldr r1, DRBAR_REGION_1
+ ldr r2, DRACR_REGION_1
+ ldr r3, DRSR_REGION_1
+ bl mpu_init
+
+ ; Define region 2
+ mov r0, #2
+ ldr r1, DRBAR_REGION_2
+ ldr r2, DRACR_REGION_2
+ ldr r3, DRSR_REGION_2
+ bl mpu_init
+
+ ; Define region 3
+ mov r0, #3
+ ldr r1, DRBAR_REGION_3
+ ldr r2, DRACR_REGION_3
+ ldr r3, DRSR_REGION_3
+ bl mpu_init
+
+ ; Define region 4
+ mov r0, #4
+ ldr r1, DRBAR_REGION_4
+ ldr r2, DRACR_REGION_4
+ ldr r3, DRSR_REGION_4
+ bl mpu_init
+
+ ; Define region 5
+ mov r0, #5
+ ldr r1, DRBAR_REGION_5
+ ldr r2, DRACR_REGION_5
+ ldr r3, DRSR_REGION_5
+ bl mpu_init
+
+ ; Define region 6
+ mov r0, #6
+ ldr r1, DRBAR_REGION_6
+ ldr r2, DRACR_REGION_6
+ ldr r3, DRSR_REGION_6
+ bl mpu_init
+
+ ; Define region 7
+ mov r0, #7
+ ldr r1, DRBAR_REGION_7
+ ldr r2, DRACR_REGION_7
+ ldr r3, DRSR_REGION_7
+ bl mpu_init
+
+ ; Define region 8
+ mov r0, #8
+ ldr r1, DRBAR_REGION_8
+ ldr r2, DRACR_REGION_8
+ ldr r3, DRSR_REGION_8
+ bl mpu_init
+
+ ; Define region 9
+ mov r0, #9
+ ldr r1, DRBAR_REGION_9
+ ldr r2, DRACR_REGION_9
+ ldr r3, DRSR_REGION_9
+ bl mpu_init
+
+ ; Define region 10
+ mov r0, #10
+ ldr r1, DRBAR_REGION_10
+ ldr r2, DRACR_REGION_10
+ ldr r3, DRSR_REGION_10
+ bl mpu_init
+
+ ; Define region 11
+ mov r0, #11
+ ldr r1, DRBAR_REGION_11
+ ldr r2, DRACR_REGION_11
+ ldr r3, DRSR_REGION_11
+ bl mpu_init
+
+ ; Enables MPU operation
+ ldr r0, SCTLR_M ; Set SCTLR.M bit to 1
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, r0
+ dsb
+ mcr p15, 0, r1, c1, c0, 0
+ isb ; Ensuring Context-changing
+
+ ; Enables I1,D1 cache operation
+ ldr r0, SCTLR_I_C ; Set SCTLR.I and C bit to 1
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, r0
+ dsb
+ mcr p15, 0, r1, c1, c0, 0
+ isb ; Ensuring Context-changing
+
+ pop {pc}
+ bx lr
+
+;***********************************************************************
+; Function Name : mpu_init
+; Description : Initialize MPU settings
+; Arguments : none
+; Return Value : none
+;***********************************************************************
+mpu_init:
+ ; RGNR(MPU Memory Region Number Register)
+ mcr p15, #0, r0, c6, c2, #0
+ isb ; Ensuring Context-changing
+
+ ; DRBAR(Data Region Base Address Register)
+ mcr p15, #0, r1, c6, c1, #0
+ isb ; Ensuring Context-changing
+
+ ; DRACR(Data Region Access Control Register)
+ mcr p15, #0, r2, c6, c1, #4
+ isb ; Ensuring Context-changing
+
+ ; DRSR(Data Region Size and Enable Register)
+ mcr p15, #0, r3, c6, c1, #2
+ isb ; Ensuring Context-changing
+
+ bx lr
+
+
+;***********************************************************************
+; Function Name : set_low_vec
+; Description : Initialize sysytem by loader program
+; Arguments : none
+; Return Value : none
+;***********************************************************************
+set_low_vec:
+ mrc p15, 0, r0, c1, c0, 0 ; Set SCTLR.V bit to 1 (low-vector)
+ and r0, r0, #0xFFFFDFFF
+ mcr p15, 0, r0, c1, c0, 0
+ isb ; Ensuring Context-changing
+
+ bx lr
+
+ END
+; End of File
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c
new file mode 100644
index 0000000000..6593ad61f0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c
@@ -0,0 +1,233 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : loader_init2.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : Loader program 2
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : Initialize the peripheral settings of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+#ifdef __ICCARM__
+
+#pragma section="VECTOR_RBLOCK"
+#pragma section="VECTOR_WBLOCK"
+#pragma section="USER_PRG_RBLOCK"
+#pragma section="USER_PRG_WBLOCK"
+#pragma section="USER_DATA_RBLOCK"
+#pragma section="USER_DATA_WBLOCK"
+
+#endif // __ICCARM__
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_system.h"
+#include "r_reset.h"
+#include "r_cpg.h"
+#include "r_atcm_init.h"
+#include "r_port.h"
+#include "r_mpc.h"
+#include "r_ecm.h"
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int _main(void);
+extern void bus_init(void);
+extern void set_low_vec(void);
+extern void cache_init(void);
+extern void __iar_data_init3(void);
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+void loader_init2(void);
+void reset_check(void);
+void cpg_init(void);
+
+/*******************************************************************************
+* Function Name : loader_init2
+* Description : Initialize sysytem by loader program 2
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void loader_init2(void)
+{
+ /* Check the reset source */
+ reset_check();
+
+ /* Set CPU clock and LOCO clock */
+ cpg_init();
+
+ /* Set ATCM access wait to 1-wait with optimization */
+ /* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz.
+ ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/
+ R_ATCM_WaitSet(ATCM_WAIT_1_OPT);
+
+ /* Copy the variable data */
+ __iar_data_init3();
+
+ /* Initialize I1, D1 Cache and MPU setting */
+ cache_init();
+
+ /* Set RZ/T1 to Low-vector (SCTLR.V = 0) */
+ set_low_vec();
+
+ /* Jump to _main() */
+ _main();
+
+}
+
+/*******************************************************************************
+ End of function loader_init2
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : reset_check
+* Description : Check the reset source and execute the each sequence.
+* When error source number 35 is generated, set P77 pin to High.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void reset_check(void)
+{
+ volatile uint8_t result;
+ volatile uint32_t dummy;
+
+ /* Check the reset status flag and execute the each sequence */
+ if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG) // ECM reset is generated
+ {
+ /* Clear reset status flag */
+ r_rst_write_enable(); // Enable writing to the RSTSR0 register
+ SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag
+ r_rst_write_disable(); // Disable writing to the RSTSR0 register
+
+ /* Please coding the User program */
+
+ }
+ else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG) // Software reset 1 is generated
+ {
+ /* Clear reset status flag */
+ r_rst_write_enable(); // Enable writing to the RSTSR0 register
+ SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag
+ r_rst_write_disable(); // Disable writing to the RSTSR0 register
+
+ /* Please coding the User program */
+
+ }
+ else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated
+ {
+ /* Clear reset status flag */
+ r_rst_write_enable(); // Enable writing to the RSTSR0 register
+ SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag
+ r_rst_write_disable(); // Disable writing to the RSTSR0 register
+
+ /* Please coding the User program */
+
+ }
+ else // Any reset is not generated
+ {
+ /* Please coding the User program */
+ }
+
+}
+
+/*******************************************************************************
+ End of function reset_check
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : cpg_init
+* Description : Set CPU clock and LOCO clock by CPG function
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void cpg_init(void)
+{
+ volatile uint32_t dummy;
+
+ /* Enables writing to the registers related to CPG function */
+ R_CPG_WriteEnable();
+
+ /* Enables LOCO clock operation */
+ SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE;
+
+ /* Set CPUCLK to 450MHz, and dummy read at three times */
+ SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz;
+ dummy = SYSTEM.PLL1CR.LONG;
+ dummy = SYSTEM.PLL1CR.LONG;
+ dummy = SYSTEM.PLL1CR.LONG;
+
+ /* Enables PLL1 operation */
+ SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON;
+
+ /* Disables writing to the registers related to CPG function */
+ R_CPG_WriteDisable();
+
+ /* Wait about 100us for PLL1 (and LOCO) stabilization */
+ R_CPG_PLL_Wait();
+
+ /* Enables writing to the registers related to CPG function */
+ R_CPG_WriteEnable();
+
+ /* Selects the PLL1 as clock source */
+ SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1;
+
+ /* Disables writing to the registers related to CPG function */
+ R_CPG_WriteDisable();
+
+}
+
+/*******************************************************************************
+ End of function cpg_init
+*******************************************************************************/
+
+
+/* End of File */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c
new file mode 100644
index 0000000000..e15bf7bf8b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c
@@ -0,0 +1,108 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_atcm_init.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for ATCM function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : ATCM access wait setting API of RZ/T1
+* Limitation : This wait setting could not be executed in ATCM program area.
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_system.h"
+#include "r_atcm_init.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define ATCM_WRITE_ENABLE (0x0000A508)
+#define ATCM_WRITE_DISABLE (0x0000A500)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+* Function Name : R_ATCM_WaitSet
+* Description : Sets ATCM access wait.
+* Arguments : atcm_wait
+* Wait settings for ATCM access
+* Return Value : none
+*******************************************************************************/
+void R_ATCM_WaitSet(uint32_t atcm_wait)
+{
+ volatile uint32_t dummy;
+
+ /* Enables writing to the ATCM register */
+ SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE;
+ dummy = SYSTEM.PRCR.LONG;
+
+ /* Sets ATCM access wait to atcm_wait value */
+ SYSTEM.SYTATCMWAIT.LONG = atcm_wait;
+
+ /* Disables writing to the ATCM register */
+ SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE;
+ dummy = SYSTEM.PRCR.LONG;
+
+}
+
+/*******************************************************************************
+ End of function R_ATCM_WaitSet
+*******************************************************************************/
+
+/* End of File */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c
new file mode 100644
index 0000000000..17775f8bdf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c
@@ -0,0 +1,162 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_cpg.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for CPG function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : CPG setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_system.h"
+#include "r_cpg.h"
+#include "r_reset.h"
+#include "r_icu_init.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define CPG_WRITE_ENABLE (0x0000A501)
+#define CPG_WRITE_DISABLE (0x0000A500)
+
+#define CPG_CMT0_CLOCK_PCLKD_32 (1)
+#define CPG_CMT0_CMI0_ENABLE (1)
+#define CPG_CMT0_CONST_100_us (0xEA)
+#define CPG_CMT0_START (1)
+#define CPG_CMT0_STOP (0)
+
+#define CPG_CMT_REG_CLEAR (0x0000)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name : R_CPG_PLL_Wait
+* Description : Wait about 100us for PLL stabilization by using CMT0
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void R_CPG_PLL_Wait(void)
+{
+
+ /* Enables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_enable();
+
+ /* Release from the CMT0 module-stop state */
+ MSTP(CMT0) = 0;
+
+ /* Disables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_disable();
+
+ /* Set CMT0 to 100us interval operation */
+ CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32
+ CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt
+ CMT0.CMCNT = CPG_CMT_REG_CLEAR; // Clear CMCNT counter
+ CMT0.CMCOR = CPG_CMT0_CONST_100_us; // Set constant value for 100us
+
+
+ /* Set IRQ21(CMI0) for polloing sequence */
+ VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt
+ VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt
+ VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
+
+ /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */
+ asm("cpsie i"); // Clear CPSR.I bit to 0
+ asm("isb"); // Ensuring Context-changing
+
+ /* Start CMT0 count */
+ CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START;
+
+ /* Wait for 100us (IRQ21 is generated) */
+ while ( !(VIC.RAIS0.BIT.RAI21) )
+ {
+ /* Wait */
+ }
+
+ /* Stop CMT0 count */
+ CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP;
+
+ /* Initialize CMT0 settings and clear interrupt detection edge */
+ CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR;
+ CMT0.CMCNT = CPG_CMT_REG_CLEAR;
+ CMT0.CMCOR = CPG_CMT_REG_CLEAR;
+ CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR;
+
+ VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
+
+
+ /* Disable IRQ interrupt (Set CPSR.I bit to 1) */
+ asm("cpsid i");
+ asm("isb");
+
+ /* Enables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_enable();
+
+ /* Set CMT0 to module-stop state */
+ MSTP(CMT0) = 1;
+
+ /* Disables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_disable();
+
+
+}
+
+/*******************************************************************************
+ End of function R_CPG_PLL_Wait
+*******************************************************************************/
+
+/* End of File */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c
new file mode 100644
index 0000000000..c68b80dfba
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c
@@ -0,0 +1,289 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_ecm.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for ECM function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : ECM API of RZ/T1
+* Limitation : LOCO operation is necessary for clearing ERROROUT# pin.
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_system.h"
+#include "r_ecm.h"
+#include "r_reset.h"
+#include "r_icu_init.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define ECM_CMT0_CLOCK_PCLKD_32 (1)
+#define ECM_CMT0_CMI0_ENABLE (1)
+#define ECM_CMT0_CONST_15_us (0x22)
+#define ECM_CMT0_START (1)
+#define ECM_CMT0_STOP (0)
+
+#define ECM_CMT_REG_CLEAR (0x0000)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+static uint32_t *g_pcmd_reg_adrr[ECM_TYPE_MAX] =
+{
+ (uint32_t *) &ECMM.ECMMPCMD0.LONG,
+ (uint32_t *) &ECMC.ECMCPCMD0.LONG,
+ (uint32_t *) &ECM.ECMPCMD1.LONG
+};
+
+/*******************************************************************************
+* Function Name : R_ECM_Init
+* Description : Initialize ECM function.
+* - Clear all error source
+* - Clear ERROROUT# pin output to in-active (High) level.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void R_ECM_Init(void)
+{
+ volatile uint8_t result;
+
+ /* Clear all error source (ECMESSTC0, ECMESSTC1, ECMESSTC2) */
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC0.LONG), 0xDFFFFFF7);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC1.LONG), 0x000001FF);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x70000000);
+
+ /* Mask all error source (ECMEMK0, ECMEMK1, ECMEMK2) for clearing ERROROUT# */
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0xDFFFFFF7);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x000001FF);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x30000000);
+
+ /* Mask ECM maskable, non-maskable interrupt and ECM reset of ECM compare match
+ error (ECMMICFG2, ECMNMICFG2, ECMIRCFG2) */
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMMICFG2.LONG), 0x00000000);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMNMICFG2.LONG), 0x00000000);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMIRCFG2.LONG), 0x00000000);
+
+ /* Clear ERROROUT# pin output to in-active (High) level */
+ result = R_ECM_Write_Reg8(ECM_MASTER, &(ECMM.ECMMECLR.BYTE), 0x01);
+ result = R_ECM_Write_Reg8(ECM_CHECKER, &(ECMC.ECMCECLR.BYTE), 0x01);
+
+ /* Wait 15us for ECM compare error stabilization */
+ R_ECM_CompareError_Wait();
+
+ /* Clear ECM compare error (ECMESSTC2) again */
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x10000000);
+
+ /* Initialize the all error mask settings (ECMEMK0, ECMEMK1, ECMEMK2) */
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0x00000000);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x00000000);
+ result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x00000000);
+
+}
+
+/*******************************************************************************
+ End of function R_ECM_Init
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : R_ECM_CompareError_Wait
+* Description : Wait about 15 us for ECM compare error stabilizeation by using CMT0
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void R_ECM_CompareError_Wait(void)
+{
+ /* Enables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_enable();
+
+ /* Release from the CMT0 module-stop state */
+ MSTP(CMT0) = 0;
+
+ /* Disables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_disable();
+
+ /* Set CMT0 to 100us interval operation */
+ CMT0.CMCR.BIT.CKS = ECM_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32
+ CMT0.CMCR.BIT.CMIE = ECM_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt
+ CMT0.CMCNT = ECM_CMT_REG_CLEAR; // Clear CMCNT counter
+ CMT0.CMCOR = ECM_CMT0_CONST_15_us; // Set constant value for 15us
+
+
+ /* Set IRQ21(CMI0) for polloing sequence */
+ VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt
+ VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt
+ VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
+
+ /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */
+ asm("cpsie i"); // Clear CPSR.I bit to 0
+ asm("isb"); // Ensuring Context-changing
+
+ /* Start CMT0 count */
+ CMT.CMSTR0.BIT.STR0 = ECM_CMT0_START;
+
+ /* Wait for 15us (IRQ21 is generated) */
+ while ( ! (VIC.RAIS0.BIT.RAI21) )
+ {
+ /* Wait */
+ }
+
+ /* Stop CMT0 count */
+ CMT.CMSTR0.BIT.STR0 = ECM_CMT0_STOP;
+
+ /* Initialize CMT0 settings and clear interrupt detection edge */
+ CMT0.CMCR.WORD = ECM_CMT_REG_CLEAR;
+ CMT0.CMCNT = ECM_CMT_REG_CLEAR;
+ CMT0.CMCOR = ECM_CMT_REG_CLEAR;
+ CMT.CMSTR0.WORD = ECM_CMT_REG_CLEAR;
+
+ VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
+
+
+ /* Disable IRQ interrupt (Set CPSR.I bit to 1) */
+ asm("cpsid i");
+ asm("isb");
+
+ /* Enables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_enable();
+
+ /* Set CMT0 to module-stop state */
+ MSTP(CMT0) = 1;
+
+ /* Disables writing to the registers related to Reset and Low-Power function */
+ r_rst_write_disable();
+
+}
+
+/*******************************************************************************
+ End of function R_ECM_CompareError_Wait
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name : R_ECM_Write_Reg8
+* Description : Writing the special sequence for 8-bit ECM protected register
+* Arguments : reg_type
+* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON)
+* *reg
+* The address of ECM protected register
+* value
+* The 8-bit value of writing to protected register
+* Return Value : none
+*******************************************************************************/
+uint8_t R_ECM_Write_Reg8( uint8_t reg_type, volatile unsigned char *reg, uint8_t value)
+{
+ uint8_t result;
+ volatile uint8_t dummy_8;
+ volatile uint32_t dummy_32;
+
+ /* Special write sequence */
+ *g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value
+ dummy_32 = *g_pcmd_reg_adrr[reg_type];
+
+ *reg = value; // Write expected value
+ *reg = ~value; // Write inversed value of the expected value
+ *reg = value; // Write expected value
+ dummy_8 = *reg;
+
+ /* Check the ECMPS register whether special sequence is success or failure
+ result = 0 : Special sequence is success.
+ = 1 : Special sequence is failure. */
+ result = ECM.ECMPS.BYTE;
+
+ return result;
+
+}
+/*******************************************************************************
+ End of function R_ECM_Write_Reg8
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : R_ECM_Write_Reg32
+* Description : Writing the special sequence for 32-bit ECM protected register
+* Arguments : reg_type
+* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON)
+* *reg
+* The address of ECM protected register
+* value
+* The 32-bit value of writing to protected register
+* Return Value : none
+*******************************************************************************/
+uint8_t R_ECM_Write_Reg32( uint8_t reg_type, volatile unsigned long *reg, uint32_t value)
+{
+ uint8_t result;
+ volatile uint32_t dummy_32;
+
+ /* Special write sequence */
+ *g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value
+ dummy_32 = *g_pcmd_reg_adrr[reg_type];
+
+ *reg = value; // Write expected value
+ *reg = ~value; // Write inversed value of the expected value
+ *reg = value; // Write expected value
+ dummy_32 = *reg;
+
+ /* Check the ECMPS register whether special sequence is success or failure
+ result = 0 : Special sequence is success.
+ = 1 : Special sequence is failure. */
+ result = ECM.ECMPS.BYTE;
+
+ return result;
+
+}
+/*******************************************************************************
+ End of function R_ECM_Write_Reg32
+*******************************************************************************/
+
+/* End of File */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c
new file mode 100644
index 0000000000..daf7ce0375
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c
@@ -0,0 +1,329 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_icu_init.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for ICU init
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : Initialize the peripheral settings of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_icu_init.h"
+#include "r_system.h"
+#include "r_mpc.h"
+#include "r_ecm.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+#ifdef __ICCARM__
+#pragma type_attribute=__irq __arm
+#endif // __ICCARM__
+void R_IRQ9_isr(void);
+
+
+
+/*******************************************************************************
+* Function Name: R_ICU_Disable
+* Description : Disable IRQ interrupt
+* Arguments : vec_num
+ Vector interrupt number (1 to 294).
+* Return Value : none
+*******************************************************************************/
+void R_ICU_Disable(uint32_t vec_num)
+{
+ /* Define IECn register address pointer */
+ volatile uint32_t *p_iec_base;
+
+ /* Variable to specify register suffix */
+ uint32_t reg_num; // IECn (n = reg_num)
+ uint32_t bit_num; // IECn.IECm (m = bit_num)
+
+ /* Calcurate register address and register suffix number */
+ if ( 255 >= vec_num ) // Vector number : 1 to 255
+ {
+ /* Set each pointer base address as IEC0 */
+ /* Casting the pointer to a (uint32_t *) is valid because this pointer
+ will reference 32 bit I/O register address */
+ p_iec_base = (uint32_t*)&(VIC.IEC0.LONG);
+
+ /* Calcurate register suffix number */
+ reg_num = vec_num / 32; // IECn (n = reg_num)
+ bit_num = vec_num % 32; // IECn.IECm (m = bit_num)
+ }
+ else // Vector number : 256 to 294
+ {
+ /* Set each pointer address as IEC8 */
+ /* Casting the pointer to a (uint32_t *) is valid because this pointer
+ will reference 32 bit I/O register address */
+ p_iec_base = (uint32_t*)&(VIC.IEC8.LONG);
+
+ /* Calcurate register suffix number. And subtract 8 from reg_num
+ because IEC8 is base address in this case */
+ reg_num = (vec_num / 32) - 8; // IECn (n = 8 + reg_num)
+ bit_num = (vec_num % 32); // IECn.IECm (m = bit_num)
+ }
+
+ /* Set interrupt enable clear register (disable interrupt) */
+ p_iec_base += reg_num; // Specify IECn register address
+ *p_iec_base |= ( 1 << bit_num ); // Set IECn.IECm bit
+
+}
+/*******************************************************************************
+ End of function R_ICU_Disable
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name: R_ICU_Enable
+* Description : Enable IRQ interrupt
+* Arguments : vec_num
+ Vector interrupt number (1 to 294).
+* Return Value : none
+*******************************************************************************/
+void R_ICU_Enable(uint32_t vec_num)
+{
+ /* Define IENn register address pointer */
+ volatile uint32_t *p_ien_base;
+
+ /* Variable to specify register suffix */
+ uint32_t reg_num; // IENn (n = reg_num)
+ uint32_t bit_num; // IENn.IENm (m = bit_num)
+
+
+ /* Calcurate register address and register suffix number */
+ if ( 255 >= vec_num ) // Vector number : 1 to 255
+ {
+ /* Set each pointer base address as IEN0 */
+ /* Casting the pointer to a (uint32_t *) is valid because this pointer
+ will reference 32 bit I/O register address */
+ p_ien_base = (uint32_t*)&(VIC.IEN0.LONG);
+
+ /* Calcurate register suffix number */
+ reg_num = vec_num / 32; // IENn (n = reg_num)
+ bit_num = vec_num % 32; // IENn.IENm (m = bit_num)
+ }
+ else // Vector number : 256 to 294
+ {
+ /* Set each pointer address as IEN8 */
+ /* Casting the pointer to a (uint32_t *) is valid because this pointer
+ will reference 32 bit I/O register address */
+ p_ien_base = (uint32_t*)&(VIC.IEN8.LONG);
+
+ /* Calcurate register suffix number. And subtract 8 from reg_num
+ because IEN8 is base address in this case */
+ reg_num = (vec_num / 32) - 8; // IENn (n = 8 + reg_num)
+ bit_num = (vec_num % 32); // IENn.IENm (m = bit_num)
+ }
+
+ /* Set interrupt enable register (enable interrupt) */
+ p_ien_base += reg_num; // Specify IENn register address
+ *p_ien_base |= ( 1 << bit_num ); // Set IENn.IENm bit
+
+}
+/*******************************************************************************
+ End of function R_ICU_Enable
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name: R_ICU_ExtPinInit
+* Description : Initialize external interrupt pin setting.
+* Arguments : pin_num
+ External interrupt pin number (0 to 15).
+ detect
+ Interrupt pin detection sense (Low, Fall, Rise, RIse&Fall).
+ dnf_set
+ Setting of degital noise filter
+* Return Value : none
+*******************************************************************************/
+void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set)
+{
+ /* Define IRQCRn register address pointer */
+ /* Casting the pointer to a (void *) is valid because this pointer will
+ reference 32 bit I/O register address */
+ volatile uint32_t *p_irqcr_base = (void *)(&(ICU.IRQCR0.LONG));
+
+ /* Disable digital noise filter (Clear IRQFLTEn bit (n = pin_num))*/
+ ICU.IRQFLTE.LONG &= (0x0000FFFF & ~( 1 << pin_num ));
+
+ /* Set IRQ detection sense */
+ p_irqcr_base += pin_num; // Specify IRQCRn register address
+ *p_irqcr_base = detect; // Set IRQCRn.IRQMD[1:0]
+
+ /* Set digital noise filter and enable */
+ if ( ICU_DNF_NO_USE != dnf_set )
+ {
+ /* Set digital noise filter */
+ ICU.IRQFLTC.LONG &= ~( 3 << ( pin_num * 2 ) ); // Clear FCLKSELn[1:0]
+ ICU.IRQFLTC.LONG |= (dnf_set << ( pin_num * 2)); // Set FCLKSELn[1:0] to dnf_set value
+
+ /* Enable digital noise filter */
+ ICU.IRQFLTE.LONG |= ( 1 << pin_num );
+ }
+
+}
+/*******************************************************************************
+ End of function R_ICU_ExtPinInit
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: R_ICU_Regist
+* Description : Registration interrupt controller setting.
+* Arguments : vec_num
+ Vector interrupt number (1 to 294).
+ type
+ IRQ detection type(Level or Edge).
+ priority
+ IRQ priority level ( Vector number 1 to 255 : 0 to 15,
+ Vector number 256 to 294 : 16 to 31)
+ isr_addr
+ Interrupt service routine address
+* Return Value : none
+*******************************************************************************/
+void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr)
+{
+ /* Define PLSn, PRLn, VADn and PICn registers address pointer */
+ volatile uint32_t *p_pls_base;
+ volatile uint32_t *p_prl_base;
+ volatile uint32_t *p_vad_base;
+ volatile uint32_t *p_pic_base;
+
+ /* Variable to specify register suffix */
+ uint32_t reg_num; // PLSn, PICn (n = reg_num)
+ uint32_t bit_num; // PLSn.PLSm, PICn.PICm (m = bit_num)
+
+
+ /* Calcurate register address and register suffix number */
+ if ( 255 >= vec_num ) // Vector number : 1 to 255
+ {
+ /* Set each pointer base address as PLS0, PRL1, VAD1 and PIC0 */
+ /* Casting the pointer to a (uint32_t *) is valid because this pointer
+ will reference 32 bit I/O register address */
+ p_pls_base = (uint32_t*)&(VIC.PLS0.LONG);
+ p_prl_base = (uint32_t*)&(VIC.PRL1.LONG);
+ p_vad_base = (uint32_t*)&(VIC.VAD1.LONG);
+ p_pic_base = (uint32_t*)&(VIC.PIC0.LONG);
+
+ /* Calcurate register suffix number */
+ reg_num = vec_num / 32; // PLSn, PICn (n = reg_num)
+ bit_num = vec_num % 32; // PLSn.PLSm, PICn.PICm (m = bit_num)
+ }
+ else // Vector number : 256 to 294
+ {
+ /* Set each pointer address as PLS8, PRL256, VAD256 and PIC8 */
+ /* Casting the pointer to a (uint32_t *) is valid because this pointer
+ will reference 32 bit I/O register address */
+ p_pls_base = (uint32_t*)&(VIC.PLS8.LONG);
+ p_prl_base = (uint32_t*)&(VIC.PRL256.LONG);
+ p_vad_base = (uint32_t*)&(VIC.VAD256.LONG);
+ p_pic_base = (uint32_t*)&(VIC.PIC8.LONG);
+
+ /* Calcurate register suffix number. And subtract 8 from reg_num
+ because PLS8 and PIC8 are base address in this case */
+ reg_num = (vec_num / 32) - 8; // PLSn, PICn (n = 8 + reg_num)
+ bit_num = (vec_num % 32); // PLSn.PLSm, PICn.PICm (m = bit_num)
+ vec_num -= 255; // Offset (PRLn and VADn base is changed (eg. VAD1 to VAD256)
+ }
+
+ /* Set interrupt detection type (Level or Edge) by PLSn */
+ p_pls_base += reg_num; // Specify PLSn register address
+ *p_pls_base &= ~( 1 << bit_num ); // Clear PLSn.PLSm bit
+ *p_pls_base |= ( type << bit_num ); // Set PLSn.PLSm bit to type value
+
+ /* Set interrupt priority level (0 to 15) or (16 to 31) */
+ p_prl_base += ( vec_num - 1 ); // Specify PRLn register address
+ *p_prl_base = priority; // Set PRLn to priority value
+
+ /* Set interrupt service routine address */
+ p_vad_base += ( vec_num - 1 ); // Specify VADn register address
+ *p_vad_base = isr_addr; // Set VADn to isr_addr value
+
+ /* Clear interrupt edge detection (edge type only)*/
+ if ( ICU_TYPE_EDGE == type )
+ {
+ p_pic_base += reg_num; // Specify PICn register address
+ *p_pic_base |= ( 1 << bit_num ); // Set PICn.PICm bit to 1
+ }
+
+}
+
+/*******************************************************************************
+ End of function R_ICU_Regist
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name: R_IRQ9_isr
+* Description : Interrupt service routine of IRQ9 (IRQ5 pin interrupt).
+* Toggle the P56 output level (LED1)
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#ifdef __ICCARM__
+#pragma type_attribute=__irq __arm
+#endif // __ICCARM__
+void R_IRQ9_isr(void)
+{
+ /* Clear interrupt edge detection */
+ VIC.PIC0.BIT.PIC9 = ICU_PIC_EDGE_CLEAR;
+
+ /* Toggle the P56 output level(LED1) */
+ PORT5.PODR.BIT.B6 ^= 1;
+
+ /* End interrupt sequence (dummy writing to HVA0 register) */
+ VIC.HVA0.LONG = 0x00000000;
+
+}
+
+/*******************************************************************************
+ End of function R_IRQ9_isr
+*******************************************************************************/
+
+
+/* End of File */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c
new file mode 100644
index 0000000000..e6f395ce52
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c
@@ -0,0 +1,148 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_ram_init.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for internal extended RAM function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : internal extended RAM setting API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_system.h"
+#include "r_ram_init.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define RAM_ECC_ENABLE (0x00000001)
+#define RAM_ECC_DISABLE (0x00000000)
+#define RAM_PROTECT (0x00000000)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : R_RAM_ECC_Enable
+* Description : Enable ECC function for internal extended RAM.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void R_RAM_ECC_Enable(void)
+{
+ /* Enables writing to the protected registers related to RAM function */
+ R_RAM_WriteEnable();
+
+ /* Enable ECC function */
+ ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE;
+
+ /* Disables writing to the protected registers related to RAM function */
+ R_RAM_WriteDisable();
+
+}
+
+/*******************************************************************************
+ End of function R_RAM_ECC_Enable
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name : R_RAM_WriteEnable
+* Description : Enable writing to the protected registers related to RAM.
+* And dummy read the register in order to fix the register value.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void R_RAM_WriteEnable(void)
+{
+ volatile uint32_t dummy;
+
+ /* Special sequence for protect release */
+ ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5
+ ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value
+ ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inversed value of the expected value
+ ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again
+ dummy = ECCRAM.RAMPCMD.LONG;
+
+}
+
+/*******************************************************************************
+ End of function R_RAM_WriteEnable
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : R_RAM_WriteDisable
+* Description : Disable writing to the protected registers related to RAM.
+* And dummy read the register in order to fix the register value.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void R_RAM_WriteDisable(void)
+{
+ volatile uint32_t dummy;
+
+ /* Clear RAMPCMD register to zero */
+ ECCRAM.RAMPCMD.LONG = RAM_PROTECT;
+ dummy = ECCRAM.RAMPCMD.LONG;
+
+}
+
+/*******************************************************************************
+ End of function R_RAM_WriteDisable
+*******************************************************************************/
+
+/* End of File */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c
new file mode 100644
index 0000000000..615f75f64f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c
@@ -0,0 +1,123 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* System Name : RZ/T1 Init program
+* File Name : r_reset.c
+* Version : 0.1
+* Device : R7S9100xx
+* Abstract : API for RESET and Low-Power function
+* Tool-Chain : IAR Embedded Workbench Ver.7.20
+* OS : not use
+* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+* Description : RESET and Low-Power API of RZ/T1
+* Limitation : none
+*******************************************************************************/
+/*******************************************************************************
+* History : DD.MM.YYYY Version Description
+* : First Release
+*******************************************************************************/
+
+/*******************************************************************************
+Includes , "Project Includes"
+*******************************************************************************/
+#include
+#include
+#include "r_system.h"
+#include "r_reset.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define RST_WRITE_ENABLE (0x0000A502)
+#define RST_WRITE_DISABLE (0x0000A500)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+
+/*******************************************************************************
+Private variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name : r_rst_write_enable
+* Description : Enables writing to the registers related to RESET and Low-
+* Power function. And dummy read the register in order to fix
+* the register value.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void r_rst_write_enable(void)
+{
+ volatile uint32_t dummy;
+
+ /* Enables writing to the Reset and Low-Power register */
+ SYSTEM.PRCR.LONG = RST_WRITE_ENABLE;
+ dummy = SYSTEM.PRCR.LONG;
+
+}
+
+/*******************************************************************************
+ End of function r_rst_write_enable
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name : r_rst_write_disable
+* Description : Disables writing to the registers related to RESET and Low-
+* Power function. And dummy read the register in order to fix
+* the register value.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void r_rst_write_disable(void)
+{
+ volatile uint32_t dummy;
+
+ /* Disables writing to the Reset and Low-Power register */
+ SYSTEM.PRCR.LONG = RST_WRITE_DISABLE;
+ dummy = SYSTEM.PRCR.LONG;
+
+}
+
+/*******************************************************************************
+ End of function r_rst_write_disable
+*******************************************************************************/
+
+/* End of File */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm
new file mode 100644
index 0000000000..1e29b24ce2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm
@@ -0,0 +1,73 @@
+;*******************************************************************************
+; DISCLAIMER
+; This software is supplied by Renesas Electronics Corporation and is only
+; intended for use with Renesas products. No other uses are authorized. This
+; software is owned by Renesas Electronics Corporation and is protected under
+; all applicable laws, including copyright laws.
+; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; Renesas reserves the right, without notice, to make changes to this software
+; and to discontinue the availability of this software. By using this software,
+; you agree to the additional terms and conditions found by accessing the
+; following link:
+; http://www.renesas.com/disclaimer
+;
+; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+;******************************************************************************
+;*******************************************************************************
+; System Name : RZ/T1 Init program
+; File Name : vector.asm
+; Version : 0.1
+; Device : R7S9100xx
+; Abstract : vector address (in low vector)
+; Tool-Chain : IAR Embedded Workbench Ver.7.20
+; OS : not use
+; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
+; Description : vector address for RZ/T1 (in low vector)
+; Limitation : none
+;******************************************************************************
+;*******************************************************************************
+; History : DD.MM.YYYY Version Description
+; : First Release
+;******************************************************************************
+
+/* This program is allocated to section "intvec" */
+ SECTION intvec:CODE:ROOT(2)
+
+ EXTERN FreeRTOS_SVC_Handler
+
+ ARM
+
+reset_handler:
+ b reset_handler
+
+undefined_handler:
+ b undefined_handler
+
+svc_handler:
+ b FreeRTOS_SVC_Handler
+
+prefetch_handler:
+ b prefetch_handler
+
+abort_handler:
+ b abort_handler
+
+reserved_handler:
+ b reserved_handler
+
+irq_handler:
+ b irq_handler
+
+fiq_handler:
+ b fiq_handler
+
+ END
+; End of File
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siochar.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siochar.c
deleted file mode 100644
index db4cb0acb1..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siochar.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only
-* intended for use with Renesas products. No other uses are authorized. This
-* software is owned by Renesas Electronics Corporation and is protected under
-* all applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
-* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
-* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
-* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
-* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
-* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
-* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software
-* and to discontinue the availability of this software. By using this software,
-* you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-/***********************************************************************************************************************
-* System Name : RZ/T1 SCIF program
-* File Name : siochar.c
-* Version : 0.1
-* Device : R7S910018
-* Abstract : Serial I/O settings controlling the character
-* Tool-Chain : GNUARM-NONEv14.02-EABI
-* OS : not use
-* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
-* Description : Control the character with serial I/O
-* Limitation : none
-***********************************************************************************************************************/
-/***********************************************************************************************************************
-* History : DD.MM.YYYY Version Description
-* : 21.05.2015 1.00 First Release
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-Includes , "Project Includes"
-***********************************************************************************************************************/
-#include "r_cg_macrodriver.h"
-#include "r_cg_userdefine.h"
-#include "r_cg_scifa.h"
-#include "siochar.h"
-
-
-/***********************************************************************************************************************
-Typedef definitions
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Macro definitions
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Imported global variables and functions (from other files)
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Exported global variables and functions (to be accessed by other files)
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Private global variables and functions
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-* Function Name: io_init_scifa2
-* Description : This function initialises SCIFA channel 2 as UART mode.
-* : The transmit and the receive of SCIFA channel 2 are enabled.
-* Arguments : none
-* Return Value : none
-***********************************************************************************************************************/
-void io_init_scifa2 (void)
-{
- /* === Initialisation of SCIFA2 if not already initialised ==== */
- if (1 == MSTP_SCIFA2)
- {
- R_SCIFA2_Create();
- }
-
- /* Ensure receive FIFO trigger is set to 1 */
- SCIFA2.FCR.BIT.RTRG = 0U;
-
- /* Reception triggered by one data */
- SCIFA2.FTCR.BIT.RFTC = 1u;
-
- /* Enable reception and receive interrupts */
- SCIFA2.SCR.BIT.RE = 1U;
- SCIFA2.SCR.BIT.RIE = 1U;
- SCIFA2.SCR.BIT.REIE = 1U;
-}
-
-/***********************************************************************************************************************
- End of function io_init_scifa2
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
- * Function Name: io_get_char
-* Description : One character is received from SCIFA2, and it's data is returned.
-* : This function keeps waiting until it can obtain the receiving data.
-* Arguments : none
-* Return Value : Character to receive (Byte).
-***********************************************************************************************************************/
-char io_get_char (void)
-{
- char data;
-
- /* Confirming receive error (ER,BRK,FER,PER) */
- if (SCIFA2.FSR.WORD & 0x09Cu)
- {
- /* ---- Detect receive error ---- */
-
- /* Disable reception */
- SCIFA2.SCR.BIT.RE = 0U;
-
- /* Reset receiving FIFO */
- SCIFA2.FCR.BIT.RFRST = 1U;
-
- /* Clearing FIFO reception reset */
- SCIFA2.FCR.BIT.RFRST = 0U;
-
- /* Error bit clear */
- SCIFA2.FSR.BIT.DR = 0U;
- SCIFA2.FSR.BIT.RDF = 0U;
-
- /* Enable reception */
- SCIFA2.SCR.BIT.RE = 1U;
-
- return (0);
- }
-
- /* Is there receive FIFO data? */
- while (0 == SCIFA2.FSR.BIT.RDF)
- {
- /* Wait */
- }
-
- /* Read receive data */
- data = SCIFA2.FRDR;
-
- /* Clear RDF */
- SCIFA2.FSR.BIT.RDF = 0U;
-
- /* Is it overflowed? */
- if (1 == SCIFA2.LSR.BIT.ORER)
- {
- /* ORER clear */
- SCIFA2.LSR.BIT.ORER = 0U;
- }
-
- return (data);
-}
-
-/***********************************************************************************************************************
- End of function io_get_char
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* Function Name: io_put_char
-* Description : Character "buffer" is output to SCIFA2.
-* : This function keeps waiting until it becomes the transmission
-* : enabled state.
-* Arguments : char buffer : character to output
-* Return Value : None
-***********************************************************************************************************************/
-void io_put_char (char buffer)
-{
- /* Check if it is possible to transmit (TDFE flag) */
- while (0 == SCIFA2.FSR.BIT.TDFE)
- {
- /* Wait */
- }
-
- /* Send the character via the terminal output */
- R_SCIFA2_Serial_Send((uint8_t *)&buffer, 1);
-
- /* Clear TEND flag */
- SCIFA2.FSR.BIT.TEND = 0u;
-}
-
-/***********************************************************************************************************************
-* End of function io_put_char
-***********************************************************************************************************************/
-
-
-/* End of File */
-
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siorw.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siorw.c
deleted file mode 100644
index d39abd076d..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siorw.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only
-* intended for use with Renesas products. No other uses are authorized. This
-* software is owned by Renesas Electronics Corporation and is protected under
-* all applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
-* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
-* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
-* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
-* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
-* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
-* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software
-* and to discontinue the availability of this software. By using this software,
-* you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-/***********************************************************************************************************************
-* System Name : RZ/T1 SCIF program
-* File Name : siorw.c
-* Version : 0.1
-* Device : R7S910018
-* Abstract : Serial I/O settings controlling the read and write command
-* Tool-Chain : GNUARM-NONEv14.02-EABI
-* OS : not use
-* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
-* Description : Control the read/write command with serial I/O
-* Limitation : none
-***********************************************************************************************************************/
-/***********************************************************************************************************************
-* History : DD.MM.YYYY Version Description
-* : 21.05.2015 1.00 First Release
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Includes , "Project Includes"
-***********************************************************************************************************************/
-#include
-#include "r_cg_macrodriver.h"
-#include "r_cg_userdefine.h"
-#include "r_cg_scifa.h"
-#include "siochar.h"
-
-
-/***********************************************************************************************************************
-Typedef definitions
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Macro definitions
-***********************************************************************************************************************/
-/* File descriptor */
-#define STDIN (0)
-#define STDOUT (1)
-#define STDERR (2)
-
-#define SIORW_SUCCESS (0)
-#define SIORW_ERROR (-1)
-#define SIORW_FLAG_OFF (0)
-#define SIORW_FLAG_ON (1)
-
-
-/***********************************************************************************************************************
-Imported global variables and functions (from other files)
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Exported global variables and functions (to be accessed by other files)
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-Private global variables and functions
-***********************************************************************************************************************/
-
-
-/***********************************************************************************************************************
-* Function Name: sio_write
-* Description : The character strings specified with buffer is output for n
-* : bytes from serial port. The output is determined by file number fileno.
-* : The effective outputs in this version are STDOUT and STDERR, and
-* : it is output to the same serial port.
-* : The line-feed code '\n'(LF) is converted in '\r'(CR)+'\n'(LF) to output.
-* Arguments : int32_t file_no ; I : File number to be the target of writing
-* : int_t * buffer ; O : Pointer to the area in which writing data is stored
-* : uint32_t writing_b; I : Writing bytes
-* Return Value : >=0 : Number of transmitting characters
-* : -1 : File number error
-***********************************************************************************************************************/
-int32_t sio_write (int32_t file_no, const char * buffer, uint32_t writing_b)
-{
- uint32_t offset;
-
- if ((STDOUT == file_no) || (STDERR == file_no))
- {
- for (offset = 0; offset < writing_b; offset++)
-
- {
- /* Writing in buffer converting line-feed code */
- if ('\n' == (*(buffer + offset)))
- {
- if (0 == offset)
- {
- io_put_char('\r');
- }
- else
- {
- if ('\r' != (*((buffer + offset) - 1)))
- {
- io_put_char('\r');
- }
- }
- io_put_char('\n');
- }
- else
- {
- io_put_char(*(buffer + offset));
- }
- }
- return ((int32_t)offset);
- }
-
- /* File number error */
- return SIORW_ERROR;
-}
-
-/***********************************************************************************************************************
- * End of function sio_write
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* Function Name: sio_read
-* Description : The character strings specified with buffer is input for
-* : n bytes from serial port.The input is determined by file number fileno.
-* : The effective input in this version is STDIN.
-* Arguments : int32_t file_no ; I : File number to be the target of reading
-* : int_t * buffer ; O : Pointer to the area in which reading data is stored
-* : uint32_t reading_b; I : Reading bytes
-* Return Value : >0 : Number of receiving characters
-* : -1 : File number, receiving data error
-***********************************************************************************************************************/
-int32_t sio_read (int32_t file_no, char * buffer, uint32_t reading_b)
-{
- int32_t char_mem;
- int32_t sp_char;
- uint32_t offset;
- static int32_t sjis_flg = SIORW_FLAG_OFF;
-
- if (STDIN == file_no)
- {
- for (offset = 0; offset < reading_b; )
- {
- /* Reading receiving data */
- char_mem = io_get_char();
-
- /* -1 is returned when it is receiving data error */
- if ((-1) == char_mem)
- {
- return SIORW_ERROR;
- }
-
- if (SIORW_FLAG_ON == sjis_flg)
- {
- sjis_flg = SIORW_FLAG_OFF;
- sio_write(STDOUT, (char *)&char_mem, 1);
-
- (*(buffer + offset)) = (char)char_mem;
- offset++;
- }
- if ((0x20 <= char_mem) && (char_mem <= 0x7E))
- {
- /* Data possible to display */
- sio_write(STDOUT, (char *)&char_mem, 1);
- (*(buffer + offset)) = (char)char_mem;
- offset++;
- }
-
- /* BS process */
- if (('\b' == char_mem) && (offset > 0))
- { sp_char = 0x20;
- sio_write(STDOUT, (char *)&char_mem, 1);
- sio_write(STDOUT, (char *)&sp_char, 1);
- sio_write(STDOUT, (char *)&char_mem, 1);
- offset--;
- }
-
- /* CR process */
- if ('\r' == char_mem)
- {
- (*(buffer + offset)) = '\n';
- sio_write(STDOUT, buffer + offset, 1);
- offset++;
- }
-
- /* Japanese SJIS ? */
- if (((char_mem >= 0x80) && (char_mem < 0xA0)) || ((char_mem >= 0xE0) && (char_mem < 0xFE)))
- {
- /* Data possible to display */
- sio_write(STDOUT, (char *)&char_mem, 1);
- (*(buffer + offset)) = (char)char_mem;
- offset++;
- sjis_flg = SIORW_FLAG_ON;
- }
- }
- return ((int32_t)offset);
- }
-
- /* File number error */
- return SIORW_ERROR;
-}
-
-/***********************************************************************************************************************
- End of function sio_read
-***********************************************************************************************************************/
-
-
-/* End of File */
-
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h
new file mode 100644
index 0000000000..49e1c887fb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h
@@ -0,0 +1,187 @@
+/*
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ ***************************************************************************
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+ ***************************************************************************
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following
+ link: http://www.freertos.org/a00114.html
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that is more than just the market leader, it *
+ * is the industry's de facto standard. *
+ * *
+ * Help yourself get started quickly while simultaneously helping *
+ * to support the FreeRTOS project by purchasing a FreeRTOS *
+ * tutorial book, reference manual, or both: *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
+ the FAQ page "My application does not run, what could be wrong?". Have you
+ defined configASSERT()?
+
+ http://www.FreeRTOS.org/support - In return for receiving this top quality
+ embedded software for free we request you assist our global community by
+ participating in the support forum.
+
+ http://www.FreeRTOS.org/training - Investing in training allows your team to
+ be as productive as possible as early as possible. Now you can receive
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ Ltd, and the world's leading authority on the world's leading RTOS.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and commercial middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configCPU_CLOCK_HZ 450000000
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 10 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configGENERATE_RUN_TIME_STATS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 5
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xEventGroupSetBitFromISR 1
+#define INCLUDE_xTimerPendFunctionCall 1
+
+/* This demo makes use of one or more example stats formatting functions. These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form. See the notes in the implementation of vTaskList() within
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1
+
+/* Cortex-R specific setting: FPU has 16 (rather than 32) d registers. */
+#define configFPU_D32 0
+
+/* Cortex-R specific setting: The address of the register within the interrupt
+controller from which the address of the current interrupt's handling function
+can be obtained. */
+#define configINTERRUPT_VECTOR_ADDRESS
+
+/* Cortex-R specific setting: The address of End of Interrupt register within
+the interrupt controller. */
+#define configEOI_ADDRESS 0xA0010200UL /* VIC HVA0 register */
+
+/* Cortex-R specific setting: configCLEAR_TICK_INTERRUPT() is a macro that is
+called by the RTOS kernel's tick handler to clear the source of the tick
+interrupt. */
+#define configCLEAR_TICK_INTERRUPT() VIC.PIC9.LONG = 0x00001000UL;
+
+/* Prevent C code being included in assembly files when the IAR compiler is
+used. */
+#ifndef __IASMARM__
+
+ /* Renesas hardware definitions. */
+ #include "iodefine.h"
+
+ /* Application specific definition. See _TBD_ for usage instructions. */
+ typedef void (*ISRFunction_t)( void );
+
+ /* Normal assert() semantics without relying on the provision of an assert.h
+ header file. */
+ #define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }
+
+
+
+ /****** Hardware specific settings. *******************************************/
+
+ /*
+ * The application must provide a function that configures a peripheral to
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
+ * in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must
+ * be installed as the peripheral's interrupt handler.
+ */
+ void vConfigureTickInterrupt( void );
+ #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
+
+#endif /* __IASMARM__ */
+
+/* To allow the debugger to find the end of the interrupt stack frame. */
+#define configTASK_RETURN_ADDRESS NULL
+
+#endif /* FREERTOS_CONFIG_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c
index 20111cb663..449274271e 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c
@@ -82,7 +82,14 @@
* variable to point to the RTOS tick handler, then branches to the FreeRTOS
* IRQ handler.
*/
-static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked));
+#ifdef __GNUC__
+ static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked));
+#endif /* __GNUC__ */
+#ifdef __ICCARM__
+ /* IAR requires the entry point to be in an assembly file. The function is
+ implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */
+ extern void FreeRTOS_Tick_Handler_Entry( void );
+#endif /* __ICCARM__ */
/*
* The FreeRTOS IRQ handler, which is implemented in the RTOS port layer.
@@ -184,17 +191,21 @@ ISRFunction_t pxISRToCall = pxISRFunction;
* saved in the pxISRFunction variable. NOTE: This entry point is a naked
* function - do not add C code to this function.
*/
-static void FreeRTOS_Tick_Handler_Entry( void )
-{
- __asm volatile ( \
- "PUSH {r0-r1} \t\n" \
- "LDR r0, =pxISRFunction \t\n" \
- "LDR R1, =FreeRTOS_Tick_Handler \t\n" \
- "STR R1, [r0] \t\n" \
- "POP {r0-r1} \t\n" \
- "B FreeRTOS_IRQ_Handler "
- );
-}
+#ifdef __GNUC__
+ /* The IAR equivalent is implemented in
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
+ static void FreeRTOS_Tick_Handler_Entry( void )
+ {
+ __asm volatile ( \
+ "PUSH {r0-r1} \t\n" \
+ "LDR r0, =pxISRFunction \t\n" \
+ "LDR R1, =FreeRTOS_Tick_Handler \t\n" \
+ "STR R1, [r0] \t\n" \
+ "POP {r0-r1} \t\n" \
+ "B FreeRTOS_IRQ_Handler "
+ );
+ }
+#endif /* __GNUC__ */
/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c
index e6abe0eba7..5aee68febc 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c
@@ -101,9 +101,16 @@ void vCMT_1_Channel_1_ISR( void );
* Entry point for the handlers. These set the pxISRFunction variable to point
* to the C handler for each timer, then branch to the FreeRTOS IRQ handler.
*/
-static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));
-static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));
-
+#ifdef __GNUC__
+ static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));
+ static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));
+#endif /* __GNUC__ */
+#ifdef __ICCARM__
+ /* IAR requires the entry point to be in an assembly file. The functions
+ are implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */
+ extern void vCMT_1_Channel_0_ISR_Entry( void );
+ extern void vCMT_1_Channel_1_ISR_Entry( void );
+#endif /* __ICCARM__ */
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
@@ -196,30 +203,38 @@ void vCMT_1_Channel_1_ISR( void )
* saved in the pxISRFunction variable. NOTE: The entry points are naked
* functions - do not add C code to these functions.
*/
-static void vCMT_1_Channel_0_ISR_Entry( void )
-{
- __asm volatile ( \
- "PUSH {r0-r1} \t\n" \
- "LDR r0, =pxISRFunction \t\n" \
- "LDR r1, =vCMT_1_Channel_0_ISR \t\n" \
- "STR r1, [r0] \t\n" \
- "POP {r0-r1} \t\n" \
- "B FreeRTOS_IRQ_Handler "
- );
-}
+#ifdef __GNUC__
+ /* The IAR equivalent is implemented in
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
+ static void vCMT_1_Channel_0_ISR_Entry( void )
+ {
+ __asm volatile ( \
+ "PUSH {r0-r1} \t\n" \
+ "LDR r0, =pxISRFunction \t\n" \
+ "LDR r1, =vCMT_1_Channel_0_ISR \t\n" \
+ "STR r1, [r0] \t\n" \
+ "POP {r0-r1} \t\n" \
+ "B FreeRTOS_IRQ_Handler "
+ );
+ }
+#endif /* __GNUC__ */
/*-----------------------------------------------------------*/
-static void vCMT_1_Channel_1_ISR_Entry( void )
-{
- __asm volatile ( \
- "PUSH {r0-r1} \t\n" \
- "LDR r0, =pxISRFunction \t\n" \
- "LDR r1, =vCMT_1_Channel_1_ISR \t\n" \
- "STR r1, [r0] \t\n" \
- "POP {r0-r1} \t\n" \
- "B FreeRTOS_IRQ_Handler "
- );
-}
+#ifdef __GNUC__
+ /* The IAR equivalent is implemented in
+ $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
+ static void vCMT_1_Channel_1_ISR_Entry( void )
+ {
+ __asm volatile ( \
+ "PUSH {r0-r1} \t\n" \
+ "LDR r0, =pxISRFunction \t\n" \
+ "LDR r1, =vCMT_1_Channel_1_ISR \t\n" \
+ "STR r1, [r0] \t\n" \
+ "POP {r0-r1} \t\n" \
+ "B FreeRTOS_IRQ_Handler "
+ );
+ }
+#endif /* __GNUC__ */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test.S b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test.S
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm
new file mode 100644
index 0000000000..653edaaf41
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm
@@ -0,0 +1,462 @@
+/*
+ FreeRTOS V8.2.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+ PUBLIC vRegTest1Implementation
+ PUBLIC vRegTest2Implementation
+ EXTERN ulRegTest1LoopCounter
+ EXTERN ulRegTest2LoopCounter
+
+ SECTION intvec:CODE:ROOT(2)
+ ARM
+
+ /* This function is explained in the comments at the top of main-full.c. */
+vRegTest1Implementation:
+
+ /* Fill each general purpose register with a known value. */
+ mov r0, #0xFF
+ mov r1, #0x11
+ mov r2, #0x22
+ mov r3, #0x33
+ mov r4, #0x44
+ mov r5, #0x55
+ mov r6, #0x66
+ mov r7, #0x77
+ mov r8, #0x88
+ mov r9, #0x99
+ mov r10, #0xAA
+ mov r11, #0xBB
+ mov r12, #0xCC
+ mov r14, #0xEE
+
+
+ /* Fill each FPU register with a known value. */
+ vmov d0, r0, r1
+ vmov d1, r2, r3
+ vmov d2, r4, r5
+ vmov d3, r6, r7
+ vmov d4, r8, r9
+ vmov d5, r10, r11
+ vmov d6, r0, r1
+ vmov d7, r2, r3
+ vmov d8, r4, r5
+ vmov d9, r6, r7
+ vmov d10, r8, r9
+ vmov d11, r10, r11
+ vmov d12, r0, r1
+ vmov d13, r2, r3
+ vmov d14, r4, r5
+ vmov d15, r6, r7
+
+ /* Loop, checking each itteration that each register still contains the
+ expected value. */
+reg1_loop:
+ /* Yield to increase test coverage */
+ svc 0
+
+ /* Check all the VFP registers still contain the values set above.
+ First save registers that are clobbered by the test. */
+ push { r0-r1 }
+
+ vmov r0, r1, d0
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d1
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d2
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d3
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d4
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d5
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d6
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d7
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d8
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d9
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d10
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d11
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d12
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d13
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d14
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d15
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+
+
+ /* Restore the registers that were clobbered by the test. */
+ pop {r0-r1}
+
+ /* VFP register test passed. Jump to the core register test. */
+ b reg1_loopf_pass
+
+reg1_error_loopf:
+ /* If this line is hit then a VFP register value was found to be
+ incorrect. */
+ b reg1_error_loopf
+
+reg1_loopf_pass:
+
+ /* Test each general purpose register to check that it still contains the
+ expected known value, jumping to reg1_error_loop if any register contains
+ an unexpected value. */
+ cmp r0, #0xFF
+ bne reg1_error_loop
+ cmp r1, #0x11
+ bne reg1_error_loop
+ cmp r2, #0x22
+ bne reg1_error_loop
+ cmp r3, #0x33
+ bne reg1_error_loop
+ cmp r4, #0x44
+ bne reg1_error_loop
+ cmp r5, #0x55
+ bne reg1_error_loop
+ cmp r6, #0x66
+ bne reg1_error_loop
+ cmp r7, #0x77
+ bne reg1_error_loop
+ cmp r8, #0x88
+ bne reg1_error_loop
+ cmp r9, #0x99
+ bne reg1_error_loop
+ cmp r10, #0xAA
+ bne reg1_error_loop
+ cmp r11, #0xBB
+ bne reg1_error_loop
+ cmp r12, #0xCC
+ bne reg1_error_loop
+ cmp r14, #0xEE
+ bne reg1_error_loop
+
+ /* Everything passed, increment the loop counter. */
+ push { r0-r1 }
+ ldr r0, =ulRegTest1LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0-r1 }
+
+ /* Start again. */
+ b reg1_loop
+
+reg1_error_loop:
+ /* If this line is hit then there was an error in a core register value.
+ The loop ensures the loop counter stops incrementing. */
+ b reg1_error_loop
+ nop
+
+/*-----------------------------------------------------------*/
+
+vRegTest2Implementation:
+
+ /* Put a known value in each register. */
+ mov r0, #0xFF000000
+ mov r1, #0x11000000
+ mov r2, #0x22000000
+ mov r3, #0x33000000
+ mov r4, #0x44000000
+ mov r5, #0x55000000
+ mov r6, #0x66000000
+ mov r7, #0x77000000
+ mov r8, #0x88000000
+ mov r9, #0x99000000
+ mov r10, #0xAA000000
+ mov r11, #0xBB000000
+ mov r12, #0xCC000000
+ mov r14, #0xEE000000
+
+ /* Likewise the floating point registers */
+ vmov d0, r0, r1
+ vmov d1, r2, r3
+ vmov d2, r4, r5
+ vmov d3, r6, r7
+ vmov d4, r8, r9
+ vmov d5, r10, r11
+ vmov d6, r0, r1
+ vmov d7, r2, r3
+ vmov d8, r4, r5
+ vmov d9, r6, r7
+ vmov d10, r8, r9
+ vmov d11, r10, r11
+ vmov d12, r0, r1
+ vmov d13, r2, r3
+ vmov d14, r4, r5
+ vmov d15, r6, r7
+
+ /* Loop, checking each itteration that each register still contains the
+ expected value. */
+reg2_loop:
+ /* Check all the VFP registers still contain the values set above.
+ First save registers that are clobbered by the test. */
+ push { r0-r1 }
+
+ vmov r0, r1, d0
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d1
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d2
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d3
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d4
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d5
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d6
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d7
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d8
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d9
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d10
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d11
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d12
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d13
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d14
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d15
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+
+ /* Restore the registers that were clobbered by the test. */
+ pop {r0-r1}
+
+ /* VFP register test passed. Jump to the core register test. */
+ b reg2_loopf_pass
+
+reg2_error_loopf:
+ /* If this line is hit then a VFP register value was found to be
+ incorrect. */
+ b reg2_error_loopf
+
+reg2_loopf_pass:
+
+ cmp r0, #0xFF000000
+ bne reg2_error_loop
+ cmp r1, #0x11000000
+ bne reg2_error_loop
+ cmp r2, #0x22000000
+ bne reg2_error_loop
+ cmp r3, #0x33000000
+ bne reg2_error_loop
+ cmp r4, #0x44000000
+ bne reg2_error_loop
+ cmp r5, #0x55000000
+ bne reg2_error_loop
+ cmp r6, #0x66000000
+ bne reg2_error_loop
+ cmp r7, #0x77000000
+ bne reg2_error_loop
+ cmp r8, #0x88000000
+ bne reg2_error_loop
+ cmp r9, #0x99000000
+ bne reg2_error_loop
+ cmp r10, #0xAA000000
+ bne reg2_error_loop
+ cmp r11, #0xBB000000
+ bne reg2_error_loop
+ cmp r12, #0xCC000000
+ bne reg2_error_loop
+ cmp r14, #0xEE000000
+ bne reg2_error_loop
+
+ /* Everything passed, increment the loop counter. */
+ push { r0-r1 }
+ ldr r0, =ulRegTest2LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0-r1 }
+
+ /* Start again. */
+ b reg2_loop
+
+reg2_error_loop:
+ /* If this line is hit then there was an error in a core register value.
+ The loop ensures the loop counter stops incrementing. */
+ b reg2_error_loop
+ nop
+
+
+ END
+
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/iodefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/iodefine.h
rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.c
deleted file mode 100644
index 3a51ac05aa..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_cmt.c
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for CMT module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-Pragma directive
-***********************************************************************************************************************/
-/* Start user code for pragma. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-Includes
-***********************************************************************************************************************/
-#include "r_cg_macrodriver.h"
-#include "r_cg_cmt.h"
-/* Start user code for include. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-#include "r_cg_userdefine.h"
-
-/***********************************************************************************************************************
-Global variables and functions
-***********************************************************************************************************************/
-/* Start user code for global. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-* Function Name: R_CMT4_Create
-* Description : This function initializes the CMT4 channel.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_CMT4_Create(void)
-{
- /* Disable CMI4 interrupt */
- VIC.IEC9.LONG = 0x00000800UL;
-
- /* Cancel CMT stop state in LPC */
- MSTP(CMT2) = 0U;
-
- /* Set control registers */
- CMT4.CMCR.WORD = _CMT_CMCR_CKS_PCLK8 | _CMT_CMCR_CMIE_ENABLE;
- CMT4.CMCOR = _CMT4_CMCOR_VALUE;
-
- /* Set CMI4 edge detection type */
- VIC.PLS9.LONG |= 0x00000800UL;
-
- /* Set CMI4 priority level */
- VIC.PRL299.LONG = _CMT_PRIORITY_LEVEL16;
-
- /* Set CMI4 interrupt address */
- VIC.VAD299.LONG = (uint32_t)r_cmt_cmi4_interrupt;
-}
-/***********************************************************************************************************************
-* Function Name: R_CMT4_Start
-* Description : This function starts the CMT4 channel counter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_CMT4_Start(void)
-{
- /* Enable CMI4 interrupt in ICU */
- VIC.IEN9.LONG |= 0x00000800UL;
-
- /* Start CMT4 count */
- CMT.CMSTR2.BIT.STR4 = 1U;
-}
-/***********************************************************************************************************************
-* Function Name: R_CMT4_Stop
-* Description : This function stops the CMT4 channel counter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_CMT4_Stop(void)
-{
- /* Disable CMI4 interrupt in ICU */
- VIC.IEC9.LONG = 0x00000800UL;
-
- /* Stop CMT4 count */
- CMT.CMSTR2.BIT.STR4 = 0U;
-}
-/***********************************************************************************************************************
-* Function Name: R_CMT5_Create
-* Description : This function initializes the CMT5 channel.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_CMT5_Create(void)
-{
- /* Disable CMI5 interrupt */
- VIC.IEC9.LONG = 0x00001000UL;
-
- /* Cancel CMT stop state in LPC */
- MSTP(CMT2) = 0U;
-
- /* Set control registers */
- CMT5.CMCR.WORD = _CMT_CMCR_CKS_PCLK8 | _CMT_CMCR_CMIE_ENABLE;
- CMT5.CMCOR = _CMT5_CMCOR_VALUE;
-
- /* Set CMI5 edge detection type */
- VIC.PLS9.LONG |= 0x00001000UL;
-
- /* Set CMI5 priority level */
- VIC.PRL300.LONG = _CMT_PRIORITY_LEVEL17;
-
- /* Set CMI5 interrupt address */
- VIC.VAD300.LONG = (uint32_t)r_cmt_cmi5_interrupt;
-}
-/***********************************************************************************************************************
-* Function Name: R_CMT5_Start
-* Description : This function starts the CMT5 channel counter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_CMT5_Start(void)
-{
- /* Enable CMI5 interrupt in ICU */
- VIC.IEN9.LONG |= 0x00001000UL;
-
- /* Start CMT5 count */
- CMT.CMSTR2.BIT.STR5 = 1U;
-}
-/***********************************************************************************************************************
-* Function Name: R_CMT5_Stop
-* Description : This function stops the CMT5 channel counter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_CMT5_Stop(void)
-{
- /* Disable CMI5 interrupt in ICU */
- VIC.IEC9.LONG = 0x00001000UL;
-
- /* Stop CMT5 count */
- CMT.CMSTR2.BIT.STR5 = 0U;
-}
-
-/* Start user code for adding. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c
index ddc0c0ec1c..ae2d886af9 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
@@ -64,10 +64,10 @@ void r_cmt_cmi4_interrupt(void)
VIC.PIC9.LONG = 0x00000800UL;
/* Start user code. Do not edit comment generated here */
-
+
/* Decrement the count value */
g_time_us_count--;
-
+
/* End user code. Do not edit comment generated here */
/* Dummy write */
@@ -84,11 +84,11 @@ void r_cmt_cmi5_interrupt(void)
/* Clear the interrupt source CMI5 */
VIC.PIC9.LONG = 0x00001000UL;
- /* Start user code. Do not edit comment generated here */
-
+ /* Start user code. Do not edit comment generated here */
+
/* Decrement the count value */
g_time_ms_count--;
-
+
/* End user code. Do not edit comment generated here */
/* Dummy write */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c
index 0052a41bb5..b8cd5b3236 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c
index d618e2e1fb..8dac89a7c2 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
@@ -57,6 +57,9 @@ volatile uint8_t g_switch_press_flg = 0u;
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
+#ifdef __ICCARM__
+ __irq __arm
+#endif /* __ICCARM__ */
void r_icu_irq12_interrupt(void)
{
VIC.PIC0.LONG = 0x00010000UL;
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h
index 625caf0700..2f0f9357c3 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
@@ -44,40 +44,36 @@ Typedef definitions
Global functions
***********************************************************************************************************************/
/* FIQ exception handler */
-void r_fiq_handler(void) __attribute__((interrupt ("FIQ")));
+#ifdef __ICCARM__
+ __irq __arm void r_fiq_handler(void);
-/* ICU IRQ12 */
-void r_icu_irq12_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* ICU IRQ12 */
+ __irq __arm void r_icu_irq12_interrupt(void);
-/* ADC Unit0 S12ADI0 */
-void r_s12ad_s12adi0_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* RSPI1 SPTI1 */
+ __irq __arm void r_rspi1_transmit_interrupt(void);
-/* RSPI1 SPTI1 */
-void r_rspi1_transmit_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* RSPI1 SPEI1 */
+ __irq __arm void r_rspi1_error_interrupt(void);
-/* RSPI1 SPEI1 */
-void r_rspi1_error_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* RSPI1 SPII1 */
+ __irq __arm void r_rspi1_idle_interrupt(void);
+#endif /* __ICCARM__ */
-/* RSPI1 SPII1 */
-void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ")));
+#ifdef __GNUC__
+ void r_fiq_handler(void) __attribute__((interrupt ("FIQ")));
-/* SCIFA TXIF2 */
-void r_scifa2_txif2_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* ICU IRQ12 */
+ void r_icu_irq12_interrupt(void) __attribute__((interrupt ("IRQ")));
-/* SCIFA DRIF2 */
-void r_scifa2_drif2_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* RSPI1 SPTI1 */
+ void r_rspi1_transmit_interrupt(void) __attribute__((interrupt ("IRQ")));
-/* SCIFA RXIF2 */
-void r_scifa2_rxif2_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* RSPI1 SPEI1 */
+ void r_rspi1_error_interrupt(void) __attribute__((interrupt ("IRQ")));
-/* SCIFA BRIF2 */
-void r_scifa2_brif2_interrupt(void) __attribute__((interrupt ("IRQ")));
+ /* RSPI1 SPII1 */
+ void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ")));
+#endif /* __GNUC__ */
-/* CMT CMI4 */
-void r_cmt_cmi4_interrupt(void) __attribute__((interrupt ("IRQ")));
-
-/* CMT CMI5 */
-void r_cmt_cmi5_interrupt(void) __attribute__((interrupt ("IRQ")));
-
-
-#endif
\ No newline at end of file
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c
index 556b9b7efd..256ffaae75 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
@@ -72,6 +72,9 @@ void r_set_exception_handler(void)
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
+#ifdef __ICCARM__
+ __irq __arm
+#endif /* __ICCARM__ */
void r_fiq_handler(void)
{
while(1);
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h
index b2e7e53ea8..79afd916aa 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
@@ -30,6 +30,7 @@
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
+#include
#include "iodefine.h"
#include "r_cg_interrupthandlers.h"
#include "r_cg_mpc.h"
@@ -128,16 +129,19 @@ Macro definitions
Typedef definitions
***********************************************************************************************************************/
#ifndef __TYPEDEF__
-typedef signed char int8_t;
-typedef unsigned char uint8_t;
-typedef signed short int16_t;
-typedef unsigned short uint16_t;
-typedef signed long int32_t;
-typedef unsigned long uint32_t;
-typedef unsigned short MD_STATUS;
-#define __TYPEDEF__
+ #ifndef __ICCARM__
+ typedef signed char int8_t;
+ typedef unsigned char uint8_t;
+ typedef signed short int16_t;
+ typedef unsigned short uint16_t;
+ typedef signed long int32_t;
+ typedef unsigned long uint32_t;
+ #endif /* __ICCARM__ */
+ typedef unsigned short MD_STATUS;
+ #define __TYPEDEF__
#endif
+
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c
index 054683ec60..9f8c973906 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c
@@ -2,15 +2,15 @@
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
+* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
@@ -56,10 +56,13 @@ extern uint16_t g_rspi1_tx_count; /* RSPI1 transmit data numb
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
+#ifdef __ICCARM__
+ __irq __arm
+#endif /* __ICCARM__ */
void r_rspi1_transmit_interrupt(void)
{
uint16_t frame_cnt;
-
+
/* Clear the interrupt source */
VIC.PIC2.LONG = 0x00200000UL;
@@ -92,6 +95,9 @@ void r_rspi1_transmit_interrupt(void)
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
+#ifdef __ICCARM__
+ __irq __arm
+#endif /* __ICCARM__ */
void r_rspi1_error_interrupt(void)
{
uint8_t err_type;
@@ -121,9 +127,9 @@ void r_rspi1_error_interrupt(void)
{
VIC.IEC2.LONG = 0x00400000UL;
}
-
+
VIC.IEN2.LONG |= 0x00400000UL;
-
+
/* Dummy write */
VIC.HVA0.LONG = 0x00000000UL;
}
@@ -133,24 +139,27 @@ void r_rspi1_error_interrupt(void)
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
+#ifdef __ICCARM__
+ __irq __arm
+#endif /* __ICCARM__ */
void r_rspi1_idle_interrupt(void)
{
/* Disable RSPI function */
RSPI1.SPCR.BIT.SPE = 0U;
-
+
/* Disable idle interrupt */
RSPI1.SPCR2.BIT.SPIIE = 0U;
-
+
r_rspi1_callback_transmitend();
-
+
/* Wait the interrupt signal is disabled */
while (0U != (VIC.IRQS2.LONG & 0x00800000UL))
{
VIC.IEC2.LONG = 0x00800000UL;
}
-
+
VIC.IEN2.LONG |= 0x00800000UL;
-
+
/* Dummy write */
VIC.HVA0.LONG = 0x00000000UL;
}
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad.c
deleted file mode 100644
index 8f583c720e..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_s12ad.c
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for S12AD module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-Pragma directive
-***********************************************************************************************************************/
-/* Start user code for pragma. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-Includes
-***********************************************************************************************************************/
-#include "r_cg_macrodriver.h"
-#include "r_cg_s12ad.h"
-/* Start user code for include. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-#include "r_cg_userdefine.h"
-
-/***********************************************************************************************************************
-Global variables and functions
-***********************************************************************************************************************/
-/* Start user code for global. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-* Function Name: R_S12AD0_Create
-* Description : This function initializes the AD0 converter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_S12AD0_Create(void)
-{
- /* Cancel S12ADC0 module stop state */
- MSTP(S12ADC0) = 0U;
-
- /* Disable and clear S12ADI0, S12GBADI0, S12CMPI0 interrupt flags */
- S12ADC0.ADCSR.BIT.ADIE = 0U;
- S12ADC0.ADCSR.BIT.GBADIE = 0U;
- S12ADC0.ADCMPCR.BIT.CMPIE = 0U;
- VIC.IEC1.LONG = 0x00000008UL;
-
- /* Set S12AD0 control registers */
- S12ADC0.ADDISCR.BYTE = _AD0_DISCONECT_SETTING;
- S12ADC0.ADCSR.WORD = _AD_DBLTRIGGER_DISABLE | _AD_SCAN_END_INTERRUPT_ENABLE | _AD_SINGLE_SCAN_MODE;
- S12ADC0.ADCER.WORD = _AD_AUTO_CLEARING_DISABLE | _AD_RIGHT_ALIGNMENT | _AD_RESOLUTION_12BIT;
- S12ADC0.ADADC.BYTE = _AD_1_TIME_CONVERSION | _AD_ADDITION_MODE;
-
- /* Set channels and sampling time */
- S12ADC0.ADANSA.WORD = _AD0_CHANNEL_SELECT_A;
- S12ADC0.ADADS.WORD = _AD0_ADDAVG_CHANNEL_SELECT;
- S12ADC0.ADSSTR7.BYTE = _AD0_SAMPLING_STATE_7;
-
- /* Set compare control register */
- S12ADC0.ADCMPCR.BYTE = _AD_WINDOWFUNCTION_DISABLE;
- S12ADC0.ADCMPANSR.WORD = _AD0_COMPARECHANNEL_SELECT;
- S12ADC0.ADCMPLR.WORD = _AD0_COMPARELEVEL_SELECT;
- S12ADC0.ADCMPDR0 = 0x0000U;
-
- /* Set S12ADI0 edge detection type */
- VIC.PLS1.LONG |= 0x00000008UL;
-
- /* Set S12ADI0 interrupt priority level */
- VIC.PRL35.LONG = _AD_PRIORITY_LEVEL0;
-
- /* Set S12ADI0 interrupt address */
- VIC.VAD35.LONG = (uint32_t)r_s12ad_s12adi0_interrupt;
-
-}
-/***********************************************************************************************************************
-* Function Name: R_S12AD0_Start
-* Description : This function starts the AD0 converter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_S12AD0_Start(void)
-{
- /* Enable S12ADI0 interrupt in ICU */
- VIC.IEN1.LONG |= 0x00000008UL;
-
- S12ADC0.ADCSR.BIT.ADST = 1U;
-}
-/***********************************************************************************************************************
-* Function Name: R_S12AD0_Stop
-* Description : This function stops the AD0 converter.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_S12AD0_Stop(void)
-{
- S12ADC0.ADCSR.BIT.ADST = 0U;
-
- /* Disable S12ADI0 interrupt in ICU */
- VIC.IEC1.LONG = 0x00000008UL;
-}
-/***********************************************************************************************************************
-* Function Name: R_S12AD0_Get_ValueResult
-* Description : This function gets result from the AD0 converter.
-* Arguments : channel -
-* channel of data register to be read
-* buffer -
-* buffer pointer
-* Return Value : None
-***********************************************************************************************************************/
-void R_S12AD0_Get_ValueResult(ad_channel_t channel, uint16_t * const buffer)
-{
- if (channel == ADSELFDIAGNOSIS)
- {
- *buffer = (uint16_t)(S12ADC0.ADRD);
- }
- else if (channel == ADCHANNEL0)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR0);
- }
- else if (channel == ADCHANNEL1)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR1);
- }
- else if (channel == ADCHANNEL2)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR2);
- }
- else if (channel == ADCHANNEL3)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR3);
- }
- else if (channel == ADCHANNEL4)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR4);
- }
- else if (channel == ADCHANNEL5)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR5);
- }
- else if (channel == ADCHANNEL6)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR6);
- }
- else if (channel == ADCHANNEL7)
- {
- *buffer = (uint16_t)(S12ADC0.ADDR7);
- }
- else if (channel == ADTEMPSENSOR)
- {
- *buffer = (uint16_t)(S12ADC0.ADTSDR);
- }
- else if (channel == ADDATADUPLICATION)
- {
- *buffer = (uint16_t)(S12ADC0.ADDBLDR);
- }
- else if (channel == ADDATADUPLICATIONA)
- {
- *buffer = (uint16_t)(S12ADC0.ADDBLDRA);
- }
- else if (channel == ADDATADUPLICATIONB)
- {
- *buffer = (uint16_t)(S12ADC0.ADDBLDRB);
- }
-}
-/***********************************************************************************************************************
-* Function Name: R_S12AD0_Set_CompareValue
-* Description : This function sets reference data for AD0 comparison.
-* Arguments : reg_value0 -
-* reference data 0 for comparison
-* reg_value1 -
-* reference data 1 for comparison
-* Return Value : None
-***********************************************************************************************************************/
-void R_S12AD0_Set_CompareValue(uint16_t reg_value0, uint16_t reg_value1 )
-{
- S12ADC0.ADCMPDR0 = reg_value0;
- S12ADC0.ADCMPDR1 = reg_value1;
-}
-
-/* Start user code for adding. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad.h
deleted file mode 100644
index 722c25f934..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_s12ad.h
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for S12AD module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-#ifndef S12AD_H
-#define S12AD_H
-
-/***********************************************************************************************************************
-Macro definitions (Register bit)
-***********************************************************************************************************************/
-
-/*
- A/D control register (ADCSR)
-*/
-/* Group B scan end interrupt enable (GBADIE) */
-#define _AD_GBADI_DISABLE (0x0000U) /* Disables S12GBADI interrupt generation upon group B scan
- completion */
-#define _AD_GBADI_ENABLE (0x0040U) /* Enables S12GBADI interrupt generation upon group B scan
- completion */
-/* Double trigger mode select (DBLE) */
-#define _AD_DBLTRIGGER_DISABLE (0x0000U) /* Disable double trigger mode */
-#define _AD_DBLTRIGGER_ENABLE (0x0080U) /* Enable double trigger mode */
-/* Trigger select (EXTRG) */
-#define _AD_SYNC_TRIGGER (0x0000U) /* A/D conversion started by snychronous trigger */
-#define _AD_ASYNC_TRIGGER (0x0100U) /* A/D conversion started by asynchronous trigger */
-/* Trigger start enable (TRGE) */
-#define _AD_SYNCASYNCTRG_DISABLE (0x0000U) /* A/D conversion synchronous or asynchronous trigger disable */
-#define _AD_SYNCASYNCTRG_ENABLE (0x0200U) /* A/D conversion synchronous or asynchronous trigger enable */
-/* Scan end interrupt enable (ADIE) */
-#define _AD_SCAN_END_INTERRUPT_DISABLE (0x0000U) /* Disable S12ADI0 interrupt generation upon scan completion */
-#define _AD_SCAN_END_INTERRUPT_ENABLE (0x1000U) /* Enable S12ADI0 interrupt generation upon scan completion */
-/* Scan mode select (ADCS) */
-#define _AD_SINGLE_SCAN_MODE (0x0000U) /* Single scan mode */
-#define _AD_GROUP_SCAN_MODE (0x2000U) /* Group scan mode */
-#define _AD_CONTINUOUS_SCAN_MODE (0x4000U) /* Continuous scan mode */
-/* A/D conversion start (ADST) */
-#define _AD_CONVERSION_STOP (0x0000U) /* Stop A/D conversion */
-#define _AD_CONVERSION_START (0x8000U) /* Start A/D conversion */
-
-/*
- A/D converted value addition count select register (ADADC)
-*/
-/* Addition Count Select (ADC[1:0]) */
-#define _AD_1_TIME_CONVERSION (0x00U) /* 1-time conversion */
-#define _AD_2_TIME_CONVERSION (0x01U) /* 2-time conversion */
-#define _AD_3_TIME_CONVERSION (0x02U) /* 3-time conversion */
-#define _AD_4_TIME_CONVERSION (0x03U) /* 4-time conversion */
-/* Average Mode Enable bit (AVEE) */
-#define _AD_ADDITION_MODE (0x00U) /* Addition mode */
-#define _AD_AVERAGE_MODE (0x80U) /* Average mode */
-
-/*
- A/D control extended register (ADCER)
-*/
-/* A/D Conversion Accuracy Specify (ADPRC) */
-#define _AD_RESOLUTION_12BIT (0x0000U) /* 12 bit resolution */
-#define _AD_RESOLUTION_10BIT (0x0002U) /* 10 bit resolution */
-#define _AD_RESOLUTION_8BIT (0x0004U) /* 8 bit resolution */
-/* Automatic clearing enable (ACE) */
-#define _AD_AUTO_CLEARING_DISABLE (0x0000U) /* Disable auto clearing */
-#define _AD_AUTO_CLEARING_ENABLE (0x0020U) /* Enable auto clearing */
-/* A/D Self-diagnosis selection (DIAGVAL) */
-#define _AD_SELFTDIAGST_DISABLE (0x0000U) /* Disable self-diagnosis */
-#define _AD_SELFTDIAGST_VREFH0_0 (0x0100U) /* Self-diagnosis using a voltage of 0V */
-#define _AD_SELFTDIAGST_VREFH0_HALF (0x0200U) /* Self-diagnosis using a voltage of VREFH0_1/2*/
-#define _AD_SELFTDIAGST_VREFH0 (0x0300U) /* Self-diagnosis using a voltage of VREFH0_1*/
-#define _AD_SELFTDIAGST_VREFH1_0 (0x0100U) /* Self-diagnosis using a voltage of 0V */
-#define _AD_SELFTDIAGST_VREFH1_HALF (0x0200U) /* Self-diagnosis using a voltage of VREFH1_1/2*/
-#define _AD_SELFTDIAGST_VREFH1 (0x0300U) /* Self-diagnosis using a voltage of VREFH1_1*/
-/* A/D Self-diagnostic mode selection (DIAGLD) */
-#define _AD_SELFTDIAGST_ROTATION (0x0000U) /* Rotation mode for self-diagnosis voltage */
-#define _AD_SELFTDIAGST_FIX (0x0400U) /* Fixed mode for self-diagnosis voltage */
-/* A/D Self-diagnostic enable (DIAGM) */
-#define _AD_SELFTDIAGST_DISABLE (0x0000U) /* 12bit self-diagnosis disable */
-#define _AD_SELFTDIAGST_ENABLE (0x0800U) /* 12bit self-diagnosis enable */
-/* A/D data register format selection (ADRFMT) */
-#define _AD_RIGHT_ALIGNMENT (0x0000U) /* Right-alignment for data register format */
-#define _AD_LEFT_ALIGNMENT (0x8000U) /* Left-alignment for data register format */
-
-/*
- A/D start trigger select register (ADSTRGR)
-*/
-/* A/D conversion start trigger select for group B (TRSB) */
-#define _AD_TRSB_TRGA0N (0x0001U) /* Compare match with or input capture to MTU0.TGRA */
-#define _AD_TRSB_TRGA1N (0x0002U) /* Compare match with or input capture to MTU1.TGRA */
-#define _AD_TRSB_TRGA2N (0x0003U) /* Compare match with or input capture to MTU2.TGRA */
-#define _AD_TRSB_TRGA3N (0x0004U) /* Compare match with or input capture to MTU3.TGRA */
-#define _AD_TRSB_TRGA4N (0x0005U) /* Compare match with or input capture to MTU4.TGRA,or an
- underflow of MTU4.TCNT (in the trough) in complementary
- PWM mode */
-#define _AD_TRSB_TRGA6N (0x0006U) /* Compare match with or input capture to MTU6.TGRA */
-#define _AD_TRSB_TRGA7N (0x0007U) /* Compare match with or input capture to MTU7.TGRA,or an
- underflow of MTU7.TCNT (in the trough) in complementary
- PWM mode */
-#define _AD_TRSB_TRG0N (0x0008U) /* Compare match with MTU0.TGRE */
-#define _AD_TRSB_TRG4AN (0x0009U) /* Compare match between MTU4.TADCORA and MTU4.TCNT */
-#define _AD_TRSB_TRG4BN (0x000AU) /* Compare match between MTU4.TADCORB and MTU4.TCNT */
-#define _AD_TRSB_TRG4BN_TRG4AN (0x000BU) /* Compare match between MTU4.TADCORA and MTU4.TCNT, or
- between MTU4.TADCORB and MTU4.TCNT */
-#define _AD_TRSB_TRG4ABN (0x000CU) /* Compare match between MTU4.TADCORA and MTU4.TCNT, and
- between MTU4.TADCORB and MTU4.TCNT (when interrupt skipping
- function 2 is in use) */
-#define _AD_TRSB_TRG7AN (0x000DU) /* Compare match between MTU7.TADCORA and MTU7.TCNT */
-#define _AD_TRSB_TRG7BN (0x000EU) /* Compare match between MTU7.TADCORB and MTU7.TCNT */
-#define _AD_TRSB_TRG7AN_TRG7BN (0x000FU) /* Compare match between MTU7.TADCORA and MTU7.TCNT, or between
- MTU7.TADCORB and MTU7.TCNT */
-#define _AD_TRSB_TRG7ABN (0x0010U) /* Compare match between MTU7.TADCORA and MTU7.TCNT, and between
- MTU7.TADCORB and MTU7.TCNT (when interrupt skipping function
- 2 is in use) */
-#define _AD_TRSB_GTADTRA0N (0x0011U) /* Compare match with GPT0.GTADTRA */
-#define _AD_TRSB_GTADTRB0N (0x0012U) /* Compare match with GPT0.GTADTRB */
-#define _AD_TRSB_GTADTRA1N (0x0013U) /* Compare match with GPT1.GTADTRA */
-#define _AD_TRSB_GTADTRB1N (0x0014U) /* Compare match with GPT1.GTADTRB */
-#define _AD_TRSB_GTADTRA2N (0x0015U) /* Compare match with GPT2.GTADTRA */
-#define _AD_TRSB_GTADTRB2N (0x0016U) /* Compare match with GPT2.GTADTRB */
-#define _AD_TRSB_GTADTRA3N (0x0017U) /* Compare match with GPT3.GTADTRA */
-#define _AD_TRSB_GTADTRB3N (0x0018U) /* Compare match with GPT3.GTADTRB */
-#define _AD_TRSB_GTADTRA0N_GTADTRB0N (0x0019U) /* Compare match with GPT0.GTADTRA or with GPT0.GTADTRB */
-#define _AD_TRSB_GTADTRA1N_GTADTRB1N (0x001AU) /* Compare match with GPT1.GTADTRA or with GPT1.GTADTRB */
-#define _AD_TRSB_GTADTRA2N_GTADTRB2N (0x001BU) /* Compare match with GPT2.GTADTRA or with GPT2.GTADTRB*/
-#define _AD_TRSB_GTADTRA3N_GTADTRB3N (0x001CU) /* Compare match with GPT3.GTADTRA or with GPT3.GTADTRB */
-#define _AD_TRSB_TPTRGAN_0 (0x001FU) /* Compare match with or input capture to TPUn.TGRA(n = 0 to 5) */
-#define _AD_TRSB_TPTRG0AN_0 (0x0020U) /* Compare match with or input capture to TPU0.TGRA */
-#define _AD_TRSB_TPTRGAN_1 (0x0021U) /* Compare match with or input capture to TPUn.TGRA(n = 6 to 11) */
-#define _AD_TRSB_TPTRG6AN_1 (0x0022U) /* Compare match with or input capture to TPU6.TGRA */
-#define _AD_TRSB_ELCTRG0N_ELCTRG1N (0x0030U) /* Trigger from ELC */
-
-/* A/D conversion start trigger select for group A (TRSA) */
-#define _AD_TRSA_ADTRG (0x0000U) /* Input pin for the trigger */
-#define _AD_TRSA_TRGA0N (0x0100U) /* Compare match with or input capture to MTU0.TGRA */
-#define _AD_TRSA_TRGA1N (0x0200U) /* Compare match with or input capture to MTU1.TGRA */
-#define _AD_TRSA_TRGA2N (0x0300U) /* Compare match with or input capture to MTU2.TGRA */
-#define _AD_TRSA_TRGA3N (0x0400U) /* Compare match with or input capture to MTU3.TGRA */
-#define _AD_TRSA_TRGA4N (0x0500U) /* Compare match with or input capture to MTU4.TGRA or, in
- complementary PWM mode,an underflow of MTU4.TCNT
- (in the trough)*/
-#define _AD_TRSA_TRGA6N (0x0600U) /* Compare match with or input capture to MTU6.TGRA */
-#define _AD_TRSA_TRGA7N (0x0700U) /* Compare match with or input capture to MTU7.TGRA or, in
- complementary PWM mode,an underflow of MTU7.TCNT
- (in the trough)*/
-#define _AD_TRSA_TRG0N (0x0800U) /* Compare match with MTU0.TGRE */
-#define _AD_TRSA_TRG4AN (0x0900U) /* Compare match between MTU4.TADCORA and MTU4.TCNT */
-#define _AD_TRSA_TRG4BN (0x0A00U) /* Compare match between MTU4.TADCORB and MTU4.TCNT */
-#define _AD_TRSA_TRG4BN_TRG4AN (0x0B00U) /* Compare match between MTU4.TADCORA and MTU4.TCNT, or between
- MTU4.TADCORB and MTU4.TCNT */
-#define _AD_TRSA_TRG4ABN (0x0C00U) /* Compare match between MTU4.TADCORA and MTU4.TCNT, and between
- MTU4.TADCORB and MTU4.TCNT (when interrupt skipping function
- 2 is in use) */
-#define _AD_TRSA_TRG7AN (0x0D00U) /* Compare match between MTU7.TADCORA and MTU7.TCNT */
-#define _AD_TRSA_TRG7BN (0x0E00U) /* Compare match between MTU7.TADCORB and MTU7.TCNT */
-#define _AD_TRSA_TRG7AN_TRG7BN (0x0F00U) /* Compare match between MTU7.TADCORA and MTU7.TCNT, or between
- MTU7.TADCORB and MTU7.TCNT */
-#define _AD_TRSA_TRG7ABN (0x1000U) /* Compare match between MTU7.TADCORA and MTU7.TCNT, and between
- MTU7.TADCORB and MTU7.TCNT (when interrupt skipping function
- 2 is in use) */
-#define _AD_TRSA_GTADTRA0N (0x1100U) /* Compare match with GPT0.GTADTRA */
-#define _AD_TRSA_GTADTRB0N (0x1200U) /* Compare match with GPT0.GTADTRB */
-#define _AD_TRSA_GTADTRA1N (0x1300U) /* Compare match with GPT1.GTADTRA */
-#define _AD_TRSA_GTADTRB1N (0x1400U) /* Compare match with GPT1.GTADTRB */
-#define _AD_TRSA_GTADTRA2N (0x1500U) /* Compare match with GPT2.GTADTRA */
-#define _AD_TRSA_GTADTRB2N (0x1600U) /* Compare match with GPT2.GTADTRB */
-#define _AD_TRSA_GTADTRA3N (0x1700U) /* Compare match with GPT3.GTADTRA */
-#define _AD_TRSA_GTADTRB3N (0x1800U) /* Compare match with GPT3.GTADTRB */
-#define _AD_TRSA_GTADTRA0N_GTADTRB0N (0x1900U) /* Compare match with GPT0.GTADTRA or with GPT0.GTADTRB */
-#define _AD_TRSA_GTADTRA1N_GTADTRB1N (0x1A00U) /* Compare match with GPT1.GTADTRA or with GPT1.GTADTRB */
-#define _AD_TRSA_GTADTRA2N_GTADTRB2N (0x1B00U) /* Compare match with GPT2.GTADTRA or with GPT2.GTADTRB */
-#define _AD_TRSA_GTADTRA3N_GTADTRB3N (0x1C00U) /* Compare match with GPT3.GTADTRA or with GPT3.GTADTRB */
-#define _AD_TRSA_TPTRGAN_0 (0x1F00U) /* Compare match with or input capture to TPUn.TGRA(n= 0 to 5) */
-#define _AD_TRSA_TPTRG0AN_0 (0x2000U) /* Compare match with or input capture to TPU0.TGRA */
-#define _AD_TRSA_TPTRGAN_1 (0x2100U) /* Compare match with or input capture to TPUn.TGRA(n= 6 to 11) */
-#define _AD_TRSA_TPTRG6AN_1 (0x2200U) /* Compare match with or input capture to TPU6.TGRA */
-#define _AD_TRSA_ELCTRG0N_ELCTRG1N (0x3000U) /* Trigger from ELC */
-
-/*
- A/D converted extended input control register (ADEXICR)
-*/
-/* Temperature sensor output A/D conversion value addition mode selection (TSSAD) */
-#define _AD_TEMP_ADDITION_DISABLE (0x0000U) /* Temperature sensor output A/D converted value addition/average
- mode disabled */
-#define _AD_TEMP_ADDITION_ENABLE (0x0001U) /* Temperature sensor output A/D converted value addition/average
- mode enabled */
-/* Temperature sensor output A/D conversion select (TSSA) */
-#define _AD_TEMP_GROUPA_DISABLE (0x0000U) /* A/D conversion of temperature sensor output is disabled in
- group A */
-#define _AD_TEMP_GROUPA_ENABLE (0x0100U) /* A/D conversion of temperature sensor output is enabled in
- group A */
-/* Temperature sensor output A/D conversion select (TSSB) */
-#define _AD_TEMP_GROUPB_DISABLE (0x0000U) /* A/D conversion of temperature sensor output is disabled in
- group B */
-#define _AD_TEMP_GROUPB_ENABLE (0x0400U) /* A/D conversion of temperature sensor output is enabled in
- group B */
-/* Extended analog input selection (EXSEL) */
-#define _AD_EXTNANEX1_IN_DISABLE (0x0000U) /* Extended analog input disable */
-#define _AD_EXTNANEX1_IN_ENABLE (0x2000U) /* Extended analog input enable */
-/* Extended analog output control (EXOEN) */
-#define _AD_EXTNANEX0_OUT_DISABLE (0x0000U) /* Extended analog output disable */
-#define _AD_EXTNANEX0_IN_ENABLE (0x8000U) /* Extended analog output enable */
-
-/*
- A/D Group Scan Priority Control Register (ADGSPCR)
-*/
-/* Group-A Priority Control Setting (PGS) */
-#define _AD_GPAPRIORITY_DISABLE (0x0000U) /* Operation is without group A priority control */
-#define _AD_GPAPRIORITY_ENABLE (0x0001U) /* Operation is with group A priority control */
-/* Group B Restart Setting (GBRSCN) */
-#define _AD_GPBRESTART_DISABLE (0x0000U) /* Group B not restart after discontinued due to Group A
- priority */
-#define _AD_GPBRESTART_ENABLE (0x0002U) /* Group B restart after discontinued due to Group A priority */
-/* Group B Single Cycle Scan Continuous Start (GBRP) */
-#define _AD_GPBSCSCS_DISABLE (0x0000U) /* Single cycle scan for group B not continuously activated */
-#define _AD_GPBSCSCS_ENABLE (0x8000U) /* Single cycle scan for group B is continuously activated */
-
-/*
- A/D Compare Control Register (ADCMPCR)
-*/
-/* Window Function Setting (WCMPE) */
-#define _AD_WINDOWFUNCTION_DISABLE (0x00U) /* Window function disabled */
-#define _AD_WINDOWFUNCTION_ENABLE (0x40U) /* Window function enabled */
-/* Compare Interrupt Enable (CMPIE) */
-#define _AD_COMPARISON_INTERRUPT_DISABLE (0x00U) /* S12CMPI interrupt is disabled */
-#define _AD_COMPARISON_INTERRUPT_ENABLE (0x80U) /* S12CMPI interrupt is enabled */
-
-/*
- A/D Compare Channel Select Extended Register (ADCMPANSER)
-*/
-/* Temperature Sensor Output Compare Select(CMPSTS) */
-#define _AD_TEMP_COMPARE_DISABLE (0x00U) /* Temperature sensor output is not a target for comparison. */
-#define _AD_TEMP_COMPARE_ENABLE (0x01U) /* Temperature sensor output is a target for comparison. */
-
-/*
- A/D Compare Level Extended Register (ADCMPLER)
-*/
-/* Temperature Sensor Output Compare Level Select(CMPLTS) */
-#define _AD_TEMP0_COMPARELEVEL (0x00U) /* AD-converted value < ADCMPDR0 register value or A/D-converted
- value > ADCMPDR1 register value */
-#define _AD_TEMP1_COMPARELEVEL (0x01U) /* ADCMPDR0 register value < A/D-converted value < ADCMPDR1
- register value */
-
-/*
- A/D Pin-Level Self-Diagnosis Control Register (ADTDCR)
-*/
-/* Pin-level Self-diagnosis Level Select (TDLV[1:0]) */
-#define _AD_EVEN_AVSS0 (0x00U) /* Input channels with even numbers are discharged to AVSS,
- and input channels with odd numbers are charged to AVCC. */
-#define _AD_EVEN_AVCC0 (0x01U) /* Input channels with even numbers are charged to AVCC,
- and input channels with odd numbers are discharged to AVSS. */
-#define _AD_ODD_AVCC0_HALF (0x02U) /* Input channels with even numbers are discharged to AVSS,
- and input channels with odd numbers are charged to AVCx1/2. */
-#define _AD_EVEN_AVCC0_HALF (0x03U) /* Input channels with even numbers are charged to AVCCx1/2,
- and input channels with odd numbers are discharged to AVSS. */
-#define _AD_EVEN_AVSS1 (0x00U) /* Input channels with even numbers are discharged to AVSS,
- and input channels with odd numbers are charged to AVCC. */
-#define _AD_EVEN_AVCC1 (0x01U) /* Input channels with even numbers are charged to AVCC,
- and input channels with odd numbers are discharged to AVSS. */
-#define _AD_ODD_AVCC1_HALF (0x02U) /* Input channels with even numbers are discharged to AVSS,
- and input channels with odd numbers are charged to AVCx1/2. */
-#define _AD_EVEN_AVCC1_HALF (0x03U) /* Input channels with even numbers are charged to AVCCx1/2,
- and input channels with odd numbers are discharged to AVSS. */
-/* Pin-level Self-diagnosis Enable (TDE) */
-#define _AD_PINLVL_ENABLE (0x00U) /* Enables pin-level self-diagnosis. */
-#define _AD_PINLVL_DISABLE (0x80U) /* Disables pin-level self-diagnosis. */
-
-
-/*
- A/D Error Control Register (ADERCR)
-*/
-/* Overwrite Error Interrupt Enable (OWEIE) */
-#define _AD_ERROR_INT_REQUEST_DISABLE (0x00U) /* Disables interrupt generation when an overwrite error is detected. */
-#define _AD_ERROR_INT_REQUEST_ENABLE (0x04U) /* Enables interrupt generation when an overwrite error is detected. */
-
-/*
- Interrupt Source Priority Register n (PRLn)
-*/
-/* Interrupt Priority Level Select (PRL[3:0]) */
-#define _AD_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
-#define _AD_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
-#define _AD_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
-#define _AD_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
-#define _AD_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
-#define _AD_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
-#define _AD_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
-#define _AD_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
-#define _AD_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
-#define _AD_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
-#define _AD_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
-#define _AD_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
-#define _AD_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
-#define _AD_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
-#define _AD_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
-#define _AD_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
-
-/***********************************************************************************************************************
-Macro definitions
-***********************************************************************************************************************/
-#define _AD0_CHANNEL_SELECT_A (0x0080U)
-#define _AD0_ADDAVG_CHANNEL_SELECT (0x0000U)
-#define _AD0_DISCONECT_SETTING (0x00U)
-#define _AD0_COMPARECHANNEL_SELECT (0x0000U)
-#define _AD0_COMPARELEVEL_SELECT (0x0000U)
-#define _AD0_SAMPLING_STATE_7 (0x16U)
-
-/***********************************************************************************************************************
-Typedef definitions
-***********************************************************************************************************************/
-typedef enum
-{
- ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL4, ADCHANNEL5, ADCHANNEL6,
- ADCHANNEL7, ADCHANNEL8, ADCHANNEL9, ADCHANNEL10, ADCHANNEL11, ADCHANNEL12,
- ADCHANNEL13, ADCHANNEL14, ADCHANNEL15, ADSELFDIAGNOSIS, ADTEMPSENSOR, ADDATADUPLICATION,
- ADDATADUPLICATIONA, ADDATADUPLICATIONB
-} ad_channel_t;
-
-/***********************************************************************************************************************
-Global functions
-***********************************************************************************************************************/
-void R_S12AD0_Create(void);
-void R_S12AD0_Start(void);
-void R_S12AD0_Stop(void);
-void R_S12AD0_Get_ValueResult(ad_channel_t channel, uint16_t * const buffer);
-void R_S12AD0_Set_CompareValue(uint16_t reg_value0, uint16_t reg_value1);
-
-/* Start user code for function. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad_user.c
deleted file mode 100644
index 6ce08b2c69..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_s12ad_user.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_s12ad_user.c
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for S12AD module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-Pragma directive
-***********************************************************************************************************************/
-/* Start user code for pragma. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-Includes
-***********************************************************************************************************************/
-#include "r_cg_macrodriver.h"
-#include "r_cg_s12ad.h"
-/* Start user code for include. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-#include "r_cg_userdefine.h"
-
-/***********************************************************************************************************************
-Global variables and functions
-***********************************************************************************************************************/
-/* Start user code for global. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-* Function Name: r_s12ad_s12adi0_interrupt
-* Description : This function is ADI0 interrupt service routine.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_s12ad_s12adi0_interrupt(void)
-{
- /* Clear the interrupt source S12ADI0 */
- VIC.PIC1.LONG = 0x00000008UL;
-
- /* Start user code. Do not edit comment generated here */
- /* End user code. Do not edit comment generated here */
-
- /* Dummy write */
- VIC.HVA0.LONG = 0x00000000UL;
-}
-
-/* Start user code for adding. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa.c
deleted file mode 100644
index 6eb85d04bb..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_scifa.c
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for SCIF module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-Pragma directive
-***********************************************************************************************************************/
-/* Start user code for pragma. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-Includes
-***********************************************************************************************************************/
-#include "r_cg_macrodriver.h"
-#include "r_cg_scifa.h"
-/* Start user code for include. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-#include "r_cg_userdefine.h"
-
-/***********************************************************************************************************************
-Global variables and functions
-***********************************************************************************************************************/
-const uint8_t * gp_scifa2_tx_address; /* SCIFA2 transmit buffer address */
-uint16_t g_scifa2_tx_count; /* SCIFA2 transmit data number */
-uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */
-uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */
-uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */
-/* Start user code for global. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-* Function Name: R_SCIFA2_Create
-* Description : This function initializes SCIFA2.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_SCIFA2_Create(void)
-{
- volatile uint16_t dummy;
- uint16_t w_count;
-
- /* Cancel SCIFA2 module stop state */
- MSTP(SCIFA2) = 0U;
-
- /* Disable TXIF2 interrupt */
- VIC.IEC3.LONG = 0x00008000UL;
-
- /* Disable RXIF2 interrupt */
- VIC.IEC3.LONG = 0x00004000UL;
-
- /* Disable BRIF2 interrupt */
- VIC.IEC3.LONG = 0x00002000UL;
-
- /* Disable DRIF2 interrupt */
- VIC.IEC3.LONG = 0x00010000UL;
-
- /* Clear transmit/receive enable bits */
- SCIFA2.SCR.BIT.TE = 0U;
- SCIFA2.SCR.BIT.RE = 0U;
-
- /* Reset transmit/receive FIFO data register operation */
- SCIFA2.FCR.BIT.TFRST = 1U;
- SCIFA2.FCR.BIT.RFRST = 1U;
-
- /* Read and clear status flags */
- dummy = SCIFA2.FSR.WORD;
- ( void ) dummy;
- SCIFA2.FSR.WORD = 0x00U;
- dummy = (uint16_t) SCIFA2.LSR.BIT.ORER;
- ( void ) dummy;
- SCIFA2.LSR.BIT.ORER = 0U;
-
- /* Set clock enable bits */
- SCIFA2.SCR.WORD = _SCIF_INTERNAL_SCK_UNUSED;
-
- /* Set transmission/reception format */
- SCIFA2.SMR.WORD = _SCIF_CLOCK_SERICLK_4 | _SCIF_STOP_1 | _SCIF_PARITY_DISABLE | _SCIF_DATA_LENGTH_8 |
- _SCIF_ASYNCHRONOUS_MODE;
- SCIFA2.SEMR.BYTE = _SCIF_16_BASE_CLOCK | _SCIF_NOISE_FILTER_ENABLE | _SCIF_DATA_TRANSFER_LSB_FIRST |
- _SCIF_BAUDRATE_SINGLE;
-
- /* Clear modulation duty register select */
- SCIFA2.SEMR.BIT.MDDRS = 0U;
-
- /* Set bit rate */
- SCIFA2.BRR_MDDR.BRR = 0x3CU;
-
- /* Wait for at least 1-bit interval */
- for (w_count = 0U; w_count < _SCIF_1BIT_INTERVAL_2; w_count++)
- {
- nop();
- }
-
- /* Set FIFO trigger conditions */
- SCIFA2.FTCR.WORD = _SCIF_TX_FIFO_TRIGGER_NUM_0 | _SCIF_TX_TRIGGER_TFTC_VALID | _SCIF_RX_FIFO_TRIGGER_NUM_1 |
- _SCIF_RX_TRIGGER_RFTC_VALID;
- SCIFA2.FCR.WORD = _SCIF_LOOPBACK_DISABLE | _SCIF_MODEM_CONTROL_DISABLE;
-
- /* Disable transmit/receive FIFO data register reset operation */
- SCIFA2.FCR.BIT.TFRST = 0U;
- SCIFA2.FCR.BIT.RFRST = 0U;
-
- /* Set TXIF2 interrupt priority */
- VIC.PRL111.LONG = _SCIF_PRIORITY_LEVEL2;
-
- /* Set TXIF2 interrupt address */
- VIC.VAD111.LONG = (uint32_t)r_scifa2_txif2_interrupt;
-
- /* Set RXIF2 interrupt priority */
- VIC.PRL110.LONG = _SCIF_PRIORITY_LEVEL3;
-
- /* Set RXIF2 interrupt address */
- VIC.VAD110.LONG = (uint32_t)r_scifa2_rxif2_interrupt;
-
- /* Set BRIF2 interrupt priority */
- VIC.PRL109.LONG = _SCIF_PRIORITY_LEVEL5;
-
- /* Set BRIF2 interrupt address */
- VIC.VAD109.LONG = (uint32_t)r_scifa2_brif2_interrupt;
-
- /* Set DRIF2 interrupt priority */
- VIC.PRL112.LONG = _SCIF_PRIORITY_LEVEL4;
-
- /* Set DRIF2 interrupt address */
- VIC.VAD112.LONG = (uint32_t)r_scifa2_drif2_interrupt;
-}
-/***********************************************************************************************************************
-* Function Name: R_SCIFA2_Start
-* Description : This function starts SCIFA2.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_SCIFA2_Start(void)
-{
- /* Enable TXIF2 interrupt */
- VIC.IEN3.LONG |= 0x00008000UL;
-
- /* Enable RXIF2 interrupt */
- VIC.IEN3.LONG |= 0x00004000UL;
-
- /* Enable BRIF2 interrupt */
- VIC.IEN3.LONG |= 0x00002000UL;
-
- /* Enable DRIF2 interrupt */
- VIC.IEN3.LONG |= 0x00010000UL;
-}
-/***********************************************************************************************************************
-* Function Name: R_SCIFA2_Stop
-* Description : This function stops SCIFA2.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void R_SCIFA2_Stop(void)
-{
- /* Disable serial transmit */
- SCIFA2.SCR.BIT.TE = 0U;
-
- /* Disable serial receive */
- SCIFA2.SCR.BIT.RE = 0U;
-
- /* Disable TXI interrupt */
- SCIFA2.SCR.BIT.TIE = 0U;
-
- /* Disable RXI and ERI interrupt */
- SCIFA2.SCR.BIT.RIE = 0U;
-
- /* Disable TXIF2 interrupt */
- VIC.IEC3.LONG = 0x00008000UL;
-
- /* Disable RXIF2 interrupt */
- VIC.IEC3.LONG = 0x00004000UL;
-
- /* Disable BRIF2 interrupt */
- VIC.IEC3.LONG = 0x00002000UL;
-
- /* Disable DRIF2 interrupt */
- VIC.IEC3.LONG = 0x00010000UL;
-}
-/***********************************************************************************************************************
-* Function Name: R_SCIFA2_Serial_Receive
-* Description : This function receives SCIFA2 data.
-* Arguments : rx_buf -
-* receive buffer pointer (Not used when receive data handled by DMAC)
-* rx_num -
-* buffer size (Not used when receive data handled by DMAC)
-* Return Value : status -
-* MD_OK or MD_ARGERROR
-***********************************************************************************************************************/
-MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num)
-{
- MD_STATUS status = MD_OK;
-
- if (rx_num < 1U)
- {
- status = MD_ARGERROR;
- }
- else
- {
- g_scifa2_rx_count = 0U;
- g_scifa2_rx_length = rx_num;
- gp_scifa2_rx_address = rx_buf;
-
- SCIFA2.FTCR.BIT.RFTC = _SCIF_RX_TRIG_NUM_2;
-
- SCIFA2.SCR.BIT.RE = 1U;
- SCIFA2.SCR.BIT.RIE = 1U;
- SCIFA2.SCR.BIT.REIE = 1U;
- }
-
- return (status);
-}
-/***********************************************************************************************************************
-* Function Name: R_SCIFA2_Serial_Send
-* Description : This function transmits SCIFA2 data.
-* Arguments : tx_buf -
-* transfer buffer pointer (Not used when transmit data handled by DMAC)
-* tx_num -
-* buffer size (Not used when transmit data handled by DMAC)
-* Return Value : status -
-* MD_OK or MD_ARGERROR
-***********************************************************************************************************************/
-MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num)
-{
- MD_STATUS status = MD_OK;
-
- if (tx_num < 1U)
- {
- status = MD_ARGERROR;
- }
- else
- {
- gp_scifa2_tx_address = tx_buf;
- g_scifa2_tx_count = tx_num;
- SCIFA2.SCR.BIT.TE = 1U;
- SCIFA2.SCR.BIT.TIE = 1U;
- }
-
- return (status);
-}
-
-/* Start user code for adding. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa.h
deleted file mode 100644
index 0d291e0a84..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_scifa.h
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for SCIF module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-#ifndef SCIF_H
-#define SCIF_H
-
-/***********************************************************************************************************************
-Macro definitions (Register bit)
-***********************************************************************************************************************/
-
-/*
- Serial mode register (SMR)
-*/
-/* Clock select (CKS[1:0]) */
-#define _SCIF_CLOCK_SERICLK (0x0000U) /* SERICLK */
-#define _SCIF_CLOCK_SERICLK_4 (0x0001U) /* SERICLK/4 */
-#define _SCIF_CLOCK_SERICLK_16 (0x0002U) /* SERICLK/16 */
-#define _SCIF_CLOCK_SERICLK_64 (0x0003U) /* SERICLK/64 */
-/* Stop bit length (STOP) */
-#define _SCIF_STOP_1 (0x0000U) /* 1 stop bit */
-#define _SCIF_STOP_2 (0x0008U) /* 2 stop bits */
-/* Parity mode (PM) */
-#define _SCIF_PARITY_EVEN (0x0000U) /* Parity even */
-#define _SCIF_PARITY_ODD (0x0010U) /* Parity odd */
-/* Parity enable (PE) */
-#define _SCIF_PARITY_DISABLE (0x0000U) /* Parity disable */
-#define _SCIF_PARITY_ENABLE (0x0020U) /* Parity enable */
-/* Character length (CHR) */
-#define _SCIF_DATA_LENGTH_8 (0x0000U) /* Data length 8 bits */
-#define _SCIF_DATA_LENGTH_7 (0x0040U) /* Data length 7 bits */
-/* Communications mode (CM) */
-#define _SCIF_ASYNCHRONOUS_MODE (0x0000U) /* Asynchronous mode */
-#define _SCIF_CLOCK_SYNCHRONOUS_MODE (0x0080U) /* Clock synchronous mode */
-
-/*
- Serial control register (SCR)
-*/
-/* Clock enable (CKE) */
-#define _SCIF_INTERNAL_SCK_UNUSED (0x0000U) /* Internal clock selected, SCK pin unused */
-#define _SCIF_INTERNAL_SCK_OUTPUT (0x0001U) /* Internal clock selected, SCK pin as clock output */
-/* Clock enable (CKE) for clock synchronous mode */
-#define _SCIF_INTERNAL_SCK_OUTPUT_SYNC (0x0000U) /* Internal clock, SCK pin is used for clock output */
-#define _SCIF_EXTERNAL_SCK_INPUT_SYNC (0x0002U) /* External clock, SCK pin is used for clock input */
-/* Transmit end interrupt enable (TEIE) */
-#define _SCIF_TEI_INTERRUPT_DISABLE (0x0000U) /* TEI interrupt request disable */
-#define _SCIF_TEI_INTERRUPT_ENABLE (0x0004U) /* TEI interrupt request enable */
-/* Receive error interrupt enable (REIE) */
-#define _SCIF_ERI_BRI_INTERRUPT_DISABLE (0x0000U) /* Disable receive-error interrupt and break interrupt */
-#define _SCIF_ERI_BRI_INTERRUPT_ENABLE (0x0008U) /* Enable receive-error interrupt and break interrupt */
-/* Receive enable (RE) */
-#define _SCIF_RECEIVE_DISABLE (0x0000U) /* Disable receive mode */
-#define _SCIF_RECEIVE_ENABLE (0x0010U) /* Enable receive mode */
-/* Transmit enable (TE) */
-#define _SCIF_TRANSMIT_DISABLE (0x0000U) /* Disable transmit mode */
-#define _SCIF_TRANSMIT_ENABLE (0x0020U) /* Enable transmit mode */
-/* Receive interrupt enable (RIE) */
-#define _SCIF_RXI_ERI_DISABLE (0x0000U) /* Disable RXI and ERI interrupt requests */
-#define _SCIF_RXI_ERI_ENABLE (0x0040U) /* Enable RXI and ERI interrupt requests */
-/* Transmit interrupt enable (TIE) */
-#define _SCIF_TXI_DISABLE (0x0000U) /* Disable TXI interrupt requests */
-#define _SCIF_TXI_ENABLE (0x0080U) /* Enable TXI interrupt requests */
-
-/*
- FIFO control register (FCR)
-*/
-/* Loop-Back test (LOOP) */
-#define _SCIF_LOOPBACK_DISABLE (0x0000U) /* Loop back test is disabled */
-#define _SCIF_LOOPBACK_ENABLE (0x0001U) /* Loop back test is enabled */
-/* Receive FIFO Data Register Reset (RFRST) */
-#define _SCIF_RX_FIFO_RESET_DISABLE (0x0000U) /* FRDR reset operation is disabled */
-#define _SCIF_RX_FIFO_RESET_ENABLE (0x0002U) /* FRDR reset operation is enabled */
-/* Transmit FIFO Data Register Reset (TFRST) */
-#define _SCIF_TX_FIFO_RESET_DISABLE (0x0000U) /* FTDR reset operation is disabled */
-#define _SCIF_TX_FIFO_RESET_ENABLE (0x0004U) /* FTDR reset operation is enabled */
-/* Modem control enable (MCE) */
-#define _SCIF_MODEM_CONTROL_DISABLE (0x0000U) /* Model signal is disabled */
-#define _SCIF_MODEM_CONTROL_ENABLE (0x0008U) /* Model signal is enabled */
-/* Transmit FIFO Data Trigger Number (TTRG[1:0]) */
-#define _SCIF_TX_TRIGGER_NUMBER_8 (0x0000U) /* 8 (or 8 when TDFE flag is 1) */
-#define _SCIF_TX_TRIGGER_NUMBER_4 (0x0010U) /* 4 (or 12 when TDFE flag is 1) */
-#define _SCIF_TX_TRIGGER_NUMBER_2 (0x0020U) /* 2 (or 14 when TDFE flag is 1) */
-#define _SCIF_TX_TRIGGER_NUMBER_0 (0x0030U) /* 0 (or 16 when TDFE flag is 1) */
-/* Receive FIFO Data Trigger Number (RTRG[1:0]) */
-#define _SCIF_RX_TRIGGER_NUMBER_1 (0x0000U) /* 1 */
-#define _SCIF_RX_TRIGGER_NUMBER_4 (0x0040U) /* 4 (for asynchronous mode) */
-#define _SCIF_RX_TRIGGER_NUMBER_2 (0x0040U) /* 2 (for clock synchronous mode */
-#define _SCIF_RX_TRIGGER_NUMBER_8 (0x0080U) /* 8 */
-#define _SCIF_RX_TRIGGER_NUMBER_14 (0x00C0U) /* 14 */
-/* RTS# Output Active Trigger Number Select (RSTRG[2:0]) */
-#define _SCIF_RTS_TRIGGER_NUMBER_15 (0x0000U) /* 15 */
-#define _SCIF_RTS_TRIGGER_NUMBER_1 (0x0100U) /* 1 */
-#define _SCIF_RTS_TRIGGER_NUMBER_4 (0x0200U) /* 4 */
-#define _SCIF_RTS_TRIGGER_NUMBER_6 (0x0300U) /* 6 */
-#define _SCIF_RTS_TRIGGER_NUMBER_8 (0x0400U) /* 8 */
-#define _SCIF_RTS_TRIGGER_NUMBER_10 (0x0500U) /* 10 */
-#define _SCIF_RTS_TRIGGER_NUMBER_12 (0x0600U) /* 12 */
-#define _SCIF_RTS_TRIGGER_NUMBER_14 (0x0700U) /* 14 */
-
-/*
- Serial port register (SPTR)
-*/
-/* Serial Port Break Data (SPB2DT) */
-#define _SCIF_SERIAL_BREAK_DATA_LOW (0x0000U) /* Input/output data is at low */
-#define _SCIF_SERIAL_BREAK_DATA_HIGH (0x0001U) /* Input/output data is at high */
-/* Serial Port Break input/output (SPB2IO) */
-#define _SCIF_SERIAL_BREAK_TXD_NO_OUTPUT (0x0000U) /* SPB2DT bit value is not output to TXD pin */
-#define _SCIF_SERIAL_BREAK_TXD_OUTPUT (0x0002U) /* SPB2DT bit value is output to TXD pin */
-/* SCK Port Data (SCKDT) */
-#define _SCIF_SCK_DATA_LOW (0x0000U) /* Input/output data is at low */
-#define _SCIF_SCK_DATA_HIGH (0x0004U) /* Input/output data is at high */
-/* SCK Port input/output (SCKIO) */
-#define _SCIF_SCK_PORT_NO_OUTPUT (0x0000U) /* SCKDT bit value is not output to SCK pin */
-#define _SCIF_SCK_PORT_OUTPUT (0x0008U) /* SCKDT bit value is output to SCK pin */
-/* CTS# Port Data Select (CTS2DT) */
-#define _SCIF_CTS_DATA_0 (0x0000U) /* Set b4 to 0. Controls CTS# pin with MCE, CTS2IO bit */
-#define _SCIF_CTS_DATA_1 (0x0010U) /* Set b4 to 1. Controls CTS# pin with MCE, CTS2IO bit */
-/* CTS# Port Output Specify (CTS2IO) */
-#define _SCIF_CTS_OUTPUT_0 (0x0000U) /* Set b5 to 0. Controls CTS# pin with MCE, CTS2IO bit */
-#define _SCIF_CTS_OUTPUT_1 (0x0020U) /* Set b5 to 1. Controls CTS# pin with MCE, CTS2IO bit */
-/* RTS# Port Data Select (RTS2DT) */
-#define _SCIF_RTS_DATA_0 (0x0000U) /* Set b6 to 0. Controls RTS# pin with MCE, RTS2IO bit */
-#define _SCIF_RTS_DATA_1 (0x0040U) /* Set b6 to 1. Controls RTS# pin with MCE, RTS2IO bit */
-/* RTS# Port Output Specify (RTS2IO) */
-#define _SCIF_RTS_OUTPUT_0 (0x0000U) /* Set b7 to 0. Controls RTS# pin with MCE, RTS2IO bit */
-#define _SCIF_RTS_OUTPUT_1 (0x0080U) /* Set b7 to 1. Controls RTS# pin with MCE, RTS2IO bit */
-
-/*
- FIFO Trigger Control Register (FTCR)
-*/
-/* Transmit FIFO Data Trigger Number (TFTC[4:0]) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_0 (0x0000U) /* 0 (no transmit data trigger) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_1 (0x0001U) /* 1 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_2 (0x0002U) /* 2 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_3 (0x0003U) /* 3 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_4 (0x0004U) /* 4 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_5 (0x0005U) /* 5 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_6 (0x0006U) /* 6 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_7 (0x0007U) /* 7 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_8 (0x0008U) /* 8 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_9 (0x0009U) /* 9 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_10 (0x000AU) /* 10 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_11 (0x000BU) /* 11 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_12 (0x000CU) /* 12 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_13 (0x000DU) /* 13 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_14 (0x000EU) /* 14 (transmit data triggers) */
-#define _SCIF_TX_FIFO_TRIGGER_NUM_15 (0x000FU) /* 15 (transmit data triggers) */
-/* Transmit Trigger Select (TTRGS) */
-#define _SCIF_TX_TRIGGER_TTRG_VALID (0x0000U) /* TTRG[1:0] bits in FCR are valid */
-#define _SCIF_TX_TRIGGER_TFTC_VALID (0x0080U) /* TFTC[4:0] bits in FTCR are valid */
-/* Receive FIFO Data Trigger Number (RFTC[4:0]) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_1 (0x0100U) /* 1 (no receive data trigger) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_2 (0x0200U) /* 2 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_3 (0x0300U) /* 3 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_4 (0x0400U) /* 4 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_5 (0x0500U) /* 5 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_6 (0x0600U) /* 6 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_7 (0x0700U) /* 7 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_8 (0x0800U) /* 8 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_9 (0x0900U) /* 9 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_10 (0x0A00U) /* 10 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_11 (0x0B00U) /* 11 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_12 (0x0C00U) /* 12 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_13 (0x0D00U) /* 13 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_14 (0x0E00U) /* 14 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_15 (0x0F00U) /* 15 (receive data triggers) */
-#define _SCIF_RX_FIFO_TRIGGER_NUM_16 (0x1000U) /* 16 (receive data triggers) */
-/* Transmit Trigger Select (RTRGS) */
-#define _SCIF_RX_TRIGGER_RTRG_VALID (0x0000U) /* RTRG[1:0] bits in FCR are valid */
-#define _SCIF_RX_TRIGGER_RFTC_VALID (0x8000U) /* RFTC[4:0] bits in FTCR are valid */
-
-/*
- Serial extended mode register (SEMR)
-*/
-/* Asynchronous base clock select (ABCS0) */
-#define _SCIF_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */
-#define _SCIF_8_BASE_CLOCK (0x01U) /* Selects 8 base clock cycles for 1 bit period */
-/* Noise Cancellation Enable (NFEN) */
-#define _SCIF_NOISE_FILTER_DISABLE (0x00U) /* Noise cancellation for the RxD pin input is disabled */
-#define _SCIF_NOISE_FILTER_ENABLE (0x04U) /* Noise cancellation for the RxD pin input is enabled */
-/* Data Transfer Direction Select (DIR) */
-#define _SCIF_DATA_TRANSFER_LSB_FIRST (0x00U) /* Transmits the data in FTDR by the LSB-first method */
-#define _SCIF_DATA_TRANSFER_MSB_FIRST (0x08U) /* Transmits the data in FTDR by the MSB-first method */
-/* Modulation Duty Register Select (MDDRS) */
-#define _SCIF_BRR_USED (0x00U) /* BRR register can be accessed */
-#define _SCIF_MDDR_USED (0x10U) /* MDDR register can be accessed. */
-/* Bit Rate Modulation Enable (BRME) */
-#define _SCIF_BIT_RATE_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */
-#define _SCIF_BIT_RATE_MODULATION_ENABLE (0x20U) /* Bit rate modulation function is enabled */
-/* Baud Rate Generator Double-Speed Mode Select (BGDM) */
-#define _SCIF_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */
-#define _SCIF_BAUDRATE_DOUBLE (0x80U) /* Baud rate generator doubles output frequency */
-
-/*
- Interrupt Source Priority Register n (PRLn)
-*/
-/* Interrupt Priority Level Select (PRL[3:0]) */
-#define _SCIF_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
-#define _SCIF_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
-#define _SCIF_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
-#define _SCIF_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
-#define _SCIF_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
-#define _SCIF_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
-#define _SCIF_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
-#define _SCIF_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
-#define _SCIF_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
-#define _SCIF_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
-#define _SCIF_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
-#define _SCIF_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
-#define _SCIF_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
-#define _SCIF_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
-#define _SCIF_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
-#define _SCIF_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
-
-/* FIFO buffer maximum size */
-#define _SCIF_FIFO_MAX_SIZE (0x10U) /* Size of 16-stage FIFO buffer */
-
-/***********************************************************************************************************************
-Macro definitions
-***********************************************************************************************************************/
-#define _SCIF_1BIT_INTERVAL_2 (0x0619U) /* Wait time for 1-bit interval */
-#define _SCIF_RX_TRIG_NUM_2 (0x01U) /* Receive FIFO data trigger number */
-
-/***********************************************************************************************************************
-Typedef definitions
-***********************************************************************************************************************/
-typedef enum
-{
- OVERRUN_ERROR,
- BREAK_DETECT,
- RECEIVE_ERROR
-} scif_error_type_t;
-
-/***********************************************************************************************************************
-Global functions
-***********************************************************************************************************************/
-void R_SCIFA2_Create(void);
-void R_SCIFA2_Start(void);
-void R_SCIFA2_Stop(void);
-MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num);
-MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num);
-void r_scifa2_callback_transmitend(void);
-void r_scifa2_callback_receiveend(void);
-void r_scifa2_callback_error(scif_error_type_t error_type);
-
-/* Start user code for function. Do not edit comment generated here */
-
-/* Contains status of user input from the serial terminal program */
-extern volatile uint8_t g_terminal_request;
-
-/* End user code. Do not edit comment generated here */
-#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa_user.c
deleted file mode 100644
index 0f174d56cc..0000000000
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_scifa_user.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/***********************************************************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
-* applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-*
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-* File Name : r_cg_scifa_user.c
-* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
-* Device(s) : R7S910018CBG
-* Tool-Chain : GCCARM
-* Description : This file implements device driver for SCIF module.
-* Creation Date: 22/04/2015
-***********************************************************************************************************************/
-
-/***********************************************************************************************************************
-Pragma directive
-***********************************************************************************************************************/
-/* Start user code for pragma. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-Includes
-***********************************************************************************************************************/
-#include "r_cg_macrodriver.h"
-#include "r_cg_scifa.h"
-/* Start user code for include. Do not edit comment generated here */
-#include "r_typedefs.h"
-/* End user code. Do not edit comment generated here */
-#include "r_cg_userdefine.h"
-
-/***********************************************************************************************************************
-Global variables and functions
-***********************************************************************************************************************/
-extern const uint8_t * gp_scifa2_tx_address; /* SCIFA2 send buffer address */
-extern uint16_t g_scifa2_tx_count; /* SCIFA2 send data number */
-extern uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */
-extern uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */
-extern uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */
-/* Start user code for global. Do not edit comment generated here */
-
-/* Contains status of user input from the serial terminal program */
-volatile uint8_t g_terminal_request = 0;
-
-/* End user code. Do not edit comment generated here */
-
-/***********************************************************************************************************************
-* Function Name: r_scifa2_txif2_interrupt
-* Description : This function is TXIF2 interrupt service routine.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_txif2_interrupt(void)
-{
- uint16_t count = 0;
-
- /* Get the amount of untransmitted data stored in the FRDR register */
- uint16_t dummy_fdr = SCIFA2.FDR.BIT.T;
-
- /* Write data to the transmit FIFO data register */
- while ((g_scifa2_tx_count > 0U) && (count < _SCIF_FIFO_MAX_SIZE - dummy_fdr))
- {
- SCIFA2.FTDR = *gp_scifa2_tx_address;
- gp_scifa2_tx_address++;
- g_scifa2_tx_count--;
- count++;
- }
-
- if (SCIFA2.FSR.BIT.TDFE == 1U)
- {
- SCIFA2.FSR.BIT.TDFE = 0U;
- }
-
- if (g_scifa2_tx_count <= 0U)
- {
- SCIFA2.SCR.BIT.TIE = 0U;
- SCIFA2.SCR.BIT.TEIE = 1U;
- }
-
- /* Wait the interrupt signal is disabled */
- while (0U != (VIC.IRQS3.LONG & 0x00008000UL))
- {
- VIC.IEC3.LONG = 0x00008000UL;
- }
-
- VIC.IEN3.LONG |= 0x00008000UL;
-
- /* Dummy write */
- VIC.HVA0.LONG = 0x00000000UL;
-}
-/***********************************************************************************************************************
-* Function Name: r_scifa2_rxif2_interrupt
-* Description : This function is RXIF2 interrupt service routine.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_rxif2_interrupt(void)
-{
- uint16_t count = 0;
-
- /* Get the amount of receive data stored in FRDR register */
- uint16_t dummy_fdr = SCIFA2.FDR.BIT.R;
-
- /* Read data from the receive FIFO data register */
- while ((g_scifa2_rx_length > g_scifa2_rx_count) && (count < dummy_fdr))
- {
- *gp_scifa2_rx_address = SCIFA2.FRDR;
- gp_scifa2_rx_address++;
- g_scifa2_rx_count++;
- count++;
- }
-
- /* If remaining data is less than the receive trigger number, receive interrupt will not occur.
- In this case, set trigger number to 1 to force receive interrupt for each one byte of data in FRDR */
- if ((g_scifa2_rx_length - g_scifa2_rx_count < _SCIF_RX_TRIG_NUM_2) && (SCIFA2.FTCR.BIT.RFTC != 1U))
- {
- SCIFA2.FTCR.BIT.RFTC = 1U;
- }
-
- /* Clear receive FIFO data full flag */
- if (SCIFA2.FSR.BIT.RDF == 1U)
- {
- SCIFA2.FSR.BIT.RDF = 0U;
- }
-
- if (g_scifa2_rx_length <= g_scifa2_rx_count)
- {
- /* All data received */
- SCIFA2.SCR.BIT.RE = 0U;
- r_scifa2_callback_receiveend();
- }
-
- /* Wait the interrupt signal is disabled */
- while (0U != (VIC.IRQS3.LONG & 0x00004000UL))
- {
- VIC.IEC3.LONG = 0x00004000UL;
- }
-
- VIC.IEN3.LONG |= 0x00004000UL;
-
- /* Dummy write */
- VIC.HVA0.LONG = 0x00000000UL;
-}
-/***********************************************************************************************************************
-* Function Name: r_scifa2_drif2_interrupt
-* Description : This function is TEIF 2 or DRIF2 interrupt service routine.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_drif2_interrupt(void)
-{
- if (1U == SCIFA2.FSR.BIT.TEND)
- {
- SCIFA2.SPTR.BIT.SPB2DT = 0U;
- SCIFA2.SPTR.BIT.SPB2IO = 1U;
- SCIFA2.SCR.BIT.TE = 0U;
- SCIFA2.SCR.BIT.TEIE = 0U;
- }
- r_scifa2_callback_transmitend();
-
- /* Clear data ready detect flag */
- if (1U == SCIFA2.FSR.BIT.DR)
- {
- /* Start user code. Do not edit comment generated here */
- /* End user code. Do not edit comment generated here */
- SCIFA2.FSR.BIT.DR = 0U;
- }
-
- /* Wait the interrupt signal is disabled */
- while (0U != (VIC.IRQS3.LONG & 0x00010000UL))
- {
- VIC.IEC3.LONG = 0x00010000UL;
- }
-
- VIC.IEN3.LONG |= 0x00010000UL;
-
- /* Dummy write */
- VIC.HVA0.LONG = 0x00000000UL;
-}
-/***********************************************************************************************************************
-* Function Name: r_scifa2_brif2_interrupt
-* Description : This function is BRIF2 or ERIF2 interrupt service routine.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_brif2_interrupt(void)
-{
- if (1U == SCIFA2.FSR.BIT.BRK)
- {
- r_scifa2_callback_error(BREAK_DETECT);
- /* Clear break detect flag */
- SCIFA2.FSR.BIT.BRK = 0U;
- }
-
- if (1U == SCIFA2.FSR.BIT.ER)
- {
- r_scifa2_callback_error(RECEIVE_ERROR);
- /* Clear receive error flag */
- SCIFA2.FSR.BIT.ER = 0U;
- }
-
- if (1U == SCIFA2.LSR.BIT.ORER)
- {
- r_scifa2_callback_error(OVERRUN_ERROR);
- /* Clear overrun error flag */
- SCIFA2.LSR.BIT.ORER = 0U;
- }
-
- /* Wait the interrupt signal is disabled */
- while (0U != (VIC.IRQS3.LONG & 0x00002000UL))
- {
- VIC.IEC3.LONG = 0x00002000UL;
- }
-
- VIC.IEN3.LONG |= 0x00002000UL;
-
- /* Dummy write */
- VIC.HVA0.LONG = 0x00000000UL;
-}
-/***********************************************************************************************************************
-* Function Name: r_scifa2_callback_transmitend
-* Description : This function is a callback function when SCIFA2 finishes transmission.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_callback_transmitend(void)
-{
- /* Start user code. Do not edit comment generated here */
- /* End user code. Do not edit comment generated here */
-}
-/***********************************************************************************************************************
-* Function Name: r_scifa2_callback_receiveend
-* Description : This function is a callback function when SCIFA2 finishes reception.
-* Arguments : None
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_callback_receiveend(void)
-{
- /* Start user code. Do not edit comment generated here */
-
- /* Read the received data */
- uint8_t uart_in = SCIFA2.FRDR;
-
- /* Check if desired character is received */
- if (('c' != uart_in) || ('C' != uart_in))
- {
- /* Set global flag to indicate user requested ADC reading */
- g_terminal_request = 1U;
- }
-
- /* Re-enable receptions */
- SCIFA2.SCR.BIT.RE = 1U;
-
- /* End user code. Do not edit comment generated here */
-}
-/***********************************************************************************************************************
-* Function Name: r_scifa2_callback_error
-* Description : This function is a callback function when SCIFA2 reception encounters error.
-* Arguments : error_type -
-* reception error type
-* Return Value : None
-***********************************************************************************************************************/
-void r_scifa2_callback_error(scif_error_type_t error_type)
-{
- /* Start user code. Do not edit comment generated here */
-
- /* Used to suppress the warning message generated for unused variables */
- UNUSED_PARAM(error_type);
-
- /* End user code. Do not edit comment generated here */
-}
-
-/* Start user code for adding. Do not edit comment generated here */
-/* End user code. Do not edit comment generated here */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c
index 5e6bfe4d52..996abb8bb0 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c
@@ -40,10 +40,7 @@ Includes
#include "r_cg_icu.h"
#include "r_cg_port.h"
#include "r_cg_tpu.h"
-#include "r_cg_cmt.h"
-#include "r_cg_scifa.h"
#include "r_cg_rspi.h"
-#include "r_cg_s12ad.h"
#include "r_cg_mpc.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
@@ -82,11 +79,7 @@ void R_Systeminit(void)
R_ICU_Create();
R_PORT_Create();
R_TPU_Create();
- R_CMT4_Create();
- R_CMT5_Create();
- R_SCIFA2_Create();
R_RSPI1_Create();
- R_S12AD0_Create();
R_MPC_Create();
/* Disable writing to MPC pin function control registers */
diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c
index a90203650c..730e617a59 100644
--- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c
+++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c
@@ -96,22 +96,20 @@
/* Renesas includes. */
#include "r_cg_macrodriver.h"
#include "r_cg_icu.h"
-#include "r_cg_scifa.h"
#include "r_cg_rspi.h"
#include "r_system.h"
#include "r_reset.h"
-#include "siochar.h"
#include "r_cg_userdefine.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
- * The start up code does not include a routine to clear the BSS segment to 0
- * (as would be normal before calling main()), so the BSS is cleared manually
+ * The GCC start up code does not include a routine to clear the BSS segment to
+ * 0 (as would be normal before calling main()), so the BSS is cleared manually
* using the following function.
*/
static void prvClearBSS( void );
@@ -176,19 +174,6 @@ int main( void )
static void prvSetupHardware( void )
{
R_Systeminit();
-
- /* Enable RSPI1 (serial peripheral interface). */
- R_RSPI1_Start();
-
- /* Configure the UART channel for communication with a host PC via on-board
- RL78/G1C device. */
- io_init_scifa2();
-
- /* Enable SCIFA2 (serial communications interface with FIFO). */
- R_SCIFA2_Start();
-
- /* SW3 interrupts. */
- R_ICU_IRQ12_Start();
}
/*-----------------------------------------------------------*/
@@ -251,13 +236,17 @@ void vApplicationTickHook( void )
static void prvClearBSS( void )
{
-extern uint32_t __bss_start__[];
-extern uint32_t __bss_end__[];
-size_t xSize;
+#ifdef __GNUC__
+ /* The GCC start up files seem to be missing code to clear the BSS, so it
+ is done manually here. */
+ extern uint32_t __bss_start__[];
+ extern uint32_t __bss_end__[];
+ size_t xSize;
/* Zero out bss. */
xSize = ( ( size_t ) __bss_end__ ) - ( ( size_t ) __bss_start__ );
memset( ( void * ) __bss_start__, 0x00, xSize );
+#endif /* __GNUC__ */
}
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
new file mode 100644
index 0000000000..31d920b9ef
--- /dev/null
+++ b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -0,0 +1,358 @@
+/*
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ ***************************************************************************
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+ ***************************************************************************
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following
+ link: http://www.freertos.org/a00114.html
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that is more than just the market leader, it *
+ * is the industry's de facto standard. *
+ * *
+ * Help yourself get started quickly while simultaneously helping *
+ * to support the FreeRTOS project by purchasing a FreeRTOS *
+ * tutorial book, reference manual, or both: *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
+ the FAQ page "My application does not run, what could be wrong?". Have you
+ defined configASSERT()?
+
+ http://www.FreeRTOS.org/support - In return for receiving this top quality
+ embedded software for free we request you assist our global community by
+ participating in the support forum.
+
+ http://www.FreeRTOS.org/training - Investing in training allows your team to
+ be as productive as possible as early as possible. Now you can receive
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ Ltd, and the world's leading authority on the world's leading RTOS.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and commercial middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+ #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+ #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created. A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE ( 0x10 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case is messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing. This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting. This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts. As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Setup the initial stack of the task. The stack is set exactly as
+ expected by the portRESTORE_CONTEXT() macro.
+
+ The fist real value on the stack is the status register, which is set for
+ system mode, with interrupts enabled. A few NULLs are added first to ensure
+ GDB does not try decoding a non-existent return address. */
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) NULL;
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+ {
+ /* The task will start in THUMB mode. */
+ *pxTopOfStack |= portTHUMB_MODE_BIT;
+ }
+
+ pxTopOfStack--;
+
+ /* Next the return address, which in this case is the start of the task. */
+ *pxTopOfStack = ( StackType_t ) pxCode;
+ pxTopOfStack--;
+
+ /* Next all the registers other than the stack pointer. */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+
+ /* The task will start with a critical nesting count of 0 as interrupts are
+ enabled. */
+ *pxTopOfStack = portNO_CRITICAL_NESTING;
+ pxTopOfStack--;
+
+ /* The task will start without a floating point context. A task that uses
+ the floating point hardware must call vPortTaskUsesFPU() before executing
+ any floating point instructions. */
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
+
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( ulPortInterruptNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+ /* Only continue if the CPU is not in User mode. The CPU must be in a
+ Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+ ulAPSR &= portAPSR_MODE_BITS_MASK;
+ configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+ if( ulAPSR != portAPSR_USER_MODE )
+ {
+ /* Start the timer that generates the tick ISR. */
+ portDISABLE_INTERRUPTS();
+ configSETUP_TICK_INTERRUPT();
+
+ /* Start the first task executing. */
+ vPortRestoreTaskContext();
+ }
+
+ /* Will only get here if xTaskStartScheduler() was called with the CPU in
+ a non-privileged mode or the binary point register was not set to its lowest
+ possible value. prvTaskExitError() is referenced to prevent a compiler
+ warning about it being defined but not referenced in the case that the user
+ defines their own exit address. */
+ ( void ) prvTaskExitError;
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+
+ /* Now interrupts are disabled ulCriticalNesting can be accessed
+ directly. Increment ulCriticalNesting to keep a count of how many times
+ portENTER_CRITICAL() has been called. */
+ ulCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( ulCriticalNesting == 1 )
+ {
+ configASSERT( ulPortInterruptNesting == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+ {
+ /* Decrement the nesting count as the critical section is being
+ exited. */
+ ulCriticalNesting--;
+
+ /* If the nesting level has reached zero then all interrupt
+ priorities must be re-enabled. */
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+ {
+ /* Critical nesting has reached zero so all interrupt priorities
+ should be unmasked. */
+ portENABLE_INTERRUPTS();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+uint32_t ulInterruptStatus;
+
+ ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ ulPortYieldRequired = pdTRUE;
+ }
+
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+
+ configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+ /* A task is registering the fact that it needs an FPU context. Set the
+ FPU flag (which is saved as part of the task context). */
+ ulPortTaskHasFPUContext = pdTRUE;
+
+ /* Initialise the floating point status register. */
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
new file mode 100644
index 0000000000..af3739feb5
--- /dev/null
+++ b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -0,0 +1,274 @@
+/*
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
+ All rights reserved
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#include "FreeRTOSConfig.h"
+
+ SECTION .text:CODE:ROOT(2)
+ arm
+
+ /* Variables and functions. */
+ EXTERN pxCurrentTCB
+ EXTERN vTaskSwitchContext
+ EXTERN vApplicationIRQHandler
+ EXTERN ulPortInterruptNesting
+ EXTERN ulPortTaskHasFPUContext
+ EXTERN ulPortYieldRequired
+ EXTERN ulCriticalNesting
+
+ PUBLIC FreeRTOS_IRQ_Handler
+ PUBLIC FreeRTOS_SVC_Handler
+ PUBLIC vPortRestoreTaskContext
+
+SYS_MODE EQU 0x1f
+SVC_MODE EQU 0x13
+IRQ_MODE EQU 0x12
+
+portSAVE_CONTEXT MACRO
+
+ /* Save the LR and SPSR onto the system mode stack before switching to
+ system mode to save the remaining system mode registers. */
+ SRSDB sp!, #SYS_MODE
+ CPS #SYS_MODE
+ PUSH {R0-R12, R14}
+
+ /* Push the critical nesting count. */
+ LDR R2, =ulCriticalNesting
+ LDR R1, [R2]
+ PUSH {R1}
+
+ /* Does the task have a floating point context that needs saving? If
+ ulPortTaskHasFPUContext is 0 then no. */
+ LDR R2, =ulPortTaskHasFPUContext
+ LDR R3, [R2]
+ CMP R3, #0
+
+ /* Save the floating point context, if any. */
+ FMRXNE R1, FPSCR
+ VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+ VPUSHNE {D16-D31}
+#endif /* configFPU_D32 */
+ PUSHNE {R1}
+
+ /* Save ulPortTaskHasFPUContext itself. */
+ PUSH {R3}
+
+ /* Save the stack pointer in the TCB. */
+ LDR R0, =pxCurrentTCB
+ LDR R1, [R0]
+ STR SP, [R1]
+
+ ENDM
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT MACRO
+
+ /* Set the SP to point to the stack of the task being restored. */
+ LDR R0, =pxCurrentTCB
+ LDR R1, [R0]
+ LDR SP, [R1]
+
+ /* Is there a floating point context to restore? If the restored
+ ulPortTaskHasFPUContext is zero then no. */
+ LDR R0, =ulPortTaskHasFPUContext
+ POP {R1}
+ STR R1, [R0]
+ CMP R1, #0
+
+ /* Restore the floating point context, if any. */
+ POPNE {R0}
+#if configFPU_D32 == 1
+ VPOPNE {D16-D31}
+#endif /* configFPU_D32 */
+ VPOPNE {D0-D15}
+ VMSRNE FPSCR, R0
+
+ /* Restore the critical section nesting depth. */
+ LDR R0, =ulCriticalNesting
+ POP {R1}
+ STR R1, [R0]
+
+ /* Restore all system mode registers other than the SP (which is already
+ being used). */
+ POP {R0-R12, R14}
+
+ /* Return to the task code, loading CPSR on the way. */
+ RFEIA sp!
+
+ ENDM
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to yield.
+ *****************************************************************************/
+FreeRTOS_SVC_Handler:
+ /* Save the context of the current task and select a new task to run. */
+ portSAVE_CONTEXT
+ LDR R0, =vTaskSwitchContext
+ BLX R0
+ portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+vPortRestoreTaskContext:
+ /* Switch to system mode. */
+ CPS #SYS_MODE
+ portRESTORE_CONTEXT
+
+FreeRTOS_IRQ_Handler:
+ /* Return to the interrupted instruction. */
+ SUB lr, lr, #4
+
+ /* Push the return address and SPSR. */
+ PUSH {lr}
+ MRS lr, SPSR
+ PUSH {lr}
+
+ /* Change to supervisor mode to allow reentry. */
+ CPS #SVC_MODE
+
+ /* Push used registers. */
+ PUSH {r0-r3, r12}
+
+ /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
+ for future use. r1 holds the original ulPortInterruptNesting value for
+ future use. */
+ LDR r3, =ulPortInterruptNesting
+ LDR r1, [r3]
+ ADD r0, r1, #1
+ STR r0, [r3]
+
+ /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
+ future use. */
+ MOV r0, sp
+ AND r2, r0, #4
+ SUB sp, sp, r2
+
+ /* Call the interrupt handler. */
+ PUSH {r0-r3, lr}
+ LDR r1, =vApplicationIRQHandler
+ BLX r1
+ POP {r0-r3, lr}
+ ADD sp, sp, r2
+
+ CPSID i
+ DSB
+ ISB
+
+ /* Write to the EOI register. */
+ LDR r2, =configEOI_ADDRESS
+ STR r0, [r2]
+
+ /* Restore the old nesting count. */
+ STR r1, [r3]
+
+ /* A context switch is never performed if the nesting count is not 0. */
+ CMP r1, #0
+ BNE exit_without_switch
+
+ /* Did the interrupt request a context switch? r1 holds the address of
+ ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+ use. */
+ LDR r1, =ulPortYieldRequired
+ LDR r0, [r1]
+ CMP r0, #0
+ BNE switch_before_exit
+
+exit_without_switch:
+ /* No context switch. Restore used registers, LR_irq and SPSR before
+ returning. */
+ POP {r0-r3, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ MOVS PC, LR
+
+switch_before_exit:
+ /* A context swtich is to be performed. Clear the context switch pending
+ flag. */
+ MOV r0, #0
+ STR r0, [r1]
+
+ /* Restore used registers, LR-irq and SPSR before saving the context
+ to the task stack. */
+ POP {r0-r3, r12}
+ CPS #IRQ_MODE
+ POP {LR}
+ MSR SPSR_cxsf, LR
+ POP {LR}
+ portSAVE_CONTEXT
+
+ /* Call the function that selects the new task to execute.
+ vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+ instructions, or 8 byte aligned stack allocated data. LR does not need
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+ LDR R0, =vTaskSwitchContext
+ BLX R0
+
+ /* Restore the context of, and branch to, the task selected to execute
+ next. */
+ portRESTORE_CONTEXT
+
+ END
+
+
+
+
+
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
new file mode 100644
index 0000000000..e33040cb40
--- /dev/null
+++ b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -0,0 +1,223 @@
+/*
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ ***************************************************************************
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+ ***************************************************************************
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following
+ link: http://www.freertos.org/a00114.html
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that is more than just the market leader, it *
+ * is the industry's de facto standard. *
+ * *
+ * Help yourself get started quickly while simultaneously helping *
+ * to support the FreeRTOS project by purchasing a FreeRTOS *
+ * tutorial book, reference manual, or both: *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
+ the FAQ page "My application does not run, what could be wrong?". Have you
+ defined configASSERT()?
+
+ http://www.FreeRTOS.org/support - In return for receiving this top quality
+ embedded software for free we request you assist our global community by
+ participating in the support forum.
+
+ http://www.FreeRTOS.org/training - Investing in training allows your team to
+ be as productive as possible as early as possible. Now you can receive
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ Ltd, and the world's leading authority on the world's leading RTOS.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and commercial middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{ \
+extern volatile uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0 \n" \
+ "ISB " );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* The I bit within the CPSR. */
+#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
+
+/* In the absence of a priority mask register, these functions and macros
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" );
+#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
+ "DSB \n" \
+ "ISB " );
+#pragma inline
+static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
+
+ __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
+ ulCPSR &= portINTERRUPT_ENABLE_BIT;
+ portDISABLE_INTERRUPTS();
+ return ulCPSR;
+}
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) if( x == 0 ) portENABLE_INTERRUPTS()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE inline
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+ } /* extern C */
+#endif
+
+
+#endif /* PORTMACRO_H */
+