github-forks
/
FreeRTOS
mirror of https://github.com/FreeRTOS/FreeRTOS.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Final V8.2.1 release ready for tagging:

Browse Source 
+ Added MSP432 (ARM Cortex-M4F MSP430!) demos for IAR, Keil and CCS.
+ Renamed directory containing demo for STM32F7 ARM Cortex-M7.
+ Renamed directory containing demo for SAMV71 ARM Cortex-M7.
+ Introduced xTaskNotifyAndQuery().
pull/1/head
Richard Barry 10 years ago
parent 693d0520bc
commit 8dadb6b87c
647 changed files with 67785 additions and 977 deletions
Show Stats Download Patch File Download Diff File

16
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.ccsproject
Unescape Escape View File

@ -0,0 +1,16 @@
<?xml version="1.0" encoding="UTF-8" ?>
<?ccsproject version="1.0"?>
<projectOptions>
<deviceVariant value="MSP432P401R"/>
<deviceFamily value="MSP432"/>
<deviceEndianness value="little"/>
<codegenToolVersion value="5.2.1"/>
<isElfFormat value="true"/>
<connection value="common/targetdb/connections/TIXDSET_Connection.xml"/>
<linkerCommandFile value="msp432p401r.cmd"/>
<rts value="libc.a"/>
<createSlaveProjects value=""/>
<ignoreDefaultDeviceSettings value="true"/>
<templateProperties value="id=OutOfBox_MSP432P401R.projectspec.OutOfBox_MSP432P401R,"/>
<isTargetManual value="true"/>
</projectOptions>

281
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.cproject
Unescape Escape View File

@ -0,0 +1,281 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<macros>
<stringMacro name="MSPWAREDLIB_ROOT" type="VALUE_PATH_DIR" value="C:/DevTools/ti/msp430/MSP430ware_1_97_00_47/examples/boards/MSP-EXP432P401R/MSP-EXP432P401R_Software_Examples/Source/OutOfBox_MSP432P401R/driverlib/MSP432P4xx/"/>
</macros>
<externalSettings/>
<extensions>
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949" name="Debug" parent="com.ti.ccstudio.buildDefinitions.MSP432.Debug" postbuildStep="${CCS_INSTALL_ROOT}/utils/tiobj2bin/tiobj2bin ${BuildArtifactFileName} ${BuildArtifactFileBaseName}.bin ${CG_TOOL_ROOT}/bin/armofd ${CG_TOOL_ROOT}/bin/armhex ${CCS_INSTALL_ROOT}/utils/tiobj2bin/mkhex4bin">
<folderInfo id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949." name="/" resourcePath="">
<toolChain id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain.873758150" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.1120233935">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=MSP432P401R"/>
<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=${PROJECT_LOC}/system/CCS/msp432p401r.cmd"/>
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
<listOptionValue builtIn="false" value="IPE_OPTION__LINKER=enabled:false;"/>
<listOptionValue builtIn="false" value="MPU_OPTION__LINKER=enabled:false;"/>
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="5.2.1" valueType="string"/>
<targetPlatform id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug.1028892013" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug"/>
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.builderDebug.420420724" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.builderDebug"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.543582640" name="MSP432 Compiler" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug">
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.SILICON_VERSION.2125641220" name="Target processor version (--silicon_version, -mv)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.SILICON_VERSION.7M4" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.CODE_STATE.833035292" name="Designate code state, 16-bit (thumb) or 32-bit (--code_state)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.CODE_STATE" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.CODE_STATE.16" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.FLOAT_SUPPORT.1565405291" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.FLOAT_SUPPORT.FPv4SPD16" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ABI.2140574058" name="Application binary interface. [See 'General' page to edit] (--abi)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ABI.eabi" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.LITTLE_ENDIAN.326781622" name="Little endian code [See 'General' page to edit] (--little_endian, -me)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.LITTLE_ENDIAN" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.INCLUDE_PATH.739915483" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.INCLUDE_PATH" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Full_Demo}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/driverlib/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/driverlib}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Full_Demo/FreeRTOS+CLI}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Full_Demo/Standard_Demo_Tasks/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/CCS/ARM_CM4F}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include/&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include/&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include/CMSIS&quot;"/>
<listOptionValue builtIn="false" value="&quot;${PROJECT_LOC}&quot;"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEBUGGING_MODEL.1429880470" name="Debugging model" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEBUGGING_MODEL" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEBUGGING_MODEL.SYMDEBUG__DWARF" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GCC.1743293558" name="Enable support for GCC extensions (DEPRECATED) (--gcc)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GCC" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEFINE.2103863989" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEFINE" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__MSP432P401R__"/>
<listOptionValue builtIn="false" value="USE_CMSIS_REGISTER_FORMAT=1"/>
<listOptionValue builtIn="false" value="TARGET_IS_MSP432P4XX"/>
<listOptionValue builtIn="false" value="ccs"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DISPLAY_ERROR_NUMBER.1609819674" name="Emit diagnostic identifier numbers (--display_error_number, -pden)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.VERBOSE_DIAGNOSTICS.1905198830" name="Verbose diagnostics (--verbose_diagnostics, -pdv)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.VERBOSE_DIAGNOSTICS" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WARNING.321098290" name="Treat diagnostic &lt;id&gt; as warning (--diag_warning, -pdsw)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WARNING" valueType="stringList">
<listOptionValue builtIn="false" value="225"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WRAP.2105562167" name="Wrap diagnostic messages (--diag_wrap)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WRAP" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WRAP.off" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GEN_FUNC_SUBSECTIONS.1581338624" name="Place each function in a separate subsection (--gen_func_subsections, -ms)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GEN_FUNC_SUBSECTIONS" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GEN_FUNC_SUBSECTIONS.on" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.OPT_LEVEL.669442165" name="Optimization level (--opt_level, -O)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.OPT_LEVEL" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.OPT_LEVEL.0" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.OPT_FOR_SPEED.1297898020" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.OPT_FOR_SPEED" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.OPT_FOR_SPEED.2" valueType="enumerated"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS.1410406594" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS.1014794987" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS.372586409" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS.414766637" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.1120233935" name="MSP432 Linker" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug">
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.OUTPUT_FILE.1945573560" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.OUTPUT_FILE" value="&quot;${ProjName}.out&quot;" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.MAP_FILE.1579574329" name="Link information (map) listed into &lt;file&gt; (--map_file, -m)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.MAP_FILE" value="&quot;${ProjName}.map&quot;" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.HEAP_SIZE.437630900" name="Heap size for C/C++ dynamic memory allocation (--heap_size, -heap)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.HEAP_SIZE" value="0" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.STACK_SIZE.255814986" name="Set C system stack size (--stack_size, -stack)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.STACK_SIZE" value="800" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.SEARCH_PATH.1685135597" name="Add &lt;dir&gt; to library search path (--search_path, -i)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.SEARCH_PATH" valueType="libPaths">
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/lib&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DISPLAY_ERROR_NUMBER.506754327" name="Emit diagnostic identifier numbers (--display_error_number)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DIAG_WRAP.932112538" name="Wrap diagnostic messages (--diag_wrap)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DIAG_WRAP" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DIAG_WRAP.off" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.XML_LINK_INFO.1932147518" name="Detailed link information data-base into &lt;file&gt; (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.XML_LINK_INFO" value="&quot;${ProjName}_linkInfo.xml&quot;" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.UNUSED_SECTION_ELIMINATION.123927567" name="Eliminate sections not needed in the executable (--unused_section_elimination)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.UNUSED_SECTION_ELIMINATION" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.UNUSED_SECTION_ELIMINATION.on" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.LIBRARY.1217884460" name="Include library file or command file as input (--library, -l)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.LIBRARY" valueType="libs">
<listOptionValue builtIn="false" value="&quot;libc.a&quot;"/>
</option>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD_SRCS.1256625757" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD2_SRCS.270345680" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD2_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__GEN_CMDS.467703825" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__GEN_CMDS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.747780422" name="MSP432 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex"/>
</toolChain>
</folderInfo>
<folderInfo id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949.Full_Demo/Standard_Demo_Tasks" name="Standard_Demo_Tasks" resourcePath="Full_Demo/Standard_Demo_Tasks">
<toolChain id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain.1230122581" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain" unusedChildren="">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866.131953646" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866"/>
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543.2107049230" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543"/>
<targetPlatform id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.1121232029" name="MSP432 Compiler" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.543582640">
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS.1829590545" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS.387599185" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS.2018384940" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS.294521512" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.270666708" name="MSP432 Linker" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.1120233935"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.1819517380" name="MSP432 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.747780422"/>
</toolChain>
</folderInfo>
<fileInfo id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949.Full_Demo/Standard_Demo_Tasks/IntQueue.c" name="IntQueue.c" rcbsApplicability="disable" resourcePath="Full_Demo/Standard_Demo_Tasks/IntQueue.c" toolsToInvoke="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.1121232029.492052490">
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.1121232029.492052490" name="MSP432 Compiler" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.1121232029">
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS.1370894378" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS.616861649" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS.1718924114" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS.563565100" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS"/>
</tool>
<tool command="" customBuildStep="true" id="org.eclipse.cdt.managedbuilder.ui.rcbs.441405388.1968322013.2014428990.1810678580" name="Resource Custom Build Step">
<inputType id="org.eclipse.cdt.managedbuilder.ui.rcbs.inputtype.1758765119.2002969237.1509378367.1617018210" name="Resource Custom Build Step Input Type">
<additionalInput kind="additionalinputdependency" paths=""/>
</inputType>
<outputType id="org.eclipse.cdt.managedbuilder.ui.rcbs.outputtype.692569172.227479984.609265658.151605149" name="Resource Custom Build Step Output Type"/>
</tool>
</fileInfo>
<folderInfo id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949.FreeRTOS_Source/portable/MemMang" name="MemMang" resourcePath="FreeRTOS_Source/portable/MemMang">
<toolChain id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain.1803319416" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain" unusedChildren="">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866.632013318" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866"/>
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543.1550367287" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543"/>
<targetPlatform id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.817376883" name="MSP432 Compiler" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.543582640">
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS.2036275470" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS.162754164" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS.1858335515" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS.2052670262" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.963840608" name="MSP432 Linker" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.1120233935"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.615420402" name="MSP432 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.747780422"/>
</toolChain>
</folderInfo>
<folderInfo id="com.ti.ccstudio.buildDefinitions.MSP432.Debug.2017455949.1670949115" name="/" resourcePath="driverlib">
<toolChain id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain.1901733313" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.DebugToolchain" unusedChildren="">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866.2103882879" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1343457866"/>
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543.1468647356" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.987376543"/>
<targetPlatform id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformDebug"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.1319430196" name="MSP432 Compiler" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerDebug.543582640">
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS.115645865" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS.1576469086" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS.938225596" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS.1447823910" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.26930881" name="MSP432 Linker" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerDebug.1120233935"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.1397748977" name="MSP432 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.747780422"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="${PROJECT_LOC}/system/CCS/msp432p401r_.cmd|${PROJECT_LOC}/SystemFiles_CCS/msp432p401r.cmd|msp432p401r.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.ti.ccstudio.buildDefinitions.MSP432.Release.1967108398">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.MSP432.Release.1967108398" moduleId="org.eclipse.cdt.core.settings" name="Release">
<macros>
<stringMacro name="MSPWAREDLIB_ROOT" type="VALUE_PATH_DIR" value="C:/DevTools/ti/msp430/MSP430ware_1_97_00_47/examples/boards/MSP-EXP432P401R/MSP-EXP432P401R_Software_Examples/Source/OutOfBox_MSP432P401R/driverlib/MSP432P4xx/"/>
</macros>
<externalSettings/>
<extensions>
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.MSP432.Release.1967108398" name="Release" parent="com.ti.ccstudio.buildDefinitions.MSP432.Release" postbuildStep="${CCS_INSTALL_ROOT}/utils/tiobj2bin/tiobj2bin ${BuildArtifactFileName} ${BuildArtifactFileBaseName}.bin ${CG_TOOL_ROOT}/bin/armofd ${CG_TOOL_ROOT}/bin/armhex ${CCS_INSTALL_ROOT}/utils/tiobj2bin/mkhex4bin">
<folderInfo id="com.ti.ccstudio.buildDefinitions.MSP432.Release.1967108398." name="/" resourcePath="">
<toolChain id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.ReleaseToolchain.708372784" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerRelease.1687622278">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.600155832" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=MSP432P401R"/>
<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=msp432p401r.cmd"/>
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.2000879366" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="5.2.1" valueType="string"/>
<targetPlatform id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformRelease.62448574" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.targetPlatformRelease"/>
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.builderRelease.965397405" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.builderRelease"/>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerRelease.762577774" name="MSP432 Compiler" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.compilerRelease">
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ADVICE__POWER.1149856586" name="Enable checking of ULP power rules (--advice:power)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ADVICE__POWER" value="all" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WARNING.1838064507" name="Treat diagnostic &lt;id&gt; as warning (--diag_warning, -pdsw)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WARNING" valueType="stringList">
<listOptionValue builtIn="false" value="225"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DISPLAY_ERROR_NUMBER.4837049" name="Emit diagnostic identifier numbers (--display_error_number, -pden)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WRAP.1892946282" name="Wrap diagnostic messages (--diag_wrap)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WRAP" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DIAG_WRAP.off" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.INCLUDE_PATH.1933328024" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.INCLUDE_PATH" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include/&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include/CMSIS&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include/&quot;"/>
<listOptionValue builtIn="false" value="&quot;${PROJECT_LOC}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${MSPWAREDLIB_ROOT}&quot;"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.LITTLE_ENDIAN.1607017771" name="Little endian code [See 'General' page to edit] (--little_endian, -me)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.LITTLE_ENDIAN" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ABI.1448464359" name="Application binary interface. [See 'General' page to edit] (--abi)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.ABI.eabi" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.SILICON_VERSION.554486312" name="Target processor version (--silicon_version, -mv)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.SILICON_VERSION.7M4" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.CODE_STATE.457151009" name="Designate code state, 16-bit (thumb) or 32-bit (--code_state)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.CODE_STATE" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.CODE_STATE.16" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.FLOAT_SUPPORT.2038208834" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.FLOAT_SUPPORT.FPv4SPD16" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEFINE.853293680" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.DEFINE" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__MSP432P401R__"/>
<listOptionValue builtIn="false" value="TARGET_IS_MSP432P4XX"/>
<listOptionValue builtIn="false" value="ccs"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GCC.1510599997" name="Enable support for GCC extensions (DEPRECATED) (--gcc)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compilerID.GCC" value="true" valueType="boolean"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS.192683832" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__C_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS.479292307" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__CPP_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS.1212351145" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS.1619491956" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.compiler.inputType__ASM2_SRCS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerRelease.1687622278" name="MSP432 Linker" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exe.linkerRelease">
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.OUTPUT_FILE.605704385" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.OUTPUT_FILE" value="&quot;${ProjName}.out&quot;" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.MAP_FILE.1722371624" name="Link information (map) listed into &lt;file&gt; (--map_file, -m)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.MAP_FILE" value="&quot;${ProjName}.map&quot;" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.XML_LINK_INFO.1912095406" name="Detailed link information data-base into &lt;file&gt; (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.XML_LINK_INFO" value="&quot;${ProjName}_linkInfo.xml&quot;" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DISPLAY_ERROR_NUMBER.943630485" name="Emit diagnostic identifier numbers (--display_error_number)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DIAG_WRAP.790930247" name="Wrap diagnostic messages (--diag_wrap)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DIAG_WRAP" value="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.DIAG_WRAP.off" valueType="enumerated"/>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.SEARCH_PATH.1840293143" name="Add &lt;dir&gt; to library search path (--search_path, -i)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.SEARCH_PATH" valueType="libPaths">
<listOptionValue builtIn="false" value="&quot;${CCS_BASE_ROOT}/arm/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/lib&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.LIBRARY.882949261" name="Include library file or command file as input (--library, -l)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.LIBRARY" valueType="libs">
<listOptionValue builtIn="false" value="&quot;libc.a&quot;"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.STACK_SIZE.338236956" name="Set C system stack size (--stack_size, -stack)" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.linkerID.STACK_SIZE" value="512" valueType="string"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD_SRCS.114303850" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD2_SRCS.400761265" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__CMD2_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__GEN_CMDS.1279453728" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.exeLinker.inputType__GEN_CMDS"/>
</tool>
<tool id="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex.632002771" name="MSP432 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.MSP432_5.2.hex"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="${PROJECT_LOC}/system/CCS/msp432p401r.cmd|${PROJECT_LOC}/system/CCS/msp432p401r_.cmd|${PROJECT_LOC}/SystemFiles_CCS/msp432p401r.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="OutOfBox_MSP432P401R.com.ti.ccstudio.buildDefinitions.MSP432.ProjectType.1600140624" name="MSP432" projectType="com.ti.ccstudio.buildDefinitions.MSP432.ProjectType"/>
</storageModule>
<storageModule moduleId="scannerConfiguration"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
<project-mappings>
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
</project-mappings>
</storageModule>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Release">
<resource resourceType="PROJECT" workspacePath="/RTOSDemo"/>
</configuration>
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/RTOSDemo"/>
</configuration>
</storageModule>
</cproject>

341
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
Unescape Escape View File

@ -0,0 +1,341 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.ti.ccstudio.core.ccsNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>FreeRTOS_Source</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source</locationURI>
</link>
<link>
<name>Full_Demo/FreeRTOS+CLI</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI</locationURI>
</link>
<link>
<name>Full_Demo/Sample-CLI-commands.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c</locationURI>
</link>
<link>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal</locationURI>
</link>
<link>
<name>Full_Demo/UARTCommandConsole.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c</locationURI>
</link>
<link>
<name>Full_Demo/Standard_Demo_Tasks/include</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>
</link>
</linkedResources>
<filteredResources>
<filter>
<id>1427193581265</id>
<name></name>
<type>10</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-settings</arguments>
</matcher>
</filter>
<filter>
<id>1427193581275</id>
<name></name>
<type>10</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-IAR_*</arguments>
</matcher>
</filter>
<filter>
<id>1427193581275</id>
<name></name>
<type>10</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-Keil_*</arguments>
</matcher>
</filter>
<filter>
<id>1424106057421</id>
<name>Full_Demo</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RegTest.s</arguments>
</matcher>
</filter>
<filter>
<id>1424106057432</id>
<name>Full_Demo</name>
<type>6</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RegTest.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780710</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-cpu.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780715</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-true-false-cs.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780721</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-gpio.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780726</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-interrupt.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780730</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-pcm.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780734</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-uart.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780739</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-wdt_a.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780744</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-fpu.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443780748</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-timer32.c</arguments>
</matcher>
</filter>
<filter>
<id>1423578948112</id>
<name>system</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-CCS</arguments>
</matcher>
</filter>
<filter>
<id>1422884503134</id>
<name>FreeRTOS_Source/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-MemMang</arguments>
</matcher>
</filter>
<filter>
<id>1422884503144</id>
<name>FreeRTOS_Source/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-CCS</arguments>
</matcher>
</filter>
<filter>
<id>1424443942773</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-sp_flop.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942777</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-semtest.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942782</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-true-false-countsem.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942787</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-GenQTest.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942791</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-recmutex.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942796</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-serial.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942801</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-TimerDemo.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942806</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-IntQueue.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942810</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-EventGroupsDemo.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942817</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-TaskNotify.c</arguments>
</matcher>
</filter>
<filter>
<id>1424443942823</id>
<name>Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-IntSemTest.c</arguments>
</matcher>
</filter>
<filter>
<id>1422884525067</id>
<name>FreeRTOS_Source/portable/CCS</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-ARM_CM4F</arguments>
</matcher>
</filter>
<filter>
<id>1422884633479</id>
<name>FreeRTOS_Source/portable/MemMang</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-heap_4.c</arguments>
</matcher>
</filter>
</filteredResources>
<variableList>
<variable>
<name>FREERTOS_ROOT</name>
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
</variable>
<variable>
<name>MSPWAREDLIB_ROOT</name>
<value>file:/C:/DevTools/ti/msp430/MSP430ware_1_97_00_47/examples/boards/MSP-EXP432P401R/MSP-EXP432P401R_Software_Examples/Source/OutOfBox_MSP432P401R/driverlib/MSP432P4xx</value>
</variable>
</variableList>
</projectDescription>

3
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.codan.core.prefs
Unescape Escape View File

@ -0,0 +1,3 @@
eclipse.preferences.version=1
inEditor=false
onBuild=false

2
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.cdt.debug.core.prefs
Unescape Escape View File

@ -0,0 +1,2 @@
eclipse.preferences.version=1
org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker

28
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.settings/org.eclipse.core.resources.prefs
Unescape Escape View File

@ -0,0 +1,28 @@
eclipse.preferences.version=1
encoding//Debug/FreeRTOS_Source/portable/CCS/ARM_CM4F/subdir_rules.mk=UTF-8
encoding//Debug/FreeRTOS_Source/portable/CCS/ARM_CM4F/subdir_vars.mk=UTF-8
encoding//Debug/FreeRTOS_Source/portable/MemMang/subdir_rules.mk=UTF-8
encoding//Debug/FreeRTOS_Source/portable/MemMang/subdir_vars.mk=UTF-8
encoding//Debug/FreeRTOS_Source/subdir_rules.mk=UTF-8
encoding//Debug/FreeRTOS_Source/subdir_vars.mk=UTF-8
encoding//Debug/Full_Demo/FreeRTOS+CLI/subdir_rules.mk=UTF-8
encoding//Debug/Full_Demo/FreeRTOS+CLI/subdir_vars.mk=UTF-8
encoding//Debug/Full_Demo/Standard_Demo_Tasks/subdir_rules.mk=UTF-8
encoding//Debug/Full_Demo/Standard_Demo_Tasks/subdir_vars.mk=UTF-8
encoding//Debug/Full_Demo/subdir_rules.mk=UTF-8
encoding//Debug/Full_Demo/subdir_vars.mk=UTF-8
encoding//Debug/Objects/subdir_rules.mk=UTF-8
encoding//Debug/Objects/subdir_vars.mk=UTF-8
encoding//Debug/SimplyBlinkyDemo/subdir_rules.mk=UTF-8
encoding//Debug/SimplyBlinkyDemo/subdir_vars.mk=UTF-8
encoding//Debug/SystemFiles_CCS/subdir_rules.mk=UTF-8
encoding//Debug/SystemFiles_CCS/subdir_vars.mk=UTF-8
encoding//Debug/driverlib/subdir_rules.mk=UTF-8
encoding//Debug/driverlib/subdir_vars.mk=UTF-8
encoding//Debug/makefile=UTF-8
encoding//Debug/objects.mk=UTF-8
encoding//Debug/sources.mk=UTF-8
encoding//Debug/subdir_rules.mk=UTF-8
encoding//Debug/subdir_vars.mk=UTF-8
encoding//Debug/system/CCS/subdir_rules.mk=UTF-8
encoding//Debug/system/CCS/subdir_vars.mk=UTF-8

227
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
Unescape Escape View File

@ -0,0 +1,227 @@
/*
FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
***NOTE*** The exception to the GPL is included to allow you to distribute
a combined work that includes FreeRTOS without being obliged to provide the
source code for proprietary components outside of the FreeRTOS kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/******************************************************************************
See http://www.freertos.org/a00110.html for an explanation of the
definitions contained in this file.
******************************************************************************/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application.
The comprehensive demo uses FreeRTOS+CLI to create a simple command line
interface through a UART.
The blinky demo uses FreeRTOS's tickless idle mode to reduce power consumption.
See the notes on the web page below regarding the difference in power saving
that can be achieved between using the generic tickless implementation (as used
by the blinky demo) and a tickless implementation that is tailored specifically
to the MSP432.
See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions. */
#define configCREATE_SIMPLE_TICKLESS_DEMO 0
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
* http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
/* Constants related to the behaviour or the scheduler. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_PREEMPTION 1
#define configUSE_TIME_SLICING 1
#define configMAX_PRIORITIES ( 5 )
#define configIDLE_SHOULD_YIELD 1
#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */
/* Constants that describe the hardware and memory usage. */
#define configCPU_CLOCK_HZ MAP_CS_getMCLK()
#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 100 )
#define configMAX_TASK_NAME_LEN ( 12 )
/* Note heap_5.c is used so this only defines the part of the heap that is in
the first block of RAM on the LPC device. See the initialisation of the heap
in main.c. */
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )
/* Constants that build features in or out. */
#define configUSE_MUTEXES 1
#define configUSE_TICKLESS_IDLE 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_NEWLIB_REENTRANT 0
#define configUSE_CO_ROUTINES 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_QUEUE_SETS 0
#define configUSE_TASK_NOTIFICATIONS 1
/* Constants that define which hook (callback) functions should be used. */
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configUSE_MALLOC_FAILED_HOOK 1
/* Constants provided for debugging and optimisation assistance. */
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define configQUEUE_REGISTRY_SIZE 0
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 3 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is only
necessary if the linker does not automatically remove functions that are not
referenced anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xSemaphoreGetMutexHolder 0
#define INCLUDE_xTimerPendFunctionCall 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command
interpreter. See the FreeRTOS+CLI documentation for more information:
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048
/* Cortex-M3/4 interrupt priority configuration follows...................... */
/* Use the system definition, if there is one. */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 8 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names - can't be used with CCS due to limitations in the assemblers
pre-processing. */
#ifndef __TI_COMPILER_VERSION__
#define xPortPendSVHandler PendSV_Handler
#define vPortSVCHandler SVC_Handler
#define xPortSysTickHandler SysTick_Handler
#endif
/* The trace facility is turned on to make some functions available for use in
CLI commands. */
#define configUSE_TRACE_FACILITY 1
/* Some board specifics. The LED is on P1.0, configure the pin as output. */
#define configTOGGLE_LED() GPIO_toggleOutputOnPin( GPIO_PORT_P1, GPIO_PIN0 )
/* The #ifdef guards against the file being included from IAR assembly files. */
#ifndef __IASMARM__
/* TI driver library includes. */
#include <driverlib.h>
void vPreSleepProcessing( uint32_t ulExpectedIdleTime );
#define configPRE_SLEEP_PROCESSING( x ) vPreSleepProcessing( x )
#if configCREATE_SIMPLE_TICKLESS_DEMO == 1
/* Constants related to the generation of run time stats. Run time stats
are gathered in the full demo, not the blinky demo. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE() 0
/* The blinky demo can use a slow tick rate to save power. */
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
#else
/* Constants related to the generation of run time stats. Run time stats
are gathered in the full demo, not the blinky demo. */
void vConfigureTimerForRunTimeStats( void );
uint32_t ulGetRunTimeCounterValue( void );
#define configGENERATE_RUN_TIME_STATS 1
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
/* Some of the tests in the full demo expecte a 1ms tick rate. */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#endif /* configCREATE_SIMPLE_TICKLESS_DEMO */
#endif /* __IASMARM__ */
#endif /* FREERTOS_CONFIG_H */

135
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
Unescape Escape View File

@ -0,0 +1,135 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
* This file initialises the two timers available in the Timer32 peripheral.
*
* Channels 0 and 1 provide the interrupts that are used with the IntQ
* standard demo tasks, which test interrupt nesting and using queues from
* interrupts.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo includes. */
#include "IntQueueTimer.h"
#include "IntQueue.h"
/* The frequencies at which the two timers expire are slightly offset to ensure
they don't remain synchronised. */
#define tmrTIMER_0_FREQUENCY ( 2000UL )
#define tmrTIMER_1_FREQUENCY ( 2003UL )
/* The interrupts use the FreeRTOS API so must be at or below the max syscall
interrupt priority. Counter-intuitively, the higher the numeric number the
lower the logical priority. http://www.freertos.org/RTOS-Cortex-M3-M4.html */
#define tmrLOWER_PRIORITY ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
#define tmrHIGHER_PRIORITY ( configMAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
/*-----------------------------------------------------------*/
/* Handlers for the two timer peripherals - two channels are used in the TC0
timer. */
void vT32_0_Handler( void );
void vT32_1_Handler( void );
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
{
/* Configure the timer channels. */
MAP_Timer32_initModule( TIMER32_0_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( TIMER32_0_MODULE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
MAP_Timer32_enableInterrupt( TIMER32_0_MODULE );
MAP_Timer32_startTimer( TIMER32_0_MODULE, false );
MAP_Interrupt_setPriority( INT_T32_INT1, tmrLOWER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT1 );
MAP_Timer32_initModule( TIMER32_1_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( TIMER32_1_MODULE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
MAP_Timer32_enableInterrupt( TIMER32_1_MODULE );
MAP_Timer32_startTimer( TIMER32_1_MODULE, false );
MAP_Interrupt_setPriority( INT_T32_INT2, tmrHIGHER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT2 );
}
/*-----------------------------------------------------------*/
void vT32_0_Handler( void )
{
MAP_Timer32_clearInterruptFlag( TIMER32_0_MODULE );
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
/*-----------------------------------------------------------*/
void vT32_1_Handler( void )
{
MAP_Timer32_clearInterruptFlag( TIMER32_1_MODULE );
portYIELD_FROM_ISR( xSecondTimerHandler() );
}

0
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/Full_Demo/IntQueueTimer.h → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.h
Unescape Escape View File

454
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.asm
Unescape Escape View File

@ -0,0 +1,454 @@
;/*
; FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
; All rights reserved
;
; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
;
; ***************************************************************************
; >>! NOTE: The modification to the GPL is included to allow you to !<<
; >>! distribute a combined work that includes FreeRTOS without being !<<
; >>! obliged to provide the source code for proprietary components !<<
; >>! outside of the FreeRTOS kernel. !<<
; ***************************************************************************
;
; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
; FOR A PARTICULAR PURPOSE. Full license text is available on the following
; link: http://www.freertos.org/a00114.html
;
; ***************************************************************************
; * *
; * FreeRTOS provides completely free yet professionally developed, *
; * robust, strictly quality controlled, supported, and cross *
; * platform software that is more than just the market leader, it *
; * is the industry's de facto standard. *
; * *
; * Help yourself get started quickly while simultaneously helping *
; * to support the FreeRTOS project by purchasing a FreeRTOS *
; * tutorial book, reference manual, or both: *
; * http://www.FreeRTOS.org/Documentation *
; * *
; ***************************************************************************
;
; http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
; the FAQ page "My application does not run, what could be wrong?". Have you
; defined configASSERT()?
;
; http://www.FreeRTOS.org/support - In return for receiving this top quality
; embedded software for free we request you assist our global community by
; participating in the support forum.
;
; http://www.FreeRTOS.org/training - Investing in training allows your team to
; be as productive as possible as early as possible. Now you can receive
; FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
; Ltd, and the world's leading authority on the world's leading RTOS.
;
; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
; including FreeRTOS+Trace - an indispensable productivity tool, a DOS
; compatible FAT file system, and our tiny thread aware UDP/IP stack.
;
; http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
; Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
;
; http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
; Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
; licenses offer ticketed support, indemnification and commercial middleware.
;
; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
; engineered and independently SIL3 certified version for use in safety and
; mission critical applications that require provable dependability.
;
; 1 tab == 4 spaces!
;*/
.thumb
.ref ulRegTest1LoopCounter
.ref ulRegTest2LoopCounter
.def vRegTest1Implementation
.def vRegTest2Implementation
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
ulNVIC_INT_CTRL: .word 0xe000ed04
;/*-----------------------------------------------------------*/
.align 4
vRegTest1Implementation: .asmfunc
;/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
;/* Fill the VFP registers with known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg1_loop:
;/* Check all the VFP registers still contain the values set above.
;First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
;/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
;/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
reg1_error_loopf:
;/* If this line is hit then a VFP register value was found to be
;incorrect. */
b reg1_error_loopf
reg1_loopf_pass:
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
;/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, ulRegTest1LoopCounterConst
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
;/* Start again. */
b reg1_loop
reg1_error_loop:
;/* If this line is hit then there was an error in a core register value.
;The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
.endasmfunc
;/*-----------------------------------------------------------*/
.align 4
vRegTest2Implementation: .asmfunc
;/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
;/* Set all the VFP to known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg2_loop:
;/* Check all the VFP registers still contain the values set above.
;First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
;/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
;/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
reg2_error_loopf
;/* If this line is hit then a VFP register value was found to be
;incorrect. */
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
;/* Increment the loop counter to indicate this test is still functioning
;correctly. */
push { r0-r1 }
ldr r0, ulRegTest2LoopCounterConst
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
;/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, ulNVIC_INT_CTRL
lsl r0, r0, #28 ;/* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
;/* Start again. */
b reg2_loop
reg2_error_loop:
;/* If this line is hit then there was an error in a core register value.
;This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
;/*-----------------------------------------------------------*/
.end

525
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
Unescape Escape View File

@ -0,0 +1,525 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
__asm vRegTest1Implementation( void )
{
PRESERVE8
IMPORT ulRegTest1LoopCounter
/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
/* Fill the VFP registers with known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg1_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
reg1_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg1_error_loopf
reg1_loopf_pass
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, =ulRegTest1LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg1_loop
reg1_error_loop
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
nop
}
/*-----------------------------------------------------------*/
__asm vRegTest2Implementation( void )
{
PRESERVE8
IMPORT ulRegTest2LoopCounter
/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
/* Set all the VFP to known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg2_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
reg2_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
/* Increment the loop counter to indicate this test is still functioning
correctly. */
push { r0-r1 }
ldr r0, =ulRegTest2LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
lsl r0, r0, #28 /* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
/* Start again. */
b reg2_loop
reg2_error_loop
/* If this line is hit then there was an error in a core register value.
This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
}
/*-----------------------------------------------------------*/
__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
{
PRESERVE8
/* Clobber the auto saved registers. */
vmov d0, r0, r0
vmov d1, r0, r0
vmov d2, r0, r0
vmov d3, r0, r0
vmov d4, r0, r0
vmov d5, r0, r0
vmov d6, r0, r0
vmov d7, r0, r0
bx lr
}
/*-----------------------------------------------------------*/
__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
{
PRESERVE8
vmov r1, s0
cmp r0, r1
bne return_error
vmov r1, s1
cmp r0, r1
bne return_error
vmov r1, s2
cmp r0, r1
bne return_error
vmov r1, s3
cmp r0, r1
bne return_error
vmov r1, s4
cmp r0, r1
bne return_error
vmov r1, s5
cmp r0, r1
bne return_error
vmov r1, s6
cmp r0, r1
bne return_error
vmov r1, s7
cmp r0, r1
bne return_error
vmov r1, s8
cmp r0, r1
bne return_error
vmov r1, s9
cmp r0, r1
bne return_error
vmov r1, s10
cmp r0, r1
bne return_error
vmov r1, s11
cmp r0, r1
bne return_error
vmov r1, s12
cmp r0, r1
bne return_error
vmov r1, s13
cmp r0, r1
bne return_error
vmov r1, s14
cmp r0, r1
bne return_error
vmov r1, s15
cmp r0, r1
bne return_error
return_pass
mov r0, #1
bx lr
return_error
mov r0, #0
bx lr
}

528
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.s
Unescape Escape View File

@ -0,0 +1,528 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN ulRegTest1LoopCounter
EXTERN ulRegTest2LoopCounter
PUBLIC vRegTest1Implementation
PUBLIC vRegTest2Implementation
/*-----------------------------------------------------------*/
vRegTest1Implementation
/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
/* Fill the VFP registers with known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg1_loop:
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
reg1_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg1_error_loopf
reg1_loopf_pass
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, =ulRegTest1LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg1_loop
reg1_error_loop:
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
/*-----------------------------------------------------------*/
vRegTest2Implementation
/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
/* Set all the VFP to known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg2_loop:
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
reg2_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
/* Increment the loop counter to indicate this test is still functioning
correctly. */
push { r0-r1 }
ldr r0, =ulRegTest2LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
lsl r0, r0, #28 /* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
/* Start again. */
b reg2_loop
reg2_error_loop:
/* If this line is hit then there was an error in a core register value.
This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
/*-----------------------------------------------------------*/
vRegTestClearFlopRegistersToParameterValue
/* Clobber the auto saved registers. */
vmov d0, r0, r0
vmov d1, r0, r0
vmov d2, r0, r0
vmov d3, r0, r0
vmov d4, r0, r0
vmov d5, r0, r0
vmov d6, r0, r0
vmov d7, r0, r0
bx lr
/*-----------------------------------------------------------*/
ulRegTestCheckFlopRegistersContainParameterValue
vmov r1, s0
cmp r0, r1
bne return_error
vmov r1, s1
cmp r0, r1
bne return_error
vmov r1, s2
cmp r0, r1
bne return_error
vmov r1, s3
cmp r0, r1
bne return_error
vmov r1, s4
cmp r0, r1
bne return_error
vmov r1, s5
cmp r0, r1
bne return_error
vmov r1, s6
cmp r0, r1
bne return_error
vmov r1, s7
cmp r0, r1
bne return_error
vmov r1, s8
cmp r0, r1
bne return_error
vmov r1, s9
cmp r0, r1
bne return_error
vmov r1, s10
cmp r0, r1
bne return_error
vmov r1, s11
cmp r0, r1
bne return_error
vmov r1, s12
cmp r0, r1
bne return_error
vmov r1, s13
cmp r0, r1
bne return_error
vmov r1, s14
cmp r0, r1
bne return_error
vmov r1, s15
cmp r0, r1
bne return_error
return_pass
mov r0, #1
bx lr
return_error
mov r0, #0
bx lr
END

126
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RunTimeStatsTimer.c
Unescape Escape View File

@ -0,0 +1,126 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
/* Utility functions to implement run time stats on Cortex-M CPUs. The collected
run time data can be viewed through the CLI interface. See the following URL for
more information on run time stats:
http://www.freertos.org/rtos-run-time-stats.html */
/* Addresses of registers in the Cortex-M debug hardware. */
#define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) )
#define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) )
#define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) )
#define rtsTRCENA_BIT ( 0x01000000UL )
#define rtsCOUNTER_ENABLE_BIT ( 0x01UL )
/* Simple shift divide for scaling to avoid an overflow occurring too soon. */
#define runtimeSHIFT_13 13
#define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) )
static const uint32_t ulPrescaleBits = runtimeSHIFT_13;
static const uint32_t ulOverflowBit = runtimeOVERFLOW_BIT_13;
/*-----------------------------------------------------------*/
void vConfigureTimerForRunTimeStats( void )
{
/* Enable TRCENA. */
rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
/* Reset counter. */
rtsDWT_CYCCNT = 0;
/* Enable counter. */
rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
uint32_t ulGetRunTimeCounterValue( void )
{
static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
unsigned long ulValueNow;
ulValueNow = rtsDWT_CYCCNT;
/* Has the value overflowed since it was last read. */
if( ulValueNow < ulLastCounterValue )
{
ulOverflows += ulOverflowBit;
}
ulLastCounterValue = ulValueNow;
/* There is no prescale on the counter, so simulate in software. */
ulValueNow = ( ulValueNow >> ulPrescaleBits ) + ulOverflows;
return ulValueNow;
}
/*-----------------------------------------------------------*/

490
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/main_full.c
Unescape Escape View File

@ -0,0 +1,490 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to
* select between the two. See the notes on using
* configCREATE_SIMPLY_BLINKY_DEMO_ONLY in main.c. This file implements the
* comprehensive version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions.
*
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* FreeRTOS+CLI command console. The command console is access through the
* UART at 19200 baud. For reasons of robustness testing the UART driver is
* deliberately written to be inefficient and should not be used as a template
* for a production driver. Type "help" to see a list of registered commands.
* The FreeRTOS+CLI license is different to the FreeRTOS license, see
* http://www.FreeRTOS.org/cli for license and usage details.
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" task - The check task period is initially set to three seconds. The
* task checks that all the standard demo tasks, and the register check tasks,
* are not only still executing, but are executing without reporting any errors.
* If the check task discovers that a task has either stalled, or reported an
* error, then it changes its own execution period from the initial three
* seconds, to just 200ms. The check task also toggles an LED each time it is
* called. This provides a visual indication of the system status: If the LED
* toggles every three seconds, then no issues have been discovered. If the LED
* toggles every 200ms, then an issue has been discovered with at least one
* task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "semtest.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "partest.h"
#include "serial.h"
#include "TimerDemo.h"
#include "IntQueue.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
/* Priorities for the demo application tasks. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL )
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
/* The priority used by the UART command console task. */
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_PERIOD_MS constant. */
#define mainNO_ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 3000UL ) )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_PERIOD_MS constant. */
#define mainERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 200UL ) )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
/* Dimensions the queue in which characters received from the UART are
placed. */
#define mainRX_QUEUE_LENGTH 10
/*-----------------------------------------------------------*/
/*
* The check task, as described at the top of this file.
*/
static void prvCheckTask( void *pvParameters );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file, but the
* entry points are kept in the C file for the convenience of checking the task
* parameter.
*/
static void prvRegTestTaskEntry1( void *pvParameters );
extern void vRegTest1Implementation( void );
static void prvRegTestTaskEntry2( void *pvParameters );
extern void vRegTest2Implementation( void );
/*
* Register commands that can be used with FreeRTOS+CLI. The commands are
* defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
*/
extern void vRegisterSampleCLICommands( void );
/*
* The task that manages the FreeRTOS+CLI input and output.
*/
extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
/*
* When the full demo is build the idle hook is used to create some timers that
* cannot be created in main() because the timer demo tasks need the entire
* command queue.
*/
void vFullDemoIdleHook( void );
/*
* The full demo configures the clocks for maximum frequency, wheras the blinky
* demo uses a slower clock as it also uses low power features.
*/
static void prvConfigureClocks( void );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check task. If the variables keep incrementing,
then the register check tasks has not discovered any errors. If a variable
stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
void main_full( void )
{
/* This demo sets the clock to its maximum. The blinky demo uses as slower
clock as it uses low power features. */
prvConfigureClocks();
/* Init the serial port for use by the CLI. The baud rate parameter is not
used so set to 0 to make this obvious. */
xSerialPortInitMinimal( 0, mainRX_QUEUE_LENGTH );
/* Start all the other standard demo/test tasks. They have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartInterruptQueueTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
/* Note - the set of standard demo tasks contains two versions of
vStartMathTasks.c. One is defined in flop.c, and uses double precision
floating point numbers and variables. The other is defined in sp_flop.c,
and uses single precision floating point numbers and variables. sp_flop.
c should be included in this project. */
vStartMathTasks( mainFLOP_TASK_PRIORITY );
/* Start the tasks that implements the command console on the UART, as
described above. */
vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );
/* Register the standard CLI commands. */
vRegisterSampleCLICommands();
/* Create the register check tasks, as described at the top of this file */
xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The onboard LED is toggled on each iteration.
If an error is detected then the delay period is decreased from
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
effect of increasing the rate at which the onboard LED toggles, and in so
doing gives visual feedback of the system status. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* Check all the demo tasks to ensure that they are all still running,
and that none have detected an error. */
if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 0UL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 1UL;
}
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 5UL;
}
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 6UL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 8UL;
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 10UL;
}
if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 14UL;
}
if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )
{
ulErrorFound |= 1UL << 9UL;
}
if( xAreEventGroupTasksStillRunning() != pdPASS )
{
ulErrorFound |= 1UL << 12UL;
}
if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 13UL;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound |= 1UL << 15UL;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound |= 1UL << 16UL;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
everything is ok. A faster toggle indicates an error. */
configTOGGLE_LED();
if( ulErrorFound != pdFALSE )
{
/* An error has been detected in one of the tasks - flash the LED
at a higher frequency to give visible feedback that something has
gone wrong (it might just be that the loop back connector required
by the comtest tasks has not been fitted). */
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
}
}
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry1( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check timer will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry2( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check timer will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvConfigureClocks( void )
{
/* The full demo configures the clocks for maximum frequency, wheras the
blinky demo uses a slower clock as it also uses low power features. Maximum
freqency also needs more voltage.
From the datashee: For AM_LDO_VCORE1 and AM_DCDC_VCORE1 modes, the maximum
CPU operating frequency is 48 MHz and maximum input clock frequency for
peripherals is 24 MHz. */
PCM_setCoreVoltageLevel( PCM_VCORE1 );
CS_setDCOCenteredFrequency( CS_DCO_FREQUENCY_48 );
CS_initClockSignal( CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
CS_initClockSignal( CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
CS_initClockSignal( CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
CS_initClockSignal( CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
}
/*-----------------------------------------------------------*/
#if( configCREATE_SIMPLE_TICKLESS_DEMO == 0 )
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
/* The full demo includes a software timer demo/test that requires
prodding periodically from the tick interrupt. */
vTimerPeriodicISRTests();
/* Call the periodic event group from ISR demo. */
vPeriodicEventGroupsProcessing();
/* Use task notifications from an interrupt. */
xNotifyTaskFromISR();
/* Use mutexes from interrupts. */
vInterruptSemaphorePeriodicTest();
}
#endif
/*-----------------------------------------------------------*/

307
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
Unescape Escape View File

@ -0,0 +1,307 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
Note1: This driver is used specifically to provide an interface to the
FreeRTOS+CLI command interpreter. It is *not* intended to be a generic
serial port driver. Nor is it intended to be used as an example of an
efficient implementation. In particular, a queue is used to buffer
received characters, which is fine in this case as key presses arrive
slowly, but a DMA and/or RAM buffer should be used in place of the queue in
applications that expect higher throughput.
Note2: This driver does not attempt to handle UART errors.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/*
* The UART interrupt handler.
*/
void vUART_Handler( void );
/*-----------------------------------------------------------*/
/* The queue into which received key presses are placed. NOTE THE COMMENTS AT
THE TOP OF THIS FILE REGARDING THE USE OF QUEUES FOR THIS PURPOSE. */
static QueueHandle_t xRxQueue = NULL;
/* Variables used in the Tx interrupt to send a string. */
static volatile const signed char *pcStringStart = NULL, *pcStringEnd = NULL;
static volatile TaskHandle_t xTransmittingTask = NULL;
static EUSCI_A0_Type * const pxUARTA0 = ( EUSCI_A0_Type * ) EUSCI_A0_MODULE;
/* UART Configuration for 19200 baud. Value generated using the tool provided
on the following page:
http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html
*/
const eUSCI_UART_Config xUARTConfig =
{
EUSCI_A_UART_CLOCKSOURCE_SMCLK, /* SMCLK Clock Source. */
156, /* BRDIV */
4, /* UCxBRF */
0, /* UCxBRS */
EUSCI_A_UART_NO_PARITY, /* No Parity. */
EUSCI_A_UART_LSB_FIRST, /* MSB First. */
EUSCI_A_UART_ONE_STOP_BIT, /* One stop bit. */
EUSCI_A_UART_MODE, /* UART mode. */
EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION /* Low Frequency Mode. */
};
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned long uxQueueLength )
{
/* Create the queue used to hold received characters. NOTE THE COMMENTS AT
THE TOP OF THIS FILE REGARDING THE USE OF QUEUES FOR THIS PURPSOE. */
xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) );
configASSERT( xRxQueue );
/* Use the library functions to initialise and enable the UART. */
MAP_UART_initModule( EUSCI_A0_MODULE, &xUARTConfig );
MAP_UART_enableModule( EUSCI_A0_MODULE );
MAP_UART_clearInterruptFlag( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT );
/* The interrupt handler uses the FreeRTOS API function so its priority must
be at or below the configured maximum system call interrupt priority.
configKERNEL_INTERRUPT_PRIORITY is the priority used by the RTOS tick and
(should) always be set to the minimum priority. */
MAP_Interrupt_setPriority( INT_EUSCIA0, configKERNEL_INTERRUPT_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_EUSCIA0 );
/* Only one UART is supported so the handle is not used. */
return ( xComPortHandle ) 0;
}
/*-----------------------------------------------------------*/
BaseType_t xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
BaseType_t xReturn;
/* Only a single port is supported. */
( void ) pxPort;
/* Obtain a received character from the queue - entering the Blocked state
(so not consuming any processing time) to wait for a character if one is not
already available. */
xReturn = xQueueReceive( xRxQueue, pcRxedChar, xBlockTime );
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL * ( uint32_t ) usStringLength );
/* Only a single port is supported. */
( void ) pxPort;
/* Note there is no mutual exclusion at the driver level. If more than one
task is using the serial port then mutual exclusion should be provided where
this function is called. */
/* Ensure notifications are not already waiting. */
( void ) ulTaskNotifyTake( pdTRUE, 0 );
/* Remember which task is sending the byte. */
xTransmittingTask = xTaskGetCurrentTaskHandle();
/* Mark the start and end of the data being sent. */
pcStringStart = pcString;
pcStringEnd = pcStringStart + usStringLength;
/* Start to send the first byte. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcString;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL );
/* Only a single port is supported. */
( void ) pxPort;
/* Note there is no mutual exclusion at the driver level. If more than one
task is using the serial port then mutual exclusion should be provided where
this function is called. */
/* Ensure notifications are not already waiting. */
( void ) ulTaskNotifyTake( pdTRUE, 0 );
/* Remember which task is sending the byte. */
xTransmittingTask = xTaskGetCurrentTaskHandle();
/* Mark the start and end of the data being sent - in this case just a
single byte. */
pcStringStart = &cOutChar;
pcStringEnd = pcStringStart + sizeof( cOutChar );
/* Start to send the byte. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) cOutChar;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
return pdPASS;
}
/*-----------------------------------------------------------*/
void vSerialClose(xComPortHandle xPort)
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/
void vUART_Handler( void )
{
uint8_t ucChar;
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
uint_fast8_t xInterruptStatus;
xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_MODULE );
if( ( xInterruptStatus & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG ) != 0x00 )
{
/* Obtain the character. */
ucChar = MAP_UART_receiveData( EUSCI_A0_MODULE );
/* Send the character to the queue. Note the comments at the top of this
file with regards to the inefficiency of this method for anything other than
very low bandwidth communications.
If writing to the queue unblocks a task, and the unblocked task has a
priority above the currently running task (the task that this interrupt
interrupted), then xHigherPriorityTaskWoken will be set to pdTRUE inside the
xQueueSendFromISR() function. xHigherPriorityTaskWoken is then passed to
portYIELD_FROM_ISR() at the end of this interrupt handler to request a
context switch so the interrupt returns directly to the (higher priority)
unblocked task. */
xQueueSendFromISR( xRxQueue, &ucChar, &xHigherPriorityTaskWoken );
}
if( ( xInterruptStatus & EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG ) != 0x00 )
{
/* Are there more characters to transmit? */
pcStringStart++;
if( ( uint32_t ) pcStringStart < ( uint32_t ) pcStringEnd )
{
/* This is probably quite a heavy wait function just for writing to
the Tx register. An optimised design would probably replace this
with a simple register write. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcStringStart;
}
else
{
/* No more characters to send. Disable the interrupt and notify the
task, if the task is waiting. */
MAP_UART_disableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
if( xTransmittingTask != NULL )
{
vTaskNotifyGiveFromISR( xTransmittingTask, &xHigherPriorityTaskWoken );
xTransmittingTask = NULL;
}
}
}
/* portYIELD_FROM_ISR() will request a context switch if executing this
interrupt handler caused a task to leave the blocked state, and the task
that left the blocked state has a higher priority than the currently running
task (the task this interrupt interrupted). See the comment above the calls
to xSemaphoreGiveFromISR() and xQueueSendFromISR() within this function. */
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
}

2741
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
View File

File diff suppressed because it is too large Load Diff

2086
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
View File

File diff suppressed because it is too large Load Diff

358
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
Unescape Escape View File

@ -0,0 +1,358 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>2</fileVersion>
<configuration>
<name>Debug</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>RuntimeChecking</name>
<archiveVersion>0</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>GenRtcDebugHeap</name>
<state>0</state>
</option>
<option>
<name>GenRtcEnableBoundsChecking</name>
<state>0</state>
</option>
<option>
<name>GenRtcCheckPtrsNonInstrMem</name>
<state>1</state>
</option>
<option>
<name>GenRtcTrackPointerBounds</name>
<state>1</state>
</option>
<option>
<name>GenRtcCheckAccesses</name>
<state>1</state>
</option>
<option>
<name>GenRtcGenerateEntries</name>
<state>0</state>
</option>
<option>
<name>GenRtcNrTrackedPointers</name>
<state>1000</state>
</option>
<option>
<name>GenRtcIntOverflow</name>
<state>0</state>
</option>
<option>
<name>GenRtcIncUnsigned</name>
<state>0</state>
</option>
<option>
<name>GenRtcIntConversion</name>
<state>0</state>
</option>
<option>
<name>GenRtcInclExplicit</name>
<state>0</state>
</option>
<option>
<name>GenRtcIntShiftOverflow</name>
<state>0</state>
</option>
<option>
<name>GenRtcInclUnsignedShiftOverflow</name>
<state>0</state>
</option>
<option>
<name>GenRtcUnhandledCase</name>
<state>0</state>
</option>
<option>
<name>GenRtcDivByZero</name>
<state>0</state>
</option>
<option>
<name>GenRtcEnable</name>
<state>0</state>
</option>
<option>
<name>GenRtcCheckPtrsNonInstrFunc</name>
<state>1</state>
</option>
</data>
</settings>
</configuration>
<configuration>
<name>Release</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>0</debug>
<settings>
<name>RuntimeChecking</name>
<archiveVersion>0</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>GenRtcDebugHeap</name>
<state>0</state>
</option>
<option>
<name>GenRtcEnableBoundsChecking</name>
<state>0</state>
</option>
<option>
<name>GenRtcCheckPtrsNonInstrMem</name>
<state>1</state>
</option>
<option>
<name>GenRtcTrackPointerBounds</name>
<state>1</state>
</option>
<option>
<name>GenRtcCheckAccesses</name>
<state>1</state>
</option>
<option>
<name>GenRtcGenerateEntries</name>
<state>0</state>
</option>
<option>
<name>GenRtcNrTrackedPointers</name>
<state>1000</state>
</option>
<option>
<name>GenRtcIntOverflow</name>
<state>0</state>
</option>
<option>
<name>GenRtcIncUnsigned</name>
<state>0</state>
</option>
<option>
<name>GenRtcIntConversion</name>
<state>0</state>
</option>
<option>
<name>GenRtcInclExplicit</name>
<state>0</state>
</option>
<option>
<name>GenRtcIntShiftOverflow</name>
<state>0</state>
</option>
<option>
<name>GenRtcInclUnsignedShiftOverflow</name>
<state>0</state>
</option>
<option>
<name>GenRtcUnhandledCase</name>
<state>0</state>
</option>
<option>
<name>GenRtcDivByZero</name>
<state>0</state>
</option>
<option>
<name>GenRtcEnable</name>
<state>0</state>
</option>
<option>
<name>GenRtcCheckPtrsNonInstrFunc</name>
<state>1</state>
</option>
</data>
</settings>
</configuration>
<group>
<name>DriverLibrary</name>
<file>
<name>$PROJ_DIR$\driverlib\cpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\cs.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\fpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\gpio.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\interrupt.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\pcm.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\timer32.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\uart.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\wdt_a.c</name>
</file>
</group>
<group>
<name>FreeRTOS_Source</name>
<group>
<name>include</name>
<file>
<name>$PROJ_DIR$\..\..\Source\include\event_groups.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\include\projdefs.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\include\queue.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\include\semphr.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\include\task.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\include\timers.h</name>
</file>
</group>
<group>
<name>Portable</name>
<group>
<name>IAR</name>
<group>
<name>Cortex-M4F</name>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\port.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portasm.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portmacro.h</name>
</file>
</group>
</group>
<group>
<name>MemMang</name>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>
</file>
</group>
</group>
<file>
<name>$PROJ_DIR$\..\..\Source\event_groups.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\list.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\tasks.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\timers.c</name>
</file>
</group>
<group>
<name>Full_Demo</name>
<group>
<name>FreeRTOS+CLI</name>
<file>
<name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.h</name>
</file>
</group>
<group>
<name>Standard Demo Tasks</name>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\IntQueue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\IntSemTest.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\sp_flop.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\TaskNotify.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\Full_Demo\IntQueueTimer.c</name>
</file>
<file>
<name>$PROJ_DIR$\Full_Demo\main_full.c</name>
</file>
<file>
<name>$PROJ_DIR$\Full_Demo\RegTest.s</name>
</file>
<file>
<name>$PROJ_DIR$\Full_Demo\RunTimeStatsTimer.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</name>
</file>
<file>
<name>$PROJ_DIR$\Full_Demo\serial.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</name>
</file>
</group>
<group>
<name>Simply Blinky Demo</name>
<file>
<name>$PROJ_DIR$\SimplyBlinkyDemo\main_blinky.c</name>
</file>
</group>
<group>
<name>System</name>
<file>
<name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\FreeRTOSConfig.h</name>
</file>
<file>
<name>$PROJ_DIR$\main.c</name>
</file>
</project>

0
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/RTOSDemo.eww → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.eww
Unescape Escape View File

800
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
Unescape Escape View File

@ -0,0 +1,800 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>4</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"XDS-ICDI (02.02.03.02) with CMSIS-DAP" -U00000001 -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59101789 -O47 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UM0149MEE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>uly,0x0A</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>ulx,0x0A</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>xTickCount,0x0A</ItemText>
</Ww>
</WatchWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
<Protocol>1</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>system</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\startup_MSP432P4.s</PathWithFileName>
<FilenameWithoutPath>startup_MSP432P4.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\system_MSP432P4.c</PathWithFileName>
<FilenameWithoutPath>system_MSP432P4.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
<FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Simple Blinky Demo</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\SimplyBlinkyDemo\main_blinky.c</PathWithFileName>
<FilenameWithoutPath>main_blinky.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>FreeRTOS Source</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\event_groups.c</PathWithFileName>
<FilenameWithoutPath>event_groups.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\list.c</PathWithFileName>
<FilenameWithoutPath>list.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\queue.c</PathWithFileName>
<FilenameWithoutPath>queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
<FilenameWithoutPath>tasks.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\timers.c</PathWithFileName>
<FilenameWithoutPath>timers.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\MemMang\heap_4.c</PathWithFileName>
<FilenameWithoutPath>heap_4.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName>
<FilenameWithoutPath>port.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Full Demo</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\main_full.c</PathWithFileName>
<FilenameWithoutPath>main_full.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RunTimeStatsTimer.c</PathWithFileName>
<FilenameWithoutPath>RunTimeStatsTimer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\serial.c</PathWithFileName>
<FilenameWithoutPath>serial.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName>
<FilenameWithoutPath>BlockQ.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\countsem.c</PathWithFileName>
<FilenameWithoutPath>countsem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\EventGroupsDemo.c</PathWithFileName>
<FilenameWithoutPath>EventGroupsDemo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\GenQTest.c</PathWithFileName>
<FilenameWithoutPath>GenQTest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntSemTest.c</PathWithFileName>
<FilenameWithoutPath>IntSemTest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\recmutex.c</PathWithFileName>
<FilenameWithoutPath>recmutex.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName>
<FilenameWithoutPath>semtest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\sp_flop.c</PathWithFileName>
<FilenameWithoutPath>sp_flop.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TaskNotify.c</PathWithFileName>
<FilenameWithoutPath>TaskNotify.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TimerDemo.c</PathWithFileName>
<FilenameWithoutPath>TimerDemo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</PathWithFileName>
<FilenameWithoutPath>FreeRTOS_CLI.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</PathWithFileName>
<FilenameWithoutPath>Sample-CLI-commands.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</PathWithFileName>
<FilenameWithoutPath>UARTCommandConsole.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RegTest.c</PathWithFileName>
<FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\IntQueueTimer.c</PathWithFileName>
<FilenameWithoutPath>IntQueueTimer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntQueue.c</PathWithFileName>
<FilenameWithoutPath>IntQueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Driver Library</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cpu.c</PathWithFileName>
<FilenameWithoutPath>cpu.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cs.c</PathWithFileName>
<FilenameWithoutPath>cs.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\gpio.c</PathWithFileName>
<FilenameWithoutPath>gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\interrupt.c</PathWithFileName>
<FilenameWithoutPath>interrupt.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\pcm.c</PathWithFileName>
<FilenameWithoutPath>pcm.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\uart.c</PathWithFileName>
<FilenameWithoutPath>uart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\wdt_a.c</PathWithFileName>
<FilenameWithoutPath>wdt_a.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\sysctl.c</PathWithFileName>
<FilenameWithoutPath>sysctl.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\fpu.c</PathWithFileName>
<FilenameWithoutPath>fpu.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\timer32.c</PathWithFileName>
<FilenameWithoutPath>timer32.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

675
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
Unescape Escape View File

@ -0,0 +1,675 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>MSP432P401R</Device>
<Vendor>Texas Instruments</Vendor>
<PackID>TI.MSP432.1.0.0</PackID>
<Cpu>IROM(0x00000000,0x00040000) IROM2(0x00200000,0x00004000) IRAM(0x20000000,0x00010000) IRAM2(0x01000000,0x00010000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD01000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB -FS00 -FL040000 -FF1MSP432P4xx_InfoFlash -FS1200000 -FL14000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:MSP432P401R$Device\Include\msp.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:MSP432P401R$SVD\MSP432P401R.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Keil_Debug\</OutputDirectory>
<OutputName>RTOSDemo</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x200000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x1000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define>keil __MSP432P401R__</Define>
<Undefine></Undefine>
<IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>system</GroupName>
<Files>
<File>
<FileName>startup_MSP432P4.s</FileName>
<FileType>2</FileType>
<FilePath>.\system\Keil\startup_MSP432P4.s</FilePath>
</File>
<File>
<FileName>system_MSP432P4.c</FileName>
<FileType>1</FileType>
<FilePath>.\system\Keil\system_MSP432P4.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>main</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
<File>
<FileName>FreeRTOSConfig.h</FileName>
<FileType>5</FileType>
<FilePath>.\FreeRTOSConfig.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Simple Blinky Demo</GroupName>
<Files>
<File>
<FileName>main_blinky.c</FileName>
<FileType>1</FileType>
<FilePath>.\SimplyBlinkyDemo\main_blinky.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FreeRTOS Source</GroupName>
<Files>
<File>
<FileName>event_groups.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\event_groups.c</FilePath>
</File>
<File>
<FileName>list.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\list.c</FilePath>
</File>
<File>
<FileName>queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\queue.c</FilePath>
</File>
<File>
<FileName>tasks.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\tasks.c</FilePath>
</File>
<File>
<FileName>timers.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\timers.c</FilePath>
</File>
<File>
<FileName>heap_4.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
</File>
<File>
<FileName>port.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Full Demo</GroupName>
<Files>
<File>
<FileName>main_full.c</FileName>
<FileType>1</FileType>
<FilePath>.\Full_Demo\main_full.c</FilePath>
</File>
<File>
<FileName>RunTimeStatsTimer.c</FileName>
<FileType>1</FileType>
<FilePath>.\Full_Demo\RunTimeStatsTimer.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>.\Full_Demo\serial.c</FilePath>
</File>
<File>
<FileName>BlockQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\BlockQ.c</FilePath>
</File>
<File>
<FileName>countsem.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\countsem.c</FilePath>
</File>
<File>
<FileName>EventGroupsDemo.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\EventGroupsDemo.c</FilePath>
</File>
<File>
<FileName>GenQTest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\GenQTest.c</FilePath>
</File>
<File>
<FileName>IntSemTest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\IntSemTest.c</FilePath>
</File>
<File>
<FileName>recmutex.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\recmutex.c</FilePath>
</File>
<File>
<FileName>semtest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\semtest.c</FilePath>
</File>
<File>
<FileName>sp_flop.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\sp_flop.c</FilePath>
</File>
<File>
<FileName>TaskNotify.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\TaskNotify.c</FilePath>
</File>
<File>
<FileName>TimerDemo.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
</File>
<File>
<FileName>FreeRTOS_CLI.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</FilePath>
</File>
<File>
<FileName>Sample-CLI-commands.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</FilePath>
</File>
<File>
<FileName>UARTCommandConsole.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</FilePath>
</File>
<File>
<FileName>RegTest.c</FileName>
<FileType>1</FileType>
<FilePath>.\Full_Demo\RegTest.c</FilePath>
</File>
<File>
<FileName>IntQueueTimer.c</FileName>
<FileType>1</FileType>
<FilePath>.\Full_Demo\IntQueueTimer.c</FilePath>
</File>
<File>
<FileName>IntQueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\IntQueue.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Driver Library</GroupName>
<Files>
<File>
<FileName>cpu.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\cpu.c</FilePath>
</File>
<File>
<FileName>cs.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\cs.c</FilePath>
</File>
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\gpio.c</FilePath>
</File>
<File>
<FileName>interrupt.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\interrupt.c</FilePath>
</File>
<File>
<FileName>pcm.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\pcm.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\uart.c</FilePath>
</File>
<File>
<FileName>wdt_a.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\wdt_a.c</FilePath>
</File>
<File>
<FileName>sysctl.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\sysctl.c</FilePath>
</File>
<File>
<FileName>fpu.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\fpu.c</FilePath>
</File>
<File>
<FileName>timer32.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\timer32.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.40.0" condition="CMSIS Core">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="Device\Source\startup_MSP432P4.s">
<instance index="0" removed="1">RTE\Device\MSP432P401R\startup_MSP432P4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="TI" Cversion="1.0.0" condition="MSP432 CMSIS-CORE"/>
<package license="license.txt" name="MSP432" schemaVersion="1.2" vendor="TI" version="1.0.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="Device\Source\system_MSP432P4.c">
<instance index="0" removed="1">RTE\Device\MSP432P401R\system_MSP432P4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="TI" Cversion="1.0.0" condition="MSP432 CMSIS-CORE"/>
<package license="license.txt" name="MSP432" schemaVersion="1.2" vendor="TI" version="1.0.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

308
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/SimplyBlinkyDemo/main_blinky.c
Unescape Escape View File

@ -0,0 +1,308 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* configCREATE_SIMPLE_TICKLESS_DEMO setting in FreeRTOSConfig.h is used to
* select between the two. See the notes on using
* configCREATE_SIMPLE_TICKLESS_DEMO in main.c. This file implements the
* simply blinky style version.
*
* The blinky demo uses FreeRTOS's tickless idle mode to reduce power
* consumption. See the notes on the web page below regarding the difference
* in power saving that can be achieved between using the generic tickless
* implementation (as used by the blinky demo) and a tickless implementation
* that is tailored specifically to the MSP432.
*
* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles the LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_PERIOD_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 1000UL ) )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* Values passed to the two tasks just to check the task parameter
functionality. */
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* Called by main() to create the simply blinky style application if
* configCREATE_SIMPLE_TICKLESS_DEMO is set to 1.
*/
void main_blinky( void );
/*
* The full demo configures the clocks for maximum frequency, wheras this blinky
* demo uses a slower clock as it also uses low power features.
*/
static void prvConfigureClocks( void );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for
instructions and notes regarding the difference in power saving that can be
achieved between using the generic tickless RTOS implementation (as used by
the blinky demo) and a tickless RTOS implementation that is tailored
specifically to the MSP432. */
/* The full demo configures the clocks for maximum frequency, wheras this
blinky demo uses a slower clock as it also uses low power features. */
prvConfigureClocks();
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
static const TickType_t xShortBlock = pdMS_TO_TICKS( 50 );
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
/* Blip the LED for a short while so as not to use too much
power. */
configTOGGLE_LED();
vTaskDelay( xShortBlock );
configTOGGLE_LED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/
static void prvConfigureClocks( void )
{
/* The full demo configures the clocks for maximum frequency, wheras this
blinky demo uses a slower clock as it also uses low power features.
From the datashee: For AM_LDO_VCORE0 and AM_DCDC_VCORE0 modes, the maximum
CPU operating frequency is 24 MHz and maximum input clock frequency for
peripherals is 12 MHz. */
CS_setDCOCenteredFrequency( CS_DCO_FREQUENCY_3 );
CS_initClockSignal( CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
CS_initClockSignal( CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
CS_initClockSignal( CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
CS_initClockSignal( CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
/* The lower frequency allows the use of CVORE level 0. */
PCM_setCoreVoltageLevel( PCM_VCORE0 );
}
/*-----------------------------------------------------------*/
void vPreSleepProcessing( uint32_t ulExpectedIdleTime )
{
}
/*-----------------------------------------------------------*/
#if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 )
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
/* Only the full demo uses the tick hook so there is no code is
executed here. */
}
#endif

748
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
Unescape Escape View File

@ -0,0 +1,748 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
#include <stdbool.h>
/* DriverLib Includes */
#include <adc14.h>
#include <debug.h>
#include <interrupt.h>
/* Statics */
static volatile uint32_t* const _ctlRegs[32] =
{ &ADC14->rMCTL0.r, &ADC14->rMCTL1.r, &ADC14->rMCTL2.r, &ADC14->rMCTL3.r,
&ADC14->rMCTL4.r, &ADC14->rMCTL5.r, &ADC14->rMCTL6.r, &ADC14->rMCTL7.r,
&ADC14->rMCTL8.r, &ADC14->rMCTL9.r, &ADC14->rMCTL10.r,
&ADC14->rMCTL11.r, &ADC14->rMCTL12.r, &ADC14->rMCTL13.r,
&ADC14->rMCTL14.r, &ADC14->rMCTL15.r, &ADC14->rMCTL16.r,
&ADC14->rMCTL17.r, &ADC14->rMCTL18.r, &ADC14->rMCTL19.r,
&ADC14->rMCTL20.r, &ADC14->rMCTL21.r, &ADC14->rMCTL22.r,
&ADC14->rMCTL23.r, &ADC14->rMCTL24.r, &ADC14->rMCTL25.r,
&ADC14->rMCTL26.r, &ADC14->rMCTL27.r, &ADC14->rMCTL28.r,
&ADC14->rMCTL29.r, &ADC14->rMCTL30.r, &ADC14->rMCTL31.r };
static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
{
switch (reg)
{
case ADC_MEM0:
return 0;
case ADC_MEM1:
return 1;
case ADC_MEM2:
return 2;
case ADC_MEM3:
return 3;
case ADC_MEM4:
return 4;
case ADC_MEM5:
return 5;
case ADC_MEM6:
return 6;
case ADC_MEM7:
return 7;
case ADC_MEM8:
return 8;
case ADC_MEM9:
return 9;
case ADC_MEM10:
return 10;
case ADC_MEM11:
return 11;
case ADC_MEM12:
return 12;
case ADC_MEM13:
return 13;
case ADC_MEM14:
return 14;
case ADC_MEM15:
return 15;
case ADC_MEM16:
return 16;
case ADC_MEM17:
return 17;
case ADC_MEM18:
return 18;
case ADC_MEM19:
return 19;
case ADC_MEM20:
return 20;
case ADC_MEM21:
return 21;
case ADC_MEM22:
return 22;
case ADC_MEM23:
return 23;
case ADC_MEM24:
return 24;
case ADC_MEM25:
return 25;
case ADC_MEM26:
return 26;
case ADC_MEM27:
return 27;
case ADC_MEM28:
return 28;
case ADC_MEM29:
return 29;
case ADC_MEM30:
return 30;
case ADC_MEM31:
return 31;
default:
ASSERT(false);
return ADC_INVALID_MEM;
}
}
//*****************************************************************************
//
//!
//! Returns a boolean value that tells if conversion is active/running or is
//! not acMSP432 ted.
//!
//! Originally a public function, but moved to static. External customers should
//! use the ADC14_isBusy function.
//!
//! \return true if conversion is active, false otherwise
//
//*****************************************************************************
static bool ADCIsConversionRunning(void)
{
return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
}
void ADC14_enableModule(void)
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 1;
}
bool ADC14_disableModule(void)
{
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 0;
return true;
}
bool ADC14_enableSampleTimer(uint32_t multiSampleConvert)
{
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 1;
if (multiSampleConvert == ADC_MANUAL_ITERATION)
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 0;
} else
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 1;
}
return true;
}
bool ADC14_disableSampleTimer(void)
{
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 0;
return true;
}
bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider,
uint32_t clockDivider, uint32_t internalChannelMask)
{
ASSERT(
clockSource == ADC_CLOCKSOURCE_ADCOSC
|| clockSource == ADC_CLOCKSOURCE_SYSOSC
|| clockSource == ADC_CLOCKSOURCE_ACLK
|| clockSource == ADC_CLOCKSOURCE_MCLK
|| clockSource == ADC_CLOCKSOURCE_SMCLK
|| clockSource == ADC_CLOCKSOURCE_HSMCLK);
ASSERT(
clockPredivider == ADC_PREDIVIDER_1
|| clockPredivider == ADC_PREDIVIDER_4
|| clockPredivider == ADC_PREDIVIDER_32
|| clockPredivider == ADC_PREDIVIDER_64);
ASSERT(
clockDivider == ADC_DIVIDER_1 || clockDivider == ADC_DIVIDER_2
|| clockDivider == ADC_DIVIDER_3
|| clockDivider == ADC_DIVIDER_4
|| clockDivider == ADC_DIVIDER_5
|| clockDivider == ADC_DIVIDER_6
|| clockDivider == ADC_DIVIDER_7
|| clockDivider == ADC_DIVIDER_8);
ASSERT(
!(internalChannelMask
& ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1
| ADC_MAPINTCH0 | ADC_TEMPSENSEMAP | ADC_BATTMAP)));
if (ADCIsConversionRunning())
return false;
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14PDIV_M | ADC14DIV_M | ADC14SSEL_M))
| clockDivider | clockPredivider | clockSource;
ADC14->rCTL1.r = (ADC14->rCTL1.r
& ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0
| ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask;
return true;
}
void ADC14_setResolution(uint32_t resolution)
{
ASSERT(
resolution == ADC_8BIT || resolution == ADC_10BIT
|| resolution == ADC_12BIT || resolution == ADC_14BIT);
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~ADC14RES_M) | resolution;
}
uint_fast32_t ADC14_getResolution(void)
{
return ADC14->rCTL1.r & ADC14RES_M;
}
bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
{
ASSERT(
source == ADC_TRIGGER_ADCSC || source == ADC_TRIGGER_SOURCE1
|| source == ADC_TRIGGER_SOURCE2
|| source == ADC_TRIGGER_SOURCE3
|| source == ADC_TRIGGER_SOURCE4
|| source == ADC_TRIGGER_SOURCE5
|| source == ADC_TRIGGER_SOURCE6
|| source == ADC_TRIGGER_SOURCE7);
if (ADCIsConversionRunning())
return false;
if (invertSignal)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14ISSH | ADC14SHS_M)) | source
| ADC14ISSH;
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14ISSH | ADC14SHS_M)) | source;
}
return true;
}
bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth,
uint32_t secondPulseWidth)
{
ASSERT(
firstPulseWidth == ADC_PULSE_WIDTH_4
|| firstPulseWidth == ADC_PULSE_WIDTH_8
|| firstPulseWidth == ADC_PULSE_WIDTH_16
|| firstPulseWidth == ADC_PULSE_WIDTH_32
|| firstPulseWidth == ADC_PULSE_WIDTH_64
|| firstPulseWidth == ADC_PULSE_WIDTH_96
|| firstPulseWidth == ADC_PULSE_WIDTH_128
|| firstPulseWidth == ADC_PULSE_WIDTH_192);
ASSERT(
secondPulseWidth == ADC_PULSE_WIDTH_4
|| secondPulseWidth == ADC_PULSE_WIDTH_8
|| secondPulseWidth == ADC_PULSE_WIDTH_16
|| secondPulseWidth == ADC_PULSE_WIDTH_32
|| secondPulseWidth == ADC_PULSE_WIDTH_64
|| secondPulseWidth == ADC_PULSE_WIDTH_96
|| secondPulseWidth == ADC_PULSE_WIDTH_128
|| secondPulseWidth == ADC_PULSE_WIDTH_192);
if (ADCIsConversionRunning())
return false;
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14SHT0_M | ADC14SHT1_M)) | secondPulseWidth
| (firstPulseWidth >> 4);
return true;
}
bool ADC14_configureMultiSequenceMode(uint32_t memoryStart, uint32_t memoryEnd,
bool repeatMode)
{
uint32_t ii;
ASSERT(
_getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
&& _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
if (ADCIsConversionRunning())
return false;
/* Clearing out any lingering EOS */
for (ii = 0; ii < 32; ii++)
{
BITBAND_PERI(*(_ctlRegs[ii]), ADC14EOS_OFS) = 0;
}
/* Setting Start/Stop locations */
BITBAND_PERI(
(*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
ADC14EOS_OFS) = 1;
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
| (_getIndexForMemRegister(memoryStart) << 16);
/* Setting multiple sample mode */
if (!repeatMode)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_1);
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_3);
}
return true;
}
bool ADC14_configureSingleSampleMode(uint32_t memoryDestination,
bool repeatMode)
{
ASSERT(_getIndexForMemRegister(memoryDestination) != 32);
if (ADCIsConversionRunning())
return false;
/* Setting the destination register */
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
| (_getIndexForMemRegister(memoryDestination) << 16);
/* Setting single sample mode */
if (!repeatMode)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_0);
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_2);
}
return true;
}
bool ADC14_enableConversion(void)
{
if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
return false;
ADC14->rCTL0.r |= (ADC14ENC);
return true;
}
bool ADC14_toggleConversionTrigger(void)
{
if (!BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
return false;
if (BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS))
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 0;
} else
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 1;
}
return true;
}
void ADC14_disableConversion(void)
{
ADC14->rCTL0.r &= ~(ADC14SC | ADC14ENC);
}
bool ADC14_isBusy(void)
{
return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
}
bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
uint32_t channelSelect, bool differntialMode)
{
uint32_t currentReg, ii;
uint32_t *curReg;
/* Initialization */
ii = 1;
currentReg = 0x01;
if (ADCIsConversionRunning())
return false;
while (memorySelect != 0)
{
if (!(memorySelect & ii))
{
ii = ii << 1;
continue;
}
currentReg = memorySelect & ii;
memorySelect &= ~ii;
ii = ii << 1;
curReg = (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
if (differntialMode)
{
(*curReg) = ((*curReg)
& ~(ADC14VRSEL_M | ADC14INCH_M
| ADC14DIF))
| (channelSelect | refSelect | ADC14DIF);
} else
{
(*curReg) = ((*curReg)
& ~(ADC14VRSEL_M | ADC14INCH_M
| ADC14DIF)) | (channelSelect | refSelect);
}
}
return true;
}
bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect)
{
uint32_t currentReg, ii;
uint32_t *curRegPoint;
/* Initialization */
ii = 1;
currentReg = 0x01;
if (ADCIsConversionRunning())
return false;
while (memorySelect != 0)
{
if (!(memorySelect & ii))
{
ii = ii << 1;
continue;
}
currentReg = memorySelect & ii;
memorySelect &= ~ii;
ii = ii << 1;
curRegPoint =
(uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
if (windowSelect == ADC_COMP_WINDOW0)
{
(*curRegPoint) = ((*curRegPoint)
& ~(ADC14WINC | ADC14WINCTH))
| (ADC14WINC);
} else if (windowSelect == ADC_COMP_WINDOW1)
{
(*curRegPoint) |= ADC14WINC | ADC14WINCTH;
}
}
return true;
}
bool ADC14_disableComparatorWindow(uint32_t memorySelect)
{
uint32_t currentReg, ii;
/* Initialization */
ii = 1;
currentReg = 0x01;
if (ADCIsConversionRunning())
return false;
while (memorySelect != 0)
{
if (!(memorySelect & ii))
{
ii = ii << 1;
continue;
}
currentReg = memorySelect & ii;
memorySelect &= ~ii;
ii = ii << 1;
(*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &=
~ADC14WINC;
}
return true;
}
bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high)
{
if (ADCIsConversionRunning())
return false;
if (window == ADC_COMP_WINDOW0)
{
ADC14->rHI0.r = (high);
ADC14->rLO0.r = (low);
} else if (window == ADC_COMP_WINDOW1)
{
ADC14->rHI1.r = (high);
ADC14->rLO1.r = (low);
} else
{
ASSERT(false);
}
return true;
}
bool ADC14_setResultFormat(uint32_t resultFormat)
{
if (ADCIsConversionRunning())
return false;
if (resultFormat == ADC_UNSIGNED_BINARY)
{
BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 0;
} else if (resultFormat == ADC_SIGNED_BINARY)
{
BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 1;
} else
{
ASSERT(false);
}
return true;
}
uint_fast16_t ADC14_getResult(uint32_t memorySelect)
{
return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
+ 0x80));
}
void ADC14_getMultiSequenceResult(uint16_t* res)
{
uint32_t *startAddr, *curAddr;
uint32_t ii;
startAddr = (uint32_t*) _ctlRegs[(ADC14->rCTL1.r & ADC14CSTARTADD_M)
>> 16];
curAddr = startAddr;
for (ii = 0; ii < 32; ii++)
{
res[ii] = *(((uint16_t*) curAddr) + 0x80);
if (BITBAND_PERI((*curAddr), ADC14EOS_OFS))
break;
if (curAddr == _ctlRegs[31])
curAddr = (uint32_t*) _ctlRegs[0];
else
curAddr += 0x04;
}
}
void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
uint16_t* res)
{
uint32_t ii = 0;
uint32_t *firstPoint, *secondPoint;
bool foundEnd = false;
ASSERT(
_getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
&& _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
firstPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryStart)];
secondPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryEnd)];
while (!foundEnd)
{
if (firstPoint == secondPoint)
{
foundEnd = true;
}
res[ii] = *(((uint16_t*) firstPoint) + 0x80);
if (firstPoint == _ctlRegs[31])
firstPoint = (uint32_t*) _ctlRegs[0];
else
firstPoint += 0x04;
}
}
bool ADC14_enableReferenceBurst(void)
{
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 1;
return true;
}
bool ADC14_disableReferenceBurst(void)
{
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 0;
return true;
}
bool ADC14_setPowerMode(uint32_t adcPowerMode)
{
if (ADCIsConversionRunning())
return false;
switch (adcPowerMode)
{
case ADC_UNRESTRICTED_POWER_MODE:
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
| (ADC14PWRMD_0);
break;
case ADC_ULTRA_LOW_POWER_MODE:
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
| (ADC14PWRMD_2);
break;
default:
ASSERT(false);
return false;
}
return true;
}
void ADC14_enableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rIER0.r |= stat;
stat = (mask >> 32);
ADC14->rIER1.r |= (stat);
}
void ADC14_disableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rIER0.r &= ~stat;
stat = (mask >> 32);
ADC14->rIER1.r &= ~(stat);
}
uint_fast64_t ADC14_getInterruptStatus(void)
{
uint_fast64_t status = ADC14->rIFGR1.r;
return ((status << 32) | ADC14->rIFGR0.r);
}
uint_fast64_t ADC14_getEnabledInterruptStatus(void)
{
uint_fast64_t stat = ADC14->rIER1.r;
return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->rIER0.r);
}
void ADC14_clearInterruptFlag(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rCLRIFGR0.r |= stat;
stat = (mask >> 32);
ADC14->rCLRIFGR1.r |= (stat);
}
void ADC14_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(INT_ADC14, intHandler);
//
// Enable the ADC interrupt.
//
Interrupt_enableInterrupt(INT_ADC14);
}
void ADC14_unregisterInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(INT_ADC14);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(INT_ADC14);
}

1076
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
View File

File diff suppressed because it is too large Load Diff

355
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
Unescape Escape View File

@ -0,0 +1,355 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <aes256.h>
#include <interrupt.h>
#include <debug.h>
bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint_fast16_t keyLength)
{
uint8_t i;
uint16_t sCipherKey;
AES256_CMSIS(moduleInstance)->rCTL0.r |= 0;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
break;
default:
return false;
}
keyLength = keyLength / 8;
for (i = 0; i < keyLength; i = i + 2)
{
sCipherKey = (uint16_t) (cipherKey[i]);
sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = sCipherKey;
}
// Wait until key is written
while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS))
;
return true;
}
void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * encryptedData)
{
uint8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to encrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
}
// Key that is already written shall be used
// Encryption is initialized by setting AESKEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
*(encryptedData + i) = (uint8_t) tempData;
*(encryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
}
void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * decryptedData)
{
uint8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
*(decryptedData + i) = (uint8_t) tempData;
*(decryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
}
bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint_fast16_t keyLength)
{
uint8_t i;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r =
(AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
break;
default:
return false;
}
keyLength = keyLength / 8;
// Write cipher key to key register
for (i = 0; i < keyLength; i = i + 2)
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
}
// Wait until key is processed ~52 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
;
return true;
}
void AES256_clearInterruptFlag(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIFG_OFS) = 0;
}
uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESRDYIFG_OFS);
}
void AES256_enableInterrupt(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 1;
}
void AES256_disableInterrupt(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 0;
}
void AES256_reset(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESSWRST_OFS) = 1;
}
void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
{
uint8_t i;
uint16_t tempVariable = 0;
// Set module to encrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
}
// Key that is already written shall be used
// Encryption is initialized by setting AESKEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
}
void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data)
{
uint8_t i;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
}
bool AES256_startSetDecipherKey(uint32_t moduleInstance,
const uint8_t * cipherKey, uint_fast16_t keyLength)
{
uint8_t i;
uint16_t tempVariable = 0;
AES256_CMSIS(moduleInstance)->rCTL0.r =
(AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
break;
default:
return false;
}
keyLength = keyLength / 8;
// Write cipher key to key register
for (i = 0; i < keyLength; i = i + 2)
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
}
return true;
}
bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
{
uint8_t i;
uint16_t tempData = 0;
// If module is busy, exit and return failure
if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
return false;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
*(outputData + i) = (uint8_t) tempData;
*(outputData + i + 1) = (uint8_t) (tempData >> 8);
}
return true;
}
bool AES256_isBusy(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS);
}
void AES256_clearErrorFlag(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS) = 0;
}
uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS);
}
void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
Interrupt_registerInterrupt(INT_AES256, intHandler);
Interrupt_enableInterrupt(INT_AES256);
}
void AES256_unregisterInterrupt(uint32_t moduleInstance)
{
Interrupt_disableInterrupt(INT_AES256);
Interrupt_unregisterInterrupt(INT_AES256);
}
uint32_t AES256_getInterruptStatus(uint32_t moduleInstance)
{
return AES256_getInterruptFlagStatus(moduleInstance);
}

451
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
Unescape Escape View File

@ -0,0 +1,451 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef AES256_H_
#define AES256_H_
//*****************************************************************************
//
//! \addtogroup aes256_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
/* Module Defines and macro for easy access */
#define AES256_CMSIS(x) ((AES256_Type *) x)
//*****************************************************************************
//
// The following are deprecated values. Please refer to documentation for the
// correct values to use.
//
//*****************************************************************************
#define Key_128BIT 128
#define Key_192BIT 192
#define Key_256BIT 256
//*****************************************************************************
//
// The following are values that can be passed to the keyLength parameter for
// functions: AES256_setCipherKey(), AES256_setDecipherKey(), and
// AES256_startSetDecipherKey().
//
//*****************************************************************************
#define AES256_KEYLENGTH_128BIT 128
#define AES256_KEYLENGTH_192BIT 192
#define AES256_KEYLENGTH_256BIT 256
//*****************************************************************************
//
// The following are values that can be passed toThe following are values that
// can be returned by the AES256_getErrorFlagStatus() function.
//
//*****************************************************************************
#define AES256_ERROR_OCCURRED AESERRFG
#define AES256_NO_ERROR 0x00
//*****************************************************************************
//
// The following are values that can be passed toThe following are values that
// can be returned by the AES256_isBusy() function.
//
//*****************************************************************************
#define AES256_BUSY AESBUSY
#define AES256_NOT_BUSY 0x00
//*****************************************************************************
//
// The following are values that can be passed toThe following are values that
// can be returned by the AES256_getInterruptFlagStatus() function.
//
//*****************************************************************************
#define AES256_READY_INTERRUPT 0x01
#define AES256_NOTREADY_INTERRUPT 0x00
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Loads a 128, 192 or 256 bit cipher key to AES256 module.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
//! that contains a 128 bit cipher key.
//! \param keyLength is the length of the key.
//! Valid values are:
//! - \b AES256_KEYLENGTH_128BIT
//! - \b AES256_KEYLENGTH_192BIT
//! - \b AES256_KEYLENGTH_256BIT
//!
//! \return true if set correctly, false otherwise
//
//*****************************************************************************
extern bool AES256_setCipherKey(uint32_t moduleInstance,
const uint8_t *cipherKey, uint_fast16_t keyLength);
//*****************************************************************************
//
//! \brief Encrypts a block of data using the AES256 module.
//!
//! The cipher key that is used for encryption should be loaded in advance by
//! using function AES256_setCipherKey()
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
//! contains data to be encrypted.
//! \param encryptedData is a pointer to an uint8_t array with a length of 16
//! bytes in that the encrypted data will be written.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_encryptData(uint32_t moduleInstance, const uint8_t *data,
uint8_t *encryptedData);
//*****************************************************************************
//
//! \brief Decrypts a block of data using the AES256 module.
//!
//! This function requires a pregenerated decryption key. A key can be loaded
//! and pregenerated by using function AES256_setDecipherKey() or
//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
//! contains encrypted data to be decrypted.
//! \param decryptedData is a pointer to an uint8_t array with a length of 16
//! bytes in that the decrypted data will be written.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_decryptData(uint32_t moduleInstance, const uint8_t *data,
uint8_t *decryptedData);
//*****************************************************************************
//
//! \brief Sets the decipher key.
//!
//! The API AES256_startSetDecipherKey or AES256_setDecipherKey must be invoked
//! before invoking AES256_startDecryptData.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
//! that contains a 128 bit cipher key.
//! \param keyLength is the length of the key.
//! Valid values are:
//! - \b AES256_KEYLENGTH_128BIT
//! - \b AES256_KEYLENGTH_192BIT
//! - \b AES256_KEYLENGTH_256BIT
//!
//! \return true if set, false otherwise
//
//*****************************************************************************
extern bool AES256_setDecipherKey(uint32_t moduleInstance,
const uint8_t *cipherKey, uint_fast16_t keyLength);
//*****************************************************************************
//
//! \brief Clears the AES256 ready interrupt flag.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! Modified bits are \b AESRDYIFG of \b AESACTL0 register.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_clearInterruptFlag(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Gets the AES256 ready interrupt flag status.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! \return One of the following:
//! - \b AES256_READY_INTERRUPT
//! - \b AES256_NOTREADY_INTERRUPT
//! \n indicating the status of the AES256 ready status
//
//*****************************************************************************
extern uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Enables AES256 ready interrupt.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! Modified bits are \b AESRDYIE of \b AESACTL0 register.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_enableInterrupt(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Disables AES256 ready interrupt.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! Modified bits are \b AESRDYIE of \b AESACTL0 register.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_disableInterrupt(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Resets AES256 Module immediately.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! Modified bits are \b AESSWRST of \b AESACTL0 register.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_reset(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Starts an encryption process on the AES256 module.
//!
//! The cipher key that is used for decryption should be loaded in advance by
//! using function AES256_setCipherKey(). This is a non-blocking equivalent pf
//! AES256_encryptData(). It is recommended to use the interrupt functionality
//! to check for procedure completion then use the AES256_getDataOut() API to
//! retrieve the encrypted data.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
//! contains data to be encrypted.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_startEncryptData(uint32_t moduleInstance,
const uint8_t *data);
//*****************************************************************************
//
//! \brief Decypts a block of data using the AES256 module.
//!
//! This is the non-blocking equivalant of AES256_decryptData(). This function
//! requires a pregenerated decryption key. A key can be loaded and
//! pregenerated by using function AES256_setDecipherKey() or
//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. It is
//! recommended to use interrupt to check for procedure completion then use the
//! AES256_getDataOut() API to retrieve the decrypted data.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
//! contains encrypted data to be decrypted.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_startDecryptData(uint32_t moduleInstance,
const uint8_t *data);
//*****************************************************************************
//
//! \brief Sets the decipher key
//!
//! The API AES256_startSetDecipherKey() or AES256_setDecipherKey() must be
//! invoked before invoking AES256_startDecryptData.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
//! that contains a 128 bit cipher key.
//! \param keyLength is the length of the key.
//! Valid values are:
//! - \b AES256_KEYLENGTH_128BIT
//! - \b AES256_KEYLENGTH_192BIT
//! - \b AES256_KEYLENGTH_256BIT
//!
//! \return true if set correctly, false otherwise
//
//*****************************************************************************
extern bool AES256_startSetDecipherKey(uint32_t moduleInstance,
const uint8_t *cipherKey, uint_fast16_t keyLength);
//*****************************************************************************
//
//! \brief Reads back the output data from AES256 module.
//!
//! This function is meant to use after an encryption or decryption process
//! that was started and finished by initiating an interrupt by use of
//! AES256_startEncryptData or AES256_startDecryptData functions.
//!
//! \param moduleInstance is the base address of the AES256 module.
//! \param outputData is a pointer to an uint8_t array with a length of 16
//! bytes in that the data will be written.
//!
//! \return true if data is valid, otherwise false
//
//*****************************************************************************
extern bool AES256_getDataOut(uint32_t moduleInstance,
uint8_t *outputData);
//*****************************************************************************
//
//! \brief Gets the AES256 module busy status.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! \return true if busy, false otherwise
//
//*****************************************************************************
extern bool AES256_isBusy(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Clears the AES256 error flag.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! Modified bits are \b AESERRFG of \b AESACTL0 register.
//!
//! \return None
//
//*****************************************************************************
extern void AES256_clearErrorFlag(uint32_t moduleInstance);
//*****************************************************************************
//
//! \brief Gets the AES256 error flag status.
//!
//! \param moduleInstance is the base address of the AES256 module.
//!
//! \return One of the following:
//! - \b AES256_ERROR_OCCURRED
//! - \b AES256_NO_ERROR
//! \n indicating the error flag status
//
//*****************************************************************************
extern uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance);
//*****************************************************************************
//
//! Registers an interrupt handler for the AES interrupt.
//!
//! \param moduleInstance Instance of the AES256 module
//!
//! \param intHandler is a pointer to the function to be called when the
//! AES interrupt occurs.
//!
//! This function registers the handler to be called when a AES
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific AES interrupts must be enabled
//! via AES256_enableInterrupt(). It is the interrupt handler's responsibility
//! to clear the interrupt source via AES256_clearInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void AES256_registerInterrupt(uint32_t moduleInstance,
void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the AES interrupt
//!
//! \param moduleInstance Instance of the AES256 module
//!
//! This function unregisters the handler to be called when AES
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void AES256_unregisterInterrupt(uint32_t moduleInstance);
//*****************************************************************************
//
//! Returns the current interrupt flag for the peripheral.
//!
//! \param moduleInstance Instance of the AES256 module
//!
//! \return The currently triggered interrupt flag for the module.
//
//*****************************************************************************
extern uint32_t AES256_getInterruptStatus(uint32_t moduleInstance);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* AES256_H_ */

316
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
Unescape Escape View File

@ -0,0 +1,316 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <comp_e.h>
#include <interrupt.h>
#include <debug.h>
static uint16_t __getRegisterSettingForInput(uint32_t input)
{
switch (input)
{
case COMP_E_INPUT0:
return CEIPSEL_0;
case COMP_E_INPUT1:
return CEIPSEL_1;
case COMP_E_INPUT2:
return CEIPSEL_2;
case COMP_E_INPUT3:
return CEIPSEL_3;
case COMP_E_INPUT4:
return CEIPSEL_4;
case COMP_E_INPUT5:
return CEIPSEL_5;
case COMP_E_INPUT6:
return CEIPSEL_6;
case COMP_E_INPUT7:
return CEIPSEL_7;
case COMP_E_INPUT8:
return CEIPSEL_8;
case COMP_E_INPUT9:
return CEIPSEL_9;
case COMP_E_INPUT10:
return CEIPSEL_10;
case COMP_E_INPUT11:
return CEIPSEL_11;
case COMP_E_INPUT12:
return CEIPSEL_12;
case COMP_E_INPUT13:
return CEIPSEL_13;
case COMP_E_INPUT14:
return CEIPSEL_14;
case COMP_E_INPUT15:
return CEIPSEL_15;
case COMP_E_VREF:
return COMP_E_VREF;
default:
ASSERT(false);
return 0x11;
}
}
bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
{
uint_fast8_t positiveTerminalInput = __getRegisterSettingForInput(
config->positiveTerminalInput);
uint_fast8_t negativeTerminalInput = __getRegisterSettingForInput(
config->negativeTerminalInput);
bool retVal = true;
ASSERT(positiveTerminalInput < 0x10); ASSERT(negativeTerminalInput < 0x10);
ASSERT(positiveTerminalInput != negativeTerminalInput);
ASSERT(
config->outputFilterEnableAndDelayLevel
<= COMP_E_FILTEROUTPUT_DLYLVL4);
/* Reset COMPE Control 1 & Interrupt Registers for initialization */
COMP_E_CMSIS(comparator)->rCTL0.r = 0;
COMP_E_CMSIS(comparator)->rINT.r = 0;
// Set the Positive Terminal
if (COMP_E_VREF != positiveTerminalInput)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->rCTL0.r |= CEIPEN + positiveTerminalInput;
// Disable the input buffer
COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << positiveTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r,CERSEL_OFS) = 0;
}
// Set the Negative Terminal
if (COMP_E_VREF != negativeTerminalInput)
{
// Enable Negative Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->rCTL0.r |= CEIMEN
+ (negativeTerminalInput << 8);
// Disable the input buffer
COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << negativeTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CERSEL_OFS) = 1;
}
// Reset and Set COMPE Control 1 Register
COMP_E_CMSIS(comparator)->rCTL1.r = config->powerMode
+ config->outputFilterEnableAndDelayLevel
+ config->invertedOutputPolarity;
return retVal;
}
void COMP_E_setReferenceVoltage(uint32_t comparator,
uint_fast16_t supplyVoltageReferenceBase,
uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
uint_fast16_t upperLimitSupplyVoltageFractionOf32)
{
ASSERT(supplyVoltageReferenceBase <= COMP_E_VREFBASE2_5V);
ASSERT(upperLimitSupplyVoltageFractionOf32 <= 32);
ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32); ASSERT(
upperLimitSupplyVoltageFractionOf32
>= lowerLimitSupplyVoltageFractionOf32);
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEMRVS_OFS) = 0;
COMP_E_CMSIS(comparator)->rCTL2.r &= CERSEL;
// Set Voltage Source(Vcc | Vref, resistor ladder or not)
if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_1;
} else if (lowerLimitSupplyVoltageFractionOf32 == 32)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_3;
} else
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_2;
}
// Set COMPE Control 2 Register
COMP_E_CMSIS(comparator)->rCTL2.r |= supplyVoltageReferenceBase
+ ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+ (lowerLimitSupplyVoltageFractionOf32 - 1);
}
void COMP_E_setReferenceAccuracy(uint32_t comparator,
uint_fast16_t referenceAccuracy)
{
ASSERT(
(referenceAccuracy == COMP_E_ACCURACY_STATIC)
|| (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
if (referenceAccuracy)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 1;
else
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 0;
}
void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode)
{
COMP_E_CMSIS(comparator)->rCTL1.r = (COMP_E_CMSIS(comparator)->rCTL1.r
& ~(CEPWRMD_M)) | powerMode;
}
void COMP_E_enableModule(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 1;
}
void COMP_E_disableModule(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 0;
}
void COMP_E_shortInputs(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 1;
}
void COMP_E_unshortInputs(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 0;
}
void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
COMP_E_CMSIS(comparator)->rCTL3.r |= (inputPort);
}
void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
COMP_E_CMSIS(comparator)->rCTL3.r &= ~(inputPort);
}
void COMP_E_swapIO(uint32_t comparator)
{
COMP_E_CMSIS(comparator)->rCTL1.r ^= CEEX; // Toggle CEEX bit
}
uint8_t COMP_E_outputValue(uint32_t comparator)
{
return COMP_E_CMSIS(comparator)->rCTL1.r & CEOUT;
}
void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
// Set the Interrupt enable bit
COMP_E_CMSIS(comparator)->rINT.r |= mask;
}
uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator)
{
return COMP_E_getInterruptStatus(comparator) &
COMP_E_CMSIS(comparator)->rINT.r;
}
void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
}
void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask)
{
COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
}
uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator)
{
return (COMP_E_CMSIS(comparator)->rINT.r & (COMP_E_OUTPUT_INTERRUPT_FLAG |
COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY |
COMP_E_INTERRUPT_FLAG_READY));
}
void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
uint_fast8_t edgeDirection)
{
ASSERT(edgeDirection <= COMP_E_RISINGEDGE);
// Set the edge direction that will trigger an interrupt
if (COMP_E_RISINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 1;
else if (COMP_E_FALLINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 0;
}
void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)
{
COMP_E_CMSIS(comparator)->rCTL1.r ^= CEIES;
}
void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void))
{
switch (comparator)
{
case COMP_E0_MODULE:
Interrupt_registerInterrupt(INT_COMP_E0, intHandler);
Interrupt_enableInterrupt(INT_COMP_E0);
break;
case COMP_E1_MODULE:
Interrupt_registerInterrupt(INT_COMP_E1, intHandler);
Interrupt_enableInterrupt(INT_COMP_E1);
break;
default:
ASSERT(false);
}
}
void COMP_E_unregisterInterrupt(uint32_t comparator)
{
switch (comparator)
{
case COMP_E0_MODULE:
Interrupt_disableInterrupt(INT_COMP_E0);
Interrupt_unregisterInterrupt(INT_COMP_E0);
break;
case COMP_E1_MODULE:
Interrupt_disableInterrupt(INT_COMP_E1);
Interrupt_unregisterInterrupt(INT_COMP_E1);
break;
default:
ASSERT(false);
}
}

733
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
Unescape Escape View File

@ -0,0 +1,733 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef COMP_E_H_
#define COMP_E_H_
//*****************************************************************************
//
//! \addtogroup comp_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
/* Module defines for Comp */
#define COMP_E_CMSIS(x) ((COMP_E0_Type *) x)
#define COMP_E_FILTEROUTPUT_OFF 0x00
#define COMP_E_FILTEROUTPUT_DLYLVL1 (CEF + CEFDLY_0)
#define COMP_E_FILTEROUTPUT_DLYLVL2 (CEF + CEFDLY_1)
#define COMP_E_FILTEROUTPUT_DLYLVL3 (CEF + CEFDLY_2)
#define COMP_E_FILTEROUTPUT_DLYLVL4 (CEF + CEFDLY_3)
#define COMP_E_INPUT0 (0x01)
#define COMP_E_INPUT1 (0x02)
#define COMP_E_INPUT2 (0x04)
#define COMP_E_INPUT3 (0x08)
#define COMP_E_INPUT4 (0x10)
#define COMP_E_INPUT5 (0x20)
#define COMP_E_INPUT6 (0x40)
#define COMP_E_INPUT7 (0x80)
#define COMP_E_INPUT8 (0x100)
#define COMP_E_INPUT9 (0x200)
#define COMP_E_INPUT10 (0x400)
#define COMP_E_INPUT11 (0x800)
#define COMP_E_INPUT12 (0x1000)
#define COMP_E_INPUT13 (0x2000)
#define COMP_E_INPUT14 (0x4000)
#define COMP_E_INPUT15 (0x8000)
#define COMP_E_VREF (0x9F)
#define COMP_E_NORMALOUTPUTPOLARITY (!(CEOUTPOL))
#define COMP_E_INVERTEDOUTPUTPOLARITY (CEOUTPOL)
#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (CEREFL_0)
#define COMP_E_VREFBASE1_2V (CEREFL_1)
#define COMP_E_VREFBASE2_0V (CEREFL_2)
#define COMP_E_VREFBASE2_5V (CEREFL_3)
#define COMP_E_ACCURACY_STATIC (!CEREFACC)
#define COMP_E_ACCURACY_CLOCKED (CEREFACC)
#define COMP_E_HIGH_SPEED_MODE (CEPWRMD_0)
#define COMP_E_NORMAL_MODE (CEPWRMD_1)
#define COMP_E_ULTRA_LOW_POWER_MODE (CEPWRMD_2)
#define COMP_E_OUTPUT_INTERRUPT (CEIE)
#define COMP_E_INVERTED_POLARITY_INTERRUPT (CEIIE)
#define COMP_E_READY_INTERRUPT (CERDYIE)
#define COMP_E_OUTPUT_INTERRUPT_FLAG (CEIFG)
#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (CEIIFG)
#define COMP_E_INTERRUPT_FLAG_READY (CERDYIFG)
#define COMP_E_FALLINGEDGE (!(CEIES))
#define COMP_E_RISINGEDGE (CEIES)
#define COMP_E_LOW (0x0)
#define COMP_E_HIGH (CEOUT)
//*****************************************************************************
//
//! \typedef COMP_E_Config
//! \brief Type definition for \link _COMP_E_Config \endlink structure
//!
//! \struct _COMP_E_Config
//! \brief Configuration structure for Comparator module. See
//! \link COMP_E_initModule \endlink for parameter documentation.
//
//*****************************************************************************
typedef struct _COMP_E_Config
{
uint_fast16_t positiveTerminalInput;
uint_fast16_t negativeTerminalInput;
uint_fast8_t outputFilterEnableAndDelayLevel;
uint_fast8_t invertedOutputPolarity;
uint_fast16_t powerMode;
} COMP_E_Config;
//*****************************************************************************
//
//! Initializes the Comparator Module.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param config Configuration structure for the Comparator module
//!
//! <hr>
//! <b>Configuration options for \link COMP_E_Config \endlink structure.</b>
//! <hr>
//!
//! \param positiveTerminalInput selects the input to the positive terminal.
//! Valid values are
//! - \b COMP_E_INPUT0 [Default]
//! - \b COMP_E_INPUT1
//! - \b COMP_E_INPUT2
//! - \b COMP_E_INPUT3
//! - \b COMP_E_INPUT4
//! - \b COMP_E_INPUT5
//! - \b COMP_E_INPUT6
//! - \b COMP_E_INPUT7
//! - \b COMP_E_INPUT8
//! - \b COMP_E_INPUT9
//! - \b COMP_E_INPUT10
//! - \b COMP_E_INPUT11
//! - \b COMP_E_INPUT12
//! - \b COMP_E_INPUT13
//! - \b COMP_E_INPUT14
//! - \b COMP_E_INPUT15
//! - \b COMP_E_VREF
//! \n Modified bits are \b CEIPSEL and \b CEIPEN of \b CECTL0 register,
//! \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register.
//! \param negativeTerminalInput selects the input to the negative terminal.
//! \n Valid values are:
//! - \b COMP_E_INPUT0 [Default]
//! - \b COMP_E_INPUT1
//! - \b COMP_E_INPUT2
//! - \b COMP_E_INPUT3
//! - \b COMP_E_INPUT4
//! - \b COMP_E_INPUT5
//! - \b COMP_E_INPUT6
//! - \b COMP_E_INPUT7
//! - \b COMP_E_INPUT8
//! - \b COMP_E_INPUT9
//! - \b COMP_E_INPUT10
//! - \b COMP_E_INPUT11
//! - \b COMP_E_INPUT12
//! - \b COMP_E_INPUT13
//! - \b COMP_E_INPUT14
//! - \b COMP_E_INPUT15
//! - \b COMP_E_VREF
//! \n Modified bits are \b CEIMSEL and \b CEIMEN of \b CECTL0 register,
//! \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register.
//! \param outputFilterEnableAndDelayLevel controls the output filter delay
//! state, which is either off or enabled with a specified delay level.
//! \n Valid values are
//! - \b COMP_E_FILTEROUTPUT_OFF [Default]
//! - \b COMP_E_FILTEROUTPUT_DLYLVL1
//! - \b COMP_E_FILTEROUTPUT_DLYLVL2
//! - \b COMP_E_FILTEROUTPUT_DLYLVL3
//! - \b COMP_E_FILTEROUTPUT_DLYLVL4
//! \n This parameter is device specific and delay levels should be found
//! in the device's datasheet.
//! \n Modified bits are \b CEF and \b CEFDLY of \b CECTL1 register.
//! \param invertedOutputPolarity controls if the output will be inverted or
//! not. Valid values are
//! - \b COMP_E_NORMALOUTPUTPOLARITY - indicates the output should be
//! normal. [Default]
//! - \b COMP_E_INVERTEDOUTPUTPOLARITY - the output should be inverted.
//! \n Modified bits are \b CEOUTPOL of \b CECTL1 register.
//! \param powerMode controls the power mode of the module
//! - \b COMP_E_HIGH_SPEED_MODE [default]
//! - \b COMP_E_NORMAL_MODE
//! - \b COMP_E_ULTRA_LOW_POWER_MODE
//! Upon successful initialization of the Comparator module, this function will
//! have reset all necessary register bits and set the given options in the
//! registers. To actually use the comparator module, the COMP_E_enableModule()
//! function must be explicitly called before use.
//! If a Reference Voltage is set to a terminal, the Voltage should be set
//! using the COMP_E_setReferenceVoltage() function.
//!
//! \return true or false of the initialization process.
//
//*****************************************************************************
extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config);
//*****************************************************************************
//
//! Generates a Reference Voltage to the terminal selected during
//! initialization.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param supplyVoltageReferenceBase decides the source and max amount of
//! Voltage that can be used as a reference.
//! Valid values are
//! - \b COMP_E_REFERENCE_AMPLIFIER_DISABLED
//! - \b COMP_E_VREFBASE1_2V
//! - \b COMP_E_VREFBASE2_0V
//! - \b COMP_E_VREFBASE2_5V
//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the
//! equation to generate the reference voltage for the upper limit
//! reference voltage. Valid values are between 0 and 32.
//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the
//! equation to generate the reference voltage for the lower limit
//! reference voltage. Valid values are between 0 and 32.
//! <br>Modified bits are \b CEREF0 of \b CECTL2 register.
//!
//! Use this function to generate a voltage to serve as a reference to the
//! terminal selected at initialization. The voltage is determined by the
//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage
//! numerators are equal, then a static reference is defined, whereas they are
//! different then a hysteresis effect is generated.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_setReferenceVoltage(uint32_t comparator,
uint_fast16_t supplyVoltageReferenceBase,
uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
uint_fast16_t upperLimitSupplyVoltageFractionOf32);
//*****************************************************************************
//
//! Sets the reference accuracy
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param referenceAccuracy is the reference accuracy setting of the
//! comparator. Clocked is for low power/low accuracy.
//! Valid values are
//! - \b COMP_E_ACCURACY_STATIC
//! - \b COMP_E_ACCURACY_CLOCKED
//! <br>Modified bits are \b CEREFACC of \b CECTL2 register.
//!
//! The reference accuracy is set to the desired setting. Clocked is better for
//! low power operations but has a lower accuracy.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_setReferenceAccuracy(uint32_t comparator,
uint_fast16_t referenceAccuracy);
//*****************************************************************************
//
//! Sets the power mode
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param powerMode decides the power mode
//! Valid values are
//! - \b COMP_E_HIGH_SPEED_MODE
//! - \b COMP_E_NORMAL_MODE
//! - \b COMP_E_ULTRA_LOW_POWER_MODE
//! <br>Modified bits are \b CEPWRMD of \b CECTL1 register.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode);
//*****************************************************************************
//
//! Turns on the Comparator module.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function sets the bit that enables the operation of the
//! Comparator module.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_enableModule(uint32_t comparator);
//*****************************************************************************
//
//! Turns off the Comparator module.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function clears the CEON bit disabling the operation of the Comparator
//! module, saving from excess power consumption.
//!
//! Modified bits are \b CEON of \b CECTL1 register.
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_disableModule(uint32_t comparator);
//*****************************************************************************
//
//! Shorts the two input pins chosen during initialization.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function sets the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
//!
//! Modified bits are \b CESHORT of \b CECTL1 register.
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_shortInputs(uint32_t comparator);
//*****************************************************************************
//
//! Disables the short of the two input pins chosen during initialization.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function clears the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
//!
//! Modified bits are \b CESHORT of \b CECTL1 register.
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_unshortInputs(uint32_t comparator);
//*****************************************************************************
//
//! Disables the input buffer of the selected input port to effectively allow
//! for analog signals.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param inputPort is the port in which the input buffer will be disabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
//! - \b COMP_E_INPUT1
//! - \b COMP_E_INPUT2
//! - \b COMP_E_INPUT3
//! - \b COMP_E_INPUT4
//! - \b COMP_E_INPUT5
//! - \b COMP_E_INPUT6
//! - \b COMP_E_INPUT7
//! - \b COMP_E_INPUT8
//! - \b COMP_E_INPUT9
//! - \b COMP_E_INPUT10
//! - \b COMP_E_INPUT11
//! - \b COMP_E_INPUT12
//! - \b COMP_E_INPUT13
//! - \b COMP_E_INPUT14
//! - \b COMP_E_INPUT15
//! <br> Modified bits are \b CEPDx of \b CECTL3 register.
//!
//! This function sets the bit to disable the buffer for the specified input
//! port to allow for analog signals from any of the comparator input pins. This
//! bit is automatically set when the input is initialized to be used with the
//! comparator module. This function should be used whenever an analog input is
//! connected to one of these pins to prevent parasitic voltage from causing
//! unexpected results.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_disableInputBuffer(uint32_t comparator,
uint_fast16_t inputPort);
//*****************************************************************************
//
//! Enables the input buffer of the selected input port to allow for digital
//! signals.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param inputPort is the port in which the input buffer will be enabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
//! - \b COMP_E_INPUT1
//! - \b COMP_E_INPUT2
//! - \b COMP_E_INPUT3
//! - \b COMP_E_INPUT4
//! - \b COMP_E_INPUT5
//! - \b COMP_E_INPUT6
//! - \b COMP_E_INPUT7
//! - \b COMP_E_INPUT8
//! - \b COMP_E_INPUT9
//! - \b COMP_E_INPUT10
//! - \b COMP_E_INPUT11
//! - \b COMP_E_INPUT12
//! - \b COMP_E_INPUT13
//! - \b COMP_E_INPUT14
//! - \b COMP_E_INPUT15
//! <br> Modified bits are \b CEPDx of \b CECTL3 register.
//!
//! This function clears the bit to enable the buffer for the specified input
//! port to allow for digital signals from any of the comparator input pins.
//! This should not be reset if there is an analog signal connected to the
//! specified input pin to prevent from unexpected results.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_enableInputBuffer(uint32_t comparator,
uint_fast16_t inputPort);
//*****************************************************************************
//
//! Toggles the bit that swaps which terminals the inputs go to, while also
//! inverting the output of the comparator.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \ bCOMP_E0
//! - \ bCOMP_E1
//!
//! This function toggles the bit that controls which input goes to which
//! terminal. After initialization, this bit is set to 0, after toggling it once
//! the inputs are routed to the opposite terminal and the output is inverted.
//!
//! Modified bits are \b CEEX of \b CECTL1 register.
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_swapIO(uint32_t comparator);
//*****************************************************************************
//
//! Returns the output value of the Comparator module.
//!
//! \param comparator is the instance of the Comparator module. Valid parameters
//! vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! Returns the output value of the Comparator module.
//!
//! \return COMP_E_HIGH or COMP_E_LOW as the output value of the Comparator
//! module.
//
//*****************************************************************************
extern uint8_t COMP_E_outputValue(uint32_t comparator);
//*****************************************************************************
//
//! Enables selected Comparator interrupt sources.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param mask is the bit mask of the interrupt sources to be enabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted
//! polarity
//! - \b COMP_E_READY_INTERRUPT - Ready interrupt
//!
//! Enables the indicated Comparator interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor. The default trigger for the non-inverted
//! interrupt is a rising edge of the output, this can be changed with the
//! interruptSetEdgeDirection() function.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask);
//*****************************************************************************
//
//! Disables selected Comparator interrupt sources.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param mask is the bit mask of the interrupt sources to be disabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted
//! polarity
//! - \b COMP_E_READY_INTERRUPT - Ready interrupt
//!
//! Disables the indicated Comparator interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask);
//*****************************************************************************
//
//! Clears Comparator interrupt flags.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param mask is a bit mask of the interrupt sources to be cleared.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag
//! - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag
//! inverted polarity
//! - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag
//!
//! The Comparator interrupt source is cleared, so that it no longer asserts.
//! The highest interrupt flag is automatically cleared when an interrupt vector
//! generator is used.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask);
//*****************************************************************************
//
//! Gets the current Comparator interrupt status.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This returns the interrupt status for the Comparator module based on which
//! flag is passed.
//!
//! \return The current interrupt flag status for the corresponding mask.
//
//*****************************************************************************
extern uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator);
//*****************************************************************************
//
//! Enables selected Comparator interrupt sources masked with the enabled
//! interrupts. This function is useful to call in ISRs to get a list
//! of pending interrupts that are actually enabled and could have caused the
//! ISR.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! Enables the indicated Comparator interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor. The default trigger for the non-inverted
//! interrupt is a rising edge of the output, this can be changed with the
//! COMP_E_setInterruptEdgeDirection() function.
//!
//! \return NONE
//
//*****************************************************************************
extern uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator);
//*****************************************************************************
//
//! Explicitly sets the edge direction that would trigger an interrupt.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! \param edgeDirection determines which direction the edge would have to go
//! to generate an interrupt based on the non-inverted interrupt flag.
//! Valid values are
//! - \b COMP_E_FALLINGEDGE - sets the bit to generate an interrupt when
//! the output of the comparator falls from HIGH to LOW if the
//! normal interrupt bit is set(and LOW to HIGH if the inverted
//! interrupt enable bit is set). [Default]
//! - \b COMP_E_RISINGEDGE - sets the bit to generate an interrupt when the
//! output of the comparator rises from LOW to HIGH if the normal
//! interrupt bit is set(and HIGH to LOW if the inverted interrupt
//! enable bit is set).
//! <br>Modified bits are \b CEIES of \b CECTL1 register.
//!
//! This function will set which direction the output will have to go, whether
//! rising or falling, to generate an interrupt based on a non-inverted
//! interrupt.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
uint_fast8_t edgeDirection);
//*****************************************************************************
//
//! Toggles the edge direction that would trigger an interrupt.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function will toggle which direction the output will have to go,
//! whether rising or falling, to generate an interrupt based on a non-inverted
//! interrupt. If the direction was rising, it is now falling, if it was
//! falling, it is now rising.
//!
//! Modified bits are \b CEIES of \b CECTL1 register.
//!
//! \return NONE
//
//*****************************************************************************
extern void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator);
//*****************************************************************************
//
//! Registers an interrupt handler for the Comparator E interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the
//! Comparator interrupt occurs.
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function registers the handler to be called when a Comparator
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific Comparator interrupts must be enabled
//! via COMP_E_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via COMP_E_clearInterruptFlag().
//!
//! \return None.
//
//*****************************************************************************
extern void COMP_E_registerInterrupt(uint32_t comparator,
void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the Comparator E interrupt
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//!
//! This function unregisters the handler to be called when Comparator E
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void COMP_E_unregisterInterrupt(uint32_t comparator);
/* Backwards Compatibility Layer */
#define COMP_E_enable(a) COMP_E_enableModule(a)
#define COMP_E_disable(a) COMP_E_disableModule(a)
#define COMP_E_IOSwap(a) COMP_E_swapIO(a)
#define COMP_E_interruptToggleEdgeDirection(a) COMP_E_toggleInterruptEdgeDirection(a)
#define COMP_E_clearInterrupt(a,b) COMP_E_clearInterruptFlag(a,b)
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* COMP_E_H_ */

430
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
Unescape Escape View File

@ -0,0 +1,430 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <cpu.h>
#include <msp.h>
#include <stdint.h>
//*****************************************************************************
//
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
uint32_t __attribute__((naked)) CPU_cpsid(void)
{
uint32_t ret;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n"
: "=r" (ret));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ret);
}
#endif
#if defined(ewarm)
uint32_t CPU_cpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
__asm uint32_t CPU_cpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
mrs r0, PRIMASK;
cpsid i;
bx lr
}
#endif
#if defined(ccs)
uint32_t CPU_cpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function returning the state of PRIMASK (indicating whether
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(gcc)
uint32_t __attribute__((naked)) CPU_primask(void)
{
uint32_t ret;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n"
: "=r" (ret));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ret);
}
#endif
#if defined(ewarm)
uint32_t CPU_primask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
__asm uint32_t CPU_primask(void)
{
//
// Read PRIMASK and disable interrupts.
//
mrs r0, PRIMASK;
bx lr
}
#endif
#if defined(ccs)
uint32_t CPU_primask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
uint32_t __attribute__((naked)) CPU_cpsie(void)
{
uint32_t ret;
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" bx lr\n"
: "=r" (ret));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ret);
}
#endif
#if defined(ewarm)
uint32_t CPU_cpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
__asm uint32_t CPU_cpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
mrs r0, PRIMASK;
cpsie i;
bx lr
}
#endif
#if defined(ccs)
uint32_t CPU_cpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPUWFI instruction.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked)) CPU_wfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void CPU_wfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n");
}
#endif
#if defined(keil)
__asm void CPU_wfi(void)
{
//
// Wait for the next interrupt.
//
wfi;
bx lr
}
#endif
#if defined(ccs)
void CPU_wfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n");
}
#endif
//*****************************************************************************
//
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void CPU_basepriSet(uint32_t newBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n");
}
#endif
#if defined(keil)
__asm void CPU_basepriSet(uint32_t newBasepri)
{
//
// Set the BASEPRI register
//
msr BASEPRI, r0;
bx lr
}
#endif
#if defined(ccs)
void CPU_basepriSet(uint32_t newBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n");
}
#endif
//*****************************************************************************
//
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
uint32_t __attribute__((naked)) CPU_basepriGet(void)
{
uint32_t ret;
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n"
: "=r" (ret));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ret);
}
#endif
#if defined(ewarm)
uint32_t CPU_basepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
__asm uint32_t CPU_basepriGet(void)
{
//
// Read BASEPRI
//
mrs r0, BASEPRI;
bx lr
}
#endif
#if defined(ccs)
uint32_t CPU_basepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif

76
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
Unescape Escape View File

@ -0,0 +1,76 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __CPU_H__
#define __CPU_H__
#include <stdint.h>
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern uint32_t CPU_cpsid(void);
extern uint32_t CPU_cpsie(void);
extern uint32_t CPU_primask(void);
extern void CPU_wfi(void);
extern uint32_t CPU_basepriGet(void);
extern void CPU_basepriSet(uint32_t newBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__

144
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
Unescape Escape View File

@ -0,0 +1,144 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include "crc32.h"
#include <msp.h>
#include <debug.h>
void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16INIRES = seed;
else
{
CRC32->rCRC32INIRES_HI = ((seed & 0xFFFF0000) >> 16);
CRC32->rCRC32INIRES_LO = (seed & 0xFFFF);
}
}
void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
HWREG8(CRC32_BASE + OFS_CRC16DI) = dataIn;
else
HWREG8(CRC32_BASE + OFS_CRC32DI) = dataIn;
}
void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16DI = dataIn;
else
CRC32->rCRC32DI = dataIn;
}
void CRC32_set32BitData(uint32_t dataIn)
{
//CRC32->rCRC32DI = dataIn & 0xFFFF;
//CRC32->rCRC32DI = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
HWREG16(CRC32_BASE + OFS_CRC32DI) = dataIn & 0xFFFF;
HWREG16(CRC32_BASE + OFS_CRC32DI) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
}
void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
HWREG8(CRC32_BASE + OFS_CRC16DIRB) = dataIn;
else
HWREG8(CRC32_BASE + OFS_CRC32DIRB) = dataIn;
}
void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16DIRB = dataIn;
else
CRC32->rCRC32DIRB = dataIn;
}
void CRC32_set32BitDataReversed(uint32_t dataIn)
{
HWREG16(CRC32_BASE + OFS_CRC32DIRB) = dataIn & 0xFFFF;
HWREG16(CRC32_BASE + OFS_CRC32DIRB) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
//CRC32->rCRC32DIRB = dataIn & 0xFFFF;
//CRC32->rCRC32DIRB = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
}
uint32_t CRC32_getResult(uint_fast8_t crcType)
{
uint32_t result;
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
return CRC32->rCRC16INIRES;
else
{
result = CRC32->rCRC32INIRES_HI;
result = (result << 16);
result |= CRC32->rCRC32INIRES_LO;
return (result);
}
}
uint32_t CRC32_getResultReversed(uint_fast8_t crcType)
{
uint32_t result;
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
return CRC32->rCRC16RESR;
else
{
result = CRC32->rCRC32RESR_HI;
result = (result << 16);
result |= CRC32->rCRC32RESR_LO;
return (result);
}
}

235
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
Unescape Escape View File

@ -0,0 +1,235 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef _CRC_32_H
//*****************************************************************************
//
//! \addtogroup crc32_api
//! @{
//
//*****************************************************************************
#include <stdint.h>
#define CRC16_MODE 0x00
#define CRC32_MODE 0x01
//*****************************************************************************
//
//! Sets the seed for the CRC.
//!
//! \param seed is the seed for the CRC to start generating a signature from.
//! Modified bits are \b CRC16INIRESL0 of \b CRC16INIRESL0 register.
//! \b CRC32INIRESL0 of \b CRC32INIRESL0 register
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function sets the seed for the CRC to begin generating a signature with
//! the given seed and all passed data. Using this function resets the CRC32
//! signature.
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType);
//*****************************************************************************
//
//! Sets the 8 Bit data to add into the CRC module to generate a new signature.
//!
//! \param dataIn is the data to be added, through the CRC module, to the
//! signature.
//! Modified bits are \b CRC16DIB0 of \b CRC16DIB0 register.
//! \b CRC32DIB0 of \b CRC32DIB0 register.
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function sets the given data into the CRC module to generate the new
//! signature from the current signature and new data. Bit 0 is
//! treated as LSB.
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType);
//*****************************************************************************
//
//! Sets the 16 Bit data to add into the CRC module to generate a new signature.
//!
//! \param dataIn is the data to be added, through the CRC module, to the
//! signature.
//! Modified bits are \b CRC16DIW0 of \b CRC16DIW0 register.
//! \b CRC32DIW0 of \b CRC32DIW0 register.
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function sets the given data into the CRC module to generate the new
//! signature from the current signature and new data. Bit 0 is
//! treated as LSB
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType);
//*****************************************************************************
//
//! Sets the 32 Bit data to add into the CRC module to generate a new signature.
//! Available only for CRC32_MODE and not for CRC16_MODE
//! \param dataIn is the data to be added, through the CRC module, to the
//! signature.
//! Modified bits are \b CRC32DIL0 of \b CRC32DIL0 register.
//!
//! This function sets the given data into the CRC module to generate the new
//! signature from the current signature and new data. Bit 0 is
//! treated as LSB
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_set32BitData(uint32_t dataIn);
//*****************************************************************************
//
//! Translates the data by reversing the bits in each 8 bit data and then sets
//! this data to add into the CRC module to generate a new signature.
//!
//! \param dataIn is the data to be added, through the CRC module, to the
//! signature.
//! Modified bits are \b CRC16DIRBB0 of \b CRC16DIRBB0 register.
//! \b CRC32DIRBB0 of \b CRC32DIRBB0 register.
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function first reverses the bits in each byte of the data and then
//! generates the new signature from the current signature and new translated
//! data. Bit 0 is treated as MSB.
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType);
//*****************************************************************************
//
//! Translates the data by reversing the bits in each 16 bit data and then
//! sets this data to add into the CRC module to generate a new signature.
//!
//! \param dataIn is the data to be added, through the CRC module, to the
//! signature.
//! Modified bits are \b CRC16DIRBW0 of \b CRC16DIRBW0 register.
//! \b CRC32DIRBW0 of \b CRC32DIRBW0 register.
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function first reverses the bits in each byte of the data and then
//! generates the new signature from the current signature and new translated
//! data. Bit 0 is treated as MSB.
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType);
//*****************************************************************************
//
//! Translates the data by reversing the bits in each 32 Bit Data and then
//! sets this data to add into the CRC module to generate a new signature.
//! Available only for CRC32 mode and not for CRC16 mode
//! \param dataIn is the data to be added, through the CRC module, to the
//! signature.
//! Modified bits are \b CRC32DIRBL0 of \b CRC32DIRBL0 register.
//!
//! This function first reverses the bits in each byte of the data and then
//! generates the new signature from the current signature and new translated
//! data. Bit 0 is treated as MSB.
//!
//! \return NONE
//
//*****************************************************************************
extern void CRC32_set32BitDataReversed(uint32_t dataIn);
//*****************************************************************************
//
//! Returns the value of CRC Signature Result.
//!
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function returns the value of the signature result generated by the CRC.
//! Bit 0 is treated as LSB.
//! \return uint32_t Result
//
//*****************************************************************************
extern uint32_t CRC32_getResult(uint_fast8_t crcType);
//*****************************************************************************
//
//! Returns the bit-wise reversed format of the 32 bit Signature Result.
//!
//! \param crcType selects between CRC32 and CRC16
//! Valid values are \b CRC16_MODE and \b CRC32_MODE
//!
//! This function returns the bit-wise reversed format of the Signature Result.
//! Bit 0 is treated as MSB.
//!
//! \return uint32_t Result
//
//*****************************************************************************
extern uint32_t CRC32_getResultReversed(uint_fast8_t crcType);
/* Defines for future devices that might have multiple instances */
#define CRC32_setSeedMultipleInstance(a,b,c) CRC32_setSeed(b,c)
#define CRC32_set8BitDataMultipleInstance(a,b,c) CRC32_set8BitData(b,c)
#define CRC32_set16BitDataMultipleInstance(a,b,c) CRC32_set16BitData(b,c)
#define CRC32_set32BitDataMultipleInstance(a,b) CRC32_set32BitData(b)
#define CRC32_set8BitDataReversedMultipleInstance(a,b,c) CRC32_set8BitDataReversed(b,c)
#define CRC32_set16BitDataReversedMultipleInstance(a,b,c) CRC32_set16BitDataReversed(b,c)
#define CRC32_set32BitDataReversedMultipleInstance(a,b) CRC32_set32BitDataReversed(b)
#define CRC32_getResultMultipleInstance(a,b) CRC32_getResult()
#define CRC32_getResultReversedMultipleInstance(a,b) CRC32_getResultReversed(b)
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif

914
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
Unescape Escape View File

@ -0,0 +1,914 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <cs.h>
#include <debug.h>
#include <sysctl.h>
#include <interrupt.h>
/* Statics */
static uint32_t hfxtFreq;
static uint32_t lfxtFreq;
#ifdef DEBUG
bool _CSIsClockDividerValid(uint8_t divider)
{
return ((divider == CS_CLOCK_DIVIDER_1) || (divider == CS_CLOCK_DIVIDER_2)
|| (divider == CS_CLOCK_DIVIDER_4) || (divider == CS_CLOCK_DIVIDER_8)
|| (divider == CS_CLOCK_DIVIDER_16) || (divider == CS_CLOCK_DIVIDER_32)
|| (divider == CS_CLOCK_DIVIDER_64) || (divider == CS_CLOCK_DIVIDER_128));
}
#endif
static uint32_t _CSGetHFXTFrequency()
{
if (hfxtFreq >= CS_1MHZ && hfxtFreq <= CS_4MHZ)
return HFXTFREQ_0;
else if (hfxtFreq > CS_4MHZ && hfxtFreq <= CS_8MHZ)
return HFXTFREQ_1;
else if (hfxtFreq > CS_8MHZ && hfxtFreq <= CS_16MHZ)
return HFXTFREQ_2;
else if (hfxtFreq > CS_16MHZ && hfxtFreq <= CS_24MHZ)
return HFXTFREQ_3;
else if (hfxtFreq > CS_24MHZ && hfxtFreq <= CS_32MHZ)
return HFXTFREQ_4;
else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ)
return HFXTFREQ_5;
else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ)
return HFXTFREQ_5;
else
{
ASSERT(false);
return 0;
}
}
static uint32_t _CSGetDividerValue(uint32_t wDivider)
{
switch (wDivider)
{
case CS_CLOCK_DIVIDER_1:
return 1;
case CS_CLOCK_DIVIDER_2:
return 2;
case CS_CLOCK_DIVIDER_4:
return 4;
case CS_CLOCK_DIVIDER_8:
return 8;
case CS_CLOCK_DIVIDER_16:
return 16;
case CS_CLOCK_DIVIDER_32:
return 32;
case CS_CLOCK_DIVIDER_64:
return 64;
case CS_CLOCK_DIVIDER_128:
return 128;
default:
ASSERT(false);
return 1;
}
}
static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
{
uint8_t bDivider;
bDivider = _CSGetDividerValue(wDivider);
switch (wClockSource)
{
case CS_LFXTCLK_SELECT:
{
if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
{
CS_clearInterruptFlag(CS_LFXT_FAULT);
if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
{
if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
return (128000 / bDivider);
else
return (32000 / bDivider);
}
}
return lfxtFreq / bDivider;
}
case CS_HFXTCLK_SELECT:
{
if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
{
CS_clearInterruptFlag(CS_HFXT_FAULT);
if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
{
if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
return (128000 / bDivider);
else
return (32000 / bDivider);
}
}
return hfxtFreq / bDivider;
}
case CS_VLOCLK_SELECT:
return CS_VLOCLK_FREQUENCY / bDivider;
case CS_REFOCLK_SELECT:
{
if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
return (128000 / bDivider);
else
return (32000 / bDivider);
}
case CS_DCOCLK_SELECT:
return (CS_getDCOFrequency() / bDivider);
case CS_MODOSC_SELECT:
return CS_MODCLK_FREQUENCY / bDivider;
default:
ASSERT(false);
return 0;
}
}
//******************************************************************************
// Internal function for getting DCO nominal frequency
//******************************************************************************
static uint32_t _CSGetDOCFrequency(void)
{
uint32_t dcoFreq;
switch (CS->rCTL0.r & DCORSEL_M)
{
case DCORSEL_0:
dcoFreq = 1500000;
break;
case DCORSEL_1:
dcoFreq = 3000000;
break;
case DCORSEL_2:
dcoFreq = 6000000;
break;
case DCORSEL_3:
dcoFreq = 12000000;
break;
case DCORSEL_4:
dcoFreq = 24000000;
break;
case DCORSEL_5:
dcoFreq = 48000000;
break;
default:
dcoFreq = 0;
}
return (dcoFreq);
}
void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
uint32_t hfxt_XT_CLK_frequency)
{
hfxtFreq = hfxt_XT_CLK_frequency;
lfxtFreq = lfxt_XT_CLK_frequency;
}
void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
uint32_t clockSourceDivider)
{
ASSERT(_CSIsClockDividerValid(clockSourceDivider));
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
switch (selectedClockSignal)
{
case CS_ACLK:
{
/* Making sure that the clock signal for ACLK isn't set to anything
* invalid
*/
ASSERT(
(selectedClockSignal != CS_DCOCLK_SELECT)
&& (selectedClockSignal != CS_MODOSC_SELECT)
&& (selectedClockSignal != CS_HFXTCLK_SELECT));
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
;
/* Setting the divider and source */
CS->rCTL1.r = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
| (clockSource << CS_ACLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(SELA_M | DIVA_M));
/* Waiting for ACLK to be ready again */
while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
;
break;
}
case CS_MCLK:
{
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
;
CS->rCTL1.r = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
| (clockSource << CS_MCLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(SELM_M | DIVM_M));
/* Waiting for MCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
;
break;
}
case CS_SMCLK:
{
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
;
CS->rCTL1.r = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
| (clockSource << CS_HSMCLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(DIVS_M | SELS_M));
/* Waiting for SMCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
;
break;
}
case CS_HSMCLK:
{
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
;
CS->rCTL1.r = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
| (clockSource << CS_HSMCLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(DIVHS_M | SELS_M));
/* Waiting for HSMCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
;
break;
}
case CS_BCLK:
{
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
;
/* Setting the clock source and then returning
* (cannot divide CLK)
*/
if (clockSource == CS_LFXTCLK_SELECT)
BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 0;
else if (clockSource == CS_REFOCLK_SELECT)
BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 1;
else
ASSERT(false);
/* Waiting for BCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
;
break;
}
default:
{
/* Should never get here */
ASSERT(false);
}
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_startHFXT(bool bypassMode)
{
CS_startHFXTWithTimeout(bypassMode, 0);
}
void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
{
uint32_t wHFFreqRange;
uint8_t bNMIStatus;
bool boolTimeout;
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
SysCtl_disableNMISource(SYSCTL_CS_SRC);
/* Determining which frequency range to use */
wHFFreqRange = _CSGetHFXTFrequency();
boolTimeout = (timeout == 0) ? false : true;
/* Setting to maximum drive strength */
BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
CS->rCTL2.r = (CS->rCTL2.r & (~HFXTFREQ_M)) | (wHFFreqRange);
if (bypassMode)
{
BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 1;
} else
{
BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 0;
}
/* Starting and Waiting for frequency stabilization */
BITBAND_PERI(CS->rCTL2.r, HFXT_EN_OFS) = 1;
while (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
BITBAND_PERI(CS->rCLRIFG.r,CLR_HFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!bypassMode)
{
if (wHFFreqRange != HFXTFREQ_0)
BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
else
BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 0;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
}
void CS_startLFXT(uint32_t xtDrive)
{
CS_startLFXTWithTimeout(xtDrive, 0);
}
void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
{
uint8_t bNMIStatus;
bool boolBypassMode, boolTimeout;
ASSERT(lfxtFreq != 0)
ASSERT(
(xtDrive == CS_LFXT_DRIVE0) || (xtDrive == CS_LFXT_DRIVE1)
|| (xtDrive == CS_LFXT_DRIVE2)
|| (xtDrive == CS_LFXT_DRIVE3)
|| (xtDrive == CS_LFXT_BYPASS));
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
SysCtl_disableNMISource(SYSCTL_CS_SRC);
boolBypassMode = (xtDrive == CS_LFXT_BYPASS) ? true : false;
boolTimeout = (timeout == 0) ? false : true;
/* Setting to maximum drive strength */
if (boolBypassMode)
{
BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 1;
} else
{
CS->rCTL2.r |= (CS_LFXT_DRIVE3);
BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 0;
}
/* Waiting for frequency stabilization */
BITBAND_PERI(CS->rCTL2.r, LFXT_EN_OFS) = 1;
while (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
BITBAND_PERI(CS->rCLRIFG.r,CLR_LFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!boolBypassMode)
{
CS->rCTL2.r = ((CS->rCTL2.r & ~CS_LFXT_DRIVE3) | xtDrive);
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
}
void CS_enableClockRequest(uint32_t selectClock)
{
ASSERT(
selectClock == CS_ACLK || selectClock == CS_HSMCLK
|| selectClock == CS_SMCLK || selectClock == CS_MCLK);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->rCLKEN.r |= selectClock;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_disableClockRequest(uint32_t selectClock)
{
ASSERT(
selectClock == CS_ACLK || selectClock == CS_HSMCLK
|| selectClock == CS_SMCLK || selectClock == CS_MCLK);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->rCLKEN.r &= ~selectClock;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
{
ASSERT(
referenceFrequency == CS_REFO_32KHZ
|| referenceFrequency == CS_REFO_128KHZ);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS) = referenceFrequency;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_enableDCOExternalResistor(void)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 1;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData)
{
CS->rDCOERCAL.r = (uiCalData);
}
void CS_disableDCOExternalResistor(void)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 0;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_setDCOCenteredFrequency(uint32_t dcoFreq)
{
ASSERT(
dcoFreq == CS_DCO_FREQUENCY_1_5 || dcoFreq == CS_DCO_FREQUENCY_3
|| dcoFreq == CS_DCO_FREQUENCY_6
|| dcoFreq == CS_DCO_FREQUENCY_12
|| dcoFreq == CS_DCO_FREQUENCY_24
|| dcoFreq == CS_DCO_FREQUENCY_48);
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
/* Resetting Tuning Parameters and Setting the frequency */
CS->rCTL0.r = ((CS->rCTL0.r & ~DCORSEL_M) | dcoFreq);
/* Locking the CS Module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_tuneDCOFrequency(int16_t tuneParameter)
{
CS->rKEY.r = CS_KEY;
if (tuneParameter < 0)
{
CS->rCTL0.r = ((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M)
| 0x1000);
}
else
{
CS->rCTL0.r =
((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M));
}
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
uint32_t CS_getDCOFrequency(void)
{
float dcoConst;
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
dcoTune = CS->rCTL0.b.bDCOTUNE;
centeredFreq = _CSGetDOCFrequency();
if (dcoTune == 0)
return (uint32_t) centeredFreq;
/* Checking to see if we need to do signed conversion */
if (dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
/* DCORSEL = 5, in final silicon this will have a different calibration
value, but currently DCORSEL5 calibration is not populated
if (centeredFreq == 48000000)
{
External Resistor
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
calVal = TLV->rDCOER_FCAL_RSEL5;
}
Internal Resistor
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
calVal = TLV->rDCOIR_FCAL_RSEL5;
}
}
DCORSEL = 4
else
{*/
/* External Resistor */
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
calVal = TLV->rDCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
calVal = TLV->rDCOIR_FCAL_RSEL04;
}
/*}*/
return (uint32_t) ((centeredFreq)
/ (1
- ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal))))));
}
void CS_setDCOFrequency(uint32_t dcoFrequency)
{
int32_t nomFreq, calVal, dcoSigned;
int16_t dcoTune;
float dcoConst;
// bool rsel5 = false;
dcoSigned = (int32_t) dcoFrequency;
if (dcoFrequency < 2000000)
{
nomFreq = CS_15MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_1_5);
} else if (dcoFrequency < 4000000)
{
nomFreq = CS_3MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_3);
} else if (dcoFrequency < 8000000)
{
nomFreq = CS_6MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_6);
} else if (dcoFrequency < 16000000)
{
nomFreq = CS_12MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
} else if (dcoFrequency < 32000000)
{
nomFreq = CS_24MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_24);
} else if (dcoFrequency < 640000001)
{
nomFreq = CS_48MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
// rsel5 = true;
} else
{
ASSERT(false);
return;
}
if(dcoFrequency == nomFreq)
{
CS_tuneDCOFrequency(0);
return;
}
/* DCORSEL = 5, in final silicon this will have a different calibration
value, but currently DCORSEL5 calibration is not populated
if (rsel5)
{
External Resistor
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
calVal = TLV->rDCOER_FCAL_RSEL5;
}
Internal Resistor
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
calVal = TLV->rDCOIR_FCAL_RSEL5;
}
}
DCORSEL = 4
else
{*/
/* External Resistor */
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
calVal = TLV->rDCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
calVal = TLV->rDCOIR_FCAL_RSEL04;
}
/*}*/
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0 + dcoConst * (768.0 - calVal)) * 8.0)
/ (dcoSigned * dcoConst));
CS_tuneDCOFrequency(dcoTune);
}
uint32_t CS_getBCLK(void)
{
if (BITBAND_PERI(CS->rCTL1.r, SELB_OFS))
return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
else
return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
}
uint32_t CS_getHSMCLK(void)
{
uint32_t wSource, wDivider;
wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVHS_M) << CS_HSMCLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
uint32_t CS_getACLK(void)
{
uint32_t wSource, wDivider;
wSource = (CS->rCTL1.r & SELA_M) >> CS_ACLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVA_M) << CS_ACLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
uint32_t CS_getSMCLK(void)
{
uint32_t wDivider, wSource;
wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVS_M));
return _CSComputeCLKFrequency(wSource, wDivider);
}
uint32_t CS_getMCLK(void)
{
uint32_t wSource, wDivider;
wSource = (CS->rCTL1.r & SELM_M) << CS_MCLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVM_M) << CS_MCLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
void CS_enableFaultCounter(uint_fast8_t counterSelect)
{
ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 1;
} else
{
BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 1;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_disableFaultCounter(uint_fast8_t counterSelect)
{
ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 0;
} else
{
BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 0;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_resetFaultCounter(uint_fast8_t counterSelect)
{
ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
BITBAND_PERI(CS->rCTL3.r, RFCNTHF_OFS) = 1;
} else
{
BITBAND_PERI(CS->rCTL3.r, RFCNTLF_OFS) = 1;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue)
{
ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
counterSelect == CS_HFXT_FAULT_COUNTER);
ASSERT(countValue == CS_FAULT_COUNTER_4096_CYCLES ||
countValue == CS_FAULT_COUNTER_8192_CYCLES ||
countValue == CS_FAULT_COUNTER_16384_CYCLES ||
countValue == CS_FAULT_COUNTER_32768_CYCLES);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTHF_M) | (countValue << 4));
} else
{
CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTLF_M) | (countValue));
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_enableInterrupt(uint32_t flags)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->rIE.r |= flags;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_disableInterrupt(uint32_t flags)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->rIE.r &= ~flags;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
uint32_t CS_getInterruptStatus(void)
{
return CS->rIFG.r;
}
uint32_t CS_getEnabledInterruptStatus(void)
{
return CS_getInterruptStatus() & CS->rIE.r;
}
void CS_clearInterruptFlag(uint32_t flags)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->rCLRIFG.r |= flags;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
}
void CS_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(INT_CS, intHandler);
//
// Enable the system control interrupt.
//
Interrupt_enableInterrupt(INT_CS);
}
void CS_unregisterInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(INT_CS);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(INT_CS);
}

843
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
Unescape Escape View File

@ -0,0 +1,843 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __CS_H__
#define __CS_H__
//*****************************************************************************
//
//! \addtogroup cs_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define CS_CLOCK_DIVIDER_1 DIVS_0
#define CS_CLOCK_DIVIDER_2 DIVS_1
#define CS_CLOCK_DIVIDER_4 DIVS_2
#define CS_CLOCK_DIVIDER_8 DIVS_3
#define CS_CLOCK_DIVIDER_16 DIVS_4
#define CS_CLOCK_DIVIDER_32 DIVS_5
#define CS_CLOCK_DIVIDER_64 DIVS_6
#define CS_CLOCK_DIVIDER_128 DIVS_7
#define CS_LFXTCLK_SELECT SELM_0
#define CS_HFXTCLK_SELECT SELM_5
#define CS_VLOCLK_SELECT SELM_1
#define CS_REFOCLK_SELECT SELM_2
#define CS_DCOCLK_SELECT SELM_3
#define CS_MODOSC_SELECT SELM_4
#define CS_KEY 0x695A
/* Number of positions to shift for divider calculation */
#define CS_ACLK_DIV_BITPOS 0x04
#define CS_MCLK_DIV_BITPOS 0x0C
#define CS_SMCLK_DIV_BITPOS 0x00
#define CS_HSMCLK_DIV_BITPOS 0x08
/* Number of positions to shift for source calculation */
#define CS_ACLK_SRC_BITPOS 0x08
#define CS_MCLK_SRC_BITPOS 0x00
#define CS_SMCLK_SRC_BITPOS 0x04
#define CS_HSMCLK_SRC_BITPOS 0x04
/* REFO Clock Values */
#define CS_REFO_32KHZ 0x00
#define CS_REFO_128KHZ 0x01
/* Frequency Values */
#define CS_VLOCLK_FREQUENCY 10000
#define CS_MODCLK_FREQUENCY 24000000
/* Interrupts */
#define CS_LFXT_FAULT LFXTIE
#define CS_HFXT_FAULT HFXTIE
#define CS_DCOMIN_FAULT DCOMINIE
#define CS_DCOMAX_FAULT DCOMAXIE
#define CS_DCORESISTOR_FAULT DCORIE
#define CS_STARTCOUNT_LFXT_FAULT FCNTLFIE
#define CS_STARTCOUNT_HFXT_FAULT FCNTHFIE
#define CS_PLL_OUTOFLOCK PLLOOLIE
#define CS_PLL_OUTOFSIGNAL PLLLOSIE
#define CS_PLL_OUTOFRANGE PLLOORIE
#define CS_REFCNT_PERIOD_COUNTER CALIE
#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
#define CS_LFXT_DRIVE0 LFXTDRIVE_0
#define CS_LFXT_DRIVE1 LFXTDRIVE_1
#define CS_LFXT_DRIVE2 LFXTDRIVE_2
#define CS_LFXT_DRIVE3 LFXTDRIVE_3
#define CS_LFXT_BYPASS LFXTBYPASS
#define CS_ACLK ACLK_EN
#define CS_MCLK MCLK_EN
#define CS_SMCLK SMCLK_EN
#define CS_HSMCLK HSMCLK_EN
#define CS_BCLK BCLK_READY
#define CS_LFXTCLK 0x01
#define CS_1MHZ 1000000
#define CS_15MHZ 1500000
#define CS_3MHZ 3000000
#define CS_4MHZ 4000000
#define CS_6MHZ 6000000
#define CS_8MHZ 8000000
#define CS_12MHZ 12000000
#define CS_16MHZ 16000000
#define CS_24MHZ 24000000
#define CS_32MHZ 32000000
#define CS_40MHZ 40000000
#define CS_48MHZ 48000000
#define CS_DCO_FREQUENCY_1_5 DCORSEL_0
#define CS_DCO_FREQUENCY_3 DCORSEL_1
#define CS_DCO_FREQUENCY_6 DCORSEL_2
#define CS_DCO_FREQUENCY_12 DCORSEL_3
#define CS_DCO_FREQUENCY_24 DCORSEL_4
#define CS_DCO_FREQUENCY_48 DCORSEL_5
#define CS_HFXT_FAULT_COUNTER 0x01
#define CS_LFXT_FAULT_COUNTER 0x02
#define CS_FAULT_COUNTER_4096_CYCLES FCNTLF_0
#define CS_FAULT_COUNTER_8192_CYCLES FCNTLF_1
#define CS_FAULT_COUNTER_16384_CYCLES FCNTLF_2
#define CS_FAULT_COUNTER_32768_CYCLES FCNTLF_3
//******************************************************************************
//
//! This function sets the external clock sources LFXT and HFXT crystal
//! oscillator frequency values. This function must be called if an external
//! crystal LFXT or HFXT is used and the user intends to call
//! CS_getSMCLK, CS_getMCLK, CS_getBCLK, CS_getHSMCLK, CS_getACLK and
//! any of the HFXT oscillator control functions
//!
//! \param lfxt_XT_CLK_frequency is the LFXT crystal frequencies in Hz
//! \param hfxt_XT_CLK_frequency is the HFXT crystal frequencies in Hz
//!
//! \return None
//
//******************************************************************************
extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
uint32_t hfxt_XT_CLK_frequency);
//******************************************************************************
//
//! This function initializes each of the clock signals. The user must ensure
//! that this function is called for each clock signal. If not, the default
//! state is assumed for the particular clock signal. Refer to DriverLib
//! documentation for CS module or Device Family User's Guide for details of
//! default clock signal states.
//!
//! Note that this function is blocking and will wait on the appropriate bit
//! to be set in the CSSTAT READY register to be set before setting the clock
//! source
//!
//! HFXTCLK is not available for BCLK or ACLK.
//!
//! \param selectedClockSignal Clock signal to initialize.
//! - \b CS_ACLK,
//! - \b CS_MCLK,
//! - \b CS_HSMCLK
//! - \b CS_SMCLK
//! - \b CS_BCLK [clockSourceDivider is ignored for this parameter]
//! \param clockSource Clock source for the selectedClockSignal signal.
//! - \b CS_LFXTCLK_SELECT,
//! - \b CS_HFXTCLK_SELECT,
//! - \b CS_VLOCLK_SELECT, [Not available for BCLK]
//! - \b CS_DCOCLK_SELECT, [Not available for ACLK, BCLK]
//! - \b CS_REFOCLK_SELECT,
//! - \b CS_MODOSC_SELECT [Not available for ACLK, BCLK]
//! \param clockSourceDivider - selected the clock divider to calculate
//! clock signal from clock source. This parameter is ignored when
//! setting BLCK. Valid values are:
//! - \b CS_CLOCK_DIVIDER_1,
//! - \b CS_CLOCK_DIVIDER_2,
//! - \b CS_CLOCK_DIVIDER_4,
//! - \b CS_CLOCK_DIVIDER_8,
//! - \b CS_CLOCK_DIVIDER_16,
//! - \b CS_CLOCK_DIVIDER_32,
//! - \b CS_CLOCK_DIVIDER_64,
//! - \b CS_CLOCK_DIVIDER_128
//!
//! \return NONE
//
//******************************************************************************
extern void CS_initClockSignal(uint32_t selectedClockSignal,
uint32_t clockSource, uint32_t clockSourceDivider);
//******************************************************************************
//
//! Initializes the HFXT crystal oscillator, which supports crystal frequencies
//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops
//! until all oscillator fault flags are cleared, with no timeout. See the
//! device-specific data sheet for appropriate drive settings. NOTE: User must
//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
//! before calling this function.
//!
//! \param bypassMode When this variable is set, the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//!
//! \return NONE
//
//******************************************************************************
extern void CS_startHFXT(bool bypassMode);
//******************************************************************************
//
//! Initializes the HFXT crystal oscillator, which supports crystal frequencies
//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops
//! until all oscillator fault flags are cleared, with no timeout. See the
//! device-specific data sheet for appropriate drive settings. NOTE: User must
//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
//! before calling this function. This function has a timeout associated with
//! stabilizing the oscillator.
//!
//! \param bypassMode When this variable is set, the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
//! \return NONE
//
//******************************************************************************
extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
//******************************************************************************
//
//! Initializes the LFXT crystal oscillator, which supports crystal frequencies
//! up to 50kHz, depending on the selected drive strength. Loops
//! until all oscillator fault flags are cleared, with no timeout. See the
//! device-specific data sheet for appropriate drive settings. NOTE: User must
//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
//! before calling this function.
//!
//! \param xtDrive is the target drive strength for the LFXT crystal
//! oscillator.
//! Valid values are:
//! - \b CS_LFXT_DRIVE0,
//! - \b CS_LFXT_DRIVE1,
//! - \b CS_LFXT_DRIVE2,
//! - \b CS_LFXT_DRIVE3, [Default Value]
//! - \b CS_LFXT_BYPASS
//!
//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//!
//! \return NONE
//
//******************************************************************************
extern void CS_startLFXT(uint32_t xtDrive);
//******************************************************************************
//
//! Initializes the LFXT crystal oscillator, which supports crystal frequencies
//! up to 50kHz, depending on the selected drive strength. Loops
//! until all oscillator fault flags are cleared. See the
//! device-specific data sheet for appropriate drive settings. NOTE: User must
//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
//! before calling this function. This function has a timeout associated with
//! stabilizing the oscillator.
//!
//! \param xtDrive is the target drive strength for the LFXT crystal
//! oscillator.
//! Valid values are:
//! - \b CS_LFXT_DRIVE0,
//! - \b CS_LFXT_DRIVE1,
//! - \b CS_LFXT_DRIVE2,
//! - \b CS_LFXT_DRIVE3, [Default Value]
//! - \b CS_LFXT_BYPASS
//!
//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will
//! start in bypass mode and the signal can be generated by a digital square
//! wave.
//!
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
//! \return NONE
//
//******************************************************************************
extern void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
//******************************************************************************
//
//! Selects between the frequency of the internal REFO clock source
//!
//! \param referenceFrequency selects between the valid frequencies:
//! - \b CS_REFO_32KHZ,
//! - \b CS_REFO_128KHZ,
//!
//! \return NONE
//
//******************************************************************************
extern void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency);
//******************************************************************************
//
//! Enables conditional module requests
//!
//! \param selectClock selects specific request enables. Valid values are
//! are a logical OR of the following values:
//! - \b CS_ACLK,
//! - \b CS_HSMCLK,
//! - \b CS_SMCLK,
//! - \b CS_MCLK
//!
//! \return NONE
//
//******************************************************************************
extern void CS_enableClockRequest(uint32_t selectClock);
//******************************************************************************
//
//! Disables conditional module requests
//!
//! \param selectClock selects specific request disables. Valid values are
//! are a logical OR of the following values:
//! - \b CS_ACLK,
//! - \b CS_HSMCLK,
//! - \b CS_SMCLK,
//! - \b CS_MCLK
//!
//! \return NONE
//
//******************************************************************************
extern void CS_disableClockRequest(uint32_t selectClock);
//******************************************************************************
//
//! Get the current ACLK frequency.
//!
//! If a oscillator fault is set, the frequency returned will be based on the
//! fail safe mechanism of CS module. The user of this API must ensure that
//! \link CS_setExternalClockSourceFrequency() \endlink API was invoked before
//! in case LFXT is being used.
//!
//! \return Current ACLK frequency in Hz
//
//******************************************************************************
extern uint32_t CS_getACLK(void);
//******************************************************************************
//
//! Get the current SMCLK frequency.
//!
//! If a oscillator fault is set, the frequency returned will be based on the
//! fail safe mechanism of CS module. The user of this API must ensure that
//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or
//! HFXT is being used.
//!
//! \return Current SMCLK frequency in Hz
//
//******************************************************************************
extern uint32_t CS_getSMCLK(void);
//******************************************************************************
//
//! Get the current MCLK frequency.
//!
//! If a oscillator fault is set, the frequency returned will be based on the
//! fail safe mechanism of CS module. The user of this API must ensure that
//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or
//! HFXT is being used.
//!
//! \return Current MCLK frequency in Hz
//
//******************************************************************************
extern uint32_t CS_getMCLK(void);
//******************************************************************************
//
//! Get the current BCLK frequency.
//!
//! If a oscillator fault is set, the frequency returned will be based on the
//! fail safe mechanism of CS module. The user of this API must ensure that
//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in
//! case LFXT or HFXT is being used.
//!
//! \return Current BCLK frequency in Hz
//
//******************************************************************************
extern uint32_t CS_getBCLK(void);
//******************************************************************************
//
//! Get the current HSMCLK frequency.
//!
//! If a oscillator fault is set, the frequency returned will be based on the
//! fail safe mechanism of CS module. The user of this API must ensure that
//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in
//! case LFXT or HFXT is being used.
//!
//! \return Current HSMCLK frequency in Hz
//
//******************************************************************************
extern uint32_t CS_getHSMCLK(void);
//******************************************************************************
//
//! Sets the centered frequency of DCO operation. Each frequency represents
//! the centred frequency of a particular frequency range. Further tuning can
//! be achieved by using the CS_tuneDCOFrequency function. Note that setting
//! the nominal frequency will reset the tuning parameters.
//!
//! \param dcoFreq selects between the valid frequencies:
//! - \b CS_DCO_FREQUENCY_1_5, [1MHz to 2MHz]
//! - \b CS_DCO_FREQUENCY_3, [2MHz to 4MHz]
//! - \b CS_DCO_FREQUENCY_6, [4MHz to 8MHz]
//! - \b CS_DCO_FREQUENCY_12, [8MHz to 16MHz]
//! - \b CS_DCO_FREQUENCY_24, [16MHz to 32MHz]
//! - \b CS_DCO_FREQUENCY_48 [32MHz to 64MHz]
//!
//! \return NONE
//
//******************************************************************************
extern void CS_setDCOCenteredFrequency(uint32_t dcoFreq);
//******************************************************************************
//
//! Automatically sets/tunes the DCO to the given frequency. Any valid value
//! up to max frequency in the spec can be given to this function and the API
//! will do its best to determine the correct tuning parameter.
//!
//! \note The frequency ranges that can be custom tuned on early release MSP432
//! devices is limited. For further details on supported tunable frequencies,
//! please refer to the device errata sheet or data sheet.
//!
//! \param dcoFrequency Frequency in Hz that the user wants to set the DCO to.
//!
//! \note This function uses floating point math to calculate the DCO tuning
//! parameter. If efficiency is a concern, the user should use the
//! \link FPU_enableModule \endlink function (if available) to enable
//! the floating point co-processor.
//!
//! \return None
//
//******************************************************************************
extern void CS_setDCOFrequency(uint32_t dcoFrequency);
//******************************************************************************
//
//! Tunes the DCO to a specific frequency. Tuning of the DCO is based off of the
//! following equation in the user's guide:
//!
//! See the user's guide for more detailed information about DCO tuning.
//!
//! \note This function is not currently available on pre-release MSP432 devices.
//! On early release versions of MSP432, the DCO calibration information has not been
//! populated making the DCO only able to operate at the pre-calibrated centered
//! frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
//! function. While this function will be added on the final devices being released,
//! for early silicon please default to the pre-calibrated DCO center frequencies.
//!
//! \param tuneParameter Tuning parameter in 2's Compliment representation.
//! Can be negative or positive.
//!
//! \return NONE
//
//******************************************************************************
extern void CS_tuneDCOFrequency(int16_t tuneParameter);
//******************************************************************************
//
//! Enables the external resistor for DCO operation
//!
//! \return NONE
//
//******************************************************************************
extern void CS_enableDCOExternalResistor(void);
//******************************************************************************
//
//! Disables the external resistor for DCO operation
//!
//! \return NONE
//
//******************************************************************************
extern void CS_disableDCOExternalResistor(void);
//******************************************************************************
//
//! Sets the calibration value for the DCO when using the external resistor
//! mode. This value is used for tuning the DCO to custom frequencies. By
//! default, the value in the CS module is populated by the calibration
//! data of the suggested external resistor (see device datasheet).
//!
//! \param uiCalData is the calibration data constant for the external resistor.
//!
//! \return None
//
//******************************************************************************
extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData);
//******************************************************************************
//
//! Gets the current tuned DCO frequency. If no tuning has been done, this
//! returns the nominal DCO frequency of the current DCO range. Note that this
//! function will grab any constant/calibration data from the DDDS table
//! without any user interaction needed.
//!
//! \note This function uses floating point math to calculate the DCO tuning
//! parameter. If efficiency is a concern, the user should use the
//! \link FPU_enableModule \endlink function (if available) to enable
//! the floating point co-processor.
//!
//! \return Current DCO frequency in Hz
//
//******************************************************************************
extern uint32_t CS_getDCOFrequency(void);
//******************************************************************************
//
//! Automatically sets/tunes the DCO to the given frequency. Any valid value
//! up to (and including) 64Mhz can be given to this function and the API
//! will do its best to determine the correct tuning parameter.
//!
//!
//! \note This function is not currently available on pre-release MSP432 devices.
//! On early release versions of MSP432, the DCO calibration information has not been
//! populated making the DCO only able to operate at the pre-calibrated centered
//! frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
//! function. While this function will be added on the final devices being released,
//! for early silicon please default to the pre-calibrated DCO center frequencies.
//!
//! \param dcoFrequency Frequency in Hz (1500000 - 64000000) that the user wants
//! to set the DCO to.
//!
//! \note This function uses floating point math to calculate the DCO tuning
//! parameter. If efficiency is a concern, the user should use the
//! \link FPU_enableModule \endlink function (if available) to enable
//! the floating point co-processor.
//!
//! \return None
//
//******************************************************************************
extern void CS_setDCOFrequency(uint32_t dcoFrequency);
//******************************************************************************
//
//! Enables the fault counter for the CS module. This function can enable
//! either the HFXT fault counter or the LFXT fault counter.
//!
//! \param counterSelect selects the fault counter to enable
//! - \b CS_HFXT_FAULT_COUNTER
//! - \b CS_LFXT_FAULT_COUNTER
//!
//! \return NONE
//
//******************************************************************************
extern void CS_enableFaultCounter(uint_fast8_t counterSelect);
//******************************************************************************
//
//! Disables the fault counter for the CS module. This function can disable
//! either the HFXT fault counter or the LFXT fault counter.
//!
//! \param counterSelect selects the fault counter to disable
//! - \b CS_HFXT_FAULT_COUNTER
//! - \b CS_LFXT_FAULT_COUNTER
//!
//! \return NONE
//
//******************************************************************************
extern void CS_disableFaultCounter(uint_fast8_t counterSelect);
//******************************************************************************
//
//! Resets the fault counter for the CS module. This function can reset
//! either the HFXT fault counter or the LFXT fault counter.
//!
//! \param counterSelect selects the fault counter to reset
//! - \b CS_HFXT_FAULT_COUNTER
//! - \b CS_LFXT_FAULT_COUNTER
//!
//! \return NONE
//
//******************************************************************************
extern void CS_resetFaultCounter(uint_fast8_t counterSelect);
//******************************************************************************
//
//! Sets the count for the start value of the fault counter. This function can
//! be used to set either the HFXT count or the LFXT count.
//!
//! \param counterSelect selects the fault counter to reset
//! - \b CS_HFXT_FAULT_COUNTER
//! - \b CS_LFXT_FAULT_COUNTER
//! \param countValue selects the cycles to set the fault counter to
//! - \b CS_FAULT_COUNTER_4096_CYCLES
//! - \b CS_FAULT_COUNTER_8192_CYCLES
//! - \b CS_FAULT_COUNTER_16384_CYCLES
//! - \b CS_FAULT_COUNTER_32768_CYCLES
//!
//! \return NONE
//
//******************************************************************************
extern void CS_startFaultCounter(uint_fast8_t counterSelect,
uint_fast8_t countValue);
//*****************************************************************************
//
//! Enables individual clock control interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be enabled. Must
//! be a logical OR of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! This function enables the indicated clock system interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void CS_enableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Disables individual clock system interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be disabled. Must
//! be a logical OR of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void CS_disableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Gets the current interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list of pending interrupts
//! that are actually enabled and could have caused the ISR.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t CS_getEnabledInterruptStatus(void);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t CS_getInterruptStatus(void);
//*****************************************************************************
//
//! Clears clock system interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be cleared. Must
//! be a logical OR of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! The specified clock system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep it from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void CS_clearInterruptFlag(uint32_t flags);
//*****************************************************************************
//
//! Registers an interrupt handler for the clock system interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the clock
//! system interrupt occurs.
//!
//! This function registers the handler to be called when a clock system
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific clock system interrupts must be enabled
//! via CS_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via CS_clearInterruptFlag().
//!
//! Clock System can generate interrupts when
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void CS_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the clock system.
//!
//! This function unregisters the handler to be called when a clock system
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void CS_unregisterInterrupt(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif

76
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
Unescape Escape View File

@ -0,0 +1,76 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long line);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#ifdef DEBUG
#define assert(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define assert(expr)
#endif
#endif // __DEBUG_H__

850
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
Unescape Escape View File

@ -0,0 +1,850 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <stdint.h>
#include <debug.h>
#include <interrupt.h>
#include <dma.h>
void DMA_enableModule(void)
{
//
// Set the master enable bit in the config register.
//
DMA->rCFG.r = DMA_CFG_;
}
void DMA_disableModule(void)
{
//
// Clear the master enable bit in the config register.
//
DMA->rCFG.r = 0;
}
uint32_t DMA_getErrorStatus(void)
{
//
// Return the DMA error status.
//
return DMA->rERRCLR.r;
}
void DMA_clearErrorStatus(void)
{
//
// Clear the DMA error interrupt.
//
DMA->rERRCLR.r = 1;
}
void DMA_enableChannel(uint32_t channelNum)
{
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
//
// Set the bit for this channel in the enable set register.
//
DMA->rENASET = 1 << (channelNum & 0x0F);
}
void DMA_disableChannel(uint32_t channelNum)
{
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
//
// Set the bit for this channel in the enable clear register.
//
DMA->rENACLR = 1 << (channelNum & 0x0F);
}
bool DMA_isChannelEnabled(uint32_t channelNum)
{
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
//
// AND the specified channel bit with the enable register and return the
// result.
//
return ((DMA->rENASET & (1 << (channelNum & 0x0F))) ? true : false);
}
void DMA_setControlBase(void *controlTable)
{
//
// Check the arguments.
//
ASSERT(((uint32_t) controlTable & ~0x3FF) == (uint32_t) controlTable);
ASSERT((uint32_t) controlTable >= 0x20000000);
//
// Program the base address into the register.
//
DMA->rCTLBASE.r = (uint32_t) controlTable;
}
void* DMA_getControlBase(void)
{
//
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA->rCTLBASE.r);
}
void* DMA_getControlAlternateBase(void)
{
//
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA->rATLBASE);
}
void DMA_requestChannel(uint32_t channelNum)
{
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
//
// Set the bit for this channel in the software DMA request register.
//
DMA->rSWREQ = 1 << (channelNum & 0x0F);
}
void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
{
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
ASSERT(
(attr
& ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
| UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
== 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelNum parameter, extract just the channel number
// from this parameter.
//
channelNum &= 0x0F;
//
// Set the useburst bit for this channel if set in config.
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA->rUSEBURSTSET = 1 << channelNum;
}
//
// Set the alternate control select bit for this channel,
// if set in config.
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA->rALTSET = 1 << channelNum;
}
//
// Set the high priority bit for this channel, if set in config.
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA->rPRIOSET = 1 << channelNum;
}
//
// Set the request mask bit for this channel, if set in config.
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA->rREQMASKSET = 1 << channelNum;
}
}
void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
{
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
ASSERT(
(attr
& ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
| UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
== 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelNum parameter, extract just the channel number
// from this parameter.
//
channelNum &= 0x0F;
//
// Clear the useburst bit for this channel if set in config.
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA->rUSEBURSTCLR = 1 << channelNum;
}
//
// Clear the alternate control select bit for this channel, if set in
// config.
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA->rALTCLR = 1 << channelNum;
}
//
// Clear the high priority bit for this channel, if set in config.
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA->rPRIOCLR = 1 << channelNum;
}
//
// Clear the request mask bit for this channel, if set in config.
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA->rREQMASKCLR = 1 << channelNum;
}
}
uint32_t DMA_getChannelAttribute(uint32_t channelNum)
{
uint32_t attr = 0;
//
// Check the arguments.
//
ASSERT((channelNum & 0xffff) < 8);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelNum parameter, extract just the channel number
// from this parameter.
//
channelNum &= 0x0F;
//
// Check to see if useburst bit is set for this channel.
//
if (DMA->rUSEBURSTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_USEBURST;
}
//
// Check to see if the alternate control bit is set for this channel.
//
if (DMA->rALTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_ALTSELECT;
}
//
// Check to see if the high priority bit is set for this channel.
//
if (DMA->rPRIOSET & (1 << channelNum))
{
attr |= UDMA_ATTR_HIGH_PRIORITY;
}
//
// Check to see if the request mask bit is set for this channel.
//
if (DMA->rREQMASKSET & (1 << channelNum))
{
attr |= UDMA_ATTR_REQMASK;
}
//
// Return the configuration flags.
//
return (attr);
}
void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
{
DMA_ControlTable *pCtl;
//
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelStructIndex parameter, extract just the channel
// index from this parameter.
//
channelStructIndex &= 0x3f;
//
// Get the base address of the control table.
//
pCtl = (DMA_ControlTable *) DMA->rCTLBASE.r;
//
// Get the current control word value and mask off the fields to be
// changed, then OR in the new settings.
//
pCtl[channelStructIndex].control = ((pCtl[channelStructIndex].control
& ~(UDMA_CHCTL_DSTINC_M | UDMA_CHCTL_DSTSIZE_M | UDMA_CHCTL_SRCINC_M
| UDMA_CHCTL_SRCSIZE_M | UDMA_CHCTL_ARBSIZE_M
| UDMA_CHCTL_NXTUSEBURST)) | control);
}
void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
void *srcAddr, void *dstAddr, uint32_t transferSize)
{
DMA_ControlTable *controlTable;
uint32_t control;
uint32_t increment;
uint32_t bufferBytes;
//
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
ASSERT((transferSize != 0) && (transferSize <= 1024));
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelStructIndex parameter, extract just the channel
// index from this parameter.
//
channelStructIndex &= 0x3f;
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
//
// Get the current control word value and mask off the mode and size
// fields.
//
control = (controlTable[channelStructIndex].control
& ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
//
// Adjust the mode if the alt control structure is selected.
//
if (channelStructIndex & UDMA_ALT_SELECT)
{
if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
|| (mode == UDMA_MODE_PER_SCATTER_GATHER))
{
mode |= UDMA_MODE_ALT_SELECT;
}
}
//
// Set the transfer size and mode in the control word (but don't write the
// control word yet as it could kick off a transfer).
//
control |= mode | ((transferSize - 1) << 4);
//
// Get the address increment value for the source, from the control word.
//
increment = (control & UDMA_CHCTL_SRCINC_M);
//
// Compute the ending source address of the transfer. If the source
// increment is set to none, then the ending address is the same as the
// beginning.
//
if (increment != UDMA_SRC_INC_NONE)
{
increment = increment >> 26;
bufferBytes = transferSize << increment;
srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes - 1);
}
//
// Load the source ending address into the control block.
//
controlTable[channelStructIndex].srcEndAddr = srcAddr;
//
// Get the address increment value for the destination, from the control
// word.
//
increment = control & UDMA_CHCTL_DSTINC_M;
//
// Compute the ending destination address of the transfer. If the
// destination increment is set to none, then the ending address is the
// same as the beginning.
//
if (increment != UDMA_DST_INC_NONE)
{
//
// There is a special case if this is setting up a scatter-gather
// transfer. The destination pointer must point to the end of
// the alternate structure for this channel instead of calculating
// the end of the buffer in the normal way.
//
if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
|| (mode == UDMA_MODE_PER_SCATTER_GATHER))
{
dstAddr = (void *) &controlTable[channelStructIndex
| UDMA_ALT_SELECT].spare;
}
//
// Not a scatter-gather transfer, calculate end pointer normally.
//
else
{
increment = increment >> 30;
bufferBytes = transferSize << increment;
dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes - 1);
}
}
//
// Load the destination ending address into the control block.
//
controlTable[channelStructIndex].dstEndAddr = dstAddr;
//
// Write the new control word value.
//
controlTable[channelStructIndex].control = control;
}
void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
void *taskList, uint32_t isPeriphSG)
{
DMA_ControlTable *controlTable;
DMA_ControlTable *pTaskTable;
//
// Check the parameters
//
ASSERT((channelNum & 0xffff) < 8);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(taskList != 0);
ASSERT(taskCount <= 1024);
ASSERT(taskCount != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelNum parameter, extract just the channel number
// from this parameter.
//
channelNum &= 0x0F;
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
//
// Get a handy pointer to the task list
//
pTaskTable = (DMA_ControlTable *) taskList;
//
// Compute the ending address for the source pointer. This address is the
// last element of the last task in the task table
//
controlTable[channelNum].srcEndAddr = &pTaskTable[taskCount - 1].spare;
//
// Compute the ending address for the destination pointer. This address
// is the end of the alternate structure for this channel.
//
controlTable[channelNum].dstEndAddr = &controlTable[channelNum
| UDMA_ALT_SELECT].spare;
//
// Compute the control word. Most configurable items are fixed for
// scatter-gather. Item and increment sizes are all 32-bit and arb
// size must be 4. The count is the number of items in the task list
// times 4 (4 words per task).
//
controlTable[channelNum].control = (UDMA_CHCTL_DSTINC_32
| UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_SRCINC_32
| UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_ARBSIZE_4
| (((taskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S)
| (isPeriphSG ?
UDMA_CHCTL_XFERMODE_PER_SG :
UDMA_CHCTL_XFERMODE_MEM_SG));
//
// Scatter-gather operations can leave the alt bit set. So if doing
// back to back scatter-gather transfers, the second attempt may not
// work correctly because the alt bit is set. Therefore, clear the
// alt bit here to ensure that it is always cleared before a new SG
// transfer is started.
//
DMA->rALTCLR = 1 << channelNum;
}
uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
{
DMA_ControlTable *controlTable;
uint32_t control;
//
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 16);
ASSERT(DMA->rCTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelStructIndex parameter, extract just the channel
// index from this parameter.
//
channelStructIndex &= 0x3f;
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
//
// Get the current control word value and mask off all but the size field
// and the mode field.
//
control = (controlTable[channelStructIndex].control
& (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
//
// If the size field and mode field are 0 then the transfer is finished
// and there are no more items to transfer
//
if (control == 0)
{
return (0);
}
//
// Otherwise, if either the size field or more field is non-zero, then
// not all the items have been transferred.
//
else
{
//
// Shift the size field and add one, then return to user.
//
return ((control >> 4) + 1);
}
}
uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
{
DMA_ControlTable *controlTable;
uint32_t control;
//
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
// passed as the channelStructIndex parameter, extract just the channel
// index from this parameter.
//
channelStructIndex &= 0x3f;
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
//
// Get the current control word value and mask off all but the mode field.
//
control =
(controlTable[channelStructIndex].control & UDMA_CHCTL_XFERMODE_M);
//
// Check if scatter/gather mode, and if so, mask off the alt bit.
//
if (((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER)
|| ((control & ~UDMA_MODE_ALT_SELECT)
== UDMA_MODE_PER_SCATTER_GATHER))
{
control &= ~UDMA_MODE_ALT_SELECT;
}
//
// Return the mode to the caller.
//
return (control);
}
void DMA_assignChannel(uint32_t mapping)
{
switch (mapping)
{
case DMA_CH0_RESERVED0:
case DMA_CH0_EUSCIA0TX:
case DMA_CH0_EUSCIB0TX0:
case DMA_CH0_EUSCIB3TX1:
case DMA_CH0_EUSCIB2TX2:
case DMA_CH0_EUSCIB1TX3:
case DMA_CH0_TIMERA0CCR0:
case DMA_CH0_AESTRIGGER0:
DMA->rCH0_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH1_RESERVED0:
case DMA_CH1_EUSCIA0RX:
case DMA_CH1_EUSCIB0RX0:
case DMA_CH1_EUSCIB3RX1:
case DMA_CH1_EUSCIB2RX2:
case DMA_CH1_EUSCIB1RX3:
case DMA_CH1_TIMERA0CCR2:
case DMA_CH1_AESTRIGGER1:
DMA->rCH1_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH2_RESERVED0:
case DMA_CH2_EUSCIA1TX:
case DMA_CH2_EUSCIB1TX0:
case DMA_CH2_EUSCIB0TX1:
case DMA_CH2_EUSCIB3TX2:
case DMA_CH2_EUSCIB2TX3:
case DMA_CH2_TIMERA1CCR0:
case DMA_CH2_AESTRIGGER2:
DMA->rCH2_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH3_RESERVED0:
case DMA_CH3_EUSCIA1RX:
case DMA_CH3_EUSCIB1RX0:
case DMA_CH3_EUSCIB0RX1:
case DMA_CH3_EUSCIB3RX2:
case DMA_CH3_EUSCIB2RX3:
case DMA_CH3_TIMERA1CCR2:
case DMA_CH3_RESERVED1:
DMA->rCH3_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH4_RESERVED0:
case DMA_CH4_EUSCIA2TX:
case DMA_CH4_EUSCIB2TX0:
case DMA_CH4_EUSCIB1TX1:
case DMA_CH4_EUSCIB0TX2:
case DMA_CH4_EUSCIB3TX3:
case DMA_CH4_TIMERA2CCR0:
case DMA_CH4_RESERVED1:
DMA->rCH4_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH5_RESERVED0:
case DMA_CH5_EUSCIA2RX:
case DMA_CH5_EUSCIB2RX0:
case DMA_CH5_EUSCIB1RX1:
case DMA_CH5_EUSCIB0RX2:
case DMA_CH5_EUSCIB3RX3:
case DMA_CH5_TIMERA2CCR2:
case DMA_CH5_RESERVED1:
DMA->rCH5_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH6_RESERVED0:
case DMA_CH6_EUSCIA3TX:
case DMA_CH6_EUSCIB3TX0:
case DMA_CH6_EUSCIB2TX1:
case DMA_CH6_EUSCIB1TX2:
case DMA_CH6_EUSCIB0TX3:
case DMA_CH6_TIMERA3CCR0:
case DMA_CH6_EXTERNALPIN:
DMA->rCH6_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
case DMA_CH7_RESERVED0:
case DMA_CH7_EUSCIA3RX:
case DMA_CH7_EUSCIB3RX0:
case DMA_CH7_EUSCIB2RX1:
case DMA_CH7_EUSCIB1RX2:
case DMA_CH7_EUSCIB0RX3:
case DMA_CH7_TIMERA3CCR2:
case DMA_CH7_ADC12C:
DMA->rCH7_SRCCFG.r = (mapping >> 24) & 0x1F;
break;
default:
ASSERT(false);
}
}
void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
{
ASSERT(
interruptNumber == DMA_INT1 || interruptNumber == DMA_INT2
|| interruptNumber == DMA_INT3);
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r = (DMA->rINT1_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r = (DMA->rINT2_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r = (DMA->rINT3_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
}
/* Enabling the assigned interrupt */
DMA_enableInterrupt(interruptNumber);
}
void DMA_requestSoftwareTransfer(uint32_t channel)
{
DMA->rSW_CHTRIG.r |= (1 << channel);
}
uint32_t DMA_getInterruptStatus(void)
{
return DMA->rINT0_SRCFLG.r;
}
void DMA_clearInterruptFlag(uint32_t channel)
{
DMA->rINT0_CLRFLG.r |= (1 << channel);
}
void DMA_enableInterrupt(uint32_t interruptNumber)
{
ASSERT(
(interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
|| (interruptNumber == DMA_INT2)
|| (interruptNumber == DMA_INT3));
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r |= DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r |= DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r |= DMA_INT3_SRCCFG_EN;
}
}
void DMA_disableInterrupt(uint32_t interruptNumber)
{
ASSERT(
(interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
|| (interruptNumber == DMA_INT2)
|| (interruptNumber == DMA_INT3));
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r &= ~DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r &= ~DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r &= ~DMA_INT3_SRCCFG_EN;
}
}
void DMA_registerInterrupt(uint32_t interruptNumber, void (*intHandler)(void))
{
//
// Check the arguments.
//
ASSERT(intHandler);
ASSERT(
(interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
|| (interruptNumber == DMA_INT2)
|| (interruptNumber == DMA_INT3)
|| (interruptNumber == DMA_INTERR));
//
// Register the interrupt handler.
//
Interrupt_registerInterrupt(interruptNumber, intHandler);
//
// Enable the memory management fault.
//
Interrupt_enableInterrupt(interruptNumber);
}
void DMA_unregisterInterrupt(uint32_t interruptNumber)
{
ASSERT(
(interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
|| (interruptNumber == DMA_INT2)
|| (interruptNumber == DMA_INT3)
|| (interruptNumber == DMA_INTERR));
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(interruptNumber);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(interruptNumber);
}

1010
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
View File

File diff suppressed because it is too large Load Diff

70
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
Unescape Escape View File

@ -0,0 +1,70 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __DRIVERLIB__H_
#define __DRIVERLIB__H_
#include "adc14.h"
#include "aes256.h"
#include "comp_e.h"
#include "cpu.h"
#include "crc32.h"
#include "cs.h"
#include "dma.h"
#include "eusci.h"
#include "flash.h"
#include "fpu.h"
#include "gpio.h"
#include "i2c.h"
#include "interrupt.h"
#include "mpu.h"
#include "pcm.h"
#include "pmap.h"
#include "pss.h"
#include "ref_a.h"
#include "reset.h"
#include "rom.h"
#include "rom_map.h"
#include "rtc_c.h"
#include "spi.h"
#include "sysctl.h"
#include "systick.h"
#include "timer32.h"
#include "timer_a.h"
#include "uart.h"
#include "wdt_a.h"
#endif

45
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
Unescape Escape View File

@ -0,0 +1,45 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef EUSCI_H_
#define EUSCI_H_
#include <msp.h>
#define EUSCI_A_CMSIS(x) ((EUSCI_A0_Type *) x)
#define EUSCI_B_CMSIS(x) ((EUSCI_B0_Type *) x)
#endif /* EUSCI_H_ */

792
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
Unescape Escape View File

@ -0,0 +1,792 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <flash.h>
#include <debug.h>
#include <interrupt.h>
#include <msp.h>
#include <cpu.h>
#include <rom.h>
#include <sysctl.h>
/* Statics */
static const uint32_t MAX_PROGRAM_TRIES = 5;
static const uint32_t MAX_ERASE_TRIES = 50;
static uint32_t getUserFlashSector(uint32_t addr)
{
if (addr > 0x1ffff)
{
addr = addr - 0x20000;
}
switch (addr)
{
case 0:
return FLASH_SECTOR0;
case 0x1000:
return FLASH_SECTOR1;
case 0x2000:
return FLASH_SECTOR2;
case 0x3000:
return FLASH_SECTOR3;
case 0x4000:
return FLASH_SECTOR4;
case 0x5000:
return FLASH_SECTOR5;
case 0x6000:
return FLASH_SECTOR6;
case 0x7000:
return FLASH_SECTOR7;
case 0x8000:
return FLASH_SECTOR8;
case 0x9000:
return FLASH_SECTOR9;
case 0xA000:
return FLASH_SECTOR10;
case 0xB000:
return FLASH_SECTOR11;
case 0xC000:
return FLASH_SECTOR12;
case 0xD000:
return FLASH_SECTOR13;
case 0xE000:
return FLASH_SECTOR14;
case 0xF000:
return FLASH_SECTOR15;
case 0x10000:
return FLASH_SECTOR16;
case 0x11000:
return FLASH_SECTOR17;
case 0x12000:
return FLASH_SECTOR18;
case 0x13000:
return FLASH_SECTOR19;
case 0x14000:
return FLASH_SECTOR20;
case 0x15000:
return FLASH_SECTOR21;
case 0x16000:
return FLASH_SECTOR22;
case 0x17000:
return FLASH_SECTOR23;
case 0x18000:
return FLASH_SECTOR24;
case 0x19000:
return FLASH_SECTOR25;
case 0x1A000:
return FLASH_SECTOR26;
case 0x1B000:
return FLASH_SECTOR27;
case 0x1C000:
return FLASH_SECTOR28;
case 0x1D000:
return FLASH_SECTOR29;
case 0x1E000:
return FLASH_SECTOR30;
case 0x1F000:
return FLASH_SECTOR31;
default:
ASSERT(false);
return 0;
}
}
static bool _FlashCtl_Program8(uint32_t src, uint32_t dest)
{
uint32_t ii;
/* Enabling the correct verification settings */
FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
for(ii=0;ii<MAX_PROGRAM_TRIES;ii++)
{
/* Clearing flags */
FLCTL->rCLRIFG.r |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
| FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
HWREG8(dest) = HWREG8(src);
while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
{
__no_operation();
}
if ((BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_PRG_ERR_OFS))
|| (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r,
FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
&& BITBAND_PERI(FLCTL->rIFG.r,
FLCTL_IFG_AVPRE_OFS))
|| (BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_AVPST_OFS)))
{
if(BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS))
{
FlashCtl_clearProgramVerification(FLASH_REGPRE);
}
}
else
{
return true;
}
}
return false;
}
static bool _FlashCtl_Program32(uint32_t src, uint32_t dest)
{
uint32_t ii;
/* Enabling the correct verification settings */
FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
for(ii=0;ii<MAX_PROGRAM_TRIES;ii++)
{
/* Clearing flags */
FLCTL->rCLRIFG.r |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
| FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
HWREG32(dest) = HWREG32(src);
while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
{
__no_operation();
}
if ((BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_PRG_ERR_OFS))
|| (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r,
FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
&& BITBAND_PERI(FLCTL->rIFG.r,
FLCTL_IFG_AVPRE_OFS))
|| (BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_AVPST_OFS)))
{
if(BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS))
{
FlashCtl_clearProgramVerification(FLASH_REGPRE);
}
}
else
{
return true;
}
}
return false;
}
void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod)
{
if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFD_OFS) = 1;
else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFD_OFS) = 1;
else if (memoryBank == FLASH_BANK0
&& accessMethod == FLASH_INSTRUCTION_FETCH)
BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFI_OFS) = 1;
else if (memoryBank == FLASH_BANK1
&& accessMethod == FLASH_INSTRUCTION_FETCH)
BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFI_OFS) = 1;
else
ASSERT(false);
}
void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod)
{
if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFD_OFS) = 0;
else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFD_OFS) = 0;
else if (memoryBank == FLASH_BANK0
&& accessMethod == FLASH_INSTRUCTION_FETCH)
BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFI_OFS) = 0;
else if (memoryBank == FLASH_BANK1
&& accessMethod == FLASH_INSTRUCTION_FETCH)
BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFI_OFS) = 0;
else
ASSERT(false);
}
bool FlashCtl_unprotectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
{
switch (memorySpace)
{
case FLASH_MAIN_MEMORY_SPACE_BANK0:
FLCTL->rBANK0_MAIN_WEPROT.r &= ~sectorMask;
break;
case FLASH_MAIN_MEMORY_SPACE_BANK1:
FLCTL->rBANK1_MAIN_WEPROT.r &= ~sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sectorMask <= 0x04);
FLCTL->rBANK0_INFO_WEPROT.r &= ~sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sectorMask <= 0x04);
FLCTL->rBANK1_INFO_WEPROT.r &= ~sectorMask;
break;
default:
ASSERT(false);
}
return !FlashCtl_isSectorProtected(memorySpace, sectorMask);
}
bool FlashCtl_protectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
{
switch (memorySpace)
{
case FLASH_MAIN_MEMORY_SPACE_BANK0:
FLCTL->rBANK0_MAIN_WEPROT.r |= sectorMask;
break;
case FLASH_MAIN_MEMORY_SPACE_BANK1:
FLCTL->rBANK1_MAIN_WEPROT.r |= sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sectorMask <= 0x04);
FLCTL->rBANK0_INFO_WEPROT.r |= sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sectorMask <= 0x04);
FLCTL->rBANK1_INFO_WEPROT.r |= sectorMask;
break;
default:
ASSERT(false);
}
return FlashCtl_isSectorProtected(memorySpace, sectorMask);
}
bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace, uint32_t sector)
{
switch (memorySpace)
{
case FLASH_MAIN_MEMORY_SPACE_BANK0:
return FLCTL->rBANK0_MAIN_WEPROT.r & sector;
case FLASH_MAIN_MEMORY_SPACE_BANK1:
return FLCTL->rBANK1_MAIN_WEPROT.r & sector;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sector <= 0x04);
return FLCTL->rBANK0_INFO_WEPROT.r & sector;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sector <= 0x04);
return FLCTL->rBANK1_INFO_WEPROT.r & sector;
default:
return false;
}
}
bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
uint_fast8_t pattern)
{
uint32_t memoryPattern, addr, otpOffset;
uint_fast8_t memoryType;
ASSERT(pattern == FLASH_0_PATTERN || pattern == FLASH_1_PATTERN);
addr = (uint32_t) verifyAddr;
memoryPattern = (pattern == FLASH_1_PATTERN) ? 0xFFFFFFFF : 0;
memoryType = (addr > __MAIN_MEMORY_END__) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
/* Taking care of byte accesses */
while ((addr & 0x03) && (length > 0))
{
if (HWREG8(addr++) != ((uint8_t) memoryPattern))
return false;
length--;
}
/* Making sure we are aligned by 128-bit address */
while (((addr & 0x0F)) && (length > 3))
{
if (HWREG32(addr) != memoryPattern)
return false;
addr = addr + 4;
length = length - 4;
}
/* Burst Verify */
if (length > 63)
{
/* Setting/clearing INFO flash flags as appropriate */
if (addr > __MAIN_MEMORY_END__)
{
FLCTL->rRDBRST_CTLSTAT.r = (FLCTL->rRDBRST_CTLSTAT.r
& ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M)
| FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1;
otpOffset = 0x00200000;
} else
{
FLCTL->rRDBRST_CTLSTAT.r = (FLCTL->rRDBRST_CTLSTAT.r
& ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M)
| FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0;
otpOffset = __MAIN_MEMORY_START__;
}
/* Clearing any lingering fault flags and preparing burst verify*/
BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
1;
FLCTL->rRDBRST_FAILCNT.r = 0;
FLCTL->rRDBRST_STARTADDR.r = addr - otpOffset;
FLCTL->rRDBRST_LEN.r = (length & 0xFFFFFFF0);
addr += FLCTL->rRDBRST_LEN.r;
length = length & 0xF;
/* Starting Burst Verify */
FLCTL->rRDBRST_CTLSTAT.r = (FLCTL_RDBRST_CTLSTAT_STOP_FAIL | pattern
| memoryType | FLCTL_RDBRST_CTLSTAT_START);
/* While the burst read hasn't finished */
while ((FLCTL->rRDBRST_CTLSTAT.r & FLCTL_RDBRST_CTLSTAT_BRST_STAT_M)
!= FLCTL_RDBRST_CTLSTAT_BRST_STAT_3)
{
__no_operation();
}
/* Checking for a verification/access error/failure */
if (BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r,
FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS)
|| BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r,
FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS)
|| FLCTL->rRDBRST_FAILCNT.r)
{
/* Clearing the Read Burst flag and returning */
BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
1;
return false;
}
/* Clearing the Read Burst flag */
BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
1;
}
/* Remaining Words */
while (length > 3)
{
if (HWREG32(addr) != memoryPattern)
return false;
addr = addr + 4;
length = length - 4;
}
/* Remaining Bytes */
while (length > 0)
{
if (HWREG8(addr++) != ((uint8_t) memoryPattern))
return false;
length--;
}
return true;
}
bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode)
{
if (FLCTL->rPOWER_STAT.r & FLCTL_POWER_STAT_RD_2T)
return false;
if (flashBank == FLASH_BANK0)
{
FLCTL->rBANK0_RDCTL.r = (FLCTL->rBANK0_RDCTL.r
& ~FLCTL_BANK0_RDCTL_RD_MODE_M) | readMode;
while (FLCTL->rBANK0_RDCTL.b.bRD_MODE != readMode)
;
} else if (flashBank == FLASH_BANK1)
{
FLCTL->rBANK1_RDCTL.r = (FLCTL->rBANK1_RDCTL.r
& ~FLCTL_BANK1_RDCTL_RD_MODE_M) | readMode;
while (FLCTL->rBANK1_RDCTL.b.bRD_MODE != readMode)
;
} else
{
ASSERT(false);
return false;
}
return true;
}
uint32_t FlashCtl_getReadMode(uint32_t flashBank)
{
if (flashBank == FLASH_BANK0)
{
return FLCTL->rBANK0_RDCTL.b.bRD_MODE;
} else if (flashBank == FLASH_BANK1)
{
return FLCTL->rBANK1_RDCTL.b.bRD_MODE;
} else
{
ASSERT(false);
return 0;
}
}
bool FlashCtl_performMassErase(void)
{
uint32_t userFlash, ii, jj, sector;
/* Trying a mass erase in ROM first. If it fails (should be rare), going
* through and erasing each sector one-by-one
*/
if (!FlashInternal_performMassErase(true))
{
userFlash = SysCtl_getFlashSize() / 2;
for (ii = __MAIN_MEMORY_START__; ii < userFlash; ii += 4096)
{
sector = getUserFlashSector(ii);
if (!((FLCTL->rBANK0_MAIN_WEPROT.r) & sector))
{
for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
{
if (FlashInternal_eraseSector(ii, true))
{
break;
}
}
if (jj == MAX_ERASE_TRIES)
return false;
}
if (!(FLCTL->rBANK1_MAIN_WEPROT.r & sector))
{
for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
{
if (FlashInternal_eraseSector(ii + userFlash, true))
{
break;
}
}
if (jj == MAX_ERASE_TRIES)
return false;
}
if (sector < FLCTL_BANK0_MAIN_WEPROT_PROT2)
{
if (!(FLCTL->rBANK0_INFO_WEPROT.r & sector))
{
for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
{
if (FlashInternal_eraseSector(ii + __BSL_MEMORY_START__,
true))
{
break;
}
}
if (jj == MAX_ERASE_TRIES)
return false;
}
if (!(FLCTL->rBANK1_INFO_WEPROT.r & sector))
{
for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
{
if (FlashInternal_eraseSector(
ii + __BSL_MEMORY_START__ + 0x2000, true))
{
break;
}
}
if (jj == MAX_ERASE_TRIES)
return false;
}
}
}
}
return true;
}
bool FlashCtl_eraseSector(uint32_t addr)
{
uint32_t ii;
for(ii=0;ii<MAX_ERASE_TRIES;ii++)
{
if(FlashInternal_eraseSector(addr, true))
{
return true;
}
}
return false;
}
bool FlashCtl_programMemory(void* src, void* dest, uint32_t length)
{
uint32_t destAddr, srcAddr;
bool res;
/* Casting to integers */
srcAddr = (uint32_t)src;
destAddr = (uint32_t)dest;
/* Enabling word programming */
FlashCtl_enableWordProgramming(FLASH_IMMEDIATE_WRITE_MODE);
/* Assume failure */
res = false;
/* Taking care of byte accesses */
while ((destAddr & 0x03) && length > 0)
{
if(!_FlashCtl_Program8(srcAddr,destAddr))
{
goto FlashProgramCleanUp;
}
else
{
srcAddr++;
destAddr++;
length--;
}
}
/* Taking care of word accesses */
while ((destAddr & 0x0F) && (length > 3))
{
if (!_FlashCtl_Program32(srcAddr, destAddr))
{
goto FlashProgramCleanUp;
}
else
{
srcAddr += 4;
destAddr += 4;
length -= 4;
}
}
/* Remaining byte accesses */
while (length > 0)
{
if(!_FlashCtl_Program8(srcAddr,destAddr))
{
goto FlashProgramCleanUp;
}
else
{
srcAddr++;
destAddr++;
length--;
}
}
/* If we got this far that means that we succeeded */
res = true;
FlashProgramCleanUp:
FlashCtl_disableWordProgramming();
return res;
}
void FlashCtl_setProgramVerification(uint32_t verificationSetting)
{
if ((verificationSetting & FLASH_BURSTPOST))
BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) =
1;
if ((verificationSetting & FLASH_BURSTPRE))
BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) =
1;
if ((verificationSetting & FLASH_REGPRE))
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 1;
if ((verificationSetting & FLASH_REGPOST))
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 1;
}
void FlashCtl_clearProgramVerification(uint32_t verificationSetting)
{
if ((verificationSetting & FLASH_BURSTPOST))
BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) =
0;
if ((verificationSetting & FLASH_BURSTPRE))
BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) =
0;
if ((verificationSetting & FLASH_REGPRE))
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 0;
if ((verificationSetting & FLASH_REGPOST))
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 0;
}
void FlashCtl_enableWordProgramming(uint32_t mode)
{
if (mode == FLASH_IMMEDIATE_WRITE_MODE)
{
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS) = 0;
} else if (mode == FLASH_COLLATED_WRITE_MODE)
{
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS) = 1;
}
}
void FlashCtl_disableWordProgramming(void)
{
BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 0;
}
uint32_t FlashCtl_isWordProgrammingEnabled(void)
{
if (!BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS))
{
return 0;
} else if (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS))
return FLASH_COLLATED_WRITE_MODE;
else
return FLASH_IMMEDIATE_WRITE_MODE;
}
void FlashCtl_setWaitState(uint32_t flashBank, uint32_t waitState)
{
if (flashBank == FLASH_BANK0)
{
FLCTL->rBANK0_RDCTL.r =
(FLCTL->rBANK0_RDCTL.r & ~FLCTL_BANK0_RDCTL_WAIT_M)
| (waitState << 12);
} else if (flashBank == FLASH_BANK1)
{
FLCTL->rBANK1_RDCTL.r =
(FLCTL->rBANK1_RDCTL.r & ~FLCTL_BANK1_RDCTL_WAIT_M)
| (waitState << 12);
} else
{
ASSERT(false);
}
}
uint32_t FlashCtl_getWaitState(uint32_t flashBank)
{
if (flashBank == FLASH_BANK0)
{
return FLCTL->rBANK0_RDCTL.b.bWAIT;
} else if (flashBank == FLASH_BANK1)
{
return FLCTL->rBANK1_RDCTL.b.bWAIT;
} else
{
ASSERT(false);
return 0;
}
}
void FlashCtl_enableInterrupt(uint32_t flags)
{
FLCTL->rIE.r |= flags;
}
void FlashCtl_disableInterrupt(uint32_t flags)
{
FLCTL->rIE.r &= ~flags;
}
uint32_t FlashCtl_getInterruptStatus(void)
{
return FLCTL->rIFG.r;
}
uint32_t FlashCtl_getEnabledInterruptStatus(void)
{
return FlashCtl_getInterruptStatus() & FLCTL->rIE.r;
}
void FlashCtl_clearInterruptFlag(uint32_t flags)
{
FLCTL->rCLRIFG.r |= flags;
}
void FlashCtl_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(INT_FLCTL, intHandler);
//
// Enable the system control interrupt.
//
Interrupt_enableInterrupt(INT_FLCTL);
}
void FlashCtl_unregisterInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(INT_FLCTL);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(INT_FLCTL);
}

813
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
Unescape Escape View File

@ -0,0 +1,813 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __FLASH_H__
#define __FLASH_H__
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <msp.h>
#include <stdbool.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define FLASH_BURST_PRG_BIT 0x03
/* Interrupts */
#define FLASH_PROGRAM_ERROR FLCTL_IFG_PRG_ERR
#define FLASH_BENCHMARK_INT FLCTL_IFG_BMRK
#define FLASH_ERASE_COMPLETE FLCTL_IFG_ERASE
#define FLASH_BRSTPRGM_COMPLETE FLCTL_IFG_PRGB
#define FLASH_WRDPRGM_COMPLETE FLCTL_IFG_PRG
#define FLASH_POSTVERIFY_FAILED FLCTL_IFG_AVPST
#define FLASH_PREVERIFY_FAILED FLCTL_IFG_AVPRE
#define FLASH_BRSTRDCMP_COMPLETE FLCTL_IFG_RDBRST
#define FLASH_NORMAL_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_0
#define FLASH_MARGIN0_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_1
#define FLASH_MARGIN1_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_2
#define FLASH_PROGRAM_VERIFY_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_3
#define FLASH_ERASE_VERIFY_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_4
#define FLASH_LEAKAGE_VERIFY_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_5
#define FLASH_MARGIN0B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_9
#define FLASH_MARGIN1B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_10
#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE 0x70000
#define FLASH_BANK0 0x00
#define FLASH_BANK1 0x01
#define FLASH_DATA_READ 0x00
#define FLASH_INSTRUCTION_FETCH 0x01
#define FLASH_MAIN_MEMORY_SPACE_BANK0 0x01
#define FLASH_MAIN_MEMORY_SPACE_BANK1 0x02
#define FLASH_INFO_MEMORY_SPACE_BANK0 0x03
#define FLASH_INFO_MEMORY_SPACE_BANK1 0x04
#define FLASH_MAIN_SPACE FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0
#define FLASH_INFO_SPACE FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1
#define FLASH_1_PATTERN FLCTL_RDBRST_CTLSTAT_DATA_CMP
#define FLASH_0_PATTERN 0x00
#define FLASH_SECTOR0 FLCTL_BANK0_MAIN_WEPROT_PROT0
#define FLASH_SECTOR1 FLCTL_BANK0_MAIN_WEPROT_PROT1
#define FLASH_SECTOR2 FLCTL_BANK0_MAIN_WEPROT_PROT2
#define FLASH_SECTOR3 FLCTL_BANK0_MAIN_WEPROT_PROT3
#define FLASH_SECTOR4 FLCTL_BANK0_MAIN_WEPROT_PROT4
#define FLASH_SECTOR5 FLCTL_BANK0_MAIN_WEPROT_PROT5
#define FLASH_SECTOR6 FLCTL_BANK0_MAIN_WEPROT_PROT6
#define FLASH_SECTOR7 FLCTL_BANK0_MAIN_WEPROT_PROT7
#define FLASH_SECTOR8 FLCTL_BANK0_MAIN_WEPROT_PROT8
#define FLASH_SECTOR9 FLCTL_BANK0_MAIN_WEPROT_PROT9
#define FLASH_SECTOR10 FLCTL_BANK0_MAIN_WEPROT_PROT10
#define FLASH_SECTOR11 FLCTL_BANK0_MAIN_WEPROT_PROT11
#define FLASH_SECTOR12 FLCTL_BANK0_MAIN_WEPROT_PROT12
#define FLASH_SECTOR13 FLCTL_BANK0_MAIN_WEPROT_PROT13
#define FLASH_SECTOR14 FLCTL_BANK0_MAIN_WEPROT_PROT14
#define FLASH_SECTOR15 FLCTL_BANK0_MAIN_WEPROT_PROT15
#define FLASH_SECTOR16 FLCTL_BANK0_MAIN_WEPROT_PROT16
#define FLASH_SECTOR17 FLCTL_BANK0_MAIN_WEPROT_PROT17
#define FLASH_SECTOR18 FLCTL_BANK0_MAIN_WEPROT_PROT18
#define FLASH_SECTOR19 FLCTL_BANK0_MAIN_WEPROT_PROT19
#define FLASH_SECTOR20 FLCTL_BANK0_MAIN_WEPROT_PROT20
#define FLASH_SECTOR21 FLCTL_BANK0_MAIN_WEPROT_PROT21
#define FLASH_SECTOR22 FLCTL_BANK0_MAIN_WEPROT_PROT22
#define FLASH_SECTOR23 FLCTL_BANK0_MAIN_WEPROT_PROT23
#define FLASH_SECTOR24 FLCTL_BANK0_MAIN_WEPROT_PROT24
#define FLASH_SECTOR25 FLCTL_BANK0_MAIN_WEPROT_PROT25
#define FLASH_SECTOR26 FLCTL_BANK0_MAIN_WEPROT_PROT26
#define FLASH_SECTOR27 FLCTL_BANK0_MAIN_WEPROT_PROT27
#define FLASH_SECTOR28 FLCTL_BANK0_MAIN_WEPROT_PROT28
#define FLASH_SECTOR29 FLCTL_BANK0_MAIN_WEPROT_PROT29
#define FLASH_SECTOR30 FLCTL_BANK0_MAIN_WEPROT_PROT30
#define FLASH_SECTOR31 FLCTL_BANK0_MAIN_WEPROT_PROT31
#define FLASH_NOVER 0
#define FLASH_BURSTPOST FLCTL_PRGBRST_CTLSTAT_AUTO_PST
#define FLASH_BURSTPRE FLCTL_PRGBRST_CTLSTAT_AUTO_PRE
#define FLASH_REGPRE FLCTL_PRG_CTLSTAT_VER_PRE
#define FLASH_REGPOST FLCTL_PRG_CTLSTAT_VER_PST
#define FLASH_FULLVER (FLCTL_PRGBRST_CTLSTAT_AUTO_PST | \
FLCTL_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_PRG_CTLSTAT_VER_PRE \
| FLCTL_PRG_CTLSTAT_VER_PST)
#define FLASH_COLLATED_WRITE_MODE 0x01
#define FLASH_IMMEDIATE_WRITE_MODE 0x02
#define FlashInternal_eraseSector \
((bool (*)(uint32_t addr, \
bool verify))ROM_FLASHCTLTABLE[9])
#define FlashInternal_performMassErase \
((bool (*)(bool verify))ROM_FLASHCTLTABLE[8])
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables read buffering on accesses to a specified bank of flash memory
//!
//! \param memoryBank is the value of the memory bank to enable read
//! buffering. Must be only one of the following values:
//! - \b FLASH_BANK0,
//! - \b FLASH_BANK1
//!
//! \param accessMethod is the value of the access type to enable read
//! buffering. Must be only one of the following values:
//! - \b FLASH_DATA_READ,
//! - \b FLASH_INSTRUCTION_FETCH
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod);
//*****************************************************************************
//
//! Disables read buffering on accesses to a specified bank of flash memory
//!
//! \param memoryBank is the value of the memory bank to disable read
//! buffering. Must be only one of the following values:
//! - \b FLASH_BANK0,
//! - \b FLASH_BANK1
//!
//! \param accessMethod is the value of the access type to disable read
//! buffering. Must ne only one of the following values:
//! - \b FLASH_DATA_READ,
//! - \b FLASH_INSTRUCTION_FETCH
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod);
//*****************************************************************************
//
//! Disables program protection on the given sector mask. This setting can be
//! applied on a sector-wise bases on a given memory space (INFO or MAIN).
//!
//! \param memorySpace is the value of the memory bank to disable program
//! protection. Must be only one of the following values:
//! - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
//! - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
//! - \b FLASH_INFO_MEMORY_SPACE_BANK0,
//! - \b FLASH_INFO_MEMORY_SPACE_BANK1
//!
//! \param sectorMask is a bit mask of the sectors to disable program
//! protection. Must be a bitfield of the following values:
//! - \b FLASH_SECTOR0,
//! - \b FLASH_SECTOR1,
//! - \b FLASH_SECTOR2,
//! - \b FLASH_SECTOR3,
//! - \b FLASH_SECTOR4,
//! - \b FLASH_SECTOR5,
//! - \b FLASH_SECTOR6,
//! - \b FLASH_SECTOR7,
//! - \b FLASH_SECTOR8,
//! - \b FLASH_SECTOR9,
//! - \b FLASH_SECTOR10,
//! - \b FLASH_SECTOR11,
//! - \b FLASH_SECTOR12,
//! - \b FLASH_SECTOR13,
//! - \b FLASH_SECTOR14,
//! - \b FLASH_SECTOR15,
//! - \b FLASH_SECTOR16,
//! - \b FLASH_SECTOR17,
//! - \b FLASH_SECTOR18,
//! - \b FLASH_SECTOR19,
//! - \b FLASH_SECTOR20,
//! - \b FLASH_SECTOR21,
//! - \b FLASH_SECTOR22,
//! - \b FLASH_SECTOR23,
//! - \b FLASH_SECTOR24,
//! - \b FLASH_SECTOR25,
//! - \b FLASH_SECTOR26,
//! - \b FLASH_SECTOR27,
//! - \b FLASH_SECTOR28,
//! - \b FLASH_SECTOR29,
//! - \b FLASH_SECTOR30,
//! - \b FLASH_SECTOR31
//!
//! \note Flash sector sizes are 4KB and the number of sectors may vary
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
//! \return true if sector protection disabled false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace,
uint32_t sectorMask);
//*****************************************************************************
//
//! Enables program protection on the given sector mask. This setting can be
//! applied on a sector-wise bases on a given memory space (INFO or MAIN).
//!
//! \param memorySpace is the value of the memory bank to enable program
//! protection. Must be only one of the following values:
//! - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
//! - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
//! - \b FLASH_INFO_MEMORY_SPACE_BANK0,
//! - \b FLASH_INFO_MEMORY_SPACE_BANK1
//!
//! \param sectorMask is a bit mask of the sectors to enable program
//! protection. Must be a bitfield of the following values:
//! - \b FLASH_SECTOR0,
//! - \b FLASH_SECTOR1,
//! - \b FLASH_SECTOR2,
//! - \b FLASH_SECTOR3,
//! - \b FLASH_SECTOR4,
//! - \b FLASH_SECTOR5,
//! - \b FLASH_SECTOR6,
//! - \b FLASH_SECTOR7,
//! - \b FLASH_SECTOR8,
//! - \b FLASH_SECTOR9,
//! - \b FLASH_SECTOR10,
//! - \b FLASH_SECTOR11,
//! - \b FLASH_SECTOR12,
//! - \b FLASH_SECTOR13,
//! - \b FLASH_SECTOR14,
//! - \b FLASH_SECTOR15,
//! - \b FLASH_SECTOR16,
//! - \b FLASH_SECTOR17,
//! - \b FLASH_SECTOR18,
//! - \b FLASH_SECTOR19,
//! - \b FLASH_SECTOR20,
//! - \b FLASH_SECTOR21,
//! - \b FLASH_SECTOR22,
//! - \b FLASH_SECTOR23,
//! - \b FLASH_SECTOR24,
//! - \b FLASH_SECTOR25,
//! - \b FLASH_SECTOR26,
//! - \b FLASH_SECTOR27,
//! - \b FLASH_SECTOR28,
//! - \b FLASH_SECTOR29,
//! - \b FLASH_SECTOR30,
//! - \b FLASH_SECTOR31
//!
//! \note Flash sector sizes are 4KB and the number of sectors may vary
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_protectSector(uint_fast8_t memorySpace,
uint32_t sectorMask);
//*****************************************************************************
//
//! Returns the sector protection for given sector mask and memory space
//!
//! \param memorySpace is the value of the memory bank to check for program
//! protection. Must be only one of the following values:
//! - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
//! - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
//! - \b FLASH_INFO_MEMORY_SPACE_BANK0,
//! - \b FLASH_INFO_MEMORY_SPACE_BANK1
//!
//! \param sector is the sector to check for program protection.
//! Must be one of the following values:
//! - \b FLASH_SECTOR0,
//! - \b FLASH_SECTOR1,
//! - \b FLASH_SECTOR2,
//! - \b FLASH_SECTOR3,
//! - \b FLASH_SECTOR4,
//! - \b FLASH_SECTOR5,
//! - \b FLASH_SECTOR6,
//! - \b FLASH_SECTOR7,
//! - \b FLASH_SECTOR8,
//! - \b FLASH_SECTOR9,
//! - \b FLASH_SECTOR10,
//! - \b FLASH_SECTOR11,
//! - \b FLASH_SECTOR12,
//! - \b FLASH_SECTOR13,
//! - \b FLASH_SECTOR14,
//! - \b FLASH_SECTOR15,
//! - \b FLASH_SECTOR16,
//! - \b FLASH_SECTOR17,
//! - \b FLASH_SECTOR18,
//! - \b FLASH_SECTOR19,
//! - \b FLASH_SECTOR20,
//! - \b FLASH_SECTOR21,
//! - \b FLASH_SECTOR22,
//! - \b FLASH_SECTOR23,
//! - \b FLASH_SECTOR24,
//! - \b FLASH_SECTOR25,
//! - \b FLASH_SECTOR26,
//! - \b FLASH_SECTOR27,
//! - \b FLASH_SECTOR28,
//! - \b FLASH_SECTOR29,
//! - \b FLASH_SECTOR30,
//! - \b FLASH_SECTOR31
//!
//! Note that flash sector sizes are 4KB and the number of sectors may vary
//! depending on the specific device. Also, for INFO memory space, only sectors
//! FLASH_SECTOR0 and FLASH_SECTOR1 will exist.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace,
uint32_t sector);
//*****************************************************************************
//
//! Verifies a given segment of memory based off either a high (1) or low (0)
//! state.
//!
//! \param verifyAddr Start address where verification will begin
//!
//! \param length Length in bytes to verify based off the pattern
//!
//! \param pattern The pattern which verification will check versus. This can
//! either be a low pattern (each register will be checked versus a pattern
//! of 32 zeros, or a high pattern (each register will be checked versus a
//! pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN
//!
//! Note that there are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//!
//! \return true if memory verification is successful, false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
uint_fast8_t pattern);
//*****************************************************************************
//
//! Performs a mass erase on all unprotected flash sectors. Protected sectors
//! are ignored.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//!
//! \return true if mass erase completes successfully, false otherwise
//
//*****************************************************************************
extern bool FlashCtl_performMassErase(void);
//*****************************************************************************
//
//! Erases a sector of MAIN or INFO flash memory.
//!
//! \param addr The start of the sector to erase. Note that with flash,
//! the minimum allowed size that can be erased is a flash sector
//! (which is 4KB on the MSP432 family). If an address is provided to
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//!
//! \return true if sector erase is successful, false otherwise.
//
//*****************************************************************************
extern bool FlashCtl_eraseSector(uint32_t addr);
//*****************************************************************************
//
//! Program a portion of flash memory with the provided data
//!
//! \param src Pointer to the data source to program into flash
//!
//! \param dest Pointer to the destination in flash to program
//!
//! \param length Length in bytes to program
//!
//! \note There are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//!
//! \return Whether or not the program succeeded
//
//*****************************************************************************
extern bool FlashCtl_programMemory(void* src, void* dest, uint32_t length);
//*****************************************************************************
//
//! Setups pre/post verification of burst and regular flash programming
//! instructions. Note that this API is for advanced users that are programming
//! their own flash drivers. The program/erase APIs are not affected by this
//! setting and take care of the verification requirements.
//!
//! \param verificationSetting Verification setting to set. This value can
//! be a bitwise OR of the following values:
//! - \b FLASH_BURSTPOST,
//! - \b FLASH_BURSTPRE,
//! - \b FLASH_REGPRE,
//! - \b FLASH_REGPOST
//! - \b FLASH_NOVER No verification enabled
//! - \b FLASH_FULLVER Full verification enabled
//!
//! \return none
//
//*****************************************************************************
extern void FlashCtl_setProgramVerification(uint32_t verificationSetting);
//*****************************************************************************
//
//! Clears pre/post verification of burst and regular flash programming
//! instructions. Note that this API is for advanced users that are programming
//! their own flash drivers. The program/erase APIs are not affected by this
//! setting and take care of the verification requirements.
//!
//! \param verificationSetting Verification setting to clear. This value can
//! be a bitwise OR of the following values:
//! - \b FLASH_BURSTPOST,
//! - \b FLASH_BURSTPRE,
//! - \b FLASH_REGPRE,
//! - \b FLASH_REGPOST
//! - \b FLASH_NOVER No verification enabled
//! - \b FLASH_FULLVER Full verification enabled
//!
//! \return none
//
//*****************************************************************************
extern void FlashCtl_clearProgramVerification(uint32_t verificationSetting);
//*****************************************************************************
//
//! Enables word programming of flash memory.
//!
//! This function will enable word programming of the flash memory and set the
//! mode of behavior when the flash write occurs.
//!
//! \param mode The mode specifies the behavior of the flash controller when
//! programming words to flash. In \b FLASH_IMMEDIATE_WRITE_MODE, the
//! program operation happens immediately on the write to flash while
//! in \b FLASH_COLLATED_WRITE_MODE the write will be delayed until a full
//! 128-bits have been collated. Possible values include:
//! - \b FLASH_IMMEDIATE_WRITE_MODE
//! - \b FLASH_COLLATED_WRITE_MODE
//!
//!
//! Refer to the user's guide for further documentation.
//!
//! \return none
//
//*****************************************************************************
extern void FlashCtl_enableWordProgramming(uint32_t mode);
//*****************************************************************************
//
//! Disables word programming of flash memory.
//!
//! Refer to FlashCtl_enableWordProgramming and the user's guide for description
//! on the difference between full word and immediate programming
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_disableWordProgramming(void);
//*****************************************************************************
//
//! Returns if word programming mode is enabled (and if it is, the specific mode)
//!
//! Refer to FlashCtl_enableWordProgramming and the user's guide for description
//! on the difference between full word and immediate programming
//!
//! \return a zero value if word programming is disabled,
//! - \b FLASH_IMMEDIATE_WRITE_MODE
//! - \b FLASH_COLLATED_WRITE_MODE
//!
//
//*****************************************************************************
extern uint32_t FlashCtl_isWordProgrammingEnabled(void);
//*****************************************************************************
//
//! Sets the flash read mode to be used by default flash read operations.
//! Note that the proper wait states must be set prior to entering this
//! function.
//!
//! \param flashBank Flash bank to set read mode for. Valid values are:
//! - \b FLASH_BANK0
//! - \b FLASH_BANK1
//!
//! \param readMode The read mode to set. Valid values are:
//! - \b FLASH_NORMAL_READ_MODE,
//! - \b FLASH_MARGIN0_READ_MODE,
//! - \b FLASH_MARGIN1_READ_MODE,
//! - \b FLASH_PROGRAM_VERIFY_READ_MODE,
//! - \b FLASH_ERASE_VERIFY_READ_MODE,
//! - \b FLASH_LEAKAGE_VERIFY_READ_MODE,
//! - \b FLASH_MARGIN0B_READ_MODE,
//! - \b FLASH_MARGIN1B_READ_MODE
//!
//! \return None.
//
//*****************************************************************************
extern bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode);
//*****************************************************************************
//
//! Gets the flash read mode to be used by default flash read operations.
//!
//! \param flashBank Flash bank to set read mode for. Valid values are:
//! - \b FLASH_BANK0
//! - \b FLASH_BANK1
//!
//! \return Returns the read mode to set. Valid values are:
//! - \b FLASH_NORMAL_READ_MODE,
//! - \b FLASH_MARGIN0_READ_MODE,
//! - \b FLASH_MARGIN1_READ_MODE,
//! - \b FLASH_PROGRAM_VERIFY_READ_MODE,
//! - \b FLASH_ERASE_VERIFY_READ_MODE,
//! - \b FLASH_LEAKAGE_VERIFY_READ_MODE,
//! - \b FLASH_MARGIN0B_READ_MODE,
//! - \b FLASH_MARGIN1B_READ_MODE
//!
//
//*****************************************************************************
extern uint32_t FlashCtl_getReadMode(uint32_t flashBank);
//*****************************************************************************
//
//! Changes the number of wait states that are used by the flash controller
//! for read operations. When changing frequency ranges of the clock, this
//! functions must be used in order to allow for readable flash memory.
//!
//! \param waitState The number of wait states to set. Note that only
//! bits 0-3 are used.
//!
//! \param flashBank Flash bank to set wait state for. Valid values are:
//! - \b FLASH_BANK0
//! - \b FLASH_BANK1
//!
//
//*****************************************************************************
extern void FlashCtl_setWaitState(uint32_t bank, uint32_t waitState);
//*****************************************************************************
//
//! Returns the set number of flash wait states for the given flash bank.
//!
//! \param flashBank Flash bank to set wait state for. Valid values are:
//! - \b FLASH_BANK0
//! - \b FLASH_BANK1
//!
//! \return The wait state setting for the specified flash bank
//
//*****************************************************************************
extern uint32_t FlashCtl_getWaitState(uint32_t bank);
//*****************************************************************************
//
//! Enables individual flash control interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be enabled. Must
//! be a logical OR of:
//! - \b FLASH_PROGRAM_ERROR,
//! - \b FLASH_BENCHMARK_INT,
//! - \b FLASH_ERASE_COMPLETE,
//! - \b FLASH_BRSTPRGM_COMPLETE,
//! - \b FLASH_WRDPRGM_COMPLETE,
//! - \b FLASH_POSTVERIFY_FAILED,
//! - \b FLASH_PREVERIFY_FAILED,
//! - \b FLASH_BRSTRDCMP_COMPLETE
//!
//! This function enables the indicated flash system interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_enableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Disables individual flash system interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be disabled. Must
//! be a logical OR of:
//! - \b FLASH_PROGRAM_ERROR,
//! - \b FLASH_BENCHMARK_INT,
//! - \b FLASH_ERASE_COMPLETE,
//! - \b FLASH_BRSTPRGM_COMPLETE,
//! - \b FLASH_WRDPRGM_COMPLETE,
//! - \b FLASH_POSTVERIFY_FAILED,
//! - \b FLASH_PREVERIFY_FAILED,
//! - \b FLASH_BRSTRDCMP_COMPLETE
//!
//! This function disables the indicated flash system interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_disableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Gets the current interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list
//! of pending interrupts that are actually enabled and could have caused the
//! ISR.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! - \b FLASH_PROGRAM_ERROR,
//! - \b FLASH_BENCHMARK_INT,
//! - \b FLASH_ERASE_COMPLETE,
//! - \b FLASH_BRSTPRGM_COMPLETE,
//! - \b FLASH_WRDPRGM_COMPLETE,
//! - \b FLASH_POSTVERIFY_FAILED,
//! - \b FLASH_PREVERIFY_FAILED,
//! - \b FLASH_BRSTRDCMP_COMPLETE
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t FlashCtl_getEnabledInterruptStatus(void);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b FLASH_PROGRAM_ERROR,
//! - \b FLASH_BENCHMARK_INT,
//! - \b FLASH_ERASE_COMPLETE,
//! - \b FLASH_BRSTPRGM_COMPLETE,
//! - \b FLASH_WRDPRGM_COMPLETE,
//! - \b FLASH_POSTVERIFY_FAILED,
//! - \b FLASH_PREVERIFY_FAILED,
//! - \b FLASH_BRSTRDCMP_COMPLETE
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t FlashCtl_getInterruptStatus(void);
//*****************************************************************************
//
//! Clears flash system interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be cleared. Must
//! be a logical OR of:
//! - \b FLASH_PROGRAM_ERROR,
//! - \b FLASH_BENCHMARK_INT,
//! - \b FLASH_ERASE_COMPLETE,
//! - \b FLASH_BRSTPRGM_COMPLETE,
//! - \b FLASH_WRDPRGM_COMPLETE,
//! - \b FLASH_POSTVERIFY_FAILED,
//! - \b FLASH_PREVERIFY_FAILED,
//! - \b FLASH_BRSTRDCMP_COMPLETE
//!
//! The specified flash system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep it from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_clearInterruptFlag(uint32_t flags);
//*****************************************************************************
//
//! Registers an interrupt handler for flash clock system interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the clock
//! system interrupt occurs.
//!
//! This function registers the handler to be called when a clock system
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific flash controller interrupts must be enabled
//! via FlashCtl_enableInterrupt(). It is the interrupt handler's
//! responsibility to clear the interrupt source via
//! FlashCtl_clearInterruptFlag().
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash system.
//!
//! This function unregisters the handler to be called when a clock system
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_unregisterInterrupt(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __FLASH_H__

115
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
Unescape Escape View File

@ -0,0 +1,115 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <fpu.h>
void FPU_enableModule(void)
{
//
// Enable the coprocessors used by the floating-point unit.
//
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_M | SCB_CPACR_CP10_M))
| SCB_CPACR_CP11_M | SCB_CPACR_CP10_M);
}
void FPU_disableModule(void)
{
//
// Disable the coprocessors used by the floating-point unit.
//
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_M | SCB_CPACR_CP11_M)));
}
void FPU_enableStacking(void)
{
//
// Enable automatic state preservation for the floating-point unit, and
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN) | FPU_FPCCR_ASPEN;
}
void FPU_enableLazyStacking(void)
{
//
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
FPU->FPCCR |= FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN;
}
void FPU_disableStacking(void)
{
//
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
FPU->FPCCR &= ~(FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN);
}
void FPU_setHalfPrecisionMode(uint32_t mode)
{
//
// Set the half-precision floating-point format.
//
FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_AHP_Msk)) | mode;
}
void FPU_setNaNMode(uint32_t mode)
{
//
// Set the NaN mode.
//
FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_DN_Msk)) | mode;
}
void FPU_setFlushToZeroMode(uint32_t mode)
{
//
// Set the flush-to-zero mode.
//
FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_FZ_Msk)) | mode;
}
void FPU_setRoundingMode(uint32_t mode)
{
//
// Set the rounding mode.
//
FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_RMode_Msk)) | mode;
}

285
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
Unescape Escape View File

@ -0,0 +1,285 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __FPU_H__
#define __FPU_H__
//*****************************************************************************
//
//!
//! \addtogroup fpu_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <msp.h>
//*****************************************************************************
//
// Values that can be passed to FPUHalfPrecisionSet as the mode parameter.
//
//*****************************************************************************
#define FPU_HALF_IEEE 0x00000000
#define FPU_HALF_ALTERNATE 0x04000000
//*****************************************************************************
//
// Values that can be passed to FPU_setNaNMode as the mode parameter.
//
//*****************************************************************************
#define FPU_NAN_PROPAGATE 0x00000000
#define FPU_NAN_DEFAULT 0x02000000
//*****************************************************************************
//
// Values that can be passed to FPU_setFlushToZeroMode as the mode parameter.
//
//*****************************************************************************
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
//*****************************************************************************
//
// Values that can be passed to FPU_setRoundingMode as the mode parameter.
//
//*****************************************************************************
#define FPU_ROUND_NEAREST 0x00000000
#define FPU_ROUND_POS_INF 0x00400000
#define FPU_ROUND_NEG_INF 0x00800000
#define FPU_ROUND_ZERO 0x00c00000
//*****************************************************************************
//
//! Enables the floating-point unit.
//!
//! This function enables the floating-point unit, allowing the floating-point
//! instructions to be executed. This function must be called prior to
//! performing any hardware floating-point operations; failure to do so results
//! in a NOCP usage fault.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_enableModule(void);
//*****************************************************************************
//
//! Disables the floating-point unit.
//!
//! This function disables the floating-point unit, preventing floating-point
//! instructions from executing (generating a NOCP usage fault instead).
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_disableModule(void);
//*****************************************************************************
//
//! Enables the stacking of floating-point registers.
//!
//! This function enables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When enabled, space is reserved on the stack for
//! the floating-point context and the floating-point state is saved into this
//! stack space. Upon return from the interrupt, the floating-point context is
//! restored.
//!
//! If the floating-point registers are not stacked, floating-point
//! instructions cannot be safely executed in an interrupt handler because the
//! values of s0-s15 are not likely to be preserved for the interrupted code.
//! On the other hand, stacking the floating-point registers increases the
//! stacking operation from 8 words to 26 words, also increasing the interrupt
//! response latency.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_enableStacking(void);
//*****************************************************************************
//
//! Enables the lazy stacking of floating-point registers.
//!
//! This function enables the lazy stacking of floating-point registers s0-s15
//! when an interrupt is handled. When lazy stacking is enabled, space is
//! reserved on the stack for the floating-point context, but the
//! floating-point state is not saved. If a floating-point instruction is
//! executed from within the interrupt context, the floating-point context is
//! first saved into the space reserved on the stack. On completion of the
//! interrupt handler, the floating-point context is only restored if it was
//! saved (as the result of executing a floating-point instruction).
//!
//! This method provides a compromise between fast interrupt response (because
//! the floating-point state is not saved on interrupt entry) and the ability
//! to use floating-point in interrupt handlers (because the floating-point
//! state is saved if floating-point instructions are used).
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_enableLazyStacking(void);
//*****************************************************************************
//
//! Disables the stacking of floating-point registers.
//!
//! This function disables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When floating-point context stacking is disabled,
//! floating-point operations performed in an interrupt handler destroy the
//! floating-point context of the main thread of execution.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_disableStacking(void);
//*****************************************************************************
//
//! Selects the format of half-precision floating-point values.
//!
//! \param mode is the format for half-precision floating-point value, which
//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
//!
//! This function selects between the IEEE half-precision floating-point
//! representation and the Cortex-M processor alternative representation. The
//! alternative representation has a larger range but does not have a way to
//! encode infinity (positive or negative) or NaN (quiet or signalling). The
//! default setting is the IEEE format.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_setHalfPrecisionMode(uint32_t mode);
//*****************************************************************************
//
//! Selects the NaN mode.
//!
//! \param mode is the mode for NaN results; which is
//! either \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
//!
//! This function selects the handling of NaN results during floating-point
//! computations. NaNs can either propagate (the default), or they can return
//! the default NaN.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_setNaNMode(uint32_t mode);
//*****************************************************************************
//
//! Selects the flush-to-zero mode.
//!
//! \param mode is the flush-to-zero mode; which is either
//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
//!
//! This function enables or disables the flush-to-zero mode of the
//! floating-point unit. When disabled (the default), the floating-point unit
//! is fully IEEE compliant. When enabled, values close to zero are treated as
//! zero, greatly improving the execution speed at the expense of some accuracy
//! (as well as IEEE compliance).
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_setFlushToZeroMode(uint32_t mode);
//*****************************************************************************
//
//! Selects the rounding mode for floating-point results.
//!
//! \param mode is the rounding mode.
//!
//! This function selects the rounding mode for floating-point results. After
//! a floating-point operation, the result is rounded toward the specified
//! value. The default mode is \b FPU_ROUND_NEAREST.
//!
//! The following rounding modes are available (as specified by \e mode):
//!
//! - \b FPU_ROUND_NEAREST - round toward the nearest value
//! - \b FPU_ROUND_POS_INF - round toward positive infinity
//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
//! - \b FPU_ROUND_ZERO - round toward zero
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
extern void FPU_setRoundingMode(uint32_t mode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __FPU_H__

356
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
Unescape Escape View File

@ -0,0 +1,356 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <gpio.h>
#include <debug.h>
#include <interrupt.h>
static const uint32_t GPIO_PORT_TO_INT[] =
{ 0x00,
INT_PORT1,
INT_PORT2,
INT_PORT3,
INT_PORT4,
INT_PORT5,
INT_PORT6 };
static const uint32_t GPIO_PORT_TO_BASE[] =
{ 0x00,
0x40004C00,
0x40004C01,
0x40004C20,
0x40004C21,
0x40004C40,
0x40004C41,
0x40004C60,
0x40004C61,
0x40004C80,
0x40004C81,
0x40004D20
};
void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
return;
}
void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins;
}
void GPIO_setAsPeripheralModuleFunctionOutputPin(uint_fast8_t selectedPort,
uint_fast16_t selectedPins, uint_fast8_t mode)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
break;
}
}
void GPIO_setAsPeripheralModuleFunctionInputPin(uint_fast8_t selectedPort,
uint_fast16_t selectedPins, uint_fast8_t mode)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
break;
}
}
void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
}
void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
}
void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins;
}
void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
}
void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
}
uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint16_t inputPinValue;
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins);
if (inputPinValue > 0)
return GPIO_INPUT_PIN_HIGH;
return GPIO_INPUT_PIN_LOW;
}
void GPIO_enableInterrupt(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIE) |= selectedPins;
}
void GPIO_disableInterrupt(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins;
}
uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
return HWREG16(baseAddress + OFS_PAIFG) & selectedPins;
}
void GPIO_clearInterruptFlag(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins;
}
void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort,
uint_fast16_t selectedPins, uint_fast8_t edgeSelect)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)
HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins;
else
HWREG16(baseAddress + OFS_PAIES) |= selectedPins;
}
uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
{
uint_fast16_t pendingInts;
uint32_t baseAddr;
pendingInts = GPIO_getInterruptStatus(selectedPort, 0xFFFF);
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
ASSERT(baseAddr != 0xFFFF);
switch (selectedPort)
{
case GPIO_PORT_P1:
case GPIO_PORT_P3:
case GPIO_PORT_P5:
case GPIO_PORT_P7:
case GPIO_PORT_P9:
return (HWREG8(baseAddr + OFS_P1IE) & pendingInts);
case GPIO_PORT_P2:
case GPIO_PORT_P4:
case GPIO_PORT_P6:
case GPIO_PORT_P8:
case GPIO_PORT_P10:
return (HWREG8(baseAddr + OFS_P2IE) & pendingInts);
case GPIO_PORT_PJ:
return (HWREG16(baseAddr + OFS_PAIE) & pendingInts);
default:
return 0;
}
}
void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
uint_fast8_t selectedPins)
{
uint32_t baseAddr;
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
HWREG8(baseAddr + OFS_PADS) |= selectedPins;
}
void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
uint_fast8_t selectedPins)
{
uint32_t baseAddr;
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
HWREG8(baseAddr + OFS_PADS) &= ~selectedPins;
}
void GPIO_registerInterrupt(uint_fast8_t selectedPort, void (*intHandler)(void))
{
uint32_t wPortInt;
wPortInt = GPIO_PORT_TO_INT[selectedPort];
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(wPortInt, intHandler);
//
// Enable the system control interrupt.
//
Interrupt_enableInterrupt(wPortInt);
}
void GPIO_unregisterInterrupt(uint_fast8_t selectedPort)
{
uint32_t wPortInt;
wPortInt = GPIO_PORT_TO_INT[selectedPort];
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(wPortInt);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(wPortInt);
}

1018
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
View File

File diff suppressed because it is too large Load Diff

744
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
Unescape Escape View File

@ -0,0 +1,744 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <i2c.h>
#include <interrupt.h>
#include <debug.h>
void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
{
uint16_t preScalarValue;
ASSERT(
(EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_B_I2C_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
|| (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate));
ASSERT(
(EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
|| (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
== config->autoSTOPGeneration)
|| (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
== config->autoSTOPGeneration));
/* Disable the USCI module and clears the other bits of control register */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
/* Configure Automatic STOP condition generation */
EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r & ~UCASTP_M)
| (config->autoSTOPGeneration);
/* Byte Count Threshold */
EUSCI_B_CMSIS(moduleInstance)->rTBCNT.r = config->byteCounterThreshold;
/*
* Configure as I2C master mode.
* UCMST = Master mode
* UCMODE_3 = I2C mode
* UCSYNC = Synchronous mode
*/
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_M)
| (config->selectClockSource | UCMST | UCMODE_3 | UCSYNC
| UCSWRST);
/*
* Compute the clock divider that achieves the fastest speed less than or
* equal to the desired speed. The numerator is biased to favor a larger
* clock divider so that the resulting clock is always less than or equal
* to the desired clock, never greater.
*/
preScalarValue = (uint16_t) (config->i2cClk / config->dataRate);
EUSCI_B_CMSIS(moduleInstance)->rBRW = preScalarValue;
}
void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable)
{
ASSERT(
(EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset)
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
/* Disable the USCI module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
/* Clear USCI master mode */
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCMST))
| (UCMODE_3 + UCSYNC);
/* Set up the slave address. */
HWREG16(moduleInstance + OFS_UCB0I2COA0 + slaveAddressOffset) = slaveAddress
+ slaveOwnAddressEnable;
}
void I2C_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 0;
}
void I2C_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
;
}
void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress)
{
/* Set the address of the slave with which the master will communicate */
EUSCI_B_CMSIS(moduleInstance)->rI2CSA.r = (slaveAddress);
}
void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
{
ASSERT(
(EUSCI_B_I2C_TRANSMIT_MODE == mode)
|| (EUSCI_B_I2C_RECEIVE_MODE == mode));
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
}
uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
{
//Set USCI in Receive mode
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTR_OFS) = 0;
//Send start
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= (UCTXSTT + UCTXSTP);
//Poll for receive interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
;
//Send single byte data.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
}
void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
{
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
}
uint8_t I2C_slaveGetData(uint32_t moduleInstance)
{
//Read a byte.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
}
uint8_t I2C_isBusBusy(uint32_t moduleInstance)
{
//Return the bus busy status.
return EUSCI_B_CMSIS(moduleInstance)->rSTATW.b.bBBUSY;
}
void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
{
//Store current TXIE status
uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
//Poll for transmit interrupt flag.
while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Poll for transmit interrupt flag.
while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
;
//Send stop condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTXSTP;
//Clear transmit interrupt flag before enabling interrupt again
EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(UCTXIFG);
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
}
bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
uint16_t txieStatus;
uint32_t timeout2 = timeout;
ASSERT(timeout > 0);
//Store current TXIE status
txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
//Poll for transmit interrupt flag.
while ((!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) && --timeout)
;
//Check if transfer timed out
if (timeout == 0)
return false;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
&& --timeout2)
;
//Check if transfer timed out
if (timeout2 == 0)
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
//Clear transmit interrupt flag before enabling interrupt again
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,UCTXIFG_OFS) = 0;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
return true;
}
void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
{
//Store current transmit interrupt enable
uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
//Poll for transmit interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
}
bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
uint16_t txieStatus;
ASSERT(timeout > 0);
//Store current transmit interrupt enable
txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
//Poll for transmit interrupt flag.
while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
&& --timeout))
;
//Check if transfer timed out
if (timeout == 0)
return false;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
return true;
}
void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
}
bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCTXIFG_OFS)) && --timeout)
;
//Check if transfer timed out
if (timeout == 0)
return false;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
return true;
}
void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Poll for transmit interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
}
bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
uint32_t timeout2 = timeout;
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCTXIFG_OFS)) && --timeout)
;
//Check if transfer timed out
if (timeout == 0)
return false;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
&& --timeout2)
;
//Check if transfer timed out
if (timeout2 == 0)
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
return true;
}
void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
}
bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
uint32_t timeout)
{
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
{
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCTXIFG_OFS)) && --timeout)
;
//Check if transfer timed out
if (timeout == 0)
return false;
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
return 0x01;
}
void I2C_masterReceiveStart(uint32_t moduleInstance)
{
//Set USCI in Receive mode
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCTR)) | UCTXSTT;
}
uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
{
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.a.bRXBUF;
}
uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
{
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS))
{
// Wait for RX buffer
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG, UCRXIFG_OFS))
;
}
/* Capture data from receive buffer after setting stop bit due to
MSP430 I2C critical timing. */
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
}
bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
uint8_t *txData, uint32_t timeout)
{
uint32_t timeout2 = timeout;
ASSERT(timeout > 0);
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS)
&& --timeout)
;
//Check if transfer timed out
if (timeout == 0)
return false;
// Wait for RX buffer
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
&& --timeout2)
;
//Check if transfer timed out
if (timeout2 == 0)
return false;
//Capture data from receive buffer after setting stop bit due to
//MSP430 I2C critical timing.
*txData = (EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF);
return true;
}
void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
{
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
}
uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
{
//Polling RXIFG0 if RXIE is not enabled
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCRXIE0_OFS))
{
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCRXIFG0_OFS))
;
}
//Read a byte.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
}
uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCB0RXBUF;
}
uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCB0TXBUF;
}
uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
{
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS);
}
bool I2C_masterIsStartSent(uint32_t moduleInstance)
{
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTT_OFS);
}
void I2C_masterSendStart(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTT_OFS) = 1;
}
void I2C_enableMultiMasterMode(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 1;
}
void I2C_disableMultiMasterMode(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 0;
}
void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Enable the interrupt masked bit
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= mask;
}
void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Disable the interrupt masked bit
EUSCI_B_CMSIS(moduleInstance)->rIE.r &= ~(mask);
}
void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Clear the I2C interrupt source.
EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
}
uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
{
ASSERT(
0x00
== (mask
& ~(EUSCI_B_I2C_STOP_INTERRUPT
+ EUSCI_B_I2C_START_INTERRUPT
+ EUSCI_B_I2C_NAK_INTERRUPT
+ EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+ EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+ EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+ EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+ EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+ EUSCI_B_I2C_RECEIVE_INTERRUPT0
+ EUSCI_B_I2C_RECEIVE_INTERRUPT1
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Return the interrupt status of the request masked bit.
return EUSCI_B_CMSIS(moduleInstance)->rIFG.r & mask;
}
uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
{
return I2C_getInterruptStatus(moduleInstance,
EUSCI_B_CMSIS(moduleInstance)->rIE.r);
}
uint_fast16_t I2C_getMode(uint32_t moduleInstance)
{
//Read the I2C mode.
return (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & UCTR);
}
void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
case EUSCI_B0_MODULE:
Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB0);
break;
case EUSCI_B1_MODULE:
Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_MODULE
case EUSCI_B2_MODULE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_MODULE
case EUSCI_B3_MODULE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
#endif
default:
ASSERT(false);
}
}
void I2C_unregisterInterrupt(uint32_t moduleInstance)
{
switch (moduleInstance)
{
case EUSCI_B0_MODULE:
Interrupt_disableInterrupt(INT_EUSCIB0);
Interrupt_unregisterInterrupt(INT_EUSCIB0);
break;
case EUSCI_B1_MODULE:
Interrupt_disableInterrupt(INT_EUSCIB1);
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_MODULE
case EUSCI_B2_MODULE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_MODULE
case EUSCI_B3_MODULE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
#endif
default:
ASSERT(false);
}
}

1407
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
View File

File diff suppressed because it is too large Load Diff

230
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
Unescape Escape View File

@ -0,0 +1,230 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family CMSIS Definitions
//
//****************************************************************************
#ifndef CMSIS_CCS_H_
#define CMSIS_CCS_H_
//*****************************************************************************
// CMSIS-compatible instruction calls
//*****************************************************************************
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
__asm(" wfi");
}
// Wait For Event
__attribute__( ( always_inline ) ) static inline void __wfe(void)
{
__asm(" wfe");
}
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
{
__asm(" cpsie i");
}
// Disable Interrupts
__attribute__( ( always_inline ) ) static inline void __disable_irq(void)
{
__asm(" cpsid i");
}
// Data Synchronization Barrier
__attribute__( ( always_inline ) ) static inline void __DSB(void)
{
__asm(" dsb");
}
#if (0)
// Get Main Stack Pointer
static inline uint32_t __get_MSP(void)
{
register uint32_t result;
//__asm (" mrs result, msp");
return(result);
}
// Set Main Stack Pointer
static inline void __set_MSP(uint32_t topOfMainStack)
{
asm(" .global topOfMainStack");
__asm (" msr msp, topOfMainStack");
}
// Get Priority Mask
static inline uint32_t __get_PRIMASK(void)
{
uint32_t result;
__asm (" mrs result, primask");
return(result);
}
// Set Priority Mask
static inline void __set_PRIMASK(uint32_t priMask)
{
__asm (" msr primask, priMask");
}
#endif
//
// v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __CLZ _norm
#define __SXTB _sxtb
#define __SXTH _sxth
#define __UXTB _uxtb
#define __UXTH _uxth
// CCS supports intrinsics to take advantage of the shift operand left/right
// before saturation extension of SSAT, but CMSIS does not take advantage
// of those, so tell the compiler to use a sat & shift left with a shift
// value of 0 whenever it encounters an SSAT
#define __SSAT(VAL, BITPOS) \
_ssatl(VAL , 0, BITPOS)
//
// Only define M4 based intrinsics if we're not using an M4
//
#if defined (__TI_TMS470_V7M4__)
//
// V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __QADD _sadd
#define __QDADD _sdadd
#define __QDSUB _sdsub
#define __SMLABB _smlabb
#define __SMLABT _smlabt
#define __SMLALBB _smlalbb
#define __SMLALBT _smlalbt
#define __SMLALTB _smlaltb
#define __SMLALTT _smlaltt
#define __SMLATB _smlatb
#define __SMLATT _smlatt
#define __SMLAWB _smlawb
#define __SMLAWT _smlawt
#define __SMULBB _smulbb
#define __SMULBT _smulbt
#define __SMULTB _smultb
#define __SMULTT _smultt
#define __SMULWB _smulwb
#define __SMULWT _smulwt
#define __QSUB _ssub
#define __SUBC _subc
//
// v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
//
#define __SHASX _shaddsubx
#define __SHSAX _shsubaddx
#define __PKHBT _pkhbt
#define __PKHTB _pkhtb
#define __QADD16 _qadd16
#define __QADD8 _qadd8
#define __QSUB16 _qsub16
#define __QSUB8 _qsub8
#define __QASX _saddsubx
#define __QSAX _qsubaddx
#define __SADD16 _sadd16
#define __SADD8 _sadd8
#define __SASX _saddsubx
#define __SEL _sel
#define __SHADD16 _shadd16
#define __SHADD8 _shadd8
#define __SHSUB16 _shsub16
#define __SHSUB8 _shsub8
#define __SMLAD _smlad
#define __SMLADX _smladx
#define __SMLALD _smlald
#define __SMLALDX _smlaldx
#define __SMLSD _smlsd
#define __SMLSDX _smlsdx
#define __SMLSLD _smlsld
#define __SMLSLDX _smlsldx
#define __SMMLA _smmla
#define __SMMLAR _smmlar
#define __SMMLS _smmls
#define __SMMLSR _smmlsr
#define __SMMUL _smmul
#define __SMMULR _smmulr
#define __SMUAD _smuad
#define __SMUADX _smuadx
#define __SMUSD _smusd
#define __SMUSDX _smusd
#define __SSAT16 _ssat16
#define __SSUB16 _ssub16
#define __SSUB8 _ssub8
#define __SSAX _ssubaddx
#define __SXTAB _sxtab
#define __SXTAB16 _sxtab16
#define __SXTAH _sxtah
#define __UMAAL _umaal
#define __UADD16 _uadd16
#define __UADD8 _uadd8
#define __UHADD16 _uhadd16
#define __UHADD8 _uhadd8
#define __UASX _uaddsubx
#define __UHSUB16 _uhsub16
#define __UHSUB8 _uhsub8
#define __UQADD16 _uqadd16
#define __UQADD8 _uqadd8
#define __UQASX _uqaddsubx
#define __UQSUB16 _uqsub16
#define __UQSUB8 _uqsub8
#define __UQSAX _uqsubaddx
#define __USAD8 _usad8
#define __USAT16 _usat16
#define __USUB16 _usub16
#define __USUB8 _usub8
#define __USAX _usubaddx
#define __UXTAB _uxtab
#define __UXTAB16 _uxtab16
#define __UXTAH _uxtah
#define __UXTB16 _uxtb16
#endif /*__TI_TMS470_V7M4__*/
#endif /*CMSIS_CCS_H_*/

1772
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
View File

File diff suppressed because it is too large Load Diff

673
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4_simd.h
Unescape Escape View File

@ -0,0 +1,673 @@
/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif

636
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
Unescape Escape View File

@ -0,0 +1,636 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

688
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
Unescape Escape View File

@ -0,0 +1,688 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

55
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
Unescape Escape View File

@ -0,0 +1,55 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family Generic Include File
//
// File creation date: 2015-01-02
//
//*****************************************************************************
#ifndef __MSP432_H__
#define __MSP432_H__
//****************************************************************************
// MSP432 devices
//****************************************************************************
#if defined (__MSP432P401R__)
#include "msp432p401r.h"
//****************************************************************************
// Failed to match a default include file
//****************************************************************************
#else
#error "Failed to match a default include file"
#endif
#endif // __MSP432_H__

55
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
Unescape Escape View File

@ -0,0 +1,55 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family Generic Include File
//
// File creation date: 2015-01-05
//
//*****************************************************************************
#ifndef __MSP432_H__
#define __MSP432_H__
//****************************************************************************
// MSP432 devices
//****************************************************************************
#if defined (__MSP432P401R__)
#include "msp432p401r.h"
//****************************************************************************
// Failed to match a default include file
//****************************************************************************
#else
#error "Failed to match a default include file"
#endif
#endif // __MSP432_H__

18130
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
View File

File diff suppressed because it is too large Load Diff

167
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
Unescape Escape View File

@ -0,0 +1,167 @@
//*****************************************************************************
//
// Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP430 intrinsic redefinitions for use with MSP432 Family Devices
//
//****************************************************************************
// Intrinsics with ARM equivalents
#if defined ( __TMS470__ ) /* TI CGT Compiler */
#include <cmsis_ccs.h>
#define __sleep() __wfi()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register(x) __set_MSP(x)
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() _enable_interrupts()
#define __enable_interrupts() _enable_interrupts()
#define __disable_interrupt() _disable_interrupts()
#define __disable_interrupts() _disable_interrupts()
#define __no_operation() __asm(" nop")
#elif defined ( __ICCARM__ ) /* IAR Compiler */
#include <stdint.h>
#define __INLINE inline
#include <cmsis_iar.h>
#define __sleep() __WFI()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register() __set_MSP()
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() __asm(" cpsie i")
#define __enable_interrupts() __asm(" cpsie i")
#define __disable_interrupt() __asm(" cpsid i")
#define __disable_interrupts() __asm(" cpsid i")
#define __no_operation() __asm(" nop")
// Intrinsics without ARM equivalents
#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#elif defined ( __CC_ARM ) /* ARM Compiler */
#define __sleep() __wfi
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register(x) __set_MSP(x)
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() __asm(" cpsie i")
#define __enable_interrupts() __asm(" cpsie i")
#define __disable_interrupt() __asm(" cpsid i")
#define __disable_interrupts() __asm(" cpsid i")
#define __no_operation() __asm(" nop")
// Intrinsics without ARM equivalents
#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#elif defined ( __GNUC__ ) /* GCC Compiler */
#define __sleep() __wfi()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
#define __get_SP_register() __get_MSP()
#define __set_SP_register(x) __set_MSP(x)
#define __get_interrupt_state() __get_PRIMASK()
#define __set_interrupt_state(x) __set_PRIMASK(x)
#define __enable_interrupt() __asm(" cpsie i")
#define __enable_interrupts() __asm(" cpsie i")
#define __disable_interrupt() __asm(" cpsid i")
#define __disable_interrupts() __asm(" cpsid i")
#define __no_operation() __asm(" nop")
// Intrinsics without ARM equivalents
#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#endif
// Intrinsics without ARM equivalents
#define __low_power_mode_0() { __sleep(); }
#define __low_power_mode_1() { __sleep(); }
#define __low_power_mode_2() { __sleep(); }
#define __low_power_mode_3() { __deep_sleep(); }
#define __low_power_mode_4() { __deep_sleep(); }
#define __data16_read_addr(x) (*((volatile uint32_t *)(x)))
#define __data20_read_char(x) (*((volatile uint8_t *)(x)))
#define __data20_read_short(x) (*((volatile uint16_t *)(x)))
#define __data20_read_long(x) (*((volatile uint32_t *)(x)))
#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) }
#define __get_SR_register() 0
#define __get_SR_register_on_exit() 0

537
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
Unescape Escape View File

@ -0,0 +1,537 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <debug.h>
#include <cpu.h>
#include <interrupt.h>
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
static const uint32_t g_pulPriority[] =
{ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4,
NVIC_APINT_PRIGROUP_5_3, NVIC_APINT_PRIGROUP_6_2,
NVIC_APINT_PRIGROUP_7_1 };
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
static const uint32_t g_pulRegs[] =
{ 0, NVIC_SYS_PRI1_R, NVIC_SYS_PRI2_R, NVIC_SYS_PRI3_R, NVIC_PRI0_R,
NVIC_PRI1_R, NVIC_PRI2_R, NVIC_PRI3_R, NVIC_PRI4_R, NVIC_PRI5_R,
NVIC_PRI6_R, NVIC_PRI7_R, NVIC_PRI8_R, NVIC_PRI9_R, NVIC_PRI10_R,
NVIC_PRI11_R, NVIC_PRI12_R, NVIC_PRI13_R, NVIC_PRI14_R, NVIC_PRI15_R };
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const uint32_t g_pulEnRegs[] =
{ NVIC_EN0_R, NVIC_EN1_R };
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const uint32_t g_pulDisRegs[] =
{ NVIC_DIS0_R, NVIC_DIS1_R };
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const uint32_t g_pulPendRegs[] =
{ NVIC_PEND0_R, NVIC_PEND1_R };
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const uint32_t g_pulUnpendRegs[] =
{ NVIC_UNPEND0_R, NVIC_UNPEND1_R };
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
static void IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while (1)
{
}
}
//*****************************************************************************
//
// The processor vector table.
//
// This contains a list of the handlers for the various interrupt sources in
// the system. The layout of this list is defined by the hardware; assertion
// of an interrupt causes the processor to start executing directly at the
// address given in the corresponding location in this list.
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) @ "VTABLE";
#elif defined(ccs)
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
void (*g_pfnRAMVectors[NUM_INTERRUPTS + 1])(void);
#else
static __attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) __attribute__((aligned(1024)));
#endif
bool Interrupt_enableMaster(void)
{
//
// Enable processor interrupts.
//
return (CPU_cpsie());
}
bool Interrupt_disableMaster(void)
{
//
// Disable processor interrupts.
//
return (CPU_cpsid());
}
void Interrupt_registerInterrupt(uint32_t interruptNumber,
void (*intHandler)(void))
{
uint32_t ulIdx, ulValue;
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Make sure that the RAM vector table is correctly aligned.
//
ASSERT(((uint32_t) g_pfnRAMVectors & 0x000000ff) == 0);
//
// See if the RAM vector table has been initialized.
//
if (SCB->VTOR != (uint32_t) g_pfnRAMVectors)
{
//
// Copy the vector table from the beginning of FLASH to the RAM vector
// table.
//
ulValue = SCB->VTOR;
for (ulIdx = 0; ulIdx < (NUM_INTERRUPTS + 1); ulIdx++)
{
g_pfnRAMVectors[ulIdx] = (void (*)(void)) HWREG32(
(ulIdx * 4) + ulValue);
}
//
// Point the NVIC at the RAM vector table.
//
SCB->VTOR = (uint32_t) g_pfnRAMVectors;
}
//
// Save the interrupt handler.
//
g_pfnRAMVectors[interruptNumber] = intHandler;
}
void Interrupt_unregisterInterrupt(uint32_t interruptNumber)
{
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Reset the interrupt handler.
//
g_pfnRAMVectors[interruptNumber] = IntDefaultHandler;
}
void Interrupt_setPriorityGrouping(uint32_t bits)
{
//
// Check the arguments.
//
ASSERT(bits < NUM_PRIORITY);
//
// Set the priority grouping.
//
SCB->AIRCR = SCB_AIRCR_VECTKEY_M | g_pulPriority[bits];
}
uint32_t Interrupt_getPriorityGrouping(void)
{
uint32_t ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = SCB->AIRCR & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for (ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
{
//
// Stop looping if this value matches.
//
if (ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return (ulLoop);
}
void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority)
{
uint32_t ulTemp;
//
// Check the arguments.
//
ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
//
// Set the interrupt priority.
//
ulTemp = HWREG32(g_pulRegs[interruptNumber >> 2]);
ulTemp &= ~(0xFF << (8 * (interruptNumber & 3)));
ulTemp |= priority << (8 * (interruptNumber & 3));
HWREG32 (g_pulRegs[interruptNumber >> 2]) = ulTemp;
}
uint8_t Interrupt_getPriority(uint32_t interruptNumber)
{
//
// Check the arguments.
//
ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
//
// Return the interrupt priority.
//
return ((HWREG32(g_pulRegs[interruptNumber >> 2])
>> (8 * (interruptNumber & 3))) & 0xFF);
}
void Interrupt_enableInterrupt(uint32_t interruptNumber)
{
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Determine the interrupt to enable.
//
if (interruptNumber == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA;
} else if (interruptNumber == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA;
} else if (interruptNumber == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
} else if (interruptNumber >= 16)
{
//
// Enable the general interrupt.
//
HWREG32 (g_pulEnRegs[(interruptNumber - 16) / 32]) = 1
<< ((interruptNumber - 16) & 31);
}
}
void Interrupt_disableInterrupt(uint32_t interruptNumber)
{
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Determine the interrupt to disable.
//
if (interruptNumber == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA);
} else if (interruptNumber == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA);
} else if (interruptNumber == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA);
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
} else if (interruptNumber >= 16)
{
//
// Disable the general interrupt.
//
HWREG32 (g_pulDisRegs[(interruptNumber - 16) / 32]) = 1
<< ((interruptNumber - 16) & 31);
}
}
bool Interrupt_isEnabled(uint32_t interruptNumber)
{
uint32_t ulRet;
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Initialize the return value.
//
ulRet = 0;
//
// Determine the interrupt to disable.
//
if (interruptNumber == FAULT_MPU)
{
//
// Check the MemManage interrupt.
//
ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA;
} else if (interruptNumber == FAULT_BUS)
{
//
// Check the bus fault interrupt.
//
ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA;
} else if (interruptNumber == FAULT_USAGE)
{
//
// Check the usage fault interrupt.
//
ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Check the System Tick interrupt.
//
ulRet = SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
} else if (interruptNumber >= 16)
{
//
// Check the general interrupt.
//
ulRet = HWREG32(g_pulEnRegs[(interruptNumber - 16) / 32])
& (1 << ((interruptNumber - 16) & 31));
}
return (ulRet);
}
void Interrupt_pendInterrupt(uint32_t interruptNumber)
{
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Determine the interrupt to pend.
//
if (interruptNumber == FAULT_NMI)
{
//
// Pend the NMI interrupt.
//
SCB->ICSR |= SCB_ICSR_NMIPENDSET;
} else if (interruptNumber == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSVSET;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSTSET;
} else if (interruptNumber >= 16)
{
//
// Pend the general interrupt.
//
HWREG32 (g_pulPendRegs[(interruptNumber - 16) / 32]) = 1
<< ((interruptNumber - 16) & 31);
}
}
void Interrupt_unpendInterrupt(uint32_t interruptNumber)
{
//
// Check the arguments.
//
ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
//
// Determine the interrupt to unpend.
//
if (interruptNumber == FAULT_PENDSV)
{
//
// Unpend the PendSV interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSVCLR;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSTCLR;
} else if (interruptNumber >= 16)
{
//
// Unpend the general interrupt.
//
HWREG32 (g_pulUnpendRegs[(interruptNumber - 16) / 32]) = 1
<< ((interruptNumber - 16) & 31);
}
}
void Interrupt_setPriorityMask(uint8_t priorityMask)
{
CPU_basepriSet(priorityMask);
}
uint8_t Interrupt_getPriorityMask(void)
{
return (CPU_basepriGet());
}
void Interrupt_setVectorTableAddress(uint32_t addr)
{
SCB->VTOR = addr;
}
uint32_t Interrupt_getVectorTableAddress(void)
{
return SCB->VTOR;
}
void Interrupt_enableSleepOnIsrExit(void)
{
SCB->SCR |= SCB_SCR_SLEEPONEXIT;
}
void Interrupt_disableSleepOnIsrExit(void)
{
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT;
}

519
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
Unescape Escape View File

@ -0,0 +1,519 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
#define NUM_PRIORITY 8
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
#define NVIC_SYS_PRI1_R 0xE000ED18 // System Handler Priority 1
#define NVIC_SYS_PRI2_R 0xE000ED1C // System Handler Priority 2
#define NVIC_SYS_PRI3_R 0xE000ED20 // System Handler Priority 3
#define NVIC_PRI0_R 0xE000E400 // Interrupt 0-3 Priority
#define NVIC_PRI1_R 0xE000E404 // Interrupt 4-7 Priority
#define NVIC_PRI2_R 0xE000E408 // Interrupt 8-11 Priority
#define NVIC_PRI3_R 0xE000E40C // Interrupt 12-15 Priority
#define NVIC_PRI4_R 0xE000E410 // Interrupt 16-19 Priority
#define NVIC_PRI5_R 0xE000E414 // Interrupt 20-23 Priority
#define NVIC_PRI6_R 0xE000E418 // Interrupt 24-27 Priority
#define NVIC_PRI7_R 0xE000E41C // Interrupt 28-31 Priority
#define NVIC_PRI8_R 0xE000E420 // Interrupt 32-35 Priority
#define NVIC_PRI9_R 0xE000E424 // Interrupt 36-39 Priority
#define NVIC_PRI10_R 0xE000E428 // Interrupt 40-43 Priority
#define NVIC_PRI11_R 0xE000E42C // Interrupt 44-47 Priority
#define NVIC_PRI12_R 0xE000E430 // Interrupt 48-51 Priority
#define NVIC_PRI13_R 0xE000E434 // Interrupt 52-55 Priority
#define NVIC_PRI14_R 0xE000E438 // Interrupt 56-59 Priority
#define NVIC_PRI15_R 0xE000E43C // Interrupt 60-63 Priority
#define NVIC_EN0_R 0xE000E100 // Interrupt 0-31 Set Enable
#define NVIC_EN1_R 0xE000E104 // Interrupt 32-54 Set Enable
#define NVIC_DIS0_R 0xE000E180 // Interrupt 0-31 Clear Enable
#define NVIC_DIS1_R 0xE000E184 // Interrupt 32-54 Clear Enable
#define NVIC_PEND0_R 0xE000E200 // Interrupt 0-31 Set Pending
#define NVIC_PEND1_R 0xE000E204 // Interrupt 32-54 Set Pending
#define NVIC_UNPEND0_R 0xE000E280 // Interrupt 0-31 Clear Pending
#define NVIC_UNPEND1_R 0xE000E284 // Interrupt 32-54 Clear Pending
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! This function allows the processor to respond to interrupts. This function
//! does not affect the set of interrupts enabled in the interrupt controller;
//! it just gates the single interrupt from the controller to the processor.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
extern bool Interrupt_enableMaster(void);
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! This function prevents the processor from receiving interrupts. This
//! function does not affect the set of interrupts enabled in the interrupt
//! controller; it just gates the single interrupt from the controller to the
//! processor.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
extern bool Interrupt_disableMaster(void);
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//! \param intHandler is a pointer to the function to be called.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise the NVIC does not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_registerInterrupt(uint32_t interruptNumber,
void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source is
//! automatically disabled (via Interrupt_disableInterrupt()) if necessary.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_unregisterInterrupt(uint32_t interruptNumber);
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param bits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! sub-priority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the MSP432 family, three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
//! seven have the same effect.
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_setPriorityGrouping(uint32_t bits);
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! sub-priority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
extern uint32_t Interrupt_getPriorityGrouping(void);
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param interruptNumber specifies the interrupt in question.
//! \param priority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the MSP432 family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
//! hardware priority mechanism on a future part. This arrangement allows
//! priorities to migrate to different NVIC implementations without changing
//! the gross prioritization of the interrupts.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority);
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param interruptNumber specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See
//! Interrupt_setPriority() for a definition of the priority value.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
extern uint8_t Interrupt_getPriority(uint32_t interruptNumber);
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! Valid values will vary from part to part, so it is important to check the
//! device specific datasheet, however for MSP432 101 the following values can
//! be provided:
//! - \b FAULT_NMI
//! - \b FAULT_HARD
//! - \b FAULT_MPU
//! - \b FAULT_BUS
//! - \b FAULT_USAGE
//! - \b FAULT_SVCALL
//! - \b FAULT_DEBUG
//! - \b FAULT_PENDSV
//! - \b FAULT_SYSTICK
//! - \b INT_PSS
//! - \b INT_CS
//! - \b INT_PCM
//! - \b INT_WDT_A
//! - \b INT_FPU
//! - \b INT_FLCTL
//! - \b INT_COMP0
//! - \b INT_COMP1
//! - \b INT_TA0_0
//! - \b INT_TA0_N
//! - \b INT_TA1_0
//! - \b INT_TA1_N
//! - \b INT_TA2_0
//! - \b INT_TA2_N
//! - \b INT_TA3_0
//! - \b INT_TA3_N
//! - \b INT_EUSCIA0
//! - \b INT_EUSCIA1
//! - \b INT_EUSCIA2
//! - \b INT_EUSCIA3
//! - \b INT_EUSCIB0
//! - \b INT_EUSCIB1
//! - \b INT_EUSCIB2
//! - \b INT_EUSCIB3
//! - \b INT_ADC14
//! - \b INT_T32_INT1
//! - \b INT_T32_INT2
//! - \b INT_T32_INTC
//! - \b INT_AES
//! - \b INT_RTCC
//! - \b INT_DMA_ERR
//! - \b INT_DMA_INT3
//! - \b INT_DMA_INT2
//! - \b INT_DMA_INT1
//! - \b INT_DMA_INT0
//! - \b INT_PORT1
//! - \b INT_PORT2
//! - \b INT_PORT3
//! - \b INT_PORT4
//! - \b INT_PORT5
//! - \b INT_PORT6
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_enableInterrupt(uint32_t interruptNumber);
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_disableInterrupt(uint32_t interruptNumber);
//*****************************************************************************
//
//! Returns if a peripheral interrupt is enabled.
//!
//! \param interruptNumber specifies the interrupt to check.
//!
//! This function checks if the specified interrupt is enabled in the interrupt
//! controller.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return A non-zero value if the interrupt is enabled.
//
//*****************************************************************************
extern bool Interrupt_isEnabled(uint32_t interruptNumber);
//*****************************************************************************
//
//! Pends an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. Pending an
//! interrupt causes the interrupt controller to execute the corresponding
//! interrupt handler at the next available time, based on the current
//! interrupt state priorities. For example, if called by a higher priority
//! interrupt handler, the specified interrupt handler is not called until
//! after the current interrupt handler has completed execution. The interrupt
//! must have been enabled for it to be called.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_pendInterrupt(uint32_t interruptNumber);
//*****************************************************************************
//
//! Un-pends an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be un-pended.
//!
//! The specified interrupt is un-pended in the interrupt controller. This
//! will cause any previously generated interrupts that have not been handled
//! yet (due to higher priority interrupts or the interrupt no having been
//! enabled yet) to be discarded.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_unpendInterrupt(uint32_t interruptNumber);
//*****************************************************************************
//
//! Sets the priority masking level
//!
//! \param priorityMask is the priority level that is masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level are masked. Masking
//! interrupts can be used to globally disable a set of interrupts with
//! priority below a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the MSP432 family), so any
//! prioritization must be performed in those bits.
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_setPriorityMask(uint8_t priorityMask);
//*****************************************************************************
//
//! Gets the priority masking level
//!
//! This function gets the current setting of the interrupt priority masking
//! level. The value returned is the priority level such that all interrupts
//! of that and lesser priority are masked. A value of 0 means that priority
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the MSP432 family), so any
//! prioritization must be performed in those bits.
//!
//! \return Returns the value of the interrupt priority level mask.
//
//*****************************************************************************
extern uint8_t Interrupt_getPriorityMask(void);
//*****************************************************************************
//
//! Sets the address of the vector table. This function is for advanced users
//! who might want to switch between multiple instances of vector tables
//! (perhaps between flash/ram).
//!
//! \param addr is the new address of the vector table.
//!
//! \return None.
//
//*****************************************************************************
extern void Interrupt_setVectorTableAddress(uint32_t addr);
//*****************************************************************************
//
//! Returns the address of the interrupt vector table.
//!
//! \return Address of the vector table.
//
//*****************************************************************************
extern uint32_t Interrupt_getVectorTableAddress(void);
//*****************************************************************************
//
//! Enables the processor to sleep when exiting an ISR. For low power operation,
//! this is ideal as power cycles are not wasted with the processing required
//! for waking up from an ISR and going back to sleep.
//!
//! \return Address of the vector table.
//
//*****************************************************************************
extern void Interrupt_enableSleepOnIsrExit(void);
//*****************************************************************************
//
//! Enables the processor to sleep when exiting an ISR. For low power operation,
//! this is ideal as power cycles are not wasted with the processing required
//! for waking up from an ISR and going back to sleep.
//!
//! \return Address of the vector table.
//
//*****************************************************************************
extern void Interrupt_disableSleepOnIsrExit(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __INTERRUPT_H__

194
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
Unescape Escape View File

@ -0,0 +1,194 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <debug.h>
#include <interrupt.h>
#include <mpu.h>
void MPU_enableModule(uint32_t mpuConfig)
{
//
// Check the arguments.
//
ASSERT(!(mpuConfig & ~(MPU_CONFIG_PRIV_DEFAULT | MPU_CONFIG_HARDFLT_NMI)));
//
// Set the MPU control bits according to the flags passed by the user,
// and also set the enable bit.
//
MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE;
}
void MPU_disableModule(void)
{
//
// Turn off the MPU enable bit.
//
MPU->CTRL &= ~MPU_CTRL_ENABLE;
}
uint32_t MPU_getRegionCount(void)
{
//
// Read the DREGION field of the MPU type register and mask off
// the bits of interest to get the count of regions.
//
return ((MPU->TYPE & MPU_TYPE_DREGION_M) >> NVIC_MPU_TYPE_DREGION_S);
}
void MPU_enableRegion(uint32_t region)
{
//
// Check the arguments.
//
ASSERT(region < 8);
//
// Select the region to modify.
//
MPU->RNR = region;
//
// Modify the enable bit in the region attributes.
//
MPU->RASR |= MPU_RASR_ENABLE;
}
void MPU_disableRegion(uint32_t region)
{
//
// Check the arguments.
//
ASSERT(region < 8);
//
// Select the region to modify.
//
MPU->RNR = region;
//
// Modify the enable bit in the region attributes.
//
MPU->RASR &= ~MPU_RASR_ENABLE;
}
void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags)
{
//
// Check the arguments.
//
ASSERT(region < 8);
//
// Program the base address, use the region field to select the
// region at the same time.
//
MPU->RBAR = addr | region | MPU_RBAR_VALID;
//
// Program the region attributes. Set the TEX field and the S, C,
// and B bits to fixed values that are suitable for all Stellaris
// memory.
//
MPU->RASR = (flags & ~(MPU_RASR_TEX_M | MPU_RASR_C)) | MPU_RASR_S
| MPU_RASR_B;
}
void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags)
{
//
// Check the arguments.
//
ASSERT(region < 8);
ASSERT(addr);
ASSERT(pflags);
//
// Select the region to get.
//
MPU->RNR = region;
//
// Read and store the base address for the region.
//
*addr = MPU->RBAR & MPU_RBAR_ADDR_M;
//
// Read and store the region attributes.
//
*pflags = MPU->RASR;
}
void MPU_registerInterrupt(void (*intHandler)(void))
{
//
// Check the arguments.
//
ASSERT(intHandler);
//
// Register the interrupt handler.
//
Interrupt_registerInterrupt(FAULT_MPU, intHandler);
}
void MPU_unregisterInterrupt(void)
{
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(FAULT_MPU);
}
void MPU_enableInterrupt(void)
{
//
// Enable the memory management fault.
//
Interrupt_enableInterrupt(FAULT_MPU);
}
void MPU_disableInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(FAULT_MPU);
}

449
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
Unescape Escape View File

@ -0,0 +1,449 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __MPU_H__
#define __MPU_H__
//*****************************************************************************
//
//! \addtogroup mpu_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <msp.h>
#include <stdint.h>
//*****************************************************************************
//
// Flags that can be passed to MPU_enableModule.
//
//*****************************************************************************
#define MPU_CONFIG_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA
#define MPU_CONFIG_HARDFLT_NMI MPU_CTRL_HFNMIENA
#define MPU_CONFIG_NONE 0
//*****************************************************************************
//
// Flags for the region size to be passed to MPU_setRegion.
//
//*****************************************************************************
#define MPU_RGN_SIZE_32B (4 << 1)
#define MPU_RGN_SIZE_64B (5 << 1)
#define MPU_RGN_SIZE_128B (6 << 1)
#define MPU_RGN_SIZE_256B (7 << 1)
#define MPU_RGN_SIZE_512B (8 << 1)
#define MPU_RGN_SIZE_1K (9 << 1)
#define MPU_RGN_SIZE_2K (10 << 1)
#define MPU_RGN_SIZE_4K (11 << 1)
#define MPU_RGN_SIZE_8K (12 << 1)
#define MPU_RGN_SIZE_16K (13 << 1)
#define MPU_RGN_SIZE_32K (14 << 1)
#define MPU_RGN_SIZE_64K (15 << 1)
#define MPU_RGN_SIZE_128K (16 << 1)
#define MPU_RGN_SIZE_256K (17 << 1)
#define MPU_RGN_SIZE_512K (18 << 1)
#define MPU_RGN_SIZE_1M (19 << 1)
#define MPU_RGN_SIZE_2M (20 << 1)
#define MPU_RGN_SIZE_4M (21 << 1)
#define MPU_RGN_SIZE_8M (22 << 1)
#define MPU_RGN_SIZE_16M (23 << 1)
#define MPU_RGN_SIZE_32M (24 << 1)
#define MPU_RGN_SIZE_64M (25 << 1)
#define MPU_RGN_SIZE_128M (26 << 1)
#define MPU_RGN_SIZE_256M (27 << 1)
#define MPU_RGN_SIZE_512M (28 << 1)
#define MPU_RGN_SIZE_1G (29 << 1)
#define MPU_RGN_SIZE_2G (30 << 1)
#define MPU_RGN_SIZE_4G (31 << 1)
//*****************************************************************************
//
// Flags for the permissions to be passed to MPU_setRegion.
//
//*****************************************************************************
#define MPU_RGN_PERM_EXEC 0x00000000
#define MPU_RGN_PERM_NOEXEC 0x10000000
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
//*****************************************************************************
//
// Flags for the sub-region to be passed to MPU_setRegion.
//
//*****************************************************************************
#define MPU_SUB_RGN_DISABLE_0 0x00000100
#define MPU_SUB_RGN_DISABLE_1 0x00000200
#define MPU_SUB_RGN_DISABLE_2 0x00000400
#define MPU_SUB_RGN_DISABLE_3 0x00000800
#define MPU_SUB_RGN_DISABLE_4 0x00001000
#define MPU_SUB_RGN_DISABLE_5 0x00002000
#define MPU_SUB_RGN_DISABLE_6 0x00004000
#define MPU_SUB_RGN_DISABLE_7 0x00008000
//*****************************************************************************
//
// Flags to enable or disable a region, to be passed to MPU_setRegion.
//
//*****************************************************************************
#define MPU_RGN_ENABLE 1
#define MPU_RGN_DISABLE 0
#define NVIC_MPU_TYPE_DREGION_S 8
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables and configures the MPU for use.
//!
//! \param mpuConfig is the logical OR of the possible configurations.
//!
//! This function enables the Cortex-M memory protection unit. It also
//! configures the default behavior when in privileged mode and while handling
//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
//! be set by calling MPU_setRegion() or else by enabling the default region for
//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
//! MPU_enableModule(). Once the MPU is enabled, a memory management fault is
//! generated for memory access violations.
//!
//! The \e mpuConfig parameter should be the logical OR of any of the
//! following:
//!
//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
//! privileged mode and when no other regions are defined. If this option
//! is not enabled, then there must be at least one valid region already
//! defined when the MPU is enabled.
//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
//! exception handler. If this option is not enabled, then the MPU is
//! disabled while in one of these exception handlers and the default
//! memory map is applied.
//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
//! no default memory map is provided in privileged mode, and the MPU is
//! not enabled in the fault handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_enableModule(uint32_t mpuConfig);
//*****************************************************************************
//
//! Disables the MPU for use.
//!
//! This function disables the Cortex-M memory protection unit. When the
//! MPU is disabled, the default memory map is used and memory management
//! faults are not generated.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_disableModule(void);
//*****************************************************************************
//
//! Gets the count of regions supported by the MPU.
//!
//! This function is used to get the total number of regions that are supported
//! by the MPU, including regions that are already programmed.
//!
//! \return The number of memory protection regions that are available
//! for programming using MPU_setRegion().
//
//*****************************************************************************
extern uint32_t MPU_getRegionCount(void);
//*****************************************************************************
//
//! Enables a specific region.
//!
//! \param region is the region number to enable. Valid values are between
//! 0 and 7 inclusively.
//!
//! This function is used to enable a memory protection region. The region
//! should already be configured with the MPU_setRegion() function. Once
//! enabled, the memory protection rules of the region are applied and access
//! violations cause a memory management fault.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_enableRegion(uint32_t region);
//*****************************************************************************
//
//! Disables a specific region.
//!
//! \param region is the region number to disable. Valid values are between
//! 0 and 7 inclusively.
//!
//! This function is used to disable a previously enabled memory protection
//! region. The region remains configured if it is not overwritten with
//! another call to MPU_setRegion(), and can be enabled again by calling
//! MPU_enableRegion().
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_disableRegion(uint32_t region);
//*****************************************************************************
//
//! Sets up the access rules for a specific region.
//!
//! \param region is the region number to set up.
//! \param addr is the base address of the region. It must be aligned
//! according to the size of the region specified in flags.
//! \param flags is a set of flags to define the attributes of the region.
//!
//! This function sets up the protection rules for a region. The region has
//! a base address and a set of attributes including the size. The base
//! address parameter, \e addr, must be aligned according to the size, and
//! the size must be a power of 2.
//!
//! \param region is the region number to set. Valid values are between
//! 0 and 7 inclusively.
//!
//! The \e flags parameter is the logical OR of all of the attributes
//! of the region. It is a combination of choices for region size,
//! execute permission, read/write permissions, disabled sub-regions,
//! and a flag to determine if the region is enabled.
//!
//! The size flag determines the size of a region and must be one of the
//! following:
//!
//! - \b MPU_RGN_SIZE_32B
//! - \b MPU_RGN_SIZE_64B
//! - \b MPU_RGN_SIZE_128B
//! - \b MPU_RGN_SIZE_256B
//! - \b MPU_RGN_SIZE_512B
//! - \b MPU_RGN_SIZE_1K
//! - \b MPU_RGN_SIZE_2K
//! - \b MPU_RGN_SIZE_4K
//! - \b MPU_RGN_SIZE_8K
//! - \b MPU_RGN_SIZE_16K
//! - \b MPU_RGN_SIZE_32K
//! - \b MPU_RGN_SIZE_64K
//! - \b MPU_RGN_SIZE_128K
//! - \b MPU_RGN_SIZE_256K
//! - \b MPU_RGN_SIZE_512K
//! - \b MPU_RGN_SIZE_1M
//! - \b MPU_RGN_SIZE_2M
//! - \b MPU_RGN_SIZE_4M
//! - \b MPU_RGN_SIZE_8M
//! - \b MPU_RGN_SIZE_16M
//! - \b MPU_RGN_SIZE_32M
//! - \b MPU_RGN_SIZE_64M
//! - \b MPU_RGN_SIZE_128M
//! - \b MPU_RGN_SIZE_256M
//! - \b MPU_RGN_SIZE_512M
//! - \b MPU_RGN_SIZE_1G
//! - \b MPU_RGN_SIZE_2G
//! - \b MPU_RGN_SIZE_4G
//!
//! The execute permission flag must be one of the following:
//!
//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
//!
//! The read/write access permissions are applied separately for the
//! privileged and user modes. The read/write access flags must be one
//! of the following:
//!
//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
//!
//! The region is automatically divided into 8 equally-sized sub-regions by
//! the MPU. Sub-regions can only be used in regions of size 256 bytes
//! or larger. Any of these 8 sub-regions can be disabled, allowing for
//! creation of ``holes'' in a region which can be left open, or overlaid
//! by another region with different attributes. Any of the 8 sub-regions
//! can be disabled with a logical OR of any of the following flags:
//!
//! - \b MPU_SUB_RGN_DISABLE_0
//! - \b MPU_SUB_RGN_DISABLE_1
//! - \b MPU_SUB_RGN_DISABLE_2
//! - \b MPU_SUB_RGN_DISABLE_3
//! - \b MPU_SUB_RGN_DISABLE_4
//! - \b MPU_SUB_RGN_DISABLE_5
//! - \b MPU_SUB_RGN_DISABLE_6
//! - \b MPU_SUB_RGN_DISABLE_7
//!
//! Finally, the region can be initially enabled or disabled with one of
//! the following flags:
//!
//! - \b MPU_RGN_ENABLE
//! - \b MPU_RGN_DISABLE
//!
//! As an example, to set a region with the following attributes: size of
//! 32 KB, execution enabled, read-only for both privileged and user, one
//! sub-region disabled, and initially enabled; the \e flags parameter would
//! have the following value:
//!
//! <code>
//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
//! </code>
//!
//! \note This function writes to multiple registers and is not protected
//! from interrupts. It is possible that an interrupt which accesses a
//! region may occur while that region is in the process of being changed.
//! The safest way to handle this is to disable a region before changing it.
//! Refer to the discussion of this in the API Detailed Description section.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags);
//*****************************************************************************
//
//! Gets the current settings for a specific region.
//!
//! \param region is the region number to get. Valid values are between
//! 0 and 7 inclusively.
//! \param addr points to storage for the base address of the region.
//! \param pflags points to the attribute flags for the region.
//!
//! This function retrieves the configuration of a specific region. The
//! meanings and format of the parameters is the same as that of the
//! MPU_setRegion() function.
//!
//! This function can be used to save the configuration of a region for later
//! use with the MPU_setRegion() function. The region's enable state is
//! preserved in the attributes that are saved.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags);
//*****************************************************************************
//
//! Registers an interrupt handler for the memory management fault.
//!
//! \param intHandler is a pointer to the function to be called when the
//! memory management fault occurs.
//!
//! This function sets and enables the handler to be called when the MPU
//! generates a memory management fault due to a protection region access
//! violation.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters an interrupt handler for the memory management fault.
//!
//! This function disables and clears the handler to be called when a
//! memory management fault occurs.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_unregisterInterrupt(void);
//*****************************************************************************
//
//! Enables the interrupt for the memory management fault.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_enableInterrupt(void);
//*****************************************************************************
//
//! Disables the interrupt for the memory management fault.
//!
//! \return None.
//
//*****************************************************************************
extern void MPU_disableInterrupt(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __MPU_H__

525
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
Unescape Escape View File

@ -0,0 +1,525 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <pcm.h>
#include <debug.h>
#include <interrupt.h>
#include <cpu.h>
bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
{
return PCM_setCoreVoltageLevelWithTimeout(voltageLevel, 0);
}
bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
uint32_t timeOut)
{
uint8_t powerMode, bCurrentVoltageLevel;
uint32_t regValue;
bool boolTimeout;
ASSERT(voltageLevel == PCM_VCORE0 || voltageLevel == PCM_VCORE1);
/* Getting current power mode and level */
powerMode = PCM_getPowerMode();
bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
boolTimeout = timeOut > 0 ? true : false;
/* If we are already at the power mode they requested, return */
if (bCurrentVoltageLevel == voltageLevel)
return true;
while (bCurrentVoltageLevel != voltageLevel)
{
regValue = PCM->rCTL0.r;
switch (PCM_getPowerState())
{
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
case PCM_AM_LDO_VCORE0:
PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE1)
| (regValue & ~(PCMKEY_M | AMR_M)));
break;
case PCM_AM_LF_VCORE0:
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LDO_VCORE1:
PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE0)
| (regValue & ~(PCMKEY_M | AMR_M)));
break;
default:
ASSERT(false);
}
while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
{
if (boolTimeout && !(--timeOut))
return false;
}
bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
}
/* Changing the power mode if we are stuck in LDO mode */
if (powerMode != PCM_getPowerMode())
{
if (powerMode == PCM_DCDC_MODE)
return PCM_setPowerMode(PCM_DCDC_MODE);
else
return PCM_setPowerMode(PCM_LF_MODE);
}
return true;
}
bool PCM_setPowerMode(uint_fast8_t powerMode)
{
return PCM_setPowerModeWithTimeout(powerMode, 0);
}
uint8_t PCM_getPowerMode(void)
{
uint8_t currentPowerState;
currentPowerState = PCM_getPowerState();
switch (currentPowerState)
{
case PCM_AM_LDO_VCORE0:
case PCM_AM_LDO_VCORE1:
case PCM_LPM0_LDO_VCORE0:
case PCM_LPM0_LDO_VCORE1:
return PCM_LDO_MODE;
case PCM_AM_DCDC_VCORE0:
case PCM_AM_DCDC_VCORE1:
case PCM_LPM0_DCDC_VCORE0:
case PCM_LPM0_DCDC_VCORE1:
return PCM_DCDC_MODE;
case PCM_LPM0_LF_VCORE0:
case PCM_LPM0_LF_VCORE1:
case PCM_AM_LF_VCORE1:
case PCM_AM_LF_VCORE0:
return PCM_LF_MODE;
default:
ASSERT(false);
return false;
}
}
uint8_t PCM_getCoreVoltageLevel(void)
{
uint8_t currentPowerState = PCM_getPowerState();
switch (currentPowerState)
{
case PCM_AM_LDO_VCORE0:
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LF_VCORE0:
case PCM_LPM0_LDO_VCORE0:
case PCM_LPM0_DCDC_VCORE0:
case PCM_LPM0_LF_VCORE0:
return PCM_VCORE0;
case PCM_AM_LDO_VCORE1:
case PCM_AM_DCDC_VCORE1:
case PCM_AM_LF_VCORE1:
case PCM_LPM0_LDO_VCORE1:
case PCM_LPM0_DCDC_VCORE1:
case PCM_LPM0_LF_VCORE1:
return PCM_VCORE1;
case PCM_LPM3:
return PCM_VCORELPM3;
default:
ASSERT(false);
return false;
}
}
bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
{
uint8_t bCurrentPowerMode, bCurrentPowerState;
uint32_t regValue;
bool boolTimeout;
ASSERT(
powerMode == PCM_LDO_MODE || powerMode == PCM_DCDC_MODE
|| powerMode == PCM_LF_MODE);
/* Getting Current Power Mode */
bCurrentPowerMode = PCM_getPowerMode();
/* If the power mode being set it the same as the current mode, return */
if (powerMode == bCurrentPowerMode)
return true;
bCurrentPowerState = PCM_getPowerState();
boolTimeout = timeOut > 0 ? true : false;
/* Go through the while loop while we haven't achieved the power mode */
while (bCurrentPowerMode != powerMode)
{
regValue = PCM->rCTL0.r;
switch (bCurrentPowerState)
{
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LF_VCORE0:
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE0
| (regValue & ~(PCMKEY_M | AMR_M)));
break;
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE1
| (regValue & ~(PCMKEY_M | AMR_M)));
break;
case PCM_AM_LDO_VCORE1:
{
if (powerMode == PCM_DCDC_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE1
| (regValue & ~(PCMKEY_M | AMR_M)));
} else if (powerMode == PCM_LF_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE1
| (regValue & ~(PCMKEY_M | AMR_M)));
} else
ASSERT(false);
break;
}
case PCM_AM_LDO_VCORE0:
{
if (powerMode == PCM_DCDC_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE0
| (regValue & ~(PCMKEY_M | AMR_M)));
} else if (powerMode == PCM_LF_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE0
| (regValue & ~(PCMKEY_M | AMR_M)));
} else
ASSERT(false);
break;
}
default:
ASSERT(false);
}
while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
{
if (boolTimeout && !(--timeOut))
return false;
}
bCurrentPowerMode = PCM_getPowerMode();
bCurrentPowerState = PCM_getPowerState();
}
return true;
}
bool PCM_setPowerState(uint_fast8_t powerState)
{
return PCM_setPowerStateWithTimeout(powerState, 0);
}
bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
{
uint8_t bCurrentPowerState;
bCurrentPowerState = PCM_getPowerState();
ASSERT(
powerState == PCM_AM_LDO_VCORE0 || powerState == PCM_AM_LDO_VCORE1
|| powerState == PCM_AM_DCDC_VCORE0 || powerState == PCM_AM_DCDC_VCORE1
|| powerState == PCM_AM_LF_VCORE0 || powerState == PCM_AM_LF_VCORE1
|| powerState == PCM_LPM0_LDO_VCORE0 || powerState == PCM_LPM0_LDO_VCORE1
|| powerState == PCM_LPM0_DCDC_VCORE0 || powerState == PCM_LPM0_DCDC_VCORE1
|| powerState == PCM_LPM3 || powerState == PCM_LPM35_VCORE0
|| powerState == PCM_LPM45);
if (bCurrentPowerState == powerState)
return true;
switch (powerState)
{
case PCM_AM_LDO_VCORE0:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
case PCM_AM_LDO_VCORE1:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
case PCM_AM_DCDC_VCORE0:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
&& PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
case PCM_AM_DCDC_VCORE1:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
&& PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
case PCM_AM_LF_VCORE0:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
case PCM_AM_LF_VCORE1:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
case PCM_LPM0_LDO_VCORE0:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LDO_VCORE1:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
break;
return PCM_gotoLPM0();
case PCM_LPM0_DCDC_VCORE0:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
break;
return PCM_gotoLPM0();
case PCM_LPM0_DCDC_VCORE1:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LF_VCORE0:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LF_VCORE1:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
break;
return PCM_gotoLPM0();
case PCM_LPM3:
return PCM_gotoLPM3();
case PCM_LPM45:
return PCM_shutdownDevice(PCM_LPM45);
case PCM_LPM35_VCORE0:
return PCM_shutdownDevice(PCM_LPM35_VCORE0);
default:
ASSERT(false);
return false;
}
return false;
}
bool PCM_shutdownDevice(uint32_t shutdownMode)
{
uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ? LPMR_12 : LPMR_10;
ASSERT(
shutdownMode == PCM_SHUTDOWN_PARTIAL
|| shutdownMode == PCM_SHUTDOWN_COMPLETE);
/* If a power transition is occuring, return false */
if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
return false;
/* Initiating the shutdown */
HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
PCM->rCTL0.r = (PCM_KEY | shutdownModeBits
| (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)));
CPU_wfi();
return true;
}
bool PCM_gotoLPM0(void)
{
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
return false;
HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
CPU_wfi();
return true;
}
bool PCM_gotoLPM0InterruptSafe(void)
{
bool slHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
slHappenedCorrect = PCM_gotoLPM0();
/* Enabling and Disabling Interrupts very quickly so that the
processor catches any pending interrupts */
Interrupt_enableMaster();
Interrupt_disableMaster();
return slHappenedCorrect;
}
bool PCM_gotoLPM3(void)
{
uint_fast8_t bCurrentPowerState;
uint_fast8_t currentPowerMode;
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
return false;
/* If we are in the middle of a shutdown, return false */
if ((PCM->rCTL0.r & LPMR_M) == LPMR_10 || (PCM->rCTL0.r & LPMR_M) == LPMR_12)
return false;
currentPowerMode = PCM_getPowerMode();
bCurrentPowerState = PCM_getPowerState();
if (currentPowerMode == PCM_DCDC_MODE || currentPowerMode == PCM_LF_MODE)
PCM_setPowerMode(PCM_LDO_MODE);
/* Clearing the SDR */
PCM->rCTL0.r = (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)) | PCM_KEY;
/* Setting the sleep deep bit */
HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
CPU_wfi();
HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
return PCM_setPowerState(bCurrentPowerState);
}
bool PCM_gotoLPM3InterruptSafe(void)
{
bool dslHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
dslHappenedCorrect = PCM_gotoLPM3();
/* Enabling and Disabling Interrupts very quickly so that the
processor catches any pending interrupts */
Interrupt_enableMaster();
Interrupt_disableMaster();
return dslHappenedCorrect;
}
uint8_t PCM_getPowerState(void)
{
return PCM->rCTL0.b.bCPM;
}
void PCM_enableRudeMode(void)
{
PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M)) | PCM_KEY | FORCE_LPM_ENTRY;
}
void PCM_disableRudeMode(void)
{
PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M | FORCE_LPM_ENTRY)) | PCM_KEY;
}
void PCM_enableInterrupt(uint32_t flags)
{
PCM->rIE.r |= flags;
}
void PCM_disableInterrupt(uint32_t flags)
{
PCM->rIE.r &= ~flags;
}
uint32_t PCM_getInterruptStatus(void)
{
return PCM->rIFG.r;
}
uint32_t PCM_getEnabledInterruptStatus(void)
{
return PCM_getInterruptStatus() & PCM->rIE.r;
}
void PCM_clearInterruptFlag(uint32_t flags)
{
PCM->rCLRIFG.r |= flags;
}
void PCM_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(INT_PCM, intHandler);
//
// Enable the system control interrupt.
//
Interrupt_enableInterrupt(INT_PCM);
}
void PCM_unregisterInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(INT_PCM);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(INT_PCM);
}

595
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
Unescape Escape View File

@ -0,0 +1,595 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __PCM_H__
#define __PCM_H__
//*****************************************************************************
//
//! \addtogroup pcm_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define PCM_KEY 0x695A0000
/* Power Modes */
#define PCM_AM_LDO_VCORE0 0x00
#define PCM_AM_LDO_VCORE1 0x01
#define PCM_AM_DCDC_VCORE0 0x04
#define PCM_AM_DCDC_VCORE1 0x05
#define PCM_AM_LF_VCORE0 0x08
#define PCM_AM_LF_VCORE1 0x09
#define PCM_LPM0_LDO_VCORE0 0x10
#define PCM_LPM0_LDO_VCORE1 0x11
#define PCM_LPM0_DCDC_VCORE0 0x14
#define PCM_LPM0_DCDC_VCORE1 0x15
#define PCM_LPM0_LF_VCORE0 0x18
#define PCM_LPM0_LF_VCORE1 0x19
#define PCM_LPM3 0x20
#define PCM_LPM35_VCORE0 0xC0
#define PCM_LPM45 0xA0
#define PCM_VCORE0 0x00
#define PCM_VCORE1 0x01
#define PCM_VCORELPM3 0x02
#define PCM_LDO_MODE 0x00
#define PCM_DCDC_MODE 0x01
#define PCM_LF_MODE 0x02
#define PCM_SHUTDOWN_PARTIAL PCM_LPM35_VCORE0
#define PCM_SHUTDOWN_COMPLETE PCM_LPM45
#define PCM_DCDCERROR PCM_INTEN_EN_DCDC_ERROR
#define PCM_AM_INVALIDTRANSITION PCM_INTEN_EN_AM_INVALID_TR
#define PCM_SM_INVALIDCLOCK PCM_INTEN_EN_SM_INVALID_CLK
#define PCM_SM_INVALIDTRANSITION PCM_INTEN_EN_SM_INVALID_TR
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//******************************************************************************
//
//! Sets the core voltage level (Vcore). The function will take care of all
//! power state transitions needed to shift between core voltage levels.
//! Because transitions between voltage levels may require changes power modes,
//! the power mode might temporarily be change. The power mode will be returned
//! to the original state (with the new voltage level) at the end of a
//! successful execution of this function.
//!
//! Refer to the device specific data sheet for specifics about core voltage
//! levels.
//!
//! \param voltageLevel The voltage level to be shifted to.
//! - \b PCM_VCORE0,
//! - \b PCM_VCORE1
//!
//! \return true if voltage level set, false otherwise.
//
//******************************************************************************
extern bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel);
//******************************************************************************
//
//! Returns the current powers state of the system see the
//! PCM_setCoreVoltageLevel function for specific information about the modes.
//!
//! \return The current voltage of the system
//!
//! Possible return values include:
//! - \b PCM_VCORE0
//! - \b PCM_VCORE1
//! - \b PCM_VCORELPM3
//!
//
//******************************************************************************
extern uint8_t PCM_getCoreVoltageLevel(void);
//******************************************************************************
//
//! Sets the core voltage level (Vcore). This function will take care of all
//! power state transitions needed to shift between core voltage levels.
//! Because transitions between voltage levels may require changes power modes,
//! the power mode might temporarily be change. The power mode will be returned
//! to the original state (with the new voltage level) at the end of a
//! successful execution of this function.
//!
//! This function is similar to PCMSetCoreVoltageLevel, however a timeout
//! mechanism is used.
//!
//! Refer to the device specific data sheet for specifics about core voltage
//! levels.
//!
//! \param voltageLevel The voltage level to be shifted to.
//! - \b PCM_VCORE0,
//! - \b PCM_VCORE1
//!
//! \param timeOut Number of loop iterations to timeout when checking for
//! power state transitions. This should be used for debugging initial
//! power/hardware configurations. After a stable hardware base is
//! established, the PCMSetCoreVoltageLevel function should be used
//!
//! \return true if voltage level set, false otherwise.
//
//******************************************************************************
extern bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
uint32_t timeOut);
//******************************************************************************
//
//! Switches between power modes. This function will take care of all
//! power state transitions needed to shift between power modes. Note for
//! changing to DCDC mode, specific hardware considerations are required.
//!
//! Refer to the device specific data sheet for specifics about power modes.
//!
//! \param powerMode The voltage modes to be shifted to. Valid values are:
//! - \b PCM_LDO_MODE,
//! - \b PCM_DCDC_MODE,
//! - \b PCM_LF_MODE
//!
//! \return true if power mode is set, false otherwise.
//
//******************************************************************************
extern bool PCM_setPowerMode(uint_fast8_t powerMode);
//******************************************************************************
//
//! Switches between power modes. This function will take care of all
//! power state transitions needed to shift between power modes. Note for
//! changing to DCDC mode, specific hardware considerations are required.
//!
//! This function is similar to PCMSetPowerMode, however a timeout
//! mechanism is used.
//!
//! Refer to the device specific data sheet for specifics about power modes.
//!
//! \param powerMode The voltage modes to be shifted to. Valid values are:
//! - \b PCM_LDO_MODE,
//! - \b PCM_DCDC_MODE,
//! - \b PCM_LF_MODE
//!
//! \param timeOut Number of loop iterations to timeout when checking for
//! power state transitions. This should be used for debugging initial
//! power/hardware configurations. After a stable hardware base is
//! established, the PCMSetPowerMode function should be used
//!
//! \return true if power mode is set, false otherwise.
//
//******************************************************************************
extern bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode,
uint32_t timeOut);
//******************************************************************************
//
//! Returns the current powers state of the system see the \b PCM_setPowerState
//! function for specific information about the modes.
//!
//! \return The current power mode of the system
//!
//
//******************************************************************************
extern uint8_t PCM_getPowerMode(void);
//******************************************************************************
//
//! Switches between power states. This is a convenience function that combines
//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
//! the sleep/LPM3/shutdown functions.
//!
//! Refer to the device specific data sheet for specifics about power states.
//!
//! \param powerState The voltage modes to be shifted to. Valid values are:
//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0]
//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1]
//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0]
//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1]
//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0]
//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1]
//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0]
//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1]
//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0]
//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1]
//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0]
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \return true if power state is set, false otherwise.
//
//******************************************************************************
extern bool PCM_setPowerState(uint_fast8_t powerState);
//******************************************************************************
//
//! Switches between power states. This is a convenience function that combines
//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
//! the LPM modes.
//!
//! This function is similar to PCMChangePowerState, however a timeout
//! mechanism is used.
//!
//! Refer to the device specific data sheet for specifics about power states.
//!
//! \param powerState The voltage modes to be shifted to. Valid values are:
//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0]
//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1]
//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0]
//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1]
//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0]
//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1]
//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0]
//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1]
//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0]
//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1]
//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0]
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \param timeout Number of loop iterations to timeout when checking for
//! power state transitions. This should be used for debugging initial
//! power/hardware configurations. After a stable hardware base is
//! established, the PCMSetPowerMode function should be used
//!
//! \return true if power state is set, false otherwise. It is important to
//! note that if a timeout occurs, false will be returned, however the
//! power state at this point is not guaranteed to be the same as the
//! state prior to the function call
//
//******************************************************************************
extern bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState,
uint32_t timeout);
//******************************************************************************
//
//! Returns the current powers state of the system see the PCMChangePowerState
//! function for specific information about the states.
//!
//! Refer to \link PCM_setPowerState \endlink for possible return values.
//!
//! \return The current power state of the system
//
//******************************************************************************
extern uint8_t PCM_getPowerState(void);
//******************************************************************************
//
//! Transitions the device into LPM3.5/LPM4.5 mode.
//!
//! Refer to the device specific data sheet for specifics about shutdown modes.
//!
//! The following events will cause a wake up from LPM3.5 mode:
//! - Device reset
//! - External reset RST
//! - Enabled RTC, WDT, and wake-up I/O only interrupt events
//!
//! The following events will cause a wake up from the LPM4.5 mode:
//! - Device reset
//! - External reset RST
//! - Wake-up I/O only interrupt events
//!
//! \param shutdownMode Specific mode to go to. Valid values are:
//! - \b PCM_LPM35_VCORE0
//! - \b PCM_LPM45
//!
//!
//! \return false if shutdown state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_shutdownDevice(uint32_t shutdownMode);
//******************************************************************************
//
//! Transitions the device into LPM0.
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM0(void);
//******************************************************************************
//
//! Transitions the device into LPM3
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//! Note that since LPM3 cannot be entered from a DCDC power modes, the
//! power mode is first switched to LDO operation (if in DCDC mode), the deep
//! sleep is entered, and the DCDC mode is restored on wake up.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM3(void);
//******************************************************************************
//
//! Transitions the device into LPM0 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to sleep, however does not want
//! to go to "miss" any interrupts due to the fact that going to DSL is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM0InterruptSafe(void);
//******************************************************************************
//
//! Transitions the device into LPM3 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to LPM3, however does not want
//! to go to "miss" any interrupts due to the fact that going to DSL is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//! Note that since LPM3 cannot be entered from a DCDC power modes, the
//! power mode is first switched to LDO operation (if in DCDC mode), the deep
//! sleep is entered, and the DCDC mode is restored on wake up.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM3InterruptSafe(void);
//******************************************************************************
//
//! Enables "rude mode" entry into LPM3 and shutdown modes. With this mode
//! enabled, an entry into shutdown or LPM3 will occur even if there are
//! clock systems active. The system will forcibly turn off all clock/systems
//! when going into these modes.
//!
//! \return None
//
//******************************************************************************
extern void PCM_enableRudeMode(void);
//******************************************************************************
//
//! Disables "rude mode" entry into LPM3 and shutdown modes. With this
//! mode disabled, an entry into shutdown or LPM3 will wait for any
//! active clock requests to free up before going into LPM3 or shutdown.
//!
//! \return None
//
//******************************************************************************
extern void PCM_disableRudeMode(void);
//*****************************************************************************
//
//! Enables individual power control interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be enabled. Must
//! be a logical OR of:
//! - \b PCM_DCDCERROR,
//! - \b PCM_AM_INVALIDTRANSITION,
//! - \b PCM_SM_INVALIDCLOCK,
//! - \b PCM_SM_INVALIDTRANSITION
//!
//! This function enables the indicated power control interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void PCM_enableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Disables individual power control interrupt sources.
//!
//! \param flags is a bit mask of the interrupt sources to be enabled. Must
//! be a logical OR of:
//! - \b PCM_DCDCERROR,
//! - \b PCM_AM_INVALIDTRANSITION,
//! - \b PCM_SM_INVALIDCLOCK,
//! - \b PCM_SM_INVALIDTRANSITION
//!
//! This function disables the indicated power control interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void PCM_disableInterrupt(uint32_t flags);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b PCM_DCDCERROR,
//! - \b PCM_AM_INVALIDTRANSITION,
//! - \b PCM_SM_INVALIDCLOCK,
//! - \b PCM_SM_INVALIDTRANSITION
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t PCM_getInterruptStatus(void);
//*****************************************************************************
//
//! Gets the current interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list of pending
//! interrupts that are actually enabled and could have caused
//! the ISR.
//!
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b PCM_DCDCERROR,
//! - \b PCM_AM_INVALIDTRANSITION,
//! - \b PCM_SM_INVALIDCLOCK,
//! - \b PCM_SM_INVALIDTRANSITION
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//
//*****************************************************************************
extern uint32_t PCM_getEnabledInterruptStatus(void);
//*****************************************************************************
//
//! Clears power system interrupt sources.
//!
//! The specified power system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep it from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \param flags is a bit mask of the interrupt sources to be cleared. Must
//! be a logical OR of
//! - \b PCM_DCDCERROR,
//! - \b PCM_AM_INVALIDTRANSITION,
//! - \b PCM_SM_INVALIDCLOCK,
//! - \b PCM_SM_INVALIDTRANSITION
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
//! which interrupt sources are available.
//!
//! \return None.
//
//*****************************************************************************
extern void PCM_clearInterruptFlag(uint32_t flags);
//*****************************************************************************
//
//! Registers an interrupt handler for the power system interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the power
//! system interrupt occurs.
//!
//! This function registers the handler to be called when a clock system
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific PCM interrupts must be enabled
//! via PCM_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via \link PCM_clearInterruptFlag \endlink .
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void PCM_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the power system.
//!
//! This function unregisters the handler to be called when a power system
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void PCM_unregisterInterrupt(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __PCM_H__

65
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
Unescape Escape View File

@ -0,0 +1,65 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <debug.h>
#include <pmap.h>
void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
uint8_t numberOfPorts, uint8_t portMapReconfigure)
{
uint16_t i;
ASSERT(
(portMapReconfigure == PMAP_ENABLE_RECONFIGURATION)
|| (portMapReconfigure == PMAP_DISABLE_RECONFIGURATION));
//Get write-access to port mapping registers:
PMAP->rKEYID = PMAP_KEYID_VAL;
//Enable/Disable reconfiguration during runtime
PMAP->rCTL.r = (PMAP->rCTL.r & ~PMAPRECFG) | portMapReconfigure;
//Configure Port Mapping:
for (i = 0; i < numberOfPorts * 8; i++)
{
HWREG8(PMAP_BASE + i + pxMAPy) = portMapping[i];
}
//Disable write-access to port mapping registers:
PMAP->rKEYID = 0;
}

129
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
Unescape Escape View File

@ -0,0 +1,129 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __PMAP_H__
#define __PMAP_H__
//*****************************************************************************
//
//! \addtogroup pmap_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <msp.h>
//*****************************************************************************
//
//The following are values that can be passed to the PMAP_configurePorts() API
//as the portMapReconfigure parameter.
//
//*****************************************************************************
#define PMAP_ENABLE_RECONFIGURATION PMAPRECFG
#define PMAP_DISABLE_RECONFIGURATION 0x00
//*****************************************************************************
//
//The following are values that can be passed to the PMAP_configurePorts() API
//as the portMapReconfigure parameter.
//
//*****************************************************************************
#define P1MAP OFS_P1MAP01
#define P2MAP OFS_P2MAP01
#define P3MAP OFS_P3MAP01
#define P4MAP OFS_P4MAP01
#define P5MAP OFS_P5MAP01
#define P6MAP OFS_P6MAP01
#define P7MAP OFS_P7MAP01
//*****************************************************************************
//
//Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! This function configures the MSP432 Port Mapper
//!
//! \param portMapping is the pointer to init Data
//! \param pxMAPy is the Port Mapper to initialize
//! \param numberOfPorts is the number of Ports to initialize
//! \param portMapReconfigure is used to enable/disable reconfiguration
//! Valid values are
//! \b PMAP_ENABLE_RECONFIGURATION
//! \b PMAP_DISABLE_RECONFIGURATION [Default value]
//! Modified registers are \b PMAPKEYID, \b PMAPCTL
//!
//! \return None
//
//*****************************************************************************
extern void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
uint8_t numberOfPorts, uint8_t portMapReconfigure);
/* Defines for future devices that might have multiple instances */
#define PMAP_configurePortsMultipleInstance(a,b,c,d,e) PMAP_configurePorts(b,c,d,e)
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif

243
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
Unescape Escape View File

@ -0,0 +1,243 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <pss.h>
#include <interrupt.h>
#include <debug.h>
#include <cpu.h>
static void __PSSUnlock()
{
PSS->rKEY.r = PSS_KEY_VALUE;
}
static void __PSSLock()
{
PSS->rKEY.r = 0;
}
void PSS_enableHighSidePinToggle(bool activeLow)
{
__PSSUnlock();
if (activeLow)
PSS->rCTL0.r |= (SVMHOE | SVMHOUTPOLAL);
else
{
BITBAND_PERI(PSS->rCTL0.r, SVMHOUTPOLAL_OFS) = 0;
BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 1;
}
__PSSLock();
}
void PSS_disableHighSidePinToggle(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 0;
__PSSLock();
}
void PSS_enableHighSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 0;
__PSSLock();
}
void PSS_disableHighSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 1;
__PSSLock();
}
void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode)
{
__PSSUnlock();
if (powerMode == PSS_FULL_PERFORMANCE_MODE)
BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 0;
else
BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 1;
__PSSLock();
}
uint_fast8_t PSS_getHighSidePerformanceMode(void)
{
if (BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS))
return PSS_NORMAL_PERFORMANCE_MODE;
else
return PSS_FULL_PERFORMANCE_MODE;
}
void PSS_enableHighSideMonitor(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 1;
__PSSLock();
}
void PSS_disableHighSideMonitor(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 0;
__PSSLock();
}
void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage)
{
__PSSUnlock();
ASSERT(!(triggerVoltage & 0xF8))
PSS->rCTL0.b.bSVSMHTH = triggerVoltage & 0x07;
__PSSLock();
}
uint_fast8_t PSS_getHighSideVoltageTrigger(void)
{
return PSS->rCTL0.b.bSVSMHTH;
}
void PSS_enableLowSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 0;
__PSSLock();
}
void PSS_disableLowSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 1;
__PSSLock();
}
void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode)
{
__PSSUnlock();
if (ui8PowerMode == PSS_FULL_PERFORMANCE_MODE)
BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 0;
else
BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 1;
__PSSLock();
}
uint_fast8_t PSS_getLowSidePerformanceMode(void)
{
if (BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS))
return PSS_NORMAL_PERFORMANCE_MODE;
else
return PSS_FULL_PERFORMANCE_MODE;
}
void PSS_enableInterrupt(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 1;
__PSSLock();
}
void PSS_disableInterrupt(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 0;
__PSSLock();
}
uint32_t PSS_getInterruptStatus(void)
{
return PSS->rIFG.r;
}
void PSS_clearInterruptFlag(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCLRIFG.r,CLRSVSMHIFG_OFS) = 0;
__PSSLock();
}
void PSS_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(INT_PSS, intHandler);
//
// Enable the system control interrupt.
//
Interrupt_enableInterrupt(INT_PSS);
}
void PSS_unregisterInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt(INT_PSS);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(INT_PSS);
}

340
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
Unescape Escape View File

@ -0,0 +1,340 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __PSS_H__
#define __PSS_H__
//*****************************************************************************
//
//! \addtogroup pss_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <msp.h>
#include <stdbool.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define PSS_KEY_VALUE 0x0000695A
#define PSS_SVSMH SVSMHIE
#define PSS_FULL_PERFORMANCE_MODE 0x01
#define PSS_NORMAL_PERFORMANCE_MODE 0x00
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables output of the High Side interrupt flag on the device \b SVMHOUT pin
//!
//! \param activeLow True if the signal should be logic low when SVSMHIFG
//! is set. False if signal should be high when \b SVSMHIFG is set.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableHighSidePinToggle(bool activeLow);
//*****************************************************************************
//
//! Disables output of the High Side interrupt flag on the device \b SVMHOUT pin
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableHighSidePinToggle(void);
//*****************************************************************************
//
//! Enables high side voltage supervisor/monitor.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableHighSide(void);
//*****************************************************************************
//
//! Disables high side voltage supervisor/monitor.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableHighSide(void);
//*****************************************************************************
//
//! Sets the performance mode of the high side regulator. Full performance
//! mode allows for the best response times while normal performance mode is
//! optimized for the lowest possible current consumption.
//!
//! \param powerMode is the performance mode to set. Valid values are one of
//! the following:
//! - \b PSS_FULL_PERFORMANCE_MODE,
//! - \b PSS_NORMAL_PERFORMANCE_MODE
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode);
//*****************************************************************************
//
//! Gets the performance mode of the high side voltage regulator. Refer to the
//! user's guide for specific information about information about the different
//! performance modes.
//!
//! \return Performance mode of the voltage regulator
//
//*****************************************************************************
extern uint_fast8_t PSS_getHighSidePerformanceMode(void);
//*****************************************************************************
//
//! Sets the high side voltage supervisor to monitor mode
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableHighSideMonitor(void);
//*****************************************************************************
//
//! Switches the high side of the power supply system to be a supervisor instead
//! of a monitor
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableHighSideMonitor(void);
//*****************************************************************************
//
//! Sets the voltage level at which the high side of the device voltage
//! regulator triggers a reset. This value is represented as an unsigned eight
//! bit integer where only the lowest three bits are most significant.
//!
//! \param triggerVoltage Voltage level in which high side supervisor/monitor
//! triggers a reset. See the device specific data sheet for details
//! on these voltage levels.
//!
//! Typical values will vary from part to part (so it is very important to
//! check the SVSH section of the data sheet. For reference only, the typical
//! MSP432 101 values are listed below:
//! - 0 --> 1.57V
//! - 1 --> 1.62V
//! - 2 --> 1.83V
//! - 3 --> 2V
//! - 4 --> 2.25V
//! - 5 --> 2.4V
//! - 6 --> 2.6V
//! - 7 --> 2.8V
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage);
//*****************************************************************************
//
//! Returns the voltage level at which the high side of the device voltage
//! regulator triggers a reset.
//!
//! \return The voltage level that the high side voltage supervisor/monitor
//! triggers a reset. This value is represented as an unsigned eight
//! bit integer where only the lowest three bits are most significant.
//! See \link PSS_setHighSideVoltageTrigger \endlink for information regarding
//! the return value
//
//*****************************************************************************
extern uint_fast8_t PSS_getHighSideVoltageTrigger(void);
//*****************************************************************************
//
//! Enables low side voltage supervisor/monitor.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableLowSide(void);
//*****************************************************************************
//
//! Disables low side voltage supervisor/monitor.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableLowSide(void);
//*****************************************************************************
//
//! Sets the performance mode of the high side regulator. Full performance
//! mode allows for the best response times while normal performance mode is
//! optimized for the lowest possible current consumption.
//!
//! \param ui8PowerMode is the performance mode to set. Valid values are one of
//! the following:
//! - \b PSS_FULL_PERFORMANCE_MODE,
//! - \b PSS_NORMAL_PERFORMANCE_MODE
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode);
//*****************************************************************************
//
//! Gets the performance mode of the low side voltage regulator. Refer to the
//! user's guide for specific information about information about the different
//! performance modes.
//!
//! \return Performance mode of the voltage regulator
//
//*****************************************************************************
extern uint_fast8_t PSS_getLowSidePerformanceMode(void);
//*****************************************************************************
//
//! Enables the power supply system interrupt source.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableInterrupt(void);
//*****************************************************************************
//
//! Disables the power supply system interrupt source.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableInterrupt(void);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \return The current interrupt status ( \b PSS_SVSMH )
//!
//*****************************************************************************
extern uint32_t PSS_getInterruptStatus(void);
//*****************************************************************************
//
//! Clears power supply system interrupt source.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_clearInterruptFlag(void);
//*****************************************************************************
//
//! Registers an interrupt handler for the power supply system interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the power
//! supply system interrupt occurs.
//!
//! This function registers the handler to be called when a power supply system
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific PSS interrupts must be enabled
//! via PSS_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via PSS_clearInterruptFlag().
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the power supply system
//!
//! This function unregisters the handler to be called when a power supply
//! system interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_unregisterInterrupt(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __PSS_H__

116
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
Unescape Escape View File

@ -0,0 +1,116 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <ref_a.h>
#include <debug.h>
void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect)
{
ASSERT(referenceVoltageSelect <= REF_A_VREF2_5V);
REF_A->rCTL0.r = (REF_A->rCTL0.r & ~REFVSEL_3) | referenceVoltageSelect;
}
void REF_A_disableTempSensor(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 1;
}
void REF_A_enableTempSensor(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 0;
}
void REF_A_enableReferenceVoltageOutput(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 1;
}
void REF_A_disableReferenceVoltageOutput(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 0;
}
void REF_A_enableReferenceVoltage(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 1;
}
void REF_A_disableReferenceVoltage(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 0;
}
uint_fast8_t REF_A_getBandgapMode(void)
{
return (REF_A->rCTL0.r & BGMODE);
}
bool REF_A_isBandgapActive(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFBGACT_OFS);
}
bool REF_A_isRefGenBusy(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFGENBUSY_OFS);
}
bool REF_A_isRefGenActive(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFGENACT_OFS);
}
bool REF_A_getBufferedBandgapVoltageStatus(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFBGRDY_OFS);
}
bool REF_A_getVariableReferenceVoltageStatus(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFGENRDY_OFS);
}
void REF_A_setReferenceVoltageOneTimeTrigger(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFGENOT_OFS) = 1;
}
void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFBGOT_OFS) = 1;
}

346
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
Unescape Escape View File

@ -0,0 +1,346 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __REF_B_H__
#define __REF_B_H__
//*****************************************************************************
//
//! \addtogroup ref_api
//! @{
//
//*****************************************************************************
#include <msp.h>
#include <stdbool.h>
#include <stdint.h>
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//The following are values that can be passed to Ref_setReferenceVoltage()
//in the referenceVoltageSelect parameter.
//
//*****************************************************************************
#define REF_A_VREF1_2V REFVSEL_0
#define REF_A_VREF1_45V REFVSEL_1
#define REF_A_VREF2_5V REFVSEL_3
//*****************************************************************************
//
//The following are values that are returned by Ref_getBandgapMode().
//
//*****************************************************************************
#define REF_A_STATICMODE 0x0
#define REF_A_SAMPLEMODE BGMODE
//*****************************************************************************
//
//! Sets the reference voltage for the voltage generator.
//!
//! \param referenceVoltageSelect is the desired voltage to generate for a
//! reference voltage.
//! Valid values are:
//! - \b REF_A_VREF1_2V [Default]
//! - \b REF_A_VREF1_45V
//! - \b REF_A_VREF2_5V
//! Modified bits are \b REFVSEL of \b REFCTL0 register.
//!
//! This function sets the reference voltage generated by the voltage generator
//! to be used by other peripherals. This reference voltage will only be valid
//! while the REF module is in control.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns \b REF_BUSY,
//! this function will have no effect.
//!
//! \return none
//
//*****************************************************************************
extern void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect);
//*****************************************************************************
//
//! Disables the internal temperature sensor to save power consumption.
//!
//! This function is used to turn off the internal temperature sensor to save
//! on power consumption. The temperature sensor is enabled by default. Please
//! note, that giving ADC12 module control over the REF module, the state of the
//! temperature sensor is dependent on the controls of the ADC12 module.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
//! \b REF_A_BUSY, this function will have no effect.
//!
//! Modified bits are \b REFTCOFF of \b REFCTL0 register.
//! \return none
//
//*****************************************************************************
extern void REF_A_disableTempSensor(void);
//*****************************************************************************
//
//! Enables the internal temperature sensor.
//!
//! This function is used to turn on the internal temperature sensor to use by
//! other peripherals. The temperature sensor is enabled by default.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
//! \b REF_A_BUSY, this function will have no effect.
//!
//! Modified bits are \b REFTCOFF of \b REFCTL0 register.
//!
//! \return none
//
//*****************************************************************************
extern void REF_A_enableTempSensor(void);
//*****************************************************************************
//
//! Outputs the reference voltage to an output pin.
//!
//! This function is used to output the reference voltage being generated to an
//! output pin. Please note, the output pin is device specific. Please note,
//! that giving ADC12 module control over the REF module, the state of the
//! reference voltage as an output to a pin is dependent on the controls of the
//! ADC12 module.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
//! \b REF_A_BUSY, this function will have no effect.
//!
//! Modified bits are \b REFOUT of \b REFCTL0 register.
//! \return none
//
//*****************************************************************************
extern void REF_A_enableReferenceVoltageOutput(void);
//*****************************************************************************
//
//! Disables the reference voltage as an output to a pin.
//!
//! This function is used to disables the reference voltage being generated to
//! be given to an output pin.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
//! \b REF_A_BUSY, this function will have no effect.
//!
//! Modified bits are \b REFOUT of \b REFCTL0 register.
//! \return none
//
//*****************************************************************************
extern void REF_A_disableReferenceVoltageOutput(void);
//*****************************************************************************
//
//! Enables the reference voltage to be used by peripherals.
//!
//! This function is used to enable the generated reference voltage to be used
//! other peripherals or by an output pin, if enabled. Please note, that giving
//! ADC12 module control over the REF module, the state of the reference voltage
//! is dependent on the controls of the ADC12 module.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
//! REF_A_BUSY, this function will have no effect.
//!
//! Modified bits are \b REFON of \b REFCTL0 register.
//! \return none
//
//*****************************************************************************
extern void REF_A_enableReferenceVoltage(void);
//*****************************************************************************
//
//! Disables the reference voltage.
//!
//! This function is used to disable the generated reference voltage.
//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
//! \b REF_A_BUSY, this function will have no effect.
//!
//! Modified bits are \b REFON of \b REFCTL0 register.
//! \return none
//
//*****************************************************************************
extern void REF_A_disableReferenceVoltage(void);
//*****************************************************************************
//
//! Returns the bandgap mode of the REF module.
//!
//! This function is used to return the bandgap mode of the REF module,
//! requested by the peripherals using the bandgap. If a peripheral requests
//! static mode, then the bandgap mode will be static for all modules, whereas
//! if all of the peripherals using the bandgap request sample mode, then that
//! will be the mode returned. Sample mode allows the bandgap to be active only
//! when necessary to save on power consumption, static mode requires the
//! bandgap to be active until no peripherals are using it anymore.
//!
//! \return The bandgap mode of the REF module:
//! - \b REF_A_STATICMODE if the bandgap is operating in static mode
//! - \b REF_A_SAMPLEMODE if the bandgap is operating in sample mode
//
//*****************************************************************************
extern uint_fast8_t REF_A_getBandgapMode(void);
//*****************************************************************************
//
//! Returns the active status of the bandgap in the REF module.
//!
//! This function is used to return the active status of the bandgap in the REF
//! module. If the bandgap is in use by a peripheral, then the status will be
//! seen as active.
//!
//! \return true if the bandgap is being used, false otherwise
//
//*****************************************************************************
extern bool REF_A_isBandgapActive(void);
//*****************************************************************************
//
//! Returns the busy status of the reference generator in the REF module.
//!
//! This function is used to return the busy status of the reference generator
//! in the REF module. If the ref. generator is in use by a peripheral, then the
//! status will be seen as busy.
//!
//! \return true if the reference generator is being used, false otherwise.
//*****************************************************************************
extern bool REF_A_isRefGenBusy(void);
//*****************************************************************************
//
//! Returns the active status of the reference generator in the REF module.
//!
//! This function is used to return the active status of the reference generator
//! in the REF module. If the ref. generator is on and ready to use, then the
//! status will be seen as active.
//!
//! \return true if the reference generator is active, false otherwise.
//
//*****************************************************************************
extern bool REF_A_isRefGenActive(void);
//*****************************************************************************
//
//! Returns the busy status of the reference generator in the REF module.
//!
//! This function is used to return the buys status of the buffered bandgap
//! voltage in the REF module. If the ref. generator is on and ready to use,
//! then the status will be seen as active.
//!
//! \return true if the buffered bandgap voltage is ready to be used, false
//! otherwise
//
//*****************************************************************************
extern bool REF_A_getBufferedBandgapVoltageStatus(void);
//*****************************************************************************
//
//! Returns the busy status of the variable reference voltage in the REF module.
//!
//! This function is used to return the buys status of the variable reference
//! voltage in the REF module. If the ref. generator is on and ready to use,
//! then the status will be seen as active.
//!
//! \return true if the variable bandgap voltage is ready to be used, false
//! otherwise
//
//*****************************************************************************
extern bool REF_A_getVariableReferenceVoltageStatus(void);
//*****************************************************************************
//
//! Enables the one-time trigger of the reference voltage.
//!
//! Triggers the one-time generation of the variable reference voltage. Once
//! the reference voltage request is set, this bit is cleared by hardware
//!
//! Modified bits are \b REFGENOT of \b REFCTL0 register.
//!
//! \return none
//
//*****************************************************************************
extern void REF_A_setReferenceVoltageOneTimeTrigger(void);
//*****************************************************************************
//
//! Enables the one-time trigger of the buffered bandgap voltage.
//!
//! Triggers the one-time generation of the buffered bandgap voltage. Once
//! the buffered bandgap voltage request is set, this bit is cleared by hardware
//!
//! Modified bits are \b RefGOT of \b REFCTL0 register.
//!
//! \return none
//
//*****************************************************************************
extern void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void);
/* Defines for future devices that might have multiple instances */
#define REF_A_setReferenceVoltageMultipleInstance(a,b) REF_A_setReferenceVoltage(b)
#define REF_A_disableTempSensorMultipleInstance(a) REF_A_disableTempSensor()
#define REF_A_enableTempSensorMultipleInstance(a) REF_A_enableTempSensor()
#define REF_A_enableReferenceVoltageOutputMultipleInstance(a) REF_A_enableReferenceVoltageOutput()
#define REF_A_disableReferenceVoltageOutputMultipleInstance(a) REF_A_disableReferenceVoltageOutput()
#define REF_A_enableReferenceVoltageMultipleInstance(a) REF_A_enableReferenceVoltage()
#define REF_A_disableReferenceVoltageMultipleInstance(a) REF_A_disableReferenceVoltage()
#define REF_A_getBandgapModeMultipleInstance(a) REF_A_getBandgapMode()
#define REF_A_isBandgapActiveMultipleInstance(a) REF_A_isBandgapActive()
#define REF_A_isRefGenBusyMultipleInstance(a) REF_A_isRefGenBusy()
#define REF_A_isRefGenActiveMultipleInstance(a) REF_A_isRefGenActive()
#define REF_A_getBufferedBandgapVoltageStatusMultipleInstance(a) REF_A_getBufferedBandgapVoltageStatus()
#define REF_A_getVariableReferenceVoltageStatusMultipleInstance(a) REF_A_getVariableReferenceVoltageStatus()
#define REF_A_setReferenceVoltageOneTimeTriggerMultipleInstance(a) REF_A_setReferenceVoltageOneTimeTrigger()
#define REF_A_setBufferedBandgapVoltageOneTimeTriggerMultipleInstance(a) REF_A_setBufferedBandgapVoltageOneTimeTrigger()
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __REF_A_H__

99
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
Unescape Escape View File

@ -0,0 +1,99 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <reset.h>
#include <debug.h>
void ResetCtl_initiateSoftReset(void)
{
RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_SOFT_RESET);
}
void ResetCtl_initiateSoftResetWithSource(uint32_t source)
{
RSTCTL->rSOFTRESET_SET.r |= (source);
}
uint32_t ResetCtl_getSoftResetSource(void)
{
return RSTCTL->rSOFTRESET_STAT.r;
}
void ResetCtl_clearSoftResetSource(uint32_t mask)
{
RSTCTL->rSOFTRESET_CLR.r |= mask;
}
void ResetCtl_initiateHardReset(void)
{
RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_HARD_RESET);
}
void ResetCtl_initiateHardResetWithSource(uint32_t source)
{
RSTCTL->rHARDRESET_SET.r |= (source);
}
uint32_t ResetCtl_getHardResetSource(void)
{
return RSTCTL->rHARDRESET_STAT.r;
}
void ResetCtl_clearHardResetSource(uint32_t mask)
{
RSTCTL->rHARDRESET_CLR.r |= mask;
}
uint32_t ResetCtl_getPSSSource(void)
{
return RSTCTL->rPSSRESET_STAT.r;
}
void ResetCtl_clearPSSFlags(void)
{
RSTCTL->rPSSRESET_CLR.r |= RSTCTL_PSSRESET_CLR_CLR;
}
uint32_t ResetCtl_getPCMSource(void)
{
return RSTCTL->rPCMRESET_STAT.r;
}
void ResetCtl_clearPCMFlags(void)
{
RSTCTL->rPCMRESET_CLR.r |= RSTCTL_PCMRESET_CLR_CLR;
}

345
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
Unescape Escape View File

@ -0,0 +1,345 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __RESET_H__
#define __RESET_H__
//*****************************************************************************
//
//! \addtogroup reset_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <msp.h>
#include <stdint.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define RESET_KEY 0x6900
#define RESET_HARD_RESET RSTCTL_RESET_REQ_HARD_REQ
#define RESET_SOFT_RESET RSTCTL_RESET_REQ_SOFT_REQ
#define RESET_SRC_0 RSTCTL_HARDRESET_CLR_SRC0
#define RESET_SRC_1 RSTCTL_HARDRESET_CLR_SRC1
#define RESET_SRC_2 RSTCTL_HARDRESET_CLR_SRC2
#define RESET_SRC_3 RSTCTL_HARDRESET_CLR_SRC3
#define RESET_SRC_4 RSTCTL_HARDRESET_CLR_SRC4
#define RESET_SRC_5 RSTCTL_HARDRESET_CLR_SRC5
#define RESET_SRC_6 RSTCTL_HARDRESET_CLR_SRC6
#define RESET_SRC_7 RSTCTL_HARDRESET_CLR_SRC7
#define RESET_SRC_8 RSTCTL_HARDRESET_CLR_SRC8
#define RESET_SRC_9 RSTCTL_HARDRESET_CLR_SRC9
#define RESET_SRC_10 RSTCTL_HARDRESET_CLR_SRC10
#define RESET_SRC_11 RSTCTL_HARDRESET_CLR_SRC11
#define RESET_SRC_12 RSTCTL_HARDRESET_CLR_SRC12
#define RESET_SRC_13 RSTCTL_HARDRESET_CLR_SRC13
#define RESET_SRC_14 RSTCTL_HARDRESET_CLR_SRC14
#define RESET_SRC_15 RSTCTL_HARDRESET_CLR_SRC15
#define RESET_VCCDET RSTCTL_PSSRESET_CLR_BGREF
#define RESET_SVSH_TRIP RSTCTL_PSSRESET_CLR_SVSMH
#define RESET_SVSL_TRIP RSTCTL_PSSRESET_CLR_SVSL
#define RESET_BGREF_BAD RSTCTL_PSSRESET_CLR_BGREF
#define RESET_SD0 RSTCTL_PCMRESET_CLR_LPM35
#define RESET_SD1 RSTCTL_PCMRESET_CLR_LPM45
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Initiates a soft system reset.
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_initiateSoftReset(void);
//*****************************************************************************
//
//! Initiates a soft system reset with a particular source given. This source
//! is generic and can be assigned by the user.
//!
//! \param source Source of the reset. Valid values are:
//! - \b RESET_SRC_0,
//! - \b RESET_SRC_1,
//! - \b RESET_SRC_2,
//! - \b RESET_SRC_3,
//! - \b RESET_SRC_4,
//! - \b RESET_SRC_5,
//! - \b RESET_SRC_6,
//! - \b RESET_SRC_7,
//! - \b RESET_SRC_8,
//! - \b RESET_SRC_9,
//! - \b RESET_SRC_10,
//! - \b RESET_SRC_11,
//! - \b RESET_SRC_12,
//! - \b RESET_SRC_13,
//! - \b RESET_SRC_14,
//! - \b RESET_SRC_15
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_initiateSoftResetWithSource(uint32_t source);
//*****************************************************************************
//
//! Retrieves previous soft reset sources
//!
//! \return the bitwise or of previous reset sources. These sources must be
//! cleared using the \link ResetCtl_clearSoftResetSource \endlink function to
//! be cleared.
//! Possible values include:
//! - \b RESET_SRC_0,
//! - \b RESET_SRC_1,
//! - \b RESET_SRC_2,
//! - \b RESET_SRC_3,
//! - \b RESET_SRC_4,
//! - \b RESET_SRC_5,
//! - \b RESET_SRC_6,
//! - \b RESET_SRC_7,
//! - \b RESET_SRC_8,
//! - \b RESET_SRC_9,
//! - \b RESET_SRC_10,
//! - \b RESET_SRC_11,
//! - \b RESET_SRC_12,
//! - \b RESET_SRC_13,
//! - \b RESET_SRC_14,
//! - \b RESET_SRC_15
//
//*****************************************************************************
extern uint32_t ResetCtl_getSoftResetSource(void);
//*****************************************************************************
//
//! Clears the reset sources associated with at soft reset
//!
//! \param mask - Bitwise OR of any of the following values:
//! - \b RESET_SRC_0,
//! - \b RESET_SRC_1,
//! - \b RESET_SRC_2,
//! - \b RESET_SRC_3,
//! - \b RESET_SRC_4,
//! - \b RESET_SRC_5,
//! - \b RESET_SRC_6,
//! - \b RESET_SRC_7,
//! - \b RESET_SRC_8,
//! - \b RESET_SRC_9,
//! - \b RESET_SRC_10,
//! - \b RESET_SRC_11,
//! - \b RESET_SRC_12,
//! - \b RESET_SRC_13,
//! - \b RESET_SRC_14,
//! - \b RESET_SRC_15
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_clearSoftResetSource(uint32_t mask);
//*****************************************************************************
//
//! Initiates a hard system reset.
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_initiateHardReset(void);
//*****************************************************************************
//
//! Initiates a hard system reset with a particular source given. This source
//! is generic and can be assigned by the user.
//!
//! \param source - Valid values are one the following values:
//! - \b RESET_SRC_0,
//! - \b RESET_SRC_1,
//! - \b RESET_SRC_2,
//! - \b RESET_SRC_3,
//! - \b RESET_SRC_4,
//! - \b RESET_SRC_5,
//! - \b RESET_SRC_6,
//! - \b RESET_SRC_7,
//! - \b RESET_SRC_8,
//! - \b RESET_SRC_9,
//! - \b RESET_SRC_10,
//! - \b RESET_SRC_11,
//! - \b RESET_SRC_12,
//! - \b RESET_SRC_13,
//! - \b RESET_SRC_14,
//! - \b RESET_SRC_15
//! \return none
//
//*****************************************************************************
extern void ResetCtl_initiateHardResetWithSource(uint32_t source);
//*****************************************************************************
//
//! Retrieves previous hard reset sources
//!
//! \return the bitwise or of previous reset sources. These sources must be
//! cleared using the \link ResetCtl_clearHardResetSource \endlink function to
//! be cleared.
//! Possible values include:
//! - \b RESET_SRC_0,
//! - \b RESET_SRC_1,
//! - \b RESET_SRC_2,
//! - \b RESET_SRC_3,
//! - \b RESET_SRC_4,
//! - \b RESET_SRC_5,
//! - \b RESET_SRC_6,
//! - \b RESET_SRC_7,
//! - \b RESET_SRC_8,
//! - \b RESET_SRC_9,
//! - \b RESET_SRC_10,
//! - \b RESET_SRC_11,
//! - \b RESET_SRC_12,
//! - \b RESET_SRC_13,
//! - \b RESET_SRC_14,
//! - \b RESET_SRC_15
//
//*****************************************************************************
extern uint32_t ResetCtl_getHardResetSource(void);
//*****************************************************************************
//
//! Clears the reset sources associated with at hard reset
//!
//! \param mask - Bitwise OR of any of the following values:
//! - \b RESET_SRC_0,
//! - \b RESET_SRC_1,
//! - \b RESET_SRC_2,
//! - \b RESET_SRC_3,
//! - \b RESET_SRC_4,
//! - \b RESET_SRC_5,
//! - \b RESET_SRC_6,
//! - \b RESET_SRC_7,
//! - \b RESET_SRC_8,
//! - \b RESET_SRC_9,
//! - \b RESET_SRC_10,
//! - \b RESET_SRC_11,
//! - \b RESET_SRC_12,
//! - \b RESET_SRC_13,
//! - \b RESET_SRC_14,
//! - \b RESET_SRC_15
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_clearHardResetSource(uint32_t mask);
//*****************************************************************************
//
//! Indicates the last cause of a power-on reset (POR) due to PSS operation.
//! Note that the bits returned from this function may be set in different
//! combinations. When a cold power up occurs, the value of all the values ORed
//! together could be returned as a cold power up causes these conditions.
//!
//! \return Bitwise OR of any of the following values:
//! - RESET_VCCDET,
//! - RESET_SVSH_TRIP,
//! - RESET_SVSL_TRIP,
//! - RESET_BGREF_BAD
//
//*****************************************************************************
extern uint32_t ResetCtl_getPSSSource(void);
//*****************************************************************************
//
//! Clears the PSS reset source flags
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_clearPSSFlags(void);
//*****************************************************************************
//
//! Indicates the last cause of a power-on reset (POR) due to PCM operation.
//!
//! \return Bitwise OR of any of the following values:
//! - RESET_SD0,
//! - RESET_SD1
//
//*****************************************************************************
extern uint32_t ResetCtl_getPCMSource(void);
//*****************************************************************************
//
//! Clears the corresponding PCM reset source flags
//!
//! \return none
//
//*****************************************************************************
extern void ResetCtl_clearPCMFlags(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __RESET_H__

1805
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
View File

File diff suppressed because it is too large Load Diff

3438
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
View File

File diff suppressed because it is too large Load Diff

338
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
Unescape Escape View File

@ -0,0 +1,338 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <rtc_c.h>
#include <interrupt.h>
#include <debug.h>
void RTC_C_startClock(void)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 0;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
void RTC_C_holdClock(void)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCCALF_3)) | frequencySelect;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
uint_fast8_t offsetValue)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->rOCAL.r = offsetValue + offsetDirection;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
uint_fast8_t offsetValue)
{
while (!BITBAND_PERI(RTC_C->rTCMP.r, RTCTCRDY_OFS))
;
RTC_C->rTCMP.r = offsetValue + offsetDirection;
if (BITBAND_PERI(RTC_C->rTCMP.r, RTCTCOK_OFS))
return true;
else
return false;
}
void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
uint_fast16_t formatSelect)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
if (formatSelect)
BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 1;
else
BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 0;
RTC_C->rTIM0.b.bSEC = calendarTime->seconds;
RTC_C->rTIM0.b.bMIN = calendarTime->minutes;
RTC_C->rTIM1.b.bHOUR = calendarTime->hours;
RTC_C->rTIM1.b.bDOW = calendarTime->dayOfWeek;
RTC_C->rDATE.b.bDAY = calendarTime->dayOfmonth;
RTC_C->rDATE.b.bMON = calendarTime->month;
RTC_C->rYEAR.r = calendarTime->year;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
RTC_C_Calendar RTC_C_getCalendarTime(void)
{
RTC_C_Calendar tempCal;
while (!(BITBAND_PERI(RTC_C->rCTL13.r, RTCRDY_OFS)))
;
tempCal.seconds = RTC_C->rTIM0.b.bSEC;
tempCal.minutes = RTC_C->rTIM0.b.bMIN;
tempCal.hours = RTC_C->rTIM1.b.bHOUR;
tempCal.dayOfWeek = RTC_C->rTIM1.b.bDOW;
tempCal.dayOfmonth = RTC_C->rDATE.b.bDAY;
tempCal.month = RTC_C->rDATE.b.bMON;
tempCal.year = RTC_C->rYEAR.r;
return (tempCal);
}
void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm,
uint_fast8_t dayOfWeekAlarm, uint_fast8_t dayOfmonthAlarm)
{
//Each of these is XORed with 0x80 to turn on if an integer is passed,
//or turn OFF if RTC_ALARM_OFF (0x80) is passed.
HWREG8(RTC_C_BASE + OFS_RTCAMINHR) = (minutesAlarm ^ 0x80);
HWREG8(RTC_C_BASE + OFS_RTCAMINHR + 1) = (hoursAlarm ^ 0x80);
HWREG8(RTC_C_BASE + OFS_RTCADOWDAY) = (dayOfWeekAlarm ^ 0x80);
HWREG8(RTC_C_BASE + OFS_RTCADOWDAY + 1) = (dayOfmonthAlarm ^ 0x80);
}
void RTC_C_setCalendarEvent(uint_fast16_t eventSelect)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCTEV_3)) | eventSelect;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleEventDivider)
{
HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) &= ~(RT0IP_7);
HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) |=
prescaleEventDivider;
}
uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
{
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
return (RTC_C->rPS.b.bRT0PS);
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
return (RTC_C->rPS.b.bRT1PS);
} else
{
return (0);
}
}
void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleCounterValue)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
RTC_C->rPS.b.bRT0PS = prescaleCounterValue;
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
RTC_C->rPS.b.bRT1PS = prescaleCounterValue;
}
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert)
{
RTC_C->rBCD2BIN = valueToConvert;
return (RTC_C->rBCD2BIN);
}
uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert)
{
RTC_C->rBIN2BCD = valueToConvert;
return (RTC_C->rBIN2BCD);
}
void RTC_C_enableInterrupt(uint8_t interruptMask)
{
if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
{
RTC_C->rCTL0.r = RTCKEY | (interruptMask
& (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 1;
}
if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 1;
}
}
void RTC_C_disableInterrupt(uint8_t interruptMask)
{
if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
{
RTC_C->rCTL0.r = RTCKEY
| (RTC_C->rCTL0.r
& ~((interruptMask | RTCKEY_M)
& (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)));
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 0;
}
}
uint_fast8_t RTC_C_getInterruptStatus(void)
{
uint_fast8_t tempInterruptFlagMask = 0x00;
uint_fast8_t interruptFlagMask = RTC_C_TIME_EVENT_INTERRUPT
| RTC_C_CLOCK_ALARM_INTERRUPT | RTC_C_CLOCK_READ_READY_INTERRUPT
| RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT
| RTC_C_OSCILLATOR_FAULT_INTERRUPT;
tempInterruptFlagMask |= (RTC_C->rCTL0.r & (interruptFlagMask >> 4));
tempInterruptFlagMask = tempInterruptFlagMask << 4;
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
if (BITBAND_PERI(RTC_C->rPS0CTL.r, RT0PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
if (BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
}
return (tempInterruptFlagMask);
}
uint_fast8_t RTC_C_getEnabledInterruptStatus(void)
{
uint32_t intStatus = RTC_C_getInterruptStatus();
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCOFIE_OFS))
{
intStatus &= ~RTC_C_OSCILLATOR_FAULT_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCTEVIE_OFS))
{
intStatus &= ~RTC_C_TIME_EVENT_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCAIE_OFS))
{
intStatus &= ~RTC_C_CLOCK_ALARM_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCRDYIE_OFS))
{
intStatus &= ~RTC_C_CLOCK_READ_READY_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rPS0CTL, RT0PSIE_OFS))
{
intStatus &= ~RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIE_OFS))
{
intStatus &= ~RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
return intStatus;
}
void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask)
{
if (interruptFlagMask
& (RTC_C_TIME_EVENT_INTERRUPT + RTC_C_CLOCK_ALARM_INTERRUPT
+ RTC_C_CLOCK_READ_READY_INTERRUPT
+ RTC_C_OSCILLATOR_FAULT_INTERRUPT))
{
RTC_C->rCTL0.r = RTCKEY
| (RTC_C->rCTL0.r & ~((interruptFlagMask >> 4) | RTCKEY_M));
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIFG_OFS) = 0;
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS) = 0;
}
}
void RTC_C_registerInterrupt(void (*intHandler)(void))
{
Interrupt_registerInterrupt(INT_RTC_C, intHandler);
Interrupt_enableInterrupt(INT_RTC_C);
}
void RTC_C_unregisterInterrupt(void)
{
Interrupt_disableInterrupt(INT_RTC_C);
Interrupt_unregisterInterrupt(INT_RTC_C);
}

661
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
Unescape Escape View File

@ -0,0 +1,661 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef RTC_C_H_
#define RTC_C_H_
//*****************************************************************************
//
//! \addtogroup rtc_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
//*****************************************************************************
//
//The following is a struct that can be passed to RTC_CalendarInit() in the
//CalendarTime parameter, as well as returned by RTC_getCalendarTime()
//
//*****************************************************************************
typedef struct _RTC_C_Calendar
{
uint_fast8_t seconds;
uint_fast8_t minutes;
uint_fast8_t hours;
uint_fast8_t dayOfWeek;
uint_fast8_t dayOfmonth;
uint_fast8_t month;
uint_fast16_t year;
} RTC_C_Calendar;
//*****************************************************************************
//
//The following are values that can be passed to RTC_setCalibrationData()
//
//*****************************************************************************
#define RTC_C_CALIBRATIONFREQ_OFF (RTCCALF_0)
#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1)
#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2)
#define RTC_C_CALIBRATIONFREQ_1HZ (RTCCALF_3)
//*****************************************************************************
//
//The following are values that can be passed to RTC_setCalibrationData()
//
//*****************************************************************************
#define RTC_C_CALIBRATION_DOWN1PPM ( !(RTCOCALS) )
#define RTC_C_CALIBRATION_UP1PPM (RTCOCALS)
//*****************************************************************************
//
//The following are values that can be passed to
//RTC_setTemperatureCompensation()
//
//*****************************************************************************
#define RTC_C_COMPENSATION_DOWN1PPM ( !(RTCTCMPS) )
#define RTC_C_COMPENSATION_UP1PPM (RTCTCMPS)
//*****************************************************************************
//
//The following are values that can be passed to RTC_iniRTC_Calendar()
//
//*****************************************************************************
#define RTC_C_FORMAT_BINARY ( !(RTCBCD) )
#define RTC_C_FORMAT_BCD (RTCBCD)
//*****************************************************************************
//
//The following is a value that can be passed to RTC_seRTC_CalendarAlarm()
//
//*****************************************************************************
#define RTC_C_ALARMCONDITION_OFF (0x80)
//*****************************************************************************
//
//The following are values that can be passed to RTC_seRTC_CalendarEvent()
//in the eventSelect parameter.
//
//*****************************************************************************
#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTCTEV_0)
#define RTC_C_CALENDAREVENT_HOURCHANGE (RTCTEV_1)
#define RTC_C_CALENDAREVENT_NOON (RTCTEV_2)
#define RTC_C_CALENDAREVENT_MIDNIGHT (RTCTEV_3)
//*****************************************************************************
//
//The following are values that can be passed to RTC_definePrescaleEvent()
//
//*****************************************************************************
#define RTC_C_PRESCALE_0 (0x0)
#define RTC_C_PRESCALE_1 (0x1)
//*****************************************************************************
//
//The following are values that can be passed to RTC_definePrescaleEvent()
//in the prescaleEventDivider parameter.
//
//*****************************************************************************
#define RTC_C_PSEVENTDIVIDER_2 (RT0IP_0)
#define RTC_C_PSEVENTDIVIDER_4 (RT0IP_1)
#define RTC_C_PSEVENTDIVIDER_8 (RT0IP_2)
#define RTC_C_PSEVENTDIVIDER_16 (RT0IP_3)
#define RTC_C_PSEVENTDIVIDER_32 (RT0IP_4)
#define RTC_C_PSEVENTDIVIDER_64 (RT0IP_5)
#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6)
#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7)
//*****************************************************************************
//
//The following are values that can be passed to the interrupt functions
//
//*****************************************************************************
#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTCOFIE
#define RTC_C_TIME_EVENT_INTERRUPT RTCTEVIE
#define RTC_C_CLOCK_ALARM_INTERRUPT RTCAIE
#define RTC_C_CLOCK_READ_READY_INTERRUPT RTCRDYIE
#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02
#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01
//*****************************************************************************
//
//! Starts the RTC.
//!
//! This function clears the RTC main hold bit to allow the RTC to function.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_startClock(void);
//*****************************************************************************
//
//! Holds the RTC.
//!
//! This function sets the RTC main hold bit to disable RTC functionality.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_holdClock(void);
//*****************************************************************************
//
//! Allows and Sets the frequency output to RTCLK pin for calibration
//! measurement.
//!
//! \param frequencySelect is the frequency output to RTCLK.
//! Valid values are
//! - \b RTC_C_CALIBRATIONFREQ_OFF - turn off calibration
//! output [Default]
//! - \b RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz
//! for calibration
//! - \b RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz
//! for calibration
//! - \b RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz
//! for calibration
//!
//! This function sets a frequency to measure at the RTCLK output pin. After
//! testing the set frequency, the calibration could be set accordingly.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect);
//*****************************************************************************
//
//! Sets the specified calibration for the RTC.
//!
//! \param offsetDirection is the direction that the calibration offset will
//! go. Valid values are
//! - \b RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1
//! - \b RTC_C_CALIBRATION_UP1PPM - calibrat at steps of +1
//! \param offsetValue is the value that the offset will be a factor of; a
//! valid value is any integer from 1-240.
//!
//! This function sets the calibration offset to make the RTC as accurate as
//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the
//! offsetValue should be from 1-240 and is multiplied by the direction setting
//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
uint_fast8_t offsetValue);
//*****************************************************************************
//
//! Sets the specified temperature compensation for the RTC.
//!
//! \param offsetDirection is the direction that the calibration offset will
//! go. Valid values are
//! - \b RTC_C_COMPENSATION_DOWN1PPM - calibrate at steps of -1
//! - \b RTC_C_COMPENSATION_UP1PPM - calibrate at steps of +1
//! \param offsetValue is the value that the offset will be a factor of; a
//! value is any integer from 1-240.
//!
//! This function sets the calibration offset to make the RTC as accurate as
//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the
//! offsetValue should be from 1-240 and is multiplied by the direction setting
//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).
//!
//! \return true if calibration was set, false if it could not be set
//!
//
//*****************************************************************************
extern bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
uint_fast8_t offsetValue);
//*****************************************************************************
//
//! Initializes the settings to operate the RTC in Calendar mode.
//!
//! \param calendarTime is the structure containing the values for the Calendar
//! to be initialized to.
//! Valid values should be of type Calendar and should contain the
//! following members and corresponding values:
//! - \b seconds between 0-59
//! - \b minutes between 0-59
//! - \b hours between 0-24
//! - \b dayOfWeek between 0-6
//! - \b dayOfmonth between 0-31
//! - \b year between 0-4095
//! \note Values beyond the ones specified may result in eradic behavior.
//! \param formatSelect is the format for the Calendar registers to use.
//! Valid values are
//! - \b RTC_FORMAT_BINARY [Default]
//! - \b RTC_FORMAT_BCD
//!
//! This function initializes the Calendar mode of the RTC module.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
uint_fast16_t formatSelect);
//*****************************************************************************
//
//! Returns the Calendar Time stored in the Calendar registers of the RTC.
//!
//!
//! This function returns the current Calendar time in the form of a Calendar
//! structure.
//!
//! \return A Calendar structure containing the current time.
//
//*****************************************************************************
extern RTC_C_Calendar RTC_C_getCalendarTime(void);
//*****************************************************************************
//
//! Sets and Enables the desired Calendar Alarm settings.
//!
//! \param minutesAlarm is the alarm condition for the minutes.
//! Valid values are
//! - An integer between 0-59, OR
//! - \b RTC_C_ALARMCONDITION_OFF [Default]
//! \param hoursAlarm is the alarm condition for the hours.
//! Valid values are
//! - An integer between 0-24, OR
//! - \b RTC_C_ALARMCONDITION_OFF [Default]
//! \param dayOfWeekAlarm is the alarm condition for the day of week.
//! Valid values are
//! - An integer between 0-6, OR
//! - \b RTC_C_ALARMCONDITION_OFF [Default]
//! \param dayOfmonthAlarm is the alarm condition for the day of the month.
//! Valid values are
//! - An integer between 0-31, OR
//! - \b RTC_C_ALARMCONDITION_OFF [Default]
//!
//! This function sets a Calendar interrupt condition to assert the RTCAIFG
//! interrupt flag. The condition is a logical and of all of the parameters.
//! For example if the minutes and hours alarm is set, then the interrupt will
//! only assert when the minutes AND the hours change to the specified setting.
//! Use the RTC_ALARM_OFF for any alarm settings that should not be apart of
//! the alarm condition.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm,
uint_fast8_t hoursAlarm, uint_fast8_t dayOfWeekAlarm,
uint_fast8_t dayOfmonthAlarm);
//*****************************************************************************
//
//! Sets a single specified Calendar interrupt condition.
//!
//! \param eventSelect is the condition selected.
//! Valid values are
//! - \b RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every
//! minute
//! - \b RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour
//! - \b RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12
//! - \b RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0
//!
//! This function sets a specified event to assert the RTCTEVIFG interrupt. This
//! interrupt is independent from the Calendar alarm interrupt.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_setCalendarEvent(uint_fast16_t eventSelect);
//*****************************************************************************
//
//! Sets up an interrupt condition for the selected Prescaler.
//!
//! \param prescaleSelect is the prescaler to define an interrupt for.
//! Valid values are
//! - \b RTC_C_PRESCALE_0
//! - \b RTC_C_PRESCALE_1
//! \param prescaleEventDivider is a divider to specify when an interrupt can
//! occur based on the clock source of the selected prescaler.
//! (Does not affect timer of the selected prescaler).
//! Valid values are
//! - \b RTC_C_PSEVENTDIVIDER_2 [Default]
//! - \b RTC_C_PSEVENTDIVIDER_4
//! - \b RTC_C_PSEVENTDIVIDER_8
//! - \b RTC_C_PSEVENTDIVIDER_16
//! - \b RTC_C_PSEVENTDIVIDER_32
//! - \b RTC_C_PSEVENTDIVIDER_64
//! - \b RTC_C_PSEVENTDIVIDER_128
//! - \b RTC_C_PSEVENTDIVIDER_256
//!
//! This function sets the condition for an interrupt to assert based on the
//! individual prescalers.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleEventDivider);
//*****************************************************************************
//
//! Returns the selected Prescaler value.
//!
//! \param prescaleSelect is the prescaler to obtain the value of.
//! Valid values are
//! - \b RTC_C_PRESCALE_0
//! - \b RTC_C_PRESCALE_1
//!
//! This function returns the value of the selected prescale counter register.
//! The counter should be held before reading. If in counter mode, the
//! individual prescaler can be held, while in Calendar mode the whole RTC must
//! be held.
//!
//! \return The value of the specified Prescaler count register
//
//*****************************************************************************
extern uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect);
//*****************************************************************************
//
//! Sets the selected Prescaler value.
//!
//! \param prescaleSelect is the prescaler to set the value for.
//! Valid values are
//! - \b RTC_C_PRESCALE_0
//! - \b RTC_C_PRESCALE_1
//! \param prescaleCounterValue is the specified value to set the prescaler to;
//! a valid value is any integer from 0-255.
//!
//! This function sets the prescale counter value. Before setting the prescale
//! counter, it should be held.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleCounterValue);
//*****************************************************************************
//
//! Returns the given BCD value in Binary Format
//!
//! \param valueToConvert is the raw value in BCD format to convert to
//! Binary.
//!
//! This function converts BCD values to Binary format.
//!
//! \return The Binary version of the valueToConvert parameter.
//
//*****************************************************************************
extern uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert);
//*****************************************************************************
//
//! Returns the given Binary value in BCD Format
//!
//! \param valueToConvert is the raw value in Binary format to convert to
//! BCD.
//!
//! This function converts Binary values to BCD format.
//!
//! \return The BCD version of the valueToConvert parameter.
//
//*****************************************************************************
extern uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert);
//*****************************************************************************
//
//! Enables selected RTC interrupt sources.
//!
//! \param interruptMask is a bit mask of the interrupts to enable.
//! Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
//! registers are settled.
//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
//! event condition is met.
//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
//! event condition is met.
//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is
//! a problem with the 32kHz oscillator, while the RTC is running.
//!
//! This function enables the selected RTC interrupt source. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_enableInterrupt(uint8_t interruptMask);
//*****************************************************************************
//
//! Disables selected RTC interrupt sources.
//!
//! \param interruptMask is a bit mask of the interrupts to disable.
//! Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
//! registers are settled.
//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
//! event condition is met.
//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
//! event condition is met.
//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a
//! problem with the 32kHz oscillator, while the RTC is running.
//!
//! This function disables the selected RTC interrupt source. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_disableInterrupt(uint8_t interruptMask);
//*****************************************************************************
//
//! Returns the status of the interrupts flags.
//!
//! \return A bit mask of the selected interrupt flag's status.
//! Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
//! registers are settled.
//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
//! event condition is met.
//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
//! event condition is met.
//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a
//! problem with the 32kHz oscillator, while the RTC is running.
//
//*****************************************************************************
extern uint_fast8_t RTC_C_getInterruptStatus(void);
//*****************************************************************************
//
//! Returns the status of the interrupts flags masked with the enabled
//! interrupts. This function is useful to call in ISRs to get a
//! list of pending interrupts that are actually enabled and could have caused
//! the ISR.
//!
//! \return A bit mask of the selected interrupt flag's status.
//! Mask Value is the logical OR of any of the following
//! - \b RTC_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! - \b RTC_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
//! registers are settled.
//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
//! event condition is met.
//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
//! event condition is met.
//! - \b RTC_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a problem
//! with the 32kHz oscillator, while the RTC is running.
//
//*****************************************************************************
extern uint_fast8_t RTC_C_getEnabledInterruptStatus(void);
//*****************************************************************************
//
//! Clears selected RTC interrupt flags.
//!
//! \param interruptFlagMask is a bit mask of the interrupt flags to be
//! cleared. Mask Value is the logical OR of any of the following
//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
//! counter mode or when Calendar event condition defined by
//! defineCalendarEvent() is met.
//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
//! Calendar mode is met.
//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
//! registers are settled.
//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
//! event condition is met.
//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
//! event condition is met.
//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is
//! a problem with the 32kHz oscillator, while the RTC is running.
//!
//! This function clears the RTC interrupt flag is cleared, so that it no longer
//! asserts.
//!
//! \return None
//
//*****************************************************************************
extern void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask);
//*****************************************************************************
//
//! Registers an interrupt handler for the RTC interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the
//! RTC interrupt occurs.
//!
//! This function registers the handler to be called when a RTC
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific AES interrupts must be enabled
//! via RTC_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via RTC_clearInterruptFlag().
//!
//! \return None.
//
//*****************************************************************************
extern void RTC_C_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the RTC interrupt
//!
//! This function unregisters the handler to be called when RTC
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void RTC_C_unregisterInterrupt(void);
/* Defines for future devices that might have multiple instances */
#define RTC_C_startClockMultipleInstance(a) RTC_C_startClock()
#define RTC_C_holdClockMultipleInstance(a) RTC_C_holdClock()
#define RTC_C_setCalibrationFrequencyMultipleInstance(a,b) RTC_C_setCalibrationFrequency(b)
#define RTC_C_setCalibrationDataMultipleInstance(a,b,c) RTC_C_setCalibrationData(b,c)
#define RTC_C_setTemperatureCompensationMultipleInstance(a,b,c) RTC_C_setTemperatureCompensation(b,c)
#define RTC_C_initCalendarMultipleInstance(a,b,c) RTC_C_initCalendar(b,c)
#define RTC_C_getCalendarTimeMultipleInstance(a) RTC_C_getCalendarTime()
#define RTC_C_setCalendarAlarmMultipleInstance(a,b,c,d,e) RTC_C_setCalendarAlarm(b,c,d,e)
#define RTC_C_setCalendarEventMultipleInstance(a,b) RTC_C_setCalendarEvent(b)
#define RTC_C_definePrescaleEventMultipleInstance(a,b,c) RTC_C_definePrescaleEvent(b,c)
#define RTC_C_getPrescaleValueMultipleInstance(a,b) RTC_C_getPrescaleValue(b)
#define RTC_C_setPrescaleValueMultipleInstance(a,b,c) RTC_C_setPrescaleValue(b,c)
#define RTC_C_convertBCDToBinaryMultipleInstance(a,b) RTC_C_convertBCDToBinary(b)
#define RTC_C_convertBinaryToBCDMultipleInstance(a,b) RTC_C_convertBinaryToBCD(b)
#define RTC_C_enableInterruptMultipleInstance(a,b) RTC_C_enableInterrupt(b)
#define RTC_C_disableInterruptMultipleInstance(a,b) RTC_C_disableInterrupt(b)
#define RTC_C_getInterruptStatusMultipleInstance(a) RTC_C_getInterruptStatus()
#define RTC_C_getEnabledInterruptStatusMultipleInstance(a) RTC_C_getEnabledInterruptStatus()
#define RTC_C_clearInterruptFlagMultipleInstance(a,b) RTC_C_clearInterruptFlag(b)
#define RTC_C_registerInterruptMultipleInstance(a,b) RTC_C_registerInterrupt(b)
#define RTC_C_unregisterInterruptMultipleInstance(a) RTC_C_unregisterInterrupt()
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* RTC_H */

1363
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
View File

File diff suppressed because it is too large Load Diff

822
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
Unescape Escape View File

@ -0,0 +1,822 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef SPI_H_
#define SPI_H_
//*****************************************************************************
//
//! \addtogroup spi_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdbool.h>
#include <stdint.h>
#include <msp.h>
#include "eusci.h"
/* Configuration Defines */
#define EUSCI_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_SPI_MSB_FIRST UCMSB
#define EUSCI_SPI_LSB_FIRST 0x00
#define EUSCI_SPI_BUSY UCBUSY
#define EUSCI_SPI_NOT_BUSY 0x00
#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
#define EUSCI_SPI_3PIN UCMODE_0
#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_SPI_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_SPI_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
//*****************************************************************************
//
//! \typedef eUSCI_SPI_MasterConfig
//! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure
//!
//! \struct _eUSCI_SPI_MasterConfig
//! \brief Configuration structure for master mode in the \b SPI module. See
//! \link SPI_initMaster \endlink for parameter documentation.
//
//*****************************************************************************
typedef struct _eUSCI_SPI_MasterConfig
{
uint_fast8_t selectClockSource;
uint32_t clockSourceFrequency;
uint32_t desiredSpiClock;
uint_fast16_t msbFirst;
uint_fast16_t clockPhase;
uint_fast16_t clockPolarity;
uint_fast16_t spiMode;
} eUSCI_SPI_MasterConfig;
//*****************************************************************************
//
//! \typedef eUSCI_SPI_SlaveConfig
//! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure
//!
//! \struct _eUSCI_SPI_SlaveConfig
//! \brief Configuration structure for slave mode in the \b SPI module. See
//! \link SPI_initSlave \endlink for parameter documentation.
//
//*****************************************************************************
typedef struct _eUSCI_SPI_SlaveConfig
{
uint_fast16_t msbFirst;
uint_fast16_t clockPhase;
uint_fast16_t clockPolarity;
uint_fast16_t spiMode;
} eUSCI_SPI_SlaveConfig;
//*****************************************************************************
//
//! Initializes the SPI Master block.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! \param config Configuration structure for SPI master mode
//!
//! <hr>
//! <b>Configuration options for \link eUSCI_SPI_MasterConfig \endlink structure.</b>
//! <hr>
//!
//! \param selectClockSource selects clock source. Valid values are
//! - \b EUSCI_SPI_CLOCKSOURCE_ACLK
//! - \b EUSCI_SPI_CLOCKSOURCE_SMCLK
//! \param clockSourceFrequency is the frequency of the selected clock source
//! \param desiredSpiClock is the desired clock rate for SPI communication
//! \param msbFirst controls the direction of the receive and transmit shift
//! register. Valid values are
//! - \b EUSCI_SPI_MSB_FIRST
//! - \b EUSCI_SPI_LSB_FIRST [Default Value]
//! \param clockPhase is clock phase select.
//! Valid values are
//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
//! [Default Value]
//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
//! \param clockPolarity is clock polarity select.
//! Valid values are
//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value]
//! \param spiMode is SPI mode select.
//! Valid values are
//! - \b EUSCI_SPI_3PIN [Default Value]
//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW
//! Upon successful initialization of the SPI master block, this function
//! will have set the bus speed for the master, but the SPI Master block
//! still remains disabled and must be enabled with SPI_enableModule()
//!
//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB,\b UCSSELx,
//! \b UCSWRST bits of \b UCAxCTLW0 register
//!
//! \return true
//
//*****************************************************************************
extern bool SPI_initMaster(uint32_t moduleInstance,
const eUSCI_SPI_MasterConfig *config);
//*****************************************************************************
//
//! Selects 4Pin Functionality
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param select4PinFunctionality selects Clock source. Valid values are
//! - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
//! - \b EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
//! This function should be invoked only in 4-wire mode. Invoking this function
//! has no effect in 3-wire mode.
//!
//! Modified bits are \b UCSTEM bit of \b UCAxCTLW0 register
//!
//! \return true
//
//*****************************************************************************
extern void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
uint_fast8_t select4PinFunctionality);
//*****************************************************************************
//
//! Initializes the SPI Master clock.At the end of this function call, SPI
//! module is left enabled.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param clockSourceFrequency is the frequency of the selected clock source
//! \param desiredSpiClock is the desired clock rate for SPI communication.
//!
//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register and
//! \b UCAxBRW register
//!
//! \return None
//
//*****************************************************************************
extern void SPI_changeMasterClock(uint32_t moduleInstance,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
//*****************************************************************************
//
//! Initializes the SPI Slave block.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! \param config Configuration structure for SPI slave mode
//!
//! <hr>
//! <b>Configuration options for \link eUSCI_SPI_SlaveConfig \endlink structure.</b>
//! <hr>
//!
//! \param msbFirst controls the direction of the receive and transmit shift
//! register. Valid values are
//! - \b EUSCI_SPI_MSB_FIRST
//! - \b EUSCI_SPI_LSB_FIRST [Default Value]
//! \param clockPhase is clock phase select.
//! Valid values are
//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
//! [Default Value]
//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
//! \param clockPolarity is clock polarity select.
//! Valid values are
//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value]
//! \param spiMode is SPI mode select.
//! Valid values are
//! - \b EUSCI_SPI_3PIN [Default Value]
//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW
//! Upon successful initialization of the SPI slave block, this function
//! will have initialized the slave block, but the SPI Slave block
//! still remains disabled and must be enabled with SPI_enableModule()
//!
//! Modified bits are \b UCMSB, \b UC7BIT, \b UCMST, \b UCCKPL, \b UCCKPH,
//! \b UCMODE, \b UCSWRST bits of \b UCAxCTLW0
//!
//! \return true
//*****************************************************************************
extern bool SPI_initSlave(uint32_t moduleInstance,
const eUSCI_SPI_SlaveConfig *config);
//*****************************************************************************
//
//! Changes the SPI clock phase and polarity.At the end of this function call,
//! SPI module is left enabled.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param clockPhase is clock phase select.
//! Valid values are:
//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
//! [Default Value]
//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
//! \param clockPolarity is clock polarity select.
//! Valid values are:
//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value]
//!
//! Modified bits are \b UCSWRST, \b UCCKPH, \b UCCKPL, \b UCSWRST bits of
//! \b UCAxCTLW0
//!
//! \return None
//
//*****************************************************************************
extern void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
uint_fast16_t clockPhase, uint_fast16_t clockPolarity);
//*****************************************************************************
//
//! Transmits a byte from the SPI Module.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param transmitData data to be transmitted from the SPI module
//!
//! This function will place the supplied data into SPI transmit data register
//! to start transmission
//!
//! Modified register is \b UCAxTXBUF
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_transmitData(uint32_t moduleInstance,
uint_fast8_t transmitData);
//*****************************************************************************
//
//! Receives a byte that has been sent to the SPI Module.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//!
//! This function reads a byte of data from the SPI receive data Register.
//!
//! \return Returns the byte received from by the SPI module, cast as an
//! uint8_t.
//
//*****************************************************************************
extern uint8_t SPI_receiveData(uint32_t moduleInstance);
//*****************************************************************************
//
//! Enables the SPI block.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//!
//! This will enable operation of the SPI block.
//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register.
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_enableModule(uint32_t moduleInstance);
//*****************************************************************************
//
//! Disables the SPI block.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//!
//! This will disable operation of the SPI block.
//!
//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register.
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_disableModule(uint32_t moduleInstance);
//*****************************************************************************
//
//! Returns the address of the RX Buffer of the SPI for the DMA module.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//!
//! Returns the address of the SPI RX Buffer. This can be used in conjunction
//! with the DMA to store the received data directly to memory.
//!
//! \return NONE
//
//*****************************************************************************
extern uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
//*****************************************************************************
//
//! Returns the address of the TX Buffer of the SPI for the DMA module.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//!
//! Returns the address of the SPI TX Buffer. This can be used in conjunction
//! with the DMA to obtain transmitted data directly from memory.
//!
//! \return NONE
//
//*****************************************************************************
extern uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
//*****************************************************************************
//
//! Indicates whether or not the SPI bus is busy.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//!
//! This function returns an indication of whether or not the SPI bus is
//! busy.This function checks the status of the bus via UCBBUSY bit
//!
//! \return EUSCI_SPI_BUSY if the SPI module transmitting or receiving
//! is busy; otherwise, returns EUSCI_SPI_NOT_BUSY.
//
//*****************************************************************************
extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance);
//*****************************************************************************
//
//! Enables individual SPI interrupt sources.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param mask is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SPI interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt
//!
//! Modified registers are \b UCAxIFG and \b UCAxIE
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//*****************************************************************************
//
//! Disables individual SPI interrupt sources.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param mask is the bit mask of the interrupt sources to be
//! disabled.
//!
//! Disables the indicated SPI interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt
//!
//! Modified register is \b UCAxIE
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//*****************************************************************************
//
//! Gets the current SPI interrupt status.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! \param mask Mask of interrupt to filter. This can include:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
//!
//! Modified registers are \b UCAxIFG.
//!
//! \return The current interrupt status as the mask of the set flags
//! Mask parameter can be either any of the following selection:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
//
//*****************************************************************************
extern uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance,
uint16_t mask);
//*****************************************************************************
//
//! Gets the current SPI interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list of pending
//! interrupts that are actually enabled and could have caused
//! the ISR.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! Modified registers are \b UCAxIFG.
//!
//! \return The current interrupt status as the mask of the set flags
//! Mask parameter can be either any of the following selection:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
//
//*****************************************************************************
extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance);
//*****************************************************************************
//
//! Clears the selected SPI interrupt status flag.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! \param mask is the masked interrupt flag to be cleared.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
//! Modified registers are \b UCAxIFG.
//!
//! \return None
//
//*****************************************************************************
extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
//*****************************************************************************
//
//! Registers an interrupt handler for the timer capture compare interrupt.
//!
//! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
//! \param intHandler is a pointer to the function to be called when the
//! timer capture compare interrupt occurs.
//!
//! This function registers the handler to be called when a timer
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific SPI interrupts must be enabled
//! via SPI_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via SPI_clearInterruptFlag().
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_registerInterrupt(uint32_t moduleInstance,
void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the timer
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//!
//! This function unregisters the handler to be called when timer
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void SPI_unregisterInterrupt(uint32_t moduleInstance);
/* Backwards Compatibility Layer */
#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
#define EUSCI_B_SPI_MSB_FIRST UCMSB
#define EUSCI_B_SPI_LSB_FIRST 0x00
#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_B_SPI_3PIN UCMODE_0
#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
#define EUSCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_B_SPI_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_B_SPI_BUSY UCBUSY
#define EUSCI_B_SPI_NOT_BUSY 0x00
#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
#define EUSCI_A_SPI_MSB_FIRST UCMSB
#define EUSCI_A_SPI_LSB_FIRST 0x00
#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_A_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_A_SPI_3PIN UCMODE_0
#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
#define EUSCI_A_SPI_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_A_SPI_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_A_SPI_BUSY UCBUSY
#define EUSCI_A_SPI_NOT_BUSY 0x00
extern void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
uint8_t select4PinFunctionality);
extern void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
extern bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode);
extern void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
uint16_t clockPhase, uint16_t clockPolarity);
extern void EUSCI_A_SPI_transmitData(uint32_t baseAddress,
uint8_t transmitData);
extern uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress);
extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress,
uint8_t mask);
extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_A_SPI_enable(uint32_t baseAddress);
extern void EUSCI_A_SPI_disable(uint32_t baseAddress);
extern uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
extern uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(
uint32_t baseAddress);
extern bool EUSCI_A_SPI_isBusy(uint32_t baseAddress);
extern void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
uint8_t select4PinFunctionality);
extern void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
extern bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode);
extern void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
uint16_t clockPhase, uint16_t clockPolarity);
extern void EUSCI_B_SPI_transmitData(uint32_t baseAddress,
uint8_t transmitData);
extern uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress);
extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress,
uint8_t mask);
extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
extern void EUSCI_B_SPI_enable(uint32_t baseAddress);
extern void EUSCI_B_SPI_disable(uint32_t baseAddress);
extern uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
extern uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(
uint32_t baseAddress);
extern bool EUSCI_B_SPI_isBusy(uint32_t baseAddress);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* SPI_H_ */

239
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
Unescape Escape View File

@ -0,0 +1,239 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
#include <stdbool.h>
/* DriverLib Includes */
#include <sysctl.h>
#include <debug.h>
#ifdef DEBUG
static bool SysCtlSRAMBankValid(uint8_t sramBank)
{
return(
sramBank == SYSCTL_SRAM_BANK7 ||
sramBank == SYSCTL_SRAM_BANK6 ||
sramBank == SYSCTL_SRAM_BANK5 ||
sramBank == SYSCTL_SRAM_BANK4 ||
sramBank == SYSCTL_SRAM_BANK3 ||
sramBank == SYSCTL_SRAM_BANK2 ||
sramBank == SYSCTL_SRAM_BANK1
);
}
static bool SysCtlSRAMBankValidRet(uint8_t sramBank)
{
sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 &
SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 &
SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 &
SYSCTL_SRAM_BANK1);
return (sramBank == 0);
}
static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral)
{
hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT &
SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 &
SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 &
SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 &
SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 &
SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE &
SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 &
SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 &
SYSCTL_PERIPH_TIMER16_0);
return (hwPeripheral == 0);
}
#endif
uint_least32_t SysCtl_getSRAMSize(void)
{
return SYSCTL->rSRAM_SIZE;
}
uint_least32_t SysCtl_getFlashSize(void)
{
return SYSCTL->rFLASH_SIZE;
}
void SysCtl_disableNMISource(uint_fast8_t flags)
{
SYSCTL->rNMI_CTLSTAT.r &= ~(flags);
}
void SysCtl_enableNMISource(uint_fast8_t flags)
{
SYSCTL->rNMI_CTLSTAT.r |= flags;
}
uint_fast8_t SysCtl_getNMISourceStatus(void)
{
return SYSCTL->rNMI_CTLSTAT.r;
}
void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
{
ASSERT(SysCtlSRAMBankValid(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
;
SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
}
void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
{
ASSERT(SysCtlSRAMBankValid(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
;
switch (sramBank)
{
case SYSCTL_SRAM_BANK7:
sramBank = SYSCTL_SRAM_BANK6 + SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK6:
sramBank = SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+ SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK5:
sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3
+ SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK4:
sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
+ SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK3:
sramBank = SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK2:
sramBank = SYSCTL_SRAM_BANK1;
break;
case SYSCTL_SRAM_BANK1:
sramBank = 0;
break;
default:
return;
}
SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
}
void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
{
ASSERT(SysCtlSRAMBankValidRet(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
;
SYSCTL->rSRAM_BANKRET.r |= sramBank;
}
void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
{
ASSERT(SysCtlSRAMBankValidRet(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
;
SYSCTL->rSRAM_BANKRET.r &= ~sramBank;
}
void SysCtl_rebootDevice(void)
{
SYSCTL->rREBOOT_CTL.r = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
}
void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
{
ASSERT(SysCtlPeripheralIsValid(devices));
SYSCTL->rPERIHALT_CTL.r &= ~devices;
}
void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
{
ASSERT(SysCtlPeripheralIsValid(devices));
SYSCTL->rPERIHALT_CTL.r |= devices;
}
void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
{
if (resetType)
SYSCTL->rWDTRESET_CTL.r |=
SYSCTL_WDTRESET_CTL_TIMEOUT;
else
SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
}
void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
{
ASSERT(resetType <= SYSCTL_HARD_RESET);
if (resetType)
SYSCTL->rWDTRESET_CTL.r |=
SYSCTL_WDTRESET_CTL_VIOLATION;
else
SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
}
void SysCtl_enableGlitchFilter(void)
{
SYSCTL->rDIO_GLTFLT_CTL.r |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
}
void SysCtl_disableGlitchFilter(void)
{
SYSCTL->rDIO_GLTFLT_CTL.r &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
}
uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
uint32_t temperature)
{
return HWREG16(TLV_BASE + refVoltage + temperature);
}

448
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
Unescape Escape View File

@ -0,0 +1,448 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
//! \addtogroup sysctl_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <msp.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
#define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
#define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
#define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
#define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
#define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
#define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
#define SYSCTL_HARD_RESET 1
#define SYSCTL_SOFT_RESET 0
#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_DMA
#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_WDT
#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_ADC
#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_EUB3
#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_EUB2
#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_EUB1
#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_EUB0
#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_EUA3
#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_EUA2
#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_EUA1
#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_EUA0
#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_T32_0
#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_T16_3
#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_T16_2
#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_T16_1
#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_T16_0
#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
#define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
#define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
#define SYSCTL_REBOOT_KEY 0x6900
#define SYSCTL_1_2V_REF OFS_TLV_ADC14_REF1P2V_TS30C
#define SYSCTL_1_45V_REF OFS_TLV_ADC14_REF1P45V_TS30C
#define SYSCTL_2_5V_REF OFS_TLV_ADC14_REF2P5V_TS30C
#define SYSCTL_85_DEGREES_C 0
#define SYSCTL_30_DEGREES_C 16
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Gets the size of the SRAM.
//!
//! \return The total number of bytes of SRAM.
//
//*****************************************************************************
extern uint_least32_t SysCtl_getSRAMSize(void);
//*****************************************************************************
//
//! Gets the size of the flash.
//!
//! \return The total number of bytes of flash.
//
//*****************************************************************************
extern uint_least32_t SysCtl_getFlashSize(void);
//*****************************************************************************
//
//! Reboots the device and causes the device to re-initialize itself.
//!
//! \return This function does not return.
//
//*****************************************************************************
extern void SysCtl_rebootDevice(void);
//*****************************************************************************
//
//! Enables a set of banks in the SRAM. This can be used to optimize power
//! consumption when every SRAM bank isn't needed. It is important to note
//! that when a higher bank is enabled, all of the SRAM banks below that bank
//! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7,
//! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled
//! (SRAM_BANK0 is reserved and always enabled).
//!
//! \param sramBank The SRAM bank tier to enable.
//! Must be only one of the following values:
//! - \b SYSCTL_SRAM_BANK1,
//! - \b SYSCTL_SRAM_BANK2,
//! - \b SYSCTL_SRAM_BANK3,
//! - \b SYSCTL_SRAM_BANK4,
//! - \b SYSCTL_SRAM_BANK5,
//! - \b SYSCTL_SRAM_BANK6,
//! - \b SYSCTL_SRAM_BANK7
//!
//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
//!
//! \return None.
//
//*****************************************************************************
extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
//*****************************************************************************
//
//! Disables a set of banks in the SRAM. This can be used to optimize power
//! consumption when every SRAM bank isn't needed. It is important to note
//! that when a higher bank is disabled, all of the SRAM banks above that bank
//! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5,
//! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled.
//!
//! \param sramBank The SRAM bank tier to disable.
//! Must be only one of the following values:
//! - \b SYSCTL_SRAM_BANK1,
//! - \b SYSCTL_SRAM_BANK2,
//! - \b SYSCTL_SRAM_BANK3,
//! - \b SYSCTL_SRAM_BANK4,
//! - \b SYSCTL_SRAM_BANK5,
//! - \b SYSCTL_SRAM_BANK6,
//! - \b SYSCTL_SRAM_BANK7
//!
//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
//!
//! \return None.
//
//*****************************************************************************
extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
//*****************************************************************************
//
//! Enables retention of the specified SRAM bank register when the device goes
//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
//! banks specified with this function will be placed into retention mode. By
//! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is
//! disabled. Retention of individual banks can be set without the restrictions
//! of the enable/disable functions.
//!
//! \param sramBank The SRAM banks to enable retention
//! Can be a bitwise OR of the following values:
//! - \b SYSCTL_SRAM_BANK1,
//! - \b SYSCTL_SRAM_BANK2,
//! - \b SYSCTL_SRAM_BANK3,
//! - \b SYSCTL_SRAM_BANK4,
//! - \b SYSCTL_SRAM_BANK5,
//! - \b SYSCTL_SRAM_BANK6,
//! - \b SYSCTL_SRAM_BANK7
//! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
//!
//!
//! \return None.
//
//*****************************************************************************
extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
//*****************************************************************************
//
//! Disables retention of the specified SRAM bank register when the device goes
//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
//! banks specified with this function will not be placed into retention mode.
//! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved)
//! is disabled. Retention of individual banks can be set without the
//! restrictions of the enable/disable SRAM bank functions.
//!
//! \param sramBank The SRAM banks to disable retention
//! Can be a bitwise OR of the following values:
//! - \b SYSCTL_SRAM_BANK1,
//! - \b SYSCTL_SRAM_BANK2,
//! - \b SYSCTL_SRAM_BANK3,
//! - \b SYSCTL_SRAM_BANK4,
//! - \b SYSCTL_SRAM_BANK5,
//! - \b SYSCTL_SRAM_BANK6,
//! - \b SYSCTL_SRAM_BANK7
//! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
//*****************************************************************************
//
//! Makes it so that the provided peripherals will either halt execution after
//! a CPU HALT. Parameters in this function can be combined to account for
//! multiple peripherals. By default, all peripherals keep running after a
//! CPU HALT.
//!
//! \param devices The peripherals to continue running after a CPU HALT
//! This can be a bitwise OR of the following values:
//! - \b SYSCTL_PERIPH_DMA,
//! - \b SYSCTL_PERIPH_WDT,
//! - \b SYSCTL_PERIPH_ADC,
//! - \b SYSCTL_PERIPH_EUSCIB3,
//! - \b SYSCTL_PERIPH_EUSCIB2,
//! - \b SYSCTL_PERIPH_EUSCIB1
//! - \b SYSCTL_PERIPH_EUSCIB0,
//! - \b SYSCTL_PERIPH_EUSCIA3,
//! - \b SYSCTL_PERIPH_EUSCIA2
//! - \b SYSCTL_PERIPH_EUSCIA1,
//! - \b SYSCTL_PERIPH_EUSCIA0,
//! - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
//! - \b SYSCTL_PERIPH_TIMER16_3,
//! - \b SYSCTL_PERIPH_TIMER16_2,
//! - \b SYSCTL_PERIPH_TIMER16_1,
//! - \b SYSCTL_PERIPH_TIMER16_0
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
//*****************************************************************************
//
//! Makes it so that the provided peripherals will either halt execution after
//! a CPU HALT. Parameters in this function can be combined to account for
//! multiple peripherals. By default, all peripherals keep running after a
//! CPU HALT.
//!
//! \param devices The peripherals to disable after a CPU HALT
//!
//! The \e devices parameter can be a bitwise OR of the following values:
//! This can be a bitwise OR of the following values:
//! - \b SYSCTL_PERIPH_DMA,
//! - \b SYSCTL_PERIPH_WDT,
//! - \b SYSCTL_PERIPH_ADC,
//! - \b SYSCTL_PERIPH_EUSCIB3,
//! - \b SYSCTL_PERIPH_EUSCIB2,
//! - \b SYSCTL_PERIPH_EUSCIB1
//! - \b SYSCTL_PERIPH_EUSCIB0,
//! - \b SYSCTL_PERIPH_EUSCIA3,
//! - \b SYSCTL_PERIPH_EUSCIA2
//! - \b SYSCTL_PERIPH_EUSCIA1,
//! - \b SYSCTL_PERIPH_EUSCIA0,
//! - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
//! - \b SYSCTL_PERIPH_TIMER16_3,
//! - \b SYSCTL_PERIPH_TIMER16_2,
//! - \b SYSCTL_PERIPH_TIMER16_1,
//! - \b SYSCTL_PERIPH_TIMER16_0
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
//*****************************************************************************
//
//! Sets the type of RESET that happens when a watchdog timeout occurs.
//!
//! \param resetType The type of reset to set
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b SYSCTL_HARD_RESET,
//! - \b SYSCTL_SOFT_RESET
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
//*****************************************************************************
//
//! Sets the type of RESET that happens when a watchdog password violation
//! occurs.
//!
//! \param resetType The type of reset to set
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b SYSCTL_HARD_RESET,
//! - \b SYSCTL_SOFT_RESET
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
//*****************************************************************************
//
//! Disables NMIs for the provided modules. When disabled, a NMI flag will not
//! occur when a fault condition comes from the corresponding modules.
//!
//! \param flags The NMI sources to disable
//! Can be a bitwise OR of the following parameters:
//! - \b SYSCTL_NMIPIN_SRC,
//! - \b SYSCTL_PCM_SRC,
//! - \b SYSCTL_PSS_SRC,
//! - \b SYSCTL_CS_SRC
//!
//
//*****************************************************************************
extern void SysCtl_disableNMISource(uint_fast8_t flags);
//*****************************************************************************
//
//! Enables NMIs for the provided modules. When enabled, a NMI flag will
//! occur when a fault condition comes from the corresponding modules.
//!
//! \param flags The NMI sources to enable
//! Can be a bitwise OR of the following parameters:
//! - \b SYSCTL_NMIPIN_SRC,
//! - \b SYSCTL_PCM_SRC,
//! - \b SYSCTL_PSS_SRC,
//! - \b SYSCTL_CS_SRC
//!
//
//*****************************************************************************
extern void SysCtl_enableNMISource(uint_fast8_t flags);
//*****************************************************************************
//
//! Returns the current sources of NMIs that are enabled
//!
//! \return Bitwise OR of NMI flags that are enabled
//
//*****************************************************************************
extern uint_fast8_t SysCtl_getNMISourceStatus(void);
//*****************************************************************************
//
//! Enables glitch suppression on the reset pin of the device. Refer to the
//! device data sheet for specific information about glitch suppression
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_enableGlitchFilter(void);
//*****************************************************************************
//
//! Disables glitch suppression on the reset pin of the device. Refer to the
//! device data sheet for specific information about glitch suppression
//!
//! \return None.
//
//
//*****************************************************************************
extern void SysCtl_disableGlitchFilter(void);
//*****************************************************************************
//
//! Retrieves the calibration constant of the temperature sensor to be used
//! in temperature calculation.
//!
//! \param refVoltage Reference voltage being used.
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b SYSCTL_1_2V_REF
//! - \b SYSCTL_1_45V_REF
//! - \b SYSCTL_2_5V_REF
//!
//! \param temperature is the calibration temperature that the user wants to be
//! returned.
//!
//! The \e temperature parameter must be only one of the following values:
//! - \b SYSCTL_30_DEGREES_C
//! - \b SYSCTL_85_DEGREES_C
//!
//! \return None.
//
//
//*****************************************************************************
extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
uint32_t temperature);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __SYSCTL_H__

118
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
Unescape Escape View File

@ -0,0 +1,118 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <debug.h>
#include <interrupt.h>
#include <systick.h>
void SysTick_enableModule(void)
{
//
// Enable SysTick.
//
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
}
void SysTick_disableModule(void)
{
//
// Disable SysTick.
//
SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
}
void SysTick_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(FAULT_SYSTICK, intHandler);
}
void SysTick_unregisterInterrupt(void)
{
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(FAULT_SYSTICK);
}
void SysTick_enableInterrupt(void)
{
//
// Enable the SysTick interrupt.
//
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
void SysTick_disableInterrupt(void)
{
//
// Disable the SysTick interrupt.
//
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk);
}
void SysTick_setPeriod(uint32_t period)
{
//
// Check the arguments.
//
ASSERT((period > 0) && (period <= 16777216));
//
// Set the period of the SysTick counter.
//
SysTick->LOAD = period - 1;
}
uint32_t SysTick_getPeriod(void)
{
//
// Return the period of the SysTick counter.
//
return (SysTick->LOAD + 1);
}
uint32_t SysTick_getValue(void)
{
//
// Return the current value of the SysTick counter.
//
return (SysTick->VAL);
}

219
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
Unescape Escape View File

@ -0,0 +1,219 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This function starts the SysTick counter. If an interrupt handler has been
//! registered, it is called when the SysTick counter rolls over.
//!
//! \note Calling this function causes the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTick_setPeriod(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force the reload. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the supplied period on the next
//! clock.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_enableModule(void);
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This function stops the SysTick counter. If an interrupt handler has been
//! registered, it is not called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_disableModule(void);
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This function registers the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function unregisters the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_unregisterInterrupt(void);
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function enables the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler is not required to clear the SysTick
//! interrupt source because it is cleared automatically by the NVIC when the
//! interrupt handler is called.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_enableInterrupt(void);
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function disables the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_disableInterrupt(void);
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param period is the number of clock ticks in each period of the SysTick
//! counter and must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the \e period supplied here on
//! the next clock after SysTick is enabled.
//!
//! \return None.
//
//*****************************************************************************
extern void SysTick_setPeriod(uint32_t period);
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
extern uint32_t SysTick_getPeriod(void);
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter, which is
//! a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
extern uint32_t SysTick_getValue(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __SYSTICK_H__

148
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
Unescape Escape View File

@ -0,0 +1,148 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <timer32.h>
#include <interrupt.h>
#include <debug.h>
void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
uint32_t mode)
{
/* Setting up one shot or continuous mode */
if (mode == TIMER32_PERIODIC_MODE)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 1;
else if (mode == TIMER32_FREE_RUN_MODE)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 0;
else
ASSERT(false);
/* Setting the resolution of the timer */
if (resolution == TIMER32_1_MODULE6BIT)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 0;
else if (resolution == TIMER32_32BIT)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 1;
else
ASSERT(false);
/* Setting the PreScaler */
ASSERT(
resolution == TIMER32_PRESCALER_1
|| resolution == TIMER32_PRESCALER_16
|| resolution == TIMER32_PRESCALER_256);
HWREG32(timer + OFS_TIMER32_CONTROL1) =
(HWREG32(timer + OFS_TIMER32_CONTROL1)
& ~TIMER32_CONTROL1_PRESCALE_M) | preScaler;
}
void Timer32_setCount(uint32_t timer, uint32_t count)
{
if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
HWREG32(timer + OFS_TIMER32_LOAD1) = UINT16_MAX;
else
HWREG32(timer + OFS_TIMER32_LOAD1) = count;
}
void Timer32_setCountInBackground(uint32_t timer, uint32_t count)
{
if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
HWREG32(timer + OFS_TIMER32_BGLOAD1) = UINT16_MAX;
else
HWREG32(timer + OFS_TIMER32_BGLOAD1) = count;
}
uint32_t Timer32_getValue(uint32_t timer)
{
return HWREG32(timer + OFS_TIMER32_VALUE1);
}
void Timer32_startTimer(uint32_t timer, bool oneShot)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
if (oneShot)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
1;
else
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
0;
HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_ENABLE;
}
void Timer32_haltTimer(uint32_t timer)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_ENABLE;
}
void Timer32_enableInterrupt(uint32_t timer)
{
HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_IE;
}
void Timer32_disableInterrupt(uint32_t timer)
{
HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_IE;
}
void Timer32_clearInterruptFlag(uint32_t timer)
{
HWREG32(timer + OFS_TIMER32_INTCLR1) |= 0x01;
}
uint32_t Timer32_getInterruptStatus(uint32_t timer)
{
return HWREG32(timer + OFS_TIMER32_MIS1);
}
void Timer32_registerInterrupt(uint32_t timerInterrupt,
void (*intHandler)(void))
{
Interrupt_registerInterrupt(timerInterrupt, intHandler);
Interrupt_enableInterrupt(timerInterrupt);
}
void Timer32_unregisterInterrupt(uint32_t timerInterrupt)
{
Interrupt_disableInterrupt(timerInterrupt);
Interrupt_unregisterInterrupt(timerInterrupt);
}

359
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
Unescape Escape View File

@ -0,0 +1,359 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef TIMER32_H_
#define TIMER32_H_
//*****************************************************************************
//
//! \addtogroup timer32_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
//*****************************************************************************
//
// Control specific variables
//
//*****************************************************************************
#define TIMER_OFFSET 0x020
#define TIMER32_0_MODULE TIMER32_BASE
#define TIMER32_1_MODULE (TIMER32_BASE + OFS_TIMER32_LOAD2)
#define TIMER32_0_INTERRUPT INT_T32_INT1
#define TIMER32_1_INTERRUPT INT_T32_INT2
#define TIMER32_COMBINED_INTERRUPT INT_T32_INTC
#define TIMER32_1_MODULE6BIT 0x00
#define TIMER32_32BIT 0x01
#define TIMER32_PRESCALER_1 0x00
#define TIMER32_PRESCALER_16 0x04
#define TIMER32_PRESCALER_256 0x08
#define TIMER32_FREE_RUN_MODE 0x00
#define TIMER32_PERIODIC_MODE 0x01
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! Initializes the Timer32 module
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! \param preScaler is the prescaler (or divider) to apply to the clock
//! source given to the Timer32 module.
//! Valid values are
//! - \b TIMER32_PRESCALER_1 [DEFAULT]
//! - \b TIMER32_PRESCALER_16
//! - \b TIMER32_PRESCALER_256
//! \param resolution is the bit resolution of the Timer32 module.
//! Valid values are
//! - \b TIMER32_1_MODULE6BIT [DEFAULT]
//! - \b TIMER32_32BIT
//! \param mode selects between free run and periodic mode. In free run
//! mode, the value of the timer is reset to UINT16_MAX (for 16-bit mode) or
//! UINT32_MAX (for 16-bit mode) when the timer reaches zero. In periodic mode,
//! the timer is reset to the value set by the Timer32_setCount function.
//! Valid values are
//! - \b TIMER32_FREE_RUN_MODE [DEFAULT]
//! - \b TIMER32_PERIODIC_MODE
//!
//!
//! \return None.
//
//*****************************************************************************
extern void Timer32_initModule(uint32_t timer, uint32_t preScaler,
uint32_t resolution, uint32_t mode);
//*****************************************************************************
//
//! Sets the count of the timer and resets the current value to the value
//! passed. This value is set on the next rising edge of the clock provided to
//! the timer module
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! \param count Value of the timer to set. Note that
//! if the timer is in 16-bit mode and a value is passed in that exceeds
//! UINT16_MAX, the value will be truncated to UINT16_MAX.
//!
//! Also note that if the timer is operating in periodic mode, the value passed
//! into this function will represent the new period of the timer (the value
//! which is reloaded into the timer each time it reaches a zero value).
//!
//! \return None
//
//*****************************************************************************
extern void Timer32_setCount(uint32_t timer, uint32_t count);
//*****************************************************************************
//
//! Sets the count of the timer without resetting the current value. When the
//! current value of the timer reaches zero, the value passed into this function
//! will be set as the new count value.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! \param count Value of the timer to set in the background. Note that
//! if the timer is in 16-bit mode and a value is passed in that exceeds
//! UINT16_MAX, the value will be truncated to UINT16_MAX.
//!
//! Also note that if the timer is operating in periodic mode, the value passed
//! into this function will represent the new period of the timer (the value
//! which is reloaded into the timer each time it reaches a zero value).
//!
//! \return None
//
//*****************************************************************************
extern void Timer32_setCountInBackground(uint32_t timer, uint32_t count);
//*****************************************************************************
//
//! Returns the current value of the timer.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! \return The current count of the timer.
//
//*****************************************************************************
extern uint32_t Timer32_getValue(uint32_t timer);
//*****************************************************************************
//
//! Starts the timer. The Timer32_initModule function should be called (in
//! conjunction with Timer32_setCount if periodic mode is desired) prior to
// starting the timer.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! \param oneShot sets whether the Timer32 module operates in one shot
//! or continuous mode. In one shot mode, the timer will halt when a zero is
//! reached and stay halted until either:
//! - The user calls the Timer32PeriodSet function
//! - The Timer32_initModule is called to reinitialize the timer with one-shot
//! mode disabled.
//!
//! A true value will cause the timer to operate in one shot mode while a false
//! value will cause the timer to operate in continuous mode
//!
//! \return None
//
//*****************************************************************************
extern void Timer32_startTimer(uint32_t timer, bool oneShot);
//*****************************************************************************
//
//! Halts the timer. Current count and setting values are preserved.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! \return None
//
//*****************************************************************************
extern void Timer32_haltTimer(uint32_t timer);
//*****************************************************************************
//
//! Enables a Timer32 interrupt source.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! Enables the indicated Timer32 interrupt source.
//!
//! \return None.
//
//*****************************************************************************
extern void Timer32_enableInterrupt(uint32_t timer);
//*****************************************************************************
//
//! Disables a Timer32 interrupt source.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! Disables the indicated Timer32 interrupt source.
//!
//! \return None.
//
//*****************************************************************************
extern void Timer32_disableInterrupt(uint32_t timer);
//*****************************************************************************
//
//! Clears Timer32 interrupt source.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! The Timer32 interrupt source is cleared, so that it no longer asserts.
//!
//! \return None.
//
//*****************************************************************************
extern void Timer32_clearInterruptFlag(uint32_t timer);
//*****************************************************************************
//
//! Gets the current Timer32 interrupt status.
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//!
//! This returns the interrupt status for the Timer32 module. A positive value
//! will indicate that an interrupt is pending while a zero value will indicate
//! that no interrupt is pending.
//!
//! \return The current interrupt status
//
//*****************************************************************************
extern uint32_t Timer32_getInterruptStatus(uint32_t timer);
//*****************************************************************************
//
//! Registers an interrupt handler for Timer32 interrupts.
//!
//! \param timerInterrupt is the specific interrupt to register. For the
//! Timer32 module, there are a total of three different interrupts: one
//! interrupt for each two Timer32 modules, and a "combined" interrupt which
//! is a logical OR of each individual Timer32 interrupt.
//! - \b TIMER32_0_INTERRUPT
//! - \b TIMER32_1_INTERRUPT
//! - \b TIMER32_COMBINED_INTERRUPT
//!
//! \param intHandler is a pointer to the function to be called when the
//! Timer32 interrupt occurs.
//!
//! This function registers the handler to be called when an Timer32
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific Timer32 interrupts must be enabled
//! via Timer32_enableInterrupt(). It is the interrupt handler's
//! responsibility to clear the interrupt source
//! via Timer32_clearInterruptFlag().
//!
//! \return None.
//
//*****************************************************************************
extern void Timer32_registerInterrupt(uint32_t timerInterrupt,
void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the Timer32 interrupt.
//!
//! \param timerInterrupt is the specific interrupt to register. For the
//! Timer32 module, there are a total of three different interrupts: one
//! interrupt for each two Timer32 modules, and a "combined" interrupt which
//! is a logical OR of each individual Timer32 interrupt.
//! - \b TIMER32_0_INTERRUPT
//! - \b TIMER32_1_INTERRUPT
//! - \b TIMER32_COMBINED_INTERRUPT
//!
//! This function unregisters the handler to be called when a Timer32
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void Timer32_unregisterInterrupt(uint32_t timerInterrupt);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* TIMER32_H_ */

796
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
Unescape Escape View File

@ -0,0 +1,796 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <timer_a.h>
#include <interrupt.h>
#include <debug.h>
static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
uint16_t clockSourceDivider)
{
TIMER_A_CMSIS(timer)->rCTL.r &= ~ID__8;
TIMER_A_CMSIS(timer)->rEX0.r &= ~TAIDEX_7;
switch (clockSourceDivider)
{
case TIMER_A_CLOCKSOURCE_DIVIDER_1:
case TIMER_A_CLOCKSOURCE_DIVIDER_2:
TIMER_A_CMSIS(timer)->rCTL.r |= ((clockSourceDivider - 1) << 6);
TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_4:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_8:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_3:
case TIMER_A_CLOCKSOURCE_DIVIDER_5:
case TIMER_A_CLOCKSOURCE_DIVIDER_6:
case TIMER_A_CLOCKSOURCE_DIVIDER_7:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__1;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_10:
case TIMER_A_CLOCKSOURCE_DIVIDER_12:
case TIMER_A_CLOCKSOURCE_DIVIDER_14:
case TIMER_A_CLOCKSOURCE_DIVIDER_16:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__2;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 2 - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_20:
case TIMER_A_CLOCKSOURCE_DIVIDER_24:
case TIMER_A_CLOCKSOURCE_DIVIDER_28:
case TIMER_A_CLOCKSOURCE_DIVIDER_32:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 4 - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_40:
case TIMER_A_CLOCKSOURCE_DIVIDER_48:
case TIMER_A_CLOCKSOURCE_DIVIDER_56:
case TIMER_A_CLOCKSOURCE_DIVIDER_64:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 8 - 1);
break;
}
}
void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode)
{
ASSERT(
(TIMER_A_UPDOWN_MODE == timerMode)
|| (TIMER_A_CONTINUOUS_MODE == timerMode)
|| (TIMER_A_UP_MODE == timerMode));
TIMER_A_CMSIS(timer)->rCTL.r |= timerMode;
}
void Timer_A_configureContinuousMode(uint32_t timer,
const Timer_A_ContinuousModeConfig *config)
{
ASSERT(
(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
== config->clockSource));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
ASSERT(
(TIMER_A_TAIE_INTERRUPT_ENABLE == config->timerInterruptEnable_TAIE)
|| (TIMER_A_TAIE_INTERRUPT_DISABLE
== config->timerInterruptEnable_TAIE));
ASSERT(
(TIMER_A_CLOCKSOURCE_DIVIDER_1 == config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_2
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_4
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_8
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_3
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_5
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_6
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_7
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_10
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_12
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_14
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_16
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_20
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_24
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_28
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_32
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_40
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_48
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_56
== config->clockSourceDivider)
|| (TIMER_A_CLOCKSOURCE_DIVIDER_64
== config->clockSourceDivider));
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r = (TIMER_A_CMSIS(timer)->rCTL.r
& ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+ TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR
+ TIMER_A_TAIE_INTERRUPT_ENABLE))
| (config->clockSource + config->timerClear
+ config->timerInterruptEnable_TAIE);
}
void Timer_A_configureUpMode(uint32_t timer, const Timer_A_UpModeConfig *config)
{
ASSERT(
(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
== config->clockSource));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + config->timerClear
+ config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
else
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
}
void Timer_A_configureUpDownMode(uint32_t timer,
const Timer_A_UpDownModeConfig *config)
{
ASSERT(
(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
== config->clockSource));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
ASSERT(
(TIMER_A_DO_CLEAR == config->timerClear)
|| (TIMER_A_SKIP_CLEAR == config->timerClear));
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_STOP_MODE
+ config->timerClear + config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
else
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
}
void Timer_A_initCapture(uint32_t timer,
const Timer_A_CaptureModeConfig *config)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== config->captureRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== config->captureRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== config->captureRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== config->captureRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== config->captureRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== config->captureRegister));
ASSERT(
(TIMER_A_CAPTUREMODE_NO_CAPTURE == config->captureMode)
|| (TIMER_A_CAPTUREMODE_RISING_EDGE == config->captureMode)
|| (TIMER_A_CAPTUREMODE_FALLING_EDGE == config->captureMode)
|| (TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
== config->captureMode));
ASSERT(
(TIMER_A_CAPTURE_INPUTSELECT_CCIxA == config->captureInputSelect)
|| (TIMER_A_CAPTURE_INPUTSELECT_CCIxB
== config->captureInputSelect)
|| (TIMER_A_CAPTURE_INPUTSELECT_GND
== config->captureInputSelect)
|| (TIMER_A_CAPTURE_INPUTSELECT_Vcc
== config->captureInputSelect));
ASSERT(
(TIMER_A_CAPTURE_ASYNCHRONOUS == config->synchronizeCaptureSource)
|| (TIMER_A_CAPTURE_SYNCHRONOUS
== config->synchronizeCaptureSource));
ASSERT(
(TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
== config->captureInterruptEnable)
|| (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
== config->captureInterruptEnable));
ASSERT(
(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE_RESET
== config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_SET_RESET
== config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE == config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET == config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE_SET
== config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET_SET
== config->captureOutputMode));
if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
{
//CaptureCompare register 0 only supports certain modes
ASSERT(
(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE
== config->captureOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET
== config->captureOutputMode));
}
HWREG16(timer + config->captureRegister) =
(HWREG16(timer + config->captureRegister)
& ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
| TIMER_A_CAPTURE_INPUTSELECT_Vcc
| TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
| TIMER_A_TAIE_INTERRUPT_ENABLE | CM_3))
| (config->captureMode | config->captureInputSelect
| config->synchronizeCaptureSource
| config->captureInterruptEnable
| config->captureOutputMode | CAP);
}
void Timer_A_initCompare(uint32_t timer,
const Timer_A_CompareModeConfig *config)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== config->compareRegister));
ASSERT(
(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
== config->compareInterruptEnable)
|| (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
== config->compareInterruptEnable));
ASSERT(
(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE_RESET
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_SET_RESET
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE_SET
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET_SET
== config->compareOutputMode));
if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
{
//CaptureCompare register 0 only supports certain modes
ASSERT(
(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET
== config->compareOutputMode));
}
HWREG16(timer + config->compareRegister) =
(HWREG16(timer + config->compareRegister)
& ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
| TIMER_A_OUTPUTMODE_RESET_SET | CAP))
| (config->compareInterruptEnable
+ config->compareOutputMode);
HWREG16(timer + config->compareRegister + OFS_TA0R) = config->compareValue;
}
uint16_t Timer_A_getCounterValue(uint32_t timer)
{
uint16_t voteOne, voteTwo, res;
voteTwo = TIMER_A_CMSIS(timer)->rR;
do
{
voteOne = voteTwo;
voteTwo = TIMER_A_CMSIS(timer)->rR;
if (voteTwo > voteOne)
res = voteTwo - voteOne;
else if (voteOne > voteTwo)
res = voteOne - voteTwo;
else
res = 0;
} while (res > TIMER_A_THRESHOLD);
return voteTwo;
}
void Timer_A_clearTimer(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r , TACLR_OFS) = 1;
}
uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
uint_fast16_t captureCompareRegister, uint_fast16_t synchronizedSetting)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
ASSERT(
(TIMER_A_READ_CAPTURE_COMPARE_INPUT == synchronizedSetting)
|| (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
== synchronizedSetting));
if (HWREG16(timer + captureCompareRegister) & synchronizedSetting)
return TIMER_A_CAPTURECOMPARE_INPUT_HIGH;
else
return TIMER_A_CAPTURECOMPARE_INPUT_LOW;
}
uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
if (HWREGBIT16(timer + captureCompareRegister, OUT_OFS))
return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH;
else
return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW;
}
uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
return HWREG16(timer + OFS_TA0R + captureCompareRegister);
}
void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
uint_fast16_t captureCompareRegister,
uint_fast8_t outputModeOutBitValue)
{
TIMER_A_setOutputForOutputModeOutBitValue(timer, captureCompareRegister,
outputModeOutBitValue);
}
void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
{
ASSERT(
(TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
|| (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
== config->clockSource));
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== config->compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== config->compareRegister));
ASSERT(
(TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE_RESET
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_SET_RESET
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_TOGGLE_SET
== config->compareOutputMode)
|| (TIMER_A_OUTPUTMODE_RESET_SET
== config->compareOutputMode));
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_UP_MODE
+ TIMER_A_DO_CLEAR);
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
HWREG16(timer + OFS_TA0CCTL0) &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+ TIMER_A_OUTPUTMODE_RESET_SET);
HWREG16(timer + config->compareRegister) |= config->compareOutputMode;
HWREG16(timer + config->compareRegister + OFS_TA0R) = config->dutyCycle;
}
void Timer_A_stopTimer(uint32_t timer)
{
TIMER_A_CMSIS(timer)->rCTL.r &= ~MC_3;
}
void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
uint_fast16_t compareValue)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister));
HWREG16(timer + compareRegister + OFS_TA0R) = compareValue;
}
void Timer_A_clearInterruptFlag(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIFG_OFS) = 0;
}
void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
HWREGBIT16(timer + captureCompareRegister, CCIFG_OFS) = 0;
}
void Timer_A_enableInterrupt(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 1;
}
void Timer_A_disableInterrupt(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 0;
}
uint32_t Timer_A_getInterruptStatus(uint32_t timer)
{
return TIMER_A_CMSIS(timer)->rCTL.b.bIFG;
}
void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 1;
}
void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
ASSERT(
(TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_1
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_2
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_3
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_4
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5
== captureCompareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 0;
}
uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister, uint_fast16_t mask)
{
return HWREG16(timer + captureCompareRegister) & mask;
}
uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
{
if (TIMER_A_CMSIS(timer)->rCTL.r & TAIE)
{
return Timer_A_getInterruptStatus(timer);
} else
{
return 0;
}
}
uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
if (HWREGBIT16(timer + captureCompareRegister, CCIE_OFS))
return Timer_A_getCaptureCompareInterruptStatus(timer,
captureCompareRegister,
TIMER_A_CAPTURE_OVERFLOW |
TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);
else
return 0;
}
void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect,
void (*intHandler)(void))
{
if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
{
switch (timer)
{
case TIMER_A0_MODULE:
Interrupt_registerInterrupt(INT_TA0_0, intHandler);
Interrupt_enableInterrupt(INT_TA0_0);
break;
case TIMER_A1_MODULE:
Interrupt_registerInterrupt(INT_TA1_0, intHandler);
Interrupt_enableInterrupt(INT_TA1_0);
break;
case TIMER_A2_MODULE:
Interrupt_registerInterrupt(INT_TA2_0, intHandler);
Interrupt_enableInterrupt(INT_TA2_0);
break;
case TIMER_A3_MODULE:
Interrupt_registerInterrupt(INT_TA3_0, intHandler);
Interrupt_enableInterrupt(INT_TA3_0);
break;
default:
ASSERT(false);
}
} else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
{
switch (timer)
{
case TIMER_A0_MODULE:
Interrupt_registerInterrupt(INT_TA0_N, intHandler);
Interrupt_enableInterrupt(INT_TA0_N);
break;
case TIMER_A1_MODULE:
Interrupt_registerInterrupt(INT_TA1_N, intHandler);
Interrupt_enableInterrupt(INT_TA1_N);
break;
case TIMER_A2_MODULE:
Interrupt_registerInterrupt(INT_TA2_N, intHandler);
Interrupt_enableInterrupt(INT_TA2_N);
break;
case TIMER_A3_MODULE:
Interrupt_registerInterrupt(INT_TA3_N, intHandler);
Interrupt_enableInterrupt(INT_TA3_N);
break;
default:
ASSERT(false);
}
} else
{
ASSERT(false);
}
}
void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect)
{
if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
{
switch (timer)
{
case TIMER_A0_MODULE:
Interrupt_disableInterrupt(INT_TA0_0);
Interrupt_unregisterInterrupt(INT_TA0_0);
break;
case TIMER_A1_MODULE:
Interrupt_disableInterrupt(INT_TA1_0);
Interrupt_unregisterInterrupt(INT_TA1_0);
break;
case TIMER_A2_MODULE:
Interrupt_disableInterrupt(INT_TA2_0);
Interrupt_unregisterInterrupt(INT_TA2_0);
break;
case TIMER_A3_MODULE:
Interrupt_disableInterrupt(INT_TA3_0);
Interrupt_unregisterInterrupt(INT_TA3_0);
break;
default:
ASSERT(false);
}
} else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
{
switch (timer)
{
case TIMER_A0_MODULE:
Interrupt_disableInterrupt(INT_TA0_N);
Interrupt_unregisterInterrupt(INT_TA0_N);
break;
case TIMER_A1_MODULE:
Interrupt_disableInterrupt(INT_TA1_N);
Interrupt_unregisterInterrupt(INT_TA1_N);
break;
case TIMER_A2_MODULE:
Interrupt_disableInterrupt(INT_TA2_N);
Interrupt_unregisterInterrupt(INT_TA2_N);
break;
case TIMER_A3_MODULE:
Interrupt_disableInterrupt(INT_TA3_N);
Interrupt_unregisterInterrupt(INT_TA3_N);
break;
default:
ASSERT(false);
}
} else
{
ASSERT(false);
}
}

1306
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
View File

File diff suppressed because it is too large Load Diff

396
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
Unescape Escape View File

@ -0,0 +1,396 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#include <uart.h>
#include <interrupt.h>
#include <debug.h>
#include <eusci.h>
bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
{
bool retVal = true;
ASSERT(
(EUSCI_A_UART_MODE == config->uartMode)
|| (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
== config->uartMode)
|| (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
== config->uartMode)
|| (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
== config->uartMode));
ASSERT(
(EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_A_UART_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
|| (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
ASSERT(
(EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
|| (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
ASSERT(
(EUSCI_A_UART_NO_PARITY == config->parity)
|| (EUSCI_A_UART_ODD_PARITY == config->parity)
|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
/* Disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
/* Clock source select */
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_3)
| config->selectClockSource;
/* MSB, LSB select */
if (config->msborLsbFirst)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 0;
/* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
if (config->numberofStopBits)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 0;
/* Parity */
switch (config->parity)
{
case EUSCI_A_UART_NO_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 0;
break;
case EUSCI_A_UART_ODD_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 0;
break;
case EUSCI_A_UART_EVEN_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 1;
break;
}
/* BaudRate Control Register */
EUSCI_A_CMSIS(moduleInstance)->rBRW = config->clockPrescalar;
EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = ((config->secondModReg << 8)
+ (config->firstModReg << 4) + config->overSampling);
/* Asynchronous mode & 8 bit character select & clear mode */
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSYNC | UC7BIT | UCMODE_3 | UCRXEIE | UCBRKIE | UCDORM
| UCTXADDR | UCTXBRK)) | config->uartMode;
return retVal;
}
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
}
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCRXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
;
return EUSCI_A_CMSIS(moduleInstance)->rRXBUF.r;
}
void UART_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 0;
}
void UART_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
}
uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
{
ASSERT(
0x00 != mask
&& (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
+ EUSCI_A_UART_OVERRUN_ERROR
+ EUSCI_A_UART_PARITY_ERROR
+ EUSCI_A_UART_BREAK_DETECT
+ EUSCI_A_UART_RECEIVE_ERROR
+ EUSCI_A_UART_ADDRESS_RECEIVED
+ EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
return EUSCI_A_CMSIS(moduleInstance)->rSTATW.r & mask;
}
void UART_setDormant(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 1;
}
void UART_resetDormant(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 0;
}
void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
{
/* Set UCTXADDR bit */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXADDR_OFS) = 1;
/* Place next byte to be sent into the transmit buffer */
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitAddress;
}
void UART_transmitBreak(uint32_t moduleInstance)
{
/* Set UCTXADDR bit */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXBRK_OFS) = 1;
/* If current mode is automatic baud-rate detection */
if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
== (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r =
EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
else
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = DEFAULT_SYNC;
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
;
}
uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCA0RXBUF;
}
uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCA0TXBUF;
}
void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
{
ASSERT(
(EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r & ~(UCGLIT_M))
| deglitchTime;
}
void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
uint8_t locMask;
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT
| EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
locMask = (mask
& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rIE.r |= locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r |= locMask;
}
void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
uint8_t locMask;
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT
| EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
locMask = (mask
& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rIE.r &= ~locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r &= ~locMask;
}
uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
return EUSCI_A_CMSIS(moduleInstance)->rIFG.r & mask;
}
uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
{
uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->rIE.r;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
}
if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
}
intEnabled = EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
}
if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
}
return intStatus;
}
void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
//Clear the UART interrupt source.
EUSCI_A_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
}
void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
case EUSCI_A0_MODULE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
case EUSCI_A1_MODULE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
#ifdef EUSCI_A2_MODULE
case EUSCI_A2_MODULE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
#ifdef EUSCI_A3_MODULE
case EUSCI_A3_MODULE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
#endif
default:
ASSERT(false);
}
}
void UART_unregisterInterrupt(uint32_t moduleInstance)
{
switch (moduleInstance)
{
case EUSCI_A0_MODULE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
case EUSCI_A1_MODULE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
#ifdef EUSCI_A2_MODULE
case EUSCI_A2_MODULE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
#ifdef EUSCI_A3_MODULE
case EUSCI_A3_MODULE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;
#endif
default:
ASSERT(false);
}
}

760
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
Unescape Escape View File

@ -0,0 +1,760 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef UART_H_
#define UART_H_
//*****************************************************************************
//
//! \addtogroup uart_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
#include <msp.h>
#include "eusci.h"
#define DEFAULT_SYNC 0x00
#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
#define EUSCI_A_UART_NO_PARITY 0x00
#define EUSCI_A_UART_ODD_PARITY 0x01
#define EUSCI_A_UART_EVEN_PARITY 0x02
#define EUSCI_A_UART_MSB_FIRST UCMSB
#define EUSCI_A_UART_LSB_FIRST 0x00
#define EUSCI_A_UART_MODE UCMODE_0
#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1
#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2
#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3
#define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_A_UART_ONE_STOP_BIT 0x00
#define EUSCI_A_UART_TWO_STOP_BITS UCSPB
#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01
#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00
#define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE
#define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE
#define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE
#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE
#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG
#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG
#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG
#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG
#define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN
#define EUSCI_A_UART_FRAMING_ERROR UCFE
#define EUSCI_A_UART_OVERRUN_ERROR UCOE
#define EUSCI_A_UART_PARITY_ERROR UCPE
#define EUSCI_A_UART_BREAK_DETECT UCBRK
#define EUSCI_A_UART_RECEIVE_ERROR UCRXERR
#define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR
#define EUSCI_A_UART_IDLELINE UCIDLE
#define EUSCI_A_UART_BUSY UCBUSY
#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00
#define EUSCI_A_UART_DEGLITCH_TIME_50ns 0x0001
#define EUSCI_A_UART_DEGLITCH_TIME_100ns 0x0002
#define EUSCI_A_UART_DEGLITCH_TIME_200ns (0x0001 + 0x0002)
//*****************************************************************************
//
//! \typedef eUSCI_eUSCI_UART_Config
//! \brief Type definition for \link _eUSCI_UART_Config \endlink
//! structure
//!
//! \struct _eUSCI_eUSCI_UART_Config
//! \brief Configuration structure for compare mode in the \b UART module. See
//! \link UART_initModule \endlink for parameter
//! documentation.
//
//*****************************************************************************
typedef struct _eUSCI_eUSCI_UART_Config
{
uint_fast8_t selectClockSource;
uint_fast16_t clockPrescalar;
uint_fast8_t firstModReg;
uint_fast8_t secondModReg;
uint_fast8_t parity;
uint_fast16_t msborLsbFirst;
uint_fast16_t numberofStopBits;
uint_fast16_t uartMode;
uint_fast8_t overSampling;
} eUSCI_UART_Config;
//*****************************************************************************
//
//! Initialization routine for the UART block. The values to be written
//! into the UCAxBRW and UCAxMCTLW registers should be pre-computed and passed
//! into the initialization function
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! \param config Configuration structure for the UART module
//!
//! <hr>
//! <b>Configuration options for \link eUSCI_UART_Config \endlink
//! structure.</b>
//! <hr>
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.
//! \param selectClockSource selects Clock source. Valid values are
//! - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK
//! - \b EUSCI_A_UART_CLOCKSOURCE_ACLK
//! \param clockPrescalar is the value to be written into UCBRx bits
//! \param firstModReg is First modulation stage register setting. This
//! value is a pre-calculated value which can be obtained from the Device
//! User Guide.This value is written into UCBRFx bits of UCAxMCTLW.
//! \param secondModReg is Second modulation stage register setting.
//! This value is a pre-calculated value which can be obtained from the
//! Device User Guide. This value is written into UCBRSx bits of
//! UCAxMCTLW.
//! \param parity is the desired parity. Valid values are
//! - \b EUSCI_A_UART_NO_PARITY [Default Value],
//! - \b EUSCI_A_UART_ODD_PARITY,
//! - \b EUSCI_A_UART_EVEN_PARITY
//! \param msborLsbFirst controls direction of receive and transmit shift
//! register. Valid values are
//! - \b EUSCI_A_UART_MSB_FIRST
//! - \b EUSCI_A_UART_LSB_FIRST [Default Value]
//! \param numberofStopBits indicates one/two STOP bits
//! Valid values are
//! - \b EUSCI_A_UART_ONE_STOP_BIT [Default Value]
//! - \b EUSCI_A_UART_TWO_STOP_BITS
//! \param uartMode selects the mode of operation
//! Valid values are
//! - \b EUSCI_A_UART_MODE [Default Value],
//! - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE,
//! - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE,
//! - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
//! \param overSampling indicates low frequency or oversampling baud
//! generation
//! Valid values are
//! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION
//! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION
//!
//! Upon successful initialization of the UART block, this function
//! will have initialized the module, but the UART block still remains
//! disabled and must be enabled with UART_enableModule()
//!
//! Refer to
//! <a href="http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html">
//! this calculator </a> for help on calculating values for the parameters.
//!
//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB,
//! \b UCMODEx, \b UCSYNC bits of \b UCAxCTL0 and \b UCSSELx,
//! \b UCSWRST bits of \b UCAxCTL1
//!
//! \return true or
//! STATUS_FAIL of the initialization process
//
//*****************************************************************************
extern bool UART_initModule(uint32_t moduleInstance,
const eUSCI_UART_Config *config);
//*****************************************************************************
//
//! Transmits a byte from the UART Module.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param transmitData data to be transmitted from the UART module
//!
//! This function will place the supplied data into UART transmit data register
//! to start transmission
//!
//! Modified register is \b UCAxTXBUF
//! \return None.
//
//*****************************************************************************
extern void UART_transmitData(uint32_t moduleInstance,
uint_fast8_t transmitData);
//*****************************************************************************
//
//! Receives a byte that has been sent to the UART Module.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! This function reads a byte of data from the UART receive data Register.
//!
//! Modified register is \b UCAxRXBUF
//!
//! \return Returns the byte received from by the UART module, cast as an
//! uint8_t.
//
//*****************************************************************************
extern uint8_t UART_receiveData(uint32_t moduleInstance);
//*****************************************************************************
//
//! Enables the UART block.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! This will enable operation of the UART block.
//!
//! Modified register is \b UCAxCTL1
//!
//! \return None.
//
//*****************************************************************************
extern void UART_enableModule(uint32_t moduleInstance);
//*****************************************************************************
//
//! Disables the UART block.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! This will disable operation of the UART block.
//!
//! Modified register is \b UCAxCTL1
//!
//! \return None.
//
//*****************************************************************************
extern void UART_disableModule(uint32_t moduleInstance);
//*****************************************************************************
//
//! Gets the current UART status flags.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param mask is the masked interrupt flag status to be returned.
//!
//! This returns the status for the UART module based on which
//! flag is passed. mask parameter can be either any of the following
//! selection.
//! - \b EUSCI_A_UART_LISTEN_ENABLE
//! - \b EUSCI_A_UART_FRAMING_ERROR
//! - \b EUSCI_A_UART_OVERRUN_ERROR
//! - \b EUSCI_A_UART_PARITY_ERROR
//! - \b eUARTBREAK_DETECT
//! - \b EUSCI_A_UART_RECEIVE_ERROR
//! - \b EUSCI_A_UART_ADDRESS_RECEIVED
//! - \b EUSCI_A_UART_IDLELINE
//! - \b EUSCI_A_UART_BUSY
//!
//! Modified register is \b UCAxSTAT
//!
//! \return the masked status flag
//
//*****************************************************************************
extern uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance,
uint_fast8_t mask);
//*****************************************************************************
//
//! Sets the UART module in dormant mode
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! Puts USCI in sleep mode
//! Only characters that are preceded by an idle-line or with address bit set
//! UCRXIFG. In UART mode with automatic baud-rate detection, only the
//! combination of a break and synch field sets UCRXIFG.
//!
//! Modified register is \b UCAxCTL1
//!
//! \return None.
//
//*****************************************************************************
extern void UART_setDormant(uint32_t moduleInstance);
//*****************************************************************************
//
//! Re-enables UART module from dormant mode
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! Not dormant. All received characters set UCRXIFG.
//!
//! Modified bits are \b UCDORM of \b UCAxCTL1 register.
//!
//! \return None.
//
//*****************************************************************************
extern void UART_resetDormant(uint32_t moduleInstance);
//*****************************************************************************
//
//! Transmits the next byte to be transmitted marked as address depending on
//! selected multiprocessor mode
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param transmitAddress is the next byte to be transmitted
//!
//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
//!
//! \return None.
//
//*****************************************************************************
extern void UART_transmitAddress(uint32_t moduleInstance,
uint_fast8_t transmitAddress);
//*****************************************************************************
//
//! Transmit break. Transmits a break with the next write to the transmit
//! buffer. In UART mode with automatic baud-rate detection,
//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to
//! generate the required break/synch fields.
//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer.
//! Also ensures module is ready for transmitting the next data
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! asEUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
//!
//! \return None.
//
//*****************************************************************************
extern void UART_transmitBreak(uint32_t moduleInstance);
//*****************************************************************************
//
//! Returns the address of the RX Buffer of the UART for the DMA module.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! Returns the address of the UART RX Buffer. This can be used in conjunction
//! with the DMA to store the received data directly to memory.
//!
//! \return None
//
//*****************************************************************************
extern uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
//*****************************************************************************
//
//! Returns the address of the TX Buffer of the UART for the DMA module.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! Returns the address of the UART TX Buffer. This can be used in conjunction
//! with the DMA to obtain transmitted data directly from memory.
//!
//! \return None
//
//*****************************************************************************
extern uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
//*****************************************************************************
//
//! Sets the deglitch time
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param deglitchTime is the selected deglitch time
//! Valid values are
//! - \b EUSCI_A_UART_DEGLITCH_TIME_2ns
//! - \b EUSCI_A_UART_DEGLITCH_TIME_50ns
//! - \b EUSCI_A_UART_DEGLITCH_TIME_100ns
//! - \b EUSCI_A_UART_DEGLITCH_TIME_200ns
//!
//!
//! Returns the address of the UART TX Buffer. This can be used in conjunction
//! with the DMA to obtain transmitted data directly from memory.
//!
//! \return None
//
//*****************************************************************************
extern void UART_selectDeglitchTime(uint32_t moduleInstance,
uint32_t deglitchTime);
//*****************************************************************************
//
//! Enables individual UART interrupt sources.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param mask is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated UART interrupt sources. The interrupt flag is first
//! and then the corresponding interrupt is enabled. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt
//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive
//! erroneous-character interrupt enable
//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt
//! enable
//!
//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
//!
//! \return None.
//
//*****************************************************************************
extern void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//*****************************************************************************
//
//! Disables individual UART interrupt sources.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param mask is the bit mask of the interrupt sources to be
//! disabled.
//!
//! Disables the indicated UART interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt
//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive
//! erroneous-character interrupt enable
//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt
//! enable
//!
//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
//! \return None.
//
//*****************************************************************************
extern void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//*****************************************************************************
//
//! Gets the current UART interrupt status.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param mask is the masked interrupt flag status to be returned.
//! Mask value is the logical OR of any of the following:
//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG
//!
//!
//! \return The current interrupt status as an ORed bit mask:
//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
//
//*****************************************************************************
extern uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance,
uint8_t mask);
//*****************************************************************************
//
//! Gets the current UART interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list of pending
//! interrupts that are actually enabled and could have caused
//! the ISR.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//!
//! \return The current interrupt status as an ORed bit mask:
//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
//
//*****************************************************************************
extern uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance);
//*****************************************************************************
//
//! Clears UART interrupt sources.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
//! \param mask is a bit mask of the interrupt sources to be cleared.
//!
//! The UART interrupt source is cleared, so that it no longer asserts.
//! The highest interrupt flag is automatically cleared when an interrupt vector
//! generator is used.
//!
//! The mask parameter has the same definition as the mask parameter to
//! EUSCI_A_UART_enableInterrupt().
//!
//! Modified register is \b UCAxIFG
//!
//! \return None.
//
//*****************************************************************************
extern void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
//*****************************************************************************
//
//! Registers an interrupt handler for UART interrupts.
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.
//!
//! \param intHandler is a pointer to the function to be called when the
//! timer capture compare interrupt occurs.
//!
//! This function registers the handler to be called when an UART
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific UART interrupts must be enabled
//! via UART_enableInterrupt(). It is the interrupt handler's responsibility to
//! clear the interrupt source via UART_clearInterruptFlag().
//!
//! \return None.
//
//*****************************************************************************
extern void UART_registerInterrupt(uint32_t moduleInstance,
void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the UART module
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.
//!
//! This function unregisters the handler to be called when timer
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void UART_unregisterInterrupt(uint32_t moduleInstance);
/* Backwards Compatibility Layer */
#define EUSCI_A_UART_transmitData UART_transmitData
#define EUSCI_A_UART_receiveData UART_receiveData
#define EUSCI_A_UART_enableInterrupt UART_enableInterrupt
#define EUSCI_A_UART_disableInterrupt UART_disableInterrupt
#define EUSCI_A_UART_getInterruptStatus UART_getInterruptStatus
#define EUSCI_A_UART_clearInterruptFlag UART_clearInterruptFlag
#define EUSCI_A_UART_enable UART_enableModule
#define EUSCI_A_UART_disable UART_disableModule
#define EUSCI_A_UART_queryStatusFlags UART_queryStatusFlags
#define EUSCI_A_UART_setDormant UART_setDormant
#define EUSCI_A_UART_resetDormant UART_resetDormant
#define EUSCI_A_UART_transmitAddress UART_transmitAddress
#define EUSCI_A_UART_transmitBreak UART_transmitBreak
#define EUSCI_A_UART_getReceiveBufferAddressForDMA UART_getReceiveBufferAddressForDMA
#define EUSCI_A_UART_getTransmitBufferAddressForDMA UART_getTransmitBufferAddressForDMA
#define EUSCI_A_UART_selectDeglitchTime UART_selectDeglitchTime
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif /* UART_H_ */

119
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
Unescape Escape View File

@ -0,0 +1,119 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/* Standard Includes */
#include <stdint.h>
/* DriverLib Includes */
#include <wdt_a.h>
#include <debug.h>
#include <interrupt.h>
void WDT_A_holdTimer(void)
{
//Set Hold bit
uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTHOLD);
WDT_A->rCTL.r = WDTPW + newWDTStatus;
}
void WDT_A_startTimer(void)
{
//Reset Hold bit
uint8_t newWDTStatus = (WDT_A->rCTL.r & ~(WDTHOLD));
WDT_A->rCTL.r = WDTPW + newWDTStatus;
}
void WDT_A_clearTimer(void)
{
//Set Counter Clear bit
uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTCNTCL);
WDT_A->rCTL.r = WDTPW + newWDTStatus;
}
void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
uint_fast8_t clockIterations)
{
WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD +
clockSelect + clockIterations;
}
void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
uint_fast8_t clockIterations)
{
WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL
+ clockSelect + clockIterations;
}
void WDT_A_setPasswordViolationReset(uint_fast8_t resetType)
{
SysCtl_setWDTPasswordViolationResetType(resetType);
}
void WDT_A_setTimeoutReset(uint_fast8_t resetType)
{
SysCtl_setWDTTimeoutResetType(resetType);
}
void WDT_A_registerInterrupt(void (*intHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
Interrupt_registerInterrupt(INT_WDT_A, intHandler);
//
// Enable the system control interrupt.
//
Interrupt_enableInterrupt (INT_WDT_A);
}
void WDT_A_unregisterInterrupt(void)
{
//
// Disable the interrupt.
//
Interrupt_disableInterrupt (INT_WDT_A);
//
// Unregister the interrupt handler.
//
Interrupt_unregisterInterrupt(INT_WDT_A);
}

296
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
Unescape Escape View File

@ -0,0 +1,296 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
//! \addtogroup wdt_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include <msp.h>
#include <stdint.h>
#include "sysctl.h"
#define WDT_A_HARD_RESET SYSCTL_HARD_RESET
#define WDT_A_SOFT_RESET SYSCTL_SOFT_RESET
//*****************************************************************************
//
// The following are values that can be passed to the clockSelect parameter for
// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
#define WDT_A_CLOCKSOURCE_SMCLK (WDTSSEL_0)
#define WDT_A_CLOCKSOURCE_ACLK (WDTSSEL_1)
#define WDT_A_CLOCKSOURCE_VLOCLK (WDTSSEL_2)
#define WDT_A_CLOCKSOURCE_XCLK (WDTSSEL_3)
//*****************************************************************************
//
// The following are values that can be passed to the clockDivider parameter
// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
#define WDT_A_CLOCKDIVIDER_2G (WDTIS_0)
#define WDT_A_CLOCKDIVIDER_128M (WDTIS_1)
#define WDT_A_CLOCKDIVIDER_8192K (WDTIS_2)
#define WDT_A_CLOCKDIVIDER_512K (WDTIS_3)
#define WDT_A_CLOCKDIVIDER_32K (WDTIS_4)
#define WDT_A_CLOCKDIVIDER_8192 (WDTIS_5)
#define WDT_A_CLOCKDIVIDER_512 (WDTIS_6)
#define WDT_A_CLOCKDIVIDER_64 (WDTIS_7)
#define WDT_A_CLOCKITERATIONS_2G WDT_A_CLOCKDIVIDER_2G
#define WDT_A_CLOCKITERATIONS_128M WDT_A_CLOCKDIVIDER_128M
#define WDT_A_CLOCKITERATIONS_8192K WDT_A_CLOCKDIVIDER_8192K
#define WDT_A_CLOCKITERATIONS_512K WDT_A_CLOCKDIVIDER_512K
#define WDT_A_CLOCKITERATIONS_32K WDT_A_CLOCKDIVIDER_32K
#define WDT_A_CLOCKITERATIONS_8192 WDT_A_CLOCKDIVIDER_8192
#define WDT_A_CLOCKITERATIONS_512 WDT_A_CLOCKDIVIDER_512
#define WDT_A_CLOCKITERATIONS_64 WDT_A_CLOCKDIVIDER_64
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Holds the Watchdog Timer.
//!
//! This function stops the watchdog timer from running. This way no interrupt
//! or PUC is asserted.
//!
//! \return None
//
//*****************************************************************************
extern void WDT_A_holdTimer(void);
//*****************************************************************************
//
//! Starts the Watchdog Timer.
//!
//! This function starts the watchdog timer functionality to start counting.
//!
//! \return None
//
//*****************************************************************************
extern void WDT_A_startTimer(void);
//*****************************************************************************
//
//! Clears the timer counter of the Watchdog Timer.
//!
//! This function clears the watchdog timer count to 0x0000h. This function
//! is used to "service the dog" when operating in watchdog mode.
//!
//! \return None
//
//*****************************************************************************
extern void WDT_A_clearTimer(void);
//*****************************************************************************
//
//! Sets the clock source for the Watchdog Timer in watchdog mode.
//!
//! \param clockSelect is the clock source that the watchdog timer will use.
//! Valid values are
//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
//! - \b WDT_A_CLOCKSOURCE_ACLK
//! - \b WDT_A_CLOCKSOURCE_VLOCLK
//! - \b WDT_A_CLOCKSOURCE_XCLK
//! \param clockIterations is the number of clock iterations for a watchdog
//! timeout.
//! Valid values are
//! - \b WDT_A_CLOCKITERATIONS_2G [Default]
//! - \b WDT_A_CLOCKITERATIONS_128M
//! - \b WDT_A_CLOCKITERATIONS_8192K
//! - \b WDT_A_CLOCKITERATIONS_512K
//! - \b WDT_A_CLOCKITERATIONS_32K
//! - \b WDT_A_CLOCKITERATIONS_8192
//! - \b WDT_A_CLOCKITERATIONS_512
//! - \b WDT_A_CLOCKITERATIONS_64
//!
//! This function sets the watchdog timer in watchdog mode, which will cause a
//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a
//! call to WDT_A_resetTimer() before the timer runs out.
//!
//! \return None
//
//*****************************************************************************
extern void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
uint_fast8_t clockDivider);
//*****************************************************************************
//
//! Sets the clock source for the Watchdog Timer in timer interval mode.
//!
//! \param clockSelect is the clock source that the watchdog timer will use.
//! Valid values are
//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
//! - \b WDT_A_CLOCKSOURCE_ACLK
//! - \b WDT_A_CLOCKSOURCE_VLOCLK
//! - \b WDT_A_CLOCKSOURCE_XCLK
//! \param clockIterations is the number of clock iterations for a watchdog
//! interval.
//! Valid values are
//! - \b WDT_A_CLOCKITERATIONS_2G [Default]
//! - \b WDT_A_CLOCKITERATIONS_128M
//! - \b WDT_A_CLOCKITERATIONS_8192K
//! - \b WDT_A_CLOCKITERATIONS_512K
//! - \b WDT_A_CLOCKITERATIONS_32K
//! - \b WDT_A_CLOCKITERATIONS_8192
//! - \b WDT_A_CLOCKITERATIONS_512
//! - \b WDT_A_CLOCKITERATIONS_64
//!
//! This function sets the watchdog timer as timer interval mode, which will
//! assert an interrupt without causing a PUC.
//!
//! \return None
//
//*****************************************************************************
extern void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
uint_fast8_t clockDivider);
//*****************************************************************************
//
//! Registers an interrupt handler for the watchdog interrupt.
//!
//! \param intHandler is a pointer to the function to be called when the
//! watchdog interrupt occurs.
//!
//! \return None.
//
//*****************************************************************************
extern void WDT_A_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
//
//! Unregisters the interrupt handler for the watchdog.
//!
//! This function unregisters the handler to be called when a watchdog
//! interrupt occurs. This function also masks off the interrupt in the
//! interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa Interrupt_registerInterrupt() for important information about
//! registering interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
extern void WDT_A_unregisterInterrupt(void);
//*****************************************************************************
//
//! Sets the type of RESET that happens when a watchdog password violation
//! occurs.
//!
//! \param resetType The type of reset to set
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b WDT_A_HARD_RESET
//! - \b WDT_A_SOFT_RESET
//!
//! \return None.
//
//
//*****************************************************************************
extern void WDT_A_setPasswordViolationReset(uint_fast8_t resetType);
//*****************************************************************************
//
//! Sets the type of RESET that happens when a watchdog timeout occurs.
//!
//! \param resetType The type of reset to set
//!
//! The \e resetType parameter must be only one of the following values:
//! - \b WDT_A_HARD_RESET
//! - \b WDT_A_SOFT_RESET
//!
//! \return None.
//
//
//*****************************************************************************
extern void WDT_A_setTimeoutReset(uint_fast8_t resetType);
/* Defines for future devices that might have multiple instances */
#define WDT_A_holdTimerMultipleTimer(a) WDT_A_holdTimer()
#define WDT_A_startTimerMultipleTimer(a) WDT_A_startTimer()
#define WDT_A_resetTimerMultipleTimer(a) WDT_A_resetTimer()
#define WDT_A_initWatchdogTimerMultipleTimer(a,b,c) WDT_A_initWatchdogTimer(b,c)
#define WDT_A_initIntervalTimerMultipleTimer(a,b,c) WDT_A_initIntervalTimer(b,c)
#define WDT_A_registerInterruptMultipleTimer(a,b) WDT_A_registerInterrupt(b)
#define WDT_A_unregisterInterruptMultipleTimer(a) WDT_A_unregisterInterrupt()
/* Backwards compatibility layer */
#define WDT_A_hold WDT_A_holdTimerMultipleTimer
#define WDT_A_start WDT_A_startTimerMultipleTimer
#define WDT_A_resetTimer WDT_A_resetTimerMultipleTimer
#define WDT_A_watchdogTimerInit WDT_A_initWatchdogTimerMultipleTimer
#define WDT_A_intervalTimerInit WDT_A_initIntervalTimerMultipleTimer
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __WATCHDOG_H__

212
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
Unescape Escape View File

@ -0,0 +1,212 @@
/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* configCREATE_SIMPLE_TICKLESS_DEMO setting (defined in FreeRTOSConfig.h) is
* used to select between the two. The simply blinky demo is implemented and
* described in main_blinky.c. The more comprehensive test and demo application
* is implemented and described in main_full.c.
*
* The comprehensive demo uses FreeRTOS+CLI to create a simple command line
* interface through a UART.
*
* The blinky demo uses FreeRTOS's tickless idle mode to reduce power
* consumption. See the notes on the web page below regarding the difference
* in power saving that can be achieved between using the generic tickless
* implementation (as used by the blinky demo) and a tickless implementation
* that is tailored specifically to the MSP432.
*
* This file implements the code that is not demo specific.
*
* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions.
*
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/*-----------------------------------------------------------*/
/*
* Set up the hardware ready to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 1.
* main_full() is used when configCREATE_SIMPLE_TICKLESS_DEMO is set to 0.
*/
extern void main_blinky( void );
extern void main_full( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* See http://www.FreeRTOS.org/TI_MSP432_Free_RTOS_Demo.html for instructions. */
/* Prepare the hardware to run this demo. */
prvSetupHardware();
/* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top
of this file. */
#if configCREATE_SIMPLE_TICKLESS_DEMO == 1
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
extern void FPU_enableModule( void );
/* The clocks are not configured here, but inside main_full() and
main_blinky() as the full demo uses a fast clock and the blinky demo uses
a slow clock. */
/* Stop the watchdog timer. */
MAP_WDT_A_holdTimer();
/* Ensure the FPU is enabled. */
FPU_enableModule();
/* Selecting P1.2 and P1.3 in UART mode and P1.0 as output (LED) */
MAP_GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_P1, GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION );
MAP_GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 );
MAP_GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void *malloc( size_t xSize )
{
/* There should not be a heap defined, so trap any attempts to call
malloc. */
Interrupt_disableMaster();
for( ;; );
}
/*-----------------------------------------------------------*/

18
FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo.Debug.cspy.bat → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.Debug.cspy.bat
Unescape Escape View File

@ -19,6 +19,22 @@
@REM
"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll" %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --device_macro "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\ST\STM32F4xx.dmac" --flash_loader "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F7xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M7" "--fpu=VFPv5_sp" "-p" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\CONFIG\debugger\ST\STM32F7xxx.ddf" "--drv_verify_download" "--semihosting=none" "--device=STM32F7xxx" "--drv_communication=USB0" "--drv_interface_speed=auto" "--jlink_initial_speed=1000" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=0,0,2000000"
@echo off
if not "%1" == "" goto debugFile
@echo on
"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.driver.xcl"
@echo off
goto end
:debugFile
@echo on
"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil\settings\RTOSDemo.Debug.driver.xcl"
@echo off
:end

0
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.crun → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.crun
Unescape Escape View File

87
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
Unescape Escape View File

@ -0,0 +1,87 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Debug-Log>
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>
<Build>
<ColumnWidth0>20</ColumnWidth0>
<ColumnWidth1>1216</ColumnWidth1>
<ColumnWidth2>324</ColumnWidth2>
<ColumnWidth3>81</ColumnWidth3>
</Build>
<Workspace>
<ColumnWidths>
<Column0>233</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<col-names>
<item>Disassembly</item><item>_I0</item></col-names>
<col-widths>
<item>500</item><item>20</item></col-widths>
<DisasmHistory><item>0</item></DisasmHistory>
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>
<Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register></Static>
<Windows>
<Wnd1>
<Tabs>
<Tab>
<Identity>TabID-24437-20285</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-23914-20295</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd1><Wnd4>
<Tabs>
<Tab>
<Identity>TabID-2417-20288</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Full_Demo</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-18267-27197</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>128</YPos2><SelStart2>5940</SelStart2><SelEnd2>5940</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-00359FA0><key>iaridepm.enu1</key></Toolbar-00359FA0></Sizes></Row0><Row1><Sizes><Toolbar-0D2EC0B0><key>debuggergui.enu1</key></Toolbar-0D2EC0B0></Sizes></Row1><Row2><Sizes><Toolbar-0D2DBAF8><key>armjet.enu1</key></Toolbar-0D2DBAF8></Sizes></Row2></Top><Left><Row0><Sizes><Wnd4><Rect><Top>-2</Top><Left>-2</Left><Bottom>585</Bottom><Right>307</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>183929</sizeVertCX><sizeVertCY>596545</sizeVertCY></Rect></Wnd4></Sizes></Row0></Left><Right><Row0><Sizes><Wnd5><Rect><Top>-2</Top><Left>-2</Left><Bottom>585</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>596545</sizeVertCY></Rect></Wnd5></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>307</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>309</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>314024</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

146
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
Unescape Escape View File

@ -0,0 +1,146 @@
[Stack]
FillEnabled=0
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnLogOnly=1
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[PlDriver]
MemConfigValue=
FirstRun=0
[PlCacheRanges]
CustomRanges0=0 0 536870912 1 0
CustomRangesText0=Code
CustomRanges1=0 536870912 33554432 0 0
CustomRangesText1=SRAM
CustomRanges2=0 570425344 33554432 0 0
CustomRangesText2=bit-banding
CustomRanges3=0 1073741824 33554432 2 0
CustomRangesText3=Peripheral
CustomRanges4=0 1107296256 33554432 2 0
CustomRangesText4=bit-banding
CustomRanges5=0 3758096384 536870912 2 0
CustomRangesText5=Private peripheral
[Jet]
JetConnSerialNo=73866
JetConnFoundProbes=
DisableInterrupts=0
MultiCoreRunAll=0
OnlineReset=Software
PrevWtdReset=System
[DebugChecksum]
Checksum=701872400
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0
[CallStack]
ShowArgs=0
[Disassembly]
MixedMode=1
[SWOManager]
SamplingDivider=8192
OverrideClock=0
CpuClock=696008061
SwoClock=560889384
DataLogMode=0
ItmPortsEnabled=63
ItmTermIOPorts=1
ItmLogPorts=0
ItmLogFile=$PROJ_DIR$\ITM.log
PowerForcePC=1
PowerConnectPC=1
[ArmDriver]
EnableCache=1
[JLinkDriver]
CStepIntDis=_ 0
[CodeCoverage]
Enabled=_ 0
[SWOTraceHWSettings]
OverrideDefaultClocks=0
CpuClock=12000000
ClockAutoDetect=1
ClockWanted=7500000
JtagSpeed=6000000
Prescaler=2
TimeStampPrescIndex=0
TimeStampPrescData=0
PcSampCYCTAP=1
PcSampPOSTCNT=15
PcSampIndex=0
DataLogMode=0
ITMportsEnable=0
ITMportsTermIO=0
ITMportsLogFile=0
ITMlogFile=$PROJ_DIR$\ITM.log
[Breakpoints]
Count=0
[Trace2]
Enabled=0
ShowSource=0
[SWOTraceWindow]
ForcedPcSampling=0
ForcedInterruptLogs=0
ForcedItmLogs=0
EventCPI=0
EventEXC=0
EventFOLD=0
EventLSU=0
EventSLEEP=0
[PowerLog]
LogEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=0
Title_0=I0
Symbol_0=0 4 1
LiveEnabled=0
LiveFile=PowerLogLive.log
[DataLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
[EventLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
SumSortOrder=0
[InterruptLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
SumSortOrder=0
[CallStackLog]
Enabled=0
[DriverProfiling]
Enabled=0
Mode=3
Graph=0
Symbiont=0
Exclusions=
[PowerProbe]
Frequency=10000
Probe0=I0
ProbeSetup0=2 1 1 2 0 0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Disassemble mode]
mode=0
[Breakpoints2]
Count=0
[Aliases]
Count=0
SuppressDialog=0

66
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
Unescape Escape View File

@ -0,0 +1,66 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>RTOSDemo/IAR_Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>307</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build>
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>
<Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log><TerminalIO/><Find-in-Files><ColumnWidth0>497</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>746</ColumnWidth2><ColumnWidth3>331</ColumnWidth3></Find-in-Files><Select-Ambiguous-Definitions><ColumnWidth0>664</ColumnWidth0><ColumnWidth1>94</ColumnWidth1><ColumnWidth2>1138</ColumnWidth2></Select-Ambiguous-Definitions><Find-All-Declarations><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-All-Declarations></Static>
<Windows>
<Wnd1>
<Tabs>
<Tab>
<Identity>TabID-2476-27879</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd1><Wnd3>
<Tabs>
<Tab>
<Identity>TabID-28448-28006</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
<Tab><Identity>TabID-6453-17552</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-23164-8214</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-26948-371</Identity><TabName>Ambiguous Definitions</TabName><Factory>Select-Ambiguous-Definitions</Factory><Session/></Tab><Tab><Identity>TabID-26862-26832</Identity><TabName>Declarations</TabName><Factory>Find-All-Declarations</Factory><Session/></Tab></Tabs>
<SelectedTab>0</SelectedTab></Wnd3></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>61</YPos2><SelStart2>5940</SelStart2><SelEnd2>5940</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-010D90F0><key>iaridepm.enu1</key></Toolbar-010D90F0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>587</Bottom><Right>381</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>227976</sizeVertCX><sizeVertCY>598577</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>353</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>355</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>360772</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

0
FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/settings/RTOSDemo.wspos → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
Unescape Escape View File

0
FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL/settings/RTOSDemo_Debug.jlink → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo_Debug.jlink
Unescape Escape View File

13
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/MSP432P401R.ccxml
Unescape Escape View File

@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="MSP432P401R" href="devices/msp432p401r.xml" id="MSP432P401R" xml="msp432p401r.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>

206
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
Unescape Escape View File

@ -0,0 +1,206 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family Interrupt Vector Table for CGT
//
//****************************************************************************
#include <stdint.h>
#include <driverlib.h>
/* Forward declaration of the default fault handlers. */
static void resetISR(void);
static void nmiISR(void);
static void faultISR(void);
static void defaultISR(void);
/* External declaration for the reset handler that is to be called when the */
/* processor is started */
extern void _c_int00(void);
/* Linker variable that marks the top of the stack. */
extern unsigned long __STACK_END;
/* External declarations for the FreeRTOS interrupt handlers. */
extern void xPortSysTickHandler( void );
extern void vPortSVCHandler( void );
extern void xPortPendSVHandler( void );
/* External declarations for the peripheral interrupts handlers used by the
demo application. */
extern void vUART_Handler( void );
extern void vT32_0_Handler( void );
extern void vT32_1_Handler( void );
/* Intrrupt vector table. Note that the proper constructs must be placed on this to */
/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
/* the program if located at a start address other than 0. */
#pragma DATA_SECTION(interruptVectors, ".intvecs")
void (* const interruptVectors[])(void) =
{
(void (*)(void))((uint32_t)&__STACK_END),
/* The initial stack pointer */
resetISR, /* The reset handler */
nmiISR, /* The NMI handler */
faultISR, /* The hard fault handler */
defaultISR, /* The MPU fault handler */
defaultISR, /* The bus fault handler */
defaultISR, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
vPortSVCHandler, /* SVCall handler */
defaultISR, /* Debug monitor handler */
0, /* Reserved */
xPortPendSVHandler, /* The PendSV handler */
xPortSysTickHandler, /* The SysTick handler */
defaultISR, /* PSS ISR */
defaultISR, /* CS ISR */
defaultISR, /* PCM ISR */
defaultISR, /* WDT ISR */
defaultISR, /* FPU ISR */
defaultISR, /* FLCTL ISR */
defaultISR, /* COMP0 ISR */
defaultISR, /* COMP1 ISR */
defaultISR, /* TA0_0 ISR */
defaultISR, /* TA0_N ISR */
defaultISR, /* TA1_0 ISR */
defaultISR, /* TA1_N ISR */
defaultISR, /* TA2_0 ISR */
defaultISR, /* TA2_N ISR */
defaultISR, /* TA3_0 ISR */
defaultISR, /* TA3_N ISR */
vUART_Handler, /* EUSCIA0 ISR */
defaultISR, /* EUSCIA1 ISR */
defaultISR, /* EUSCIA2 ISR */
defaultISR, /* EUSCIA3 ISR */
defaultISR, /* EUSCIB0 ISR */
defaultISR, /* EUSCIB1 ISR */
defaultISR, /* EUSCIB2 ISR */
defaultISR, /* EUSCIB3 ISR */
defaultISR, /* ADC14 ISR */
vT32_0_Handler, /* T32_INT1 ISR */
vT32_1_Handler, /* T32_INT2 ISR */
defaultISR, /* T32_INTC ISR */
defaultISR, /* AES ISR */
defaultISR, /* RTC ISR */
defaultISR, /* DMA_ERR ISR */
defaultISR, /* DMA_INT3 ISR */
defaultISR, /* DMA_INT2 ISR */
defaultISR, /* DMA_INT1 ISR */
defaultISR, /* DMA_INT0 ISR */
defaultISR, /* PORT1 ISR */
defaultISR, /* PORT2 ISR */
defaultISR, /* PORT3 ISR */
defaultISR, /* PORT4 ISR */
defaultISR, /* PORT5 ISR */
defaultISR, /* PORT6 ISR */
defaultISR, /* Reserved 41 */
defaultISR, /* Reserved 42 */
defaultISR, /* Reserved 43 */
defaultISR, /* Reserved 44 */
defaultISR, /* Reserved 45 */
defaultISR, /* Reserved 46 */
defaultISR, /* Reserved 47 */
defaultISR, /* Reserved 48 */
defaultISR, /* Reserved 49 */
defaultISR, /* Reserved 50 */
defaultISR, /* Reserved 51 */
defaultISR, /* Reserved 52 */
defaultISR, /* Reserved 53 */
defaultISR, /* Reserved 54 */
defaultISR, /* Reserved 55 */
defaultISR, /* Reserved 56 */
defaultISR, /* Reserved 57 */
defaultISR, /* Reserved 58 */
defaultISR, /* Reserved 59 */
defaultISR, /* Reserved 60 */
defaultISR, /* Reserved 61 */
defaultISR, /* Reserved 62 */
defaultISR, /* Reserved 63 */
defaultISR /* Reserved 64 */
};
/* This is the code that gets called when the processor first starts execution */
/* following a reset event. Only the absolutely necessary set is performed, */
/* after which the application supplied entry() routine is called. Any fancy */
/* actions (such as making decisions based on the reset cause register, and */
/* resetting the bits in that register) are left solely in the hands of the */
/* application. */
void resetISR(void)
{
/* Jump to the CCS C Initialization Routine. */
MAP_WDT_A_holdTimer();
__asm(" .global _c_int00\n"
" b.w _c_int00");
}
/* This is the code that gets called when the processor receives a NMI. This */
/* simply enters an infinite loop, preserving the system state for examination */
/* by a debugger. */
static void nmiISR(void)
{
/* Enter an infinite loop. */
while(1)
{
}
}
/* This is the code that gets called when the processor receives a fault */
/* interrupt. This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger. */
static void faultISR(void)
{
/* Enter an infinite loop. */
while(1)
{
}
}
/* This is the code that gets called when the processor receives an unexpected */
/* interrupt. This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger. */
static void defaultISR(void)
{
/* Enter an infinite loop. */
while(1)
{
}
}

84
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432p401r.cmd
Unescape Escape View File

@ -0,0 +1,84 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Default linker command file for Texas Instruments MSP432P401R
*
* File creation date: 2015-01-20
*
*****************************************************************************/
--retain=interruptVectors
--retain=flashMailbox
MEMORY
{
MAIN (RX) : origin = 0x00000000, length = 0x00040000
INFO (RX) : origin = 0x00200000, length = 0x00004000
SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
}
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* A heap size of 1024 bytes is recommended when you plan to use printf() */
/* for debug output to the console window. */
/* */
/* --heap_size=1024 */
/* --stack_size=512 */
/* --library=rtsv7M4_T_le_eabi.lib */
/* Section allocation in memory */
SECTIONS
{
.intvecs: > 0x00000000
.text : > MAIN
.const : > MAIN
.cinit : > MAIN
.pinit : > MAIN
.flashMailbox : > 0x00200000
.vtable : > 0x20000000
.data : > SRAM_DATA
.bss : > SRAM_DATA
.sysmem : > SRAM_DATA
.stack : > SRAM_DATA (HIGH)
}
/* Symbolic definition of the WDTCTL register for RTS */
WDTCTL_SYM = 0x4000480C;

312
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/printf-stdarg.c
Unescape Escape View File

@ -0,0 +1,312 @@
/*
Copyright 2001, 2002 Georges Menie (www.menie.org)
stdarg version contributed by Christian Ettinger
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
putchar is the only external dependency for this file,
if you have a working putchar, leave it commented out.
If not, uncomment the define below and
replace outbyte(c) by your own function call.
*/
#define putchar(c) c
#include <stdarg.h>
static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen );
static void printchar(char **str, int c, char *buflimit)
{
//extern int putchar(int c);
if (str) {
if( buflimit == ( char * ) 0 ) {
/* Limit of buffer not known, write charater to buffer. */
**str = (char)c;
++(*str);
}
else if( ( ( unsigned long ) *str ) < ( ( unsigned long ) buflimit ) ) {
/* Withing known limit of buffer, write character. */
**str = (char)c;
++(*str);
}
}
else
{
(void)putchar(c);
}
}
#define PAD_RIGHT 1
#define PAD_ZERO 2
static int prints(char **out, const char *string, int width, int pad, char *buflimit)
{
register int pc = 0, padchar = ' ';
if (width > 0) {
register int len = 0;
register const char *ptr;
for (ptr = string; *ptr; ++ptr) ++len;
if (len >= width) width = 0;
else width -= len;
if (pad & PAD_ZERO) padchar = '0';
}
if (!(pad & PAD_RIGHT)) {
for ( ; width > 0; --width) {
printchar (out, padchar, buflimit);
++pc;
}
}
for ( ; *string ; ++string) {
printchar (out, *string, buflimit);
++pc;
}
for ( ; width > 0; --width) {
printchar (out, padchar, buflimit);
++pc;
}
return pc;
}
/* the following should be enough for 32 bit int */
#define PRINT_BUF_LEN 12
static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase, char *buflimit)
{
char print_buf[PRINT_BUF_LEN];
register char *s;
register int t, neg = 0, pc = 0;
register unsigned int u = (unsigned int)i;
if (i == 0) {
print_buf[0] = '0';
print_buf[1] = '\0';
return prints (out, print_buf, width, pad, buflimit);
}
if (sg && b == 10 && i < 0) {
neg = 1;
u = (unsigned int)-i;
}
s = print_buf + PRINT_BUF_LEN-1;
*s = '\0';
while (u) {
t = (unsigned int)u % b;
if( t >= 10 )
t += letbase - '0' - 10;
*--s = (char)(t + '0');
u /= b;
}
if (neg) {
if( width && (pad & PAD_ZERO) ) {
printchar (out, '-', buflimit);
++pc;
--width;
}
else {
*--s = '-';
}
}
return pc + prints (out, s, width, pad, buflimit);
}
static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen )
{
register int width, pad;
register int pc = 0;
char scr[2], *buflimit;
if( buflen == 0 ){
buflimit = ( char * ) 0;
}
else {
/* Calculate the last valid buffer space, leaving space for the NULL
terminator. */
buflimit = ( *out ) + ( buflen - 1 );
}
for (; *format != 0; ++format) {
if (*format == '%') {
++format;
width = pad = 0;
if (*format == '\0') break;
if (*format == '%') goto out;
if (*format == '-') {
++format;
pad = PAD_RIGHT;
}
while (*format == '0') {
++format;
pad |= PAD_ZERO;
}
for ( ; *format >= '0' && *format <= '9'; ++format) {
width *= 10;
width += *format - '0';
}
if( *format == 's' ) {
register char *s = (char *)va_arg( args, int );
pc += prints (out, s?s:"(null)", width, pad, buflimit);
continue;
}
if( *format == 'd' ) {
pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a', buflimit);
continue;
}
if( *format == 'x' ) {
pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a', buflimit);
continue;
}
if( *format == 'X' ) {
pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A', buflimit);
continue;
}
if( *format == 'u' ) {
pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a', buflimit);
continue;
}
if( *format == 'c' ) {
/* char are converted to int then pushed on the stack */
scr[0] = (char)va_arg( args, int );
scr[1] = '\0';
pc += prints (out, scr, width, pad, buflimit);
continue;
}
}
else {
out:
printchar (out, *format, buflimit);
++pc;
}
}
if (out) **out = '\0';
va_end( args );
return pc;
}
int printf(const char *format, ...)
{
va_list args;
va_start( args, format );
return tiny_print( 0, format, args, 0 );
}
int sprintf(char *out, const char *format, ...)
{
va_list args;
va_start( args, format );
return tiny_print( &out, format, args, 0 );
}
int snprintf( char *buf, unsigned int count, const char *format, ... )
{
va_list args;
( void ) count;
va_start( args, format );
return tiny_print( &buf, format, args, count );
}
#ifdef TEST_PRINTF
int main(void)
{
char *ptr = "Hello world!";
char *np = 0;
int i = 5;
unsigned int bs = sizeof(int)*8;
int mi;
char buf[80];
mi = (1 << (bs-1)) + 1;
printf("%s\n", ptr);
printf("printf test\n");
printf("%s is null pointer\n", np);
printf("%d = 5\n", i);
printf("%d = - max int\n", mi);
printf("char %c = 'a'\n", 'a');
printf("hex %x = ff\n", 0xff);
printf("hex %02x = 00\n", 0);
printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
printf("%d %s(s)%", 0, "message");
printf("\n");
printf("%d %s(s) with %%\n", 0, "message");
sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
return 0;
}
/*
* if you compile this file with
* gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
* you will get a normal warning:
* printf.c:214: warning: spurious trailing `%' in format
* this line is testing an invalid % at the end of the format string.
*
* this should display (on 32bit int machine) :
*
* Hello world!
* printf test
* (null) is null pointer
* 5 = 5
* -2147483647 = - max int
* char a = 'a'
* hex ff = ff
* hex 00 = 00
* signed -3 = unsigned 4294967293 = hex fffffffd
* 0 message(s)
* 0 message(s) with %
* justif: "left "
* justif: " right"
* 3: 0003 zero padded
* 3: 3 left justif.
* 3: 3 right justif.
* -3: -003 zero padded
* -3: -3 left justif.
* -3: -3 right justif.
*/
#endif
/* To keep linker happy. */
int write( int i, char* c, int n)
{
(void)i;
(void)n;
(void)c;
return 0;
}

Some files were not shown because too many files have changed in this diff Show More

Write Preview
Loading…
Cancel
Save