From 881305dcb813c93bd71e0ec2d3374cc741dec2bd Mon Sep 17 00:00:00 2001 From: Jonathan Cubides <92931721+cubidesj@users.noreply.github.com> Date: Mon, 10 Mar 2025 12:36:13 +0100 Subject: [PATCH] Update RV32 qemu Demo to support RVA23 (#1329) * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Increase the memory for RVA23 compilation * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Update the regtest to include fpu registers * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Fix small issues for 64-bit configs * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Enable FPU unit * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Enable compilation for RVA23 platforms * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Fix copyright related CI issues * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Update submodule manifest * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Update a few typos and left overs * Demo: RISC-V_RV32_QEMU_VIRT_GCC: Apply @aggarg's sugestions * Update pointer to Freertos-Kernel --- .../FreeRTOSConfig.h | 5 + .../Demo/RISC-V_RV32_QEMU_VIRT_GCC/Readme.md | 37 +- .../build/gcc/Makefile | 36 +- .../build/gcc/RegTest.S | 408 +++++++++++++++++- .../build/gcc/fake_rom.ld | 2 +- .../build/gcc/printf-stdarg.c | 12 +- .../build/gcc/start.S | 8 +- .../Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c | 2 +- .../RISC-V_RV32_QEMU_VIRT_GCC/main_full.c | 4 + FreeRTOS/Source | 2 +- manifest.yml | 2 +- 11 files changed, 480 insertions(+), 38 deletions(-) diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h index 21a2938648..5b2201ddc7 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/FreeRTOSConfig.h @@ -51,8 +51,13 @@ #define configUSE_TICK_HOOK 1 #define configCPU_CLOCK_HZ ( ( unsigned long ) 25000000 ) #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#if __riscv_xlen == 64 +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 240 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 220 * 1024 ) ) +#else #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 80 * 1024 ) ) +#endif #define configMAX_TASK_NAME_LEN ( 12 ) #define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/Readme.md b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/Readme.md index d613ed8dd8..045d60eaba 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/Readme.md +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/Readme.md @@ -2,11 +2,15 @@ ## Requirements -1. GNU RISC-V toolchains (tested on pre-built Sifive GNU Embedded Toolchain — v2020.12.8) - - https://www.sifive.com/software -1. qemu-riscv32-system (tested on pre-built Sifive QEMU — v2020.08.1) - - https://www.sifive.com/software -1. Linux OS (tested on Ubuntu 20.04.3 LTS) +1. GNU RISC-V toolchains Tested on: + * Pre-built Sifive GNU Embedded Toolchain — v3.0.4 - https://www.sifive.com/software + * Self built from https://github.com/riscv-collab/riscv-gnu-toolchain/tree/a33dac0251d17a7b74d99bd8fd401bfce87d2aed (tag: 2025.01.20) + +1. qemu-riscv64-system. Tested on: + * pre-built Sifive QEMU — v3.0.4 - https://www.sifive.com/software + * qemu-system-riscv64 v 8.2.2 +1. Linux OS. Tested on: + * Ubuntu 24.04 LTS ## How to build @@ -35,16 +39,31 @@ To clean build artifacts: $ make -C build/gcc/ clean ``` +For any of the previous configurations, if you want to use the port on a RVA23 system instead of a RV32, you may append append `RVA23=1` + +``` +$ make -C build/gcc/ RVA23=1 +``` + If the build was successful, the RTOSDemo.elf executable will be located in the build/gcc/output directory. ## How to run +For the RV32 build: + +``` +$ qemu-system-riscv32 -nographic -machine virt -net none -chardev stdio,id=con,mux=on \ + -serial chardev:con -mon chardev=con,mode=readline -bios none -smp 4 \ + -s --kernel build/gcc/output/RTOSDemo.elf +``` + +For the RVA23 build: + ``` -$ qemu-system-riscv32 -nographic -machine virt -net none \ - -chardev stdio,id=con,mux=on -serial chardev:con \ - -mon chardev=con,mode=readline -bios none \ - -smp 4 -kernel ./build/gcc/output/RTOSDemo.elf +$ qemu-system-riscv64 -nographic -machine virt -net none -chardev stdio,id=con,mux=on \ + -serial chardev:con -mon chardev=con,mode=readline -bios none -smp 4 \ + -s --kernel build/gcc/output/RTOSDemo.elf ``` diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile index 25dc920b6a..d23da92603 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/Makefile @@ -13,24 +13,39 @@ MAKE = make GCC_VERSION = $(shell $(CC) --version | grep ^$(CC) | sed 's/^.* //g' | awk -F. '{ printf("%d%02d%02d"), $$1, $$2, $$3 }') GCC_VERSION_NEED_ZICSR = "110100" +ifeq ($(RVA23),1) + # For the time being, we don't include the vector extensions. + MARCH = rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa_zicclsm_za64rs_zihintpause_zic64b_zicbom_zicbop_zicboz_zfhmin_zkt_zihintntl_zawrs + MABI = lp64d + MCMODEL = medany + CFLAGS+=-DconfigENABLE_FPU=1 + $(info Using RVA23 build) +else + ifeq ($(shell test $(GCC_VERSION) -ge $(GCC_VERSION_NEED_ZICSR) && echo true),true) + MARCH=rv32imac_zicsr + else + MARCH=rv32imac + endif + MABI=ilp32 + MCMODEL=medlow + $(info Using RV32 build) +endif + +INCLUDE_DIRS += -I$(KERNEL_PORT_DIR)/chip_specific_extensions/RV32I_CLINT_no_extensions + CFLAGS += $(INCLUDE_DIRS) -fmessage-length=0 \ - -mabi=ilp32 -mcmodel=medlow -ffunction-sections -fdata-sections \ + -march=$(MARCH) -mabi=$(MABI) -mcmodel=$(MCMODEL) -ffunction-sections -fdata-sections \ -Wno-unused-parameter -nostartfiles -g3 -Os -ifeq ($(shell test $(GCC_VERSION) -ge $(GCC_VERSION_NEED_ZICSR) && echo true),true) - CFLAGS += -march=rv32imac_zicsr -else - CFLAGS += -march=rv32imac -endif - + ifeq ($(PICOLIBC),1) -CFLAGS += --specs=picolibc.specs -DPICOLIBC_INTEGER_PRINTF_SCANF +CFLAGS += --specs=picolibc.specs -DPICOLIBC_INTEGER_PRINTF_SCANF else CFLAGS += --specs=nano.specs -fno-builtin-printf endif LDFLAGS += -nostartfiles -Xlinker --gc-sections -Wl,-Map,$(OUTPUT_DIR)/RTOSDemo.map \ - -T./fake_rom.ld -march=rv32imac -mabi=ilp32 -mcmodel=medlow -Xlinker \ + -T./fake_rom.ld -march=$(MARCH) -mabi=$(MABI) -mcmodel=$(MCMODEL) -Xlinker \ --defsym=__stack_size=350 -Wl,--start-group -Wl,--end-group ifeq ($(PICOLIBC),1) @@ -54,8 +69,7 @@ endif KERNEL_DIR = $(FREERTOS_ROOT)/Source KERNEL_PORT_DIR += $(KERNEL_DIR)/portable/GCC/RISC-V INCLUDE_DIRS += -I$(KERNEL_DIR)/include \ - -I$(KERNEL_PORT_DIR) \ - -I$(KERNEL_PORT_DIR)/chip_specific_extensions/RV32I_CLINT_no_extensions + -I$(KERNEL_PORT_DIR) VPATH += $(KERNEL_DIR) $(KERNEL_PORT_DIR) $(KERNEL_DIR)/portable/MemMang SOURCE_FILES += $(KERNEL_DIR)/tasks.c SOURCE_FILES += $(KERNEL_DIR)/list.c diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S index fff1e4f6f2..a740163b07 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -37,7 +37,7 @@ * main_full.c. */ -.align( 4 ) +.align( 8 ) vRegTest1Implementation: /* Fill the core registers with known values. */ @@ -69,6 +69,70 @@ vRegTest1Implementation: li x30, 0x1e li x31, 0x1f #endif +#if __riscv_flen == 64 + li x15, 0xC030000000000000 // -16 + fmv.d.x f0, x15 + li x15, 0xC02E000000000000 // -15 + fmv.d.x f1, x15 + li x15, 0xC02C000000000000 // -14 + fmv.d.x f2, x15 + li x15, 0xc02a000000000000 // -13 + fmv.d.x f3, x15 + li x15, 0xC028000000000000 // -12 + fmv.d.x f4, x15 + li x15, 0xC026000000000000 // -11 + fmv.d.x f5, x15 + li x15, 0xc024000000000000 // -10 + fmv.d.x f6, x15 + li x15, 0xc022000000000000 // -9 + fmv.d.x f7, x15 + li x15, 0xc020000000000000 // -8 + fmv.d.x f8, x15 + li x15, 0xc01c000000000000 // -7 + fmv.d.x f9, x15 + li x15, 0xc018000000000000 // -6 + fmv.d.x f10, x15 + li x15, 0xc014000000000000 // -5 + fmv.d.x f11, x15 + li x15, 0xc010000000000000 // -4 + fmv.d.x f12, x15 + li x15, 0xc008000000000000 // -3 + fmv.d.x f13, x15 + li x15, 0xc000000000000000 // -2 + fmv.d.x f14, x15 + li x15, 0xbff0000000000000 // -1 + fmv.d.x f15, x15 + li x15, 0 // 0 + fmv.d.x f16, x15 + li x15, 0x3ff0000000000000 // 1 + fmv.d.x f17, x15 + li x15, 0x4000000000000000 // 2 + fmv.d.x f18, x15 + li x15, 0x4008000000000000 // 3 + fmv.d.x f19, x15 + li x15, 0x4010000000000000 // 4 + fmv.d.x f20, x15 + li x15, 0x4014000000000000 // 5 + fmv.d.x f21, x15 + li x15, 0x4018000000000000 // 6 + fmv.d.x f22, x15 + li x15, 0x401c000000000000 // 7 + fmv.d.x f23, x15 + li x15, 0x4020000000000000 // 8 + fmv.d.x f24, x15 + li x15, 0x4022000000000000 // 9 + fmv.d.x f25, x15 + li x15, 0x4024000000000000 // 10 + fmv.d.x f26, x15 + li x15, 0x4026000000000000 // 11 + fmv.d.x f27, x15 + li x15, 0x4028000000000000 // 12 + fmv.d.x f28, x15 + li x15, 0x402a000000000000 // 13 + fmv.d.x f29, x15 + li x15, 0x402C000000000000 // 14 + fmv.d.x f30, x15 +#endif reg1_loop: @@ -129,12 +193,145 @@ reg1_loop: li x15, 0x1f bne x15, x31, reg1_error_loop #endif +#if __riscv_flen == 64 + li x15, 0xC030000000000000 // -16 + fmv.d.x f31, x15 + feq.d x15, f0, f31 + beqz x15, reg1_error_loop + li x15, 0xC02E000000000000 // -15 + fmv.d.x f31, x15 + feq.d x15, f1, f31 + beqz x15, reg1_error_loop + li x15, 0xC02C000000000000 // -14 + fmv.d.x f31, x15 + feq.d x15, f2, f31 + beqz x15, reg1_error_loop + li x15, 0xc02a000000000000 // -13 + fmv.d.x f31, x15 + feq.d x15, f3, f31 + beqz x15, reg1_error_loop + li x15, 0xC028000000000000 // -12 + fmv.d.x f31, x15 + feq.d x15, f4, f31 + beqz x15, reg1_error_loop + li x15, 0xC026000000000000 // -11 + fmv.d.x f31, x15 + feq.d x15, f5, f31 + beqz x15, reg1_error_loop + li x15, 0xc024000000000000 // -10 + fmv.d.x f31, x15 + feq.d x15, f6, f31 + beqz x15, reg1_error_loop + li x15, 0xc022000000000000 // -9 + fmv.d.x f31, x15 + feq.d x15, f7, f31 + beqz x15, reg1_error_loop + li x15, 0xc020000000000000 // -8 + fmv.d.x f31, x15 + feq.d x15, f8, f31 + beqz x15, reg1_error_loop + li x15, 0xc01c000000000000 // -7 + fmv.d.x f31, x15 + feq.d x15, f9, f31 + beqz x15, reg1_error_loop + li x15, 0xc018000000000000 // -6 + fmv.d.x f31, x15 + feq.d x15, f10, f31 + beqz x15, reg1_error_loop + li x15, 0xc014000000000000 // -5 + fmv.d.x f31, x15 + feq.d x15, f11, f31 + beqz x15, reg1_error_loop + li x15, 0xc010000000000000 // -4 + fmv.d.x f31, x15 + feq.d x15, f12, f31 + beqz x15, reg1_error_loop + li x15, 0xc008000000000000 // -3 + fmv.d.x f31, x15 + feq.d x15, f13, f31 + beqz x15, reg1_error_loop + li x15, 0xc000000000000000 // -2 + fmv.d.x f31, x15 + feq.d x15, f14, f31 + beqz x15, reg1_error_loop + li x15, 0xbff0000000000000 // -1 + fmv.d.x f31, x15 + feq.d x15, f15, f31 + beqz x15, reg1_error_loop + li x15, 0 // 0 + fmv.d.x f31, x15 + feq.d x15, f16, f31 + beqz x15, reg1_error_loop + li x15, 0x3ff0000000000000 // 1 + fmv.d.x f31, x15 + feq.d x15, f17, f31 + beqz x15, reg1_error_loop + li x15, 0x4000000000000000 // 2 + fmv.d.x f31, x15 + feq.d x15, f18, f31 + beqz x15, reg1_error_loop + li x15, 0x4008000000000000 // 3 + fmv.d.x f31, x15 + feq.d x15, f19, f31 + beqz x15, reg1_error_loop + li x15, 0x4010000000000000 // 4 + fmv.d.x f31, x15 + feq.d x15, f20, f31 + beqz x15, reg1_error_loop + li x15, 0x4014000000000000 // 5 + fmv.d.x f31, x15 + feq.d x15, f21, f31 + beqz x15, reg1_error_loop + li x15, 0x4018000000000000 // 6 + fmv.d.x f31, x15 + feq.d x15, f22, f31 + beqz x15, reg1_error_loop + li x15, 0x401c000000000000 // 7 + fmv.d.x f31, x15 + feq.d x15, f23, f31 + beqz x15, reg1_error_loop + li x15, 0x4020000000000000 // 8 + fmv.d.x f31, x15 + feq.d x15, f24, f31 + beqz x15, reg1_error_loop + li x15, 0x4022000000000000 // 9 + fmv.d.x f31, x15 + feq.d x15, f25, f31 + beqz x15, reg1_error_loop + li x15, 0x4024000000000000 // 10 + fmv.d.x f31, x15 + feq.d x15, f26, f31 + beqz x15, reg1_error_loop + li x15, 0x4026000000000000 // 11 + fmv.d.x f31, x15 + feq.d x15, f27, f31 + beqz x15, reg1_error_loop + li x15, 0x4028000000000000 // 12 + fmv.d.x f31, x15 + feq.d x15, f28, f31 + beqz x15, reg1_error_loop + li x15, 0x402a000000000000 // 13 + fmv.d.x f31, x15 + feq.d x15, f29, f31 + beqz x15, reg1_error_loop + li x15, 0x402C000000000000 // 14 + fmv.d.x f31, x15 + feq.d x15, f30, f31 + beqz x15, reg1_error_loop +#endif /* Everything passed, increment the loop counter. */ +#if __riscv_xlen == 64 + ld x15, ulRegTest1LoopCounterConst + ld x14, 0(x15) + addi x14, x14, 1 + sd x14, 0(x15) +#else lw x15, ulRegTest1LoopCounterConst lw x14, 0(x15) addi x14, x14, 1 sw x14, 0(x15) +#endif /* Restore clobbered register reading for next loop. */ li x14, 0xe @@ -149,12 +346,12 @@ reg1_error_loop: /* Busy loop which holds the task. */ jal reg1_error_loop -.align( 4 ) -ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter +.align( 8 ) +ulRegTest1LoopCounterConst: .dword ulRegTest1LoopCounter /*-----------------------------------------------------------*/ -.align( 4 ) +.align( 8 ) vRegTest2Implementation: /* Fill the core registers with known values. */ @@ -186,6 +383,70 @@ vRegTest2Implementation: li x30, 0x2e li x31, 0x2f #endif +#if __riscv_flen == 64 + li x5, 0x402E000000000000 // 15 + fmv.d.x f1, x5 + li x5, 0x402C000000000000 // 14 + fmv.d.x f2, x5 + li x5, 0x402a000000000000 // 13 + fmv.d.x f3, x5 + li x5, 0x4028000000000000 // 12 + fmv.d.x f4, x5 + li x5, 0x4026000000000000 // 11 + fmv.d.x f5, x5 + li x5, 0x4024000000000000 // 10 + fmv.d.x f6, x5 + li x5, 0x4022000000000000 // 9 + fmv.d.x f7, x5 + li x5, 0x4020000000000000 // 8 + fmv.d.x f8, x5 + li x5, 0x401c000000000000 // 7 + fmv.d.x f9, x5 + li x5, 0x4018000000000000 // 6 + fmv.d.x f10, x5 + li x5, 0x4014000000000000 // 5 + fmv.d.x f11, x5 + li x5, 0x4010000000000000 // 4 + fmv.d.x f12, x5 + li x5, 0x4008000000000000 // 3 + fmv.d.x f13, x5 + li x5, 0x4000000000000000 // 2 + fmv.d.x f14, x5 + li x5, 0x3ff0000000000000 // 1 + fmv.d.x f15, x5 + li x5, 0 // 0 + fmv.d.x f16, x5 + li x5, 0xbff0000000000000 // -1 + fmv.d.x f17, x5 + li x5, 0xc000000000000000 // -2 + fmv.d.x f18, x5 + li x5, 0xc008000000000000 // -3 + fmv.d.x f19, x5 + li x5, 0xc010000000000000 // -4 + fmv.d.x f20, x5 + li x5, 0xc014000000000000 // -5 + fmv.d.x f21, x5 + li x5, 0xc018000000000000 // -6 + fmv.d.x f22, x5 + li x5, 0xc01c000000000000 // -7 + fmv.d.x f23, x5 + li x5, 0xc020000000000000 // -8 + fmv.d.x f24, x5 + li x5, 0xc022000000000000 // -9 + fmv.d.x f25, x5 + li x5, 0xc024000000000000 // -10 + fmv.d.x f26, x5 + li x5, 0xC026000000000000 // -11 + fmv.d.x f27, x5 + li x5, 0xC028000000000000 // -12 + fmv.d.x f28, x5 + li x5, 0xC02A000000000000 // -13 + fmv.d.x f29, x5 + li x5, 0xC02C000000000000 // -14 + fmv.d.x f30, x5 + li x5, 0xC02E000000000000 // -15 + fmv.d.x f31, x5 +#endif Reg2_loop: @@ -246,12 +507,145 @@ Reg2_loop: li x5, 0x2f bne x5, x31, reg2_error_loop #endif +#if __riscv_flen == 64 + li x5, 0x402E000000000000 // 15 + fmv.d.x f0, x5 + feq.d x5, f1, f0 + beqz x5, reg2_error_loop + li x5, 0x402C000000000000 // 14 + fmv.d.x f0, x5 + feq.d x5, f2, f0 + beqz x5, reg2_error_loop + li x5, 0x402a000000000000 // 13 + fmv.d.x f0, x5 + feq.d x5, f3, f0 + beqz x5, reg2_error_loop + li x5, 0x4028000000000000 // 12 + fmv.d.x f0, x5 + feq.d x5, f4, f0 + beqz x5, reg2_error_loop + li x5, 0x4026000000000000 // 11 + fmv.d.x f0, x5 + feq.d x5, f5, f0 + beqz x5, reg2_error_loop + li x5, 0x4024000000000000 // 10 + fmv.d.x f0, x5 + feq.d x5, f6, f0 + beqz x5, reg2_error_loop + li x5, 0x4022000000000000 // 9 + fmv.d.x f0, x5 + feq.d x5, f7, f0 + beqz x5, reg2_error_loop + li x5, 0x4020000000000000 // 8 + fmv.d.x f0, x5 + feq.d x5, f8, f0 + beqz x5, reg2_error_loop + li x5, 0x401c000000000000 // 7 + fmv.d.x f0, x5 + feq.d x5, f9, f0 + beqz x5, reg2_error_loop + li x5, 0x4018000000000000 // 6 + fmv.d.x f0, x5 + feq.d x5, f10, f0 + beqz x5, reg2_error_loop + li x5, 0x4014000000000000 // 5 + fmv.d.x f0, x5 + feq.d x5, f11, f0 + beqz x5, reg2_error_loop + li x5, 0x4010000000000000 // 4 + fmv.d.x f0, x5 + feq.d x5, f12, f0 + beqz x5, reg2_error_loop + li x5, 0x4008000000000000 // 3 + fmv.d.x f0, x5 + feq.d x5, f13, f0 + beqz x5, reg2_error_loop + li x5, 0x4000000000000000 // 2 + fmv.d.x f0, x5 + feq.d x5, f14, f0 + beqz x5, reg2_error_loop + li x5, 0x3ff0000000000000 // 1 + fmv.d.x f0, x5 + feq.d x5, f15, f0 + beqz x5, reg2_error_loop + li x5, 0 // 0 + fmv.d.x f0, x5 + feq.d x5, f16, f0 + beqz x5, reg2_error_loop + li x5, 0xbff0000000000000 // -1 + fmv.d.x f0, x5 + feq.d x5, f17, f0 + beqz x5, reg2_error_loop + li x5, 0xc000000000000000 // -2 + fmv.d.x f0, x5 + feq.d x5, f18, f0 + beqz x5, reg2_error_loop + li x5, 0xc008000000000000 // -3 + fmv.d.x f0, x5 + feq.d x5, f19, f0 + beqz x5, reg2_error_loop + li x5, 0xc010000000000000 // -4 + fmv.d.x f0, x5 + feq.d x5, f20, f0 + beqz x5, reg2_error_loop + li x5, 0xc014000000000000 // -5 + fmv.d.x f0, x5 + feq.d x5, f21, f0 + beqz x5, reg2_error_loop + li x5, 0xc018000000000000 // -6 + fmv.d.x f0, x5 + feq.d x5, f22, f0 + beqz x5, reg2_error_loop + li x5, 0xc01c000000000000 // -7 + fmv.d.x f0, x5 + feq.d x5, f23, f0 + beqz x5, reg2_error_loop + li x5, 0xc020000000000000 // -8 + fmv.d.x f0, x5 + feq.d x5, f24, f0 + beqz x5, reg2_error_loop + li x5, 0xc022000000000000 // -9 + fmv.d.x f0, x5 + feq.d x5, f25, f0 + beqz x5, reg2_error_loop + li x5, 0xc024000000000000 // -10 + fmv.d.x f0, x5 + feq.d x5, f26, f0 + beqz x5, reg2_error_loop + li x5, 0xC026000000000000 // -11 + fmv.d.x f0, x5 + feq.d x5, f27, f0 + beqz x5, reg2_error_loop + li x5, 0xC028000000000000 // -12 + fmv.d.x f0, x5 + feq.d x5, f28, f0 + beqz x5, reg2_error_loop + li x5, 0xC02A000000000000 // -13 + fmv.d.x f0, x5 + feq.d x5, f29, f0 + beqz x5, reg2_error_loop + li x5, 0xC02C000000000000 // -14 + fmv.d.x f0, x5 + feq.d x5, f30, f0 + beqz x5, reg2_error_loop + li x5, 0xC02E000000000000 // -15 + fmv.d.x f0, x5 + feq.d x5, f31, f0 + beqz x5, reg2_error_loop +#endif /* Everything passed, increment the loop counter. */ +#if __riscv_xlen == 64 + ld x5, ulRegTest2LoopCounterConst + ld x6, 0(x5) + addi x6, x6, 1 + sd x6, 0(x5) +#else lw x5, ulRegTest2LoopCounterConst lw x6, 0(x5) addi x6, x6, 1 sw x6, 0(x5) +#endif /* Restore clobbered register reading for next loop. */ li x6, 0x61 @@ -263,5 +657,5 @@ reg2_error_loop: /* Busy loop which holds the task. */ jal reg2_error_loop -.align( 4 ) -ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter +.align( 8 ) +ulRegTest2LoopCounterConst: .dword ulRegTest2LoopCounter diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/fake_rom.ld b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/fake_rom.ld index 6f3cef8035..f3e12d9784 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/fake_rom.ld +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/fake_rom.ld @@ -5,7 +5,7 @@ MEMORY { /* Fake ROM area */ rom (rxa) : ORIGIN = 0x80000000, LENGTH = 512K - ram (wxa) : ORIGIN = 0x80080000, LENGTH = 512K + ram (wxa) : ORIGIN = 0x80080000, LENGTH = 1024K } SECTIONS diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/printf-stdarg.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/printf-stdarg.c index e8b3add570..5997d1878b 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/printf-stdarg.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/printf-stdarg.c @@ -168,29 +168,29 @@ static int tiny_print( char **out, const char *format, va_list args, unsigned in width += *format - '0'; } if( *format == 's' ) { - register char *s = (char *)va_arg( args, int ); + register char *s = (char *)va_arg( args, long ); pc += prints (out, s?s:"(null)", width, pad, buflimit); continue; } if( *format == 'd' ) { - pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a', buflimit); + pc += printi (out, va_arg( args, long ), 10, 1, width, pad, 'a', buflimit); continue; } if( *format == 'x' ) { - pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a', buflimit); + pc += printi (out, va_arg( args, long ), 16, 0, width, pad, 'a', buflimit); continue; } if( *format == 'X' ) { - pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A', buflimit); + pc += printi (out, va_arg( args, long ), 16, 0, width, pad, 'A', buflimit); continue; } if( *format == 'u' ) { - pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a', buflimit); + pc += printi (out, va_arg( args, long ), 10, 0, width, pad, 'a', buflimit); continue; } if( *format == 'c' ) { /* char are converted to int then pushed on the stack */ - scr[0] = (char)va_arg( args, int ); + scr[0] = (char)va_arg( args, long ); scr[1] = '\0'; pc += prints (out, scr, width, pad, buflimit); continue; diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/start.S b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/start.S index d36339cd40..61deae8d9f 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/start.S +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/start.S @@ -1,6 +1,6 @@ /* * FreeRTOS V202212.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -68,6 +68,12 @@ _start: addi a0, a0, REGSIZE bltu a0, a1, 1b 2: +#ifdef __riscv_fdiv + // Enable FPU + li t0, (1 << 13) + csrs mstatus, t0 + fscsr x0 +#endif // argc, argv, envp is 0 li a0, 0 diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c index 1eac040957..55d46f124f 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main.c @@ -252,7 +252,7 @@ void vAssertCalled( const char * pcFileName, * used by the Idle task. */ void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, - uint32_t * pulIdleTaskStackSize ) + StackType_t * pulIdleTaskStackSize ) { /* If the buffers to be provided to the Idle task are declared inside this * function then they must be declared static - otherwise they will be allocated on diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c index 974507ee64..f66506328e 100644 --- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c +++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/main_full.c @@ -249,7 +249,11 @@ static void prvCheckTask( void * pvParameters ) ( void ) pvParameters; /* Demo start marker. */ +#if __riscv_flen == 64 + printf( "FreeRTOS Demo Start (With FPU)\r\n" ); +#else printf( "FreeRTOS Demo Start\r\n" ); +#endif xPreviousWakeTime = xTaskGetTickCount(); diff --git a/FreeRTOS/Source b/FreeRTOS/Source index 1b8f5965d3..4d9cd906d3 160000 --- a/FreeRTOS/Source +++ b/FreeRTOS/Source @@ -1 +1 @@ -Subproject commit 1b8f5965d360953ebf5559c97418f5f5264bdbee +Subproject commit 4d9cd906d3f7c339ee3d6d64a00c416d58a8b003 diff --git a/manifest.yml b/manifest.yml index 182126d147..943a353765 100644 --- a/manifest.yml +++ b/manifest.yml @@ -5,7 +5,7 @@ license: "MIT" dependencies: - name: "FreeRTOS-Kernel" - version: "1b8f596" + version: "4d9cd90" repository: type: "git" url: "https://github.com/FreeRTOS/FreeRTOS-Kernel.git"