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ARMv7-R No_GIC Port Demo (#1236)

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Add ARM_CRx_No_GIC_Demo
pull/1244/head
Rahul Kar 6 months ago committed by GitHub
parent d3d6893489
commit 8582188293
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151 changed files with 72639 additions and 0 deletions
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1
.github/.cSpellWords.txt vendored
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@ -724,6 +724,7 @@ CMock
CNBTR
CNDA
CNDTR
CNOT
CNTALOAD
CNTAMAX
CNTBLOAD

1
.github/scripts/core_checker.py vendored
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@ -307,6 +307,7 @@ FREERTOS_IGNORED_PATTERNS = [
r'FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/.*',
r'FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC/BoardFiles/.*',
r'FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC/BoardFiles/.*',
r'FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/.*',
r'FreeRTOS/Demo/AVR_ATMega4809_Atmel_Studio/RTOSDemo/.*',
r'FreeRTOS/Demo/AVR32_UC3/.*',
r'FreeRTOS/Demo/AVR_ATMega4809_IAR/.*',

8
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.ccsproject
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104
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.clang-format
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180
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject
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50
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace vendored
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
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<property Type="choicelist" Value="1" id="Debug Probe Selection">
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<property Type="stringfield" Value="HLR57L00" id="-- Enter the serial number"/>
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</connection>
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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h
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/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: Device_RM57.c
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file defines the number of sectors.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 01.15.00 06Jun2014 Vishwanath Reddy Initial Version.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#ifndef DEVICE_RM57_H
#define DEVICE_RM57_H
/** @def DEVICE_CONFIGURATION_VERSION
* @brief Device Configuration Version
*
* @note Indicates the current version of the device files
*/
#define DEVICE_CONFIGURATION_VERSION \
0U /* Indicates the current version of the device files */
/** @def DEVICE_NUMBER_OF_FLASH_BANKS
* @brief Number of Flash Banks
*
* @note Defines the number of Flash Banks on the device
*/
#define DEVICE_NUMBER_OF_FLASH_BANKS \
1U /* Defines the number of Flash Banks on the device */
/** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS
* @brief Maximum number of Sectors
*
* @note Defines the maxium number of sectors in all banks
*/
#define DEVICE_BANK_MAX_NUMBER_OF_SECTORS \
32U /* Defines the maxium number of sectors in all banks */
/** @def DEVICE_BANK1_NUMBER_OF_SECTORS
* @brief Number of Sectors
*
* @note Defines the number of sectors in bank1
*/
#define DEVICE_BANK1_NUMBER_OF_SECTORS \
32U /* Defines the number of sectors in bank1 */
/** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS
* @brief Number of Sectors
*
* @note Defines the number of Read Cycle Thresholds
*/
#define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS \
4U /* Defines the number of Read Cycle Thresholds */
/* Include Files */
#ifndef _PLATFORM_TYPES_H_
#define _PLATFORM_TYPES_H_
#endif
#ifndef _L2FMC
#define _L2FMC
#endif
#include "F021.h"
#include "hal_stdtypes.h"
#include "Device_types.h"
#endif /* DEVICE_RM57_H */
/* End of File */

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h
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/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: Device_header.h
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file includes the header file.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 01.15.00 06Jun2014 Vishwanath Reddy Initial Version.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#ifndef TI_FEE_DEVICEHEADER_H
#define TI_FEE_DEVICEHEADER_H
/* Uncomment the appropriate include file depending on the device you are using */
#include "Device_RM57.h"
/* End of file */
#endif

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/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: Device_types.h
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file defines the structures.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 01.15.00 06Jun2014 Vishwanath Reddy Initial Version.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#ifndef DEVICE_TYPES_H
#define DEVICE_TYPES_H
#include "hal_stdtypes.h"
/* Enum to describe the type of error handling on the device */
typedef enum
{
Device_ErrorHandlingNone, /* Device has no error handling */
Device_ErrorHandlingParity, /* Device has parity error handling */
Device_ErrorHandlingEcc /* Device has ECC error handling */
} Device_FlashErrorCorrectionProcessType;
/* Enum to describe the ARM core on the device*/
typedef enum
{
Device_CoreNone, /* To indicate that the device has a single core */
Device_Arm7, /* To indicate that the device has a ARM7 core */
Device_CortexR4, /* To indicate that the device has a CortexR4 core */
Device_CortexM3 /* To indicate that the device has a CortexM3 core */
} Device_ArmCoreType;
/* Structure defines an individual sector within a bank */
typedef struct
{
Fapi_FlashSectorType Device_Sector; /* Sector number */
uint32 Device_SectorStartAddress; /* Starting address of the sector */
uint32 Device_SectorLength; /* Length of the sector */
uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */
uint32 Device_EccAddress;
uint32 Device_EccLength;
} Device_SectorType;
/* Structure defines an individual bank */
typedef struct
{
Fapi_FmcRegistersType * Device_ControlRegister;
Fapi_FlashBankType Device_Core; /* Core number for this bank */
Device_SectorType Device_SectorInfo[ DEVICE_BANK_MAX_NUMBER_OF_SECTORS ]; /* Array of
the
Sectors
within a
bank */
} Device_BankType;
/* Structure defines the Flash structure of the device */
typedef struct
{
uint8 Device_DeviceName[ 12 ]; /* Device name */
uint32 Device_EngineeringId; /* Device Engineering ID */
Device_FlashErrorCorrectionProcessType
Device_FlashErrorHandlingProcessInfo; /* Indicates
which
type
of bit
Error
handling
is on
the
device
*/
Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device
*/
boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash
interrupts for processing Flash */
uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS
*/
uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS
*/
Device_BankType Device_BankInfo[ DEVICE_NUMBER_OF_FLASH_BANKS ]; /* Array of Banks on
the device */
} Device_FlashType;
#endif /* DEVICE_TYPES_H */
/* End of File */

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h
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/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __MEM_MAP_H__
#define __MEM_MAP_H__
#endif /* __MEM_MAP_H__ */

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h
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/** @file adc.h
* @brief ADC Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ADC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __ADC_H__
#define __ADC_H__
#include "reg_adc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* ADC General Definitions */
/** @def adcGROUP0
* @brief Alias name for ADC event group
*
* @note This value should be used for API argument @a group
*/
#define adcGROUP0 0U
/** @def adcGROUP1
* @brief Alias name for ADC group 1
*
* @note This value should be used for API argument @a group
*/
#define adcGROUP1 1U
/** @def adcGROUP2
* @brief Alias name for ADC group 2
*
* @note This value should be used for API argument @a group
*/
#define adcGROUP2 2U
/** @def ADC_12_BIT_MODE
* @brief Alias name for ADC 12-bit mode of operation
*/
#define ADC_12_BIT_MODE 0x80000000U
/** @enum adcResolution
* @brief Alias names for data resolution
* This enumeration is used to provide alias names for the data resolution:
* - 12 bit resolution
* - 10 bit resolution
* - 8 bit resolution
*/
enum adcResolution
{
ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */
ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */
ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */
};
/** @enum adcFiFoStatus
* @brief Alias names for FiFo status
* This enumeration is used to provide alias names for the current FiFo states:
* - FiFo is not full
* - FiFo is full
* - FiFo overflow occurred
*/
enum adcFiFoStatus
{
ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */
ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */
ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */
};
/** @enum adcConversionStatus
* @brief Alias names for conversion status
* This enumeration is used to provide alias names for the current conversion states:
* - Conversion is not finished
* - Conversion is finished
*/
enum adcConversionStatus
{
ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished
*/
ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */
};
/** @enum adc1HwTriggerSource
* @brief Alias names for hardware trigger source
* This enumeration is used to provide alias names for the hardware trigger sources:
*/
enum adc1HwTriggerSource
{
ADC1_EVENT = 0U, /**< Alias for event pin */
ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */
ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */
ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */
ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */
ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */
ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */
ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */
ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */
ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */
ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */
ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */
ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */
ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */
ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */
ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */
ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */
ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */
ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */
};
/** @enum adc2HwTriggerSource
* @brief Alias names for hardware trigger source
* This enumeration is used to provide alias names for the hardware trigger sources:
*/
enum adc2HwTriggerSource
{
ADC2_EVENT = 0U, /**< Alias for event pin */
ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */
ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */
ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */
ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */
ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */
ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */
ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */
ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */
ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */
ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */
ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */
ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */
ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */
ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */
ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */
ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */
ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */
ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */
};
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @struct adcData
* @brief ADC Conversion data structure
*
* This type is used to pass adc conversion data.
*/
/** @typedef adcData_t
* @brief ADC Data Type Definition
*/
typedef struct adcData
{
uint32 id; /**< Channel/Pin Id */
uint16 value; /**< Conversion data value */
} adcData_t;
/* USER CODE BEGIN (2) */
/* USER CODE END */
typedef struct adc_config_reg
{
uint32 CONFIG_OPMODECR;
uint32 CONFIG_CLOCKCR;
uint32 CONFIG_GxMODECR[ 3U ];
uint32 CONFIG_G0SRC;
uint32 CONFIG_G1SRC;
uint32 CONFIG_G2SRC;
uint32 CONFIG_BNDCR;
uint32 CONFIG_BNDEND;
uint32 CONFIG_G0SAMP;
uint32 CONFIG_G1SAMP;
uint32 CONFIG_G2SAMP;
uint32 CONFIG_G0SAMPDISEN;
uint32 CONFIG_G1SAMPDISEN;
uint32 CONFIG_G2SAMPDISEN;
uint32 CONFIG_PARCR;
} adc_config_reg_t;
#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U
#define ADC1_CLOCKCR_CONFIGVALUE ( 7U )
#define ADC1_G0MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define ADC1_G1MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC1_G2MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC1_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT )
#define ADC1_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT )
#define ADC1_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT )
#define ADC1_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) )
#define ADC1_BNDEND_CONFIGVALUE ( 2U )
#define ADC1_G0SAMP_CONFIGVALUE ( 1U )
#define ADC1_G1SAMP_CONFIGVALUE ( 1U )
#define ADC1_G2SAMP_CONFIGVALUE ( 1U )
#define ADC1_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC1_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC1_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC1_PARCR_CONFIGVALUE ( 0x00000005U )
#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U
#define ADC2_CLOCKCR_CONFIGVALUE ( 7U )
#define ADC2_G0MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define ADC2_G1MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC2_G2MODECR_CONFIGVALUE \
( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define ADC2_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT )
#define ADC2_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT )
#define ADC2_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT )
#define ADC2_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) )
#define ADC2_BNDEND_CONFIGVALUE ( 2U )
#define ADC2_G0SAMP_CONFIGVALUE ( 1U )
#define ADC2_G1SAMP_CONFIGVALUE ( 1U )
#define ADC2_G2SAMP_CONFIGVALUE ( 1U )
#define ADC2_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC2_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC2_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U )
#define ADC2_PARCR_CONFIGVALUE ( 0x00000005U )
/**
* @defgroup ADC ADC
* @brief Analog To Digital Converter Module.
*
* The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit
*resolution
*
* Related Files
* - reg_adc.h
* - adc.h
* - adc.c
* @addtogroup ADC
* @{
*/
/* ADC Interface Functions */
void adcInit( void );
void adcStartConversion( adcBASE_t * adc, uint32 group );
void adcStopConversion( adcBASE_t * adc, uint32 group );
void adcResetFiFo( adcBASE_t * adc, uint32 group );
uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data );
uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group );
uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group );
void adcEnableNotification( adcBASE_t * adc, uint32 group );
void adcDisableNotification( adcBASE_t * adc, uint32 group );
void adcCalibration( adcBASE_t * adc );
uint32 adcMidPointCalibration( adcBASE_t * adc );
void adcSetEVTPin( adcBASE_t * adc, uint32 value );
uint32 adcGetEVTPin( adcBASE_t * adc );
void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type );
void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type );
/** @fn void adcNotification(adcBASE_t *adc, uint32 group)
* @brief Group notification
* @param[in] adc Pointer to ADC node:
* - adcREG1: ADC1 module pointer
* - adcREG2: ADC2 module pointer
* @param[in] group number of ADC node:
* - adcGROUP0: ADC event group
* - adcGROUP1: ADC group 1
* - adcGROUP2: ADC group 2
*
* @note This function has to be provide by the user.
*/
void adcNotification( adcBASE_t * adc, uint32 group );
/* USER CODE BEGIN (3) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file can.h
* @brief CAN Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the CAN driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __CAN_H__
#define __CAN_H__
#include "reg_can.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* CAN General Definitions */
/** @def canLEVEL_ACTIVE
* @brief Alias name for CAN error operation level active (Error counter 0-95)
*/
#define canLEVEL_ACTIVE 0x00U
/** @def canLEVEL_WARNING
* @brief Alias name for CAN error operation level warning (Error counter 96-127)
*/
#define canLEVEL_WARNING 0x40U
/** @def canLEVEL_PASSIVE
* @brief Alias name for CAN error operation level passive (Error counter 128-255)
*/
#define canLEVEL_PASSIVE 0x20U
/** @def canLEVEL_BUS_OFF
* @brief Alias name for CAN error operation level bus off (Error counter 256)
*/
#define canLEVEL_BUS_OFF 0x80U
/** @def canLEVEL_PARITY_ERR
* @brief Alias name for CAN Parity error (Error counter 256-511)
*/
#define canLEVEL_PARITY_ERR 0x100U
/** @def canLEVEL_TxOK
* @brief Alias name for CAN Sucessful Transmission
*/
#define canLEVEL_TxOK 0x08U
/** @def canLEVEL_RxOK
* @brief Alias name for CAN Sucessful Reception
*/
#define canLEVEL_RxOK 0x10U
/** @def canLEVEL_WakeUpPnd
* @brief Alias name for CAN Initiated a WakeUp to system
*/
#define canLEVEL_WakeUpPnd 0x200U
/** @def canLEVEL_PDA
* @brief Alias name for CAN entered low power mode successfully.
*/
#define canLEVEL_PDA 0x400U
/** @def canERROR_NO
* @brief Alias name for no CAN error occurred
*/
#define canERROR_OK 0U
/** @def canERROR_STUFF
* @brief Alias name for CAN stuff error an RX message
*/
#define canERROR_STUFF 1U
/** @def canERROR_FORMAT
* @brief Alias name for CAN form/format error an RX message
*/
#define canERROR_FORMAT 2U
/** @def canERROR_ACKNOWLEDGE
* @brief Alias name for CAN TX message wasn't acknowledged
*/
#define canERROR_ACKNOWLEDGE 3U
/** @def canERROR_BIT1
* @brief Alias name for CAN TX message sending recessive level but monitoring dominant
*/
#define canERROR_BIT1 4U
/** @def canERROR_BIT0
* @brief Alias name for CAN TX message sending dominant level but monitoring recessive
*/
#define canERROR_BIT0 5U
/** @def canERROR_CRC
* @brief Alias name for CAN RX message received wrong CRC
*/
#define canERROR_CRC 6U
/** @def canERROR_NO
* @brief Alias name for CAN no message has send or received since last call of
* CANGetLastError
*/
#define canERROR_NO 7U
/** @def canMESSAGE_BOX1
* @brief Alias name for CAN message box 1
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX1 1U
/** @def canMESSAGE_BOX2
* @brief Alias name for CAN message box 2
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX2 2U
/** @def canMESSAGE_BOX3
* @brief Alias name for CAN message box 3
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX3 3U
/** @def canMESSAGE_BOX4
* @brief Alias name for CAN message box 4
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX4 4U
/** @def canMESSAGE_BOX5
* @brief Alias name for CAN message box 5
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX5 5U
/** @def canMESSAGE_BOX6
* @brief Alias name for CAN message box 6
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX6 6U
/** @def canMESSAGE_BOX7
* @brief Alias name for CAN message box 7
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX7 7U
/** @def canMESSAGE_BOX8
* @brief Alias name for CAN message box 8
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX8 8U
/** @def canMESSAGE_BOX9
* @brief Alias name for CAN message box 9
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX9 9U
/** @def canMESSAGE_BOX10
* @brief Alias name for CAN message box 10
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX10 10U
/** @def canMESSAGE_BOX11
* @brief Alias name for CAN message box 11
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX11 11U
/** @def canMESSAGE_BOX12
* @brief Alias name for CAN message box 12
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX12 12U
/** @def canMESSAGE_BOX13
* @brief Alias name for CAN message box 13
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX13 13U
/** @def canMESSAGE_BOX14
* @brief Alias name for CAN message box 14
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX14 14U
/** @def canMESSAGE_BOX15
* @brief Alias name for CAN message box 15
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX15 15U
/** @def canMESSAGE_BOX16
* @brief Alias name for CAN message box 16
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX16 16U
/** @def canMESSAGE_BOX17
* @brief Alias name for CAN message box 17
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX17 17U
/** @def canMESSAGE_BOX18
* @brief Alias name for CAN message box 18
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX18 18U
/** @def canMESSAGE_BOX19
* @brief Alias name for CAN message box 19
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX19 19U
/** @def canMESSAGE_BOX20
* @brief Alias name for CAN message box 20
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX20 20U
/** @def canMESSAGE_BOX21
* @brief Alias name for CAN message box 21
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX21 21U
/** @def canMESSAGE_BOX22
* @brief Alias name for CAN message box 22
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX22 22U
/** @def canMESSAGE_BOX23
* @brief Alias name for CAN message box 23
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX23 23U
/** @def canMESSAGE_BOX24
* @brief Alias name for CAN message box 24
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX24 24U
/** @def canMESSAGE_BOX25
* @brief Alias name for CAN message box 25
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX25 25U
/** @def canMESSAGE_BOX26
* @brief Alias name for CAN message box 26
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX26 26U
/** @def canMESSAGE_BOX27
* @brief Alias name for CAN message box 27
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX27 27U
/** @def canMESSAGE_BOX28
* @brief Alias name for CAN message box 28
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX28 28U
/** @def canMESSAGE_BOX29
* @brief Alias name for CAN message box 29
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX29 29U
/** @def canMESSAGE_BOX30
* @brief Alias name for CAN message box 30
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX30 30U
/** @def canMESSAGE_BOX31
* @brief Alias name for CAN message box 31
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX31 31U
/** @def canMESSAGE_BOX32
* @brief Alias name for CAN message box 32
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX32 32U
/** @def canMESSAGE_BOX33
* @brief Alias name for CAN message box 33
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX33 33U
/** @def canMESSAGE_BOX34
* @brief Alias name for CAN message box 34
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX34 34U
/** @def canMESSAGE_BOX35
* @brief Alias name for CAN message box 35
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX35 35U
/** @def canMESSAGE_BOX36
* @brief Alias name for CAN message box 36
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX36 36U
/** @def canMESSAGE_BOX37
* @brief Alias name for CAN message box 37
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX37 37U
/** @def canMESSAGE_BOX38
* @brief Alias name for CAN message box 38
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX38 38U
/** @def canMESSAGE_BOX39
* @brief Alias name for CAN message box 39
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX39 39U
/** @def canMESSAGE_BOX40
* @brief Alias name for CAN message box 40
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX40 40U
/** @def canMESSAGE_BOX41
* @brief Alias name for CAN message box 41
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX41 41U
/** @def canMESSAGE_BOX42
* @brief Alias name for CAN message box 42
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX42 42U
/** @def canMESSAGE_BOX43
* @brief Alias name for CAN message box 43
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX43 43U
/** @def canMESSAGE_BOX44
* @brief Alias name for CAN message box 44
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX44 44U
/** @def canMESSAGE_BOX45
* @brief Alias name for CAN message box 45
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX45 45U
/** @def canMESSAGE_BOX46
* @brief Alias name for CAN message box 46
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX46 46U
/** @def canMESSAGE_BOX47
* @brief Alias name for CAN message box 47
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX47 47U
/** @def canMESSAGE_BOX48
* @brief Alias name for CAN message box 48
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX48 48U
/** @def canMESSAGE_BOX49
* @brief Alias name for CAN message box 49
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX49 49U
/** @def canMESSAGE_BOX50
* @brief Alias name for CAN message box 50
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX50 50U
/** @def canMESSAGE_BOX51
* @brief Alias name for CAN message box 51
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX51 51U
/** @def canMESSAGE_BOX52
* @brief Alias name for CAN message box 52
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX52 52U
/** @def canMESSAGE_BOX53
* @brief Alias name for CAN message box 53
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX53 53U
/** @def canMESSAGE_BOX54
* @brief Alias name for CAN message box 54
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX54 54U
/** @def canMESSAGE_BOX55
* @brief Alias name for CAN message box 55
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX55 55U
/** @def canMESSAGE_BOX56
* @brief Alias name for CAN message box 56
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX56 56U
/** @def canMESSAGE_BOX57
* @brief Alias name for CAN message box 57
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX57 57U
/** @def canMESSAGE_BOX58
* @brief Alias name for CAN message box 58
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX58 58U
/** @def canMESSAGE_BOX59
* @brief Alias name for CAN message box 59
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX59 59U
/** @def canMESSAGE_BOX60
* @brief Alias name for CAN message box 60
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX60 60U
/** @def canMESSAGE_BOX61
* @brief Alias name for CAN message box 61
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX61 61U
/** @def canMESSAGE_BOX62
* @brief Alias name for CAN message box 62
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX62 62U
/** @def canMESSAGE_BOX63
* @brief Alias name for CAN message box 63
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX63 63U
/** @def canMESSAGE_BOX64
* @brief Alias name for CAN message box 64
*
* @note This value should be used for API argument @a messageBox
*/
#define canMESSAGE_BOX64 64U
/** @enum canloopBackType
* @brief canLoopback type definition
*/
/** @typedef canloopBackType_t
* @brief canLoopback type Type Definition
*
* This type is used to select the can module Loopback type Digital or Analog loopback.
*/
typedef enum canloopBackType
{
Internal_Lbk = 0x00000010U,
External_Lbk = 0x00000100U,
Internal_Silent_Lbk = 0x00000018U
} canloopBackType_t;
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Configuration registers */
typedef struct can_config_reg
{
uint32 CONFIG_CTL;
uint32 CONFIG_ES;
uint32 CONFIG_BTR;
uint32 CONFIG_TEST;
uint32 CONFIG_ABOTR;
uint32 CONFIG_INTMUX0;
uint32 CONFIG_INTMUX1;
uint32 CONFIG_INTMUX2;
uint32 CONFIG_INTMUX3;
uint32 CONFIG_TIOC;
uint32 CONFIG_RIOC;
} can_config_reg_t;
/* Configuration registers initial value for CAN1*/
#define CAN1_CTL_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U )
#define CAN1_ES_CONFIGVALUE 0x00000007U
#define CAN1_BTR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \
| ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \
| ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U )
#define CAN1_TEST_CONFIGVALUE 0x00000080U
#define CAN1_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) )
#define CAN1_INTMUX0_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN1_INTMUX1_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN1_INTMUX2_CONFIGVALUE 0x00000000U
#define CAN1_INTMUX3_CONFIGVALUE 0x00000000U
#define CAN1_TIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define CAN1_RIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
/* Configuration registers initial value for CAN2*/
#define CAN2_CTL_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U )
#define CAN2_ES_CONFIGVALUE 0x00000007U
#define CAN2_BTR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \
| ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \
| ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U )
#define CAN2_TEST_CONFIGVALUE 0x00000080U
#define CAN2_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) )
#define CAN2_INTMUX0_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN2_INTMUX1_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U
#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U
#define CAN2_TIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define CAN2_RIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
/* Configuration registers initial value for CAN3*/
#define CAN3_CTL_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U )
#define CAN3_ES_CONFIGVALUE 0x00000007U
#define CAN3_BTR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \
| ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \
| ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U )
#define CAN3_TEST_CONFIGVALUE 0x00000080U
#define CAN3_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) )
#define CAN3_INTMUX0_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN3_INTMUX1_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U
#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U
#define CAN3_TIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define CAN3_RIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
/* Configuration registers initial value for CAN4*/
#define CAN4_CTL_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U )
#define CAN4_ES_CONFIGVALUE 0x00000007U
#define CAN4_BTR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \
| ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \
| ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U )
#define CAN4_TEST_CONFIGVALUE 0x00000080U
#define CAN4_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) )
#define CAN4_INTMUX0_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN4_INTMUX1_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define CAN4_INTMUX2_CONFIGVALUE 0x00000000U
#define CAN4_INTMUX3_CONFIGVALUE 0x00000000U
#define CAN4_TIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define CAN4_RIOC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
/**
* @defgroup CAN CAN
* @brief Controller Area Network Module.
*
* The Controller Area Network is a high-integrity, serial, multi-master communication
* protocol for distributed real-time applications. This CAN module is implemented
* according to ISO 11898-1 and is suitable for industrial, automotive and general
* embedded communications
*
* Related Files
* - reg_can.h
* - can.h
* - can.c
* @addtogroup CAN
* @{
*/
/* CAN Interface Functions */
void canInit( void );
uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data );
uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data );
uint32 canGetID( canBASE_t * node, uint32 messageBox );
void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal );
uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox );
uint32 canFillMessageObjectData( canBASE_t * node,
uint32 messageBox,
const uint8 * data );
uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox );
uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox );
uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox );
uint32 canGetLastError( canBASE_t * node );
uint32 canGetErrorLevel( canBASE_t * node );
void canEnableErrorNotification( canBASE_t * node );
void canDisableErrorNotification( canBASE_t * node );
void canEnableStatusChangeNotification( canBASE_t * node );
void canDisableStatusChangeNotification( canBASE_t * node );
void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype );
void canDisableloopback( canBASE_t * node );
void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir );
void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue );
uint32 canIoTxGetBit( canBASE_t * node );
uint32 canIoRxGetBit( canBASE_t * node );
void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type );
void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type );
void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type );
void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type );
/** @fn void canErrorNotification(canBASE_t *node, uint32 notification)
* @brief Error notification
* @param[in] node Pointer to CAN node:
* - canREG1: CAN1 node pointer
* - canREG2: CAN2 node pointer
* - canREG3: CAN3 node pointer
* @param[in] notification Error notification code:
* - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32
* and 63
* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and
* 127
* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255
* - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256
*
* @note This function has to be provide by the user.
*/
void canErrorNotification( canBASE_t * node, uint32 notification );
/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification)
* @brief Status Change notification
* @param[in] node Pointer to CAN node:
* - canREG1: CAN1 node pointer
* - canREG2: CAN2 node pointer
* - canREG3: CAN3 node pointer
* @param[in] notification Status change notification code:
* - canLEVEL_TxOK (0x08) : When sucessful transmission
* - canLEVEL_RxOK (0x10) : When sucessful reception
* - canLEVEL_WakeUpPnd (0x200): When sucessful WakeUp to system initiated
* - canLEVEL_PDA (0x400): When sucessful low power mode entrance
*
* @note This function has to be provide by the user.
*/
void canStatusChangeNotification( canBASE_t * node, uint32 notification );
/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox)
* @brief Message notification
* @param[in] node Pointer to CAN node:
* - canREG1: CAN1 node pointer
* - canREG2: CAN2 node pointer
* - canREG3: CAN3 node pointer
* @param[in] messageBox Message box number of CAN node:
* - canMESSAGE_BOX1: CAN message box 1
* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
* - canMESSAGE_BOX64: CAN message box 64
*
* @note This function has to be provide by the user.
*/
void canMessageNotification( canBASE_t * node, uint32 messageBox );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h
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@ -0,0 +1,344 @@
/** @file crc.h
* @brief CRC Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the CRC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __CRC_H__
#define __CRC_H__
#include "reg_crc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* CRC General Definitions */
/** @def CRCLEVEL_ACTIVE
* @brief Alias name for CRC error operation level active
*/
#define CRCLEVEL_ACTIVE 0x00U
/** @def CRC_AUTO
* @brief Alias name for CRC auto mode
*/
#define CRC_AUTO 0x00000001U
/** @def CRC_SEMI_CPU
* @brief Alias name for semi cpu mode setting
*/
#define CRC_SEMI_CPU 0x00000002U
/** @def CRC_FULL_CPU
* @brief Alias name for CRC cpu full mode
*/
#define CRC_FULL_CPU 0x00000003U
/** @def CRC_CH4_TO
* @brief Alias name for channel4 time out interrupt flag
*/
#define CRC_CH4_TO 0x10000000U
/** @def CRC_CH4_UR
* @brief Alias name for channel4 underrun interrupt flag
*/
#define CRC_CH4_UR 0x08000000U
/** @def CRC_CH4_OR
* @brief Alias name for channel4 overrun interrupt flag
*/
#define CRC_CH4_OR 0x04000000U
/** @def CRC_CH4_FAIL
* @brief Alias name for channel4 crc fail interrupt flag
*/
#define CRC_CH4_FAIL 0x02000000U
/** @def CRC_CH4_CC
* @brief Alias name for channel4 compression complete interrupt flag
*/
#define CRC_CH4_CC 0x01000000U
/** @def CRC_CH3_TO
* @brief Alias name for channel3 time out interrupt flag
*/
#define CRC_CH3_TO 0x00100000U
/** @def CRC_CH3_UR
* @brief Alias name for channel3 underrun interrupt flag
*/
#define CRC_CH3_UR 0x00080000U
/** @def CRC_CH3_OR
* @brief Alias name for channel3 overrun interrupt flag
*/
#define CRC_CH3_OR 0x00040000U
/** @def CRC_CH3_FAIL
* @brief Alias name for channel3 crc fail interrupt flag
*/
#define CRC_CH3_FAIL 0x00020000U
/** @def CRC_CH3_CC
* @brief Alias name for channel3 compression complete interrupt flag
*/
#define CRC_CH3_CC 0x00010000U
/** @def CRC_CH2_TO
* @brief Alias name for channel2 time out interrupt flag
*/
#define CRC_CH2_TO 0x00001000U
/** @def CRC_CH2_UR
* @brief Alias name for channel2 underrun interrupt flag
*/
#define CRC_CH2_UR 0x00000800U
/** @def CRC_CH2_OR
* @brief Alias name for channel2 overrun interrupt flag
*/
#define CRC_CH2_OR 0x00000400U
/** @def CRC_CH2_FAIL
* @brief Alias name for channel2 crc fail interrupt flag
*/
#define CRC_CH2_FAIL 0x00000200U
/** @def CRC_CH2_CC
* @brief Alias name for channel2 compression complete interrupt flag
*/
#define CRC_CH2_CC 0x00000100U
/** @def CRC_CH1_TO
* @brief Alias name for channel1 time out interrupt flag
*/
#define CRC_CH1_TO 0x00000010U
/** @def CRC_CH1_UR
* @brief Alias name for channel1 underrun interrupt flag
*/
#define CRC_CH1_UR 0x00000008U
/** @def CRC_CH1_OR
* @brief Alias name for channel1 overrun interrupt flag
*/
#define CRC_CH1_OR 0x00000004U
/** @def CRC_CH1_FAIL
* @brief Alias name for channel1 crc fail interrupt flag
*/
#define CRC_CH1_FAIL 0x00000002U
/** @def CRC_CH1_CC
* @brief Alias name for channel1 compression complete interrupt flag
*/
#define CRC_CH1_CC 0x00000001U
/** @def CRC_CH1
* @brief Alias name for channel1
*/
#define CRC_CH1 0x00000000U
/** @def CRC_CH1
* @brief Alias name for channel2
*/
#define CRC_CH2 0x00000001U
/** @def CRC_CH3
* @brief Alias name for channel3
*/
#define CRC_CH3 0x00000002U
/** @def CRC_CH4
* @brief Alias name for channel4
*/
#define CRC_CH4 0x00000003U
/** @struct crcModConfig
* @brief CRC mode specific parameters
*
* This type is used to pass crc mode specific parameters
*/
/** @typedef crcModConfig_t
* @brief CRC Data Type Definition
*/
typedef struct crcModConfig
{
uint32 mode; /**< Mode of operation */
uint32 crc_channel; /**< CRC channel-0,1 */
uint64 * src_data_pat; /**< Pattern data */
uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/
} crcModConfig_t;
/** @struct crcConfig
* @brief CRC configuration for different modes
*
* This type is used to pass crc configuration
*/
/** @typedef crcConfig_t
* @brief CRC Data Type Definition
*/
typedef struct crcConfig
{
uint32 crc_channel; /**< CRC channel-0,1 */
uint32 mode; /**< Mode of operation */
uint32 pcount; /**< Pattern count*/
uint32 scount; /**< Sector count */
uint32 wdg_preload; /**< Watchdog period */
uint32 block_preload; /**< Block period*/
} crcConfig_t;
/* USER CODE BEGIN (1) */
/* USER CODE END */
typedef struct crc_config_reg
{
uint32 CONFIG_CTRL0;
uint32 CONFIG_CTRL1;
uint32 CONFIG_CTRL2;
uint32 CONFIG_INTS;
uint32 CONFIG_PCOUNT_REG1;
uint32 CONFIG_SCOUNT_REG1;
uint32 CONFIG_WDTOPLD1;
uint32 CONFIG_BCTOPLD1;
uint32 CONFIG_PCOUNT_REG2;
uint32 CONFIG_SCOUNT_REG2;
uint32 CONFIG_WDTOPLD2;
uint32 CONFIG_BCTOPLD2;
} crc_config_reg_t;
#define CRC1_CTRL0_CONFIGVALUE 0x00000000U
#define CRC1_CTRL1_CONFIGVALUE 0x00000000U
#define CRC1_CTRL2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \
| ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) )
#define CRC1_INTS_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define CRC1_PCOUNT_REG1_CONFIGVALUE ( 0x00000000U )
#define CRC1_SCOUNT_REG1_CONFIGVALUE ( 0x00000000U )
#define CRC1_WDTOPLD1_CONFIGVALUE ( 0x00000000U )
#define CRC1_BCTOPLD1_CONFIGVALUE ( 0x00000000U )
#define CRC1_PCOUNT_REG2_CONFIGVALUE ( 0x00000000U )
#define CRC1_SCOUNT_REG2_CONFIGVALUE ( 0x00000000U )
#define CRC1_WDTOPLD2_CONFIGVALUE ( 0x00000000U )
#define CRC1_BCTOPLD2_CONFIGVALUE ( 0x00000000U )
#define CRC2_CTRL0_CONFIGVALUE 0x00000000U
#define CRC2_CTRL1_CONFIGVALUE 0x00000000U
#define CRC2_CTRL2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \
| ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) )
#define CRC2_INTS_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define CRC2_PCOUNT_REG1_CONFIGVALUE ( 0U )
#define CRC2_SCOUNT_REG1_CONFIGVALUE ( 0U )
#define CRC2_WDTOPLD1_CONFIGVALUE ( 0U )
#define CRC2_BCTOPLD1_CONFIGVALUE ( 0U )
#define CRC2_PCOUNT_REG2_CONFIGVALUE ( 0U )
#define CRC2_SCOUNT_REG2_CONFIGVALUE ( 0U )
#define CRC2_WDTOPLD2_CONFIGVALUE ( 0U )
#define CRC2_BCTOPLD2_CONFIGVALUE ( 0U )
/**
* @defgroup CRC CRC
* @brief Cyclic Redundancy Check Controller Module.
*
* The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check)
* to verify the integrity of memory system. A signature representing the contents of the
* memory is obtained when the contents of the memory are read into CRC controller. The
* responsibility of CRC controller is to calculate the signature for a set of data and
* then compare the calculated signature value against a pre-determined good signature
* value. CRC controller supports two channels to perform CRC calculation on multiple
* memories in parallel and can be used on any memory system.
*
* Related Files
* - reg_crc.h
* - crc.h
* - crc.c
* @addtogroup CRC
* @{
*/
/* CRC Interface Functions */
void crcInit( void );
void crcSendPowerDown( crcBASE_t * crc );
void crcSignGen( crcBASE_t * crc, crcModConfig_t * param );
void crcSetConfig( crcBASE_t * crc, crcConfig_t * param );
uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel );
uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel );
uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel );
uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel );
void crcChannelReset( crcBASE_t * crc, uint32 channel );
void crcEnableNotification( crcBASE_t * crc, uint32 flags );
void crcDisableNotification( crcBASE_t * crc, uint32 flags );
void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type );
void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type );
/** @fn void crcNotification(crcBASE_t *crc, uint32 flags)
* @brief Interrupt callback
* @param[in] crc - crc module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called upon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void crcNotification( crcBASE_t * crc, uint32 flags );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file dcc.h
* @brief DCC Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __DCC_H__
#define __DCC_H__
#include "reg_dcc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* DCC General Definitions */
/** @def dcc1CNT0_CLKSRC_HFLPO
* @brief Alias name for DCC1 Counter 0 Clock Source HFLPO
*
* This is an alias name for the Clock Source HFLPO for DCC1 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U
/** @def dcc1CNT0_CLKSRC_TCK
* @brief Alias name for DCC1 Counter 0 Clock Source TCK
*
* This is an alias name for the Clock Source TCK for DCC1 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc1CNT0_CLKSRC_TCK 0x0000000AU
/** @def dcc1CNT0_CLKSRC_OSCIN
* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
*
* This is an alias name for the Clock Source OSCIN for DCC1 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU
/** @def dcc1CNT1_CLKSRC_PLL1
* @brief Alias name for DCC1 Counter 1 Clock Source PLL1
*
* This is an alias name for the Clock Source PLL for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
/** @def dcc1CNT1_CLKSRC_PLL2
* @brief Alias name for DCC1 Counter 1 Clock Source PLL2
*
* This is an alias name for the Clock Source OSCIN for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
/** @def dcc1CNT1_CLKSRC_LFLPO
* @brief Alias name for DCC1 Counter 1 Clock Source LFLPO
*
* This is an alias name for the Clock Source LFLPO for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U
/** @def dcc1CNT1_CLKSRC_HFLPO
* @brief Alias name for DCC1 Counter 1 Clock Source HFLPO
*
* This is an alias name for the Clock Source HFLPO for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U
/** @def dcc1CNT1_CLKSRC_EXTCLKIN1
* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1
*
* This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U
/** @def dcc1CNT1_CLKSRC_EXTCLKIN2
* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2
*
* This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U
/** @def dcc1CNT1_CLKSRC_VCLK
* @brief Alias name for DCC1 Counter 1 Clock Source VCLK
*
* This is an alias name for the Clock Source VCLK for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U
/** @def dcc1CNT1_CLKSRC_N2HET1_31
* @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31
*
* This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU
/** @def dcc2CNT0_CLKSRC_TCK
* @brief Alias name for DCC2 Counter 0 Clock Source TCK
*
* This is an alias name for the Clock Source TCK for DCC2 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc2CNT0_CLKSRC_TCK 0x0000000AU
/** @def dcc1CNT0_CLKSRC_OSCIN
* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
*
* This is an alias name for the Clock Source OSCIN for DCC2 Counter 0.
*
* @note This value should be used for API argument @a cnt0_Clock_Source
*/
#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU
/** @def dcc2CNT1_CLKSRC_VCLK
* @brief Alias name for DCC2 Counter 1 Clock Source VCLK
*
* This is an alias name for the Clock Source VCLK for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U
/** @def dcc2CNT1_CLKSRC_ODCLK8
* @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/8
*
* This is an alias name for the Clock Source PLL2_post_ODCLK/8 for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_ODCLK8 0x0000A001U
/** @def dcc2CNT1_CLKSRC_ODCLK16
* @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/16
*
* This is an alias name for the Clock Source PLL2_post_ODCLK/16 for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_ODCLK16 0x0000A002U
/** @def dcc2CNT1_CLKSRC_N2HET1_0
* @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0
*
* This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1.
*
* @note This value should be used for API argument @a cnt1_Clock_Source
*/
#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU
/** @def dccNOTIFICATION_DONE
* @brief Alias name for DCC Done notification
*
* This is an alias name for the DCC Done notification.
*
* @note This value should be used for API argument @a notification
*/
#define dccNOTIFICATION_DONE 0x0000A000U
/** @def dccNOTIFICATION_ERROR
* @brief Alias name for DCC Error notification
*
* This is an alias name for the DCC Error notification.
*
* @note This value should be used for API argument @a notification
*/
#define dccNOTIFICATION_ERROR 0x000000A0U
/** @enum dcc1clocksource
* @brief Alias names for dcc clock sources
*
* This enumeration is used to provide alias names for the clock sources:
*/
enum dcc1clocksource
{
DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
};
/** @enum dcc2clocksource
* @brief Alias names for dcc clock sources
*
* This enumeration is used to provide alias names for the clock sources:
*/
enum dcc2clocksource
{
DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
DCC2_CNT1_ODCLK8 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
DCC2_CNT1_ODCLK16 = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
};
/* Configuration registers */
typedef struct dcc_config_reg
{
uint32 CONFIG_GCTRL;
uint32 CONFIG_CNT0SEED;
uint32 CONFIG_VALID0SEED;
uint32 CONFIG_CNT1SEED;
uint32 CONFIG_CNT1CLKSRC;
uint32 CONFIG_CNT0CLKSRC;
} dcc_config_reg_t;
/* Configuration registers initial value */
#define DCC1_GCTRL_CONFIGVALUE \
( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \
| ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) )
#define DCC1_CNT0SEED_CONFIGVALUE 39204U
#define DCC1_VALID0SEED_CONFIGVALUE 792U
#define DCC1_CNT1SEED_CONFIGVALUE 742500U
#define DCC1_CNT1CLKSRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 10U << 12U ) | ( uint32 ) DCC1_CNT1_PLL1 )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Values come from GUI drop down option" */
#define DCC1_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC1_CNT0_OSCIN )
#define DCC2_GCTRL_CONFIGVALUE \
( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \
| ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) )
#define DCC2_CNT0SEED_CONFIGVALUE 0U
#define DCC2_VALID0SEED_CONFIGVALUE 0U
#define DCC2_CNT1SEED_CONFIGVALUE 0U
#define DCC2_CNT1CLKSRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | ( uint32 ) DCC2_CNT1_VCLK )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Values come from GUI drop down option" */
#define DCC2_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC2_CNT0_OSCIN )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**
* @defgroup DCC DCC
* @brief Dual-Clock Comparator Module
*
* The primary purpose of a DCC module is to measure the frequency of a clock signal
* using a second known clock signal as a reference. This capability can be used to ensure
* the correct frequency range for several different device clock sources, thereby
* enhancing the system safety metrics.
*
* Related Files
* - reg_dcc.h
* - dcc.h
* - dcc .c
* @addtogroup DCC
* @{
*/
/* DCC Interface Functions */
void dccInit( void );
void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed );
void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed );
void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed );
void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed );
void dccSelectClockSource( dccBASE_t * dcc,
uint32 cnt0_Clock_Source,
uint32 cnt1_Clock_Source );
void dccEnable( dccBASE_t * dcc );
void dccDisable( dccBASE_t * dcc );
uint32 dccGetErrStatus( dccBASE_t * dcc );
void dccEnableNotification( dccBASE_t * dcc, uint32 notification );
void dccDisableNotification( dccBASE_t * dcc, uint32 notification );
void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type );
void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type );
/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags)
* @brief Interrupt callback
* @param[in] dcc - dcc module base address
* @param[in] flags - status flags
*
* This is a callback function provided by the application. It is call when
* a dcc is complete or detected error.
*/
void dccNotification( dccBASE_t * dcc, uint32 flags );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file dmm.h
* @brief DMM Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __DMM_H__
#define __DMM_H__
#include "reg_dmm.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Configuration registers */
typedef struct dmm_config_reg
{
uint32 CONFIG_PC0;
uint32 CONFIG_PC1;
uint32 CONFIG_PC3;
uint32 CONFIG_PC6;
uint32 CONFIG_PC7;
uint32 CONFIG_PC8;
} dmm_config_reg_t;
#define DMM_PC3_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define DMM_PC1_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
#define DMM_PC6_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define DMM_PC8_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
#define DMM_PC7_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define DMM_PC0_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
/**
* @defgroup DMM DMM
* @brief Data Modification Module.
*
* The DMM module provides the capability to modify data in the entire 4 GB address space
*of the device from an external peripheral, with minimal interruption of the application.
*
* Related Files
* - reg_dmm.h
* - dmm.h
* - dmm.c
* @addtogroup DMM
* @{
*/
/* DMM Interface Functions */
void dmmInit( void );
void dmmGetConfigValue( dmm_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file ecap.h
* @brief ECAP Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ECAP driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __ECAP_H__
#define __ECAP_H__
#include "reg_ecap.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @brief Enumeration to define the capture (CAP) interrupts
*/
typedef enum
{
ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */
ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */
ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */
ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */
ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */
ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */
ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */
ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */
ecapInt_All = 0x00FFU /*< Denotes All interrupts */
} ecapInterrupt_t;
/** @brief Enumeration to define the capture (CAP) prescaler values
*/
typedef enum
{
ecapPrescale_By_1 = ( ( uint16 ) 0U << 9U ), /*< Divide by 1 */
ecapPrescale_By_2 = ( ( uint16 ) 1U << 9U ), /*< Divide by 2 */
ecapPrescale_By_4 = ( ( uint16 ) 2U << 9U ), /*< Divide by 4 */
ecapPrescale_By_6 = ( ( uint16 ) 3U << 9U ), /*< Divide by 6 */
ecapPrescale_By_8 = ( ( uint16 ) 4U << 9U ), /*< Divide by 8 */
ecapPrescale_By_10 = ( ( uint16 ) 5U << 9U ), /*< Divide by 10 */
ecapPrescale_By_12 = ( ( uint16 ) 6U << 9U ), /*< Divide by 12 */
ecapPrescale_By_14 = ( ( uint16 ) 7U << 9U ), /*< Divide by 14 */
ecapPrescale_By_16 = ( ( uint16 ) 8U << 9U ), /*< Divide by 16 */
ecapPrescale_By_18 = ( ( uint16 ) 9U << 9U ), /*< Divide by 18 */
ecapPrescale_By_20 = ( ( uint16 ) 10U << 9U ), /*< Divide by 20 */
ecapPrescale_By_22 = ( ( uint16 ) 11U << 9U ), /*< Divide by 22 */
ecapPrescale_By_24 = ( ( uint16 ) 12U << 9U ), /*< Divide by 24 */
ecapPrescale_By_26 = ( ( uint16 ) 13U << 9U ), /*< Divide by 26 */
ecapPrescale_By_28 = ( ( uint16 ) 14U << 9U ), /*< Divide by 28 */
ecapPrescale_By_30 = ( ( uint16 ) 15U << 9U ), /*< Divide by 30 */
ecapPrescale_By_32 = ( ( uint16 ) 16U << 9U ), /*< Divide by 32 */
ecapPrescale_By_34 = ( ( uint16 ) 17U << 9U ), /*< Divide by 34 */
ecapPrescale_By_36 = ( ( uint16 ) 18U << 9U ), /*< Divide by 36 */
ecapPrescale_By_38 = ( ( uint16 ) 19U << 9U ), /*< Divide by 38 */
ecapPrescale_By_40 = ( ( uint16 ) 20U << 9U ), /*< Divide by 40 */
ecapPrescale_By_42 = ( ( uint16 ) 21U << 9U ), /*< Divide by 42 */
ecapPrescale_By_44 = ( ( uint16 ) 22U << 9U ), /*< Divide by 44 */
ecapPrescale_By_46 = ( ( uint16 ) 23U << 9U ), /*< Divide by 46 */
ecapPrescale_By_48 = ( ( uint16 ) 24U << 9U ), /*< Divide by 48 */
ecapPrescale_By_50 = ( ( uint16 ) 25U << 9U ), /*< Divide by 50 */
ecapPrescale_By_52 = ( ( uint16 ) 26U << 9U ), /*< Divide by 52 */
ecapPrescale_By_54 = ( ( uint16 ) 27U << 9U ), /*< Divide by 54 */
ecapPrescale_By_56 = ( ( uint16 ) 28U << 9U ), /*< Divide by 56 */
ecapPrescale_By_58 = ( ( uint16 ) 29U << 9U ), /*< Divide by 58 */
ecapPrescale_By_60 = ( ( uint16 ) 30U << 9U ), /*< Divide by 60 */
ecapPrescale_By_62 = ( ( uint16 ) 31U << 9U ) /*< Divide by 62 */
} ecapPrescale_t;
/** @brief Enumeration to define the Sync Out options
*/
typedef enum
{
SyncOut_SyncIn = ( ( uint16 ) 0U << 6U ), /*< Sync In used for Sync Out */
SyncOut_CTRPRD = ( ( uint16 ) 1U << 6U ), /*< CTR = PRD used for Sync Out */
SyncOut_None = ( ( uint16 ) 2U << 6U ) /*< Disables Sync Out */
} ecapSyncOut_t;
/** @brief Enumeration to define the Polarity
*/
typedef enum
{
RISING_EDGE = 0U,
FALLING_EDGE = 1U
} ecapEdgePolarity_t;
typedef enum
{
ACTIVE_HIGH = 0U,
ACTIVE_LOW = 1U
} ecapAPWMPolarity_t;
/** @brief Enumeration to define the Mode of operation
*/
typedef enum
{
CONTINUOUS = 0U,
ONE_SHOT = 1U
} ecapMode_t;
/** @brief Enumeration to define the capture events
*/
typedef enum
{
CAPTURE_EVENT1 = 0U,
CAPTURE_EVENT2 = 1U,
CAPTURE_EVENT3 = 2U,
CAPTURE_EVENT4 = 3U
} ecapEvent_t;
typedef enum
{
RESET_ENABLE = 1U,
RESET_DISABLE = 0U
} ecapReset_t;
typedef struct ecap_config_reg
{
uint32 CONFIG_CTRPHS;
uint16 CONFIG_ECCTL1;
uint16 CONFIG_ECCTL2;
uint16 CONFIG_ECEINT;
} ecap_config_reg_t;
#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP1_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP1_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP1_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP2_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP2_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP2_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP3_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP3_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP3_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP4_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP4_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP4_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP5_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP5_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP5_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U
#define ECAP6_ECCTL1_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \
| ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) )
#define ECAP6_ECCTL2_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \
| ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U )
#define ECAP6_ECEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
/**
* @defgroup eCAP eCAP
* @brief Enhanced Capture Module.
*
* The enhanced Capture (eCAP) module is essential in systems where accurate timing of
*external events is important. This microcontroller implements 6 instances of the eCAP
*module.
*
* Related Files
* - reg_ecap.h
* - ecap.h
* - ecap.c
* @addtogroup eCAP
* @{
*/
void ecapInit( void );
void ecapSetCounter( ecapBASE_t * ecap, uint32 value );
void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase );
void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap );
void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale );
void ecapSetCaptureEvent1( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureEvent2( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureEvent3( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureEvent4( ecapBASE_t * ecap,
ecapEdgePolarity_t edgePolarity,
ecapReset_t resetenable );
void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event );
void ecapEnableCapture( ecapBASE_t * ecap );
void ecapDisableCapture( ecapBASE_t * ecap );
void ecapStartCounter( ecapBASE_t * ecap );
void ecapStopCounter( ecapBASE_t * ecap );
void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc );
void ecapEnableAPWMmode( ecapBASE_t * ecap,
ecapAPWMPolarity_t pwmPolarity,
uint32 period,
uint32 duty );
void ecapDisableAPWMMode( ecapBASE_t * ecap );
void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts );
void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts );
uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events );
void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events );
uint32 ecapGetCAP1( ecapBASE_t * ecap );
uint32 ecapGetCAP2( ecapBASE_t * ecap );
uint32 ecapGetCAP3( ecapBASE_t * ecap );
uint32 ecapGetCAP4( ecapBASE_t * ecap );
void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type );
/** @brief Interrupt callback
* @param[in] ecap Handle to CAP object
* @param[in] flags Copy of interrupt flags
*/
void ecapNotification( ecapBASE_t * ecap, uint16 flags );
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif /*end of _CAP_H_ definition */

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/**
* \file emac.h
*
* \brief EMAC APIs and macros.
*
* This file contains the driver API prototypes and macro definitions.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __EMAC_H__
#define __EMAC_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_common.h"
#include "hw_reg_access.h"
#include "hw_emac.h"
#include "hw_emac_ctrl.h"
#include "mdio.h"
#include "emac_phyConfig.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/*****************************************************************************/
/*
** Macros which can be used as speed parameter to the API EMACRMIISpeedSet
*/
#define EMAC_RMIISPEED_10MBPS ( 0x00000000U )
#define EMAC_RMIISPEED_100MBPS ( 0x00008000U )
/* Macros for enabling taken as inputs from HALCoGen GUI. */
#define EMAC_TX_ENABLE ( 1U )
#define EMAC_RX_ENABLE ( 1U )
#define EMAC_MII_ENABLE ( 1U )
#define EMAC_FULL_DUPLEX_ENABLE ( 1U )
#define EMAC_LOOPBACK_ENABLE ( 0U )
#define EMAC_BROADCAST_ENABLE ( 1U )
#define EMAC_UNICAST_ENABLE ( 1U )
#define EMAC_CHANNELNUMBER ( 0U )
#define EMAC_PHYADDRESS ( 1U )
/*
* Macros to indicate EMAC Channel Numbers
*/
#define EMAC_CHANNEL_0 ( 0x00000000U )
#define EMAC_CHANNEL_1 ( 0x00000001U )
#define EMAC_CHANNEL_2 ( 0x00000002U )
#define EMAC_CHANNEL_3 ( 0x00000003U )
#define EMAC_CHANNEL_4 ( 0x00000004U )
#define EMAC_CHANNEL_5 ( 0x00000005U )
#define EMAC_CHANNEL_6 ( 0x00000006U )
#define EMAC_CHANNEL_7 ( 0x00000007U )
/* Macros which can be used as duplexMode parameter to the API
** EMACDuplexSet
*/
#define EMAC_DUPLEX_FULL ( 0x00000001U )
#define EMAC_DUPLEX_HALF ( 0x00000000U )
/*
** Macros which can be used as matchFilt parameters to the API
** EMACMACAddrSet
*/
/* Address not used to match/filter incoming packets */
#define EMAC_MACADDR_NO_MATCH_NO_FILTER ( 0x00000000U )
/* Address will be used to filter incoming packets */
#define EMAC_MACADDR_FILTER ( 0x00100000U )
/* Address will be used to match incoming packets */
#define EMAC_MACADDR_MATCH ( 0x00180000U )
/*
** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API
*/
#define EMAC_INT_CORE0_RX ( 0x1U )
#define EMAC_INT_CORE1_RX ( 0x5U )
#define EMAC_INT_CORE2_RX ( 0x9U )
/*
** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API
*/
#define EMAC_INT_CORE0_TX ( 0x2U )
#define EMAC_INT_CORE1_TX ( 0x6U )
#define EMAC_INT_CORE2_TX ( 0xAU )
/* Base Addresses */
#define EMAC_CTRL_RAM_0_BASE 0xFC520000U
#define EMAC_0_BASE 0xFCF78000U
#define EMAC_CTRL_0_BASE 0xFCF78800U
#define MDIO_0_BASE 0xFCF78900U
/*MAC address length*/
#define EMAC_HWADDR_LEN 6U
#define MAX_EMAC_INSTANCE 1U
#define SIZE_EMAC_CTRL_RAM 0x2000U
#define MAX_TRANSFER_UNIT 1514U
#define MAX_RX_PBUF_ALLOC ( 10U )
#define MIN_PKT_LEN 60U
#define MIN_PACKET_SIZE ( 46U )
#define EMAC_BUF_DESC_OWNER 0x20000000U
#define EMAC_BUF_DESC_SOP 0x80000000U
#define EMAC_BUF_DESC_EOP 0x40000000U
#define EMAC_BUF_DESC_EOQ 0x10000000U
#define EMAC_NETSTATREGS( n ) ( ( uint32 ) 0x200U + ( uint32 ) ( ( n ) * 4U ) )
/* Error Signalling Macros */
#define EMAC_ERR_CONNECT 0x2U /* Not connected. */
#define EMAC_ERR_OK 0x1U /* No error, everything OK. */
/* Macros for Configuration Value Registers */
#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U
#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U
#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U
#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U
#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U
#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U
#define EMAC_MACSRCADDRHI_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0xFFU << 24U ) | ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) \
| ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) )
#define EMAC_MACSRCADDRLO_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) )
#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU
#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U
#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U
/* Structure to store pending status from the Tx Interrupt Status Registers. */
typedef struct emac_tx_int_status
{
volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit
Interrupt Status (Masked) Register (TXINTSTATMASKED)
*/
volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit
Interrupt Status (Unmasked) Register (TXINTSTATRAW) */
} emac_tx_int_status_t;
/* Structure to store pending status from the Rx Interrupt Status Registers. */
typedef struct emac_rx_int_status
{
volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt
Status (Unmasked) Register (RXINTSTATRAW) */
volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the
Receive Interrupt Status (Unmasked)
Register (RXINTSTATRAW) */
volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt
Status (Unmasked) Register (RXINTSTATRAW) */
volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive
Interrupt Status (Unmasked) Register
(RXINTSTATRAW) */
} emac_rx_int_status_t;
/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer
* descriptor structure.*/
typedef struct emac_tx_bd
{
volatile struct emac_tx_bd * next;
volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be
transmitted. */
volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */
volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
} emac_tx_bd_t;
/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer
* descriptor structure. */
typedef struct emac_rx_bd
{
volatile struct emac_rx_bd * next; /*Used as a pointer for next element in the linked
list of descriptors.*/
volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received
data.*/
volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/
volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
} emac_rx_bd_t;
/**
* Helper struct to hold the data used to operate on a particular
* receive channel
*/
typedef struct rxch_struct
{
volatile emac_rx_bd_t * free_head; /*Used to point to the free buffer descriptor which
can receive new data.*/
volatile emac_rx_bd_t * active_head; /*Used to point to the active descriptor in the
chain which is receiving.*/
volatile emac_rx_bd_t * active_tail; /*Used to point to the last descriptor in the
chain.*/
} rxch_t;
/**
* Helper struct to hold the data used to operate on a particular
* transmit channel
*/
typedef struct txch_struct
{
volatile emac_tx_bd_t * free_head; /*Used to point to the free buffer descriptor which
can transmit new data.*/
volatile emac_tx_bd_t * active_tail; /*Used to point to the last descriptor in the
chain.*/
volatile emac_tx_bd_t * next_bd_to_process; /*Used to point to the next descriptor in
the chain to be processed.*/
} txch_t;
/**
* Helper struct to hold private data used to operate the ethernet interface.
*/
typedef struct hdkif_struct
{
/* MAC Address of the Module. */
uint8_t mac_addr[ 6 ];
/* emac base address */
uint32 emac_base;
/* emac controller base address */
volatile uint32 emac_ctrl_base;
volatile uint32 emac_ctrl_ram;
/* mdio base address */
volatile uint32 mdio_base;
/* phy parameters for this instance - for future use */
uint32 phy_addr;
boolean ( *phy_autoneg )( uint32 param1, uint32 param2, uint16 param3 );
boolean ( *phy_partnerability )( uint32 param4, uint32 param5, uint16 * param6 );
/* The tx/rx channels for the interface */
txch_t txchptr;
rxch_t rxchptr;
} hdkif_t;
/*Ethernet Frame Structure */
typedef struct ethernet_frame
{
uint8 dest_addr[ 6 ]; /* Destination MAC Address */
uint8 src_addr[ 6 ]; /*Source MAC Address. */
uint16 frame_length; /* Data Frame Length */
uint8 data[ 1500 ]; /* Data */
} ethernet_frame_t;
/* Struct used to take packet data input from the user for transmit APIs. */
typedef struct pbuf_struct
{
/** next pbuf in singly linked pbuf chain */
struct pbuf_struct * next;
/**
* Pointer to the actual ethernet packet/packet fragment to be transmitted.
* The packet needs to be in the following format:
* |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2
*bytes)| Data (46- 1500 bytes) The data can be split up over multiple pbufs which are
*linked as a linked list.
**/
uint8 * payload;
/**
* total length of this buffer and all next buffers in chain
* belonging to the same packet.
*
* For non-queue packet chains this is the invariant:
* p->tot_len == p->len + (p->next? p->next->tot_len: 0)
*/
uint16 tot_len;
/** length of this buffer */
uint16 len;
} pbuf_t;
/* Structure to hold the values of the EMAC Configuration Registers. */
typedef struct emac_config_reg_struct
{
/* EMAC Module Register Values */
uint32 TXCONTROL; /* Transmit Control Register. */
uint32 RXCONTROL; /* Receive Control Register */
uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */
uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */
uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */
uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/
uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/
uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/
/*MDIO Module Registers */
uint32 MDIOCONTROL; /*MDIO Control Register. */
/* EMAC Control Module Registers */
uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/
uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/
} emac_config_reg_t;
/*****************************************************************************/
/**
* @defgroup EMACMDIO EMAC/MDIO
* @brief Ethernet Media Access Controller/Management Data Input/Output.
*
* The EMAC controls the flow of packet data from the system to the PHY. The MDIO module
*controls PHY configuration and status monitoring.
*
* Both the EMAC and the MDIO modules interface to the system core through a custom
*interface that allows efficient data transmission and reception. This custom interface
*is referred to as the EMAC control module and is considered integral to the EMAC/MDIO
*peripheral
*
* Related Files
* - emac.h
* - emac.c
* - hw_emac.h
* - hw_emac_ctrl.h
* - hw_mdio.h
* - hw_reg_access.h
* - mdio.h
* - mdio.c
* @addtogroup EMACMDIO
* @{
*/
/*
** Prototypes for the APIs
*/
extern uint32 EMACLinkSetup( hdkif_t * hdkif );
extern void EMACInstConfig( hdkif_t * hdkif );
extern void EMACTxIntPulseEnable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACTxIntPulseDisable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACRxIntPulseEnable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACRxIntPulseDisable( uint32 emacBase,
uint32 emacCtrlBase,
uint32 ctrlCore,
uint32 channel );
extern void EMACRMIISpeedSet( uint32 emacBase, uint32 speed );
extern void EMACDuplexSet( uint32 emacBase, uint32 duplexMode );
extern void EMACTxEnable( uint32 emacBase );
extern void EMACTxDisable( uint32 emacBase );
extern void EMACRxEnable( uint32 emacBase );
extern void EMACRxDisable( uint32 emacBase );
uint32 EMACSwizzleData( uint32 word );
extern void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel );
extern void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel );
extern void EMACInit( uint32 emacCtrlBase, uint32 emacBase );
extern void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] );
extern void EMACMACAddrSet( uint32 emacBase,
uint32 channel,
uint8 macAddr[ 6 ],
uint32 matchFilt );
extern void EMACMIIEnable( uint32 emacBase );
extern void EMACMIIDisable( uint32 emacBase );
extern void EMACRxUnicastSet( uint32 emacBase, uint32 channel );
extern void EMACRxUnicastClear( uint32 emacBase, uint32 channel );
extern void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag );
extern void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr );
extern void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr );
extern void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel );
extern void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel );
extern void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel );
extern void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel );
extern void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf );
extern uint32 EMACIntVectorGet( uint32 emacBase );
uint32 EMACHWInit( uint8_t macaddr[ 6U ] );
void EMACTxTeardown( uint32 emacBase, uint32 channel );
void EMACRxTeardown( uint32 emacBase, uint32 channel );
void EMACFrameSelect( uint32 emacBase, uint64 hashTable );
void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType );
void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase );
void EMACEnableIdleState( uint32 emacBase );
void EMACDisableIdleState( uint32 emacBase );
void EMACEnableLoopback( uint32 emacBase );
void EMACDisableLoopback( uint32 emacBase );
void EMACTxFlowControlEnable( uint32 emacBase );
void EMACTxFlowControlDisable( uint32 emacBase );
void EMACRxFlowControlEnable( uint32 emacBase );
void EMACRxFlowControlDisable( uint32 emacBase );
void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold );
uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo );
void EMACDMAInit( hdkif_t * hdkif );
boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf );
void EMACTxIntHandler( hdkif_t * hdkif );
void EMACReceive( hdkif_t * hdkif );
/* Notification Function to which received packets are passed after processing */
void emacTxNotification( hdkif_t * hdkif );
void emacRxNotification( hdkif_t * hdkif );
void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat );
void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat );
void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* __EMAC_H__ */

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/**
* \file emac_phyConfig.h
*
* \brief PHY Configuration file for selecting and configuring the required PHY.
*
* This file contains the mappings of the PHY APIs so that the right one is chosen based
* on the user's preference.
*/
/* (c) Texas Instruments 2009-2014, All rights reserved. */
#ifndef _EMAC_PHYCONFIG_H_
#define _EMAC_PHYCONFIG_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "phy_dp83640.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (2) */
/* USER CODE END */
#define PhyIDGet Dp83640IDGet
#define PhyLinkStatusGet Dp83640LinkStatusGet
#define PhyAutoNegotiate Dp83640AutoNegotiate
#define PhyPartnerAbilityGet Dp83640PartnerAbilityGet
#define PhyReset Dp83640Reset
#define PhyEnableLoopback Dp83640EnableLoopback
#define PhyDisableLoopback Dp83640DisableLoopback
#define PhyGetTimeStamp Dp83640GetTimeStamp
#define PhyPartnerSpdGet Dp83640PartnerSpdGet
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _EMAC_PHYCONFIG_H_ */

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/** @file emif.h
* @brief emif Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _EMIF_H_
#define _EMIF_H_
#include "reg_emif.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum emif_pins
* @brief Alias for emif pins
*
*/
enum emif_pins
{
emif_wait_pin0 = 0U,
emif_wait_pin1 = 1U
};
/** @enum emif_size
* @brief Alias for emif page size
*
*/
enum emif_size
{
elements_256 = 0U,
elements_512 = 1U,
elements_1024 = 2U,
elements_2048 = 3U
};
/** @enum emif_port
* @brief Alias for emif port
*
*/
enum emif_port
{
emif_8_bit_port = 0U,
emif_16_bit_port = 1U
};
/** @enum emif_pagesize
* @brief Alias for emif pagesize
*
*/
enum emif_pagesize
{
emif_4_words = 0U,
emif_8_words = 1U
};
/** @enum emif_wait_polarity
* @brief Alias for emif wait polarity
*
*/
enum emif_wait_polarity
{
emif_pin_low = 0U,
emif_pin_high = 1U
};
#define PTR ( ( volatile uint32 * ) ( 0x80000000U ) )
/* Configuration registers */
typedef struct emif_config_reg
{
uint32 CONFIG_AWCC;
uint32 CONFIG_SDCR;
uint32 CONFIG_SDRCR;
uint32 CONFIG_CE2CFG;
uint32 CONFIG_CE3CFG;
uint32 CONFIG_CE4CFG;
uint32 CONFIG_CE5CFG;
uint32 CONFIG_SDTIMR;
uint32 CONFIG_SDSRETR;
uint32 CONFIG_INTMSK;
uint32 CONFIG_PMCR;
} emif_config_reg_t;
/* Configuration registers initial value for EMIF*/
#define EMIF_AWCC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) \
| ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) \
| ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) \
| ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) \
| ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) | ( uint32 ) ( ( uint32 ) 0U ) \
| ( uint32 ) 0xC0000000U )
#define EMIF_SDCR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 31U ) | ( uint32 ) ( ( uint32 ) 1U << 14U ) \
| ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) elements_256 ) )
#define EMIF_SDRCR_CONFIGVALUE 0U
#define EMIF_CE2CFG_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \
| ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \
| ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \
| ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) )
#define EMIF_CE3CFG_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \
| ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \
| ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \
| ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) )
#define EMIF_CE4CFG_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \
| ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \
| ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \
| ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) )
#define EMIF_CE5CFG_CONFIGVALUE 0x3FFFFFFDU
#define EMIF_SDTIMR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | 0x00000000U )
#define EMIF_SDSRETR_CONFIGVALUE 0U
#define EMIF_INTMSK_CONFIGVALUE 0x00000000U
#define EMIF_PMCR_CONFIGVALUE \
( 0xFC000000U | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) \
| ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \
| ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) )
/**
* @defgroup EMIF EMIF
* @brief External Memory Interface.
*
* This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories
*utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU
*to connect to a variety of external devices including:
* - Single data rate (SDR) SDRAM
* - Asynchronous devices including NOR Flash and SRAM
* The most common use for the EMIF is to interface with both a flash device and an SDRAM
*device simultaneously. contains an example of operating the EMIF in this configuration.
*
* Related Files
* - reg_emif.h
* - emif.h
* - emif.c
* @addtogroup EMIF
* @{
*/
/* EMIF Interface Functions */
void emif_SDRAMInit( void );
void emif_SDRAM_StartupInit( void );
void emif_ASYNC1Init( void );
void emif_ASYNC2Init( void );
void emif_ASYNC3Init( void );
void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /*EMIF_H_*/

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h
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/** @file epc.h
* @brief EPC Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the EPC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYS_EPC_H_
#define SYS_EPC_H_
#include "reg_epc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
enum CAMIndex
{
CAMIndex_0 = 0U,
CAMIndex_1 = 1U,
CAMIndex_2 = 2U,
CAMIndex_3 = 3U,
CAMIndex_4 = 4U,
CAMIndex_5 = 5U,
CAMIndex_6 = 6U,
CAMIndex_7 = 7U,
CAMIndex_8 = 8U,
CAMIndex_9 = 9U,
CAMIndex_10 = 10U,
CAMIndex_11 = 11U,
CAMIndex_12 = 12U,
CAMIndex_13 = 13U,
CAMIndex_14 = 14U,
CAMIndex_15 = 15U,
CAMIndex_16 = 16U,
CAMIndex_17 = 17U,
CAMIndex_18 = 18U,
CAMIndex_19 = 19U,
CAMIndex_20 = 20U,
CAMIndex_21 = 21U,
CAMIndex_22 = 22U,
CAMIndex_23 = 23U,
CAMIndex_24 = 24U,
CAMIndex_25 = 25U,
CAMIndex_26 = 26U,
CAMIndex_27 = 27U,
CAMIndex_28 = 28U,
CAMIndex_29 = 29U,
CAMIndex_30 = 30U,
CAMIndex_31 = 31U
};
/**
* @defgroup EPC EPC
* @brief Error Profiling Controller
*
* Related files:
* - reg_epc.h
* - sys_epc.h
* - sys_epc.c
*
* @addtogroup EPC
* @{
*/
void epcEnableIP1ErrorGen( void );
void epcDisableIP1ErrorGen( void );
void epcEnableIP2ErrorGen( void );
void epcDisableIP2ErrorGen( void );
void epcEnableSERREvent( void );
void epcDisableSERREvent( void );
void epcEnableInterrupt( void );
void epcDisableInterrupt( void );
void epcCAMInit( void );
boolean epcDiagnosticTest( void );
boolean epcAddCAMEEntry( uint32 address );
boolean epcCheckCAMEntry( uint32 index );
void epcCAMFullNotification( void );
void epcFIFOFullNotification( uint32 epcFIFOStatus );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* SYS_EPC_H_ */

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/** @file eqep.h
* @brief EQEP Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __eQEP_H__
#define __eQEP_H__
#include "reg_eqep.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
#define QEP_BASE_ADDR ( 0x00006B00U ) /*<base address of QEP */
/*QDECCTL Register */
#define eQEP_QDECCTL_QSRC \
( ( uint16 ) ( ( uint16 ) 3U << 14U ) ) /*<position counter source selection */
#define eQEP_QDECCTL_SOEN \
( ( uint16 ) ( ( uint16 ) 1U << 13U ) ) /*<sync output enable */
#define eQEP_QDECCTL_SPSEL \
( ( uint16 ) ( ( uint16 ) 1U << 12U ) ) /*<sync output pin selection */
#define eQEP_QDECCTL_XCR \
( ( uint16 ) ( ( uint16 ) 1U << 11U ) ) /*<external clock rate */
#define eQEP_QDECCTL_SWAP \
( ( uint16 ) ( ( uint16 ) 1U << 10U ) ) /*<swap quadrature clock inputs */
#define eQEP_QDECCTL_IGATE \
( ( uint16 ) ( ( uint16 ) 1U << 9U ) ) /*<index pulse gating option */
#define eQEP_QDECCTL_QAP \
( ( uint16 ) ( ( uint16 ) 1U << 8U ) ) /*<QEPA input polarity */
#define eQEP_QDECCTL_QBP \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<QEPB input polarity */
#define eQEP_QDECCTL_QIP \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<QEPI input polarity */
#define eQEP_QDECCTL_QSP \
( ( uint16 ) ( ( uint16 ) 1U << 5U ) ) /*<QEPS input polarity */
/*QEPCTL Register */
#define eQEP_QEPCTL_FREESOFT \
( ( uint16 ) ( ( uint16 ) 3U << 14U ) ) /*<emulation control bit */
#define eQEP_QEPCTL_PCRM \
( ( uint16 ) ( ( uint16 ) 3U << 12U ) ) /*<emulation control bit */
#define eQEP_QEPCTL_SEI \
( ( uint16 ) ( ( uint16 ) 3U << 10U ) ) /*<strobe event initialization of position \
counter */
#define eQEP_QEPCTL_IEI \
( ( uint16 ) ( ( uint16 ) 3U << 8U ) ) /*<index event initialization of position \
counter */
#define eQEP_QEPCTL_SWI \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<software initialization of position \
counter */
#define eQEP_QEPCTL_SEL \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<strobe event latch of position counter */
#define eQEP_QEPCTL_IEL \
( ( uint16 ) ( ( uint16 ) 3U << 4U ) ) /*<index event latch of position counter \
((uint16)((uint16)software index marker) \
*/
#define eQEP_QEPCTL_QPEN \
( ( uint16 ) ( ( uint16 ) 1U << 3U ) ) /*<quad position counter enable/software \
reset */
#define eQEP_QEPCTL_QCLM \
( ( uint16 ) ( ( uint16 ) 1U << 2U ) ) /*<QEP capture latch mode */
#define eQEP_QEPCTL_UTE \
( ( uint16 ) ( ( uint16 ) 1U << 1U ) ) /*<QEP unit timer enable \
*/
#define eQEP_QEPCTL_WDE \
( ( uint16 ) ( ( uint16 ) 1U << 0U ) ) /*<watchdog timer enable \
*/
/*QPOSCTL Register */
#define eQEP_QPOSCTL_PCSHDW \
( ( uint16 ) ( ( uint16 ) 1U << 15U ) ) /*<position compare shadow enable */
#define eQEP_QPOSCTL_PCLOAD \
( ( uint16 ) ( ( uint16 ) 1U << 14U ) ) /*<position compare shadow load mode */
#define eQEP_QPOSCTL_PCPOL \
( ( uint16 ) ( ( uint16 ) 1U << 13U ) ) /*<load when QPOSCNT = QPOSCMP */
#define eQEP_QPOSCTL_PCE \
( ( uint16 ) ( ( uint16 ) 1U << 12U ) ) /*<position compare enable/disable */
#define eQEP_QPOSCTL_PCSPW \
( ( uint16 ) ( ( uint16 ) 4095U << 0U ) ) /*<selection position compare sync output \
pulse width */
/*QCAPCTL Register */
#define eQEP_QCAPCTL_CEN \
( ( uint16 ) ( ( uint16 ) 1U << 15U ) ) /*<enable QEP capture */
#define eQEP_QCAPCTL_CCPS \
( ( uint16 ) ( ( uint16 ) 7U << 4U ) ) /*<qep capture timer clock prescaler */
#define eQEP_QCAPCTL_UPPS \
( ( uint16 ) ( ( uint16 ) 15U << 0U ) ) /*<unit position event prescaler */
/*QEINT Register */
#define eQEP_QEINT_UTO \
( ( uint16 ) ( ( uint16 ) 1U << 11U ) ) /*<unit timeout interrupt enable */
#define eQEP_QEINT_IEL \
( ( uint16 ) ( ( uint16 ) 1U << 10U ) ) /*<index event latch interrupt enable */
#define eQEP_QEINT_SEL \
( ( uint16 ) ( ( uint16 ) 1U << 9U ) ) /*<strobe event latch interrupt enable */
#define eQEP_QEINT_PCM \
( ( uint16 ) ( ( uint16 ) 1U << 8U ) ) /*<position compare match interrupt enable \
*/
#define eQEP_QEINT_PCR \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<position compare ready interrupt enable */
#define eQEP_QEINT_PCO \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<position counter overflow interrupt enable \
*/
#define eQEP_QEINT_PCU \
( ( uint16 ) ( ( uint16 ) 1U << 5U ) ) /*<position counter underflow interrupt \
enable */
#define eQEP_QEINT_WTO \
( ( uint16 ) ( ( uint16 ) 1U << 4U ) ) /*<watchdog time out interrupt enable */
#define eQEP_QEINT_QDC \
( ( uint16 ) ( ( uint16 ) 1U << 3U ) ) /*<quadrature direction change interrupt \
enable */
#define eQEP_QEINT_QPE \
( ( uint16 ) ( ( uint16 ) 1U << 2U ) ) /*<quadrature phase error interrupt enable */
#define eQEP_QEINT_PCE \
( ( uint16 ) ( ( uint16 ) 1U << 1U ) ) /*<position counter error interrupt enable */
/*QFLG Register */
#define eQEP_QFLG_UTO \
( ( uint16 ) ( ( uint16 ) 1U << 11U ) ) /*<unit timeout interrupt flag */
#define eQEP_QFLG_IEL \
( ( uint16 ) ( ( uint16 ) 1U << 10U ) ) /*<index event latch interrupt flag */
#define eQEP_QFLG_SEL \
( ( uint16 ) ( ( uint16 ) 1U << 9U ) ) /*<strobe event latch interrupt flag */
#define eQEP_QFLG_PCM \
( ( uint16 ) ( ( uint16 ) 1U << 8U ) ) /*<position compare match interrupt flag */
#define eQEP_QFLG_PCR \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<position compare ready interrupt flag */
#define eQEP_QFLG_PCO \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<position counter overflow interrupt flag \
*/
#define eQEP_QFLG_PCU \
( ( uint16 ) ( ( uint16 ) 1U << 5U ) ) /*<position counter underflow interrupt flag \
*/
#define eQEP_QFLG_WTO \
( ( uint16 ) ( ( uint16 ) 1U << 4U ) ) /*<watchdog time out interrupt flag */
#define eQEP_QFLG_QDC \
( ( uint16 ) ( ( uint16 ) 1U << 3U ) ) /*<quadrature direction change interrupt flag \
*/
#define eQEP_QFLG_QPE \
( ( uint16 ) ( ( uint16 ) 1U << 2U ) ) /*<quadrature phase error interrupt flag */
#define eQEP_QFLG_PCE \
( ( uint16 ) ( ( uint16 ) 1U << 1U ) ) /*<position counter error interrupt flag */
/*QCLR Register */
#define eQEP_QCLR_UTO \
( ( uint16 ) ( ( uint16 ) 1U << 11U ) ) /*<clear unit timeout interrupt flag */
#define eQEP_QCLR_IEL \
( ( uint16 ) ( ( uint16 ) 1U << 10U ) ) /*<clear index event latch interrupt flag */
#define eQEP_QCLR_SEL \
( ( uint16 ) ( ( uint16 ) 1U << 9U ) ) /*<clear strobe event latch interrupt flag */
#define eQEP_QCLR_PCM \
( ( uint16 ) ( ( uint16 ) 1U << 8U ) ) /*<clear position compare match interrupt \
flag */
#define eQEP_QCLR_PCR \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<clear position compare ready interrupt \
flag */
#define eQEP_QCLR_PCO \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<clear position counter overflow interrupt \
flag */
#define eQEP_QCLR_PCU \
( ( uint16 ) ( ( uint16 ) 1U << 5U ) ) /*<clear position counter underflow interrupt \
flag */
#define eQEP_QCLR_WTO \
( ( uint16 ) ( ( uint16 ) 1U << 4U ) ) /*<clear watchdog time out interrupt flag */
#define eQEP_QCLR_QDC \
( ( uint16 ) ( ( uint16 ) 1U << 3U ) ) /*<clear quadrature direction change \
interrupt flag */
#define eQEP_QCLR_QPE \
( ( uint16 ) ( ( uint16 ) 1U << 2U ) ) /*<clear quadrature phase error interrupt \
flag */
#define eQEP_QCLR_PCE \
( ( uint16 ) ( ( uint16 ) 1U << 1U ) ) /*<clear position counter error interrupt \
flag */
/*QFRC Register */
#define eQEP_QFRC_UTO \
( ( uint16 ) ( ( uint16 ) 1U << 11U ) ) /*<force unit timeout interrupt */
#define eQEP_QFRC_IEL \
( ( uint16 ) ( ( uint16 ) 1U << 10U ) ) /*<force index event latch interrupt */
#define eQEP_QFRC_SEL \
( ( uint16 ) ( ( uint16 ) 1U << 9U ) ) /*<force strobe event latch interrupt */
#define eQEP_QFRC_PCM \
( ( uint16 ) ( ( uint16 ) 1U << 8U ) ) /*<force position compare match interrupt */
#define eQEP_QFRC_PCR \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<force position compare ready interrupt */
#define eQEP_QFRC_PCO \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<force position counter overflow interrupt \
*/
#define eQEP_QFRC_PCU \
( ( uint16 ) ( ( uint16 ) 1U << 5U ) ) /*<force position counter underflow interrupt \
*/
#define eQEP_QFRC_WTO \
( ( uint16 ) ( ( uint16 ) 1U << 4U ) ) /*<force watchdog time out interrupt */
#define eQEP_QFRC_QDC \
( ( uint16 ) ( ( uint16 ) 1U << 3U ) ) /*<force quadrature direction change \
interrupt */
#define eQEP_QFRC_QPE \
( ( uint16 ) ( ( uint16 ) 1U << 2U ) ) /*<force quadrature phase error interrupt */
#define eQEP_QFRC_PCE \
( ( uint16 ) ( ( uint16 ) 1U << 1U ) ) /*<force position counter error interrupt */
/*QEPSTS Register */
#define eQEP_QEPSTS_UPEVNT \
( ( uint16 ) ( ( uint16 ) 1U << 7U ) ) /*<unit position event flag */
#define eQEP_QEPSTS_FDF \
( ( uint16 ) ( ( uint16 ) 1U << 6U ) ) /*<direction on the first index marker */
#define eQEP_QEPSTS_QDF \
( ( uint16 ) ( ( uint16 ) 1U << 5U ) ) /*<quadrature direction flag */
#define eQEP_QEPSTS_QDLF \
( ( uint16 ) ( ( uint16 ) 1U << 4U ) ) /*<direction latch flag \
*/
#define eQEP_QEPSTS_COEF \
( ( uint16 ) ( ( uint16 ) 1U << 3U ) ) /*<capture overflow error flag */
#define eQEP_QEPSTS_CDEF \
( ( uint16 ) ( ( uint16 ) 1U << 2U ) ) /*<capture direction error flag */
#define eQEP_QEPSTS_FIMF \
( ( uint16 ) ( ( uint16 ) 1U << 1U ) ) /*<first index marker flag */
#define eQEP_QEPSTS_PCEF \
( ( uint16 ) ( ( uint16 ) 1U << 0U ) ) /*<position counter error flag */
/*PC mode */
#define eQEP_QUADRATURE_COUNT 0x00U
#define eQEP_DIRECTION_COUNT 0x01U
#define eQEP_UP_COUNT 0x02U
#define eQEP_DOWN_COUNT 0x03U
/*External Clock Rate */
#define eQEP_RESOLUTION_2x 0x00U
#define eQEP_RESOLUTION_1x 0x01U
/*Direction */
#define eQEP_CLOCKWISE 0x01U
#define eQEP_COUNTERCLOCKWISE 0x01U
/*Edge */
#define eQEP_RISING_EDGE 0x00U
#define eQEP_FALLING_EDGE 0x01U
#define eQEP_DIRECTON_DEPENDENT 0x01U
/*Index event latch of position counter */
#define eQEP_LATCH_RISING_EDGE 0x01U
#define eQEP_LATCH_FALLING_EDGE 0x02U
#define eQEP_LATCH_SW_INDEX_MARKER 0x03U
/*Position counter reset mode */
#define eQEP_INDEX_EVENT 0x00U
#define eQEP_MAX_POSITION 0x01U
#define eQEP_FIRST_INDEX_EVENT 0x02U
#define eQEP_UNITTIME_EVENT 0x03U
/*eQEP capture timer clock prescaler and Unit position event prescaler */
#define eQEP_PS_1 0x00U
#define eQEP_PS_2 0x01U
#define eQEP_PS_4 0x02U
#define eQEP_PS_8 0x03U
#define eQEP_PS_16 0x04U
#define eQEP_PS_32 0x05U
#define eQEP_PS_64 0x06U
#define eQEP_PS_128 0x07U
#define eQEP_PS_256 0x08U
#define eQEP_PS_512 0x09U
#define eQEP_PS_1024 0x0AU
#define eQEP_PS_2048 0x0BU
/*eQEP capture latch mode */
#define eQEP_ON_POSITION_COUNTER_READ 0x00U
#define eQEP_ON_UNIT_TIMOUT_EVENT 0x01U
/*Sync output pin selection */
#define eQEP_INDEX_PIN 0x00U
#define eQEP_STROBE_PIN 0x01U
/*Position-compare shadow load mode */
#define eQEP_QPOSCNT_EQ_0 0x00U
#define eQEP_QPOSCNT_EQ_QPSCMP 0x01U
/*Polarity of sync output */
#define eQEP_ACTIVE_HIGH 0x00U
#define eQEP_ACTIVE_LOW 0x01U
/***************************************************************************
* the typedefs
*/
/** @brief QEP counting mode
*/
typedef enum
{
eQEP_Qsrc_Quad_Count_Mode = ( ( uint16 ) 0U << 14U ), /*<quadrature count mode */
eQEP_Qsrc_Dir_Count_Mode = ( ( uint16 ) 1U << 14U ), /*<direction count mode */
eQEP_Qsrc_Up_Count_Mode = ( ( uint16 ) 2U << 14U ), /*<up count mode for frequency
measurement (QCLK=XCLK,
QDIR=1U) */
eQEP_Qsrc_Down_Count_Mode = ( ( uint16 ) 3U << 14U ) /*<down count mode for frequency
measurement (QCLK=XCLK,
QDIR=0U) */
} eQEP_Qsrc_t;
/** @brief Sync output pin selection
*/
typedef enum
{
eQEP_Spsel_Index_Pin_Sync_Output = ( ( uint16 ) 0U << 12U ), /*<index pin for sync
output */
eQEP_Spsel_Strobe_Pin_Sync_Output = ( ( uint16 ) 1U << 12U ) /*<strobe pin for sync
output */
} eQEP_Spsel_t;
/** @brief External clock rate
*/
typedef enum
{
eQEP_Xcr_2x_Res = ( ( uint16 ) 0U << 11U ), /*<2x resolution: count the rising/falling
edge */
eQEP_Xcr_1x_Res = ( ( uint16 ) 1U << 11U ) /*<1x resolution: count the rising edge
only */
} eQEP_Xcr_t;
/** @brief Swap A/B channels
*/
typedef enum
{
eQEP_Swap_Not_Swapped = ( ( uint16 ) 0U << 10U ), /*<quad inputs not swapped */
eQEP_Swap_Swapped = ( ( uint16 ) 1U << 10U ) /*<quad inputs swapped */
} eQEP_Swap_t;
/** @brief Index gating
*/
typedef enum
{
eQEP_Igate_Disable = ( ( uint16 ) 0U << 9U ), /*<disable gating of index pulse */
eQEP_Igate_Enable = ( ( uint16 ) 1U << 9U ) /*<enable gating of index pulse */
} eQEP_Igate_t;
/** @brief Channel A polarity
*/
typedef enum
{
eQEP_Qap_No_Effect = ( ( uint16 ) 0U << 8U ), /*<no effect */
eQEP_Qap_Inverted = ( ( uint16 ) 1U << 8U ) /*<negates QEPA input */
} eQEP_Qap_t;
/** @brief Channel B polarity
*/
typedef enum
{
eQEP_Qbp_No_Effect = ( ( uint16 ) 0U << 7U ), /*<no effect */
eQEP_Qbp_Inverted = ( ( uint16 ) 1U << 7U ) /*<negates QEPB input */
} eQEP_Qbp_t;
/** @brief Index polarity
*/
typedef enum
{
eQEP_Qip_No_Effect = ( ( uint16 ) 0U << 6U ), /*<no effect */
eQEP_Qip_Inverted = ( ( uint16 ) 1U << 6U ) /*<negates QEPI input */
} eQEP_Qip_t;
/** @brief Channel S polarity
*/
typedef enum
{
eQEP_Qsp_No_Effect = ( ( uint16 ) 0U << 5U ), /*<no effect*/
eQEP_Qsp_Inverted = ( ( uint16 ) 1U << 5U ) /*<negates QEPS input */
} eQEP_Qsp_t;
/** @brief Emulation control bits
*/
typedef enum
{
QEPCTL_Freesoft_Immediate_Halt = ( ( uint16 ) 0U << 14U ), /*<position, watchdog, unit
timer, capture timer
stops immediately */
QEPCTL_Freesoft_Rollover_Halt = ( ( uint16 ) 1U << 14U ), /*<position, watchdog, unit
timer continues until
rollover, capture counts
until next unit period
event */
QEPCTL_Freesoft_Unaffected_Halt = ( ( uint16 ) 2U << 14U ) /*<position, watchdog, unit
timer, capture timer
unaffected by emu
suspend */
} QEPCTL_Freesoft_t;
/** @brief Position counter reset mode
*/
typedef enum
{
QEPCTL_Pcrm_Index_Reset = ( ( uint16 ) 0U << 12U ), /*<position counter reset on index
event */
QEPCTL_Pcrm_Max_Reset = ( ( uint16 ) 1U << 12U ), /*<position counter reset on max
position */
QEPCTL_Pcrm_First_Index_Reset = ( ( uint16 ) 2U << 12U ), /*<position counter reset on
first index event*/
QEPCTL_Pcrm_Unit_Time_Reset = ( ( uint16 ) 3U << 12U ) /*<position counter reset on
unit time event */
} QEPCTL_Pcrm_t;
/** @brief Strobe event initialization of position counter
*/
typedef enum
{
QEPCTL_Sei_Nothing = ( ( uint16 ) 0U << 10U ), /*<does nothing */
QEPCTL_Sei_Rising_Edge_Init = ( ( uint16 ) 2U << 10U ), /*<initializes on rising edge
of QEPS signal */
QEPCTL_Sei_Rising_Falling_Edge_Init = ( ( uint16 ) 3U << 10U ) /*<initializes on
rising/falling edge
of QEPS signal */
} QEPCTL_Sei_t;
/** @brief Index event initialization of position counter
*/
typedef enum
{
QEPCTL_Iei_Nothing = ( ( uint16 ) 0U << 8U ), /*<does nothing */
QEPCTL_Iei_Rising_Edge_Init = ( ( uint16 ) 2U << 8U ), /*<initializes on rising edge
of QEPI signal */
QEPCTL_Iei_Rising_Falling_Edge_Init = ( ( uint16 ) 3U << 8U ) /*<initializes on
falling edge of QEPI
signal */
} QEPCTL_Iei_t;
/** @brief Software initialization of position counter
*/
typedef enum
{
QEPCTL_Swi_Nothing = ( ( uint16 ) 0U << 7U ), /*<does nothing */
QEPCTL_Swi_Auto_Init_Counter = ( ( uint16 ) 1U << 7U ) /*<init position counter
(QPOSCNT=QPOSINIT) */
} QEPCTL_Swi_t;
/** @brief Strobe event latch of position counter
*/
typedef enum
{
QEPCTL_Sel_Rising_Edge = ( ( uint16 ) 0U << 6U ), /*<Position counter latched on
rising edge of QEPS strobe
(QPOSSLAT = POSCCNT) */
QEPCTL_Sel_Rising_Falling_Edge = ( ( uint16 ) 1U << 6U ) /*<Clockwise: position
counter latched on rising
edge, counter clockwise:
latched on falling edge */
} QEPCTL_Sel_t;
/** @brief Index event latch of position counter (software index marker)
*/
typedef enum
{
QEPCTL_Iel_Rising_Edge = ( ( uint16 ) 1U << 4U ), /*<latches position counter on
rising edge of index signal */
QEPCTL_Iel_Falling_Edge = ( ( uint16 ) 2U << 4U ), /*<ditto on falling edge of index
signal */
QEPCTL_Iel_Software_Index_Marker = ( ( uint16 ) 3U << 4U ) /*<software index marker.
See data sheet. */
} QEPCTL_Iel_t;
/** @brief QEP capture latch mode
*/
typedef enum
{
QEPCTL_Qclm_Latch_on_CPU_Read = ( ( uint16 ) 0U << 2U ), /*<latch on position counter
read by cpu */
QEPCTL_Qclm_Latch_on_Unit_Timeout = ( ( uint16 ) 1U << 2U ) /*<latch on unit time out
*/
} QEPCTL_Qclm_t;
/** @brief Position compare shadow enable
*/
typedef enum
{
QPOSCTL_Pcshdw_Load_Immediate = ( ( uint16 ) 0U << 15U ), /*<shadow disabled, load
immediate */
QPOSCTL_Pcshdw_Shadow_Enabled = ( ( uint16 ) 1U << 15U ) /*<shadow enabled */
} QPOSCTL_Pcshdw_t;
/** @brief Position compare shadow load mode
*/
typedef enum
{
QPOSCTL_Pcload_Load_Posn_Count_Zero = ( ( uint16 ) 0U << 14U ), /*<load on qposcnt = 0
*/
QPOSCTL_Pcload_Load_Posn_Count_Equal_Compare = ( ( uint16 ) 1U << 14U ) /*<load when
qposcnt =
qposcmp */
} QPOSCTL_Pcload_t;
/** @brief Polarity of sync output
*/
typedef enum
{
QPOSCTL_Pcpol_Active_High = ( ( uint16 ) 0U << 13U ), /*<active high pulse output */
QPOSCTL_Pcpol_Active_Low = ( ( uint16 ) 1U << 13U ) /*<active low pulse output */
} QPOSCTL_Pcpol_t;
/** @brief QEP capture timer clock prescaler
*/
typedef enum
{
QCAPCTL_Ccps_Capture_Div_1 = ( ( uint16 ) 0U << 4U ), /*<capclk = sysclkout/1 */
QCAPCTL_Ccps_Capture_Div_2 = ( ( uint16 ) 1U << 4U ), /*<capclk = sysclkout/2 */
QCAPCTL_Ccps_Capture_Div_4 = ( ( uint16 ) 2U << 4U ), /*<capclk = sysclkout/4 */
QCAPCTL_Ccps_Capture_Div_8 = ( ( uint16 ) 3U << 4U ), /*<capclk = sysclkout/8 */
QCAPCTL_Ccps_Capture_Div_16 = ( ( uint16 ) 4U << 4U ), /*<capclk = sysclkout/16 */
QCAPCTL_Ccps_Capture_Div_32 = ( ( uint16 ) 5U << 4U ), /*<capclk = sysclkout/32 */
QCAPCTL_Ccps_Capture_Div_64 = ( ( uint16 ) 6U << 4U ), /*<capclk = sysclkout/64 */
QCAPCTL_Ccps_Capture_Div_128 = ( ( uint16 ) 7U << 4U ) /*<capclk = sysclkout/128 */
} QCAPCTL_Ccps_t;
/** @brief Unit position event prescaler
*/
typedef enum
{
QCAPCTL_Upps_Div_1_Prescale = ( ( uint16 ) 0U << 0U ), /*<upevnt = qclk/1 */
QCAPCTL_Upps_Div_2_Prescale = ( ( uint16 ) 1U << 0U ), /*<upevnt = qclk/2 */
QCAPCTL_Upps_Div_4_Prescale = ( ( uint16 ) 2U << 0U ), /*<upevnt = qclk/4 */
QCAPCTL_Upps_Div_8_Prescale = ( ( uint16 ) 3U << 0U ), /*<upevnt = qclk/8 */
QCAPCTL_Upps_Div_16_Prescale = ( ( uint16 ) 4U << 0U ), /*<upevnt = qclk/16 */
QCAPCTL_Upps_Div_32_Prescale = ( ( uint16 ) 5U << 0U ), /*<upevnt = qclk/32 */
QCAPCTL_Upps_Div_64_Prescale = ( ( uint16 ) 6U << 0U ), /*<upevnt = qclk/64 */
QCAPCTL_Upps_Div_128_Prescale = ( ( uint16 ) 7U << 0U ), /*<upevnt = qclk/128 */
QCAPCTL_Upps_Div_256_Prescale = ( ( uint16 ) 8U << 0U ), /*<upevnt = qclk/256 */
QCAPCTL_Upps_Div_512_Prescale = ( ( uint16 ) 9U << 0U ), /*<upevnt = qclk/512 */
QCAPCTL_Upps_Div_1024_Prescale = ( ( uint16 ) 10U << 0U ), /*<upevnt = qclk/1024 */
QCAPCTL_Upps_Div_2048_Prescale = ( ( uint16 ) 11U << 0U ) /*<upevnt = qclk/2048 */
} QCAPCTL_Upps_t;
/** @brief QEP interrupt enable flags
*/
typedef enum
{
QEINT_Uto = ( ( uint16 ) 1U << 11U ), /*<unit time out interrupt enable */
QEINT_Iel = ( ( uint16 ) 1U << 10U ), /*<index event latch interrupt enable */
QEINT_Sel = ( ( uint16 ) 1U << 9U ), /*<strobe event latch interrupt enable */
QEINT_Pcm = ( ( uint16 ) 1U << 8U ), /*<position compare match interrupt enable */
QEINT_Pcr = ( ( uint16 ) 1U << 7U ), /*<position compare ready interrupt enable */
QEINT_Pco = ( ( uint16 ) 1U << 6U ), /*<position compare overflow interrupt enable */
QEINT_Pcu = ( ( uint16 ) 1U << 5U ), /*<position compare underflow interrupt enable */
QEINT_Wto = ( ( uint16 ) 1U << 4U ), /*<position compare watchdog time out interrupt
enable */
QEINT_Qdc = ( ( uint16 ) 1U << 3U ), /*<quadrature direction change interrupt enable
*/
QEINT_Qpe = ( ( uint16 ) 1U << 2U ), /*<quadrature phase error interrupt enable */
QEINT_Pce = ( ( uint16 ) 1U << 1U ) /*<position counter interrupt enable */
} QEINT_t;
/* Configuration registers */
typedef struct eqep_config_reg
{
uint32 CONFIG_QPOSINIT;
uint32 CONFIG_QPOSMAX;
uint32 CONFIG_QPOSCMP;
uint32 CONFIG_QUPRD;
uint16 CONFIG_QWDPRD;
uint16 CONFIG_QDECCTL;
uint16 CONFIG_QEPCTL;
uint16 CONFIG_QCAPCTL;
uint16 CONFIG_QPOSCTL;
uint16 CONFIG_QEINT;
} eqep_config_reg_t;
#define EQEP1_QPOSINIT_CONFIGVALUE ( ( uint32 ) 0x00000000U )
#define EQEP1_QPOSMAX_CONFIGVALUE ( ( uint32 ) 0x00000000U )
#define EQEP1_QPOSCMP_CONFIGVALUE ( ( uint32 ) 0x00000000U )
#define EQEP1_QUPRD_CONFIGVALUE ( ( uint32 ) 0x00000000U )
#define EQEP1_QWDPRD_CONFIGVALUE ( ( uint16 ) 0x0000U )
#define EQEP1_QDECCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) \
| ( uint16 ) ( ( uint16 ) 0U << 13U ) \
| ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) \
| ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) \
| ( uint16 ) ( ( uint16 ) 0U << 10U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) \
| ( uint16 ) ( ( uint16 ) 0U << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 6U ) \
| ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) 0x0000U ) )
#define EQEP1_QEPCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) \
| ( uint16 ) ( ( uint16 ) 0U << 11U ) \
| ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) \
| ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) \
| ( uint16 ) ( ( uint16 ) 0U << 7U ) \
| ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ << 2U ) \
| ( uint16 ) 0x0000U ) )
#define EQEP1_QCAPCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) \
| ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) | ( uint16 ) 0x0000U ) )
#define EQEP1_QPOSCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) \
| ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP << 14U ) \
| ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) \
| ( uint16 ) ( ( uint16 ) 0x000U ) | ( uint16 ) 0x0000U ) )
#define EQEP1_QEINT_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) \
| ( uint16 ) ( ( uint16 ) 0U << 10U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) \
| ( uint16 ) ( ( uint16 ) 0U << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 6U ) \
| ( uint16 ) ( ( uint16 ) 0U << 5U ) \
| ( uint16 ) ( ( uint16 ) 0U << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) \
| ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) ) )
#define EQEP2_QPOSINIT_CONFIGVALUE ( ( uint32 ) 0x00000000U )
#define EQEP2_QPOSMAX_CONFIGVALUE ( ( uint32 ) 0x00000000U )
#define EQEP2_QPOSCMP_CONFIGVALUE ( ( uint32 ) 0U )
#define EQEP2_QUPRD_CONFIGVALUE ( ( uint32 ) 0U )
#define EQEP2_QWDPRD_CONFIGVALUE ( ( uint16 ) 0U )
#define EQEP2_QDECCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) \
| ( uint16 ) ( ( uint16 ) 0U << 13U ) \
| ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) \
| ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) \
| ( uint16 ) ( ( uint16 ) 0U << 10U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) \
| ( uint16 ) ( ( uint16 ) 0U << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 6U ) \
| ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) 0x0000U ) )
#define EQEP2_QEPCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) \
| ( uint16 ) ( ( uint16 ) 0U << 11U ) \
| ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) \
| ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) \
| ( uint16 ) ( ( uint16 ) 0U << 7U ) \
| ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) \
| ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) \
| ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ << 2U ) \
| ( uint16 ) 0x0000U ) )
#define EQEP2_QCAPCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) \
| ( ( uint16 ) eQEP_PS_512 ) | ( uint16 ) 0x0000U ) )
#define EQEP2_QPOSCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) \
| ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP << 14U ) \
| ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) \
| ( uint16 ) ( ( uint16 ) 0U ) | ( uint16 ) 0x0000U ) )
#define EQEP2_QEINT_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) \
| ( uint16 ) ( ( uint16 ) 0U << 10U ) \
| ( uint16 ) ( ( uint16 ) 0U << 9U ) \
| ( uint16 ) ( ( uint16 ) 0U << 8U ) \
| ( uint16 ) ( ( uint16 ) 0U << 7U ) \
| ( uint16 ) ( ( uint16 ) 0U << 6U ) \
| ( uint16 ) ( ( uint16 ) 0U << 5U ) \
| ( uint16 ) ( ( uint16 ) 0U << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) \
| ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) ) )
/**
* @defgroup eQEP eQEP
* @brief Enhanced QEP Module.
*
* The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with
*a linear or rotary incremental encoder to get position, direction, and speed information
*from a rotating machine for use in a high-performance motion and position-control
*system. This microcontroller implements 2 instances of the eQEP module.
*
* Related Files
* - reg_eqep.h
* - eqep.h
* - eqep.c
* @addtogroup eQEP
* @{
*/
/***************************************************************************
*the function prototypes
*/
void QEPInit( void );
void eqepClearAllInterruptFlags( eqepBASE_t * eqep );
void eqepClearInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type );
void eqepClearPosnCounter( eqepBASE_t * eqep );
void eqepDisableAllInterrupts( eqepBASE_t * eqep );
void eqepDisableCapture( eqepBASE_t * eqep );
void eqepDisableGateIndex( eqepBASE_t * eqep );
void eqepDisableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type );
void eqepDisablePosnCompare( eqepBASE_t * eqep );
void eqepDisablePosnCompareShadow( eqepBASE_t * eqep );
void eqepDisableSyncOut( eqepBASE_t * eqep );
void eqepDisableUnitTimer( eqepBASE_t * eqep );
void eqepDisableWatchdog( eqepBASE_t * eqep );
void eqepEnableCapture( eqepBASE_t * eqep );
void eqepEnableCounter( eqepBASE_t * eqep );
void eqepEnableGateIndex( eqepBASE_t * eqep );
void eqepEnableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type );
void eqepEnablePosnCompare( eqepBASE_t * eqep );
void eqepEnablePosnCompareShadow( eqepBASE_t * eqep );
void eqepEnableSyncOut( eqepBASE_t * eqep );
void eqepEnableUnitTimer( eqepBASE_t * eqep );
void eqepEnableWatchdog( eqepBASE_t * eqep );
void eqepForceInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type );
uint16 eqepReadCapturePeriodLatch( eqepBASE_t * eqep );
uint16 eqepReadCaptureTimerLatch( eqepBASE_t * eqep );
uint16 eqepReadInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type );
uint32 eqepReadPosnCompare( eqepBASE_t * eqep );
uint32 eqepReadPosnCount( eqepBASE_t * eqep );
uint32 eqepReadPosnIndexLatch( eqepBASE_t * eqep );
uint32 eqepReadPosnLatch( eqepBASE_t * eqep );
uint32 eqepReadPosnStrobeLatch( eqepBASE_t * eqep );
uint16 eqepReadStatus( eqepBASE_t * eqep );
void eqepResetCounter( eqepBASE_t * eqep );
void eqepSetCaptureLatchMode( eqepBASE_t * eqep, QEPCTL_Qclm_t QEPCTL_Qclm );
void eqepSetCapturePeriod( eqepBASE_t * eqep, uint16 period );
void eqepSetCapturePrescale( eqepBASE_t * eqep, QCAPCTL_Ccps_t QCAPCTL_Ccps );
void eqepSetEmuControl( eqepBASE_t * eqep, QEPCTL_Freesoft_t QEPCTL_Freesoft );
void eqepSetExtClockRate( eqepBASE_t * eqep, eQEP_Xcr_t eQEP_Xcr );
void eqepSetIndexEventInit( eqepBASE_t * eqep, QEPCTL_Iei_t QEPCTL_Iei );
void eqepSetIndexEventLatch( eqepBASE_t * eqep, QEPCTL_Iel_t QEPCTL_Iel );
void eqepSetIndexPolarity( eqepBASE_t * eqep, eQEP_Qip_t eQEP_Qip );
void eqepSetMaxPosnCount( eqepBASE_t * eqep, uint32 max_count );
void eqepSetPosnComparePulseWidth( eqepBASE_t * eqep, uint16 pulse_width );
void eqepSetPosnCompareShadowLoad( eqepBASE_t * eqep, QPOSCTL_Pcload_t QPOSCTL_Pcload );
void eqepSetPosnCountResetMode( eqepBASE_t * eqep, QEPCTL_Pcrm_t QEPCTL_Pcrm );
void eqepSetPosnInitCount( eqepBASE_t * eqep, uint32 init_count );
void eqepSetSelectSyncPin( eqepBASE_t * eqep, eQEP_Spsel_t eQEP_SPsel );
void eqepSetSoftInit( eqepBASE_t * eqep, QEPCTL_Swi_t QEPCTL_Swi );
void eqepSetStrobeEventInit( eqepBASE_t * eqep, QEPCTL_Sei_t QEPCTL_Sei );
void eqepSetStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel );
void eqepSetStrobePolarity( eqepBASE_t * eqep, eQEP_Qsp_t eQEP_Qsp );
void eqepSetSwapQuadInputs( eqepBASE_t * eqep, eQEP_Swap_t eQEP_Swap );
void eqepSetSynchOutputComparePolarity( eqepBASE_t * eqep,
QPOSCTL_Pcpol_t QPOSCTL_Pcpol );
void eqepSetUnitPeriod( eqepBASE_t * eqep, uint32 unit_period );
void eqepSetUnitPosnPrescale( eqepBASE_t * eqep, QCAPCTL_Upps_t QCAPCTL_Upps );
void eqepSetWatchdogPeriod( eqepBASE_t * eqep, uint16 watchdog_period );
void eqepSetupStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel );
void eqepSetAPolarity( eqepBASE_t * eqep, eQEP_Qap_t eQEP_Qap );
void eqepSetBPolarity( eqepBASE_t * eqep, eQEP_Qbp_t eQEP_Qbp );
void eqepSetQEPSource( eqepBASE_t * eqep, eQEP_Qsrc_t eQEP_Qsrc );
void eqepWritePosnCompare( eqepBASE_t * eqep, uint32 posn );
/** @brief Interrupt callback
* @param[in] eqep Handle to QEP object
* @param[in] flags Copy of interrupt flags
*/
void eqepNotification( eqepBASE_t * eqep, uint16 flags );
void eqep1GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type );
void eqep2GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type );
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /*end of _eQEP_H_ definition */

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/errata.h
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/** @file errata.c
* @brief Errata workaround Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Errata workaround API's
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __errata_H__
#define __errata_H__
#include "reg_pbist.h"
#include "reg_system.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
#define PBISTERRATA_FAIL1 1U
#define PBISTERRATA_FAIL2 2U
#define PBISTERRATA_FAIL3 3U
void errata_PBIST_4( void );
void errataFailNotification( uint32 flag );
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif

48
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/errata_SSWF021_45.h
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/** @file errata_SSWF021_45.c
* @brief errata for PLLs
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef INCLUDE_ERRATA_SSWF021_45_H_
#define INCLUDE_ERRATA_SSWF021_45_H_
uint32 _errata_SSWF021_45_both_plls( uint32 count );
uint32 _errata_SSWF021_45_pll1( uint32 count );
uint32 _errata_SSWF021_45_pll2( uint32 count );
#endif /* INCLUDE_ERRATA_SSWF021_45_H_ */

204
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/errata_SSWF021_45_defs.h
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/** @file errata_SSWF021_45.c
* @brief errata for PLLs
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef INCLUDE_ERRATA_SSWF021_45_DEFS_H_
#define INCLUDE_ERRATA_SSWF021_45_DEFS_H_
typedef unsigned int uint32_t;
typedef uint32_t uint32;
typedef volatile struct systemBase1
{
uint32 SYSPC1; /* 0x0000 */
uint32 SYSPC2; /* 0x0004 */
uint32 SYSPC3; /* 0x0008 */
uint32 SYSPC4; /* 0x000C */
uint32 SYSPC5; /* 0x0010 */
uint32 SYSPC6; /* 0x0014 */
uint32 SYSPC7; /* 0x0018 */
uint32 SYSPC8; /* 0x001C */
uint32 SYSPC9; /* 0x0020 */
uint32 SSWPLL1; /* 0x0024 */
uint32 SSWPLL2; /* 0x0028 */
uint32 SSWPLL3; /* 0x002C */
uint32 CSDIS; /* 0x0030 */
uint32 CSDISSET; /* 0x0034 */
uint32 CSDISCLR; /* 0x0038 */
uint32 CDDIS; /* 0x003C */
uint32 CDDISSET; /* 0x0040 */
uint32 CDDISCLR; /* 0x0044 */
uint32 GHVSRC; /* 0x0048 */
uint32 VCLKASRC; /* 0x004C */
uint32 RCLKSRC; /* 0x0050 */
uint32 CSVSTAT; /* 0x0054 */
uint32 MSTGCR; /* 0x0058 */
uint32 MINITGCR; /* 0x005C */
uint32 MSINENA; /* 0x0060 */
uint32 MSTFAIL; /* 0x0064 */
uint32 MSTCGSTAT; /* 0x0068 */
uint32 MINISTAT; /* 0x006C */
uint32 PLLCTL1; /* 0x0070 */
uint32 PLLCTL2; /* 0x0074 */
uint32 SYSPC10; /* 0x0078 */
uint32 DIEIDL; /* 0x007C */
uint32 DIEIDH; /* 0x0080 */
uint32 VRCTL; /* 0x0084 */
uint32 LPOMONCTL; /* 0x0088 */
uint32 CLKTEST; /* 0x008C */
uint32 DFTCTRLREG1; /* 0x0090 */
uint32 DFTCTRLREG2; /* 0x0094 */
uint32 rsvd1; /* 0x0098 */
uint32 rsvd2; /* 0x009C */
uint32 GPREG1; /* 0x00A0 */
uint32 BTRMSEL; /* 0x00A4 */
uint32 IMPFASTS; /* 0x00A8 */
uint32 IMPFTADD; /* 0x00AC */
uint32 SSISR1; /* 0x00B0 */
uint32 SSISR2; /* 0x00B4 */
uint32 SSISR3; /* 0x00B8 */
uint32 SSISR4; /* 0x00BC */
uint32 RAMGCR; /* 0x00C0 */
uint32 BMMCR1; /* 0x00C4 */
uint32 BMMCR2; /* 0x00C8 */
uint32 CPURSTCR; /* 0x00CC */
uint32 CLKCNTL; /* 0x00D0 */
uint32 ECPCNTL; /* 0x00D4 */
uint32 DSPGCR; /* 0x00D8 */
uint32 DEVCR1; /* 0x00DC */
uint32 SYSECR; /* 0x00E0 */
uint32 SYSESR; /* 0x00E4 */
uint32 SYSTASR; /* 0x00E8 */
uint32 GBLSTAT; /* 0x00EC */
uint32 DEV; /* 0x00F0 */
uint32 SSIVEC; /* 0x00F4 */
uint32 SSIF; /* 0x00F8 */
} systemBASE1_t;
typedef volatile struct systemBase2
{
uint32 PLLCTL3; /* 0x0000 */
uint32 rsvd1; /* 0x0004 */
uint32 STCCLKDIV; /* 0x0008 */
uint32 rsvd2[ 6U ]; /* 0x000C */
uint32 ECPCNTRL0; /* 0x0024 */
uint32 rsvd3[ 5U ]; /* 0x0028 */
uint32 CLK2CNTL; /* 0x003C */
uint32 VCLKACON1; /* 0x0040 */
uint32 rsvd4[ 11U ]; /* 0x0044 */
uint32 CLKSLIP; /* 0x0070 */
uint32 rsvd5[ 30U ]; /* 0x0074 */
uint32 EFC_CTLEN; /* 0x00EC */
uint32 DIEIDL_REG0; /* 0x00F0 */
uint32 DIEIDH_REG1; /* 0x00F4 */
uint32 DIEIDL_REG2; /* 0x00F8 */
uint32 DIEIDH_REG3; /* 0x00FC */
} systemBASE2_t;
typedef volatile struct esmBase
{
uint32 EEPAPR1; /* 0x0000 */
uint32 DEPAPR1; /* 0x0004 */
uint32 IESR1; /* 0x0008 */
uint32 IECR1; /* 0x000C */
uint32 ILSR1; /* 0x0010 */
uint32 ILCR1; /* 0x0014 */
uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */
uint32 EPSR; /* 0x0024 */
uint32 IOFFHR; /* 0x0028 */
uint32 IOFFLR; /* 0x002C */
uint32 LTCR; /* 0x0030 */
uint32 LTCPR; /* 0x0034 */
uint32 EKR; /* 0x0038 */
uint32 SSR2; /* 0x003C */
uint32 IEPSR4; /* 0x0040 */
uint32 IEPCR4; /* 0x0044 */
uint32 IESR4; /* 0x0048 */
uint32 IECR4; /* 0x004C */
uint32 ILSR4; /* 0x0050 */
uint32 ILCR4; /* 0x0054 */
uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */
} esmBASE_t;
typedef volatile struct dccBase
{
uint32 GCTRL; /**< 0x0000: DCC Control Register */
uint32 REV; /**< 0x0004: DCC Revision Id Register */
uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */
uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */
uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */
uint32 STAT; /**< 0x0014: DCC Status Register */
uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */
uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */
uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */
uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */
uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */
} dccBASE_t;
enum dcc1clocksource
{
DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
};
#define SYS_CLKSRC_PLL1 0x00000002U
#define SYS_CLKSRC_PLL2 0x00000040U
#define SYS_CLKCNTRL_PENA 0x00000100U
#define ESM_SR1_PLL1SLIP 0x400U
#define ESM_SR4_PLL2SLIP 0x400U
#define PLL1 0x08
#define PLL2 0x80
#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
#define systemREG1 ( ( systemBASE1_t * ) 0xFFFFFF00U )
#define systemREG2 ( ( systemBASE2_t * ) 0xFFFFE100U )
#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U )
#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U )
#endif /* INCLUDE_ERRATA_SSWF021_45_DEFS_H_ */

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/** @file etpwm.h
* @brief ETPWM Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __ETPWM_H__
#define __ETPWM_H__
#include "reg_etpwm.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
#define COUNT_UP ( 1U << 13U )
#define COUNT_DOWN 0U
/** @brief Enumeration to define the pulse width modulation (ETPWM) clock divider
* TBCLK = VCLK4 / (HSPCLKDIV × CLKDIV)
*/
typedef enum
{
ClkDiv_by_1 = ( ( uint16 ) 0U << 10U ), /** CLKDIV = 1 */
ClkDiv_by_2 = ( ( uint16 ) 1U << 10U ), /** CLKDIV = 2 */
ClkDiv_by_4 = ( ( uint16 ) 2U << 10U ), /** CLKDIV = 4 */
ClkDiv_by_8 = ( ( uint16 ) 3U << 10U ), /** CLKDIV = 8 */
ClkDiv_by_16 = ( ( uint16 ) 4U << 10U ), /** CLKDIV = 16 */
ClkDiv_by_32 = ( ( uint16 ) 5U << 10U ), /** CLKDIV = 32 */
ClkDiv_by_64 = ( ( uint16 ) 6U << 10U ), /** CLKDIV = 64 */
ClkDiv_by_128 = ( ( uint16 ) 7U << 10U ) /** CLKDIV = 128 */
} etpwmClkDiv_t;
/** @brief Enumeration to define the pulse width modulation (ETPWM) high speed clock
* divider TBCLK = VCLK4 / (HSPCLKDIV × CLKDIV)
*/
typedef enum
{
HspClkDiv_by_1 = ( ( uint16 ) 0U << 7U ), /** HSPCLKDIV = 1 */
HspClkDiv_by_2 = ( ( uint16 ) 1U << 7U ), /** HSPCLKDIV = 2 */
HspClkDiv_by_4 = ( ( uint16 ) 2U << 7U ), /** HSPCLKDIV = 4 */
HspClkDiv_by_6 = ( ( uint16 ) 3U << 7U ), /** HSPCLKDIV = 8 */
HspClkDiv_by_8 = ( ( uint16 ) 4U << 7U ), /** HSPCLKDIV = 16 */
HspClkDiv_by_10 = ( ( uint16 ) 5U << 7U ), /** HSPCLKDIV = 32 */
HspClkDiv_by_12 = ( ( uint16 ) 6U << 7U ), /** HSPCLKDIV = 64 */
HspClkDiv_by_14 = ( ( uint16 ) 7U << 7U ) /** HSPCLKDIV = 128 */
} etpwmHspClkDiv_t;
/** @brief Enumeration to select the source of Synchronization Output signal (EPWMxSYNCO)
*/
typedef enum
{
SyncOut_EPWMxSYNCI = 0x00U, /** EPWMxSYNCI */
SyncOut_CtrEqZero = 0x10U, /** CTR = zero */
SyncOut_CtrEqCmpB = 0x20U, /** CTR = CMPB */
SyncOut_Disable = 0x30U /** Disable EPWMxSYNCO signal */
} etpwmSyncOut_t;
/** @brief Enumeration to define the pulse width modulation (ETPWM) counter modes
*/
typedef enum
{
CounterMode_Up = 0U, /** Up-count mode */
Countermode_Down = 1U, /** Down-count mode */
CounterMode_UpDown = 2U, /** Up-down-count mode */
CounterMode_Stop = 3U /** Stop - freeze counter operaton */
} etpwmCounterMode_t;
/** @brief Enumeration to the behavior of the ePWM time-base counter during emulation
* events
*/
typedef enum
{
RunMode_SoftStopAfterIncr = ( ( uint16 ) 0U << 14U ), /** Stop after the next
time-base counter increment
*/
RunMode_SoftStopAfterDecr = ( ( uint16 ) 0U << 14U ), /** Stop after the next
time-base counter decrement
*/
RunMode_SoftStopAfterCycle = ( ( uint16 ) 1U << 14U ), /** Stop when counter completes
a whole cycle */
RunMode_FreeRun = ( ( uint16 ) 2U << 14U ) /** Free run */
} etpwmRunMode_t;
/** @brief Enumeration to define the pulse width modulation (ETPWM) load modes
*/
typedef enum
{
LoadMode_CtrEqZero = 0U, /** Load on CTR = Zero */
LoadMode_CtrEqPeriod = 1U, /** Load on CTR = PRD */
LoadMode_CtrEqZeroPeriod = 2U, /** Load on CTR = Zero or CTR = PRD */
LoadMode_Freeze = 3U /** Freeze (no loads possible) */
} etpwmLoadMode_t;
/** @brief Enumeration to define the pulse width modulation (ETPWM) trip zone sources
*/
typedef enum
{
CycleByCycle_TZ1 = ( ( uint16 ) 1U << 0U ),
CycleByCycle_TZ2 = ( ( uint16 ) 1U << 1U ),
CycleByCycle_TZ3 = ( ( uint16 ) 1U << 2U ),
CycleByCycle_TZ4 = ( ( uint16 ) 1U << 3U ),
CycleByCycle_TZ5 = ( ( uint16 ) 1U << 4U ),
CycleByCycle_TZ6 = ( ( uint16 ) 1U << 5U ),
CycleByCycle_DCAEVT2 = ( ( uint16 ) 1U << 6U ),
CycleByCycle_DCBEVT2 = ( ( uint16 ) 1U << 7U ),
OneShot_TZ1 = ( ( uint16 ) 1U << 8U ),
OneShot_TZ2 = ( ( uint16 ) 1U << 9U ),
OneShot_TZ3 = ( ( uint16 ) 1U << 10U ),
OneShot_TZ4 = ( ( uint16 ) 1U << 11U ),
OneShot_TZ5 = ( ( uint16 ) 1U << 12U ),
OneShot_TZ6 = ( ( uint16 ) 1U << 13U ),
OneShot_DCAEVT1 = ( ( uint16 ) 1U << 14U ),
OneShot_DCBEVT1 = ( ( uint16 ) 1U << 15U )
} etpwmTripZoneSrc_t;
/** @brief Enumeration to define the pulse width modulation (ETPWM) trip events
*/
typedef enum
{
CycleByCycleTrip = ( ( uint16 ) 1U << 1U ), /** Trip Zone Cycle-By-Cycle */
OneShotTrip = ( ( uint16 ) 1U << 2U ), /** TripZone One-shot */
DCAEVT1_inter = ( ( uint16 ) 1U << 3U ), /** Digital Comparator Output A Event 1 */
DCAEVT2_inter = ( ( uint16 ) 1U << 4U ), /** Digital Comparator Output A Event 2 */
DCBEVT1_inter = ( ( uint16 ) 1U << 5U ), /** Digital Comparator Output B Event 1 */
DCBEVT2_inter = ( ( uint16 ) 1U << 6U ) /** Digital Comparator Output B Event 2 */
} etpwmTrip_t;
/** @brief Enumeration to define the sources for EPWMx_INT, SOCA or SOCB
*/
typedef enum
{
NO_EVENT = 0U, /** Reserved */
DCAEVT1 = 0U, /** DCAEVT1.soc event */
DCBEVT1 = 0U, /** DCBEVT1.soc event */
CTR_ZERO = 1U, /** Event CTR = Zero */
CTR_PRD = 2U, /** Event CTR = PRD */
CTR_ZERO_PRD = 3U, /** Event CTR = Zero or CTR = PRD */
CTR_UP_CMPA = 4U, /** Event CTR = CMPA when when the timer is incrementing */
CTR_D0WM_CMPA = 5U, /** Event CTR = CMPA when when the timer is decrementing */
CTR_UP_CMPB = 6U, /** Event CTR = CMPB when when the timer is incrementing */
CTR_D0WM_CMPB = 7U /** Event CTR = CMPB when when the timer is decrementing */
} etpwmEventSrc_t;
/** @brief Enumeration to define the period of EPWMx_INT, SOCA or SOCB
*/
typedef enum
{
EventPeriod_Disable = 0U, /** Disable EPWMx_INT/SOCA/SOCB event counter */
EventPeriod_FirstEvent = 1U, /** Generate EPWMx_INT/SOCA/SOCB pulse on the first event
*/
EventPeriod_SecondEvent = 2U, /** Generate EPWMx_INT/SOCA/SOCB pulse on the second
event */
EventPeriod_ThirdEvent = 3U /** Generate EPWMx_INT/SOCA/SOCB pulse on the third event
*/
} etpwmEventPeriod_t;
/** @brief Enumeration to define the output events from ETPWMx
*/
typedef enum
{
Event_Interrupt = 1U, /** EPWM Interrupt */
Event_SOCA = 4U, /** Start Of Conversion A */
Event_SOCB = 8U /** Start Of conversion B */
} etpwmEvent_t;
/** @brief Enumeration to define the pulse width modulation (ETPWM) action qualifiers
*
* @note This enum should be use to populate the struct passed as the parameter
* to the APIs etpwmSetActionQualPwmA and etpwmSetActionQualPwmB
*/
typedef enum
{
ActionQual_Disabled = 0U, /** Do nothing (action disabled) */
ActionQual_Clear = 1U, /** Clear: force EPTWMxA/ETPWMB output low */
ActionQual_Set = 2U, /** Set: force ETPWMxA/ETPWMxB output high */
ActionQual_Toggle = 3U, /** Toggle EPWMxA/ETPWMxB output */
ForceSize_ActionQual = 0xFFFFU /** Do not use (Makes sure that etpwmActionQual_t is at
least 16 bits wide) */
} etpwmActionQual_t;
/** @brief Enumeration to define the DeadBand input mode
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableDeadBand
*/
typedef enum
{
PWMA_RED_FED = 0x00U, /** Source of Rising edge delay: ETPWMxA, Source of Falling edge
delay: ETPWMxA */
PWMA_FED_PWMB_RED = 0x10U, /** Source of Rising edge delay: ETPWMxB, Source of Falling
edge delay: ETPWMxA */
PWMA_RED_PWMB_FED = 0x20U, /** Source of Rising edge delay: ETPWMxA, Source of Falling
edge delay: ETPWMxB */
PWMB_RED_FED = 0x30U, /** Source of Rising edge delay: ETPWMxB, Source of Falling edge
delay: ETPWMxB */
ForceSize_DBInput = 0xFFFFU /** Do not use (Makes sure that etpwmDeadBandInputMode_t
is at least 16 bits wide) */
} etpwmDeadBandInputMode_t;
/** @brief Enumeration to define the DeadBand output mode
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableDeadBand
*/
typedef enum
{
PWMA_PWMB_NIL = 0U, /** Deadband generation is bypassed for both output signals */
PWMA_NIL_PWMB_FED = 1U, /** Disable rising-edge delay. The falling-edge delayed signal
is seen on output EPWMxB. */
PWMA_RED_PWMB_NIL = 2U, /** Disable falling-edge delay. The rising-edge delayed signal
is seen on output EPWMxA. */
PWMB_FED_PWMA_RED = 3U, /** Rising-edge delayed signal on output EPWMxA and
falling-edge delayed signal on output EPWMxB. */
ForceSize_DBOutput = 0xFFFFU /** Do not use (Makes sure that etpwmDeadBandOutputMode_t
is at least 16 bits wide) */
} etpwmDeadBandOutputMode_t;
/** @brief Enumeration to define the DeadBand polarity
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableDeadBand
*
*/
typedef enum
{
DisableInvert = ( ( uint16 ) 0U << 2U ), /** Neither EPWMxA nor EPWMxB is inverted */
Invert_PWMA = ( ( uint16 ) 1U << 2U ), /** EPWMxA is inverted */
Invert_PWMB = ( ( uint16 ) 2U << 2U ), /** EPWMxB is inverted */
Invert_PWMA_PWMB = ( ( uint16 ) 3U << 2U ), /** Both EPWMxA and EPWMxB are inverted */
ForceSize_DBPol = 0xFFFFU /** Do not use (Makes sure that etpwmDeadBandPolarity_t is
at least 16 bits wide) */
} etpwmDeadBandPolarity_t;
/** @brief Enumeration to define the action on EPWMA/EPWMB when a trip event happens
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmSetTripAction
*
*/
typedef enum
{
TripZoneState_HighImp = 0U, /** High-Impedance state */
TripZoneState_EPWM_High = 1U, /** Force to High state */
TripZoneState_EPWM_Low = 2U, /** Force to Low state */
TripZoneState_DoNothing = 3U, /** Do nothing */
ForceSize_TripZoneState = 0xFFFFU /** Do not use (Makes sure that etpwmTripZoneState_t
is at least 16 bits wide) */
} etpwmTripZoneState_t;
/** @brief Enumeration to define One-Shot Pulse Width in chopper submodule
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableChopping
*
*/
typedef enum
{
ChoppingPulseWidth_8_VCLK4 = ( ( uint16 ) 0U << 1U ), /** 1 x VCLK4/8 wide */
ChoppingPulseWidth_16_VCLK4 = ( ( uint16 ) 1U << 1U ), /** 2 x VCLK4/8 wide */
ChoppingPulseWidth_24_VCLK4 = ( ( uint16 ) 2U << 1U ), /** 3 x VCLK4/8 wide */
ChoppingPulseWidth_32_VCLK4 = ( ( uint16 ) 3U << 1U ), /** 4 x VCLK4/8 wide */
ChoppingPulseWidth_40_VCLK4 = ( ( uint16 ) 4U << 1U ), /** 5 x VCLK4/8 wide */
ChoppingPulseWidth_48_VCLK4 = ( ( uint16 ) 5U << 1U ), /** 6 x VCLK4/8 wide */
ChoppingPulseWidth_56_VCLK4 = ( ( uint16 ) 6U << 1U ), /** 7 x VCLK4/8 wide */
ChoppingPulseWidth_64_VCLK4 = ( ( uint16 ) 7U << 1U ), /** 8 x VCLK4/8 wide */
ChoppingPulseWidth_72_VCLK4 = ( ( uint16 ) 8U << 1U ), /** 9 x VCLK4/8 wide */
ChoppingPulseWidth_80_VCLK4 = ( ( uint16 ) 9U << 1U ), /** 10 x VCLK4/8 wide */
ChoppingPulseWidth_88_VCLK4 = ( ( uint16 ) 10U << 1U ), /** 11 x VCLK4/8 wide */
ChoppingPulseWidth_96_VCLK4 = ( ( uint16 ) 11U << 1U ), /** 12 x VCLK4/8 wide */
ChoppingPulseWidth_104_VCLK4 = ( ( uint16 ) 12U << 1U ), /** 13 x VCLK4/8 wide */
ChoppingPulseWidth_112_VCLK4 = ( ( uint16 ) 13U << 1U ), /** 14 x VCLK4/8 wide */
ChoppingPulseWidth_120_VCLK4 = ( ( uint16 ) 14U << 1U ), /** 15 x VCLK4/8 wide */
ChoppingPulseWidth_128_VCLK4 = ( ( uint16 ) 15U << 1U ), /** 16 x VCLK4/8 wide */
ForceSize_ChopPulseWidth = 0xFFFFU /** Do not use (Makes sure that
etpwmChoppingPulseWidth_t is at least 16 bits
wide) */
} etpwmChoppingPulseWidth_t;
/** @brief Enumeration to define Chopping Clock Frequency
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableChopping
*
*/
typedef enum
{
ChoppingClkFreq_VCLK4_by_8 = ( ( uint16 ) 0U << 5U ), /** VCLK4/8 divided by 1 */
ChoppingClkFreq_VCLK4_by_16 = ( ( uint16 ) 1U << 5U ), /** VCLK4/8 divided by 2 */
ChoppingClkFreq_VCLK4_by_24 = ( ( uint16 ) 2U << 5U ), /** VCLK4/8 divided by 3 */
ChoppingClkFreq_VCLK4_by_32 = ( ( uint16 ) 3U << 5U ), /** VCLK4/8 divided by 4 */
ChoppingClkFreq_VCLK4_by_40 = ( ( uint16 ) 4U << 5U ), /** VCLK4/8 divided by 5 */
ChoppingClkFreq_VCLK4_by_48 = ( ( uint16 ) 5U << 5U ), /** VCLK4/8 divided by 6 */
ChoppingClkFreq_VCLK4_by_56 = ( ( uint16 ) 6U << 5U ), /** VCLK4/8 divided by 7 */
ChoppingClkFreq_VCLK4_by_64 = ( ( uint16 ) 7U << 5U ), /** VCLK4/8 divided by 8 */
ForceSize_ChopClkFreq = 0xFFFFU /** Do not use (Makes sure that etpwmChoppingClkFreq_t
is at least 16 bits wide) */
} etpwmChoppingClkFreq_t;
/** @brief Enumeration to define Chopping Clock duty cycle
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableChopping
*
*/
typedef enum
{
ChoppingDutyCycle_One_Eighth = 0x0000U, /** Duty = 1/8 (12.5%) */
ChoppingDutyCycle_Two_Eighths = 0x0100U, /** Duty = 2/8 (25.0%) */
ChoppingDutyCycle_Three_Eighths = 0x0200U, /** Duty = 3/8 (37.5%) */
ChoppingDutyCycle_Four_Eighths = 0x0300U, /** Duty = 4/8 (50.0%) */
ChoppingDutyCycle_Five_Eighths = 0x0400U, /** Duty = 5/8 (62.5%) */
ChoppingDutyCycle_Six_Eighths = 0x0500U, /** Duty = 6/8 (75.0%) */
ChoppingDutyCycle_Seven_Eighths = 0x0600U, /** Duty = 7/8 (87.5%) */
ForceSize_ChopDuty = 0xFFFFU /** Do not use (Makes sure that etpwmChoppingDutyCycle_t
is at least 16 bits wide) */
} etpwmChoppingDutyCycle_t;
/** @brief Enumeration to define Digital Compare Input
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableDigitalCompareEvents
*
*/
typedef enum
{
TZ1 = 0U,
TZ2 = 1U,
TZ3 = 2U,
ForceSize_DCInput = 0xFFFFU /** Do not use (Makes sure that etpwmDCInput_t is at least
16 bits wide) */
} etpwmDCInput_t;
/** @brief Enumeration to define Digital Compare Output selection
*
* @note This enum should be use to populate the struct passed as the parameter
* to the API etpwmEnableDigitalCompareEvents.
* @note DCAH_Low, DCAH_High, DCAL_Low, DCAL_High, DCAL_High_DCAH_Low should be used
* only for selecting DCAEVT1_event and DCAEVT2_event and DCBH_Low, DCBH_High, DCBL_Low,
* DCBL_High, DCBL_High_DCBH_Low should be used only for selecting DCBEVT1_event and
* DCBEVT2_event
*
*/
typedef enum
{
Event_Disabled = 0U, /** Event Disabled */
DCAH_Low = 1U, /** DCAEVTx selection : DCAH = low, DCAL = don't care */
DCAH_High = 2U, /** DCAEVTx selection : DCAH = high, DCAL = don't care */
DCAL_Low = 3U, /** DCAEVTx selection : DCAL = low, DCAH = don't care */
DCAL_High = 4U, /** DCAEVTx selection : DCAL = high, DCAH = don't care */
DCAL_High_DCAH_Low = 5U, /** DCAEVTx selection : DCAL = high, DCAH = low */
DCBH_Low = 1U, /** DCBEVTx selection : DCBH = low, DCBL = don't care */
DCBH_High = 2U, /** DCBEVTx selection : DCBH = high, DCBL = don't care */
DCBL_Low = 3U, /** DCBEVTx selection : DCBL = low, DCBH = don't care */
DCBL_High = 4U, /** DCBEVTx selection : DCBL = high, DCBH = don't care */
DCBL_High_DCBH_low = 5U, /** DCBEVTx selection : DCBL = high, DCBH = low */
ForceSize_DCSelect = 0xFFFFU /** Do not use (Makes sure that etpwmDCInput_t is at
least 16 bits wide) */
} etpwmDCOutputSelect_t;
/** @brief ETPWMx Action Qualifier configuration
*/
typedef struct
{
etpwmActionQual_t CtrEqZero_Action;
etpwmActionQual_t CtrEqPeriod_Action;
etpwmActionQual_t CtrEqCmpAUp_Action;
etpwmActionQual_t CtrEqCmpADown_Action;
etpwmActionQual_t CtrEqCmpBUp_Action;
etpwmActionQual_t CtrEqCmpBDown_Action;
} etpwmActionQualConfig_t;
/** @brief ETPWMx Deadband configuration
*/
typedef struct
{
etpwmDeadBandInputMode_t inputmode;
etpwmDeadBandOutputMode_t outputmode;
etpwmDeadBandPolarity_t polarity;
boolean halfCycleEnable;
} etpwmDeadBandConfig_t;
/** @brief ETPWMx Chopper configuration
*/
typedef struct
{
etpwmChoppingPulseWidth_t oswdth;
etpwmChoppingClkFreq_t freq;
etpwmChoppingDutyCycle_t duty;
} etpwmChoppingConfig_t;
/** @brief ETPWMx Trip action configuration
*/
typedef struct
{
etpwmTripZoneState_t TripEvent_ActionOnPWMA;
etpwmTripZoneState_t TripEvent_ActionOnPWMB;
etpwmTripZoneState_t DCAEVT1_ActionOnPWMA;
etpwmTripZoneState_t DCAEVT2_ActionOnPWMA;
etpwmTripZoneState_t DCBEVT1_ActionOnPWMB;
etpwmTripZoneState_t DCBEVT2_ActionOnPWMB;
} etpwmTripActionConfig_t;
/** @brief ETPWMx Digital Compare configuration
*/
typedef struct
{
etpwmDCInput_t DCAH_src;
etpwmDCInput_t DCAL_src;
etpwmDCInput_t DCBH_src;
etpwmDCInput_t DCBL_src;
etpwmDCOutputSelect_t DCAEVT1_event;
etpwmDCOutputSelect_t DCAEVT2_event;
etpwmDCOutputSelect_t DCBEVT1_event;
etpwmDCOutputSelect_t DCBEVT2_event;
} etpwmDigitalCompareConfig_t;
typedef struct etpwm_config_reg
{
uint16 CONFIG_TBCTL;
uint16 CONFIG_TBPHS;
uint16 CONFIG_TBPRD;
uint16 CONFIG_CMPCTL;
uint16 CONFIG_CMPA;
uint16 CONFIG_CMPB;
uint16 CONFIG_AQCTLA;
uint16 CONFIG_AQCTLB;
uint16 CONFIG_DBCTL;
uint16 CONFIG_DBRED;
uint16 CONFIG_DBFED;
uint16 CONFIG_TZSEL;
uint16 CONFIG_TZDCSEL;
uint16 CONFIG_TZCTL;
uint16 CONFIG_TZEINT;
uint16 CONFIG_ETSEL;
uint16 CONFIG_ETPS;
uint16 CONFIG_PCCTL;
uint16 CONFIG_DCTRIPSEL;
uint16 CONFIG_DCACTL;
uint16 CONFIG_DCBCTL;
uint16 CONFIG_DCFCTL;
uint16 CONFIG_DCCAPCTL;
uint16 CONFIG_DCFWINDOW;
uint16 CONFIG_DCFWINDOWCNT;
} etpwm_config_reg_t;
#define ETPWM1_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM1_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM1_TBPRD_CONFIGVALUE 1000U
#define ETPWM1_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM1_CMPA_CONFIGVALUE 50U
#define ETPWM1_CMPB_CONFIGVALUE 50U
#define ETPWM1_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM1_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM1_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM1_DBRED_CONFIGVALUE 1U
#define ETPWM1_DBFED_CONFIGVALUE 1U
#define ETPWM1_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM1_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM1_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM1_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM1_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM1_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM1_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM1_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM1_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM1_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM1_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM1_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM1_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM1_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
#define ETPWM2_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM2_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM2_TBPRD_CONFIGVALUE 1000U
#define ETPWM2_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM2_CMPA_CONFIGVALUE 50U
#define ETPWM2_CMPB_CONFIGVALUE 50U
#define ETPWM2_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM2_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM2_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM2_DBRED_CONFIGVALUE 1U
#define ETPWM2_DBFED_CONFIGVALUE 1U
#define ETPWM2_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM2_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM2_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM2_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM2_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM2_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM2_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM2_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM2_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM2_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM2_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM2_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM2_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM2_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
#define ETPWM3_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM3_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM3_TBPRD_CONFIGVALUE 1000U
#define ETPWM3_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM3_CMPA_CONFIGVALUE 50U
#define ETPWM3_CMPB_CONFIGVALUE 50U
#define ETPWM3_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM3_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM3_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM3_DBRED_CONFIGVALUE 1U
#define ETPWM3_DBFED_CONFIGVALUE 1U
#define ETPWM3_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM3_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM3_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM3_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM3_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM3_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM3_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM3_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM3_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM3_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM3_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM3_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM3_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM3_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
#define ETPWM4_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM4_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM4_TBPRD_CONFIGVALUE 1000U
#define ETPWM4_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM4_CMPA_CONFIGVALUE 50U
#define ETPWM4_CMPB_CONFIGVALUE 50U
#define ETPWM4_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM4_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM4_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM4_DBRED_CONFIGVALUE 1U
#define ETPWM4_DBFED_CONFIGVALUE 1U
#define ETPWM4_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM4_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM4_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM4_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM4_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM4_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM4_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM4_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM4_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM4_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM4_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM4_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM4_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM4_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
#define ETPWM5_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM5_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM5_TBPRD_CONFIGVALUE 1000U
#define ETPWM5_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM5_CMPA_CONFIGVALUE 50U
#define ETPWM5_CMPB_CONFIGVALUE 50U
#define ETPWM5_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM5_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM5_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM5_DBRED_CONFIGVALUE 1U
#define ETPWM5_DBFED_CONFIGVALUE 1U
#define ETPWM5_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM5_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM5_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM5_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM5_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM5_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM5_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM5_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM5_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM5_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM5_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM5_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM5_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM5_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
#define ETPWM6_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM6_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM6_TBPRD_CONFIGVALUE 1000U
#define ETPWM6_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM6_CMPA_CONFIGVALUE 50U
#define ETPWM6_CMPB_CONFIGVALUE 50U
#define ETPWM6_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM6_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM6_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM6_DBRED_CONFIGVALUE 1U
#define ETPWM6_DBFED_CONFIGVALUE 1U
#define ETPWM6_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM6_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM6_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM6_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM6_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM6_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM6_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM6_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM6_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM6_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM6_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM6_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM6_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM6_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
#define ETPWM7_TBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 7U ) | ( uint16 ) ( ( uint16 ) 0U << 10U ) )
#define ETPWM7_TBPHS_CONFIGVALUE 0x00000000U
#define ETPWM7_TBPRD_CONFIGVALUE 1000U
#define ETPWM7_CMPCTL_CONFIGVALUE 0x00000000U
#define ETPWM7_CMPA_CONFIGVALUE 50U
#define ETPWM7_CMPB_CONFIGVALUE 50U
#define ETPWM7_AQCTLA_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) )
#define ETPWM7_AQCTLB_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) \
| ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) )
#define ETPWM7_DBCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 5U ) | ( uint16 ) ( ( uint16 ) 0u << 4U ) \
| ( uint16 ) ( ( uint16 ) 0U << 3U ) | ( uint16 ) ( ( uint16 ) 0U << 2U ) \
| ( uint16 ) ( ( uint16 ) 0U << 1U ) | ( uint16 ) ( ( uint16 ) 0U << 0U ) )
#define ETPWM7_DBRED_CONFIGVALUE 1U
#define ETPWM7_DBFED_CONFIGVALUE 1U
#define ETPWM7_TZSEL_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U \
| 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM7_TZDCSEL_CONFIGVALUE 0x00000000U
#define ETPWM7_TZCTL_CONFIGVALUE 0x00000000U
#define ETPWM7_TZEINT_CONFIGVALUE \
( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U )
#define ETPWM7_ETSEL_CONFIGVALUE \
( ( ( ( uint16 ) NO_EVENT == 0U ) ? 0x0000U : 0x0008U ) | ( uint16 ) NO_EVENT \
| ( uint16 ) 0x0000U | ( uint16 ) 0x0000U \
| ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) \
| ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) )
#define ETPWM7_ETPS_CONFIGVALUE \
( 1U | ( uint16 ) ( ( uint16 ) 1U << 8U ) | ( uint16 ) ( ( uint16 ) 1U << 12U ) )
#define ETPWM7_PCCTL_CONFIGVALUE \
( ( uint16 ) ( ( uint16 ) 0U << 0U ) | ( uint16 ) ( ( uint16 ) 1U << 1U ) \
| ( uint16 ) ( ( uint16 ) 3U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 5U ) )
#define ETPWM7_DCTRIPSEL_CONFIGVALUE 0x00000000U
#define ETPWM7_DCACTL_CONFIGVALUE 0x00000000U
#define ETPWM7_DCBCTL_CONFIGVALUE 0x00000000U
#define ETPWM7_DCFCTL_CONFIGVALUE 0x00000000U
#define ETPWM7_DCCAPCTL_CONFIGVALUE 0x00000000U
#define ETPWM7_DCFWINDOW_CONFIGVALUE 0x00000000U
#define ETPWM7_DCFWINDOWCNT_CONFIGVALUE 0x00000000U
/**
* @defgroup ePWM ePWM
* @brief Enhanced Pulse Width Modulator.
*
* The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling
* many of the power electronic systems found in both commercial and industrial
* equipments. The features supported by the ePWM make it especially suitable for digital
* motor control.
*
* Related Files
* - reg_etpwm.h
* - etpwm.h
* - etpwm.c
* @addtogroup ePWM
* @{
*/
void etpwmInit( void );
void etpwmStartTBCLK( void );
void etpwmStopTBCLK( void );
void etpwmSetClkDiv( etpwmBASE_t * etpwm,
etpwmClkDiv_t clkdiv,
etpwmHspClkDiv_t hspclkdiv );
void etpwmSetTimebasePeriod( etpwmBASE_t * etpwm, uint16 period );
void etpwmSetCount( etpwmBASE_t * etpwm, uint16 count );
void etpwmDisableTimebasePeriodShadowMode( etpwmBASE_t * etpwm );
void etpwmEnableTimebasePeriodShadowMode( etpwmBASE_t * etpwm );
void etpwmEnableCounterLoadOnSync( etpwmBASE_t * etpwm, uint16 phase, uint16 direction );
void etpwmDisableCounterLoadOnSync( etpwmBASE_t * etpwm );
void etpwmSetSyncOut( etpwmBASE_t * etpwm, etpwmSyncOut_t syncOutSrc );
void etpwmSetCounterMode( etpwmBASE_t * etpwm, etpwmCounterMode_t countermode );
void etpwmTriggerSWSync( etpwmBASE_t * etpwm );
void etpwmSetRunMode( etpwmBASE_t * etpwm, etpwmRunMode_t runmode );
void etpwmSetCmpA( etpwmBASE_t * etpwm, uint16 value );
void etpwmSetCmpB( etpwmBASE_t * etpwm, uint16 value );
void etpwmEnableCmpAShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode );
void etpwmDisableCmpAShadowMode( etpwmBASE_t * etpwm );
void etpwmEnableCmpBShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode );
void etpwmDisableCmpBShadowMode( etpwmBASE_t * etpwm );
void etpwmSetActionQualPwmA( etpwmBASE_t * etpwm,
etpwmActionQualConfig_t actionqualconfig );
void etpwmSetActionQualPwmB( etpwmBASE_t * etpwm,
etpwmActionQualConfig_t actionqualconfig );
void etpwmEnableDeadBand( etpwmBASE_t * etpwm, etpwmDeadBandConfig_t deadbandconfig );
void etpwmDisableDeadband( etpwmBASE_t * etpwm );
void etpwmSetDeadBandDelay( etpwmBASE_t * etpwm, uint16 Rdelay, uint16 Fdelay );
void etpwmEnableChopping( etpwmBASE_t * etpwm, etpwmChoppingConfig_t choppingconfig );
void etpwmDisableChopping( etpwmBASE_t * etpwm );
void etpwmEnableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources );
void etpwmDisableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources );
void etpwmSetTripAction( etpwmBASE_t * etpwm, etpwmTripActionConfig_t tripactionconfig );
void etpwmEnableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts );
void etpwmDisableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts );
void etpwmClearTripCondition( etpwmBASE_t * etpwm, etpwmTrip_t trips );
void etpwmClearTripInterruptFlag( etpwmBASE_t * etpwm );
void etpwmForceTripEvent( etpwmBASE_t * etpwm, etpwmTrip_t trip );
void etpwmEnableSOCA( etpwmBASE_t * etpwm,
etpwmEventSrc_t eventsource,
etpwmEventPeriod_t eventperiod );
void etpwmDisableSOCA( etpwmBASE_t * etpwm );
void etpwmEnableSOCB( etpwmBASE_t * etpwm,
etpwmEventSrc_t eventsource,
etpwmEventPeriod_t eventperiod );
void etpwmDisableSOCB( etpwmBASE_t * etpwm );
void etpwmEnableInterrupt( etpwmBASE_t * etpwm,
etpwmEventSrc_t eventsource,
etpwmEventPeriod_t eventperiod );
void etpwmDisableInterrupt( etpwmBASE_t * etpwm );
uint16 etpwmGetEventStatus( etpwmBASE_t * etpwm );
void etpwmClearEventFlag( etpwmBASE_t * etpwm, etpwmEvent_t events );
void etpwmTriggerEvent( etpwmBASE_t * etpwm, etpwmEvent_t events );
void etpwmEnableDigitalCompareEvents( etpwmBASE_t * etpwm,
etpwmDigitalCompareConfig_t digitalcompareconfig );
void etpwm1GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
void etpwm2GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
void etpwm3GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
void etpwm4GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
void etpwm5GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
void etpwm6GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
void etpwm7GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type );
/** @brief Notification for ETPWMx Interrupts
* @param[in] node The pulse width modulation (ETPWM) object handle
*/
void etpwmNotification( etpwmBASE_t * node );
/** @brief Notification for ETPWM Trip zone Interrupts
* @param[in] node The pulse width modulation (ETPWM) object handle
* @param[in] flags Event and Interrupt flag.
*/
void etpwmTripNotification( etpwmBASE_t * node, uint16 flags );
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif /* end of _ETPWM_H_ definition */

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/**********************************************************************************************************************
* FILE DESCRIPTION
*
-------------------------------------------------------------------------------------------------------------------
* File: fee_interface.h
* Project: Tms570_TIFEEDriver
* Module: FEE Driver
* Generator: None
*
* Description: This file is interfce between Autosar FEE and TI FEE.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 00.01.00 07Sept2012 Vishwanath Reddy 0000000000000 Initial Version
* 00.01.01 14Sept2012 Vishwanath Reddy 0000000000000 Review changes
* 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory
segmentation changes.
* 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested
by Vector.
* 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature :
copying of unconfigured blocks.
* 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature :
Number of 8 bytes writes, fixed issue with copy blocks.
* 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature :CRC
check for unconfigured blocks, Main function modified to complete writes as fast as
possible, Added Non polling mode support.
* 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags
added.
* MISRA C fixes.
* 01.21.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization
changes. Added mew ,acro
* TI_FEE_TOTAL_BLOCKS_DATASETS
* 01.22.00 26Dec2014 Vishwanath Reddy SDOCM00114423 Following new macros
added.
* TI_FEE_VIRTUALSECTOR_SIZE,
* TI_FEE_PHYSICALSECTOR_SIZE,
* TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC.
* 01.23.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version
history.
* 01.23.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Updated version
history.
* 01.23.02 10Mar2016 Vishwanath Reddy SDOCM00121622 Updated version
history.
* 01.23.03 04Aug2016 Vishwanath Reddy SDOCM00122571 Update patch version
FEE_SW_PATCH_VERSION.
* 01.23.04 12Aug2016 Vishwanath Reddy SDOCM00122592
TI_FEE_CHECK_BANK7_ACCESS is always turned on.
* FEE_FLASH_CRC_ENABLE
is renamed to
* FEE_FLASH_CHECKSUM_ENABLE.
* New macro
FEE_USEPARTIALERASEDSECTOR added.
* 01.23.05 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version
history for AUTOSAR FEE
* (This corresponds to
TI FEE 1.19.04.)
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef FEE_INTERFACE_H
#define FEE_INTERFACE_H
#include "ti_fee_cfg.h"
#if( TI_FEE_DRIVER == 0U ) /* Include following macros only in Autosar Context */
#include "fee_cfg.h"
#include "nvm.h"
#define Fee_None \
0x00U /* Take no action on single bit errors, (respond with corrected data), \
*/
/* return error for uncorrectable error reads (multi bit errors for ECC or parity
* failures). */
/* For devices with no ECC (they may have parity or not) the only valid option is
* none. */
#define Fee_Fix \
0x01U /* single bit "zero" error will be fixed by reprogramming, single bit \
"one" error */
/* will be fixed by marking the current entry as invalid and copying the data to a new
* entry,*/
/* return error for uncorrectable error reads (multi bit errors for ECC or parity
* failures). */
#define TI_Fee_None \
0x00U /* Take no action on single bit errors, (respond with corrected data), \
*/
/* return error for uncorrectable error reads(multibit errors for ECC or parity
* failures)*/
/* For devices with no ECC (they may have parity or not) the only valid option is
* none. */
#define TI_Fee_Fix \
0x01U /* single bit "zero" error will be fixed by reprogramming, single bit \
"one" error */
/* will be fixed by marking the current entry as invalid and copying the data to a new
entry, */
/* return error for uncorrectable error reads (multi bit errors for ECC or parity
failures)*/
#if( FEE_FLASH_ERROR_CORRECTION_HANDLING == Fee_Fix )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_Fee_Fix is a symbolic
* constant."*/
#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix
#else
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_Fee_None is a symbolic
* constant."*/
#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None
#endif
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_MAXIMUM_BLOCKING_TIME is a
* symbolic constant"*/
#define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_OPERATING_FREQUENCY is a
* symbolic constant."*/
#define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE
* is a symbolic constant."*/
#define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_CHECKSUM_ENABLE is a
* symbolic constant."*/
#define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a
* symbolic constant."*/
#define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - NVM_DATASET_SELECTION_BITS is a
* symbolic constant."*/
#define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_EEPS is a symbolic
* constant."*/
#define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_INDEX is a symbolic
* constant."*/
#define TI_FEE_INDEX FEE_INDEX
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_PAGE_OVERHEAD is a symbolic
* constant."*/
#define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_BLOCK_OVERHEAD is a symbolic
* constant."*/
#define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUAL_PAGE_SIZE is a
* symbolic constant."*/
#define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a
* symbolic constant."*/
#define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason -
* FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/
#define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY \
FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a
* symbolic constant."*/
#define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NVM_JOB_END_NOTIFICATION is a
* symbolic constant."*/
#define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is
* a symbolic constant."*/
#define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_POLLING_MODE is a symbolic
* constant."*/
#define TI_FEE_POLLING_MODE FEE_POLLING_MODE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_CHECK_BANK7_ACCESS is a
* symbolic constant."*/
#ifndef FEE_CHECK_BANK7_ACCESS
#define TI_FEE_CHECK_BANK7_ACCESS STD_ON
#else
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_CHECK_BANK7_ACCESS is a
* symbolic constant."*/
#define TI_FEE_CHECK_BANK7_ACCESS STD_ON
#endif
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_TOTAL_BLOCKS_DATASETS is a
* symbolic constant."*/
#define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_VIRTUALSECTOR_SIZE is a
* symbolic constant."*/
#define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_PHYSICALSECTOR_SIZE is a
* symbolic constant."*/
#define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason -
* FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/
#define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC \
FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_USEPARTIALERASEDSECTOR is a
* symbolic constant."*/
#define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR
/*----------------------------------------------------------------------------*/
/* Virtual Sector Configuration */
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a
* symbolic constant."*/
/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is
* required here."*/
#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1
* is a symbolic constant."*/
/*SAFETYMCUSW 384 S MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is
* required here."*/
/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - Similar Identifier name is
* required here."*/
#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1
/*----------------------------------------------------------------------------*/
/* Block Configuration */
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic
* constant."*/
#define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Reason - TI_FEE_VARIABLE_DATASETS is a
* symbolic constant."*/
#define TI_FEE_VARIABLE_DATASETS STD_ON
#endif /* TI_FEE_DRIVER */
#endif /* FEE_INTERFACE_H */
/**********************************************************************************************************************
* END OF FILE: fee_interface.h
*********************************************************************************************************************/

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/** @file gio.h
* @brief GIO Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __GIO_H__
#define __GIO_H__
#include "reg_gio.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
typedef struct gio_config_reg
{
uint32 CONFIG_INTDET;
uint32 CONFIG_POL;
uint32 CONFIG_INTENASET;
uint32 CONFIG_LVLSET;
uint32 CONFIG_PORTADIR;
uint32 CONFIG_PORTAPDR;
uint32 CONFIG_PORTAPSL;
uint32 CONFIG_PORTAPULDIS;
uint32 CONFIG_PORTBDIR;
uint32 CONFIG_PORTBPDR;
uint32 CONFIG_PORTBPSL;
uint32 CONFIG_PORTBPULDIS;
} gio_config_reg_t;
#define GIO_INTDET_CONFIGVALUE 0U
#define GIO_POL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) )
#define GIO_INTENASET_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) )
#define GIO_LVLSET_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) )
#define GIO_PORTADIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTAPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTAPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTAPULDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
#define GIO_PORTBPULDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) )
/**
* @defgroup GIO GIO
* @brief General-Purpose Input/Output Module.
*
* The GIO module provides the family of devices with input/output (I/O) capability.
* The I/O pins are bidirectional and bit-programmable.
* The GIO module also supports external interrupt capability.
*
* Related Files
* - reg_gio.h
* - gio.h
* - gio.c
* @addtogroup GIO
* @{
*/
/* GIO Interface Functions */
void gioInit( void );
void gioSetDirection( gioPORT_t * port, uint32 dir );
void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value );
void gioSetPort( gioPORT_t * port, uint32 value );
uint32 gioGetBit( gioPORT_t * port, uint32 bit );
uint32 gioGetPort( gioPORT_t * port );
void gioToggleBit( gioPORT_t * port, uint32 bit );
void gioEnableNotification( gioPORT_t * port, uint32 bit );
void gioDisableNotification( gioPORT_t * port, uint32 bit );
void gioNotification( gioPORT_t * port, uint32 bit );
void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h
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/** @file hal_stdtypes.h
* @brief HALCoGen standard types header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Type and Global definitions which are relevant for all drivers.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HAL_STDTYPES_H__
#define __HAL_STDTYPES_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include <stdint.h>
#include <stdbool.h>
/* USER CODE BEGIN (1) */
/* USER CODE END */
/************************************************************/
/* Type Definitions */
/************************************************************/
#ifndef _UINT64_DECLARED
typedef uint64_t uint64;
#define _UINT64_DECLARED
#endif
#ifndef _UINT32_DECLARED
typedef uint32_t uint32;
#define _UINT32_DECLARED
#endif
#ifndef _UINT16_DECLARED
typedef uint16_t uint16;
#define _UINT16_DECLARED
#endif
#ifndef _UINT8_DECLARED
typedef uint8_t uint8;
#define _UINT8_DECLARED
#endif
#ifndef _BOOLEAN_DECLARED
#ifdef __cplusplus
typedef bool boolean;
#else
typedef _Bool boolean;
#endif
#define _BOOLEAN_DECLARED
#endif
#ifndef _SINT64_DECLARED
typedef int64_t sint64;
#define _SINT64_DECLARED
#endif
#ifndef _SINT32_DECLARED
typedef int32_t sint32;
#define _SINT32_DECLARED
#endif
#ifndef _SINT16_DECLARED
typedef int16_t sint16;
#define _SINT16_DECLARED
#endif
#ifndef _SINT8_DECLARED
typedef int8_t sint8;
#define _SINT8_DECLARED
#endif
#ifndef _FLOAT32_DECLARED
typedef float float32;
#define _FLOAT32_DECLARED
#endif
#ifndef _FLOAT64_DECLARED
typedef double float64;
#define _FLOAT64_DECLARED
#endif
typedef uint8 Std_ReturnType;
typedef struct
{
uint16 vendorID;
uint16 moduleID;
uint8 instanceID;
uint8 sw_major_version;
uint8 sw_minor_version;
uint8 sw_patch_version;
} Std_VersionInfoType;
/*****************************************************************************/
/* SYMBOL DEFINITIONS */
/*****************************************************************************/
#ifndef STATUSTYPEDEFINED
#define STATUSTYPEDEFINED
#define E_OK 0x00U
typedef unsigned char StatusType;
#endif
#ifndef E_NOT_OK
#define E_NOT_OK 0x01U
#endif
#ifndef STD_ON
#define STD_ON 0x01U
#endif
#ifndef STD_OFF
#define STD_OFF 0x00U
#endif
/************************************************************/
/* Global Definitions */
/************************************************************/
/** @def NULL
* @brief NULL definition
*/
#ifndef NULL
#define NULL ( ( void * ) 0U )
#endif
/** @def TRUE
* @brief definition for TRUE
*/
#ifndef TRUE
#define TRUE true
#endif
/** @def FALSE
* @brief BOOLEAN definition for FALSE
*/
#ifndef FALSE
#define FALSE false
#endif
/*****************************************************************************/
/* Define: NULL_PTR */
/* Description: Void pointer to 0 */
/*****************************************************************************/
#ifndef NULL_PTR
#define NULL_PTR ( ( void * ) 0x0U )
#endif
/* USER CODE BEGIN (2) */
/* USER CODE END */
#endif /* __HAL_STDTYPES_H__ */

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/** @file het.h
* @brief HET Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HET_H__
#define __HET_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "reg_het.h"
#include <string.h>
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** @def pwm0
* @brief Pwm signal 0
*
* Alias for pwm signal 0
*/
#define pwm0 0U
/** @def pwm1
* @brief Pwm signal 1
*
* Alias for pwm signal 1
*/
#define pwm1 1U
/** @def pwm2
* @brief Pwm signal 2
*
* Alias for pwm signal 2
*/
#define pwm2 2U
/** @def pwm3
* @brief Pwm signal 3
*
* Alias for pwm signal 3
*/
#define pwm3 3U
/** @def pwm4
* @brief Pwm signal 4
*
* Alias for pwm signal 4
*/
#define pwm4 4U
/** @def pwm5
* @brief Pwm signal 5
*
* Alias for pwm signal 5
*/
#define pwm5 5U
/** @def pwm6
* @brief Pwm signal 6
*
* Alias for pwm signal 6
*/
#define pwm6 6U
/** @def pwm7
* @brief Pwm signal 7
*
* Alias for pwm signal 7
*/
#define pwm7 7U
/** @def edge0
* @brief Edge signal 0
*
* Alias for edge signal 0
*/
#define edge0 0U
/** @def edge1
* @brief Edge signal 1
*
* Alias for edge signal 1
*/
#define edge1 1U
/** @def edge2
* @brief Edge signal 2
*
* Alias for edge signal 2
*/
#define edge2 2U
/** @def edge3
* @brief Edge signal 3
*
* Alias for edge signal 3
*/
#define edge3 3U
/** @def edge4
* @brief Edge signal 4
*
* Alias for edge signal 4
*/
#define edge4 4U
/** @def edge5
* @brief Edge signal 5
*
* Alias for edge signal 5
*/
#define edge5 5U
/** @def edge6
* @brief Edge signal 6
*
* Alias for edge signal 6
*/
#define edge6 6U
/** @def edge7
* @brief Edge signal 7
*
* Alias for edge signal 7
*/
#define edge7 7U
/** @def cap0
* @brief Capture signal 0
*
* Alias for capture signal 0
*/
#define cap0 0U
/** @def cap1
* @brief Capture signal 1
*
* Alias for capture signal 1
*/
#define cap1 1U
/** @def cap2
* @brief Capture signal 2
*
* Alias for capture signal 2
*/
#define cap2 2U
/** @def cap3
* @brief Capture signal 3
*
* Alias for capture signal 3
*/
#define cap3 3U
/** @def cap4
* @brief Capture signal 4
*
* Alias for capture signal 4
*/
#define cap4 4U
/** @def cap5
* @brief Capture signal 5
*
* Alias for capture signal 5
*/
#define cap5 5U
/** @def cap6
* @brief Capture signal 6
*
* Alias for capture signal 6
*/
#define cap6 6U
/** @def cap7
* @brief Capture signal 7
*
* Alias for capture signal 7
*/
#define cap7 7U
/** @def pwmEND_OF_DUTY
* @brief Pwm end of duty
*
* Alias for pwm end of duty notification
*/
#define pwmEND_OF_DUTY 2U
/** @def pwmEND_OF_PERIOD
* @brief Pwm end of period
*
* Alias for pwm end of period notification
*/
#define pwmEND_OF_PERIOD 4U
/** @def pwmEND_OF_BOTH
* @brief Pwm end of duty and period
*
* Alias for pwm end of duty and period notification
*/
#define pwmEND_OF_BOTH 6U
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** @struct hetBase
* @brief HET Register Definition
*
* This structure is used to access the HET module registers.
*/
/** @typedef hetBASE_t
* @brief HET Register Frame Type Definition
*
* This type is used to access the HET Registers.
*/
enum hetPinSelect
{
PIN_HET_0 = 0U,
PIN_HET_1 = 1U,
PIN_HET_2 = 2U,
PIN_HET_3 = 3U,
PIN_HET_4 = 4U,
PIN_HET_5 = 5U,
PIN_HET_6 = 6U,
PIN_HET_7 = 7U,
PIN_HET_8 = 8U,
PIN_HET_9 = 9U,
PIN_HET_10 = 10U,
PIN_HET_11 = 11U,
PIN_HET_12 = 12U,
PIN_HET_13 = 13U,
PIN_HET_14 = 14U,
PIN_HET_15 = 15U,
PIN_HET_16 = 16U,
PIN_HET_17 = 17U,
PIN_HET_18 = 18U,
PIN_HET_19 = 19U,
PIN_HET_20 = 20U,
PIN_HET_21 = 21U,
PIN_HET_22 = 22U,
PIN_HET_23 = 23U,
PIN_HET_24 = 24U,
PIN_HET_25 = 25U,
PIN_HET_26 = 26U,
PIN_HET_27 = 27U,
PIN_HET_28 = 28U,
PIN_HET_29 = 29U,
PIN_HET_30 = 30U,
PIN_HET_31 = 31U
};
/** @struct hetSignal
* @brief HET Signal Definition
*
* This structure is used to define a pwm signal.
*/
/** @typedef hetSIGNAL_t
* @brief HET Signal Type Definition
*
* This type is used to access HET Signal Information.
*/
typedef struct hetSignal
{
uint32 duty; /**< Duty cycle in % of the period */
float64 period; /**< Period in us */
} hetSIGNAL_t;
/* Configuration registers */
typedef struct het_config_reg
{
uint32 CONFIG_GCR;
uint32 CONFIG_PFR;
uint32 CONFIG_INTENAS;
uint32 CONFIG_INTENAC;
uint32 CONFIG_PRY;
uint32 CONFIG_AND;
uint32 CONFIG_HRSH;
uint32 CONFIG_XOR;
uint32 CONFIG_DIR;
uint32 CONFIG_PDR;
uint32 CONFIG_PULDIS;
uint32 CONFIG_PSL;
uint32 CONFIG_PCR;
} het_config_reg_t;
/* Configuration registers initial value for HET1*/
#define HET1_DIR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_PDR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_PULDIS_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_PSL_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_HRSH_CONFIGVALUE \
( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \
| ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \
| ( uint32 ) 0x00000001U )
#define HET1_AND_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define HET1_XOR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define HET1_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U )
#define HET1_PRY_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_INTENAC_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_INTENAS_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET1_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U )
#define HET1_GCR_CONFIGVALUE \
( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) )
/* Configuration registers initial value for HET2*/
#define HET2_DIR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_PDR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_PULDIS_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_PSL_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_HRSH_CONFIGVALUE \
( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \
| ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \
| ( uint32 ) 0x00000001U )
#define HET2_AND_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define HET2_XOR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U )
#define HET2_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U )
#define HET2_PRY_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_INTENAC_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_INTENAS_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \
| ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U )
#define HET2_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U )
#define HET2_GCR_CONFIGVALUE \
( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) )
/**
* @defgroup HET HET
* @brief HighEnd Timer Module.
*
* The HET is a software-controlled timer with a dedicated specialized timer micromachine
*and a set of 30 instructions. The HET micromachine is connected to a port of up to 32
*input/output (I/O) pins.
*
* Related Files
* - reg_het.h
* - het.h
* - het.c
* - reg_htu.h
* - htu.h
* - std_nhet.h
* @addtogroup HET
* @{
*/
/* HET Interface Functions */
void hetInit( void );
/* PWM Interface Functions */
void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm );
void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm );
void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty );
void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal );
void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal );
void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification );
void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification );
void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification );
/* Edge Interface Functions */
void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge );
uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge );
void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge );
void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge );
void edgeNotification( hetBASE_t * hetREG, uint32 edge );
/* Captured Signal Interface Functions */
void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal );
/* Timestamp Interface Functions */
void hetResetTimestamp( hetRAMBASE_t * hetRAM );
uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM );
void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type );
void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type );
/** @fn void hetNotification(hetBASE_t *het, uint32 offset)
* @brief het interrupt callback
* @param[in] het - Het module base address
* - hetREG1: HET1 module base address pointer
* - hetREG2: HET2 module base address pointer
* @param[in] offset - het interrupt offset / Source number
*
* @note This function has to be provide by the user.
*
* This is a interrupt callback that is provided by the application and is call upon
* an het interrupt. The parameter passed to the callback is a copy of the interrupt
* offset register which is used to decode the interrupt source.
*/
void hetNotification( hetBASE_t * het, uint32 offset );
/* USER CODE BEGIN (4) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file htu.h
* @brief HTU Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HTU_H__
#define __HTU_H__
#include "reg_htu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* HTU General Definitions */
#define HTU1PARLOC ( *( volatile uint32 * ) 0xFF4E0200U )
#define HTU2PARLOC ( *( volatile uint32 * ) 0xFF4C0200U )
#define HTU1RAMLOC ( *( volatile uint32 * ) 0xFF4E0000U )
#define HTU2RAMLOC ( *( volatile uint32 * ) 0xFF4C0000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/*
* hw_emac1.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _HW_EMAC_CTRL_H_
#define _HW_EMAC_CTRL_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
#define EMAC_CTRL_REVID ( 0x0U )
#define EMAC_CTRL_SOFTRESET ( 0x4U )
#define EMAC_CTRL_INTCONTROL ( 0xCU )
#define EMAC_CTRL_C0RXTHRESHEN ( 0x10U )
#define EMAC_CTRL_CnRXEN( n ) ( ( uint32 ) 0x14u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_CnTXEN( n ) ( ( uint32 ) 0x18u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_CnMISCEN( n ) \
( ( uint32 ) 0x1Cu + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_CnRXTHRESHEN( n ) \
( ( uint32 ) 0x20u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) )
#define EMAC_CTRL_C0RXTHRESHSTAT ( 0x40U )
#define EMAC_CTRL_C0RXSTAT ( 0x44U )
#define EMAC_CTRL_C0TXSTAT ( 0x48U )
#define EMAC_CTRL_C0MISCSTAT ( 0x4CU )
#define EMAC_CTRL_C1RXTHRESHSTAT ( 0x50U )
#define EMAC_CTRL_C1RXSTAT ( 0x54U )
#define EMAC_CTRL_C1TXSTAT ( 0x58U )
#define EMAC_CTRL_C1MISCSTAT ( 0x5CU )
#define EMAC_CTRL_C2RXTHRESHSTAT ( 0x60U )
#define EMAC_CTRL_C2RXSTAT ( 0x64U )
#define EMAC_CTRL_C2TXSTAT ( 0x68U )
#define EMAC_CTRL_C2MISCSTAT ( 0x6CU )
#define EMAC_CTRL_C0RXIMAX ( 0x70U )
#define EMAC_CTRL_C0TXIMAX ( 0x74U )
#define EMAC_CTRL_C1RXIMAX ( 0x78U )
#define EMAC_CTRL_C1TXIMAX ( 0x7CU )
#define EMAC_CTRL_C2RXIMAX ( 0x80U )
#define EMAC_CTRL_C2TXIMAX ( 0x84U )
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif

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/*
* hw_mdio.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _HW_MDIO_H_
#define _HW_MDIO_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
#define MDIO_BASE ( 0xFCF78900U )
#define MDIO_REVID ( 0x0U )
#define MDIO_CONTROL ( 0x4U )
#define MDIO_ALIVE ( 0x8U )
#define MDIO_LINK ( 0xCU )
#define MDIO_LINKINTRAW ( 0x10U )
#define MDIO_LINKINTMASKED ( 0x14U )
#define MDIO_USERINTRAW ( 0x20U )
#define MDIO_USERINTMASKED ( 0x24U )
#define MDIO_USERINTMASKSET ( 0x28U )
#define MDIO_USERINTMASKCLEAR ( 0x2CU )
#define MDIO_USERACCESS0 ( 0x80U )
#define MDIO_USERPHYSEL0 ( 0x84U )
#define MDIO_USERACCESS1 ( 0x88U )
#define MDIO_USERPHYSEL1 ( 0x8CU )
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* REVID */
#define MDIO_REVID_REV ( 0xFFFFFFFFU )
#define MDIO_REVID_REV_SHIFT ( 0x00000000U )
/* CONTROL */
#define MDIO_CONTROL_IDLE ( 0x80000000U )
#define MDIO_CONTROL_IDLE_SHIFT ( 0x0000001FU )
/*----IDLE Tokens----*/
#define MDIO_CONTROL_IDLE_NO ( 0x00000000U )
#define MDIO_CONTROL_IDLE_YES ( 0x00000001U )
#define MDIO_CONTROL_ENABLE ( 0x40000000U )
#define MDIO_CONTROL_ENABLE_SHIFT ( 0x0000001EU )
#define MDIO_CONTROL_HIGHEST_USER_CHANNEL ( 0x1F000000U )
#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT ( 0x00000018U )
#define MDIO_CONTROL_PREAMBLE ( 0x00100000U )
#define MDIO_CONTROL_PREAMBLE_SHIFT ( 0x00000014U )
/*----PREAMBLE Tokens----*/
#define MDIO_CONTROL_FAULT ( 0x00080000U )
#define MDIO_CONTROL_FAULT_SHIFT ( 0x00000013U )
#define MDIO_CONTROL_FAULTENB ( 0x00040000U )
#define MDIO_CONTROL_FAULTENB_SHIFT ( 0x00000012U )
/*----FAULTENB Tokens----*/
#define MDIO_CONTROL_CLKDIV ( 0x0000FFFFU )
#define MDIO_CONTROL_CLKDIV_SHIFT ( 0x00000000U )
/*----CLKDIV Tokens----*/
/* ALIVE */
#define MDIO_ALIVE_REGVAL ( 0xFFFFFFFFU )
#define MDIO_ALIVE_REGVAL_SHIFT ( 0x00000000U )
/* LINK */
#define MDIO_LINK_REGVAL ( 0xFFFFFFFFU )
#define MDIO_LINK_REGVAL_SHIFT ( 0x00000000U )
/* LINKINTRAW */
#define MDIO_LINKINTRAW_USERPHY1 ( 0x00000002U )
#define MDIO_LINKINTRAW_USERPHY1_SHIFT ( 0x00000001U )
#define MDIO_LINKINTRAW_USERPHY0 ( 0x00000001U )
#define MDIO_LINKINTRAW_USERPHY0_SHIFT ( 0x00000000U )
/* LINKINTMASKED */
#define MDIO_LINKINTMASKED_USERPHY1 ( 0x00000002U )
#define MDIO_LINKINTMASKED_USERPHY1_SHIFT ( 0x00000001U )
#define MDIO_LINKINTMASKED_USERPHY0 ( 0x00000001U )
#define MDIO_LINKINTMASKED_USERPHY0_SHIFT ( 0x00000000U )
/* USERINTRAW */
#define MDIO_USERINTRAW_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTRAW_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTRAW_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTRAW_USERACCESS0_SHIFT ( 0x00000000U )
/* USERINTMASKED */
#define MDIO_USERINTMASKED_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTMASKED_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTMASKED_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTMASKED_USERACCESS0_SHIFT ( 0x00000000U )
/* USERINTMASKSET */
#define MDIO_USERINTMASKSET_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTMASKSET_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT ( 0x00000000U )
/* USERINTMASKCLEAR */
#define MDIO_USERINTMASKCLEAR_USERACCESS1 ( 0x00000002U )
#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT ( 0x00000001U )
#define MDIO_USERINTMASKCLEAR_USERACCESS0 ( 0x00000001U )
#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT ( 0x00000000U )
/* USERACCESS0 */
#define MDIO_USERACCESS0_GO ( 0x80000000U )
#define MDIO_USERACCESS0_GO_SHIFT ( 0x0000001FU )
#define MDIO_USERACCESS0_WRITE ( 0x40000000U )
#define MDIO_USERACCESS0_READ ( 0x00000000U )
#define MDIO_USERACCESS0_WRITE_SHIFT ( 0x0000001EU )
#define MDIO_USERACCESS0_ACK ( 0x20000000U )
#define MDIO_USERACCESS0_ACK_SHIFT ( 0x0000001DU )
#define MDIO_USERACCESS0_REGADR ( 0x03E00000U )
#define MDIO_USERACCESS0_REGADR_SHIFT ( 0x00000015U )
#define MDIO_USERACCESS0_PHYADR ( 0x001F0000U )
#define MDIO_USERACCESS0_PHYADR_SHIFT ( 0x00000010U )
#define MDIO_USERACCESS0_DATA ( 0x0000FFFFU )
#define MDIO_USERACCESS0_DATA_SHIFT ( 0x00000000U )
/* USERPHYSEL0 */
#define MDIO_USERPHYSEL0_LINKSEL ( 0x00000080U )
#define MDIO_USERPHYSEL0_LINKSEL_SHIFT ( 0x00000007U )
#define MDIO_USERPHYSEL0_LINKINTENB ( 0x00000040U )
#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT ( 0x00000006U )
#define MDIO_USERPHYSEL0_PHYADRMON ( 0x0000001FU )
#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT ( 0x00000000U )
/* USERACCESS1 */
#define MDIO_USERACCESS1_GO ( 0x80000000U )
#define MDIO_USERACCESS1_GO_SHIFT ( 0x0000001FU )
#define MDIO_USERACCESS1_WRITE ( 0x40000000U )
#define MDIO_USERACCESS1_WRITE_SHIFT ( 0x0000001EU )
#define MDIO_USERACCESS1_ACK ( 0x20000000U )
#define MDIO_USERACCESS1_ACK_SHIFT ( 0x0000001DU )
#define MDIO_USERACCESS1_REGADR ( 0x03E00000U )
#define MDIO_USERACCESS1_REGADR_SHIFT ( 0x00000015U )
#define MDIO_USERACCESS1_PHYADR ( 0x001F0000U )
#define MDIO_USERACCESS1_PHYADR_SHIFT ( 0x00000010U )
#define MDIO_USERACCESS1_DATA ( 0x0000FFFFU )
#define MDIO_USERACCESS1_DATA_SHIFT ( 0x00000000U )
/* USERPHYSEL1 */
#define MDIO_USERPHYSEL1_LINKSEL ( 0x00000080U )
#define MDIO_USERPHYSEL1_LINKSEL_SHIFT ( 0x00000007U )
#define MDIO_USERPHYSEL1_LINKINTENB ( 0x00000040U )
#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT ( 0x00000006U )
#define MDIO_USERPHYSEL1_PHYADRMON ( 0x0000001FU )
#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT ( 0x00000000U )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif

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/*
* hw_reg_access.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _HW_REG_ACCESS_H_
#define _HW_REG_ACCESS_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/*******************************************************************************
*
* Macros for hardware access, both direct and via the bit-band region.
*
*****************************************************************************/
#define HWREG( x ) ( *( ( volatile uint32 * ) ( x ) ) )
#define HWREGH( x ) ( *( ( volatile uint16 * ) ( x ) ) )
#define HWREGB( x ) ( *( ( volatile uint8 * ) ( x ) ) )
#define HWREGBITW( x, b ) \
( HWREG( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \
| ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \
| ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) )
#define HWREGBITH( x, b ) \
( HWREGH( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \
| ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \
| ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) )
#define HWREGBITB( x, b ) \
( HWREGB( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \
| ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \
| ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif /* __HW_TYPES_H__ */

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/** @file I2C.h
* @brief I2C Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __I2C_H__
#define __I2C_H__
#include "reg_i2c.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum i2cMode
* @brief Alias names for i2c modes
* This enumeration is used to provide alias names for I2C modes:
*/
enum i2cMode
{
I2C_FD_FORMAT = 0x0008U, /* Free Data Format */
I2C_START_BYTE = 0x0010U,
I2C_RESET_OUT = 0x0020U,
I2C_RESET_IN = 0x0000U,
I2C_DLOOPBACK = 0x0040U,
I2C_REPEATMODE = 0x0080U, /* In Master Mode only */
I2C_10BIT_AMODE = 0x0100U,
I2C_7BIT_AMODE = 0x0000U,
I2C_TRANSMITTER = 0x0200U,
I2C_RECEIVER = 0x0000U,
I2C_MASTER = 0x0400U,
I2C_SLAVE = 0x0000U,
I2C_STOP_COND = 0x0800U, /* In Master Mode only */
I2C_START_COND = 0x2000U, /* In Master Mode only */
I2C_FREE_RUN = 0x4000U,
I2C_NACK_MODE = 0x8000U
};
/** @enum i2cBitCount
* @brief Alias names for i2c bit count
* This enumeration is used to provide alias names for I2C bit count:
*/
enum i2cBitCount
{
I2C_2_BIT = 0x2U,
I2C_3_BIT = 0x3U,
I2C_4_BIT = 0x4U,
I2C_5_BIT = 0x5U,
I2C_6_BIT = 0x6U,
I2C_7_BIT = 0x7U,
I2C_8_BIT = 0x0U
};
/** @enum i2cIntFlags
* @brief Interrupt Flag Definitions
*
* Used with I2CEnableNotification, I2CDisableNotification
*/
enum i2cIntFlags
{
I2C_AL_INT = 0x0001U, /* arbitration lost */
I2C_NACK_INT = 0x0002U, /* no acknowledgment */
I2C_ARDY_INT = 0x0004U, /* access ready */
I2C_RX_INT = 0x0008U, /* receive data ready */
I2C_TX_INT = 0x0010U, /* transmit data ready */
I2C_SCD_INT = 0x0020U, /* stop condition detect */
I2C_AAS_INT = 0x0040U /* address as slave */
};
/** @enum i2cStatFlags
* @brief Interrupt Status Definitions
*
*/
enum i2cStatFlags
{
I2C_AL = 0x0001U, /* arbitration lost */
I2C_NACK = 0x0002U, /* no acknowledgement */
I2C_ARDY = 0x0004U, /* access ready */
I2C_RX = 0x0008U, /* receive data ready */
I2C_TX = 0x0010U, /* transmit data ready */
I2C_SCD = 0x0020U, /* stop condition detect */
I2C_AD0 = 0x0100U, /* address Zero Status */
I2C_AAS = 0x0200U, /* address as slave */
I2C_XSMT = 0x0400U, /* Transmit shift empty not */
I2C_RXFULL = 0x0800U, /* receive full */
I2C_BUSBUSY = 0x1000U, /* bus busy */
I2C_NACKSNT = 0x2000U, /* No Ack Sent */
I2C_SDIR = 0x4000U /* Slave Direction */
};
/** @enum i2cDMA
* @brief I2C DMA definitions
*
* Used before i2c transfer
*/
enum i2cDMA
{
I2C_TXDMA = 0x20U,
I2C_RXDMA = 0x10U
};
/* Configuration registers */
typedef struct i2c_config_reg
{
uint32 CONFIG_OAR;
uint32 CONFIG_IMR;
uint32 CONFIG_CLKL;
uint32 CONFIG_CLKH;
uint32 CONFIG_CNT;
uint32 CONFIG_SAR;
uint32 CONFIG_MDR;
uint32 CONFIG_EMDR;
uint32 CONFIG_PSC;
uint32 CONFIG_DMAC;
uint32 CONFIG_FUN;
uint32 CONFIG_DIR;
uint32 CONFIG_ODR;
uint32 CONFIG_PD;
uint32 CONFIG_PSL;
} i2c_config_reg_t;
/* Configuration registers initial value for I2C*/
#define I2C1_OAR_CONFIGVALUE 0x00000000U
#define I2C1_IMR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( ( uint32 ) 0U ) )
#define I2C1_CLKL_CONFIGVALUE 37U
#define I2C1_CLKH_CONFIGVALUE 37U
#define I2C1_CNT_CONFIGVALUE 8U
#define I2C1_SAR_CONFIGVALUE 0x000003FFU
#define I2C1_MDR_CONFIGVALUE \
( 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( ( uint32 ) I2C_TRANSMITTER ) \
| ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \
| ( ( uint32 ) 0U ) | ( ( uint32 ) I2C_8_BIT ) | ( uint32 ) I2C_RESET_OUT )
#define I2C1_EMDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_PSC_CONFIGVALUE 8U
#define I2C1_DMAC_CONFIGVALUE 0x00000000U
#define I2C1_FUN_CONFIGVALUE 0U
#define I2C1_DIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_ODR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_PD_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C1_PSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) )
/* Configuration registers initial value for I2C*/
#define I2C2_OAR_CONFIGVALUE 0x00000000U
#define I2C2_IMR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( ( uint32 ) 0U ) )
#define I2C2_CLKL_CONFIGVALUE 37U
#define I2C2_CLKH_CONFIGVALUE 37U
#define I2C2_CNT_CONFIGVALUE 8U
#define I2C2_SAR_CONFIGVALUE 0x000003FFU
#define I2C2_MDR_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) \
| ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U ) | ( uint32 ) ( ( uint32 ) I2C_2_BIT ) \
| ( uint32 ) I2C_RESET_OUT )
#define I2C2_EMDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_PSC_CONFIGVALUE 8U
#define I2C2_DMAC_CONFIGVALUE 0x00000000U
#define I2C2_FUN_CONFIGVALUE 0U
#define I2C2_DIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_ODR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_PD_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define I2C2_PSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) )
/**
* @defgroup I2C I2C
* @brief Inter-Integrated Circuit Module.
*
* The I2C is a multi-master communication module providing an interface between the
* Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor
* I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support
* any slave or master I2C compatible device.
*
* Related Files
* - reg_i2c.h
* - i2c.h
* - i2c.c
* @addtogroup I2C
* @{
*/
/* I2C Interface Functions */
void i2cInit( void );
void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd );
void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd );
void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud );
uint32 i2cIsTxReady( i2cBASE_t * i2c );
void i2cSendByte( i2cBASE_t * i2c, uint8 byte );
void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data );
uint32 i2cIsRxReady( i2cBASE_t * i2c );
uint32 i2cIsStopDetected( i2cBASE_t * i2c );
void i2cClearSCD( i2cBASE_t * i2c );
uint32 i2cRxError( i2cBASE_t * i2c );
uint8 i2cReceiveByte( i2cBASE_t * i2c );
void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data );
void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags );
void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags );
void i2cSetStart( i2cBASE_t * i2c );
void i2cSetStop( i2cBASE_t * i2c );
void i2cSetCount( i2cBASE_t * i2c, uint32 cnt );
void i2cEnableLoopback( i2cBASE_t * i2c );
void i2cDisableLoopback( i2cBASE_t * i2c );
void i2cSetMode( i2cBASE_t * i2c, uint32 mode );
void i2cSetDirection( i2cBASE_t * i2c, uint32 dir );
bool i2cIsMasterReady( i2cBASE_t * i2c );
bool i2cIsBusBusy( i2cBASE_t * i2c );
void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type );
void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type );
/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags)
* @brief Interrupt callback
* @param[in] i2c - I2C module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called apon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void i2cNotification( i2cBASE_t * i2c, uint32 flags );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file lin.h
* @brief LIN Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __LIN_H__
#define __LIN_H__
#include "reg_lin.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @def LIN_BREAK_INT
* @brief Alias for break detect interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_BREAK_INT 0x00000001U
/** @def LIN_WAKEUP_INT
* @brief Alias for wakeup interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_WAKEUP_INT 0x00000002U
/** @def LIN_TO_INT
* @brief Alias for time out interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_TO_INT 0x00000010U
/** @def LIN_TOAWUS_INT
* @brief Alias for time out after wakeup signal interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_TOAWUS_INT 0x00000040U
/** @def LIN_TOA3WUS_INT
* @brief Alias for time out after 3 wakeup signals interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_TOA3WUS_INT 0x00000080U
/** @def LIN_TX_READY
* @brief Alias for transmit buffer ready flag
*
* Used with linIsTxReady.
*/
#define LIN_TX_READY 0x00000100U
/** @def LIN_RX_INT
* @brief Alias for receive buffer ready interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_RX_INT 0x00000200U
/** @def LIN_ID_INT
* @brief Alias for received matching identifier interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_ID_INT 0x00002000U
/** @def LIN_PE_INT
* @brief Alias for parity error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_PE_INT 0x01000000U
/** @def LIN_OE_INT
* @brief Alias for overrun error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_OE_INT 0x02000000U
/** @def LIN_FE_INT
* @brief Alias for framing error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_FE_INT 0x04000000U
/** @def LIN_NRE_INT
* @brief Alias for no response error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_NRE_INT 0x08000000U
/** @def LIN_ISFE_INT
* @brief Alias for inconsistent sync field error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_ISFE_INT 0x10000000U
/** @def LIN_CE_INT
* @brief Alias for checksum error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_CE_INT 0x20000000U
/** @def LIN_PBE_INT
* @brief Alias for physical bus error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_PBE_INT 0x40000000U
/** @def LIN_BE_INT
* @brief Alias for bit error interrupt flag
*
* Used with linEnableNotification, linDisableNotification.
*/
#define LIN_BE_INT 0x80000000U
/** @struct linBase
* @brief LIN Register Definition
*
* This structure is used to access the LIN module registers.
*/
/** @typedef linBASE_t
* @brief LIN Register Frame Type Definition
*
* This type is used to access the LIN Registers.
*/
enum linPinSelect
{
PIN_LIN_TX = 4U,
PIN_LIN_RX = 2U
};
/* Configuration registers */
typedef struct lin_config_reg
{
uint32 CONFIG_GCR0;
uint32 CONFIG_GCR1;
uint32 CONFIG_GCR2;
uint32 CONFIG_SETINT;
uint32 CONFIG_SETINTLVL;
uint32 CONFIG_FORMAT;
uint32 CONFIG_BRSR;
uint32 CONFIG_FUN;
uint32 CONFIG_DIR;
uint32 CONFIG_ODR;
uint32 CONFIG_PD;
uint32 CONFIG_PSL;
uint32 CONFIG_COMP;
uint32 CONFIG_MASK;
uint32 CONFIG_MBRSR;
} lin_config_reg_t;
/* Configuration registers initial value for LIN*/
#define LIN1_GCR0_CONFIGVALUE 0x00000001U
#define LIN1_GCR1_CONFIGVALUE \
( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) )
#define LIN1_GCR2_CONFIGVALUE 0x00000000U
#define LIN1_SETINTLVL_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN1_SETINT_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN1_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) )
#define LIN1_BRSR_CONFIGVALUE ( 233U )
#define LIN1_COMP_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) )
#define LIN1_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU )
#define LIN1_MBRSR_CONFIGVALUE ( 3370U )
#define LIN1_FUN_CONFIGVALUE ( 4U | 2U | 0U )
#define LIN1_DIR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN1_ODR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN1_PD_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN1_PSL_CONFIGVALUE ( 4U | 2U | 1U )
/* Configuration registers initial value for LIN*/
#define LIN2_GCR0_CONFIGVALUE 0x00000001U
#define LIN2_GCR1_CONFIGVALUE \
( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) )
#define LIN2_GCR2_CONFIGVALUE 0x00000000U
#define LIN2_SETINTLVL_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN2_SETINT_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U )
#define LIN2_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) )
#define LIN2_BRSR_CONFIGVALUE ( 233U )
#define LIN2_COMP_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) )
#define LIN2_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU )
#define LIN2_MBRSR_CONFIGVALUE ( 3370U )
#define LIN2_FUN_CONFIGVALUE ( 4U | 2U | 0U )
#define LIN2_DIR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN2_ODR_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN2_PD_CONFIGVALUE ( 0U | 0U | 0U )
#define LIN2_PSL_CONFIGVALUE ( 4U | 2U | 1U )
/**
* @defgroup LIN LIN
* @brief Local Interconnect Network Module.
*
* The LIN standard is based on the SCI (UART) serial data link format. The communication
*concept is single-master/multiple-slave with a message identification for multi-cast
*transmission between any network nodes.
*
* Related Files
* - reg_lin.h
* - lin.h
* - lin.c
* @addtogroup LIN
* @{
*/
/* LIN Interface Functions */
void linInit( void );
void linSetFunctional( linBASE_t * lin, uint32 port );
void linSendHeader( linBASE_t * lin, uint8 identifier );
void linSendWakupSignal( linBASE_t * lin );
void linEnterSleep( linBASE_t * lin );
void linSoftwareReset( linBASE_t * lin );
uint32 linIsTxReady( linBASE_t * lin );
void linSetLength( linBASE_t * lin, uint32 length );
void linSend( linBASE_t * lin, uint8 * data );
uint32 linIsRxReady( linBASE_t * lin );
uint32 linTxRxError( linBASE_t * lin );
uint32 linGetIdentifier( linBASE_t * lin );
void linGetData( linBASE_t * lin, uint8 * const data );
void linEnableNotification( linBASE_t * lin, uint32 flags );
void linDisableNotification( linBASE_t * lin, uint32 flags );
void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype );
void linDisableLoopback( linBASE_t * lin );
void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type );
void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type );
uint32 linGetStatusFlag( linBASE_t * lin );
void linClearStatusFlag( linBASE_t * lin, uint32 flags );
/** @fn void linNotification(linBASE_t *lin, uint32 flags)
* @brief Interrupt callback
* @param[in] lin - lin module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called upon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void linNotification( linBASE_t * lin, uint32 flags );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file mdio.h
*
* \brief MDIO APIs and macros.
*
* This file contains the driver API prototypes and macro definitions.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __MDIO_H__
#define __MDIO_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_common.h"
#include "system.h"
#include "hw_mdio.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* MDIO input and output frequencies in Hz */
#define MDIO_FREQ_INPUT ( ( uint32 ) ( VCLK3_FREQ * 1000000.00F ) )
#define MDIO_FREQ_OUTPUT 1000000U
/*****************************************************************************/
/**
* @addtogroup EMACMDIO
* @{
*/
/*
** Prototypes for the APIs
*/
extern uint32 MDIOPhyAliveStatusGet( uint32 baseAddr );
extern uint32 MDIOPhyLinkStatusGet( uint32 baseAddr );
extern void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq );
extern boolean MDIOPhyRegRead( uint32 baseAddr,
uint32 phyAddr,
uint32 regNum,
volatile uint16 * dataPtr );
extern void MDIOPhyRegWrite( uint32 baseAddr,
uint32 phyAddr,
uint32 regNum,
uint16 RegVal );
extern void MDIOEnable( uint32 baseAddr );
extern void MDIODisable( uint32 baseAddr );
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* __MDIO_H__ */

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/** @file mibspi.h
* @brief MIBSPI Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __MIBSPI_H__
#define __MIBSPI_H__
#include "reg_mibspi.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum triggerEvent
* @brief Transfer Group Trigger Event
*/
enum triggerEvent
{
TRG_NEVER = 0U,
TRG_RISING = 1U,
TRG_FALLING = 2U,
TRG_BOTH = 3U,
TRG_HIGH = 5U,
TRG_LOW = 6U,
TRG_ALWAYS = 7U
};
/** @enum triggerSource
* @brief Transfer Group Trigger Source
*/
enum triggerSource
{
TRG_DISABLED,
TRG_GIOA0,
TRG_GIOA1,
TRG_GIOA2,
TRG_GIOA3,
TRG_GIOA4,
TRG_GIOA5,
TRG_GIOA6,
TRG_GIOA7,
TRG_HET1_8,
TRG_HET1_10,
TRG_HET1_12,
TRG_HET1_14,
TRG_HET1_16,
TRG_HET1_18,
TRG_TICK
};
/** @enum mibspiPinSelect
* @brief mibspi Pin Select
*/
enum mibspiPinSelect
{
PIN_CS0 = 0U,
PIN_CS1 = 1U,
PIN_CS2 = 2U,
PIN_CS3 = 3U,
PIN_CS4 = 4U,
PIN_CS5 = 5U,
PIN_CS6 = 6U,
PIN_CS7 = 7U,
PIN_ENA = 8U,
PIN_CLK = 9U,
PIN_SIMO = 10U,
PIN_SOMI = 11U,
PIN_SIMO_1 = 17U,
PIN_SIMO_2 = 18U,
PIN_SIMO_3 = 19U,
PIN_SIMO_4 = 20U,
PIN_SIMO_5 = 21U,
PIN_SIMO_6 = 22U,
PIN_SIMO_7 = 23U,
PIN_SOMI_1 = 25U,
PIN_SOMI_2 = 26U,
PIN_SOMI_3 = 27U,
PIN_SOMI_4 = 28U,
PIN_SOMI_5 = 29U,
PIN_SOMI_6 = 30U,
PIN_SOMI_7 = 31U
};
/** @enum chipSelect
* @brief Transfer Group Chip Select
*/
enum chipSelect
{
CS_NONE = 0xFFU,
CS_0 = 0xFEU,
CS_1 = 0xFDU,
CS_2 = 0xFBU,
CS_3 = 0xF7U,
CS_4 = 0xEFU,
CS_5 = 0xDFU,
CS_6 = 0xBFU,
CS_7 = 0x7FU
};
/** @typedef mibspiPmode_t
* @brief Mibspi Parellel mode Type Definition
*
* This type is used to represent Mibspi Parellel mode.
*/
typedef enum mibspiPmode
{
PMODE_NORMAL = 0x0U,
PMODE_2_DATALINE = 0x1U,
PMODE_4_DATALINE = 0x2U,
PMODE_8_DATALINE = 0x3U
} mibspiPmode_t;
/** @typedef mibspiDFMT_t
* @brief Mibspi Data format selection Type Definition
*
* This type is used to represent Mibspi Data format selection.
*/
typedef enum mibspiDFMT
{
DATA_FORMAT0 = 0x0U,
DATA_FORMAT1 = 0x1U,
DATA_FORMAT2 = 0x2U,
DATA_FORMAT3 = 0x3U
} mibspiDFMT_t;
typedef struct mibspi_config_reg
{
uint32 CONFIG_GCR1;
uint32 CONFIG_INT0;
uint32 CONFIG_LVL;
uint32 CONFIG_PCFUN;
uint32 CONFIG_PCDIR;
uint32 CONFIG_PCPDR;
uint32 CONFIG_PCDIS;
uint32 CONFIG_PCPSL;
uint32 CONFIG_DELAY;
uint32 CONFIG_FMT0;
uint32 CONFIG_FMT1;
uint32 CONFIG_FMT2;
uint32 CONFIG_FMT3;
uint32 CONFIG_MIBSPIE;
uint32 CONFIG_LTGPEND;
uint32 CONFIG_TGCTRL[ 8U ];
uint32 CONFIG_PAR_ECC_CTRL;
} mibspi_config_reg_t;
#define MIBSPI1_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U )
#define MIBSPI1_INT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI1_LVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI1_PCFUN_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \
| ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) )
#define MIBSPI1_PCDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) )
#define MIBSPI1_PCPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) )
#define MIBSPI1_PCDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) )
#define MIBSPI1_PCPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \
| ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) )
#define MIBSPI1_DELAY_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI1_FMT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI1_FMT1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI1_FMT2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI1_FMT3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI1_MIBSPIE_CONFIGVALUE 0x501U
#define MIBSPI1_LTGPEND_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) )
#define MIBSPI1_TGCTRL0_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) ) )
#define MIBSPI1_TGCTRL1_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 8U << 8U ) ) )
#define MIBSPI1_TGCTRL2_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) )
#define MIBSPI1_TGCTRL3_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) )
#define MIBSPI1_TGCTRL4_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI1_TGCTRL5_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI1_TGCTRL6_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI1_TGCTRL7_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U )
#define MIBSPI2_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U )
#define MIBSPI2_INT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U ) )
#define MIBSPI2_LVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define MIBSPI2_PCFUN_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define MIBSPI2_PCDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI2_PCPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI2_PCDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI2_PCPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define MIBSPI2_DELAY_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI2_FMT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI2_FMT1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI2_FMT2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI2_FMT3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI2_MIBSPIE_CONFIGVALUE 0x501U
#define MIBSPI2_LTGPEND_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) )
#define MIBSPI2_TGCTRL0_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) ) )
#define MIBSPI2_TGCTRL1_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 8U << 8U ) ) )
#define MIBSPI2_TGCTRL2_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) )
#define MIBSPI2_TGCTRL3_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) )
#define MIBSPI2_TGCTRL4_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI2_TGCTRL5_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI2_TGCTRL6_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI2_TGCTRL7_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U )
#define MIBSPI3_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U )
#define MIBSPI3_INT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI3_LVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI3_PCFUN_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define MIBSPI3_PCDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI3_PCPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI3_PCDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI3_PCPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define MIBSPI3_DELAY_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI3_FMT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI3_FMT1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI3_FMT2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI3_FMT3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI3_MIBSPIE_CONFIGVALUE 0x501U
#define MIBSPI3_LTGPEND_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) )
#define MIBSPI3_TGCTRL0_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) ) )
#define MIBSPI3_TGCTRL1_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 8U << 8U ) ) )
#define MIBSPI3_TGCTRL2_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) )
#define MIBSPI3_TGCTRL3_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) )
#define MIBSPI3_TGCTRL4_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI3_TGCTRL5_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI3_TGCTRL6_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI3_TGCTRL7_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U )
#define MIBSPI4_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U )
#define MIBSPI4_INT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U ) )
#define MIBSPI4_LVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) )
#define MIBSPI4_PCFUN_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define MIBSPI4_PCDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI4_PCPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI4_PCDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) )
#define MIBSPI4_PCPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define MIBSPI4_DELAY_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI4_FMT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI4_FMT1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI4_FMT2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI4_FMT3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI4_MIBSPIE_CONFIGVALUE 0x501U
#define MIBSPI4_LTGPEND_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) )
#define MIBSPI4_TGCTRL0_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) ) )
#define MIBSPI4_TGCTRL1_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 8U << 8U ) ) )
#define MIBSPI4_TGCTRL2_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) )
#define MIBSPI4_TGCTRL3_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) )
#define MIBSPI4_TGCTRL4_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI4_TGCTRL5_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI4_TGCTRL6_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI4_TGCTRL7_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U )
#define MIBSPI5_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U )
#define MIBSPI5_INT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI5_LVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI5_PCFUN_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \
| ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \
| ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \
| ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) )
#define MIBSPI5_PCDIR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \
| ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) )
#define MIBSPI5_PCPDR_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \
| ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) )
#define MIBSPI5_PCDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \
| ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \
| ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) )
#define MIBSPI5_PCPSL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \
| ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \
| ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \
| ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) )
#define MIBSPI5_DELAY_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define MIBSPI5_FMT0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI5_FMT1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI5_FMT2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI5_FMT3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \
| ( uint32 ) ( ( uint32 ) 16U << 0U ) )
#define MIBSPI5_MIBSPIE_CONFIGVALUE 0x501U
#define MIBSPI5_LTGPEND_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) )
#define MIBSPI5_TGCTRL0_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) ) )
#define MIBSPI5_TGCTRL1_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) 8U << 8U ) ) )
#define MIBSPI5_TGCTRL2_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) )
#define MIBSPI5_TGCTRL3_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) )
#define MIBSPI5_TGCTRL4_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI5_TGCTRL5_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI5_TGCTRL6_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI5_TGCTRL7_CONFIGVALUE \
( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \
| ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \
| ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) )
#define MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U )
/**
* @defgroup MIBSPI MIBSPI
* @brief Multi-Buffered Serial Peripheral Interface Module.
*
* The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a
*serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the
*device at a programmed bit-transfer rate. The MibSPI has a programmable buffer memory
*that enables programmed transmission to be completed without CPU intervention
*
* Related Files
* - reg_mibspi.h
* - mibspi.h
* - mibspi.c
* @addtogroup MIBSPI
* @{
*/
/* MIBSPI Interface Functions */
void mibspiInit( void );
boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi );
void mibspiOutofReset( mibspiBASE_t * mibspi );
void mibspiReset( mibspiBASE_t * mibspi );
void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port );
void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data );
uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data );
void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group );
boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group );
void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level );
void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group );
void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype );
void mibspiDisableLoopback( mibspiBASE_t * mibspi );
void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT );
void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type );
void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type );
void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type );
void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type );
void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type );
/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
* @brief Error interrupt callback
* @param[in] mibspi - mibSpi module base address
* @param[in] flags - Copy of error interrupt flags
*
* This is a error callback that is provided by the application and is call upon
* an error interrupt. The paramer passed to the callback is a copy of the error
* interrupt flag register.
*/
void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags );
/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
* @brief Transfer complete notification callback
* @param[in] mibspi - mibSpi module base address
* @param[in] group - Transfer group
*
* This is a callback function provided by the application. It is call when
* a transfer is complete. The parameter is the transfer group that triggered
* the interrupt.
*/
void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file nmpu.h
* @brief NMPU Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the NMPU driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NMPU_H_
#define NMPU_H_
#include "reg_nmpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
typedef enum nmpuRegion
{
NMPU_REGION0 = 0U,
NMPU_REGION1 = 1U,
NMPU_REGION2 = 2U,
NMPU_REGION3 = 3U,
NMPU_REGION4 = 4U,
NMPU_REGION5 = 5U,
NMPU_REGION6 = 6U,
NMPU_REGION7 = 7U
} nmpuReg_t;
typedef enum nmpuAccessPermission
{
NMPU_PRIV_NA_USER_NA = 0U,
NMPU_PRIV_RW_USER_NA = 1U,
NMPU_PRIV_RW_USER_RO = 2U,
NMPU_PRIV_RW_USER_RW = 3U,
NMPU_PRIV_RO_USER_NA = 5U,
NMPU_PRIV_RO_USER_RO = 6U
} nmpuAP_t;
typedef enum nmpuRegionSize
{
NMPU_SIZE_32_BYTES = 0x4U,
NMPU_SIZE_64_BYTES = 0x5U,
NMPU_SIZE_128_BYTES = 0x6U,
NMPU_SIZE_256_BYTES = 0x7U,
NMPU_SIZE_512_BYTES = 0x8U,
NMPU_SIZE_1_KB = 0x9U,
NMPU_SIZE_2_KB = 0xAU,
NMPU_SIZE_4_KB = 0xBU,
NMPU_SIZE_8_KB = 0xCU,
NMPU_SIZE_16_KB = 0xDU,
NMPU_SIZE_32_KB = 0xEU,
NMPU_SIZE_64_KB = 0xFU,
NMPU_SIZE_128_KB = 0x10U,
NMPU_SIZE_256_KB = 0x11U,
NMPU_SIZE_512_KB = 0x12U,
NMPU_SIZE_1_MB = 0x13U,
NMPU_SIZE_2_MB = 0x14U,
NMPU_SIZE_4_MB = 0x15U,
NMPU_SIZE_8_MB = 0x16U,
NMPU_SIZE_16_MB = 0x17U,
NMPU_SIZE_32_MB = 0x18U,
NMPU_SIZE_64_MB = 0x19U,
NMPU_SIZE_128_MB = 0x1AU,
NMPU_SIZE_256_MB = 0x1BU,
NMPU_SIZE_512_MB = 0x1CU,
NMPU_SIZE_1_GB = 0x1DU,
NMPU_SIZE_2_GB = 0x1EU,
NMPU_SIZE_4_GB = 0x1FU
} nmpuRegionSize_t;
typedef enum nmpuError
{
NMPU_ERROR_NONE,
NMPU_ERROR_AP_READ,
NMPU_ERROR_AP_WRITE,
NMPU_ERROR_BG_READ,
NMPU_ERROR_BG_WRITE
} nmpuErr_t;
typedef struct nmpuRegionAttributes
{
uint32 baseaddr;
nmpuReg_t regionsize;
nmpuAP_t accesspermission;
} nmpuRegionAttributes_t;
/**
* @defgroup NMPU NMPU
* @brief System Memory Protection Unit
*
* Related files:
* - reg_nmpu.h
* - sys_nmpu.h
* - sys_nmpu.c
*
* @addtogroup NMPU
* @{
*/
void nmpuEnable( nmpuBASE_t * nmpu );
void nmpuDisable( nmpuBASE_t * nmpu );
void nmpuEnableErrorGen( nmpuBASE_t * nmpu );
void nmpuDisableErrorGen( nmpuBASE_t * nmpu );
boolean nmpuEnableRegion( nmpuBASE_t * nmpu,
nmpuReg_t region,
nmpuRegionAttributes_t config );
boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region );
nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu );
nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu );
uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu );
void nmpuClearErrorStatus( nmpuBASE_t * nmpu );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* NMPU_H_ */

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h
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/*
* DP83640.h
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _PHY_DP83640_H_
#define _PHY_DP83640_H_
/* USER CODE BEGIN (0) */
/* USER CODE END */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @enum PHY_timestamp
* @brief Alias names for transmit and receive timestamps
* This enumeration is used to provide alias names for getting the transmit and receive
* timestamps from the Dp83640GetTimeStamp API.
*/
typedef enum phyTimeStamp
{
Txtimestamp = 1, /*Transmit Timestamp*/
Rxtimestamp = 2 /*Receive Timestamp */
} phyTimeStamp_t;
/* PHY register offset definitions */
#define PHY_BCR ( 0u )
#define PHY_BSR ( 1u )
#define PHY_ID1 ( 2u )
#define PHY_ID2 ( 3u )
#define PHY_AUTONEG_ADV ( 4u )
#define PHY_LINK_PARTNER_ABLTY ( 5u )
#define PHY_LINK_PARTNER_SPD ( 16u )
#define PHY_TXTS ( 28u )
#define PHY_RXTS ( 29u )
/* PHY status definitions */
#define PHY_ID_SHIFT ( 16u )
#define PHY_SOFTRESET ( 0x8000U )
#define PHY_AUTONEG_ENABLE ( 0x1000u )
#define PHY_AUTONEG_RESTART ( 0x0200u )
#define PHY_AUTONEG_COMPLETE ( 0x0020u )
#define PHY_AUTONEG_INCOMPLETE ( 0x0000u )
#define PHY_AUTONEG_STATUS ( 0x0020u )
#define PHY_AUTONEG_ABLE ( 0x0008u )
#define PHY_LPBK_ENABLE ( 0x4000u )
#define PHY_LINK_STATUS ( 0x0004u )
#define PHY_INVALID_TYPE ( 0x0u )
/* PHY ID. The LSB nibble will vary between different phy revisions */
#define DP83640_PHY_ID ( 0x0007C0F0u )
#define DP83640_PHY_ID_REV_MASK ( 0x0000000Fu )
/* Pause operations */
#define DP83640_PAUSE_NIL ( 0x0000u )
#define DP83640_PAUSE_SYM ( 0x0400u )
#define DP83640_PAUSE_ASYM ( 0x0800u )
#define DP83640_PAUSE_BOTH_SYM_ASYM ( 0x0C00u )
/* 100 Base TX Full Duplex capablity */
#define DP83640_100BTX_HD ( 0x0000u )
#define DP83640_100BTX_FD ( 0x0100u )
/* 100 Base TX capability */
#define DP83640_NO_100BTX ( 0x0000u )
#define DP83640_100BTX ( 0x0080u )
/* 10 BaseT duplex capabilities */
#define DP83640_10BT_HD ( 0x0000u )
#define DP83640_10BT_FD ( 0x0040u )
/* 10 BaseT ability*/
#define DP83640_NO_10BT ( 0x0000u )
#define DP83640_10BT ( 0x0020u )
/**************************************************************************
API function Prototypes
***************************************************************************/
extern uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal );
extern boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
extern boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr,
uint32 phyAddr,
volatile uint32 retries );
extern uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr,
uint32 phyAddr,
phyTimeStamp_t type );
extern void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
/* USER CODE BEGIN (2) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif

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/*
* Tlk111.h
*/
/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com
* ALL RIGHTS RESERVED
*/
#ifndef _PHY_TLK111_H_
#define _PHY_TLK111_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @enum PHY_timestamp
* @brief Alias names for transmit and receive timestamps
* This enumeration is used to provide alias names for getting the transmit and receive
* timestamps from the Tlk111GetTimeStamp API.
*/
typedef enum phyTimeStamp
{
Txtimestamp = 1, /*Transmit Timestamp*/
Rxtimestamp = 2 /*Receive Timestamp */
} phyTimeStamp_t;
/* PHY register offset definitions */
#define PHY_BCR ( 0u )
#define PHY_BSR ( 1u )
#define PHY_ID1 ( 2u )
#define PHY_ID2 ( 3u )
#define PHY_AUTONEG_ADV ( 4u )
#define PHY_LINK_PARTNER_ABLTY ( 5u )
#define PHY_LINK_PARTNER_SPD ( 16u )
#define PHY_SWSCR1 ( 9u )
#define PHY_SWSCR2 ( 10u )
#define PHY_SWSCR3 ( 11u )
#define PHY_TXTS ( 28u )
#define PHY_RXTS ( 29u )
/* PHY status definitions */
#define PHY_ID_SHIFT ( 16u )
#define PHY_SOFTRESET ( 0x8000U )
#define PHY_AUTONEG_ENABLE ( 0x1000u )
#define PHY_AUTONEG_RESTART ( 0x0200u )
#define PHY_AUTONEG_COMPLETE ( 0x0020u )
#define PHY_AUTONEG_INCOMPLETE ( 0x0000u )
#define PHY_AUTONEG_STATUS ( 0x0020u )
#define PHY_AUTONEG_ABLE ( 0x0008u )
#define PHY_LPBK_ENABLE ( 0x4000u )
#define PHY_LINK_STATUS ( 0x0004u )
#define PHY_INVALID_TYPE ( 0x0u )
/* PHY ID. The LSB nibble will vary between different phy revisions */
#define Tlk111_PHY_ID ( 0x2000A212 )
#define Tlk111_PHY_ID_REV_MASK ( 0x0000000Fu )
#define Tlk111_PHY_ID_OUI ( 0x2000A000 )
#define Tlk111_PHY_ID_OUI_MASK ( 0xFFFFFC00 )
/* Pause operations */
#define Tlk111_PAUSE_NIL ( 0x0000u )
#define Tlk111_PAUSE_SYM ( 0x0400u )
#define Tlk111_PAUSE_ASYM ( 0x0800u )
#define Tlk111_PAUSE_BOTH_SYM_ASYM ( 0x0C00u )
/* 100 Base TX Full Duplex capablity */
#define Tlk111_100BTX_HD ( 0x0000u )
#define Tlk111_100BTX_FD ( 0x0100u )
/* 100 Base TX capability */
#define Tlk111_NO_100BTX ( 0x0000u )
#define Tlk111_100BTX ( 0x0080u )
/* 10 BaseT duplex capabilities */
#define Tlk111_10BT_HD ( 0x0000u )
#define Tlk111_10BT_FD ( 0x0040u )
/* 10 BaseT ability*/
#define Tlk111_NO_10BT ( 0x0000u )
#define Tlk111_10BT ( 0x0020u )
/* Software Strap Register 1 */
#define Tlk111_SWStrapDone ( 1u << 15 )
#define Tlk111_Auto_MDIX_Ena ( 1u << 14 )
#define Tlk111_Auto_Neg_Ena ( 1u << 13 )
#define Tlk111_Auto_AnMode_10BT_HD ( 0u << 11 )
#define Tlk111_Auto_AnMode_10BT_FD ( 1u << 11 )
#define Tlk111_Auto_AnMode_100BT_HD ( 2u << 11 )
#define Tlk111_Auto_AnMode_100BT_FD ( 3u << 11 )
#define Tlk111_Force_LEDMode1 ( 1u << 10 )
#define Tlk111_RMII_Enhanced ( 1u << 9 )
#define Tlk111_TDR_AutoRun ( 1u << 8 )
#define Tlk111_LinkLoss_Recovery ( 1u << 8 )
#define Tlk111_FastAutoMdix ( 1u << 6 )
#define Tlk111_RobustAutoMdix ( 1u << 5 )
#define Tlk111_FastAnEn ( 1u << 4 )
#define Tlk111_FastAnSel0 ( 0u << 2 )
#define Tlk111_FastAnSel1 ( 1u << 2 )
#define Tlk111_FastAnSel2 ( 2u << 2 )
#define Tlk111_FastRxDvDetect ( 1u << 1 )
#define Tlk111_IntPdn_InterruptOut ( 1u << 0 )
/* Software Strap Register 2 */
#define Tlk111_100BT_Force_FE_LinkDrop ( 1u << 15 )
#define Tlk111_Rsv1 ( 2u << 7 )
#define Tlk111_FastLinkUpParallel ( 1u << 6 )
#define Tlk111_ExtendedFDAbility ( 1u << 5 )
#define Tlk111_ExtendedLEDLink ( 1u << 4 )
#define Tlk111_IsolateMII_100BT_HD ( 1u << 3 )
#define Tlk111_RXERR_DuringIdle ( 1u << 2 )
#define Tlk111_OddNibbleDetectDisable ( 1u << 1 )
#define Tlk111_RMII_Use_RXCLK ( 1u << 0 )
#define Tlk111_RMII_Use_XI ( 0u << 0 )
/* Software Strap Register 2 */
#define Tlk111_FastLinkDown ( 1u << 10 )
#define Tlk111_PolaritySwap ( 1u << 6 )
#define Tlk111_MDIXSwap ( 1u << 5 )
#define Tlk111_Bypass4B5B ( 1u << 4 )
#define Tlk111_FastLinkDownRxErrCnt ( 1u << 3 )
#define Tlk111_FastLinkDownMLT3ErrCnt ( 1u << 2 )
#define Tlk111_FastLinkDownLowSnr ( 1u << 1 )
#define Tlk111_FastLinkDownSigLoss ( 1u << 0 )
/* The Values for SWSCR Registers */
#define Tlk111_SWSCR1_Val \
( Tlk111_Auto_MDIX_Ena | Tlk111_Auto_Neg_Ena | Tlk111_Auto_AnMode_100BT_FD \
| Tlk111_Force_LEDMode1 | Tlk111_IntPdn_InterruptOut )
#define Tlk111_SWSCR2_Val ( Tlk111_Rsv1 | Tlk111_RXERR_DuringIdle )
#define Tlk111_SWSCR3_Val ( 0u )
/**************************************************************************
API function Prototypes
***************************************************************************/
extern uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal );
extern boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
extern boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr,
uint32 phyAddr,
volatile uint32 retries );
extern uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr,
uint32 phyAddr,
phyTimeStamp_t type );
extern void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr );
extern boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr,
uint32 phyAddr,
uint16 * ptnerAblty );
#ifdef __cplusplus
}
#endif
#endif

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/** @file pom.h
* @brief POM Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __POM_H__
#define __POM_H__
#include "reg_pom.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum pom_region_size
* @brief Alias names for pom region size
* This enumeration is used to provide alias names for POM region size:
*/
enum pom_region_size
{
SIZE_32BYTES = 0U,
SIZE_64BYTES = 1U,
SIZE_128BYTES = 2U,
SIZE_256BYTES = 3U,
SIZE_512BYTES = 4U,
SIZE_1KB = 5U,
SIZE_2KB = 6U,
SIZE_4KB = 7U,
SIZE_8KB = 8U,
SIZE_16KB = 9U,
SIZE_32KB = 10U,
SIZE_64KB = 11U,
SIZE_128KB = 12U,
SIZE_256KB = 13U
};
/** @def INTERNAL_RAM
* @brief Alias name for Internal RAM
*/
#define INTERNAL_RAM 0x08000000U
/** @def SDRAM
* @brief Alias name for SD RAM
*/
#define SDRAM 0x80000000U
/** @def ASYNC_MEMORY
* @brief Alias name for Async RAM
*/
#define ASYNC_MEMORY 0x60000000U
typedef uint32 REGION_t;
/** @struct REGION_CONFIG_ST
* @brief POM region configuration
*/
typedef struct
{
uint32 Prog_Reg_Sta_Addr;
uint32 Ovly_Reg_Sta_Addr;
uint32 Reg_Size;
} REGION_CONFIG_t;
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Configuration registers */
typedef struct pom_config_reg
{
uint32 CONFIG_POMGLBCTRL;
uint32 CONFIG_POMPROGSTART0;
uint32 CONFIG_POMOVLSTART0;
uint32 CONFIG_POMREGSIZE0;
uint32 CONFIG_POMPROGSTART1;
uint32 CONFIG_POMOVLSTART1;
uint32 CONFIG_POMREGSIZE1;
uint32 CONFIG_POMPROGSTART2;
uint32 CONFIG_POMOVLSTART2;
uint32 CONFIG_POMREGSIZE2;
uint32 CONFIG_POMPROGSTART3;
uint32 CONFIG_POMOVLSTART3;
uint32 CONFIG_POMREGSIZE3;
uint32 CONFIG_POMPROGSTART4;
uint32 CONFIG_POMOVLSTART4;
uint32 CONFIG_POMREGSIZE4;
uint32 CONFIG_POMPROGSTART5;
uint32 CONFIG_POMOVLSTART5;
uint32 CONFIG_POMREGSIZE5;
uint32 CONFIG_POMPROGSTART6;
uint32 CONFIG_POMOVLSTART6;
uint32 CONFIG_POMREGSIZE6;
uint32 CONFIG_POMPROGSTART7;
uint32 CONFIG_POMOVLSTART7;
uint32 CONFIG_POMREGSIZE7;
uint32 CONFIG_POMPROGSTART8;
uint32 CONFIG_POMOVLSTART8;
uint32 CONFIG_POMREGSIZE8;
uint32 CONFIG_POMPROGSTART9;
uint32 CONFIG_POMOVLSTART9;
uint32 CONFIG_POMREGSIZE9;
uint32 CONFIG_POMPROGSTART10;
uint32 CONFIG_POMOVLSTART10;
uint32 CONFIG_POMREGSIZE10;
uint32 CONFIG_POMPROGSTART11;
uint32 CONFIG_POMOVLSTART11;
uint32 CONFIG_POMREGSIZE11;
uint32 CONFIG_POMPROGSTART12;
uint32 CONFIG_POMOVLSTART12;
uint32 CONFIG_POMREGSIZE12;
uint32 CONFIG_POMPROGSTART13;
uint32 CONFIG_POMOVLSTART13;
uint32 CONFIG_POMREGSIZE13;
uint32 CONFIG_POMPROGSTART14;
uint32 CONFIG_POMOVLSTART14;
uint32 CONFIG_POMREGSIZE14;
uint32 CONFIG_POMPROGSTART15;
uint32 CONFIG_POMOVLSTART15;
uint32 CONFIG_POMREGSIZE15;
uint32 CONFIG_POMPROGSTART16;
uint32 CONFIG_POMOVLSTART16;
uint32 CONFIG_POMREGSIZE16;
uint32 CONFIG_POMPROGSTART17;
uint32 CONFIG_POMOVLSTART17;
uint32 CONFIG_POMREGSIZE17;
uint32 CONFIG_POMPROGSTART18;
uint32 CONFIG_POMOVLSTART18;
uint32 CONFIG_POMREGSIZE18;
uint32 CONFIG_POMPROGSTART19;
uint32 CONFIG_POMOVLSTART19;
uint32 CONFIG_POMREGSIZE19;
uint32 CONFIG_POMPROGSTART20;
uint32 CONFIG_POMOVLSTART20;
uint32 CONFIG_POMREGSIZE20;
uint32 CONFIG_POMPROGSTART21;
uint32 CONFIG_POMOVLSTART21;
uint32 CONFIG_POMREGSIZE21;
uint32 CONFIG_POMPROGSTART22;
uint32 CONFIG_POMOVLSTART22;
uint32 CONFIG_POMREGSIZE22;
uint32 CONFIG_POMPROGSTART23;
uint32 CONFIG_POMOVLSTART23;
uint32 CONFIG_POMREGSIZE23;
uint32 CONFIG_POMPROGSTART24;
uint32 CONFIG_POMOVLSTART24;
uint32 CONFIG_POMREGSIZE24;
uint32 CONFIG_POMPROGSTART25;
uint32 CONFIG_POMOVLSTART25;
uint32 CONFIG_POMREGSIZE25;
uint32 CONFIG_POMPROGSTART26;
uint32 CONFIG_POMOVLSTART26;
uint32 CONFIG_POMREGSIZE26;
uint32 CONFIG_POMPROGSTART27;
uint32 CONFIG_POMOVLSTART27;
uint32 CONFIG_POMREGSIZE27;
uint32 CONFIG_POMPROGSTART28;
uint32 CONFIG_POMOVLSTART28;
uint32 CONFIG_POMREGSIZE28;
uint32 CONFIG_POMPROGSTART29;
uint32 CONFIG_POMOVLSTART29;
uint32 CONFIG_POMREGSIZE29;
uint32 CONFIG_POMPROGSTART30;
uint32 CONFIG_POMOVLSTART30;
uint32 CONFIG_POMREGSIZE30;
uint32 CONFIG_POMPROGSTART31;
uint32 CONFIG_POMOVLSTART31;
uint32 CONFIG_POMREGSIZE31;
} pom_config_reg_t;
/* Configuration registers initial value for POM*/
#define POM_POMGLBCTRL_CONFIGVALUE ( ( uint32 ) INTERNAL_RAM | 0x00000005U )
#define POM_POMPROGSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU )
#define POM_POMOVLSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU )
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Values come from GUI drop down option" */
#define POM_POMREGSIZE0_CONFIGVALUE ( ( uint32 ) SIZE_64BYTES )
#define POM_POMPROGSTART1_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART1_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE1_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART2_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART2_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE2_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART3_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART3_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE3_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART4_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART4_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE4_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART5_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART5_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE5_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART6_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART6_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE6_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART7_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART7_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE7_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART8_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART8_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE8_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART9_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART9_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE9_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART10_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART10_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE10_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART11_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART11_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE11_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART12_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART12_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE12_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART13_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART13_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE13_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART14_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART14_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE14_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART15_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART15_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE15_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART16_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART16_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE16_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART17_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART17_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE17_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART18_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART18_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE18_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART19_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART19_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE19_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART20_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART20_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE20_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART21_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART21_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE21_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART22_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART22_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE22_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART23_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART23_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE23_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART24_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART24_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE24_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART25_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART25_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE25_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART26_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART26_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE26_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART27_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART27_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE27_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART28_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART28_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE28_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART29_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART29_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE29_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART30_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART30_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE30_CONFIGVALUE 0x00000000U
#define POM_POMPROGSTART31_CONFIGVALUE 0x00000000U
#define POM_POMOVLSTART31_CONFIGVALUE 0x00000000U
#define POM_POMREGSIZE31_CONFIGVALUE 0x00000000U
/**
* @defgroup POM POM
* @brief Parameter Overlay Module.
*
* The POM provides a mechanism to redirect accesses to non-volatile memory into a
* volatile memory internal or external to the device. The data requested by the CPU will
* be fetched from the overlay memory instead of the main non-volatile memory.
*
* Related Files
* - reg_pom.h
* - pom.h
* - pom.c
* @addtogroup POM
* @{
*/
/* POM Interface Functions */
void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num );
void POM_Reset( void );
void POM_Init( void );
void POM_Enable( void );
void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (2) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* __POM_H_*/

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/** @file reg_adc.h
* @brief ADC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ADC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_ADC_H__
#define __REG_ADC_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Adc Register Frame Definition */
/** @struct adcBase
* @brief ADC Register Frame Definition
*
* This type is used to access the ADC Registers.
*/
/** @typedef adcBASE_t
* @brief ADC Register Frame Type Definition
*
* This type is used to access the ADC Registers.
*/
typedef volatile struct adcBase
{
uint32 RSTCR; /**< 0x0000: Reset control register */
uint32 OPMODECR; /**< 0x0004: Operating mode control register */
uint32 CLOCKCR; /**< 0x0008: Clock control register */
uint32 CALCR; /**< 0x000C: Calibration control register */
uint32 GxMODECR[ 3U ]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */
uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */
uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */
uint32 GxINTENA[ 3U ]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register
*/
uint32 GxINTFLG[ 3U ]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */
uint32 GxINTCR[ 3U ]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */
uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */
uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */
uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */
uint32 BNDCR; /**< 0x0058: Buffer boundary control register */
uint32 BNDEND; /**< 0x005C: Buffer boundary end register */
uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */
uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */
uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */
uint32 EVSR; /**< 0x006C: Group 0 status register */
uint32 G1SR; /**< 0x0070: Group 1 status register */
uint32 G2SR; /**< 0x0074: Group 2 status register */
uint32 GxSEL[ 3U ]; /**< 0x0078-0x007C: Group 0-2 channel select register */
uint32 CALR; /**< 0x0084: Calibration register */
uint32 SMSTATE; /**< 0x0088: State machine state register */
uint32 LASTCONV; /**< 0x008C: Last conversion register */
struct
{
uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */
uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */
uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */
uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */
uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */
uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */
uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */
uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */
} GxBUF[ 3U ];
uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */
uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */
uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */
uint32 EVTDIR; /**< 0x00FC: Event pin direction register */
uint32 EVTOUT; /**< 0x0100: Event pin digital output register */
uint32 EVTIN; /**< 0x0104: Event pin digital input register */
uint32 EVTSET; /**< 0x0108: Event pin set register */
uint32 EVTCLR; /**< 0x010C: Event pin clear register */
uint32 EVTPDR; /**< 0x0110: Event pin open drain register */
uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */
uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */
uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */
uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */
uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */
uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */
uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */
uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */
uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */
uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */
uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */
uint32 rsvd1; /**< 0x0140: Reserved */
uint32 rsvd2; /**< 0x0144: Reserved */
uint32 rsvd3; /**< 0x0148: Reserved */
uint32 rsvd4; /**< 0x014C: Reserved */
uint32 rsvd5; /**< 0x0150: Reserved */
uint32 rsvd6; /**< 0x0154: Reserved */
uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */
uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */
uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */
uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */
uint32 GxFIFORESETCR[ 3U ]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register
*/
uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */
uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */
uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */
uint32 PARCR; /**< 0x0180: Parity control register */
uint32 PARADDR; /**< 0x0184: Parity error address register */
uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */
uint32 rsvd7; /**< 0x018C: Reserved */
uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control
Register */
uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register
*/
uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register
*/
uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */
uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */
uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */
uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */
uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */
uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */
} adcBASE_t;
/** @struct adcLUTEntry
* @brief ADC Look-Up Table Entry
*
* This type is used to access ADC Look-Up Table Entry
*/
/** @typedef adcLUTEntry_t
* @brief ADC Look-Up Table Entry
*
* This type is used to access the Look-Up Table Entry.
*/
typedef struct adcLUTEntry
{
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
uint8 EV_INT_CHN_MUX_SEL;
uint8 EV_EXT_CHN_MUX_SEL;
uint16 rsvd;
#else
uint16 rsvd;
uint8 EV_EXT_CHN_MUX_SEL;
uint8 EV_INT_CHN_MUX_SEL;
#endif
} adcLUTEntry_t;
/** @struct adcLUT
* @brief ADC Look-Up Table
*
* This type is used to access ADC Look-Up Table
*/
/** @typedef adcLUT_t
* @brief ADC Look-Up Table
*
* This type is used to access the ADC Look-Up Table.
*/
typedef volatile struct adcLUT
{
adcLUTEntry_t eventGroup[ 32 ];
adcLUTEntry_t Group1[ 32 ];
adcLUTEntry_t Group2[ 32 ];
} adcLUT_t;
/** @def adcREG1
* @brief ADC1 Register Frame Pointer
*
* This pointer is used by the ADC driver to access the ADC1 registers.
*/
#define adcREG1 ( ( adcBASE_t * ) 0xFFF7C000U )
/** @def adcREG2
* @brief ADC2 Register Frame Pointer
*
* This pointer is used by the ADC driver to access the ADC2 registers.
*/
#define adcREG2 ( ( adcBASE_t * ) 0xFFF7C200U )
/** @def adcRAM1
* @brief ADC1 RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC1 RAM.
*/
#define adcRAM1 ( *( volatile uint32 * ) 0xFF3E0000U )
/** @def adcRAM2
* @brief ADC2 RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC2 RAM.
*/
#define adcRAM2 ( *( volatile uint32 * ) 0xFF3A0000U )
/** @def adcPARRAM1
* @brief ADC1 Parity RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC1 Parity RAM.
*/
#define adcPARRAM1 ( *( volatile uint32 * ) ( 0xFF3E0000U + 0x1000U ) )
/** @def adcPARRAM2
* @brief ADC2 Parity RAM Pointer
*
* This pointer is used by the ADC driver to access the ADC2 Parity RAM.
*/
#define adcPARRAM2 ( *( volatile uint32 * ) ( 0xFF3A0000U + 0x1000U ) )
/** @def adcLUT1
* @brief ADC1 Look-Up Table
*
* This pointer is used by the ADC driver to access the ADC1 Look-Up Table.
*/
#define adcLUT1 ( ( adcLUT_t * ) ( 0xFF3E0000U + 0x2000U ) )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_can.h
* @brief CAN Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the CAN driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_CAN_H__
#define __REG_CAN_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Can Register Frame Definition */
/** @struct canBase
* @brief CAN Register Frame Definition
*
* This type is used to access the CAN Registers.
*/
/** @typedef canBASE_t
* @brief CAN Register Frame Type Definition
*
* This type is used to access the CAN Registers.
*/
typedef volatile struct canBase
{
uint32 CTL; /**< 0x0000: Control Register */
uint32 ES; /**< 0x0004: Error and Status Register */
uint32 EERC; /**< 0x0008: Error Counter Register */
uint32 BTR; /**< 0x000C: Bit Timing Register */
uint32 INT; /**< 0x0010: Interrupt Register */
uint32 TEST; /**< 0x0014: Test Register */
uint32 rsvd1; /**< 0x0018: Reserved */
uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */
uint32 rsvd11; /**< 0x0020: Reserved */
uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */
uint32 ECCDIAG_STAT; /**< 0x0028: ECC Diagnostic Status Register */
uint32 ECC_CS; /**< 0x002C: ECC Control and Status Register */
uint32 ECC_SERR; /**< 0x0030: ECC Single Bit Error code register */
uint32 rsvd2[ 19 ]; /**< 0x002C - 0x7C: Reserved */
uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */
uint32 TXRQX; /**< 0x0084: Transmission Request X Register */
uint32 TXRQx[ 4U ]; /**< 0x0088-0x0094: Transmission Request Registers */
uint32 NWDATX; /**< 0x0098: New Data X Register */
uint32 NWDATx[ 4U ]; /**< 0x009C-0x00A8: New Data Registers */
uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */
uint32 INTPNDx[ 4U ]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */
uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */
uint32 MSGVALx[ 4U ]; /**< 0x00C4-0x00D0: Message Valid Registers */
uint32 rsvd3; /**< 0x00D4: Reserved */
uint32 INTMUXx[ 4U ]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
uint32 rsvd4[ 6 ]; /**< 0x00E8: Reserved */
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
#else
uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
#endif
uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */
uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */
uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */
uint8 IF1DATx[ 8U ]; /**< 0x0110-0x0114: IF1 Data A and B Registers */
uint32 rsvd5[ 2 ]; /**< 0x0118: Reserved */
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */
uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
#else
uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */
#endif
uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */
uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */
uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */
uint8 IF2DATx[ 8U ]; /**< 0x0130-0x0134: IF2 Data A and B Registers */
uint32 rsvd6[ 2 ]; /**< 0x0138: Reserved */
uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */
uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */
uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */
uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */
uint8 IF3DATx[ 8U ]; /**< 0x0150-0x0154: IF3 Data A and B Registers */
uint32 rsvd7[ 2 ]; /**< 0x0158: Reserved */
uint32 IF3UEy[ 4U ]; /**< 0x0160-0x016C: IF3 Update Enable Registers */
uint32 rsvd8[ 28 ]; /**< 0x0170: Reserved */
uint32 TIOC; /**< 0x01E0: TX IO Control Register */
uint32 RIOC; /**< 0x01E4: RX IO Control Register */
} canBASE_t;
/** @def canREG1
* @brief CAN1 Register Frame Pointer
*
* This pointer is used by the CAN driver to access the CAN1 registers.
*/
#define canREG1 ( ( canBASE_t * ) 0xFFF7DC00U )
/** @def canREG2
* @brief CAN2 Register Frame Pointer
*
* This pointer is used by the CAN driver to access the CAN2 registers.
*/
#define canREG2 ( ( canBASE_t * ) 0xFFF7DE00U )
/** @def canREG3
* @brief CAN3 Register Frame Pointer
*
* This pointer is used by the CAN driver to access the CAN3 registers.
*/
#define canREG3 ( ( canBASE_t * ) 0xFFF7E000U )
/** @def canREG4
* @brief CAN4 Register Frame Pointer
*
* This pointer is used by the CAN driver to access the CAN4 registers.
*/
#define canREG4 ( ( canBASE_t * ) 0xFFF7E200U )
/** @def canRAM1
* @brief CAN1 Mailbox RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN1 RAM.
*/
#define canRAM1 ( *( volatile uint32 * ) 0xFF1E0000U )
/** @def canRAM2
* @brief CAN2 Mailbox RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN2 RAM.
*/
#define canRAM2 ( *( volatile uint32 * ) 0xFF1C0000U )
/** @def canRAM3
* @brief CAN3 Mailbox RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN3 RAM.
*/
#define canRAM3 ( *( volatile uint32 * ) 0xFF1A0000U )
/** @def canRAM4
* @brief CAN4 Mailbox RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN4 RAM.
*/
#define canRAM4 ( *( volatile uint32 * ) 0xFF180000U )
/** @def canPARRAM1
* @brief CAN1 Mailbox Parity RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN1 Parity RAM
* for testing RAM parity error detect logic.
*/
#define canPARRAM1 ( *( volatile uint32 * ) ( 0xFF1E0000U + 0x10U ) )
/** @def canPARRAM2
* @brief CAN2 Mailbox Parity RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN2 Parity RAM
* for testing RAM parity error detect logic.
*/
#define canPARRAM2 ( *( volatile uint32 * ) ( 0xFF1C0000U + 0x10U ) )
/** @def canPARRAM3
* @brief CAN3 Mailbox Parity RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN3 Parity RAM
* for testing RAM parity error detect logic.
*/
#define canPARRAM3 ( *( volatile uint32 * ) ( 0xFF1A0000U + 0x10U ) )
/** @def canPARRAM4
* @brief CAN4 Mailbox Parity RAM Pointer
*
* This pointer is used by the CAN driver to access the CAN4 Parity RAM
* for testing RAM parity error detect logic.
*/
#define canPARRAM4 ( *( volatile uint32 * ) ( 0xFF180000U + 0x10U ) )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_ccmr5.h
* @brief CCMR5 Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_CCMR5_H__
#define __REG_CCMR5_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Efc Register Frame Definition */
/** @struct ccmr5Base
* @brief Efc Register Frame Definition
*
* This type is used to access the Efc Registers.
*/
/** @typedef ccmr5BASE_t
* @brief Efc Register Frame Type Definition
*
* This type is used to access the Efc Registers.
*/
typedef volatile struct ccmr5Base
{
uint32 CCMSR1; /* 0x00 Status Register 1 */
uint32 CCMKEYR1; /* 0x04 Key Register 1 */
uint32 CCMSR2; /* 0x08 Status Register 2 */
uint32 CCMKEYR2; /* 0x0C Key Register 2 */
uint32 CCMSR3; /* 0x10 Status Register 3 */
uint32 CCMKEYR3; /* 0x14 Key Register 3 */
uint32 CCMPOLCNTRL; /* 0x18 Polarity Control Register */
uint32 CCMSR4; /* 0x1C Status Register 4 */
uint32 CCMKEYR4; /* 0x20 Key Register 4 */
uint32 CCMPDSTAT0; /* 0x24 Power Domain Status Register 0 */
} ccmr5BASE_t;
#define ccmr5REG ( ( ccmr5BASE_t * ) 0xFFFFF600U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_crc.h
* @brief CRC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the CRC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_CRC_H__
#define __REG_CRC_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Crc Register Frame Definition */
/** @struct crcBase
* @brief CRC Register Frame Definition
*
* This type is used to access the CRC Registers.
*/
/** @typedef crcBASE_t
* @brief CRC Register Frame Type Definition
*
* This type is used to access the CRC Registers.
*/
typedef volatile struct crcBase
{
uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/
uint32 rvd1; /**< 0x0004: reserved >**/
uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/
uint32 rvd2; /**< 0x000C: reserved >**/
uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/
uint32 rvd3; /**< 0x0014: reserved >**/
uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/
uint32 rvd4; /**< 0x001C: reserved >**/
uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/
uint32 rvd5; /**< 0x0024: reserved >**/
uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/
uint32 rvd6; /**< 0x002C: reserved >**/
uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/
uint32 rvd7; /**< 0x0034: reserved >**/
uint32 BUSY; /**< 0x0038: CRC Busy Register >**/
uint32 rvd8; /**< 0x003C: reserved >**/
uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/
uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/
uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/
uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
uint32 rvd9[ 3 ]; /**< 0x0054: reserved >**/
uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/
uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/
uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/
uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/
uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/
uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/
uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/
uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/
uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/
uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/
uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
uint32 rvd10[ 3 ]; /**< 0x0094: reserved >**/
uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/
uint32 PSA_SIGREGH2; /**< 0x00A4: Channel 2 PSA signature high register >**/
uint32 REGL2; /**< 0x00A8: Channel 2 CRC value low register >**/
uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/
uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/
uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/
uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/
uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/
} crcBASE_t;
/** @def crcREG1
* @brief CRC1 Register Frame Pointer
*
* This pointer is used by the CRC driver to access the CRC1 registers.
*/
#define crcREG1 ( ( crcBASE_t * ) 0xFE000000U )
/** @def crcREG2
* @brief CRC2 Register Frame Pointer
*
* This pointer is used by the CRC driver to access the CRC2 registers.
*/
#define crcREG2 ( ( crcBASE_t * ) 0xFB000000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_dcc.h
* @brief DCC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the DCC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_DCC_H__
#define __REG_DCC_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Dcc Register Frame Definition */
/** @struct dccBase
* @brief DCC Base Register Definition
*
* This structure is used to access the DCC module registers.
*/
/** @typedef dccBASE_t
* @brief DCC Register Frame Type Definition
*
* This type is used to access the DCC Registers.
*/
typedef volatile struct dccBase
{
uint32 GCTRL; /**< 0x0000: DCC Control Register */
uint32 REV; /**< 0x0004: DCC Revision Id Register */
uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */
uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */
uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */
uint32 STAT; /**< 0x0014: DCC Status Register */
uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */
uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */
uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */
uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */
uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */
} dccBASE_t;
/** @def dccREG1
* @brief DCC1 Register Frame Pointer
*
* This pointer is used by the DCC driver to access the dcc2 module registers.
*/
#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U )
/** @def dccREG2
* @brief DCC2 Register Frame Pointer
*
* This pointer is used by the DCC driver to access the dcc2 module registers.
*/
#define dccREG2 ( ( dccBASE_t * ) 0xFFFFF400U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_dma.h
* @brief DMA Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the DMA driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_DMA_H__
#define __REG_DMA_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* DMA Register Frame Definition */
/** @struct dmaBase
* @brief DMA Register Frame Definition
*
* This type is used to access the DMA Registers.
*/
/** @struct dmaBASE_t
* @brief DMA Register Definition
*
* This structure is used to access the DMA module egisters.
*/
typedef volatile struct dmaBase
{
uint32 GCTRL; /**< 0x0000: Global Control Register */
uint32 PEND; /**< 0x0004: Channel Pending Register */
uint32 FBREG; /**< 0x0008: Fall Back Register */
uint32 DMASTAT; /**< 0x000C: Status Register */
uint32 rsvd1; /**< 0x0010: Reserved */
uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */
uint32 rsvd2; /**< 0x0018: Reserved */
uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */
uint32 rsvd3; /**< 0x0020: Reserved */
uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */
uint32 rsvd4; /**< 0x0028: Reserved */
uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */
uint32 rsvd5; /**< 0x0030: Reserved */
uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */
uint32 rsvd6; /**< 0x0038: Reserved */
uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */
uint32 rsvd7; /**< 0x0040: Reserved */
uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */
uint32 rsvd8; /**< 0x0048: Reserved */
uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Reset */
uint32 rsvd9; /**< 0x0050: Reserved */
uint32 DREQASI[ 8U ]; /**< 0x0054 - 0x70: DMA Request Assignment Register */
uint32 rsvd10[ 8U ]; /**< 0x0074 - 0x90: Reserved */
uint32 PAR[ 4U ]; /**< 0x0094 - 0xA0: Port Assignment Register */
uint32 rsvd11[ 4U ]; /**< 0x00A4 - 0xB0: Reserved */
uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */
uint32 rsvd12; /**< 0x00B8: Reserved */
uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */
uint32 rsvd13; /**< 0x00C0: Reserved */
uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */
uint32 rsvd14; /**< 0x00C8: Reserved */
uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */
uint32 rsvd15; /**< 0x00D0: Reserved */
uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */
uint32 rsvd16; /**< 0x00D8: Reserved */
uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */
uint32 rsvd17; /**< 0x00E0: Reserved */
uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */
uint32 rsvd18; /**< 0x00E8: Reserved */
uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */
uint32 rsvd19; /**< 0x00F0: Reserved */
uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */
uint32 rsvd20; /**< 0x00F8: Reserved */
uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */
uint32 rsvd21; /**< 0x0100: Reserved */
uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */
uint32 rsvd22; /**< 0x0108: Reserved */
uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */
uint32 rsvd23; /**< 0x0110: Reserved */
uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */
uint32 rsvd24; /**< 0x0118: Reserved */
uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */
uint32 rsvd25; /**< 0x0120: Reserved */
uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */
uint32 rsvd26; /**< 0x0128: Reserved */
uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */
uint32 rsvd27; /**< 0x0130: Reserved */
uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */
uint32 rsvd28; /**< 0x0138: Reserved */
uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */
uint32 rsvd29; /**< 0x0140: Reserved */
uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */
uint32 rsvd30; /**< 0x0148: Reserved */
uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */
uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */
uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */
uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */
uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */
uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */
uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */
uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */
uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */
uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */
uint32 rsvd31; /**< 0x0174: Reserved */
uint32 PTCRL; /**< 0x0178: Port Control Register */
uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */
uint32 DCTRL; /**< 0x0180: Debug Control */
uint32 WPR; /**< 0x0184: Watch Point Register */
uint32 WMR; /**< 0x0188: Watch Mask Register */
uint32 FAACSADDR; /**< 0x018C: */
uint32 FAACDADDR; /**< 0x0190: */
uint32 FAACTC; /**< 0x0194: */
uint32 FBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */
uint32 FBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */
uint32 FBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */
uint32 rsvd32; /**< 0x01A4: Reserved */
uint32 DMAPCR; /**< 0x01A8: Parity Control Register */
uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */
uint32 DMAMPCTRL1; /**< 0x01B0: DMA Memory Protection Control Register */
uint32 DMAMPST1; /**< 0x01B4: DMA Memory Protection Status Register */
struct
{
uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region
Start Address Register */
uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region
Start Address Register */
} DMAMPR_L[ 4U ];
uint32 DMAMPCTRL2; /**< 0x01D8: Memory Protection Control Register */
uint32 DMAPST2; /**< 0x01DC: Memory Protection Status Register */
struct
{
uint32 STARTADD; /**< 0x01E0, 0x01E8, 0x01F0, 0x01F8: DMA Memory Protection
Region Start Address Register */
uint32 ENDADD; /**< 0x01E4, 0x01EC, 0x01F4, 0x01FC: DMA Memory Protection Region
Start Address Register */
} DMAMPR_H[ 4U ];
uint32 rsvd33[ 10U ]; /**< 0x0200 - 0x224: Reserved */
uint32 DMASECCCTRL; /**< 0x0228: DMA Single bit ECC Control RegisteR */
uint32 rsvd34; /**< 0x022C: Reserved */
uint32 DMAECCSBE; /**< 0x0230: DMA ECC Single bit Error Address Register */
uint32 rsvd35[ 3U ]; /**< 0x0234 - 0x023C: Reserved */
uint32 FIFOASTATREG; /**< 0x0240: FIFO A Status Register */
uint32 FIFOBSTATREG; /**< 0x0244: FIFO B Status Register */
uint32 rsvd37[ 58U ]; /**< 0x0248 - 0x032C: Reserved */
uint32 DMAREQPS1; /**< 0x0330: DMA Request Polarity Select Register 1 */
uint32 DMAREQPS0; /**< 0x0334: DMA Request Polarity Select Register 0 */
uint32 rsvd38[ 32 ]; /**< 0x0338 - 0x033C: Reserved */
uint32 TERECTRL; /**< 0x0340: TER Event Control Register */
uint32 TERFLAG; /**< 0x0344: TER Event Flag Register */
uint32 TERROFFSET; /**< 0x0348: TER Event Channel Offset Register */
} dmaBASE_t;
typedef volatile struct
{
struct /* 0x000-0x400 */
{
uint32 ISADDR;
uint32 IDADDR;
uint32 ITCOUNT;
uint32 rsvd1;
uint32 CHCTRL;
uint32 EIOFF;
uint32 FIOFF;
uint32 rsvd2;
} PCP[ 32U ];
struct /* 0x400-0x800 */
{
uint32 res[ 256U ];
} RESERVED;
struct /* 0x800-0xA00 */
{
uint32 CSADDR;
uint32 CDADDR;
uint32 CTCOUNT;
uint32 rsvd3;
} WCP[ 32U ];
} dmaRAMBASE_t;
#define dmaRAMREG ( ( dmaRAMBASE_t * ) 0xFFF80000U )
/** @def dmaREG
* @brief DMA1 Register Frame Pointer
*
* This pointer is used by the DMA driver to access the DMA module registers.
*/
#define dmaREG ( ( dmaBASE_t * ) 0xFFFFF000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif /* REG_DMA_H_ */

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/** @file reg_dmm.h
* @brief DMM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the DMM driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_DMM_H__
#define __REG_DMM_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Dmm Register Frame Definition */
/** @struct dmmBase
* @brief DMM Base Register Definition
*
* This structure is used to access the DMM module registers.
*/
/** @typedef dmmBASE_t
* @brief DMM Register Frame Type Definition
*
* This type is used to access the DMM Registers.
*/
typedef volatile struct dmmBase
{
uint32 GLBCTRL; /**< 0x0000: Global control register 0 */
uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */
uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */
uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */
uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */
uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */
uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */
uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */
uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */
uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */
uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */
uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */
uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */
uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */
uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */
uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */
uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */
uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */
uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */
uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */
uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */
uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */
uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */
uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */
uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */
uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */
uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */
uint32 PC0; /**< 0x006C: DMM Pin Control 0 */
uint32 PC1; /**< 0x0070: DMM Pin Control 1 */
uint32 PC2; /**< 0x0074: DMM Pin Control 2 */
uint32 PC3; /**< 0x0078: DMM Pin Control 3 */
uint32 PC4; /**< 0x007C: DMM Pin Control 4 */
uint32 PC5; /**< 0x0080: DMM Pin Control 5 */
uint32 PC6; /**< 0x0084: DMM Pin Control 6 */
uint32 PC7; /**< 0x0088: DMM Pin Control 7 */
uint32 PC8; /**< 0x008C: DMM Pin Control 8 */
} dmmBASE_t;
/** @def dmmREG
* @brief DMM Register Frame Pointer
*
* This pointer is used by the DMM driver to access the DMM module registers.
*/
#define dmmREG ( ( dmmBASE_t * ) 0xFFFFF700U )
/** @def dmmPORT
* @brief DMM Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of DMM
* (use the GIO drivers to access the port pins).
*/
#define dmmPORT ( ( gioPORT_t * ) 0xFFFFF770U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_ecap.h
* @brief ECAP Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ECAP driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_ECAP_H__
#define __REG_ECAP_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Ecap Register Frame Definition */
/** @struct ecapBASE
* @brief ECAP Register Frame Definition
*
* This type is used to access the ECAP Registers.
*/
/** @typedef ecapBASE_t
* @brief ECAP Register Frame Type Definition
*
* This type is used to access the ECAP Registers.
*/
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
typedef volatile struct ecapBASE
{
uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/
uint32 CTRPHS; /**< 0x0004 Counter phase Register*/
uint32 CAP1; /**< 0x0008 Capture 1 Register*/
uint32 CAP2; /**< 0x000C Capture 2 Register*/
uint32 CAP3; /**< 0x0010 Capture 3 Register*/
uint32 CAP4; /**< 0x0014 Capture 4 Register*/
uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/
uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/
uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/
uint16 ECEINT; /**< 0x002C Interrupt enable Register*/
uint16 ECFLG; /**< 0x002E Interrupt flags Register*/
uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/
uint16 ECFRC; /**< 0x0032 Interrupt force Register*/
uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/
} ecapBASE_t;
#else
typedef volatile struct ecapBASE
{
uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/
uint32 CTRPHS; /**< 0x0004 Counter phase Register*/
uint32 CAP1; /**< 0x0008 Capture 1 Register*/
uint32 CAP2; /**< 0x000C Capture 2 Register*/
uint32 CAP3; /**< 0x0010 Capture 3 Register*/
uint32 CAP4; /**< 0x0014 Capture 4 Register*/
uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/
uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/
uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/
uint16 ECFLG; /**< 0x002E Interrupt flags Register*/
uint16 ECEINT; /**< 0x002C Interrupt enable Register*/
uint16 ECFRC; /**< 0x0032 Interrupt force Register*/
uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/
uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/
} ecapBASE_t;
#endif
/** @def ecapREG1
* @brief ECAP1 Register Frame Pointer
*
* This pointer is used by the ECAP driver to access the ECAP1 registers.
*/
#define ecapREG1 ( ( ecapBASE_t * ) 0xFCF79300U )
/** @def ecapREG2
* @brief ECAP2 Register Frame Pointer
*
* This pointer is used by the ECAP driver to access the ECAP2 registers.
*/
#define ecapREG2 ( ( ecapBASE_t * ) 0xFCF79400U )
/** @def ecapREG3
* @brief ECAP3 Register Frame Pointer
*
* This pointer is used by the ECAP driver to access the ECAP3 registers.
*/
#define ecapREG3 ( ( ecapBASE_t * ) 0xFCF79500U )
/** @def ecapREG4
* @brief ECAP4 Register Frame Pointer
*
* This pointer is used by the ECAP driver to access the ECAP4 registers.
*/
#define ecapREG4 ( ( ecapBASE_t * ) 0xFCF79600U )
/** @def ecapREG5
* @brief ECAP5 Register Frame Pointer
*
* This pointer is used by the ECAP driver to access the ECAP5 registers.
*/
#define ecapREG5 ( ( ecapBASE_t * ) 0xFCF79700U )
/** @def ecapREG6
* @brief ECAP6 Register Frame Pointer
*
* This pointer is used by the ECAP driver to access the ECAP6 registers.
*/
#define ecapREG6 ( ( ecapBASE_t * ) 0xFCF79800U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_efc.h
* @brief EFC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_EFC_H__
#define __REG_EFC_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Efc Register Frame Definition */
/** @struct efcBase
* @brief Efc Register Frame Definition
*
* This type is used to access the Efc Registers.
*/
/** @typedef efcBASE_t
* @brief Efc Register Frame Type Definition
*
* This type is used to access the Efc Registers.
*/
typedef volatile struct efcBase
{
uint32 rsvd1; /* 0x00 RESERVED */
uint32 rsvd2; /* 0x04 RESERVED */
uint32 rsvd3; /* 0x08 RESERVED */
uint32 rsvd4; /* 0x0C RESERVED */
uint32 rsvd5; /* 0x10 RESERVED */
uint32 rsvd6; /* 0x14 RESERVED */
uint32 rsvd7; /* 0x18 RESERVED */
uint32 BOUND; /* 0x1C RESERVED */
uint32 rsvd8; /* 0x20 RESERVED */
uint32 rsvd9; /* 0x24 RESERVED */
uint32 rsvd10; /* 0x28 RESERVED */
uint32 PINS; /* 0x2C RESERVED */
uint32 rsvd11; /* 0x30 RESERVED */
uint32 rsvd12; /* 0x34 RESERVED */
uint32 rsvd13; /* 0x38 RESERVED */
uint32 ERR_STAT; /* 0x3C RESERVED */
uint32 rsvd14; /* 0x40 RESERVED */
uint32 rsvd15; /* 0x44 RESERVED */
uint32 ST_CY; /* 0x48 RESERVED */
uint32 ST_SIG; /* 0x4C RESERVED */
} efcBASE_t;
#define efcREG ( ( efcBASE_t * ) 0xFFF8C000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_emif.h
* @brief EMIF Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the EMIF driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_EMIF_H__
#define __REG_EMIF_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Emif Register Frame Definition */
/** @struct emifBASE_t
* @brief emifBASE Register Definition
*
* This structure is used to access the EMIF module registers.
*/
typedef volatile struct emifBase
{
uint32 MIDR; /**< 0x0000 Module ID Register */
uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/
uint32 SDCR; /**< 0x0008 SDRAM configuration register */
uint32 SDRCR; /**< 0x000C Set Interrupt Enable Register */
uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */
uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */
uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */
uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */
uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */
uint32 dummy1[ 6 ]; /** reserved **/
uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */
uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/
uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */
uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */
uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */
uint32 dummy2[ 6 ]; /** reserved **/
uint32 PMCR; /**< 0x0068 Page Mode Control Register*/
} emifBASE_t;
#define emifREG ( ( emifBASE_t * ) 0xFCFFE800U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif
#endif

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/** @file reg_epc.h
* @brief EPC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the EPC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_EPC_H__
#define __REG_EPC_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* EPC Register Frame Definition */
/** @struct epcBase
* @brief EPC Base Register Definition
*
* This structure is used to access the EPC module registers.
*/
/** @typedef epcBASE_t
* @brief EPC Register Frame Type Definition
*
* This type is used to access the EPC Registers.
*/
typedef volatile struct epcBase
{
uint32 EPCREVID; /**< 0x0000: EPC REVID Register */
uint32 EPCCNTRL; /**< 0x0004: EPC Control Register */
uint32 UERRSTAT; /**< 0x0008: Uncorrectable Error Status Register */
uint32 EPCERRSTAT; /**< 0x000C: EPC Error Status Register */
uint32 FIFOFULLSTAT; /**< 0x0010: FIFO Full Status Register */
uint32 OVRFLWSTAT; /**< 0x0014: IP Interface FIFO Overflow Status Register */
uint32 CAMAVAILSTAT; /**< 0x0018: CAM Index Available Status Register */
uint32 rsvd1; /**< 0x001C: Reserved */
uint32 UERRADDR[ 2 ]; /**< 0x0020 - 0x0024: Uncorrectable Error Address Registers */
uint32 rsvd2[ 30 ]; /**< 0x0028 - 0x009C: Reserved */
uint32 CAM_CONTENT[ 32 ]; /**< 0x00A0 - 0x011C: CAM Content Update Registers */
uint32 rsvd3[ 56 ]; /**< 0x0120 - 0x01FC: Reserved */
uint32 CAM_INDEX[ 8 ]; /**< 0x0200 - 0x021C: CAM Index Register 0 to 7 */
} epcBASE_t;
#define epcREG1 ( ( epcBASE_t * ) 0xFFFF0C00U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file reg_eqep.h
* @brief EQEP Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the EQEP driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_EQEP_H__
#define __REG_EQEP_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Eqep Register Frame Definition */
/** @struct eqepBASE
* @brief EQEP Register Frame Definition
*
* This type is used to access the EQEP Registers.
*/
/** @typedef eqepBASE_t
* @brief EQEP Register Frame Type Definition
*
* This type is used to access the EQEP Registers.
*/
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
typedef volatile struct eqepBASE
{
uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/
uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/
uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/
uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/
uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/
uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/
uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/
uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/
uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/
uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/
uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/
uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/
uint16 QEPCTL; /*< 0x002A eQEP Control*/
uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/
uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/
uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/
uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/
uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/
uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/
uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/
uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/
uint16 QCPRD; /*< 0x003C eQEP Capture Period*/
uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/
uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/
uint16 rsvd_1; /*< 0x0042 Reserved*/
} eqepBASE_t;
#else
typedef volatile struct eqepBASE
{
uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/
uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/
uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/
uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/
uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/
uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/
uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/
uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/
uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/
uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/
uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/
uint16 QEPCTL; /*< 0x002A eQEP Control*/
uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/
uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/
uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/
uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/
uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/
uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/
uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/
uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/
uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/
uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/
uint16 QCPRD; /*< 0x003C eQEP Capture Period*/
uint16 rsvd_1; /*< 0x0042 Reserved*/
uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/
} eqepBASE_t;
#endif
/** @def eqepREG1
* @brief eQEP1 Register Frame Pointer
*
* This pointer is used by the eQEP driver to access the eQEP1 registers.
*/
#define eqepREG1 ( ( eqepBASE_t * ) 0xFCF79900U )
/** @def eqepREG2
* @brief eQEP2 Register Frame Pointer
*
* This pointer is used by the eQEP driver to access the eQEP2 registers.
*/
#define eqepREG2 ( ( eqepBASE_t * ) 0xFCF79A00U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_esm.h
* @brief ESM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ESM driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_ESM_H__
#define __REG_ESM_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Esm Register Frame Definition */
/** @struct esmBase
* @brief Esm Register Frame Definition
*
* This type is used to access the Esm Registers.
*/
/** @typedef esmBASE_t
* @brief Esm Register Frame Type Definition
*
* This type is used to access the Esm Registers.
*/
typedef volatile struct esmBase
{
uint32 EEPAPR1; /* 0x0000 */
uint32 DEPAPR1; /* 0x0004 */
uint32 IESR1; /* 0x0008 */
uint32 IECR1; /* 0x000C */
uint32 ILSR1; /* 0x0010 */
uint32 ILCR1; /* 0x0014 */
uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */
uint32 EPSR; /* 0x0024 */
uint32 IOFFHR; /* 0x0028 */
uint32 IOFFLR; /* 0x002C */
uint32 LTCR; /* 0x0030 */
uint32 LTCPR; /* 0x0034 */
uint32 EKR; /* 0x0038 */
uint32 SSR2; /* 0x003C */
uint32 IEPSR4; /* 0x0040 */
uint32 IEPCR4; /* 0x0044 */
uint32 IESR4; /* 0x0048 */
uint32 IECR4; /* 0x004C */
uint32 ILSR4; /* 0x0050 */
uint32 ILCR4; /* 0x0054 */
uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */
uint32 rsvd1[ 7U ]; /* 0x0064 - 0x007C */
uint32 IEPSR7; /* 0x0080 */
uint32 IEPCR7; /* 0x0084 */
uint32 IESR7; /* 0x0088 */
uint32 IECR7; /* 0x008C */
uint32 ILSR7; /* 0x0090 */
uint32 ILCR7; /* 0x0094 */
uint32 SR7[ 3U ]; /* 0x0098, 0x009C, 0x00A0 */
} esmBASE_t;
/** @def esmREG
* @brief Esm Register Frame Pointer
*
* This pointer is used by the Esm driver to access the Esm registers.
*/
#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_etpwm.h
* @brief ETPWM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the ETPWM driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_ETPWM_H__
#define __REG_ETPWM_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* ETPWM Register Frame Definition */
/** @struct etpwmBASE
* @brief ETPWM Register Frame Definition
*
* This type is used to access the ETPWM Registers.
*/
/** @typedef etpwmBASE_t
* @brief ETPWM Register Frame Type Definition
*
* This type is used to access the ETPWM Registers.
*/
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
typedef volatile struct etpwmBASE
{
uint16 TBCTL; /**< 0x0000 Time-Base Control Register*/
uint16 TBSTS; /**< 0x0002 Time-Base Status Register*/
uint16 rsvd1; /**< 0x0004 Reserved*/
uint16 TBPHS; /**< 0x0006 Time-Base Phase Register*/
uint16 TBCTR; /**< 0x0008 Time-Base Counter Register*/
uint16 TBPRD; /**< 0x000A Time-Base Period Register*/
uint16 rsvd2; /**< 0x000C Reserved*/
uint16 CMPCTL; /**< 0x000E Counter-Compare Control Register*/
uint16 rsvd3; /**< 0x0010 Reserved*/
uint16 CMPA; /**< 0x0012 Counter-Compare A Register*/
uint16 CMPB; /**< 0x0014 Counter-Compare B Register*/
uint16 AQCTLA; /**< 0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/
uint16 AQCTLB; /**< 0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/
uint16 AQSFRC; /**< 0x001A Action-Qualifier Software Force Register*/
uint16 AQCSFRC; /**< 0x001C Action-Qualifier Continuous S/W Force Register Set*/
uint16 DBCTL; /**< 0x001E Dead-Band Generator Control Register*/
uint16 DBRED; /**< 0x0020 Dead-Band Generator Rising Edge Delay Count Register*/
uint16 DBFED; /**< 0x0022 Dead-Band Generator Falling Edge Delay Count Register*/
uint16 TZSEL; /**< 0x0024 Trip-Zone Select Register*/
uint16 TZDCSEL; /**< 0x0026 Trip Zone Digital Compare Select Register*/
uint16 TZCTL; /**< 0x0028 Trip-Zone Control Register*/
uint16 TZEINT; /**< 0x002A Trip-Zone Enable Interrupt Register*/
uint16 TZFLG; /**< 0x002C Trip-Zone Flag Register*/
uint16 TZCLR; /**< 0x002E Trip-Zone Clear Register*/
uint16 TZFRC; /**< 0x0030 Trip-Zone Force Register*/
uint16 ETSEL; /**< 0x0032 Event-Trigger Selection Register*/
uint16 ETPS; /**< 0x0034 Event-Trigger Pre-Scale Register*/
uint16 ETFLG; /**< 0x0036 Event-Trigger Flag Register*/
uint16 ETCLR; /**< 0x0038 Event-Trigger Clear Register*/
uint16 ETFRC; /**< 0x003A Event-Trigger Force Register*/
uint16 PCCTL; /**< 0x003C PWM-Chopper Control Register*/
uint16 rsvd4; /**< 0x003E Reserved*/
uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/
uint16 DCTRIPSEL; /**< 0x0060 Digital Compare Trip Select Register*/
uint16 DCACTL; /**< 0x0062 Digital Compare A Control Register*/
uint16 DCBCTL; /**< 0x0064 Digital Compare B Control Register*/
uint16 DCFCTL; /**< 0x0066 Digital Compare Filter Control Register*/
uint16 DCCAPCTL; /**< 0x0068 Digital Compare Capture Control Register*/
uint16 DCFOFFSET; /**< 0x006A Digital Compare Filter Offset Register*/
uint16 DCFOFFSETCNT; /**< 0x006C Digital Compare Filter Offset Counter Register*/
uint16 DCFWINDOW; /**< 0x006E Digital Compare Filter Window Register*/
uint16 DCFWINDOWCNT; /**< 0x0070 Digital Compare Filter Window Counter Register*/
uint16 DCCAP; /**< 0x0072 Digital Compare Counter Capture Register*/
} etpwmBASE_t;
#else
typedef volatile struct etpwmBASE
{
uint16 TBSTS; /**< 0x0000 Time-Base Status Register*/
uint16 TBCTL; /**< 0x0002 Time-Base Control Register*/
uint16 TBPHS; /**< 0x0004 Time-Base Phase Register*/
uint16 rsvd1; /**< 0x0006 Reserved*/
uint16 TBPRD; /**< 0x0008 Time-Base Period Register*/
uint16 TBCTR; /**< 0x000A Time-Base Counter Register*/
uint16 CMPCTL; /**< 0x000C Counter-Compare Control Register*/
uint16 rsvd2; /**< 0x000E Reserved*/
uint16 CMPA; /**< 0x0010 Counter-Compare A Register*/
uint16 rsvd3; /**< 0x0012 Reserved*/
uint16 AQCTLA; /**< 0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/
uint16 CMPB; /**< 0x0016 Counter-Compare B Register*/
uint16 AQSFRC; /**< 0x0018 Action-Qualifier Software Force Register*/
uint16 AQCTLB; /**< 0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/
uint16 DBCTL; /**< 0x001C Dead-Band Generator Control Register*/
uint16 AQCSFRC; /**< 0x001E Action-Qualifier Continuous S/W Force Register Set*/
uint16 DBFED; /**< 0x0020 Dead-Band Generator Falling Edge Delay Count Register*/
uint16 DBRED; /**< 0x0022 Dead-Band Generator Rising Edge Delay Count Register*/
uint16 TZDCSEL; /**< 0x0024 Trip Zone Digital Compare Select Register*/
uint16 TZSEL; /**< 0x0026 Trip-Zone Select Register*/
uint16 TZEINT; /**< 0x0028 Trip-Zone Enable Interrupt Register*/
uint16 TZCTL; /**< 0x002A Trip-Zone Control Register*/
uint16 TZCLR; /**< 0x002C Trip-Zone Clear Register*/
uint16 TZFLG; /**< 0x002E Trip-Zone Flag Register*/
uint16 ETSEL; /**< 0x0030 Event-Trigger Selection Register*/
uint16 TZFRC; /**< 0x0032 Trip-Zone Force Register*/
uint16 ETFLG; /**< 0x0034 Event-Trigger Flag Register*/
uint16 ETPS; /**< 0x0036 Event-Trigger Pre-Scale Register*/
uint16 ETFRC; /**< 0x0038 Event-Trigger Force Register*/
uint16 ETCLR; /**< 0x003A Event-Trigger Clear Register*/
uint16 rsvd4; /**< 0x003C Reserved*/
uint16 PCCTL; /**< 0x003E PWM-Chopper Control Register*/
uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/
uint16 DCACTL; /**< 0x0060 Digital Compare A Control Register*/
uint16 DCTRIPSEL; /**< 0x0062 Digital Compare Trip Select Register*/
uint16 DCFCTL; /**< 0x0064 Digital Compare Filter Control Register*/
uint16 DCBCTL; /**< 0x0066 Digital Compare B Control Register*/
uint16 DCFOFFSET; /**< 0x0068 Digital Compare Filter Offset Register*/
uint16 DCCAPCTL; /**< 0x006A Digital Compare Capture Control Register*/
uint16 DCFWINDOW; /**< 0x006C Digital Compare Filter Window Register*/
uint16 DCFOFFSETCNT; /**< 0x006E Digital Compare Filter Offset Counter Register*/
uint16 DCCAP; /**< 0x0070 Digital Compare Counter Capture Register*/
uint16 DCFWINDOWCNT; /**< 0x0072 Digital Compare Filter Window Counter Register*/
} etpwmBASE_t;
#endif
/** @def etpwmREG1
* @brief ETPWM1 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM1 registers.
*/
#define etpwmREG1 ( ( etpwmBASE_t * ) 0xFCF78C00U )
/** @def etpwmREG2
* @brief ETPWM2 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM2 registers.
*/
#define etpwmREG2 ( ( etpwmBASE_t * ) 0xFCF78D00U )
/** @def etpwmREG3
* @brief ETPWM3 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM3 registers.
*/
#define etpwmREG3 ( ( etpwmBASE_t * ) 0xFCF78E00U )
/** @def etpwmREG4
* @brief ETPWM4 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM4 registers.
*/
#define etpwmREG4 ( ( etpwmBASE_t * ) 0xFCF78F00U )
/** @def etpwmREG5
* @brief ETPWM5 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM5 registers.
*/
#define etpwmREG5 ( ( etpwmBASE_t * ) 0xFCF79000U )
/** @def etpwmREG6
* @brief ETPWM6 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM6 registers.
*/
#define etpwmREG6 ( ( etpwmBASE_t * ) 0xFCF79100U )
/** @def etpwmREG7
* @brief ETPWM7 Register Frame Pointer
*
* This pointer is used by the ETPWM driver to access the ETPWM7 registers.
*/
#define etpwmREG7 ( ( etpwmBASE_t * ) 0xFCF79200U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_flash.h
* @brief Flash Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_FLASH_H__
#define __REG_FLASH_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_common.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Flash Register Frame Definition */
/** @struct flashWBase
* @brief Flash Wrapper Register Frame Definition
*
* This type is used to access the Flash Wrapper Registers.
*/
/** @typedef flashWBASE_t
* @brief Flash Wrapper Register Frame Type Definition
*
* This type is used to access the Flash Wrapper Registers.
*/
typedef volatile struct flashWBase
{
uint32 FRDCNTL; /* 0x0000 */
uint32 rsvd1; /* 0x0004 */
uint32 EE_FEDACCTRL1; /* 0x0008 */
uint32 rsvd2; /* 0x000C */
uint32 rsvd3; /* 0x0010 */
uint32 FEDAC_PASTATUS; /* 0x0014 */
uint32 FEDAC_PBSTATUS; /* 0x0018 */
uint32 FEDAC_GBLSTATUS; /* 0x001C */
uint32 rsvd4; /* 0x0020 */
uint32 FEDACSDIS; /* 0x0024 */
uint32 FPRIM_ADD_TAG; /* 0x0028 */
uint32 FDUP_ADD_TAG; /* 0x002C */
uint32 FBPROT; /* 0x0030 */
uint32 FBSE; /* 0x0034 */
uint32 FBBUSY; /* 0x0038 */
uint32 FBAC; /* 0x003C */
uint32 FBPWRMODE; /* 0x0040 */
uint32 FBPRDY; /* 0x0044 */
uint32 FPAC1; /* 0x0048 */
uint32 rsvd5; /* 0x004C */
uint32 FMAC; /* 0x0050 */
uint32 FMSTAT; /* 0x0054 */
uint32 FEMU_DMSW; /* 0x0058 */
uint32 FEMU_DLSW; /* 0x005C */
uint32 FEMU_ECC; /* 0x0060 */
uint32 FLOCK; /* 0x0064 */
uint32 rsvd6; /* 0x0068 */
uint32 FDIAGCTRL; /* 0x006C */
uint32 rsvd7; /* 0x0070 */
uint32 FRAW_ADDR; /* 0x0074 */
uint32 rsvd8; /* 0x0078 */
uint32 FPAR_OVR; /* 0x007C */
uint32 rsvd9[ 13U ]; /* 0x0080 - 0x00B0 */
uint32 RCR_VALID; /* 0x00B4 */
uint32 ACC_THRESHOLD; /* 0x00B8 */
uint32 rsvd10; /* 0x00BC */
uint32 FEDACSDIS2; /* 0x00C0 */
uint32 rsvd11; /* 0x00C4 */
uint32 rsvd12; /* 0x00C8 */
uint32 rsvd13; /* 0x00CC */
uint32 RCR_VALUE0; /* 0x00D0 */
uint32 RCR_VALUE1; /* 0x00D4 */
uint32 rsvd14[ 108U ]; /* 0x00D8 - 0x00284 */
uint32 FSM_WR_ENA; /* 0x0288 */
uint32 rsvd15[ 11U ]; /* 0x028C - 0x002B4 */
uint32 EEPROM_CONFIG; /* 0x02B8 */
uint32 rsvd16; /* 0x02BC */
uint32 FSM_SECTOR1; /* 0x02C0 */
uint32 FSM_SECTOR2; /* 0x02C4 */
uint32 rsvd17[ 78U ]; /* 0x02A8 */
uint32 FCFG_BANK; /* 0x02B8 */
} flashWBASE_t;
/** @def flashWREG
* @brief Flash Wrapper Register Frame Pointer
*
* This pointer is used by the system driver to access the flash wrapper registers.
*/
#define flashWREG ( ( flashWBASE_t * ) ( 0xFFF87000U ) )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#endif

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/** @file reg_gio.h
* @brief GIO Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the GIO driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_GIO_H__
#define __REG_GIO_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Gio Register Frame Definition */
/** @struct gioBase
* @brief GIO Base Register Definition
*
* This structure is used to access the GIO module registers.
*/
/** @typedef gioBASE_t
* @brief GIO Register Frame Type Definition
*
* This type is used to access the GIO Registers.
*/
typedef volatile struct gioBase
{
uint32 GCR0; /**< 0x0000: Global Control Register */
uint32 rsvd; /**< 0x0004: Reserved*/
uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/
uint32 POL; /**< 0x000C: Interrupt Polarity Register */
uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */
uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */
uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */
uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */
uint32 FLG; /**< 0x0020: Interrupt Flag Register */
uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */
uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */
uint32 EMU1; /**< 0x002C: Emulation 1 Register */
uint32 EMU2; /**< 0x0030: Emulation 2 Register */
} gioBASE_t;
/** @struct gioPort
* @brief GIO Port Register Definition
*/
/** @typedef gioPORT_t
* @brief GIO Port Register Type Definition
*
* This type is used to access the GIO Port Registers.
*/
typedef volatile struct gioPort
{
uint32 DIR; /**< 0x0000: Data Direction Register */
uint32 DIN; /**< 0x0004: Data Input Register */
uint32 DOUT; /**< 0x0008: Data Output Register */
uint32 DSET; /**< 0x000C: Data Output Set Register */
uint32 DCLR; /**< 0x0010: Data Output Clear Register */
uint32 PDR; /**< 0x0014: Open Drain Register */
uint32 PULDIS; /**< 0x0018: Pullup Disable Register */
uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */
} gioPORT_t;
/** @def gioREG
* @brief GIO Register Frame Pointer
*
* This pointer is used by the GIO driver to access the gio module registers.
*/
#define gioREG ( ( gioBASE_t * ) 0xFFF7BC00U )
/** @def gioPORTA
* @brief GIO Port (A) Register Pointer
*
* Pointer used by the GIO driver to access PORTA
*/
#define gioPORTA ( ( gioPORT_t * ) 0xFFF7BC34U )
/** @def gioPORTB
* @brief GIO Port (B) Register Pointer
*
* Pointer used by the GIO driver to access PORTB
*/
#define gioPORTB ( ( gioPORT_t * ) 0xFFF7BC54U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_het.h
* @brief HET Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the HET driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_HET_H__
#define __REG_HET_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Het Register Frame Definition */
/** @struct hetBase
* @brief HET Base Register Definition
*
* This structure is used to access the HET module registers.
*/
/** @typedef hetBASE_t
* @brief HET Register Frame Type Definition
*
* This type is used to access the HET Registers.
*/
typedef volatile struct hetBase
{
uint32 GCR; /**< 0x0000: Global control register */
uint32 PFR; /**< 0x0004: Prescale factor register */
uint32 ADDR; /**< 0x0008: Current address register */
uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */
uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */
uint32 INTENAS; /**< 0x0014: Interrupt enable set register */
uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */
uint32 EXC1; /**< 0x001C: Exception control register 1 */
uint32 EXC2; /**< 0x0020: Exception control register 2 */
uint32 PRY; /**< 0x0024: Interrupt priority register */
uint32 FLG; /**< 0x0028: Interrupt flag register */
uint32 AND; /**< 0x002C: AND share control register */
uint32 rsvd1; /**< 0x0030: Reserved */
uint32 HRSH; /**< 0x0034: High resolution share register */
uint32 XOR; /**< 0x0038: XOR share register */
uint32 REQENS; /**< 0x003C: Request enable set register */
uint32 REQENC; /**< 0x0040: Request enable clear register */
uint32 REQDS; /**< 0x0044: Request destination select register */
uint32 rsvd2; /**< 0x0048: Reserved */
uint32 DIR; /**< 0x004C: Direction register */
uint32 DIN; /**< 0x0050: Data input register */
uint32 DOUT; /**< 0x0054: Data output register */
uint32 DSET; /**< 0x0058: Data output set register */
uint32 DCLR; /**< 0x005C: Data output clear register */
uint32 PDR; /**< 0x0060: Open drain register */
uint32 PULDIS; /**< 0x0064: Pull disable register */
uint32 PSL; /**< 0x0068: Pull select register */
uint32 rsvd3; /**< 0x006C: Reserved */
uint32 rsvd4; /**< 0x0070: Reserved */
uint32 PCR; /**< 0x0074: Parity control register */
uint32 PAR; /**< 0x0078: Parity address register */
uint32 PPR; /**< 0x007C: Parity pin select register */
uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */
uint32 SFENA; /**< 0x0084: Suppression filter enable register */
uint32 rsvd5; /**< 0x0088: Reserved */
uint32 LBPSEL; /**< 0x008C: Loop back pair select register */
uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */
uint32 PINDIS; /**< 0x0094: Pin disable register */
} hetBASE_t;
/** @struct hetInstructionBase
* @brief HET Instruction Definition
*
* This structure is used to access the HET RAM.
*/
/** @typedef hetINSTRUCTION_t
* @brief HET Instruction Type Definition
*
* This type is used to access a HET Instruction.
*/
typedef volatile struct hetInstructionBase
{
uint32 Program;
uint32 Control;
uint32 Data;
uint32 rsvd1;
} hetINSTRUCTION_t;
/** @struct hetRamBase
* @brief HET RAM Definition
*
* This structure is used to access the HET RAM.
*/
/** @typedef hetRAMBASE_t
* @brief HET RAM Type Definition
*
* This type is used to access the HET RAM.
*/
typedef volatile struct het1RamBase
{
hetINSTRUCTION_t Instruction[ 160U ];
} hetRAMBASE_t;
/** @def hetREG1
* @brief HET Register Frame Pointer
*
* This pointer is used by the HET driver to access the het module registers.
*/
#define hetREG1 ( ( hetBASE_t * ) 0xFFF7B800U )
/** @def hetPORT1
* @brief HET GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of HET1
* (use the GIO drivers to access the port pins).
*/
#define hetPORT1 ( ( gioPORT_t * ) 0xFFF7B84CU )
/** @def hetREG2
* @brief HET2 Register Frame Pointer
*
* This pointer is used by the HET driver to access the het module registers.
*/
#define hetREG2 ( ( hetBASE_t * ) 0xFFF7B900U )
/** @def hetPORT2
* @brief HET2 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of HET2
* (use the GIO drivers to access the port pins).
*/
#define hetPORT2 ( ( gioPORT_t * ) 0xFFF7B94CU )
#define hetRAM1 ( ( hetRAMBASE_t * ) 0xFF460000U )
#define hetRAM2 ( ( hetRAMBASE_t * ) 0xFF440000U )
#define NHET1RAMPARLOC ( *( volatile uint32 * ) 0xFF462000U )
#define NHET1RAMLOC ( *( volatile uint32 * ) 0xFF460000U )
#define NHET2RAMPARLOC ( *( volatile uint32 * ) 0xFF442000U )
#define NHET2RAMLOC ( *( volatile uint32 * ) 0xFF440000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_htu.h
* @brief HTU Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the HTU driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_HTU_H__
#define __REG_HTU_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* htu Register Frame Definition */
/** @struct htuBase
* @brief HTU Base Register Definition
*
* This structure is used to access the HTU module registers.
*/
/** @typedef htuBASE_t
* @brief HTU Register Frame Type Definition
*
* This type is used to access the HTU Registers.
*/
typedef volatile struct htuBase
{
uint32 GC; /** 0x00 */
uint32 CPENA; /** 0x04 */
uint32 BUSY0; /** 0x08 */
uint32 BUSY1; /** 0x0C */
uint32 BUSY2; /** 0x10 */
uint32 BUSY3; /** 0x14 */
uint32 ACPE; /** 0x18 */
uint32 rsvd1; /** 0x1C */
uint32 RLBECTRL; /** 0x20 */
uint32 BFINTS; /** 0x24 */
uint32 BFINTC; /** 0x28 */
uint32 INTMAP; /** 0x2C */
uint32 rsvd2; /** 0x30 */
uint32 INTOFF0; /** 0x34 */
uint32 INTOFF1; /** 0x38 */
uint32 BIM; /** 0x3C */
uint32 RLOSTFL; /** 0x40 */
uint32 BFINTFL; /** 0x44 */
uint32 BERINTFL; /** 0x48 */
uint32 MP1S; /** 0x4C */
uint32 MP1E; /** 0x50 */
uint32 DCTRL; /** 0x54 */
uint32 WPR; /** 0x58 */
uint32 WMR; /** 0x5C */
uint32 ID; /** 0x60 */
uint32 PCR; /** 0x64 */
uint32 PAR; /** 0x68 */
uint32 rsvd3; /** 0x6C */
uint32 MPCS; /** 0x70 */
uint32 MP0S; /** 0x74 */
uint32 MP0E; /** 0x78 */
} htuBASE_t;
typedef volatile struct htudcp
{
uint32 IFADDRA;
uint32 IFADDRB;
uint32 IHADDRCT;
uint32 ITCOUNT;
} htudcp_t;
typedef volatile struct htucdcp
{
uint32 CFADDRA;
uint32 CFADDRB;
uint32 CFCOUNT;
uint32 rsvd4;
} htucdcp_t;
#define htuREG1 ( ( htuBASE_t * ) 0xFFF7A400U )
#define htuREG2 ( ( htuBASE_t * ) 0xFFF7A500U )
#define htuDCP1 ( ( htudcp_t * ) 0xFF4E0000U )
#define htuDCP2 ( ( htudcp_t * ) 0xFF4C0000U )
#define htuCDCP1 ( ( htucdcp_t * ) 0xFF4E0100U )
#define htuCDCP2 ( ( htucdcp_t * ) 0xFF4C0100U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_i2c.h
* @brief I2C Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the I2C driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_I2C_H__
#define __REG_I2C_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* I2c Register Frame Definition */
/** @struct i2cBase
* @brief I2C Base Register Definition
*
* This structure is used to access the I2C module registers.
*/
/** @typedef i2cBASE_t
* @brief I2C Register Frame Type Definition
*
* This type is used to access the I2C Registers.
*/
typedef volatile struct i2cBase
{
uint32 OAR; /**< 0x0000 I2C Own Address register */
uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */
uint32 STR; /**< 0x0008 I2C Interrupt Status register */
uint32 CKL; /**< 0x000C I2C Clock Divider Low register */
uint32 CKH; /**< 0x0010 I2C Clock Divider High register */
uint32 CNT; /**< 0x0014 I2C Data Count register */
uint32 DRR; /**< 0x0018: I2C Data Receive register, */
uint32 SAR; /**< 0x001C I2C Slave Address register */
uint32 DXR; /**< 0x0020: I2C Data Transmit register, */
uint32 MDR; /**< 0x0024 I2C Mode register */
uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */
uint32 EMDR; /**< 0x002C I2C Extended Mode register */
uint32 PSC; /**< 0x0030 I2C Prescaler register */
uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */
uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */
uint32 DMACR; /**< 0x003C I2C DMA Control Register */
uint32 rsvd7; /**< 0x0040 Reserved */
uint32 rsvd8; /**< 0x0044 Reserved */
uint32 PFNC; /**< 0x0048 Pin Function Register */
uint32 DIR; /**< 0x004C Pin Direction Register */
uint32 DIN; /**< 0x0050 Pin Data In Register */
uint32 DOUT; /**< 0x0054 Pin Data Out Register */
uint32 SET; /**< 0x0058 Pin Data Set Register */
uint32 CLR; /**< 0x005C Pin Data Clr Register */
uint32 PDR; /**< 0x0060 Pin Open Drain Output Enable Register */
uint32 PDIS; /**< 0x0064 Pin Pullup/Pulldown Disable Register */
uint32 PSEL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */
uint32 PSRS; /**< 0x006C Pin Slew Rate Select Register */
} i2cBASE_t;
/** @def i2cREG1
* @brief I2C Register Frame Pointer
*
* This pointer is used by the I2C driver to access the I2C module registers.
*/
#define i2cREG1 ( ( i2cBASE_t * ) 0xFFF7D400U )
/** @def i2cREG2
* @brief I2C2 Register Frame Pointer
*
* This pointer is used by the I2C driver to access the I2C2 module registers.
*/
#define i2cREG2 ( ( i2cBASE_t * ) 0xFFF7D500U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @def i2cPORT1
* @brief I2C1 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of I2C1
* (use the GIO drivers to access the port pins).
*/
#define i2cPORT1 ( ( gioPORT_t * ) 0xFFF7D44CU )
/** @def i2cPORT2
* @brief I2C2 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of I2C2
* (use the GIO drivers to access the port pins).
*/
#define i2cPORT2 ( ( gioPORT_t * ) 0xFFF7D54CU )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#endif

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/** @file reg_l2ramw.h
* @brief L2RAMW Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_L2RAMW_H__
#define __REG_L2RAMW_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sys_common.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* L2ram Register Frame Definition */
/** @struct l2ramwBase
* @brief L2RAMW Wrapper Register Frame Definition
*
* This type is used to access the L2RAMW Wrapper Registers.
*/
/** @typedef l2ramwBASE_t
* @brief L2RAMW Wrapper Register Frame Type Definition
*
* This type is used to access the L2RAMW Wrapper Registers.
*/
typedef volatile struct l2ramwBase
{
uint32 RAMCTRL; /* 0x0000 */
uint32 rsvd1[ 3 ]; /* 0x0004 */
uint32 RAMERRSTATUS; /* 0x0010 */
uint32 rsvd2[ 4 ]; /* 0x0014 */
uint32 DIAGDATAVECTOR_H; /* 0x0024 */
uint32 DIAGDATAVECTOR_L; /* 0x0028 */
uint32 DIAG_ECC; /* 0x002C */
uint32 RAMTEST; /* 0x0030 */
uint32 rsvd3; /* 0x0034 */
uint32 RAMADDRDECVECT; /* 0x0038 */
uint32 MEMINITDOMAIN; /* 0x003C */
uint32 rsvd4; /* 0x0040 */
uint32 BANKDOMAINMAP0; /* 0x0044 */
uint32 BANKDOMAINMAP1; /* 0x0048 */
} l2ramwBASE_t;
#define l2ramwREG ( ( l2ramwBASE_t * ) ( 0xFFFFF900U ) )
/* USER CODE BEGIN (2) */
/* USER CODE END */
#endif

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/** @file reg_lin.h
* @brief LIN Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the LIN driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_LIN_H__
#define __REG_LIN_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Lin Register Frame Definition */
/** @struct linBase
* @brief LIN Base Register Definition
*
* This structure is used to access the LIN module registers.
*/
/** @typedef linBASE_t
* @brief LIN Register Frame Type Definition
*
* This type is used to access the LIN Registers.
*/
typedef volatile struct linBase
{
uint32 GCR0; /**< 0x0000: Global control register 0 */
uint32 GCR1; /**< 0x0004: Global control register 1 */
uint32 GCR2; /**< 0x0008: Global control register 2 */
uint32 SETINT; /**< 0x000C: Set interrupt enable register */
uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */
uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */
uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */
uint32 FLR; /**< 0x001C: interrupt flag register */
uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */
uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */
uint32 FORMAT; /**< 0x0028: Format Control Register */
uint32 BRS; /**< 0x002C: Baud rate selection register */
uint32 ED; /**< 0x0030: Emulation register */
uint32 RD; /**< 0x0034: Receive data register */
uint32 TD; /**< 0x0038: Transmit data register */
uint32 PIO0; /**< 0x003C: Pin function register */
uint32 PIO1; /**< 0x0040: Pin direction register */
uint32 PIO2; /**< 0x0044: Pin data in register */
uint32 PIO3; /**< 0x0048: Pin data out register */
uint32 PIO4; /**< 0x004C: Pin data set register */
uint32 PIO5; /**< 0x0050: Pin data clr register */
uint32 PIO6; /**< 0x0054: Pin open drain output enable register */
uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */
uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */
uint32 COMP; /**< 0x0060: Compare register */
uint8 RDx[ 8U ]; /**< 0x0064-0x0068: RX buffer register */
uint32 MASK; /**< 0x006C: Mask register */
uint32 ID; /**< 0x0070: Identification Register */
uint8 TDx[ 8U ]; /**< 0x0074-0x0078: TX buffer register */
uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */
uint32 rsvd1[ 4U ]; /**< 0x0080 - 0x8C: Reserved */
uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */
} linBASE_t;
/** @def linREG1
* @brief LIN1 Register Frame Pointer
*
* This pointer is used by the LIN driver to access the lin1 module registers.
*/
#define linREG1 ( ( linBASE_t * ) 0xFFF7E400U )
/** @def linPORT1
* @brief LIN1 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of LIN1
* (use the GIO drivers to access the port pins).
*/
#define linPORT1 ( ( gioPORT_t * ) 0xFFF7E440U )
/** @def linREG2
* @brief LIN2 Register Frame Pointer
*
* This pointer is used by the LIN driver to access the lin2 module registers.
*/
#define linREG2 ( ( linBASE_t * ) 0xFFF7E600U )
/** @def linPORT2
* @brief LIN2 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of LIN2
* (use the GIO drivers to access the port pins).
*/
#define linPORT2 ( ( gioPORT_t * ) 0xFFF7E640U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_mibspi.h
* @brief MIBSPI Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the MIBSPI driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_MIBSPI_H__
#define __REG_MIBSPI_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Mibspi Register Frame Definition */
/** @struct mibspiBase
* @brief MIBSPI Register Definition
*
* This structure is used to access the MIBSPI module registers.
*/
/** @typedef mibspiBASE_t
* @brief MIBSPI Register Frame Type Definition
*
* This type is used to access the MIBSPI Registers.
*/
typedef volatile struct mibspiBase
{
uint32 GCR0; /**< 0x0000: Global Control 0 */
uint32 GCR1; /**< 0x0004: Global Control 1 */
uint32 INT0; /**< 0x0008: Interrupt Register */
uint32 LVL; /**< 0x000C: Interrupt Level */
uint32 FLG; /**< 0x0010: Interrupt flags */
uint32 PC0; /**< 0x0014: Function Pin Enable */
uint32 PC1; /**< 0x0018: Pin Direction */
uint32 PC2; /**< 0x001C: Pin Input Latch */
uint32 PC3; /**< 0x0020: Pin Output Latch */
uint32 PC4; /**< 0x0024: Output Pin Set */
uint32 PC5; /**< 0x0028: Output Pin Clr */
uint32 PC6; /**< 0x002C: Open Drain Output Enable */
uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */
uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */
uint32 DAT0; /**< 0x0038: Transmit Data */
uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
uint32 BUF; /**< 0x0040: Receive Buffer */
uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
uint32 DELAY; /**< 0x0048: Delays */
uint32 DEF; /**< 0x004C: Default Chip Select */
uint32 FMT0; /**< 0x0050: Data Format 0 */
uint32 FMT1; /**< 0x0054: Data Format 1 */
uint32 FMT2; /**< 0x0058: Data Format 2 */
uint32 FMT3; /**< 0x005C: Data Format 3 */
uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
uint32 rsvd3; /**< 0x0068: Slew Rate Select */
uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */
uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */
uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */
uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */
uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */
uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */
uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */
uint32 rsvd1[ 2U ]; /**< 0x0088: Reserved */
uint32 TICKCNT; /**< 0x0090: Tick Counter */
uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */
uint32 TGCTRL[ 16U ]; /**< 0x0098 - 0x00D4: Transfer Group Control */
uint32 DMACTRL[ 8U ]; /**< 0x00D8 - 0x00F4: DMA Control */
uint32 DMACOUNT[ 8U ]; /**< 0x00F8 - 0x0114: DMA Count */
uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */
uint32 rsvd2; /**< 0x011C: Reserved */
uint32 PAR_ECC_CTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control
*/
uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */
uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */
uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */
uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */
uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
uint32 EXT_PRESCALE1; /**< 0x0138: SPI Extended Prescale Register 1*/
uint32 EXT_PRESCALE2; /**< 0x013C: SPI Extended Prescale Register 2*/
uint32 ECCDIAG_CTRL; /**< 0x0140: ECC Diagnostic Control register*/
uint32 ECCDIAG_STAT; /**< 0x0144: ECC Diagnostic Status register*/
uint32 SBERRADDR1; /**< 0x0148: */
uint8 rsvd4[ 6 ]; /**< 0x014C-0x152: Single Bit Error Address Register - RXRAM*/
uint32 SBERRADDR0; /**< 0x0152: Single Bit Error Address Register - TXRAM*/
} mibspiBASE_t;
/** @def mibspiREG1
* @brief MIBSPI1 Register Frame Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi module registers.
*/
#define mibspiREG1 ( ( mibspiBASE_t * ) 0xFFF7F400U )
/** @def mibspiPORT1
* @brief MIBSPI1 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of MIBSPI1
* (use the GIO drivers to access the port pins).
*/
#define mibspiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U )
/** @def mibspiREG2
* @brief MIBSPI2 Register Frame Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi module registers.
*/
#define mibspiREG2 ( ( mibspiBASE_t * ) 0xFFF7F600U )
/** @def mibspiPORT2
* @brief MIBSPI2 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of MIBSPI2
* (use the GIO drivers to access the port pins).
*/
#define mibspiPORT2 ( ( gioPORT_t * ) 0xFFF7F618U )
/** @def mibspiREG3
* @brief MIBSPI3 Register Frame Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi module registers.
*/
#define mibspiREG3 ( ( mibspiBASE_t * ) 0xFFF7F800U )
/** @def mibspiPORT3
* @brief MIBSPI3 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of MIBSPI3
* (use the GIO drivers to access the port pins).
*/
#define mibspiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U )
/** @def mibspiREG4
* @brief MIBSPI4 Register Frame Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi module registers.
*/
#define mibspiREG4 ( ( mibspiBASE_t * ) 0xFFF7FA00U )
/** @def mibspiPORT4
* @brief MIBSPI4 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of MIBSPI4
* (use the GIO drivers to access the port pins).
*/
#define mibspiPORT4 ( ( gioPORT_t * ) 0xFFF7FA18U )
/** @def mibspiREG5
* @brief MIBSPI5 Register Frame Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi module registers.
*/
#define mibspiREG5 ( ( mibspiBASE_t * ) 0xFFF7FC00U )
/** @def mibspiPORT5
* @brief MIBSPI5 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of MIBSPI5
* (use the GIO drivers to access the port pins).
*/
#define mibspiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U )
/** @struct mibspiRamBase
* @brief MIBSPI Buffer RAM Definition
*
* This structure is used to access the MIBSPI buffer memory.
*/
/** @typedef mibspiRAM_t
* @brief MIBSPI RAM Type Definition
*
* This type is used to access the MIBSPI RAM.
*/
typedef volatile struct mibspiRamBase
{
struct
{
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
uint16 data; /**< tx buffer data */
uint16 control; /**< tx buffer control */
#else
uint16 control; /**< tx buffer control */
uint16 data; /**< tx buffer data */
#endif
} tx[ 128 ];
struct
{
#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) )
uint16 data; /**< rx buffer data */
uint16 flags; /**< rx buffer flags */
#else
uint16 flags; /**< rx buffer flags */
uint16 data; /**< rx buffer data */
#endif
} rx[ 128 ];
} mibspiRAM_t;
/** @def mibspiRAM1
* @brief MIBSPI1 Buffer RAM Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiRAM1 ( ( mibspiRAM_t * ) 0xFF0E0000U )
/** @def mibspiRAM2
* @brief MIBSPI2 Buffer RAM Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiRAM2 ( ( mibspiRAM_t * ) 0xFF080000U )
/** @def mibspiRAM3
* @brief MIBSPI3 Buffer RAM Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiRAM3 ( ( mibspiRAM_t * ) 0xFF0C0000U )
/** @def mibspiRAM4
* @brief MIBSPI4 Buffer RAM Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiRAM4 ( ( mibspiRAM_t * ) 0xFF060000U )
/** @def mibspiRAM5
* @brief MIBSPI5 Buffer RAM Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiRAM5 ( ( mibspiRAM_t * ) 0xFF0A0000U )
/** @def mibspiPARRAM1
* @brief MIBSPI1 Buffer RAM PARITY Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiPARRAM1 ( *( volatile uint32 * ) ( 0xFF0E0000U + 0x00000400U ) )
/** @def mibspiPARRAM2
* @brief MIBSPI2 Buffer RAM PARITY Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiPARRAM2 ( *( volatile uint32 * ) ( 0xFF080000U + 0x00000400U ) )
/** @def mibspiPARRAM3
* @brief MIBSPI3 Buffer RAM PARITY Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiPARRAM3 ( *( volatile uint32 * ) ( 0xFF0C0000U + 0x00000400U ) )
/** @def mibspiPARRAM4
* @brief MIBSPI4 Buffer RAM PARITY Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiPARRAM4 ( *( volatile uint32 * ) ( 0xFF060000U + 0x00000400U ) )
/** @def mibspiPARRAM5
* @brief MIBSPI5 Buffer RAM PARITY Pointer
*
* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
*/
#define mibspiPARRAM5 ( *( volatile uint32 * ) ( 0xFF0A0000U + 0x00000400U ) )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_nmpu.h
* @brief NMPU Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the NMPU driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_NMPU_H__
#define __REG_NMPU_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* NMPU Register Frame Definition */
/** @struct nmpuBASE_t
* @brief nmpuBASE Register Definition
*
* This structure is used to access the NMPU module registers.
*/
typedef volatile struct nmpuBase
{
uint32 MPUREV; /**< 0x0000 MPU Revision ID Register */
uint32 MPULOCK; /**< 0x0004 MPU Lock Register */
uint32 MPUDIAGCTRL; /**< 0x0008 MPU Diagnostics Control Register */
uint32 MPUDIAGADDR; /**< 0x000C MPU Diagnostic Address Register */
uint32 MPUERRSTAT; /**< 0x0010 MPU Error Status Register */
uint32 MPUERRADDR; /**< 0x0014 MPU Error Address Register */
uint32 MPUIAM; /**< 0x0018 MPU Input Address Mask Register */
uint32 rsvd1; /**< 0x001C Reserved */
uint32 MPUCTRL1; /**< 0x0020 MPU Control Register 1 */
uint32 MPUCTRL2; /**< 0x0024 MPU Control Register 2 */
uint32 rsvd2; /**< 0x0028 Reserved */
uint32 MPUTYPE; /**< 0x002C MPU Type Register */
uint32 MPUREGBASE; /**< 0x0030 MPU Region Base Address Register */
uint32 MPUREGSENA; /**< 0x0034 MPU Region Size and Enable Register */
uint32 MPUREGACR; /**< 0x0038 MPU Region Access Control Register */
uint32 MPUREGNUM; /**< 0x003C MPU Region Number Register */
} nmpuBASE_t;
#define nmpu_emacREG ( ( nmpuBASE_t * ) 0xFCFF1800U )
#define nmpu_dmaREG ( ( nmpuBASE_t * ) 0xFFFF1A00U )
#define nmpu_ps_scr_sREG ( ( nmpuBASE_t * ) 0xFFFF1800U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file reg_pbist.h
* @brief PBIST Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_PBIST_H__
#define __REG_PBIST_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* PBIST Register Frame Definition */
/** @struct pbistBase
* @brief PBIST Base Register Definition
*
* This structure is used to access the PBIST module registers.
*/
/** @typedef pbistBASE_t
* @brief PBIST Register Frame Type Definition
*
* This type is used to access the PBIST Registers.
*/
typedef volatile struct pbistBase
{
uint32 RAMT; /* 0x0160: RAM Configuration Register */
uint32 DLR; /* 0x0164: Datalogger Register */
uint32 rsvd1[ 6U ]; /* 0x0168 */
uint32 PACT; /* 0x0180: PBIST Activate Register */
uint32 PBISTID; /* 0x0184: PBIST ID Register */
uint32 OVER; /* 0x0188: Override Register */
uint32 rsvd2; /* 0x018C */
uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */
uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */
uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */
uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */
uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */
uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */
uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */
uint32 rsvd3; /* 0x01AC */
uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */
uint32 rsvd4[ 3U ]; /* 0x01B4 */
uint32 ROM; /* 0x01C0: ROM Mask Register */
uint32 ALGO; /* 0x01C4: Algorithm Mask Register */
uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */
uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */
} pbistBASE_t;
#define pbistREG ( ( pbistBASE_t * ) 0xFFFFE560U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_pcr.h
* @brief PCR Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_PCR_H__
#define __REG_PCR_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Pcr Register Frame Definition */
/** @struct pcrBase
* @brief Pcr Register Frame Definition
*
* This type is used to access the Pcr Registers.
*/
/** @typedef pcrBASE_t
* @brief PCR Register Frame Type Definition
*
* This type is used to access the PCR Registers.
*/
typedef volatile struct pcrBase
{
uint32 PMPROTSET0; /* 0x0000 */
uint32 PMPROTSET1; /* 0x0004 */
uint32 rsvd1[ 2U ]; /* 0x0008 */
uint32 PMPROTCLR0; /* 0x0010 */
uint32 PMPROTCLR1; /* 0x0014 */
uint32 rsvd2[ 2U ]; /* 0x0018 */
uint32 PPROTSET0; /* 0x0020 */
uint32 PPROTSET1; /* 0x0024 */
uint32 PPROTSET2; /* 0x0028 */
uint32 PPROTSET3; /* 0x002C */
uint32 rsvd3[ 4U ]; /* 0x0030 */
uint32 PPROTCLR0; /* 0x0040 */
uint32 PPROTCLR1; /* 0x0044 */
uint32 PPROTCLR2; /* 0x0048 */
uint32 PPROTCLR3; /* 0x004C */
uint32 rsvd4[ 4U ]; /* 0x0050 */
uint32 PCSPWRDWNSET0; /* 0x0060 */
uint32 PCSPWRDWNSET1; /* 0x0064 */
uint32 rsvd5[ 2U ]; /* 0x0068 */
uint32 PCSPWRDWNCLR0; /* 0x0070 */
uint32 PCSPWRDWNCLR1; /* 0x0074 */
uint32 rsvd6[ 2U ]; /* 0x0078 */
uint32 PSPWRDWNSET0; /* 0x0080 */
uint32 PSPWRDWNSET1; /* 0x0084 */
uint32 PSPWRDWNSET2; /* 0x0088 */
uint32 PSPWRDWNSET3; /* 0x008C */
uint32 rsvd7[ 4U ]; /* 0x0090 */
uint32 PSPWRDWNCLR0; /* 0x00A0 */
uint32 PSPWRDWNCLR1; /* 0x00A4 */
uint32 PSPWRDWNCLR2; /* 0x00A8 */
uint32 PSPWRDWNCLR3; /* 0x00AC */
uint32 rsvd8[ 4U ]; /* 0x00B0 */
uint32 PDPWRDWNSET; /* 0x00C0 */
uint32 PDPWRDWNCLR; /* 0x00C4 */
uint32 rsvd9[ 78U ]; /* 0x00C8 */
uint32 MSTIDWRENA; /* 0x0200 */
uint32 MSTIDENA; /* 0x0204 */
uint32 MSTIDDIAGCTRL; /* 0x0208 */
uint32 rsvd10[ 61U ]; /* 0x020C */
struct
{
uint32 PSxMSTID_L;
uint32 PSxMSTID_H;
} PSxMSTID[ 32 ]; /* 0x0300 */
struct
{
uint32 PPSxMSTID_L;
uint32 PPSxMSTID_H;
} PPSxMSTID[ 8 ]; /* 0x0400 */
struct
{
uint32 PPSExMSTID_L;
uint32 PPSExMSTID_H;
} PPSExMSTID[ 32 ]; /* 0x0440 */
uint32 PCSxMSTID[ 32 ]; /* 0x0540 */
uint32 PPCSxMSTID[ 8 ]; /* 0x05C0 */
} pcrBASE_t;
/** @def pcrREG1
* @brief Pcr1 Register Frame Pointer
*
* This pointer is used by the system driver to access the Pcr1 registers.
*/
#define pcrREG1 ( ( pcrBASE_t * ) 0xFFFF1000U )
/** @def pcrREG2
* @brief Pcr2 Register Frame Pointer
*
* This pointer is used by the system driver to access the Pcr2 registers.
*/
#define pcrREG2 ( ( pcrBASE_t * ) 0xFCFF1000U )
/** @def pcrREG3
* @brief Pcr3 Register Frame Pointer
*
* This pointer is used by the system driver to access the Pcr3 registers.
*/
#define pcrREG3 ( ( pcrBASE_t * ) 0xFFF78000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_pinmux.h
* @brief PINMUX Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the PINMUX driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_PINMUX_H__
#define __REG_PINMUX_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @struct pinMuxBase
* @brief PINMUX Register Definition
*
* This structure is used to access the PINMUX module registers.
*/
/** @typedef pinMuxBASE_t
* @brief PINMUX Register Frame Type Definition
*
* This type is used to access the PINMUX Registers.
*/
typedef volatile struct pinMuxBase
{
uint32 REVISION_REG; /**< 0x00: Revision Register */
uint32 rsvd1[ 7 ]; /**<Reserved */
uint32 BOOT_REG; /**< 0x20: Boot Mode Register */
uint32 rsvd2[ 5 ]; /**<Reserved */
uint32 KICKER0; /**< 0x38: Kicker Register 0 */
uint32 KICKER1; /**< 0x3C: Kicker Register 1 */
uint32 rsvd3[ 40 ]; /**<Reserved */
uint32 ERR_RAW_STATUS_REG; /**< 0xE0: Error Raw Status / Set Register */
uint32 ERR_ENABLED_STATUS_REG; /**< 0xE4: Error Enabled Status / Clear Register */
uint32 ERR_ENABLE_REG; /**< 0xE8: Error Signaling Enable Register */
uint32 ERR_ENABLE_CLR_REG; /**< 0xEC: Error Signaling Enable Clear Register*/
uint32 rsvd4; /**<Reserved */
uint32 FAULT_ADDRESS_REG; /**< 0xF4: Fault Address Register */
uint32 FAULT_STATUS_REG; /**< 0xF8: Fault Status Register */
uint32 FAULT_CLEAR_REG; /**< 0xFC: Fault Clear Register */
uint32 rsvd5[ 4 ]; /**< Reserved*/
uint32 PINMUX[ 180 ]; /**< 0x110 - 1A4 : Output Pin Multiplexing Control Registers (38
registers); 0x250 - 0x29C : Input Pin Multiplexing Control
Registers (20); 0X390 - 3DC : Special Functionality Control
Registers (20) */
} pinMuxBASE_t;
/** @def pinMuxReg
* @brief Pin Muxing Control Register Frame Pointer
*
* This pointer is used to access the PINMUX module registers.
*/
#define pinMuxReg ( ( pinMuxBASE_t * ) 0xFFFF1C00U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_pmm.h
* @brief PMM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the PMM driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_PMM_H__
#define __REG_PMM_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Pmm Register Frame Definition */
/** @struct pmmBase
* @brief Pmm Register Frame Definition
*
* This type is used to access the Pmm Registers.
*/
/** @typedef pmmBase_t
* @brief Pmm Register Frame Type Definition
*
* This type is used to access the Pmm Registers.
*/
typedef volatile struct pmmBase
{
uint32 LOGICPDPWRCTRL0; /**< 0x0000: Logic Power Domain Control Register 0 */
uint32 LOGICPDPWRCTRL1; /**< 0x0000: Logic Power Domain Control Register 1 */
uint32 rsvd1[ 6U ]; /**< 0x0008 - 0x001C: Reserved*/
uint32 PDCLKDIS; /**< 0x0020: Power Domain Clock Disable Register */
uint32 PDCLKDISSET; /**< 0x0024: Power Domain Clock Disable Set Register */
uint32 PDCLKDISCLR; /**< 0x0028: Power Domain Clock Disable Clear Register */
uint32 rsvd2[ 5U ]; /**< 0x002C - 0x003C: Reserved */
uint32 LOGICPDPWRSTAT[ 5U ]; /**< 0x0040 - 0x0050: Logic Power Domain Power Status
Register
- 0: PD2
- 1: PD3
- 2: PD4
- 3: PD5
- 4: PD6 */
uint32 rsvd3[ 19U ]; /**< 0x0054 - 0x009F: Reserved*/
uint32 GLOBALCTRL1; /**< 0x00A0: Global Control Register 1 */
uint32 rsvd4; /**< 0x00A4: Reserved */
uint32 GLOBALSTAT; /**< 0x00A8: Global Status Register */
uint32 PRCKEYREG; /**< 0x00AC: PSCON Diagnostic Compare Key Register */
uint32 LPDDCSTAT1; /**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */
uint32 LPDDCSTAT2; /**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */
uint32 rsvd5; /**< 0x00B8: Reserved */
uint32 rsvd6; /**< 0x00BC: Reserved */
uint32 ISODIAGSTAT; /**< 0x00C0: Isolation Diagnostic Status Register */
} pmmBase_t;
/** @def pmmREG
* @brief Pmm Register Frame Pointer
*
* This pointer is used by the Pmm driver to access the Pmm registers.
*/
#define pmmREG ( ( pmmBase_t * ) 0xFFFF0000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_pom.h
* @brief POM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the POM driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_POM_H__
#define __REG_POM_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Pom Register Frame Definition */
/** @struct POMBase
* @brief POM Register Frame Definition
*
* This structure is used to access the POM module registers(POM Register Map).
*/
typedef struct
{
uint32 POMGLBCTRL; /* 0x00 */
uint32 POMREV; /* 0x04 */
uint32 rsvd1; /* 0x08 */
uint32 POMFLG; /* 0x0C */
struct
{
uint32 rsdv2;
} RESERVED_REG[ 124U ];
struct /* 0x200 ... */
{
uint32 POMPROGSTART;
uint32 POMOVLSTART;
uint32 POMREGSIZE;
uint32 rsdv3;
} POMRGNCONF_ST[ 32U ];
} pomBASE_t;
/** @struct POM_CORESIGHT_ST
* @brief POM_CORESIGHT_ST Register Definition
*
* This structure is used to access the POM module registers(POM CoreSight Registers ).
*/
typedef struct
{
uint32 POMITCTRL; /* 0xF00 */
struct /* 0xF04 to 0xF9C */
{
uint32 Reserved_Reg;
} Reserved1_ST[ 39U ];
uint32 POMCLAIMSET; /* 0xFA0 */
uint32 POMCLAIMCLR; /* 0xFA4 */
uint32 rsvd1[ 2U ]; /* 0xFA8 */
uint32 POMLOCKACCESS; /* 0xFB0 */
uint32 POMLOCKSTATUS; /* 0xFB4 */
uint32 POMAUTHSTATUS; /* 0xFB8 */
uint32 rsvd2[ 3U ]; /* 0xFBC */
uint32 POMDEVID; /* 0xFC8 */
uint32 POMDEVTYPE; /* 0xFCC */
uint32 POMPERIPHERALID4; /* 0xFD0 */
uint32 POMPERIPHERALID5; /* 0xFD4 */
uint32 POMPERIPHERALID6; /* 0xFD8 */
uint32 POMPERIPHERALID7; /* 0xFDC */
uint32 POMPERIPHERALID0; /* 0xFE0 */
uint32 POMPERIPHERALID1; /* 0xFE4 */
uint32 POMPERIPHERALID2; /* 0xFE8 */
uint32 POMPERIPHERALID3; /* 0xFEC */
uint32 POMCOMPONENTID0; /* 0xFF0 */
uint32 POMCOMPONENTID1; /* 0xFF4 */
uint32 POMCOMPONENTID2; /* 0xFF8 */
uint32 POMCOMPONENTID3; /* 0xFFC */
} POM_CORESIGHT_ST;
#define pomREG ( ( pomBASE_t * ) 0xFFA04000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_rtp.h
* @brief RTP Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the RTP driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_RTP_H__
#define __REG_RTP_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Rtp Register Frame Definition */
/** @struct rtpBase
* @brief RTP Base Register Definition
*
* This structure is used to access the RTP module registers.
*/
/** @typedef rtpBASE_t
* @brief RTP Register Frame Type Definition
*
* This type is used to access the RTP Registers.
*/
typedef volatile struct rtpBase
{
uint32 GLBCTRL; /**< 0x0000: RTP Global Control Register */
uint32 TRENA; /**< 0x0004: RTP Trace Enable Register */
uint32 GSR; /**< 0x0008: RTP Global Status Register */
uint32 RAM1REG1; /**< 0x000C: RTP RAM 1 Trace Region 1 Register */
uint32 RAM1REG2; /**< 0x0010: RTP RAM 1 Trace Region 2 Register */
uint32 RAM2REG1; /**< 0x0014: RTP RAM 2 Trace Region 1 Register */
uint32 RAM2REG2; /**< 0x0018: RTP RAM 2 Trace Region 2 Register */
uint32 rsvd1[ 2U ]; /**< 0x001C: Reserved
*/
uint32 ERREG1; /**< 0x0024: RTP Peripheral Trace Region 1 Register */
uint32 ERREG2; /**< 0x0028: RTP Peripheral Trace Region 2 Register */
uint32 DDMW; /**< 0x002C: RTP Direct Data Mode Write Register */
uint32 rsvd2; /**< 0x0030: Reserved */
uint32 PC0; /**< 0x0034: RTP Pin Control 0 Register */
uint32 PC1; /**< 0x0038: RTP Pin Control 1 Register */
uint32 PC2; /**< 0x003C: RTP Pin Control 2 Register */
uint32 PC3; /**< 0x0040: RTP Pin Control 3 Register */
uint32 PC4; /**< 0x0044: RTP Pin Control 4 Register */
uint32 PC5; /**< 0x0048: RTP Pin Control 5 Register */
uint32 PC6; /**< 0x004C: RTP Pin Control 6 Register */
uint32 PC7; /**< 0x0050: RTP Pin Control 7 Register */
uint32 PC8; /**< 0x0054: RTP Pin Control 8 Register */
} rtpBASE_t;
/** @def rtpREG
* @brief RTP Register Frame Pointer
*
* This pointer is used by the RTP driver to access the RTP module registers.
*/
#define rtpREG ( ( rtpBASE_t * ) 0xFFFFFA00U )
/** @def rtpPORT
* @brief RTP Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of RTP
* (use the GIO drivers to access the port pins).
*/
#define rtpPORT ( ( gioPORT_t * ) 0xFFFFFA38U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_sci.h
* @brief SCI Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the SCI driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_SCI_H__
#define __REG_SCI_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Sci Register Frame Definition */
/** @struct sciBase
* @brief SCI Base Register Definition
*
* This structure is used to access the SCI module registers.
*/
/** @typedef sciBASE_t
* @brief SCI Register Frame Type Definition
*
* This type is used to access the SCI Registers.
*/
typedef volatile struct sciBase
{
uint32 GCR0; /**< 0x0000 Global Control Register 0 */
uint32 GCR1; /**< 0x0004 Global Control Register 1 */
uint32 GCR2; /**< 0x0008 Global Control Register 2. Note: Applicable only to LIN – SCI
Compatibility Mode,Reserved for standalone SCI*/
uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */
uint32 CLEARINT; /**< 0x0010 Clear Interrupt Enable Register */
uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */
uint32 CLEARINTLVL; /**< 0x0018 Set Interrupt Level Register */
uint32 FLR; /**< 0x001C Interrupt Flag Register */
uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */
uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */
uint32 FORMAT; /**< 0x0028 Format Control Register */
uint32 BRS; /**< 0x002C Baud Rate Selection Register */
uint32 ED; /**< 0x0030 Emulation Register */
uint32 RD; /**< 0x0034 Receive Data Buffer */
uint32 TD; /**< 0x0038 Transmit Data Buffer */
uint32 PIO0; /**< 0x003C Pin Function Register */
uint32 PIO1; /**< 0x0040 Pin Direction Register */
uint32 PIO2; /**< 0x0044 Pin Data In Register */
uint32 PIO3; /**< 0x0048 Pin Data Out Register */
uint32 PIO4; /**< 0x004C Pin Data Set Register */
uint32 PIO5; /**< 0x0050 Pin Data Clr Register */
uint32 PIO6; /**< 0x0054: Pin Open Drain Output Enable Register */
uint32 PIO7; /**< 0x0058: Pin Pullup/Pulldown Disable Register */
uint32 PIO8; /**< 0x005C: Pin Pullup/Pulldown Selection Register */
uint32 rsdv2[ 12U ]; /**< 0x0060: Reserved */
uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */
} sciBASE_t;
/** @def sciREG1
* @brief Register Frame Pointer
*
* This pointer is used by the SCI driver to access the sci1 module registers.
*/
#define sciREG1 ( ( sciBASE_t * ) 0xFFF7E400U )
#define scilinREG ( ( sciBASE_t * ) 0xFFF7E400U )
/** @def sciPORT1
* @brief SCI1 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SCI1
* (use the GIO drivers to access the port pins).
*/
#define sciPORT1 ( ( gioPORT_t * ) 0xFFF7E440U )
#define scilinPORT ( ( gioPORT_t * ) 0xFFF7E440U )
/** @def sciREG2
* @brief Register Frame Pointer
*
* This pointer is used by the SCI driver to access the sci2 module registers.
*/
#define sciREG2 ( ( sciBASE_t * ) 0xFFF7E600U )
/** @def sciPORT2
* @brief SCI2 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SCI2
* (use the GIO drivers to access the port pins).
*/
#define sciPORT2 ( ( gioPORT_t * ) 0xFFF7E640U )
/** @def sciREG3
* @brief Register Frame Pointer
*
* This pointer is used by the SCI driver to access the sci3 module registers.
*/
#define sciREG3 ( ( sciBASE_t * ) 0xFFF7E500U )
/** @def sciPORT3
* @brief SCI3 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SCI3
* (use the GIO drivers to access the port pins).
*/
#define sciPORT3 ( ( gioPORT_t * ) 0xFFF7E540U )
/** @def sciREG4
* @brief Register Frame Pointer
*
* This pointer is used by the SCI driver to access the sci4 module registers.
*/
#define sciREG4 ( ( sciBASE_t * ) 0xFFF7E700U )
/** @def sciPORT4
* @brief SCI4 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SCI4
* (use the GIO drivers to access the port pins).
*/
#define sciPORT4 ( ( gioPORT_t * ) 0xFFF7E740U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_scm.h
* @brief SCM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the SCM driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_SCM_H__
#define __REG_SCM_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* SCM Register Frame Definition */
/** @struct scmBase
* @brief SCM Base Register Definition
*
* This structure is used to access the SCM module registers.
*/
/** @typedef scmBASE_t
* @brief SCM Register Frame Type Definition
*
* This type is used to access the SCM Registers.
*/
typedef volatile struct scmBase
{
uint32 SCMREVID; /**< 0x0000: SCM REVID Register */
uint32 SCMCNTRL; /**< 0x0004: SCM Control Register */
uint32 SCMTHRESHOLD; /**< 0x0008: SCM Compare Threshold Counter Register */
uint32 rsvd1; /**< 0x000C: Reserved */
uint32 SCMIAERR0STAT; /**< 0x0010: SCM Initiator Error0 Status Register */
uint32 SCMIAERR1STAT; /**< 0x0014: SCM Initiator Error1 Status Register */
uint32 SCMIASTAT; /**< 0x0018: SCM Initiator Active Status Register */
uint32 rsvd2; /**< 0x001C: Reserved */
uint32 SCMTASTAT; /**< 0x0020: SCM Target Active Status Register */
} scmBASE_t;
#define scmREG1 ( ( scmBASE_t * ) 0xFFFF0A00U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file reg_sdcmmr.h
* @brief SDCMMR Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the SDCMMR driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_SDCMMR_H__
#define __REG_SDCMMR_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* SDCMMR Register Frame Definition */
/** @struct sdcmmrBase
* @brief SDCMMR Base Register Definition
*
* This structure is used to access the SDCMMR module registers.
*/
/** @typedef sdcmmrBASE_t
* @brief SDCMMR Register Frame Type Definition
*
* This type is used to access the SDCMMR Registers.
*/
typedef volatile struct sdcmmrBase
{
uint32 SDC_STATUS; /**< SDC Status Register */
uint32 SDC_CONTROL; /**< SDC Control Register */
uint32 ERR_GENERIC_PARITY; /**< Error Generic Parity Register */
uint32 ERR_UNEXPECTED_TRANS; /**< Error Unexpected Transaction Register */
uint32 ERR_TRANS_ID; /**< Error Transaction ID Register */
uint32 ERR_TRANS_SIGNATURE; /**< Error Transaction Signature Register */
uint32 ERR_TRANS_TYPE; /**< Error Transaction Type Register */
uint32 ERR_USER_PARITY; /**< IError User Parity Register */
uint32 SERR_UNEXPECTED_MID; /**< Slave Error Unexpected Master ID register */
uint32 SERR_ADDR_DECODE; /**< Slave Error Address Decode Register */
uint32 SERR_USER_PARITY; /**< Slave Error User Parity Register */
} sdcmmrBASE_t;
#define sdcmmrREG1 ( ( sdcmmrBASE_t * ) 0xFA000000U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file reg_spi.h
* @brief SPI Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the SPI driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_SPI_H__
#define __REG_SPI_H__
#include "sys_common.h"
#include "reg_gio.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Spi Register Frame Definition */
/** @struct spiBase
* @brief SPI Register Definition
*
* This structure is used to access the SPI module registers.
*/
/** @typedef spiBASE_t
* @brief SPI Register Frame Type Definition
*
* This type is used to access the SPI Registers.
*/
typedef volatile struct spiBase
{
uint32 GCR0; /**< 0x0000: Global Control 0 */
uint32 GCR1; /**< 0x0004: Global Control 1 */
uint32 INT0; /**< 0x0008: Interrupt Register */
uint32 LVL; /**< 0x000C: Interrupt Level */
uint32 FLG; /**< 0x0010: Interrupt flags */
uint32 PC0; /**< 0x0014: Function Pin Enable */
uint32 PC1; /**< 0x0018: Pin Direction */
uint32 PC2; /**< 0x001C: Pin Input Latch */
uint32 PC3; /**< 0x0020: Pin Output Latch */
uint32 PC4; /**< 0x0024: Output Pin Set */
uint32 PC5; /**< 0x0028: Output Pin Clr */
uint32 PC6; /**< 0x002C: Open Drain Output Enable */
uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */
uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */
uint32 DAT0; /**< 0x0038: Transmit Data */
uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
uint32 BUF; /**< 0x0040: Receive Buffer */
uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
uint32 DELAY; /**< 0x0048: Delays */
uint32 DEF; /**< 0x004C: Default Chip Select */
uint32 FMT0; /**< 0x0050: Data Format 0 */
uint32 FMT1; /**< 0x0054: Data Format 1 */
uint32 FMT2; /**< 0x0058: Data Format 2 */
uint32 FMT3; /**< 0x005C: Data Format 3 */
uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
uint32 RESERVED[ 51U ]; /**< 0x0068 to 0x0130: Reserved */
uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
} spiBASE_t;
/** @def spiREG1
* @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer
*
* This pointer is used by the SPI driver to access the spi module registers.
*/
#define spiREG1 ( ( spiBASE_t * ) 0xFFF7F400U )
/** @def spiPORT1
* @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SPI1
* (use the GIO drivers to access the port pins).
*/
#define spiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U )
/** @def spiREG2
* @brief SPI2 Register Frame Pointer
*
* This pointer is used by the SPI driver to access the spi module registers.
*/
#define spiREG2 ( ( spiBASE_t * ) 0xFFF7F600U )
/** @def spiPORT2
* @brief SPI2 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SPI2
* (use the GIO drivers to access the port pins).
*/
#define spiPORT2 ( ( gioPORT_t * ) 0xFFF7F618U )
/** @def spiREG3
* @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer
*
* This pointer is used by the SPI driver to access the spi module registers.
*/
#define spiREG3 ( ( spiBASE_t * ) 0xFFF7F800U )
/** @def spiPORT3
* @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SPI3
* (use the GIO drivers to access the port pins).
*/
#define spiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U )
/** @def spiREG4
* @brief SPI4 Register Frame Pointer
*
* This pointer is used by the SPI driver to access the spi module registers.
*/
#define spiREG4 ( ( spiBASE_t * ) 0xFFF7FA00U )
/** @def spiPORT4
* @brief SPI4 GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SPI4
* (use the GIO drivers to access the port pins).
*/
#define spiPORT4 ( ( gioPORT_t * ) 0xFFF7FA18U )
/** @def spiREG5
* @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer
*
* This pointer is used by the SPI driver to access the spi module registers.
*/
#define spiREG5 ( ( spiBASE_t * ) 0xFFF7FC00U )
/** @def spiPORT5
* @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of SPI5
* (use the GIO drivers to access the port pins).
*/
#define spiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_stc.h
* @brief STC Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the STC driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_STC_H__
#define __REG_STC_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Stc Register Frame Definition */
/** @struct stcBase
* @brief STC Base Register Definition
*
* This structure is used to access the STC module registers.
*/
/** @typedef stcBASE_t
* @brief STC Register Frame Type Definition
*
* This type is used to access the STC Registers.
*/
typedef volatile struct stcBase
{
uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */
uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */
uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */
uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */
uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */
uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */
uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */
uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */
uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */
uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */
uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */
uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */
uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */
uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */
uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */
uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */
uint32 STCCADDR1; /**< 0x0040: STC Current ROM Address Register - CORE2 */
uint32 STCCLKDIV; /**< 0x0044: STC Clock Divider Register */
uint32 STCSEGPLR; /**< 0x0048: STC Segment First Preload Register */
} stcBASE_t;
#define stcREG1 ( ( stcBASE_t * ) 0xFFFFE600U )
#define stcREG2 ( ( stcBASE_t * ) 0xFFFF0800U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file reg_system.h
* @brief System Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_SYSTEM_H__
#define __REG_SYSTEM_H__
#include "sys_common.h"
#include "reg_gio.h"
/* System Register Frame 1 Definition */
/** @struct systemBase1
* @brief System Register Frame 1 Definition
*
* This type is used to access the System 1 Registers.
*/
/** @typedef systemBASE1_t
* @brief System Register Frame 1 Type Definition
*
* This type is used to access the System 1 Registers.
*/
typedef volatile struct systemBase1
{
uint32 SYSPC1; /* 0x0000 */
uint32 SYSPC2; /* 0x0004 */
uint32 SYSPC3; /* 0x0008 */
uint32 SYSPC4; /* 0x000C */
uint32 SYSPC5; /* 0x0010 */
uint32 SYSPC6; /* 0x0014 */
uint32 SYSPC7; /* 0x0018 */
uint32 SYSPC8; /* 0x001C */
uint32 SYSPC9; /* 0x0020 */
uint32 rsvd1; /* 0x0024 */
uint32 rsvd2; /* 0x0028 */
uint32 rsvd3; /* 0x002C */
uint32 CSDIS; /* 0x0030 */
uint32 CSDISSET; /* 0x0034 */
uint32 CSDISCLR; /* 0x0038 */
uint32 CDDIS; /* 0x003C */
uint32 CDDISSET; /* 0x0040 */
uint32 CDDISCLR; /* 0x0044 */
uint32 GHVSRC; /* 0x0048 */
uint32 VCLKASRC; /* 0x004C */
uint32 RCLKSRC; /* 0x0050 */
uint32 CSVSTAT; /* 0x0054 */
uint32 MSTGCR; /* 0x0058 */
uint32 MINITGCR; /* 0x005C */
uint32 MSINENA; /* 0x0060 */
uint32 MSTFAIL; /* 0x0064 */
uint32 MSTCGSTAT; /* 0x0068 */
uint32 MINISTAT; /* 0x006C */
uint32 PLLCTL1; /* 0x0070 */
uint32 PLLCTL2; /* 0x0074 */
uint32 SYSPC10; /* 0x0078 */
uint32 DIEIDL; /* 0x007C */
uint32 DIEIDH; /* 0x0080 */
uint32 rsvd4; /* 0x0084 */
uint32 LPOMONCTL; /* 0x0088 */
uint32 CLKTEST; /* 0x008C */
uint32 DFTCTRLREG1; /* 0x0090 */
uint32 DFTCTRLREG2; /* 0x0094 */
uint32 rsvd5; /* 0x0098 */
uint32 rsvd6; /* 0x009C */
uint32 GPREG1; /* 0x00A0 */
uint32 rsvd7; /* 0x00A4 */
uint32 rsvd8; /* 0x00A8 */
uint32 rsvd9; /* 0x00AC */
uint32 SSIR1; /* 0x00B0 */
uint32 SSIR2; /* 0x00B4 */
uint32 SSIR3; /* 0x00B8 */
uint32 SSIR4; /* 0x00BC */
uint32 RAMGCR; /* 0x00C0 */
uint32 BMMCR1; /* 0x00C4 */
uint32 rsvd10; /* 0x00C8 */
uint32 CPURSTCR; /* 0x00CC */
uint32 CLKCNTL; /* 0x00D0 */
uint32 ECPCNTL; /* 0x00D4 */
uint32 rsvd11; /* 0x00D8 */
uint32 DEVCR1; /* 0x00DC */
uint32 SYSECR; /* 0x00E0 */
uint32 SYSESR; /* 0x00E4 */
uint32 SYSTASR; /* 0x00E8 */
uint32 GBLSTAT; /* 0x00EC */
uint32 DEVID; /* 0x00F0 */
uint32 SSIVEC; /* 0x00F4 */
uint32 SSIF; /* 0x00F8 */
} systemBASE1_t;
/** @def systemREG1
* @brief System Register Frame 1 Pointer
*
* This pointer is used by the system driver to access the system frame 1 registers.
*/
#define systemREG1 ( ( systemBASE1_t * ) 0xFFFFFF00U )
/** @def systemPORT
* @brief ECLK GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of System/Eclk
* (use the GIO drivers to access the port pins).
*/
#define systemPORT ( ( gioPORT_t * ) 0xFFFFFF04U )
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* System Register Frame 2 Definition */
/** @struct systemBase2
* @brief System Register Frame 2 Definition
*
* This type is used to access the System 2 Registers.
*/
/** @typedef systemBASE2_t
* @brief System Register Frame 2 Type Definition
*
* This type is used to access the System 2 Registers.
*/
typedef volatile struct systemBase2
{
uint32 PLLCTL3; /* 0x0000 */
uint32 rsvd1; /* 0x0004 */
uint32 STCCLKDIV; /* 0x0008 */
uint32 rsvd2[ 6U ]; /* 0x000C */
uint32 ECPCNTL; /* 0x0024 */
uint32 ECPCNTL1; /* 0x0028 */
uint32 rsvd3[ 4U ]; /* 0x002C */
uint32 CLK2CNTRL; /* 0x003C */
uint32 VCLKACON1; /* 0x0040 */
uint32 rsvd4[ 4U ]; /* 0x0044 */
uint32 HCLKCNTL; /* 0x0054 */
uint32 rsvd5[ 6U ]; /* 0x0058 */
uint32 CLKSLIP; /* 0x0070 */
uint32 rsvd6; /* 0x0074 */
uint32 IP1ECCERREN; /* 0x0078 */
uint32 rsvd7[ 28U ]; /* 0x007C */
uint32 EFC_CTLEN; /* 0x00EC */
uint32 DIEIDL_REG0; /* 0x00F0 */
uint32 DIEIDH_REG1; /* 0x00F4 */
uint32 DIEIDL_REG2; /* 0x00F8 */
uint32 DIEIDH_REG3; /* 0x00FC */
} systemBASE2_t;
/** @def systemREG2
* @brief System Register Frame 2 Pointer
*
* This pointer is used by the system driver to access the system frame 2 registers.
*/
#define systemREG2 ( ( systemBASE2_t * ) 0xFFFFE100U )
#endif

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/** @file reg_vim.h
* @brief VIM Register Layer Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __REG_VIM_H__
#define __REG_VIM_H__
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Vim Register Frame Definition */
/** @struct vimBase
* @brief Vim Register Frame Definition
*
* This type is used to access the Vim Registers.
*/
/** @typedef vimBASE_t
* @brief VIM Register Frame Type Definition
*
* This type is used to access the VIM Registers.
*/
typedef volatile struct vimBase
{
uint32 rsvd1[ 59U ]; /* 0x0000 - 0x00E8 Reserved */
uint32 ECCSTAT; /* 0x00EC */
uint32 ECCCTL; /* 0x00F0 */
uint32 UERRADDR; /* 0x00F4 */
uint32 FBVECADDR; /* 0x00F8 */
uint32 SBERRADDR; /* 0x00FC */
uint32 IRQINDEX; /* 0x0100 */
uint32 FIQINDEX; /* 0x0104 */
uint32 rsvd2; /* 0x0108 */
uint32 rsvd3; /* 0x010C */
uint32 FIRQPR0; /* 0x0110 */
uint32 FIRQPR1; /* 0x0114 */
uint32 FIRQPR2; /* 0x0118 */
uint32 FIRQPR3; /* 0x011C */
uint32 INTREQ0; /* 0x0120 */
uint32 INTREQ1; /* 0x0124 */
uint32 INTREQ2; /* 0x0128 */
uint32 INTREQ3; /* 0x012C */
uint32 REQMASKSET0; /* 0x0130 */
uint32 REQMASKSET1; /* 0x0134 */
uint32 REQMASKSET2; /* 0x0138 */
uint32 REQMASKSET3; /* 0x013C */
uint32 REQMASKCLR0; /* 0x0140 */
uint32 REQMASKCLR1; /* 0x0144 */
uint32 REQMASKCLR2; /* 0x0148 */
uint32 REQMASKCLR3; /* 0x014C */
uint32 WAKEMASKSET0; /* 0x0150 */
uint32 WAKEMASKSET1; /* 0x0154 */
uint32 WAKEMASKSET2; /* 0x0158 */
uint32 WAKEMASKSET3; /* 0x015C */
uint32 WAKEMASKCLR0; /* 0x0160 */
uint32 WAKEMASKCLR1; /* 0x0164 */
uint32 WAKEMASKCLR2; /* 0x0168 */
uint32 WAKEMASKCLR3; /* 0x016C */
uint32 IRQVECREG; /* 0x0170 */
uint32 FIQVECREG; /* 0x0174 */
uint32 CAPEVT; /* 0x0178 */
uint32 rsvd4; /* 0x017C */
uint32 CHANCTRL[ 32U ]; /* 0x0180-0x02FC */
} vimBASE_t;
#define vimREG ( ( vimBASE_t * ) 0xFFFFFD00U )
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif

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/** @file rtp.h
* @brief RTP Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __RTP_H__
#define __RTP_H__
#include "reg_rtp.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Configuration registers */
typedef struct rtp_config_reg
{
uint32 CONFIG_PC0;
uint32 CONFIG_PC1;
uint32 CONFIG_PC3;
uint32 CONFIG_PC6;
uint32 CONFIG_PC7;
uint32 CONFIG_PC8;
} rtp_config_reg_t;
#define RTP_PC3_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define RTP_PC1_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
#define RTP_PC6_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define RTP_PC8_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
#define RTP_PC7_CONFIGVALUE \
( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) )
#define RTP_PC0_CONFIGVALUE \
( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \
| ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \
| ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \
| ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \
| ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \
| ( uint32 ) ( ( uint32 ) 1U << 18U ) )
/**
* @defgroup RTP RTP
* @brief RAM Trace Port.
*
* RAM Trace Port (RTP) module provides the features to datalog the RAM contents of the
*devices or accesses to peripherals without program intrusion. It can trace all data
*write or read accesses to internal RAM.
*
* Related Files
* - reg_rtp.h
* - rtp.h
* - rtp.c
* @addtogroup RTP
* @{
*/
/* RTP Interface Functions */
void rtpInit( void );
void rtpGetConfigValue( rtp_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file sci.h
* @brief SCI Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SCI_H__
#define __SCI_H__
#include "reg_sci.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum sciIntFlags
* @brief Interrupt Flag Definitions
*
* Used with sciEnableNotification, sciDisableNotification
*/
enum sciIntFlags
{
SCI_FE_INT = 0x04000000U, /* framing error */
SCI_OE_INT = 0x02000000U, /* overrun error */
SCI_PE_INT = 0x01000000U, /* parity error */
SCI_RX_INT = 0x00000200U, /* receive buffer ready */
SCI_TX_INT = 0x00000100U, /* transmit buffer ready */
SCI_WAKE_INT = 0x00000002U, /* wakeup */
SCI_BREAK_INT = 0x00000001U /* break detect */
};
/** @def SCI_IDLE
* @brief Alias name for the SCI IDLE Flag
*
* This is an alias name for the SCI IDLE Flag.
*
*/
#define SCI_IDLE 0x00000004U
/** @struct sciBase
* @brief SCI Register Definition
*
* This structure is used to access the SCI module registers.
*/
/** @typedef sciBASE_t
* @brief SCI Register Frame Type Definition
*
* This type is used to access the SCI Registers.
*/
enum sciPinSelect
{
PIN_SCI_TX = 4U,
PIN_SCI_RX = 2U
};
/* Configuration registers */
typedef struct sci_config_reg
{
uint32 CONFIG_GCR0;
uint32 CONFIG_GCR1;
uint32 CONFIG_SETINT;
uint32 CONFIG_SETINTLVL;
uint32 CONFIG_FORMAT;
uint32 CONFIG_BRS;
uint32 CONFIG_PIO0;
uint32 CONFIG_PIO1;
uint32 CONFIG_PIO6;
uint32 CONFIG_PIO7;
uint32 CONFIG_PIO8;
} sci_config_reg_t;
/* Configuration registers initial value for SCI3*/
#define SCI3_GCR0_CONFIGVALUE 0x00000001U
#define SCI3_GCR1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 5U ) | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( 0x03000080U ) )
#define SCI3_SETINTLVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define SCI3_SETINT_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define SCI3_FORMAT_CONFIGVALUE ( 8U - 1U )
#define SCI3_BRS_CONFIGVALUE ( 40U )
#define SCI3_PIO0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) )
#define SCI3_PIO1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define SCI3_PIO6_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define SCI3_PIO7_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define SCI3_PIO8_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) )
/* Configuration registers initial value for SCI4*/
#define SCI4_GCR0_CONFIGVALUE 0x00000001U
#define SCI4_GCR1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 5U ) | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) \
| ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \
| ( uint32 ) ( 0x03000080U ) )
#define SCI4_SETINTLVL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define SCI4_SETINT_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) )
#define SCI4_FORMAT_CONFIGVALUE ( 8U - 1U )
#define SCI4_BRS_CONFIGVALUE ( 40U )
#define SCI4_PIO0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) )
#define SCI4_PIO1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define SCI4_PIO6_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define SCI4_PIO7_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) )
#define SCI4_PIO8_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) )
/**
* @defgroup SCI SCI
* @brief Serial Communication Interface Module.
*
* The SCI module is a universal asynchronous receiver-transmitter that implements the
*standard nonreturn to zero format. The SCI can be used to communicate, for example,
*through an RS-232 port or over a K-line.
*
* Related Files
* - reg_sci.h
* - sci.h
* - sci.c
* @addtogroup SCI
* @{
*/
/* SCI Interface Functions */
void sciInit( void );
void sciSetFunctional( sciBASE_t * sci, uint32 port );
void sciSetBaudrate( sciBASE_t * sci, uint32 baud );
uint32 sciIsTxReady( sciBASE_t * sci );
void sciSendByte( sciBASE_t * sci, uint8 byte );
void sciSend( sciBASE_t * sci, uint32 length, uint8 * data );
uint32 sciIsRxReady( sciBASE_t * sci );
uint32 sciIsIdleDetected( sciBASE_t * sci );
uint32 sciRxError( sciBASE_t * sci );
uint32 sciReceiveByte( sciBASE_t * sci );
void sciReceive( sciBASE_t * sci, uint32 length, uint8 * data );
void sciEnableNotification( sciBASE_t * sci, uint32 flags );
void sciDisableNotification( sciBASE_t * sci, uint32 flags );
void sciEnableLoopback( sciBASE_t * sci, loopBackType_t Loopbacktype );
void sciDisableLoopback( sciBASE_t * sci );
void sciEnterResetState( sciBASE_t * sci );
void sciExitResetState( sciBASE_t * sci );
void sci3GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type );
void sci4GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type );
/** @fn void sciNotification(sciBASE_t *sci, uint32 flags)
* @brief Interrupt callback
* @param[in] sci - sci module base address
* @param[in] flags - copy of error interrupt flags
*
* This is a callback that is provided by the application and is called upon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void sciNotification( sciBASE_t * sci, uint32 flags );
/* USER CODE BEGIN (1) */
/** @fn void sciDisplayData(sciBASE_t *sci, uint8 *text,uint32 length)
* @brief Write data out to UART using the given SCI register
*
* @param[in] sci - SCI module base address
* @param[in] text - Pointer to the data that is going to be displayed on console
* @param[in] length - Number of bytes of data that are to be written
* This function will write the values in the text buffer out to be read over UART
*
*/
void sciDisplayData( sciBASE_t * sci, uint8_t * text, uint32 length );
/** @fn void sciDisplayText(sciBASE_t *sci, uint8 *text,uint32 length)
* @brief Write text out to UART using the given SCI register
*
* @param[in] sci - SCI module base address
* @param[in] text - Pointer to the string that is going to be displayed on console
* @param[in] length - Number of characters that are to be written
* This function will write string in the text buffer out to be read over UART
*
*/
void sciDisplayText( sciBASE_t * sci, char * text, uint32 length );
/** @fn void sci_print(char * str)
* @brief Simple print function that takes in a str and prints to SCI/UART
*
* @param[in] str - Pointer to the string that is going to be displayed on console
* This function will write string in the str pointer out to be read over UART
*
*/
void sci_print( char * str );
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* ifndef __SCI_H__ */

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/** @file spi.h
* @brief SPI Driver Definition File
* @date 11-Dec-2018
* @version 04.07.01
*
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SPI_H__
#define __SPI_H__
#include "reg_spi.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @enum chipSelect
* @brief Transfer Group Chip Select
*/
enum spiChipSelect
{
SPI_CS_NONE = 0xFFU,
SPI_CS_0 = 0xFEU,
SPI_CS_1 = 0xFDU,
SPI_CS_2 = 0xFBU,
SPI_CS_3 = 0xF7U,
SPI_CS_4 = 0xEFU,
SPI_CS_5 = 0xDFU,
SPI_CS_6 = 0xBFU,
SPI_CS_7 = 0x7FU
};
/** @enum spiPinSelect
* @brief spi Pin Select
*/
enum spiPinSelect
{
SPI_PIN_CS0 = 0U,
SPI_PIN_CS1 = 1U,
SPI_PIN_CS2 = 2U,
SPI_PIN_CS3 = 3U,
SPI_PIN_CS4 = 4U,
SPI_PIN_CS5 = 5U,
SPI_PIN_CS6 = 6U,
SPI_PIN_CS7 = 7U,
SPI_PIN_ENA = 8U,
SPI_PIN_CLK = 9U,
SPI_PIN_SIMO = 10U,
SPI_PIN_SOMI = 11U,
SPI_PIN_SIMO_1 = 17U,
SPI_PIN_SIMO_2 = 18U,
SPI_PIN_SIMO_3 = 19U,
SPI_PIN_SIMO_4 = 20U,
SPI_PIN_SIMO_5 = 21U,
SPI_PIN_SIMO_6 = 22U,
SPI_PIN_SIMO_7 = 23U,
SPI_PIN_SOMI_1 = 25U,
SPI_PIN_SOMI_2 = 26U,
SPI_PIN_SOMI_3 = 27U,
SPI_PIN_SOMI_4 = 28U,
SPI_PIN_SOMI_5 = 29U,
SPI_PIN_SOMI_6 = 30U,
SPI_PIN_SOMI_7 = 31U
};
/** @enum dataformat
* @brief SPI dataformat register select
*/
typedef enum dataformat
{
SPI_FMT_0 = 0U,
SPI_FMT_1 = 1U,
SPI_FMT_2 = 2U,
SPI_FMT_3 = 3U
} SPIDATAFMT_t;
/** @struct spiDAT1RegConfig
* @brief SPI data register configuration
*/
typedef struct spiDAT1RegConfig
{
boolean CS_HOLD;
boolean WDEL;
SPIDATAFMT_t DFSEL;
uint8 CSNR;
} spiDAT1_t;
/** @enum SpiTxRxDataStatus
* @brief SPI Data Status
*/
typedef enum SpiTxRxDataStatus
{
SPI_READY = 0U,
SPI_PENDING = 1U,
SPI_COMPLETED = 2U
} SpiDataStatus_t;
/* USER CODE BEGIN (0) */
/* USER CODE END */
typedef struct spi_config_reg
{
uint32 CONFIG_GCR1;
uint32 CONFIG_INT0;
uint32 CONFIG_LVL;
uint32 CONFIG_PC0;
uint32 CONFIG_PC1;
uint32 CONFIG_PC6;
uint32 CONFIG_PC7;
uint32 CONFIG_PC8;
uint32 CONFIG_DELAY;
uint32 CONFIG_FMT0;
uint32 CONFIG_FMT1;
uint32 CONFIG_FMT2;
uint32 CONFIG_FMT3;
} spi_config_reg_t;
/**
* @defgroup SPI SPI
* @brief Serial Peripheral Interface Module.
*
* SPI is a high-speed synchronous serial input/output port that allows a serial bit
* stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a
* programmed bit-transfer rate.
*
* Related Files
* - reg_spi.h
* - spi.h
* - spi.c
* @addtogroup SPI
* @{
*/
/* SPI Interface Functions */
void spiInit( void );
void spiSetFunctional( spiBASE_t * spi, uint32 port );
void spiEnableNotification( spiBASE_t * spi, uint32 flags );
void spiDisableNotification( spiBASE_t * spi, uint32 flags );
uint32 spiTransmitData( spiBASE_t * spi,
spiDAT1_t * dataconfig_t,
uint32 blocksize,
uint16 * srcbuff );
void spiSendData( spiBASE_t * spi,
spiDAT1_t * dataconfig_t,
uint32 blocksize,
uint16 * srcbuff );
uint32 spiReceiveData( spiBASE_t * spi,
spiDAT1_t * dataconfig_t,
uint32 blocksize,
uint16 * destbuff );
void spiGetData( spiBASE_t * spi,
spiDAT1_t * dataconfig_t,
uint32 blocksize,
uint16 * destbuff );
uint32 spiTransmitAndReceiveData( spiBASE_t * spi,
spiDAT1_t * dataconfig_t,
uint32 blocksize,
uint16 * srcbuff,
uint16 * destbuff );
void spiSendAndGetData( spiBASE_t * spi,
spiDAT1_t * dataconfig_t,
uint32 blocksize,
uint16 * srcbuff,
uint16 * destbuff );
void spiEnableLoopback( spiBASE_t * spi, loopBackType_t Loopbacktype );
void spiDisableLoopback( spiBASE_t * spi );
SpiDataStatus_t SpiTxStatus( spiBASE_t * spi );
SpiDataStatus_t SpiRxStatus( spiBASE_t * spi );
/** @fn void spiNotification(spiBASE_t *spi, uint32 flags)
* @brief Interrupt callback
* @param[in] spi - Spi module base address
* @param[in] flags - Copy of error interrupt flags
*
* This is a callback that is provided by the application and is called upon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void spiNotification( spiBASE_t * spi, uint32 flags );
/** @fn void spiEndNotification(spiBASE_t *spi)
* @brief Interrupt callback for End of TX or RX data length.
* @param[in] spi - Spi module base address
*
* This is a callback that is provided by the application and is called upon
* an interrupt at the End of TX or RX data length.
*/
void spiEndNotification( spiBASE_t * spi );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file sys_common.h
* @brief Common Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - General Definitions
* .
* which are relevant for all drivers.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_COMMON_H__
#define __SYS_COMMON_H__
#include "hal_stdtypes.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/************************************************************/
/* Type Definitions */
/************************************************************/
#ifndef _TBOOLEAN_DECLARED
typedef boolean tBoolean;
#define _TBOOLEAN_DECLARED
#endif
/** @enum loopBackType
* @brief Loopback type definition
*/
/** @typedef loopBackType_t
* @brief Loopback type Type Definition
*
* This type is used to select the module Loopback type Digital or Analog loopback.
*/
typedef enum loopBackType
{
Digital_Lbk = 0U,
Analog_Lbk = 1U
} loopBackType_t;
/** @enum config_value_type
* @brief config type definition
*/
/** @typedef config_value_type_t
* @brief config type Type Definition
*
* This type is used to specify the Initial and Current value.
*/
typedef enum config_value_type
{
InitialValue,
CurrentValue
} config_value_type_t;
#ifndef __little_endian__
#define __little_endian__ 1
#endif
#ifndef __LITTLE_ENDIAN__
#define __LITTLE_ENDIAN__ 1
#endif
/* USER CODE BEGIN (1) */
/* USER CODE END */
/********************************************************************************/
/* The ASSERT macro, which does the actual assertion checking. Typically, this */
/* will be for procedure arguments. */
/********************************************************************************/
#ifdef DEBUG
#define ASSERT( expr ) \
{ \
if( !( expr ) ) \
{ \
__error__( __FILE__, __LINE__ ); \
} \
}
#else
#define ASSERT( expr )
#endif
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* USER CODE BEGIN (3) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file sys_core.h
* @brief System Core Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Core Interface Functions
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_CORE_H__
#define __SYS_CORE_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @def USER_STACK_LENGTH
* @brief USER Mode Stack length (in bytes)
*
* Alias for USER Mode Stack length (in bytes)
*
* @note: Use this macro for USER Mode Stack length (in bytes)
*/
#define USER_STACK_LENGTH 0x00000300U
/** @def SVC_STACK_LENGTH
* @brief SVC Mode Stack length (in bytes)
*
* Alias for SVC Mode Stack length (in bytes)
*
* @note: Use this macro for SVC Mode Stack length (in bytes)
*/
#define SVC_STACK_LENGTH 0x00000100U
/** @def FIQ_STACK_LENGTH
* @brief FIQ Mode Stack length (in bytes)
*
* Alias for FIQ Mode Stack length (in bytes)
*
* @note: Use this macro for FIQ Mode Stack length (in bytes)
*/
#define FIQ_STACK_LENGTH 0x00000100U
/** @def IRQ_STACK_LENGTH
* @brief IRQ Mode Stack length (in bytes)
*
* Alias for IRQ Mode Stack length (in bytes)
*
* @note: Use this macro for IRQ Mode Stack length (in bytes)
*/
#define IRQ_STACK_LENGTH 0x00000100U
/** @def ABORT_STACK_LENGTH
* @brief ABORT Mode Stack length (in bytes)
*
* Alias for ABORT Mode Stack length (in bytes)
*
* @note: Use this macro for ABORT Mode Stack length (in bytes)
*/
#define ABORT_STACK_LENGTH 0x00000100U
/** @def UNDEF_STACK_LENGTH
* @brief UNDEF Mode Stack length (in bytes)
*
* Alias for UNDEF Mode Stack length (in bytes)
*
* @note: Use this macro for UNDEF Mode Stack length (in bytes)
*/
#define UNDEF_STACK_LENGTH 0x00000100U
/* System Core Interface Functions */
/** @fn void _coreInitRegisters_(void)
* @brief Initialize Core register
*/
void _coreInitRegisters_( void );
/** @fn void _coreInitStackPointer_(void)
* @brief Initialize Core stack pointer
*/
void _coreInitStackPointer_( void );
/** @fn void _getCPSRValue_(void)
* @brief Get CPSR Value
*/
uint32 _getCPSRValue_( void );
/** @fn void _checkMemInitOn_(void)
* @brief Wait until Mem Init is complete if initiated already.
*/
void _checkMemInitOn_( void );
/** @fn void _gotoCPUIdle_(void)
* @brief Take CPU to Idle state
*/
void _gotoCPUIdle_( void );
/** @fn void _coreEnableIrqVicOffset_(void)
* @brief Enable Irq offset propagation via Vic controller
*/
void _coreEnableIrqVicOffset_( void );
/** @fn void _coreEnableVfp_(void)
* @brief Enable vector floating point unit
*/
void _coreEnableVfp_( void );
/** @fn void _coreEnableEventBusExport_(void)
* @brief Enable event bus export for external monitoring modules
* @note It is required to enable event bus export to process ecc issues.
*
* This function enables event bus exports to external monitoring modules
* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
*/
void _coreEnableEventBusExport_( void );
/** @fn void _coreDisableEventBusExport_(void)
* @brief Disable event bus export for external monitoring modules
*
* This function disables event bus exports to external monitoring modules
* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
*/
void _coreDisableEventBusExport_( void );
/** @fn uint32 _coreGetDataFault_(void)
* @brief Get core data fault status register
* @return The function will return the data fault status register value:
* - bit [10,3..0]:
* - 0b00001: Alignment -> address is valid
* - 0b00000: Background -> address is valid
* - 0b01101: Permission -> address is valid
* - 0b01000: Precise External Abort -> address is valid
* - 0b10110: Imprecise External Abort -> address is
* unpredictable
* - 0b11001: Precise ECC Error -> address is valid
* - 0b11000: Imprecise ECC Error -> address is
* unpredictable
* - 0b00010: Debug -> address is unchanged
* - bit [11]:
* - 0: Read
* - 1: Write
* - bit [12]:
* - 0: AXI Decode Error (DECERR)
* - 1: AXI Slave Error (SLVERR)
*/
uint32 _coreGetDataFault_( void );
/** @fn void _coreClearDataFault_(void)
* @brief Clear core data fault status register
*/
void _coreClearDataFault_( void );
/** @fn uint32 _coreGetInstructionFault_(void)
* @brief Get core instruction fault status register
* @return The function will return the instruction fault status register value:
* - bit [10,3..0]:
* - 0b00001: Alignment -> address is valid
* - 0b00000: Background -> address is valid
* - 0b01101: Permission -> address is valid
* - 0b01000: Precise External Abort -> address is valid
* - 0b10110: Imprecise External Abort -> address is
* unpredictable
* - 0b11001: Precise ECC Error -> address is valid
* - 0b11000: Imprecise ECC Error -> address is
* unpredictable
* - 0b00010: Debug -> address is unchanged
* - bit [12]:
* - 0: AXI Decode Error (DECERR)
* - 1: AXI Slave Error (SLVERR)
*/
uint32 _coreGetInstructionFault_( void );
/** @fn void _coreClearInstructionFault_(void)
* @brief Clear core instruction fault status register
*/
void _coreClearInstructionFault_( void );
/** @fn uint32 _coreGetDataFaultAddress_(void)
* @brief Get core data fault address register
* @return The function will return the data fault address:
*/
uint32 _coreGetDataFaultAddress_( void );
/** @fn void _coreClearDataFaultAddress_(void)
* @brief Clear core data fault address register
*/
void _coreClearDataFaultAddress_( void );
/** @fn uint32 _coreGetInstructionFaultAddress_(void)
* @brief Get core instruction fault address register
* @return The function will return the instruction fault address:
*/
uint32 _coreGetInstructionFaultAddress_( void );
/** @fn void _coreClearInstructionFaultAddress_(void)
* @brief Clear core instruction fault address register
*/
void _coreClearInstructionFaultAddress_( void );
/** @fn uint32 _coreGetAuxiliaryDataFault_(void)
* @brief Get core auxiliary data fault status register
* @return The function will return the auxiliary data fault status register value:
* - bit [13..5]:
* - Index value for access giving error
* - bit [21]:
* - 0: Unrecoverable error
* - 1: Recoverable error
* - bit [23..22]:
* - 0: Side cache
* - 1: Side ATCM (Flash)
* - 2: Side BTCM (RAM)
* - 3: Reserved
* - bit [27..24]:
* - Cache way or way in which error occurred
*/
uint32 _coreGetAuxiliaryDataFault_( void );
/** @fn void _coreClearAuxiliaryDataFault_(void)
* @brief Clear core auxiliary data fault status register
*/
void _coreClearAuxiliaryDataFault_( void );
/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void)
* @brief Get core auxiliary instruction fault status register
* @return The function will return the auxiliary instruction fault status register
* value:
* - bit [13..5]:
* - Index value for access giving error
* - bit [21]:
* - 0: Unrecoverable error
* - 1: Recoverable error
* - bit [23..22]:
* - 0: Side cache
* - 1: Side ATCM (Flash)
* - 2: Side BTCM (RAM)
* - 3: Reserved
* - bit [27..24]:
* - Cache way or way in which error occurred
*/
uint32 _coreGetAuxiliaryInstructionFault_( void );
/** @fn void _coreClearAuxiliaryInstructionFault_(void)
* @brief Clear core auxiliary instruction fault status register
*/
void _coreClearAuxiliaryInstructionFault_( void );
/** @fn void _disable_IRQ_interrupt_(void)
* @brief Disable IRQ Interrupt mode in CPSR register
*
* This function disables IRQ Interrupt mode in CPSR register.
*/
void _disable_IRQ_interrupt_( void );
/** @fn void _enable_IRQ_interrupt_(void)
* @brief Enable IRQ Interrupt mode in CPSR register
*
* This function enables IRQ Interrupt mode in CPSR register.
*/
void _enable_IRQ_interrupt_( void );
/** @fn void _enable_interrupt_(void)
* @brief Enable IRQ and FIQ Interrupt mode in CPSR register
*
* This function Enables IRQ and FIQ Interrupt mode in CPSR register.
* User must call this function to enable Interrupts in non-OS environments.
*/
void _enable_interrupt_( void );
/** @fn void _esmCcmErrorsClear_(void)
* @brief Clears ESM Error caused due to CCM Errata in RevA Silicon
*
* This function Clears ESM Error caused due to CCM Errata
* in RevA Silicon immediately after powerup.
*/
void _esmCcmErrorsClear_( void );
/** @fn void _memInit_(void)
* @brief Initialize RAM
*/
void _memInit_( void );
/** @fn void _cacheEnable_(void)
* @brief Initialize RAM
*/
void _cacheEnable_( void );
/** @fn void _cacheDisable_(void)
* @brief Enable Cache
*/
void _cacheDisable_( void );
/** @fn void _dCacheInvalidate_(void)
* @brief Invalidate DCache.
*/
void _dCacheInvalidate_( void );
/** @fn void _iCacheInvalidate_(void)
* @brief Invalidate ICache.
*/
void _iCacheInvalidate_( void );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file sys_dma.h
* @brief DMA Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the DMA driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef DMA_H_
#define DMA_H_
#include "reg_dma.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
typedef enum dmaChannel
{
DMA_CH0 = 0U,
DMA_CH1,
DMA_CH2,
DMA_CH3,
DMA_CH4,
DMA_CH5,
DMA_CH6,
DMA_CH7,
DMA_CH8,
DMA_CH9,
DMA_CH10,
DMA_CH11,
DMA_CH12,
DMA_CH13,
DMA_CH14,
DMA_CH15,
DMA_CH16,
DMA_CH17,
DMA_CH18,
DMA_CH19,
DMA_CH20,
DMA_CH21,
DMA_CH22,
DMA_CH23,
DMA_CH24,
DMA_CH25,
DMA_CH26,
DMA_CH27,
DMA_CH28,
DMA_CH29,
DMA_CH30,
DMA_CH31
} dmaChannel_t;
typedef enum dmaRequest
{
DMA_REQ0 = 0U,
DMA_REQ1,
DMA_REQ2,
DMA_REQ3,
DMA_REQ4,
DMA_REQ5,
DMA_REQ6,
DMA_REQ7,
DMA_REQ8,
DMA_REQ9,
DMA_REQ10,
DMA_REQ11,
DMA_REQ12,
DMA_REQ13,
DMA_REQ14,
DMA_REQ15,
DMA_REQ16,
DMA_REQ17,
DMA_REQ18,
DMA_REQ19,
DMA_REQ20,
DMA_REQ21,
DMA_REQ22,
DMA_REQ23,
DMA_REQ24,
DMA_REQ25,
DMA_REQ26,
DMA_REQ27,
DMA_REQ28,
DMA_REQ29,
DMA_REQ30,
DMA_REQ31,
DMA_REQ32,
DMA_REQ33,
DMA_REQ34,
DMA_REQ35,
DMA_REQ36,
DMA_REQ37,
DMA_REQ38,
DMA_REQ39,
DMA_REQ40,
DMA_REQ41,
DMA_REQ42,
DMA_REQ43,
DMA_REQ44,
DMA_REQ45,
DMA_REQ46,
DMA_REQ47
} dmaRequest_t;
typedef enum dmaTriggerType
{
DMA_HW,
DMA_SW
} dmaTriggerType_t;
typedef enum dmaPriorityQueue
{
LOWPRIORITY,
HIGHPRIORITY
} dmaPriorityQueue_t;
typedef enum dmaInterrupt
{
FTC, /**< Frame transfer complete Interrupt */
LFS, /**< Last frame transfer started Interrupt */
HBC, /**< First half of block complete Interrupt */
BTC /**< Block transfer complete Interrupt */
} dmaInterrupt_t;
typedef enum dmaIntGroup
{
DMA_INTA = 0U, /**< Group A Interrupt */
DMA_INTB = 1U /**< Group B Interrupt (Reserved for Lock-step devices) */
} dmaIntGroup_t;
typedef enum dmaMPURegion
{
DMA_REGION0 = 0U,
DMA_REGION1 = 1U,
DMA_REGION2 = 2U,
DMA_REGION3 = 3U,
DMA_REGION4 = 4U,
DMA_REGION5 = 5U,
DMA_REGION6 = 6U,
DMA_REGION7 = 7U
} dmaMPURegion_t;
typedef enum dmaRegionAccess
{
FULLACCESS = 0U,
READONLY = 1U,
WRITEONLY = 2U,
NOACCESS = 3U
} dmaRegionAccess_t;
typedef enum dmaMPUInt
{
INTERRUPT_DISABLE = 0U,
INTERRUPTA_ENABLE = 1U,
INTERRUPTB_ENABLE = 3U
} dmaMPUInt_t;
enum dmaPort
{
PORTB_READ_PORTB_WRITE = 0x3U,
PORTA_READ_PORTA_WRITE = 0x2U,
PORTA_READ_PORTB_WRITE = 0x1U,
PORTB_READ_PORTA_WRITE = 0x0U
};
enum dmaElementSize
{
ACCESS_8_BIT = 0U,
ACCESS_16_BIT = 1U,
ACCESS_32_BIT = 2U,
ACCESS_64_BIT = 3U
};
enum dmaTransferType
{
FRAME_TRANSFER = 0U,
BLOCK_TRANSFER = 1U
};
enum dmaAddressMode
{
ADDR_FIXED = 0U,
ADDR_INC1 = 1U,
ADDR_OFFSET = 3U
};
enum dmaAutoInitMode
{
AUTOINIT_OFF = 0U,
AUTOINIT_ON = 1U
};
typedef struct dmaCTRLPKT
{
uint32 SADD; /* Initial source address */
uint32 DADD; /* Initial destination address */
uint32 CHCTRL; /* Next channel to be triggered + 1 */
uint32 FRCNT; /* Frame count */
uint32 ELCNT; /* Element count */
uint32 ELDOFFSET; /* Element destination offset */
uint32 ELSOFFSET; /* Element source offset */
uint32 FRDOFFSET; /* Frame destination offset */
uint32 FRSOFFSET; /* Frame source offset */
uint32 PORTASGN; /* DMA port */
uint32 RDSIZE; /* Read element size */
uint32 WRSIZE; /* Write element size */
uint32 TTYPE; /* Trigger type - frame/block */
uint32 ADDMODERD; /* Addressing mode for source */
uint32 ADDMODEWR; /* Addressing mode for destination */
uint32 AUTOINIT; /* Auto-init mode */
} g_dmaCTRL;
void dmaEnable( void );
void dmaDisable( void );
void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT );
void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type );
void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline );
void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority );
void dmaEnableInterrupt( dmaChannel_t channel,
dmaInterrupt_t inttype,
dmaIntGroup_t group );
void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype );
void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add );
void dmaEnableRegion( dmaMPURegion_t region,
dmaRegionAccess_t access,
dmaMPUInt_t intenable );
void dmaDisableRegion( dmaMPURegion_t region );
void dmaEnableECC( void );
void dmaDisableECC( void );
uint32 dmaGetReq( dmaChannel_t channel );
boolean dmaIsBusy( void );
boolean dmaIsChannelActive( dmaChannel_t channel );
boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype );
/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
* @brief Interrupt callback
* @param[in] inttype Interrupt type
* - FTC
* - LFS
* - HBC
* - BTC
* @param[in] channel channel number 0..15
* This is a callback that is provided by the application and is called apon
* an interrupt. The parameter passed to the callback is a copy of the
* interrupt flag register.
*/
void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel );
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif /* DMA_H_ */

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/** @file sys_mpu.h
* @brief System Mpu Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Mpu Interface Functions
* .
* which are relevant for the memory protection unit driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_MPU_H__
#define __SYS_MPU_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @def mpuREGION1
* @brief Mpu region 1
*
* Alias for Mpu region 1
*/
#define mpuREGION1 0U
/** @def mpuREGION2
* @brief Mpu region 2
*
* Alias for Mpu region 1
*/
#define mpuREGION2 1U
/** @def mpuREGION3
* @brief Mpu region 3
*
* Alias for Mpu region 3
*/
#define mpuREGION3 2U
/** @def mpuREGION4
* @brief Mpu region 4
*
* Alias for Mpu region 4
*/
#define mpuREGION4 3U
/** @def mpuREGION5
* @brief Mpu region 5
*
* Alias for Mpu region 5
*/
#define mpuREGION5 4U
/** @def mpuREGION6
* @brief Mpu region 6
*
* Alias for Mpu region 6
*/
#define mpuREGION6 5U
/** @def mpuREGION7
* @brief Mpu region 7
*
* Alias for Mpu region 7
*/
#define mpuREGION7 6U
/** @def mpuREGION8
* @brief Mpu region 8
*
* Alias for Mpu region 8
*/
#define mpuREGION8 7U
/** @def mpuREGION9
* @brief Mpu region 9
*
* Alias for Mpu region 9
*/
#define mpuREGION9 8U
/** @def mpuREGION10
* @brief Mpu region 10
*
* Alias for Mpu region 10
*/
#define mpuREGION10 9U
/** @def mpuREGION11
* @brief Mpu region 11
*
* Alias for Mpu region 11
*/
#define mpuREGION11 10U
/** @def mpuREGION12
* @brief Mpu region 12
*
* Alias for Mpu region 12
*/
#define mpuREGION12 11U
/** @def mpuREGION13
* @brief Mpu region 13
*
* Alias for Mpu region 13
*/
#define mpuREGION13 12U
/** @def mpuREGION14
* @brief Mpu region 14
*
* Alias for Mpu region 14
*/
#define mpuREGION14 13U
/** @def mpuREGION15
* @brief Mpu region 15
*
* Alias for Mpu region 15
*/
#define mpuREGION15 14U
/** @def mpuREGION16
* @brief Mpu region 16
*
* Alias for Mpu region 16
*/
#define mpuREGION16 15U
/** @def mpuREGION_ENABLE
* @brief Enable MPU Region
*
* Alias for MPU region enable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuREGION_ENABLE 1U
/** @def mpuREGION_DISABLE
* @brief Disable MPU Region
*
* Alias for MPU region disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuREGION_DISABLE 0U
/** @def mpuSUBREGION0_DISABLE
* @brief Disable MPU Sub Region0
*
* Alias for MPU subregion0 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION0_DISABLE 0x100U
/** @def mpuSUBREGION1_DISABLE
* @brief Disable MPU Sub Region1
*
* Alias for MPU subregion1 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION1_DISABLE 0x200U
/** @def mpuSUBREGION2_DISABLE
* @brief Disable MPU Sub Region2
*
* Alias for MPU subregion2 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION2_DISABLE 0x400U
/** @def mpuSUBREGION3_DISABLE
* @brief Disable MPU Sub Region3
*
* Alias for MPU subregion3 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION3_DISABLE 0x800U
/** @def mpuSUBREGION4_DISABLE
* @brief Disable MPU Sub Region4
*
* Alias for MPU subregion4 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION4_DISABLE 0x1000U
/** @def mpuSUBREGION5_DISABLE
* @brief Disable MPU Sub Region5
*
* Alias for MPU subregion5 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION5_DISABLE 0x2000U
/** @def mpuSUBREGION6_DISABLE
* @brief Disable MPU Sub Region6
*
* Alias for MPU subregion6 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION6_DISABLE 0x4000U
/** @def mpuSUBREGION7_DISABLE
* @brief Disable MPU Sub Region7
*
* Alias for MPU subregion7 disable.
*
* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
*/
#define mpuSUBREGION7_DISABLE 0x8000U
/** @enum mpuRegionAccessPermission
* @brief Alias names for mpu region access permissions
*
* This enumeration is used to provide alias names for the mpu region access permission:
* - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and
* execute
* - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode
* and execute
* - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode
* and execute
* - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode
* and execute
* - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and
* execute
* - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and
* execute
* - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode
* and no execution
* - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode
* and no execution
* - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode
* and no execution
* - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode
* and no execution
* - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode
* and no execution
* - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode
* and no execution
*
*/
enum mpuRegionAccessPermission
{
MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access
in user mode and execute */
MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias no read/write in privileged mode, no
access in user mode and execute */
MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias no read/write in privileged mode, read
only in user mode and execute */
MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias no read/write in privileged mode,
read/write in user mode and execute */
MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias no read only in privileged mode, no
access in user mode and execute */
MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias no read only in privileged mode, read
only in user mode and execute */
MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no
access in user mode and no execution */
MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no
access in user mode and no execution */
MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode,
read only in user mode and no execution */
MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode,
read/write in user mode and no execution */
MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no
access in user mode and no execution */
MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias no read only in privileged mode, read
only in user mode and no execution */
};
/** @enum mpuRegionType
* @brief Alias names for mpu region type
*
* This enumeration is used to provide alias names for the mpu region type:
* - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
* - MPU_DEVICE_SHAREABLE Memory type device and sharable
* - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through,
* no write allocate and non shared
* - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through,
* no write allocate and shared
* - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no
* write allocate and non shared
* - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no
* write allocate and shared
* - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cacheable
* and non shared
* - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cacheable
* and shared
* - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back,
* write allocate and non shared
* - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back,
* write allocate and shared
* - MPU_DEVICE_NONSHAREABLE Memory type device and non sharable
*/
enum mpuRegionType
{
MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and
sharable */
MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */
MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner
write-through, no write allocate and non
shared */
MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner
write-back, no write allocate and non
shared */
MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner
write-through, no write allocate and shared
*/
MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner
write-back, no write allocate and shared */
MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner
non-cacheable and non shared */
MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner
write-back, write allocate and non shared */
MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner
non-cacheable and shared */
MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner
write-back, write allocate and shared */
MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */
};
/** @enum mpuRegionSize
* @brief Alias names for mpu region type
*
* This enumeration is used to provide alias names for the mpu region type:
* - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
* - MPU_32_BYTES Memory size in bytes
* - MPU_64_BYTES Memory size in bytes
* - MPU_128_BYTES Memory size in bytes
* - MPU_256_BYTES Memory size in bytes
* - MPU_512_BYTES Memory size in bytes
* - MPU_1_KB Memory size in kB
* - MPU_2_KB Memory size in kB
* - MPU_4_KB Memory size in kB
* - MPU_8_KB Memory size in kB
* - MPU_16_KB Memory size in kB
* - MPU_32_KB Memory size in kB
* - MPU_64_KB Memory size in kB
* - MPU_128_KB Memory size in kB
* - MPU_256_KB Memory size in kB
* - MPU_512_KB Memory size in kB
* - MPU_1_MB Memory size in MB
* - MPU_2_MB Memory size in MB
* - MPU_4_MB Memory size in MB
* - MPU_8_MBv Memory size in MB
* - MPU_16_MB Memory size in MB
* - MPU_32_MB Memory size in MB
* - MPU_64_MB Memory size in MB
* - MPU_128_MB Memory size in MB
* - MPU_256_MB Memory size in MB
* - MPU_512_MB Memory size in MB
* - MPU_1_GB Memory size in GB
* - MPU_2_GB Memory size in GB
* - MPU_4_GB Memory size in GB
*/
enum mpuRegionSize
{
MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */
MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */
MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */
MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */
MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */
MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */
MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */
MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */
MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */
MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */
MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */
MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */
MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */
MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */
MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */
MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */
MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */
MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */
MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */
MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */
MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */
MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */
MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */
MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */
MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */
MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */
MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */
MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */
};
/** @fn void _mpuInit_(void)
* @brief Initialize Mpu
*
* This function initializes memory protection unit.
*/
void _mpuInit_( void );
/** @fn void _mpuEnable_(void)
* @brief Enable Mpu
*
* This function enables memory protection unit.
*/
void _mpuEnable_( void );
/** @fn void _mpuDisable_(void)
* @brief Disable Mpu
*
* This function disables memory protection unit.
*/
void _mpuDisable_( void );
/** @fn void _mpuEnableBackgroundRegion_(void)
* @brief Enable Mpu background region
*
* This function enables background region of the memory protection unit.
*/
void _mpuEnableBackgroundRegion_( void );
/** @fn void _mpuDisableBackgroundRegion_(void)
* @brief Disable Mpu background region
*
* This function disables background region of the memory protection unit.
*/
void _mpuDisableBackgroundRegion_( void );
/** @fn uint32 _mpuGetNumberOfRegions_(void)
* @brief Returns number of implemented Mpu regions
* @return Number of implemented mpu regions
*
* This function returns the number of implemented mpu regions.
*/
uint32 _mpuGetNumberOfRegions_( void );
/** @fn uint32 _mpuAreRegionsSeparate_(void)
* @brief Returns the type of the implemented mpu regions
* @return Mpu type of regions
*
* This function returns 0 when mpu regions are of type unified otherwise regions are of
* type separate.
*/
uint32 _mpuAreRegionsSeparate_( void );
/** @fn void _mpuSetRegion_(uint32 region)
* @brief Set mpu region number
* @param[in] region Region number: mpuREGION1..mpuREGION12
*
* This function selects one of the implemented mpu regions.
*/
void _mpuSetRegion_( uint32 region );
/** @fn uint32 _mpuGetRegion_(void)
* @brief Returns the currently selected mpu region
* @return Mpu region number
*
* This function returns currently selected mpu region number.
*/
uint32 _mpuGetRegion_( void );
/** @fn void _mpuSetRegionBaseAddress_(uint32 address)
* @brief Set base address of currently selected mpu region
* @param[in] address Base address of the MPU region
* @note The base address must always aligned with region size
*
* This function sets the base address of currently selected mpu region.
*/
void _mpuSetRegionBaseAddress_( uint32 address );
/** @fn uint32 _mpuGetRegionBaseAddress_(void)
* @brief Returns base address of currently selected mpu region
* @return Current base address of selected mpu region
*
* This function returns the base address of currently selected mpu region.
*/
uint32 _mpuGetRegionBaseAddress_( void );
/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission)
* @brief Set type of currently selected mpu region
* @param[in] type Region Type
* - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and
* sharable
* - MPU_DEVICE_SHAREABLE : Memory type device and sharable
* - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and
* inner write-through, no write allocate and non shared
* - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and
* inner write-back, no write allocate and non shared
* - MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and
* inner write-through, no write allocate and shared
* - MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and
* inner write-back, no write allocate and shared
* - MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and
* inner non-cacheable and non shared
* - MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and
* inner write-back, write allocate and non shared
* - MPU_NORMAL_OINC_SHARED : Memory type normal outer and
* inner non-cacheable and shared
* - MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and
* inner write-back, write allocate and shared
* - MPU_DEVICE_NONSHAREABLE : Memory type device and non
* sharable
*
* @param[in] permission Region Access permission
* - MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged
* mode, no access in user mode and execute
* - MPU_PRIV_RW_USER_NA_EXEC : Alias no read/write in
* privileged mode, no access in user mode and execute
* - MPU_PRIV_RW_USER_RO_EXEC : Alias no read/write in
* privileged mode, read only in user mode and execute
* - MPU_PRIV_RW_USER_RW_EXEC : Alias no read/write in
* privileged mode, read/write in user mode and execute
* - MPU_PRIV_RO_USER_NA_EXEC : Alias no read only in
* privileged mode, no access in user mode and execute
* - MPU_PRIV_RO_USER_RO_EXEC : Alias no read only in
* privileged mode, read only in user mode and execute
* - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged
* mode, no access in user mode and no execution
* - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in
* privileged mode, no access in user mode and no execution
* - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in
* privileged mode, read only in user mode and no execution
* - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in
* privileged mode, read/write in user mode and no execution
* - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in
* privileged mode, no access in user mode and no execution
* - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in
* privileged mode, read only in user mode and no execution
*
* This function sets the type of currently selected mpu region.
*/
void _mpuSetRegionTypeAndPermission_( uint32 type, uint32 permission );
/** @fn uint32 _mpuGetRegionType_(void)
* @brief Returns the type of currently selected mpu region
* @return Current type of selected mpu region
*
* This function returns the type of currently selected mpu region.
*/
uint32 _mpuGetRegionType_( void );
/** @fn uint32 _mpuGetRegionPermission_(void)
* @brief Returns permission of currently selected mpu region
* @return Current type of selected mpu region
*
* This function returns permission of currently selected mpu region.
*/
uint32 _mpuGetRegionPermission_( void );
/** @fn void _mpuSetRegionSizeRegister_(uint32 value)
* @brief Set mpu region size register value
* @param[in] value Value to be written in the MPU Region Size and Enable register
*
* This function sets mpu region size register value.
*
* Sample usuage:
* _mpuSetRegion_(mpuREGION5);
* _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE |
* mpuSUBREGION4_DISABLE);
*/
void _mpuSetRegionSizeRegister_( uint32 value );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @file pcr.h
* @brief PCR Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* - Interface Prototypes
* .
* which are relevant for the PCR driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef PCR_H_
#define PCR_H_
#include "reg_pcr.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
#define QUADRANT0 1U
#define QUADRANT1 2U
#define QUADRANT2 4U
#define QUADRANT3 8U
typedef enum
{
PS0 = 0U,
PS1,
PS2,
PS3,
PS4,
PS5,
PS6,
PS7,
PS8,
PS9,
PS10,
PS11,
PS12,
PS13,
PS14,
PS15,
PS16,
PS17,
PS18,
PS19,
PS20,
PS21,
PS22,
PS23,
PS24,
PS25,
PS26,
PS27,
PS28,
PS29,
PS30,
PS31
} peripheral_Frame_t;
typedef enum
{
PPS0 = 0U,
PPS1,
PPS2,
PPS3,
PPS4,
PPS5,
PPS6,
PPS7
} privileged_Peripheral_Frame_t;
typedef enum
{
PPSE0 = 0U,
PPSE1,
PPSE2,
PPSE3,
PPSE4,
PPSE5,
PPSE6,
PPSE7,
PPSE8,
PPSE9,
PPSE10,
PPSE11,
PPSE12,
PPSE13,
PPSE14,
PPSE15,
PPSE16,
PPSE17,
PPSE18,
PPSE19,
PPSE20,
PPSE21,
PPSE22,
PPSE23,
PPSE24,
PPSE25,
PPSE26,
PPSE27,
PPSE28,
PPSE29,
PPSE30,
PPSE31
} privileged_Peripheral_Extended_Frame_t;
typedef enum
{
PCS0 = 0U,
PCS1,
PCS2,
PCS3,
PCS4,
PCS5,
PCS6,
PCS7,
PCS8,
PCS9,
PCS10,
PCS11,
PCS12,
PCS13,
PCS14,
PCS15,
PCS16,
PCS17,
PCS18,
PCS19,
PCS20,
PCS21,
PCS22,
PCS23,
PCS24,
PCS25,
PCS26,
PCS27,
PCS28,
PCS29,
PCS30,
PCS31,
PCS32,
PCS33,
PCS34,
PCS35,
PCS36,
PCS37,
PCS38,
PCS39,
PCS40,
PCS41,
PCS42,
PCS43,
PCS44,
PCS45,
PCS46,
PCS47,
PCS48,
PCS49,
PCS50,
PCS51,
PCS52,
PCS53,
PCS54,
PCS55,
PCS56,
PCS57,
PCS58,
PCS59,
PCS60,
PCS61,
PCS62,
PCS63
} peripheral_Memory_t;
typedef enum
{
PPCS0 = 0U,
PPCS1,
PPCS2,
PPCS3,
PPCS4,
PPCS5,
PPCS6,
PPCS7,
PPCS8,
PPCS9,
PPCS10,
PPCS11,
PPCS12,
PPCS13,
PPCS14,
PPCS15
} privileged_Peripheral_Memory_t;
typedef enum
{
Master_CPU0 = 0U,
Master_CPU1 = 1U, /* Reserved for Lock-Step device */
Master_DMA = 2U,
Master_HTU1 = 3U,
Master_HTU2 = 4U,
Master_FTU = 5U,
Master_DMM = 7U,
Master_DAP = 9U,
Master_EMAC = 10U
} master_ID_t;
/**
* @defgroup PCR PCR
* @brief PPeripheral Central Resource Module
*
* Related files:
* - reg_pcr.h
* - sys_pcr.h
* - sys_pcr.c
*
* @addtogroup PCR
* @{
*/
void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS );
void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS );
void peripheral_Frame_Protection_Set( pcrBASE_t * pcr,
peripheral_Frame_t PS,
uint32 quadrant );
void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr,
peripheral_Frame_t PS,
uint32 quadrant );
void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS );
void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS );
void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr,
peripheral_Frame_t PS,
uint32 quadrant );
void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr,
peripheral_Frame_t PS,
uint32 quadrant );
void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr,
peripheral_Frame_t PS,
uint32 quadrant,
master_ID_t master );
void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr,
peripheral_Frame_t PS,
uint32 quadrant,
master_ID_t master );
void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr,
privileged_Peripheral_Frame_t PPS,
uint32 quadrant,
master_ID_t master );
void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr,
privileged_Peripheral_Frame_t PPS,
uint32 quadrant,
master_ID_t master );
void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable(
pcrBASE_t * pcr,
privileged_Peripheral_Extended_Frame_t PPSE,
uint32 quadrant,
master_ID_t master );
void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable(
pcrBASE_t * pcr,
privileged_Peripheral_Extended_Frame_t PPSE,
uint32 quadrant,
master_ID_t master );
void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr,
peripheral_Memory_t PCS,
master_ID_t master );
void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr,
peripheral_Memory_t PCS,
master_ID_t master );
void privileged_Peripheral_Memory_MasterIDFilter_Disable(
pcrBASE_t * pcr,
privileged_Peripheral_Memory_t PPCS,
master_ID_t master );
void privileged_Peripheral_Memory_MasterIDFilter_Enable(
pcrBASE_t * pcr,
privileged_Peripheral_Memory_t PPCS,
master_ID_t master );
void pcrEnableMasterIDCheck( pcrBASE_t * pcr );
void pcrDisableMasterIDCheck( pcrBASE_t * pcr );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#endif /* PCR_H_ */

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/** @file sys_pmm.h
* @brief PMM Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_PMM_H__
#define __SYS_PMM_H__
#include "reg_pmm.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @enum pmmLogicPDTag
* @brief PMM Logic Power Domain
*
* Used to define PMM Logic Power Domain
*/
typedef enum pmmLogicPDTag
{
PMM_LOGICPD1 = 5U, /*-- NOT USED*/
PMM_LOGICPD2 = 0U,
PMM_LOGICPD3 = 1U,
PMM_LOGICPD4 = 2U,
PMM_LOGICPD5 = 3U,
PMM_LOGICPD6 = 4U
} pmm_LogicPD_t;
/** @enum pmmModeTag
* @brief PSCON operating mode
*
* Used to define the operating mode of PSCON Compare Block
*/
typedef enum pmmModeTag
{
LockStep = 0x0U,
SelfTest = 0x6U,
ErrorForcing = 0x9U,
SelfTestErrorForcing = 0xFU
} pmm_Mode_t;
/**
* @defgroup PMM PMM
* @brief Power Management Module
*
* The PMM provides memory-mapped registers that control the states of the supported power
* domains. The PMM includes interfaces to the Power Mode Controller (PMC) and the Power
* State Controller (PSCON). The PMC and PSCON control the power up/down sequence of each
* power domain.
*
* Related files:
* - reg_pmm.h
* - sys_pmm.h
* - sys_pmm.c
*
* @addtogroup PMM
* @{
*/
/* Pmm Interface Functions */
boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD );
boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD );
boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD );
/**@}*/
/* USER CODE BEGIN (1) */
/* USER CODE END */
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file sys_pmu.h
* @brief System Pmu Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Pmu Interface Functions
* .
* which are relevant for the performance monitor unit driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_PMU_H__
#define __SYS_PMU_H__
#include "sys_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/** @def pmuCOUNTER0
* @brief pmu event counter 0
*
* Alias for pmu event counter 0
*/
#define pmuCOUNTER0 0x00000001U
/** @def pmuCOUNTER1
* @brief pmu event counter 1
*
* Alias for pmu event counter 1
*/
#define pmuCOUNTER1 0x00000002U
/** @def pmuCOUNTER2
* @brief pmu event counter 2
*
* Alias for pmu event counter 2
*/
#define pmuCOUNTER2 0x00000004U
/** @def pmuCYCLE_COUNTER
* @brief pmu cycle counter
*
* Alias for pmu event counter
*/
#define pmuCYCLE_COUNTER 0x80000000U
/** @enum pmuEvent
* @brief pmu event
*
* Alias for pmu event counter increment source
*/
enum pmuEvent
{
PMU_INST_CACHE_MISS = 0x01U,
PMU_DATA_CACHE_MISS = 0x03U,
PMU_DATA_CACHE_ACCESS = 0x04U,
PMU_DATA_READ_ARCH_EXECUTED = 0x06U,
PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U,
PMU_INST_ARCH_EXECUTED = 0x08U,
PMU_EXCEPTION_TAKEN = 0x09U,
PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU,
PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU,
PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU,
PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU,
PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU,
PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU,
PMU_BRANCH_MISSPREDICTED = 0x10U,
PMU_CYCLE_COUNT = 0x11U,
PMU_PREDICTABLE_BRANCHES = 0x12U,
PMU_INST_BUFFER_STALL = 0x40U,
PMU_DATA_DEPENDENCY_INST_STALL = 0x41U,
PMU_DATA_CACHE_WRITE_BACK = 0x42U,
PMU_EXT_MEMORY_REQUEST = 0x43U,
PMU_LSU_BUSY_STALL = 0x44U,
PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U,
PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U,
PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U,
PMU_ETMEXTOUT_0 = 0x48U,
PMU_ETMEXTOUT_1 = 0x49U,
PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU,
PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU,
PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU,
PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU,
PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU,
PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU,
PMU_STORE_BUFFER_MERGE = 0x50U,
PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U,
PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U,
PMU_INTEGER_DIV_EXECUTED = 0x53U,
PMU_STALL_INTEGER_DIV = 0x54U,
PMU_PLD_INST_LINE_FILL = 0x55U,
PMU_PLD_INST_NO_LINE_FILL = 0x56U,
PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U,
PMU_INST_CACHE_ACCESS = 0x58U,
PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U,
PMU_DUAL_ISSUE_CASE_A = 0x5AU,
PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU,
PMU_DUAL_ISSUE_OTHER = 0x5CU,
PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU,
PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU,
PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U,
PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U,
PMU_PROCESSOR_LIVE_LOCK = 0x62U,
PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U,
PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U,
PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U,
PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U,
PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U,
PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U,
PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU,
PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU,
PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU,
PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU,
PMU_ALL_CORRECTABLE_EVENTS = 0x6EU,
PMU_ALL_FATAL_EVENTS = 0x6FU,
PMU_ALL_CORRECTABLE_FAULTS = 0x70U,
PMU_ALL_FATAL_FAULTS = 0x71U,
PMU_ACP_DCACHE_ACCESS_LOOKUP_INVALIDATE = 0x72U,
PMU_ACP_DCACHE_INVALIDATE = 0x73U
};
/** @fn void _pmuInit_(void)
* @brief Initialize Performance Monitor Unit
*/
void _pmuInit_( void );
/** @fn void _pmuEnableCountersGlobal_(void)
* @brief Enable and reset cycle counter and all 3 event counters
*/
void _pmuEnableCountersGlobal_( void );
/** @fn void _pmuDisableCountersGlobal_(void)
* @brief Disable cycle counter and all 3 event counters
*/
void _pmuDisableCountersGlobal_( void );
/** @fn void _pmuResetCycleCounter_(void)
* @brief Reset cycle counter
*/
void _pmuResetCycleCounter_( void );
/** @fn void _pmuResetEventCounters_(void)
* @brief Reset event counters 0-2
*/
void _pmuResetEventCounters_( void );
/** @fn void _pmuResetCounters_(void)
* @brief Reset cycle counter and event counters 0-2
*/
void _pmuResetCounters_( void );
/** @fn void _pmuStartCounters_(uint32 counters)
* @brief Starts selected counters
* @param[in] counters - Counter mask
*/
void _pmuStartCounters_( uint32 counters );
/** @fn void _pmuStopCounters_(uint32 counters)
* @brief Stops selected counters
* @param[in] counters - Counter mask
*/
void _pmuStopCounters_( uint32 counters );
/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event)
* @brief Set event counter count event
* @param[in] counter - Counter select 0..2
* @param[in] event - Count event
*/
void _pmuSetCountEvent_( uint32 counter, uint32 event );
/** @fn uint32 _pmuGetCycleCount_(void)
* @brief Returns current cycle counter value
*
* @return cycle count.
*/
uint32 _pmuGetCycleCount_( void );
/** @fn uint32 _pmuGetEventCount_(uint32 counter)
* @brief Returns current event counter value
* @param[in] counter - Counter select 0..2
*
* @return event counter count.
*/
uint32 _pmuGetEventCount_( uint32 counter );
/** @fn uint32 _pmuGetOverflow_(void)
* @brief Returns current overflow register and clear flags
*
* @return overflow flags.
*/
uint32 _pmuGetOverflow_( void );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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/** @file sys_vim.h
* @brief Vectored Interrupt Module Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - VIM Type Definitions
* - VIM General Definitions
* .
* which are relevant for Vectored Interrupt Controller.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_VIM_H__
#define __SYS_VIM_H__
#include "reg_vim.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* VIM Type Definitions */
/** @typedef t_isrFuncPTR
* @brief ISR Function Pointer Type Definition
*
* This type is used to access the ISR handler.
*/
typedef void ( *t_isrFuncPTR )( void );
/** @enum systemInterrupt
* @brief Alias names for clock sources
*
* This enumeration is used to provide alias names for the clock sources:
* - IRQ
* - FIQ
*/
typedef enum systemInterrupt
{
SYS_IRQ = 0U, /**< Alias for IRQ interrupt */
SYS_FIQ = 1U /**< Alias for FIQ interrupt */
} systemInterrupt_t;
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* VIM General Configuration */
#define VIM_CHANNELS 128U
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* Interrupt Handlers */
extern void custom_dabort( void );
extern void esmHighInterrupt( void ) __attribute__( ( weak, interrupt( "FIQ" ) ) );
extern void phantomInterrupt( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) );
extern void FreeRTOS_Tick_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) );
extern void vPortYieldWithinAPI( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) );
extern void FreeRTOS_IRQ_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) );
/* USER CODE BEGIN (3) */
/* USER CODE END */
#define VIM_ECCSTAT ( *( volatile uint32 * ) 0xFFFFFDECU )
#define VIM_ECCCTL ( *( volatile uint32 * ) 0xFFFFFDF0U )
#define VIM_UERRADDR ( *( volatile uint32 * ) 0xFFFFFDF4U )
#define VIM_FBVECADDR ( *( volatile uint32 * ) 0xFFFFFDF8U )
#define VIM_SBERRADDR ( *( volatile uint32 * ) 0xFFFFFDFCU )
#define VIMRAMECCLOC ( *( volatile uint32 * ) 0xFFF82400U )
#define VIMRAMLOC ( *( volatile uint32 * ) 0xFFF82000U )
/* Configuration registers */
typedef struct vim_config_reg
{
uint32 CONFIG_FIRQPR0;
uint32 CONFIG_FIRQPR1;
uint32 CONFIG_FIRQPR2;
uint32 CONFIG_FIRQPR3;
uint32 CONFIG_REQMASKSET0;
uint32 CONFIG_REQMASKSET1;
uint32 CONFIG_REQMASKSET2;
uint32 CONFIG_REQMASKSET3;
uint32 CONFIG_WAKEMASKSET0;
uint32 CONFIG_WAKEMASKSET1;
uint32 CONFIG_WAKEMASKSET2;
uint32 CONFIG_WAKEMASKSET3;
uint32 CONFIG_CAPEVT;
uint32 CONFIG_CHANCTRL[ 24U ];
} vim_config_reg_t;
/* Configuration registers initial value */
#define VIM_FIRQPR0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) )
#define VIM_FIRQPR1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) )
#define VIM_FIRQPR2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) )
#define VIM_FIRQPR3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \
| ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) )
#define VIM_REQMASKSET0_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \
| ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 1U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \
| ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) )
#define VIM_REQMASKSET1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \
| ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) )
#define VIM_REQMASKSET2_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \
| ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) )
#define VIM_REQMASKSET3_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \
| ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \
| ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \
| ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \
| ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \
| ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \
| ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \
| ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \
| ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \
| ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \
| ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \
| ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) )
#define VIM_WAKEMASKSET0_CONFIGVALUE 0xFFFFFFFFU
#define VIM_WAKEMASKSET1_CONFIGVALUE 0xFFFFFFFFU
#define VIM_WAKEMASKSET2_CONFIGVALUE 0xFFFFFFFFU
#define VIM_WAKEMASKSET3_CONFIGVALUE 0xFFFFFFFFU
#define VIM_CAPEVT_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) )
#define VIM_CHANCTRL0_CONFIGVALUE 0x00010203U
#define VIM_CHANCTRL1_CONFIGVALUE 0x04050607U
#define VIM_CHANCTRL2_CONFIGVALUE 0x08090A0BU
#define VIM_CHANCTRL3_CONFIGVALUE 0x0C0D0E0FU
#define VIM_CHANCTRL4_CONFIGVALUE 0x10111213U
#define VIM_CHANCTRL5_CONFIGVALUE 0x14151617U
#define VIM_CHANCTRL6_CONFIGVALUE 0x18191A1BU
#define VIM_CHANCTRL7_CONFIGVALUE 0x1C1D1E1FU
#define VIM_CHANCTRL8_CONFIGVALUE 0x20212223U
#define VIM_CHANCTRL9_CONFIGVALUE 0x24252627U
#define VIM_CHANCTRL10_CONFIGVALUE 0x28292A2BU
#define VIM_CHANCTRL11_CONFIGVALUE 0x2C2D2E2FU
#define VIM_CHANCTRL12_CONFIGVALUE 0x30313233U
#define VIM_CHANCTRL13_CONFIGVALUE 0x34353637U
#define VIM_CHANCTRL14_CONFIGVALUE 0x38393A3BU
#define VIM_CHANCTRL15_CONFIGVALUE 0x3C3D3E3FU
#define VIM_CHANCTRL16_CONFIGVALUE 0x40414243U
#define VIM_CHANCTRL17_CONFIGVALUE 0x44454647U
#define VIM_CHANCTRL18_CONFIGVALUE 0x48494A4BU
#define VIM_CHANCTRL19_CONFIGVALUE 0x4C4D4E4FU
#define VIM_CHANCTRL20_CONFIGVALUE 0x50515253U
#define VIM_CHANCTRL21_CONFIGVALUE 0x54555657U
#define VIM_CHANCTRL22_CONFIGVALUE 0x58595A5BU
#define VIM_CHANCTRL23_CONFIGVALUE 0x5C5D5E5FU
/**
* @defgroup VIM VIM
* @brief Vectored Interrupt Manager
*
* The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and
* controlling the many interrupt sources present on a device. Interrupts are caused by
* events outside of the normal flow of program execution.
*
* Related files:
* - reg_vim.h
* - sys_vim.h
* - sys_vim.c
*
* @addtogroup VIM
* @{
*/
/*VIM Interface functions*/
void vimInit( void );
void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler );
void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype );
void vimDisableInterrupt( uint32 channel );
void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type );
/*@}*/
#endif

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/** @file system.h
* @brief System Driver Header File
* @date 11-Dec-2018
* @version 04.07.01
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __SYS_SYSTEM_H__
#define __SYS_SYSTEM_H__
#include "reg_system.h"
#include "reg_flash.h"
#include "reg_l2ramw.h"
#include "reg_ccmr5.h"
#include "sys_core.h"
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* System General Definitions */
/** @enum systemClockSource
* @brief Alias names for clock sources
*
* This enumeration is used to provide alias names for the clock sources:
* - Oscillator
* - Pll1
* - External1
* - Low Power Oscillator Low
* - Low Power Oscillator High
* - PLL2
* - External2
* - Synchronous VCLK1
*/
enum systemClockSource
{
SYS_OSC = 0x0U, /**< Alias for oscillator clock Source */
SYS_PLL1 = 0x1U, /**< Alias for Pll1 clock Source */
SYS_EXTERNAL1 = 0x3U, /**< Alias for external clock Source */
SYS_LPO_LOW = 0x4U, /**< Alias for low power oscillator low clock Source */
SYS_LPO_HIGH = 0x5U, /**< Alias for low power oscillator high clock Source */
SYS_PLL2 = 0x6U, /**< Alias for Pll2 clock Source */
SYS_EXTERNAL2 = 0x7U, /**< Alias for external 2 clock Source */
SYS_VCLK = 0x9U, /**< Alias for synchronous VCLK1 clock Source */
SYS_PLL2_ODCLK_8 = 0xEU, /**< Alias for PLL2_post_ODCLK/8 */
SYS_PLL2_ODCLK_16 = 0xFU /**< Alias for PLL2_post_ODCLK/8 */
};
/** @enum resetSource
* @brief Alias names for reset sources
*
* This enumeration is used to provide alias names for the reset sources:
* - Power On Reset
* - Osc Failure Reset
* - Watch Dog Reset
* - Icepick Reset
* - CPU Reset
* - Software Reset
* - External Reset
*
*/
typedef enum
{
POWERON_RESET = 0x8000U, /**< Alias for Power On Reset */
OSC_FAILURE_RESET = 0x4000U, /**< Alias for Osc Failure Reset */
WATCHDOG_RESET = 0x2000U, /**< Alias for Watch Dog Reset */
WATCHDOG2_RESET = 0x1000U, /**< Alias for Watch Dog 2 Reset */
DEBUG_RESET = 0x0800U, /**< Alias for Debug Reset */
INTERCONNECT_RESET = 0x0080U, /**< Alias for Interconnect Reset */
CPU0_RESET = 0x0020U, /**< Alias for CPU 0 Reset */
SW_RESET = 0x0010U, /**< Alias for Software Reset */
EXT_RESET = 0x0008U, /**< Alias for External Reset */
NO_RESET = 0x0000U /**< Alias for No Reset */
} resetSource_t;
#define SYS_DOZE_MODE 0x000F3F02U
#define SYS_SNOOZE_MODE 0x000F3F03U
#define SYS_SLEEP_MODE 0x000FFFFFU
#define LPO_TRIM_VALUE ( ( ( *( volatile uint32 * ) 0xF00801B4U ) & 0xFFFF0000U ) >> 16U )
#define SYS_EXCEPTION ( *( volatile uint32 * ) 0xFFFFFFE4U )
#define WATCHDOG_STATUS ( *( volatile uint32 * ) 0xFFFFFC98U )
#define DEVICE_ID_REV ( *( volatile uint32 * ) 0xFFFFFFF0U )
/** @def OSC_FREQ
* @brief Oscillator clock source exported from HALCoGen GUI
*
* Oscillator clock source exported from HALCoGen GUI
*/
#define OSC_FREQ 16.0F
/** @def PLL1_FREQ
* @brief PLL 1 clock source exported from HALCoGen GUI
*
* PLL 1 clock source exported from HALCoGen GUI
*/
#define PLL1_FREQ 300.00F
/** @def LPO_LF_FREQ
* @brief LPO Low Freq Oscillator source exported from HALCoGen GUI
*
* LPO Low Freq Oscillator source exported from HALCoGen GUI
*/
#define LPO_LF_FREQ 0.080F
/** @def LPO_HF_FREQ
* @brief LPO High Freq Oscillator source exported from HALCoGen GUI
*
* LPO High Freq Oscillator source exported from HALCoGen GUI
*/
#define LPO_HF_FREQ 10.000F
/** @def PLL1_FREQ
* @brief PLL 2 clock source exported from HALCoGen GUI
*
* PLL 2 clock source exported from HALCoGen GUI
*/
#define PLL2_FREQ 300.00F
/** @def GCLK_FREQ
* @brief GCLK domain frequency exported from HALCoGen GUI
*
* GCLK domain frequency exported from HALCoGen GUI
*/
#define GCLK_FREQ 300.000F
/** @def HCLK_FREQ
* @brief HCLK domain frequency exported from HALCoGen GUI
*
* HCLK domain frequency exported from HALCoGen GUI
*/
#define HCLK_FREQ 150.000F
/** @def RTI_FREQ
* @brief RTI Clock frequency exported from HALCoGen GUI
*
* RTI Clock frequency exported from HALCoGen GUI
*/
#define RTI_FREQ 75.000F
/** @def AVCLK1_FREQ
* @brief AVCLK1 Domain frequency exported from HALCoGen GUI
*
* AVCLK Domain frequency exported from HALCoGen GUI
*/
#define AVCLK1_FREQ 75.000F
/** @def AVCLK2_FREQ
* @brief AVCLK2 Domain frequency exported from HALCoGen GUI
*
* AVCLK2 Domain frequency exported from HALCoGen GUI
*/
#define AVCLK2_FREQ 0.000F
/** @def AVCLK3_FREQ
* @brief AVCLK3 Domain frequency exported from HALCoGen GUI
*
* AVCLK3 Domain frequency exported from HALCoGen GUI
*/
#define AVCLK3_FREQ 75.000F
/** @def AVCLK4_FREQ
* @brief AVCLK4 Domain frequency exported from HALCoGen GUI
*
* AVCLK4 Domain frequency exported from HALCoGen GUI
*/
#define AVCLK4_FREQ 75.000F
/** @def VCLK1_FREQ
* @brief VCLK1 Domain frequency exported from HALCoGen GUI
*
* VCLK1 Domain frequency exported from HALCoGen GUI
*/
#define VCLK1_FREQ 75.000F
/** @def VCLK2_FREQ
* @brief VCLK2 Domain frequency exported from HALCoGen GUI
*
* VCLK2 Domain frequency exported from HALCoGen GUI
*/
#define VCLK2_FREQ 75.000F
/** @def VCLK3_FREQ
* @brief VCLK3 Domain frequency exported from HALCoGen GUI
*
* VCLK3 Domain frequency exported from HALCoGen GUI
*/
#define VCLK3_FREQ 75.000F
/** @def VCLK4_FREQ
* @brief VCLK4 Domain frequency exported from HALCoGen GUI
*
* VCLK4 Domain frequency exported from HALCoGen GUI
*/
#define VCLK4_FREQ 75.0F
/** @def SYS_PRE1
* @brief Alias name for RTI1CLK PRE clock source
*
* This is an alias name for the RTI1CLK pre clock source.
* This can be either:
* - Oscillator
* - Pll
* - 32 kHz Oscillator
* - External
* - Low Power Oscillator Low
* - Low Power Oscillator High
* - Flexray Pll
*/
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Macro filled using GUI parameter cannot be avoided"
*/
#define SYS_PRE1 ( SYS_PLL1 )
/** @def SYS_PRE2
* @brief Alias name for RTI2CLK pre clock source
*
* This is an alias name for the RTI2CLK pre clock source.
* This can be either:
* - Oscillator
* - Pll
* - 32 kHz Oscillator
* - External
* - Low Power Oscillator Low
* - Low Power Oscillator High
* - Flexray Pll
*/
/*SAFETYMCUSW 79 S MR:19.4 <APPROVED> "Macro filled using GUI parameter cannot be avoided"
*/
#define SYS_PRE2 ( SYS_PLL1 )
/* Configuration registers */
typedef struct system_config_reg
{
uint32 CONFIG_SYSPC1;
uint32 CONFIG_SYSPC2;
uint32 CONFIG_SYSPC7;
uint32 CONFIG_SYSPC8;
uint32 CONFIG_SYSPC9;
uint32 CONFIG_CSDIS;
uint32 CONFIG_CDDIS;
uint32 CONFIG_GHVSRC;
uint32 CONFIG_VCLKASRC;
uint32 CONFIG_RCLKSRC;
uint32 CONFIG_MSTGCR;
uint32 CONFIG_MINITGCR;
uint32 CONFIG_MSINENA;
uint32 CONFIG_PLLCTL1;
uint32 CONFIG_PLLCTL2;
uint32 CONFIG_SYSPC10;
uint32 CONFIG_LPOMONCTL;
uint32 CONFIG_CLKTEST;
uint32 CONFIG_DFTCTRLREG1;
uint32 CONFIG_DFTCTRLREG2;
uint32 CONFIG_GPREG1;
uint32 CONFIG_RAMGCR;
uint32 CONFIG_BMMCR1;
uint32 CONFIG_CLKCNTL;
uint32 CONFIG_ECPCNTL;
uint32 CONFIG_DEVCR1;
uint32 CONFIG_SYSECR;
uint32 CONFIG_PLLCTL3;
uint32 CONFIG_STCCLKDIV;
uint32 CONFIG_ECPCNTL1;
uint32 CONFIG_CLK2CNTRL;
uint32 CONFIG_VCLKACON1;
uint32 CONFIG_HCLKCNTL;
uint32 CONFIG_CLKSLIP;
uint32 CONFIG_EFC_CTLEN;
} system_config_reg_t;
/* Configuration registers initial value */
#define SYS_SYSPC1_CONFIGVALUE 0U
#define SYS_SYSPC2_CONFIGVALUE 1U
#define SYS_SYSPC7_CONFIGVALUE 0U
#define SYS_SYSPC8_CONFIGVALUE 0U
#define SYS_SYSPC9_CONFIGVALUE 1U
#define SYS_CSDIS_CONFIGVALUE \
( 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U | 0x00000000U | 0x00000000U \
| 0x00000000U | 0x4U )
#define SYS_CDDIS_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \
| ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \
| ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) )
#define SYS_GHVSRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) \
| ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) \
| ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ) )
#define SYS_VCLKASRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) \
| ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) )
#define SYS_RCLKSRC_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) )
#define SYS_MSTGCR_CONFIGVALUE 0x00000105U
#define SYS_MINITGCR_CONFIGVALUE 0x5U
#define SYS_MSINENA_CONFIGVALUE 0U
#define SYS_PLLCTL1_CONFIGVALUE_1 \
( ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U \
| ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U \
| ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) )
#define SYS_PLLCTL1_CONFIGVALUE_2 \
( ( ( SYS_PLLCTL1_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \
| ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) )
#define SYS_PLLCTL2_CONFIGVALUE \
( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 255U << 22U ) \
| ( uint32 ) ( ( uint32 ) 7U << 12U ) \
| ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U )
#define SYS_SYSPC10_CONFIGVALUE 0U
#define SYS_LPOMONCTL_CONFIGVALUE_1 \
( ( uint32 ) ( ( uint32 ) 1U << 24U ) | LPO_TRIM_VALUE )
#define SYS_LPOMONCTL_CONFIGVALUE_2 \
( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 16U << 8U ) | 16U )
#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U
#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U
#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U
#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU
#define SYS_RAMGCR_CONFIGVALUE 0x00050000U
#define SYS_BMMCR1_CONFIGVALUE 0xAU
#define SYS_CLKCNTL_CONFIGVALUE \
( 0x00000100U | ( uint32 ) ( ( uint32 ) 1U << 16U ) \
| ( uint32 ) ( ( uint32 ) 1U << 24U ) )
#define SYS_ECPCNTL_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \
| ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ) )
#define SYS_DEVCR1_CONFIGVALUE 0xAU
#define SYS_SYSECR_CONFIGVALUE 0x00004000U
#define SYS2_PLLCTL3_CONFIGVALUE_1 \
( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) \
| ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) \
| ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) )
#define SYS2_PLLCTL3_CONFIGVALUE_2 \
( ( ( SYS2_PLLCTL3_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \
| ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) )
#define SYS2_STCCLKDIV_CONFIGVALUE 0U
#define SYS2_ECPCNTL1_CONFIGVALUE 0x50000000U
#define SYS2_CLK2CNTRL_CONFIGVALUE ( 1U | 0x00000100U )
#define SYS2_HCLKCNTL_CONFIGVALUE 1U
#define SYS2_VCLKACON1_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 1U << 20U ) \
| ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \
| ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) )
#define SYS2_CLKSLIP_CONFIGVALUE 0x5U
#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U
#define L2FLASH_FBPWRMODE_CONFIGVALUE \
( ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) | ( uint32 ) ( ( uint32 ) 3U << 12U ) \
| ( uint32 ) ( ( uint32 ) 3U << 10U ) | ( uint32 ) ( ( uint32 ) 3U << 8U ) \
| ( uint32 ) ( ( uint32 ) 3U << 6U ) | ( uint32 ) ( ( uint32 ) 3U << 4U ) \
| ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) \
| ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ) )
#define L2FLASH_FRDCNTL_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U )
void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type );
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* FlashW General Definitions */
/** @enum flashWPowerModes
* @brief Alias names for flash bank power modes
*
* This enumeration is used to provide alias names for the flash bank power modes:
* - sleep
* - standby
* - active
*/
enum flashWPowerModes
{
SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
};
/* USER CODE BEGIN (2) */
/* USER CODE END */
#define FSM_WR_ENA_HL ( *( volatile uint32 * ) 0xFFF87288U )
#define EEPROM_CONFIG_HL ( *( volatile uint32 * ) 0xFFF872B8U )
#define FSM_SECTOR1 ( *( volatile uint32 * ) 0xFFF872C0U )
#define FSM_SECTOR2 ( *( volatile uint32 * ) 0xFFF872C4U )
#define FCFG_BANK ( *( volatile uint32 * ) 0xFFF87400U )
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* System Interface Functions */
void setupPLL( void );
void trimLPO( void );
void customTrimLPO( void );
void setupFlash( void );
void periphInit( void );
void mapClocks( void );
void systemInit( void );
void systemPowerDown( uint32 mode );
resetSource_t getResetSource( void );
/* USER CODE BEGIN (4) */
/* USER CODE END */
/**@}*/
#ifdef __cplusplus
}
#endif /*extern "C" */
#endif

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FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h
Unescape Escape View File

@ -0,0 +1,625 @@
/**********************************************************************************************************************
* FILE DESCRIPTION
*
-------------------------------------------------------------------------------------------------------------------
* File: ti_fee.h
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: None
*
* Description: This file implements the TI FEE Api.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version
* 00.01.01 29Oct2012 Vishwanath Reddy 0000000000000 Changes for
implementing Error Recovery
* 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory
segmentation changes.
* 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested
by Vector.
* 00.01.04 12Feb2012 Vishwanath Reddy SDOCM00099152 Integration issues
fix.
* 00.01.05 04Mar2013 Vishwanath Reddy SDOCM00099152 Added Deleting a
block feature, bug fixes.
* 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature :
copying of unconfigured blocks.
* 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature :
Number of 8 bytes writes, fixed issue with copy blocks.
* 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature : CRC
check for unconfigured blocks, Main function modified to complete writes as fast as
possible, Added Non polling mode support.
* 00.01.09 19Apr2013 Vishwanath Reddy SDOCM00099152 Warning removal,
Added feature comparision of data during write.
* 00.01.10 11Jun2013 Vishwanath Reddy SDOCM00101845 Updated version
information.
* 00.01.11 05Jul2013 Vishwanath Reddy SDOCM00101643 Updated version
information.
* 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags
added.
* MISRA C fixes.
Version info corrected.
* 01.13.00 30Dec2013 Vishwanath Reddy 0000000000000 Undated version info
for SDOCM00107976
* and SDOCM00105795.
* 01.13.01 19May2014 Vishwanath Reddy 0000000000000 Updated version info
for SDOCM00107913
* and SDOCM00107622.
* 01.13.02 12Jun2014 Vishwanath Reddy 0000000000000 Updated version info
for SDOCM00108238
* 01.14.00 26Mar2014 Vishwanath Reddy Update version info
for SDOCM00107161.
* 01.15.00 06Jun2014 Vishwanath Reddy Support for
Conqueror.
* 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA
warnings.
* 01.16.01 12Sep2014 Vishwanath Reddy SDOCM00112930 Prototype for
TI_Fee_SuspendResumeErase added.
* TI_Fee_EraseCommandType enum added.
* extern added for
TI_Fee_bEraseSuspended.
* 01.17.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization
changes.
* 01.17.01 30Oct2014 Vishwanath Reddy SDOCM00113536 Support for
TMS570LS07xx,TMS570LS09xx,
* TMS570LS05xx, RM44Lx.
* 01.17.02 26Dec2014 Vishwanath Reddy SDOCM00114102 FLEE Errata Fix.
* SDOCM00114104 Change ALL 1's OK
check condition.
* Updated version info.
Added new macros.
* SDOCM00114423 Add new enum
TI_Fee_DeviceType.
* Add new variable
TI_Fee_MaxSectors and
* prototype
TI_FeeInternal_PopulateStructures.
* 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version
history.
* Update ti_fee_util.c
file for the
* bugfix "If morethan
one data set is config-
* ured, then a valid
block may get invalidated if
* multiple valid blocks
are present in FEE memory.
* 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version
history.
* In
TI_FeeInternal_FeeManager, do not change the
* state to IDLE,after
completing the copy operation.
* 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version
history.
* Add a call of
TI_FeeInternal_PollFlashStatus()
* before reading data
from FEE bank in
* TI_FeeInternal_UpdateBlockOffsetArray(),
* TI_Fee_WriteAsync(),TI_Fee_WriteSync(),
* TI_Fee_ReadSync(),
TI_Fee_Read()
* 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update patch version
TI_FEE_SW_PATCH_VERSION.
* TI_FEE_FLASH_CRC_ENABLE is renamed to
* TI_FEE_FLASH_CHECKSUM_ENABLE.
* SDOCM00122429 In ti_fee_types.h,
add error when endianess
* is not defined.
* 01.19.00 08Augu2016 Vishwanath Reddy SDOCM00122592 Update patch version
TI_FEE_MINOR_VERSION.
* Code for using
partially ersed sector is now
* removed.
* Bugfix for FEE
reading from unimplemented memory
* space.
* 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update patch version
TI_FEE_MINOR_VERSION.
* Synchronous write API
modified to avoid copy of
* already copied block.
* 01.19.02 25Janu2017 Vishwanath Reddy SDOCM00122832 Update patch version
TI_FEE_MINOR_VERSION.
* Format API modified
to erase all configured VS.
* SDOCM00122833 In API
TI_Fee_ErrorRecovery, added polling for
* flash status before
calling TI_Fee_Init.
* 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Added
TI_Fee_bIsMainFunctionCalled Global Variable.
* 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version
history.
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef TI_FEE_H
#define TI_FEE_H
/**********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#include "hal_stdtypes.h"
#include "fee_interface.h"
#include "ti_fee_types.h"
#include "ti_fee_cfg.h"
/**********************************************************************************************************************
* GLOBAL CONSTANT MACROS
*********************************************************************************************************************/
/* Fee Published Information */
#define TI_FEE_MAJOR_VERSION 3U
#define TI_FEE_MINOR_VERSION 0U
#define TI_FEE_PATCH_VERSION 2U
#define TI_FEE_SW_MAJOR_VERSION 1U
#define TI_FEE_SW_MINOR_VERSION 19U
#define TI_FEE_SW_PATCH_VERSION 4U
#define TI_FEE_VIRTUAL_SECTOR_VERSION 1U
/* Virtual sector states */
#define ActiveVSHi 0x0000FFFFU
#define ActiveVSLo 0x00000000U
#define CopyVSHi 0xFFFFFFFFU
#define CopyVSLo 0x00000000U
#define EmptyVSHi 0xFFFFFFFFU
#define EmptyVSLo 0x0000FFFFU
#define InvalidVSHi 0xFFFFFFFFU
#define InvalidVSLo 0xFFFFFFFFU
#define ReadyforEraseVSHi 0x00000000U
#define ReadyforEraseVSLo 0x00000000U
/* Data Block states*/
#define EmptyBlockHi 0xFFFFFFFFU
#define EmptyBlockLo 0xFFFFFFFFU
#define StartProgramBlockHi 0xFFFF0000U
#define StartProgramBlockLo 0xFFFFFFFFU
#define ValidBlockHi 0x00000000U
#define ValidBlockLo 0xFFFFFFFFU
#define InvalidBlockHi 0x00000000U
#define InvalidBlockLo 0xFFFF0000U
#define CorruptBlockHi 0x00000000U
#define CorruptBlockLo 0x00000000U
#define FEE_BANK 0U
/* Enable/Disable FEE sectors */
#define FEE_DISABLE_SECTORS_31_00 0x00000000U
#define FEE_DISABLE_SECTORS_63_32 0x00000000U
#define FEE_ENABLE_SECTORS_31_00 0xFFFFFFFFU
#define FEE_ENABLE_SECTORS_63_32 0xFFFFFFFFU
/**********************************************************************************************************************
* GLOBAL DATA TYPES AND STRUCTURES
*********************************************************************************************************************/
/* Structures used */
/* Enum to describe the Fee Status types */
typedef enum
{
TI_FEE_OK = 0U, /* Function returned no error */
TI_FEE_ERROR = 1U /* Function returned an error */
} TI_Fee_StatusType;
/* Enum to describe the Virtual Sector State */
typedef enum
{
VsState_Invalid = 1U,
VsState_Empty = 2U,
VsState_Copy = 3U,
VsState_Active = 4U,
VsState_ReadyForErase = 5U
} VirtualSectorStatesType;
/* Enum to describe the Block State */
typedef enum
{
Block_StartProg = 1U,
Block_Valid = 2U,
Block_Invalid = 3U
} BlockStatesType;
/* Enum for error trpes */
typedef enum
{
Error_Nil = 0U,
Error_TwoActiveVS = 1U,
Error_TwoCopyVS = 2U,
Error_SetupStateMachine = 3U,
Error_CopyButNoActiveVS = 4U,
Error_NoActiveVS = 5U,
Error_BlockInvalid = 6U,
Error_NullDataPtr = 7U,
Error_NoFreeVS = 8U,
Error_InvalidVirtualSectorParameter = 9U,
Error_ExceedSectorOnBank = 10U,
Error_EraseVS = 11U,
Error_BlockOffsetGtBlockSize = 12U,
Error_LengthParam = 13U,
Error_FeeUninit = 14U,
Error_Suspend = 15U,
Error_InvalidBlockIndex = 16U,
Error_NoErase = 17U,
Error_CurrentAddress = 18U,
Error_Exceed_No_Of_DataSets = 19U
} TI_Fee_ErrorCodeType;
typedef enum
{
Suspend_Erase = 0U,
Resume_Erase
} TI_Fee_EraseCommandType;
/* Enum to describe the Device types */
typedef enum
{
CHAMPION = 0U, /* Function returned no error */
ARCHER = 1U /* Function returned an error */
} TI_Fee_DeviceType;
typedef uint32 TI_Fee_AddressType; /* Used for defining variables to indicate number of
bytes for address offset */
typedef uint32 TI_Fee_LengthType; /* Used for defining variables to indicate number of
bytes per read/write/erase */
typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType;
/* Structure used when defining virtual sectors */
/* The following error checks need to be performed: */
/* Virtual Sector definitions are not allowed to overlap */
/* Virtual Sector definition is at least twice the size in bytes of the total size of all
* defined blocks */
/* We will need to define a formula to indicate if the number of write cycles indicated in
* the block definitions */
/* is possible in the defined Virtual Sector. */
/* Ending sector cannot be less than Starting sector */
typedef struct
{
uint16 FeeVirtualSectorNumber; /* Virtual Sector's Number - 0 and 0xFFFF values are
not allowed*/
/* Minimum 1, Maximum 4 */
uint16 FeeFlashBank; /* Flash Bank to use for virtual sector. */
/* As we do not allow Flash EEPROM Emulation in Bank 0,
0 is not a valid option */
/* Defaultvalue 1, Minimum 1, Maxiumum 7 */
Fapi_FlashSectorType FeeStartSector; /* Defines the Starting Sector inthe Bank for
this VirtualSector*/
Fapi_FlashSectorType FeeEndSector; /* Defines the Ending Sector inthe Bank for this
Virtual Sector */
/* Start and End sectors can be the same, which indicates only
one sector */
/* is the entire virtual sector. */
/* Values are based on the FLASH_SECT enum */
/* Defaultvalue and Min is the same sector defined as the starting
sector */
/* Max values are based onthe device definition file being used.*/
} Fee_VirtualSectorConfigType;
/* Structure used when defining blocks */
typedef struct
{
uint16 FeeBlockNumber; /* Block's Number - 0 and 0xFFFF values are not allowed */
/* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */
uint16 FeeBlockSize; /* Block's Size - Actual number of bits used is reduced */
/* by number of bits used for dataset. */
/* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */
boolean FeeImmediateData; /* Indicates if the block is used for immediate data */
/* Default: False */
uint32 FeeNumberOfWriteCycles; /* Number of write cycles this block requires */
/* Default: 0, but this will not be a valid number.
Force customer to select a value */
/* Min 1, Max (2^32)-1 */
uint8 FeeDeviceIndex; /* Device Index - This will always be 0 */
/* Fixed value: 0 */
uint8 FeeNumberOfDataSets; /* Number of DataSets for the Block */
/* Default value: 1 */
uint8 FeeEEPNumber;
} Fee_BlockConfigType;
/* Structure used for Global variables */
typedef struct
{
TI_Fee_AddressType Fee_oFlashNextAddress; /* The next Flash Address to write to */
TI_Fee_AddressType Fee_oCopyCurrentAddress; /* Indicates the Address within the Active
VS which will be copied to Copy VS */
TI_Fee_AddressType Fee_oCopyNextAddress; /* Indicates the Address within the Copy VS
to which the data from Active VS will be
copied to */
TI_Fee_AddressType Fee_u32nextwriteaddress; /* Indicates the next free Address within
the curent VS to which the data will be
written */
TI_Fee_AddressType Fee_oVirtualSectorStartAddress; /* Start Address of the current
Virtual Sector */
TI_Fee_AddressType Fee_oVirtualSectorEndAddress; /* End Address of the current Virtual
Sector */
TI_Fee_AddressType Fee_oCopyVirtualSectorAddress; /* Start Address of the Copy Virtual
Address */
TI_Fee_AddressType Fee_oCurrentStartAddress; /* Start Address of the Previous Block */
TI_Fee_AddressType Fee_oCurrentBlockHeader; /* Start Address of the Block which is
being currently written*/
TI_Fee_AddressType Fee_oWriteAddress; /* Address within the VS where data is to be
written */
TI_Fee_AddressType Fee_oCopyWriteAddress; /* Address within the VS where data is to be
copied */
TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; /* Start Address of the Active VS
*/
TI_Fee_AddressType Fee_oBlankFailAddress; /* Address of first non-blank location */
TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress; /* Start Address of the
active VS */
TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress; /* End Address of the active VS
*/
TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress; /* Start Address of the Copy VS
*/
TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress; /* End Address of the Copy VS */
TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress; /* Next write address in Active VS
*/
TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress; /* Next write address in Copy VS */
uint16 Fee_u16CopyBlockSize; /* Indicates the size of current block in bytes which is
been copied from Active to Copy VS */
uint8 Fee_u8VirtualSectorStart; /* Index of the Start Sector of the VS */
uint8 Fee_u8VirtualSectorEnd; /* Index of the End Sector of the VS */
uint32 Fee_au32VirtualSectorStateValue[ TI_FEE_VIRTUAL_SECTOR_OVERHEAD
>> 2U ]; /* Array to store the Virtual
Sector Header and
Information record */
uint8 Fee_au8VirtualSectorState[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Stores the
state of each
Virtual sector
*/
uint32 Fee_au32VirtualSectorEraseCount[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Array
to
store
the
erase
count
of each
Virtual
Sector*/
uint16 Fee_au16BlockOffset[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to store within
the VS */
uint32 Fee_au32BlockHeader[ TI_FEE_BLOCK_OVERHEAD >> 2U ]; /* Array to store the Block
Header value */
uint8 Fee_au8BlockCopyStatus[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to storeblock
copy status */
uint8 Fee_u8InternalVirtualSectorStart; /* Indicates internal VS start index */
uint8 Fee_u8InternalVirtualSectorEnd; /* Indicates internal VS end index */
TI_FeeModuleStatusType Fee_ModuleState; /* Indicates the state of the FEE module */
TI_FeeJobResultType Fee_u16JobResult; /* Stores the Job Result of the current command
*/
TI_Fee_StatusType Fee_oStatus; /* Indicates the status of FEE */
TI_Fee_ErrorCodeType Fee_Error; /* Indicates the Error code */
uint16 Fee_u16CopyBlockNumber; /* Block number which is currently being copied */
uint16 Fee_u16BlockIndex; /* Index of the Current Block */
uint16 Fee_u16BlockCopyIndex; /* Index of the Block being copied from Copy to Active
VS */
uint16 Fee_u16DataSetIndex; /* Index of the Current DataSet */
uint16 Fee_u16ArrayIndex; /* Index of the Current DataSet */
uint16 Fee_u16BlockSize; /* Size of the current block in bytes */
uint16 Fee_u16BlockSizeinBlockHeader; /* Size of the current block. Used to write into
Block Header */
uint16 Fee_u16BlockNumberinBlockHeader; /* Number of the current block. Used to write
into Block Header */
uint8 Fee_u8ActiveVirtualSector; /* Indicates the FeeVirtualSectorNumber for the
Active VS */
uint8 Fee_u8CopyVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Copy VS
*/
uint32 Fee_u32InternalEraseQueue; /* Indicates which VS can be erased when the FEE is
in BusyInternal State*/
uint8 Fee_u8WriteCopyVSHeader; /* Indicates the number of bytes of the Copy VS Header
being written */
uint8 Fee_u8WriteCount; /* Indicates the number of bytes of the Block Header being
written */
uint8 * Fee_pu8ReadDataBuffer; /* Pointer to read data */
uint8 * Fee_pu8ReadAddress; /* Pointer to read address */
uint8 * Fee_pu8Data; /* Pointer to the next data to be written to the VS */
uint8 * Fee_pu8CopyData; /* Pointer to the next data to be copied to the VS */
uint8 * Fee_pu8DataStart; /* Pointer to the first data to be written to the VS */
boolean Fee_bInvalidWriteBit; /* Indicates whether the block is
written/invalidated/erased for the first time */
boolean Fee_bWriteData; /* Indicates that there is data which is pending to be written
to the Block */
boolean Fee_bWriteBlockHeader; /* Indicates whether the Block Header has been written
or not */
boolean bWriteFirstTime; /* Indicates if the block is being written first time */
boolean Fee_bFindNextVirtualSector; /* Indicates if there is aneed to find next free
VS */
boolean Fee_bWriteVSHeader; /* Indicates if block header needs to be written */
boolean Fee_bWriteStartProgram; /* Indicates if start program block header needs to be
written */
boolean Fee_bWritePartialBlockHeader; /* Indicates if start program block header needs
to be written */
#if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U )
uint16 Fee_au16UnConfiguredBlockAddress
[ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Indicates
number of unconfigured blocks to copy */
uint8 Fee_au8UnConfiguredBlockCopyStatus
[ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Array to store block
copy status */
#endif
} TI_Fee_GlobalVarsType;
/**********************************************************************************************************************
* EXTERN Declarations
*********************************************************************************************************************/
/* Fee Global Variables */
extern const Fee_BlockConfigType Fee_BlockConfiguration[ TI_FEE_NUMBER_OF_BLOCKS ];
#if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF )
extern const Fee_VirtualSectorConfigType
Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ];
extern const Device_FlashType Device_FlashDevice;
#endif
#if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON )
extern Fee_VirtualSectorConfigType
Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ];
extern Device_FlashType Device_FlashDevice;
extern uint8 TI_Fee_MaxSectors;
#endif
extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[ TI_FEE_NUMBER_OF_EEPS ];
extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[ TI_FEE_NUMBER_OF_EEPS ];
#if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON )
extern uint32 TI_Fee_u32FletcherChecksum;
#endif
extern uint32 TI_Fee_u32BlockEraseCount;
extern uint8 TI_Fee_u8DataSets;
extern uint8 TI_Fee_u8DeviceIndex;
extern uint32 TI_Fee_u32ActCpyVS;
extern uint8 TI_Fee_u8ErrEraseVS;
#if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U )
extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[ TI_FEE_NUMBER_OF_EEPS ];
#endif
#if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix )
extern boolean Fee_bDoubleBitError;
extern boolean Fee_bSingleBitError;
#endif
#if( TI_FEE_NUMBER_OF_EEPS == 2U )
extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global;
#endif
extern boolean TI_Fee_FapiInitCalled;
extern boolean TI_Fee_bEraseSuspended;
extern boolean TI_Fee_bIsMainFunctionCalled;
/**********************************************************************************************************************
* GLOBAL FUNCTION PROTOTYPES
*********************************************************************************************************************/
/* Interface Functions */
extern void TI_Fee_Cancel( uint8 u8EEPIndex );
extern Std_ReturnType TI_Fee_EraseImmediateBlock( uint16 BlockNumber );
extern TI_FeeModuleStatusType TI_Fee_GetStatus( uint8 u8EEPIndex );
extern void TI_Fee_GetVersionInfo( Std_VersionInfoType * VersionInfoPtr );
extern void TI_Fee_Init( void );
extern Std_ReturnType TI_Fee_InvalidateBlock( uint16 BlockNumber );
extern Std_ReturnType TI_Fee_Read( uint16 BlockNumber,
uint16 BlockOffset,
uint8 * DataBufferPtr,
uint16 Length );
extern Std_ReturnType TI_Fee_WriteAsync( uint16 BlockNumber, uint8 * DataBufferPtr );
extern void TI_Fee_MainFunction( void );
extern TI_Fee_ErrorCodeType TI_FeeErrorCode( uint8 u8EEPIndex );
extern void TI_Fee_ErrorRecovery( TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector );
extern TI_FeeJobResultType TI_Fee_GetJobResult( uint8 u8EEPIndex );
extern void TI_Fee_SuspendResumeErase( TI_Fee_EraseCommandType Command );
#if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix )
extern void TI_Fee_ErrorHookSingleBitError( void );
extern void TI_Fee_ErrorHookDoubleBitError( void );
#endif
#if( TI_FEE_DRIVER == 1U )
extern Std_ReturnType TI_Fee_WriteSync( uint16 BlockNumber, uint8 * DataBufferPtr );
extern Std_ReturnType TI_Fee_Shutdown( void );
extern boolean TI_Fee_Format( uint32 u32FormatKey );
extern Std_ReturnType TI_Fee_ReadSync( uint16 BlockNumber,
uint16 BlockOffset,
uint8 * DataBufferPtr,
uint16 Length );
#endif
/* TI Fee Internal Functions */
TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress( uint8 u8EEPIndex );
TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC( TI_Fee_AddressType oAddress );
TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress( uint16 BlockNumber,
uint16 DataSetNumber,
uint8 u8EEPIndex );
/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason -
* TI_FeeInternal_GetVirtualSectorParameter name is required here."*/
uint32 TI_FeeInternal_GetVirtualSectorParameter( Fapi_FlashSectorType oSector,
uint16 u16Bank,
boolean VirtualSectorInfo,
uint8 u8EEPIndex );
uint32 TI_FeeInternal_PollFlashStatus( void );
uint16 TI_FeeInternal_GetBlockSize( uint16 BlockIndex );
uint16 TI_FeeInternal_GetBlockIndex( uint16 BlockNumber );
uint16 TI_FeeInternal_GetDataSetIndex( uint16 BlockNumber );
uint16 TI_FeeInternal_GetBlockNumber( uint16 BlockNumber );
uint8 TI_FeeInternal_FindNextVirtualSector( uint8 u8EEPIndex );
uint8 TI_FeeInternal_WriteDataF021( boolean bCopy,
uint16 u16WriteSize,
uint8 u8EEPIndex );
boolean TI_FeeInternal_BlankCheck( uint32 u32StartAddress,
uint32 u32EndAddress,
uint16 u16Bank,
uint8 u8EEPIndex );
Std_ReturnType TI_FeeInternal_CheckReadParameters( uint32 u32BlockSize,
uint16 BlockOffset,
const uint8 * DataBufferPtr,
uint16 Length,
uint8 u8EEPIndex );
Std_ReturnType TI_FeeInternal_CheckModuleState( uint8 u8EEPIndex );
Std_ReturnType TI_FeeInternal_InvalidateErase( uint16 BlockNumber );
TI_Fee_StatusType TI_FeeInternal_FeeManager( uint8 u8EEPIndex );
void TI_FeeInternal_WriteVirtualSectorHeader( uint8 FeeVirtualSectorNumber,
VirtualSectorStatesType VsState,
uint8 u8EEPIndex );
/*SAFETYMCUSW 61 X MR:1.4,5.1 <APPROVED> "Reason - TI_FeeInternal_GetVirtualSectorIndex
* name is required here."*/
void TI_FeeInternal_GetVirtualSectorIndex( Fapi_FlashSectorType oSectorStart,
Fapi_FlashSectorType oSectorEnd,
uint16 u16Bank,
boolean bOperation,
uint8 u8EEPIndex );
void TI_FeeInternal_WritePreviousBlockHeader( boolean bWrite, uint8 u8EEPIndex );
void TI_FeeInternal_WriteBlockHeader( boolean bWrite,
uint8 u8EEPIndex,
uint16 Fee_BlockSize_u16,
uint16 u16BlockNumber );
void TI_FeeInternal_SetClearCopyBlockState( uint8 u8EEPIndex, boolean bSetClear );
void TI_FeeInternal_SanityCheck( uint16 BlockSize, uint8 u8EEPIndex );
void TI_FeeInternal_StartProgramBlock( uint8 u8EEPIndex );
void TI_FeeInternal_UpdateBlockOffsetArray( uint8 u8EEPIndex,
boolean bActCpyVS,
uint8 u8VirtualSector );
void TI_FeeInternal_WriteInitialize( TI_Fee_AddressType oFlashNextAddress,
uint8 * DataBufferPtr,
uint8 u8EEPIndex );
void TI_FeeInternal_CheckForError( uint8 u8EEPIndex );
void TI_FeeInternal_EnableRequiredFlashSector( uint32 u32VirtualSectorStartAddress );
uint16 TI_FeeInternal_GetArrayIndex( uint16 BlockNumber,
uint16 DataSetNumber,
uint8 u8EEPIndex,
boolean bCallContext );
#if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON )
uint32 TI_FeeInternal_Fletcher16( uint8 const * pu8data, uint16 u16Length );
#endif
#if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON )
void TI_FeeInternal_PopulateStructures( TI_Fee_DeviceType DeviceType );
#endif
#endif /* TI_FEE_H */
/**********************************************************************************************************************
* END OF FILE: ti_fee.h
*********************************************************************************************************************/

55
FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h
Unescape Escape View File

@ -0,0 +1,55 @@
/**********************************************************************************************************************
* FILE DESCRIPTION
* -------------------------------------------------------------------------------------------------------------------
* File: ti_fee_cfg.h
* Project: Tms570_TIFEEDriver
* Module: TIFEEDriver
* Generator: HALCoGen
*
* Description: This file implements the TI FEE Api.
*---------------------------------------------------------------------------------------------------------------------
* Author: Vishwanath Reddy
*---------------------------------------------------------------------------------------------------------------------
* Revision History
*---------------------------------------------------------------------------------------------------------------------
* Version Date Author Change ID Description
*---------------------------------------------------------------------------------------------------------------------
* 00.00.01 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version
* 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version
*history.
*
*********************************************************************************************************************/
/*
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

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