Continue work on emac driver.
Richard Barry
16 years ago
parent
ec5827a601
commit
83c2470ead
@ -0,0 +1,456 @@
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/******************************************************************
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***** *****
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***** Ver.: 1.0 *****
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***** Date: 07/05/2001 *****
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***** Auth: Andreas Dannenberg *****
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***** HTWK Leipzig *****
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***** university of applied sciences *****
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***** Germany *****
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***** Func: ethernet packet-driver for use with LAN- *****
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***** controller CS8900 from Crystal/Cirrus Logic *****
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***** *****
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***** Keil: Module modified for use with Philips *****
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***** LPC2378 EMAC Ethernet controller *****
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***** *****
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******************************************************************/
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/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#include "LPC17xx_defs.h"
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#include "EthDev_LPC17xx.h"
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#define emacPINSEL2_VALUE 0x50150105
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#define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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#define emacSHORT_DELAY ( 2 )
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#define emacLINK_ESTABLISHED ( 0x0001 )
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#define emacFULL_DUPLEX_ENABLED ( 0x0004 )
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#define emac10BASE_T_MODE ( 0x0002 )
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/* The semaphore used to wake the uIP task when data arives. */
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xSemaphoreHandle xEMACSemaphore = NULL;
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static unsigned short *rptr;
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static unsigned short *tptr;
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static void prvInitDescriptors( void );
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static void prvSetupEMACHardware( void );
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static void prvConfigurePHY( void );
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static long prvSetupLinkStatus( void );
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/*-----------------------------------------------------------*/
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int write_PHY( long lPhyReg, long lValue )
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{
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const long lMaxTime = 10;
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long x;
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MAC_MADR = DP83848C_DEF_ADR | lPhyReg;
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MAC_MWTD = lValue;
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x = 0;
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for( x = 0; x < lMaxTime; x++ )
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{
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if( ( MAC_MIND & MIND_BUSY ) == 0 )
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{
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/* Operation has finished. */
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break;
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}
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vTaskDelay( emacSHORT_DELAY );
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}
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if( x < lMaxTime )
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{
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return pdPASS;
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}
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else
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{
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return pdFAIL;
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}
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}
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/*-----------------------------------------------------------*/
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unsigned short read_PHY( unsigned char ucPhyReg, portBASE_TYPE *pxStatus )
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{
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long x;
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const long lMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | ucPhyReg;
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MAC_MCMD = MCMD_READ;
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for( x = 0; x < lMaxTime; x++ )
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{
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/* Operation has finished. */
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if( ( MAC_MIND & MIND_BUSY ) == 0 )
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{
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break;
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}
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vTaskDelay( emacSHORT_DELAY );
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}
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MAC_MCMD = 0;
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if( x >= lMaxTime )
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{
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*pxStatus = pdFAIL;
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}
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return( MAC_MRDD );
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}
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/*-----------------------------------------------------------*/
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static void prvInitDescriptors( void )
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{
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long x;
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for( x = 0; x < NUM_RX_FRAG; x++ )
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{
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RX_DESC_PACKET( x ) = RX_BUF( x );
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RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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RX_STAT_INFO( x ) = 0;
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RX_STAT_HASHCRC( x ) = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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MAC_RXDESCRIPTOR = RX_DESC_BASE;
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MAC_RXSTATUS = RX_STAT_BASE;
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MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;
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/* Rx Descriptors Point to 0 */
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MAC_RXCONSUMEINDEX = 0;
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for( x = 0; x < NUM_TX_FRAG; x++ )
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{
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TX_DESC_PACKET( x ) = TX_BUF( x );
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TX_DESC_CTRL( x ) = 0;
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TX_STAT_INFO( x ) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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MAC_TXDESCRIPTOR = TX_DESC_BASE;
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MAC_TXSTATUS = TX_STAT_BASE;
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MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;
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/* Tx Descriptors Point to 0 */
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MAC_TXPRODUCEINDEX = 0;
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}
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/*-----------------------------------------------------------*/
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static void prvSetupEMACHardware( void )
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{
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unsigned short us;
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long x;
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/* Enable P1 Ethernet Pins. */
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PINSEL2 = emacPINSEL2_VALUE;
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PINSEL3 = ( PINSEL3 & ~0x0000000F ) | 0x00000005;
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/* Power Up the EMAC controller. */
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PCONP |= PCONP_PCENET;
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vTaskDelay( emacSHORT_DELAY );
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/* Reset all EMAC internal modules. */
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MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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/* A short delay after reset. */
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vTaskDelay( emacSHORT_DELAY );
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/* Initialize MAC control registers. */
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MAC_MAC1 = MAC1_PASS_ALL;
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MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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MAC_MAXF = ETH_MAX_FLEN;
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MAC_CLRT = CLRT_DEF;
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MAC_IPGR = IPGR_DEF;
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/* Enable Reduced MII interface. */
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MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
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/* Reset Reduced MII Logic. */
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MAC_SUPP = SUPP_RES_RMII;
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vTaskDelay( emacSHORT_DELAY );
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MAC_SUPP = 0;
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/* Put the PHY in reset mode */
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write_PHY( PHY_REG_BMCR, MCFG_RES_MII );
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write_PHY( PHY_REG_BMCR, MCFG_RES_MII );
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/* Wait for hardware reset to end. */
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for( x = 0; x < 100; x++ )
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{
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vTaskDelay( emacSHORT_DELAY * 5 );
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us = read_PHY( PHY_REG_BMCR, &us );
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if( !( us & MCFG_RES_MII ) )
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{
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/* Reset complete */
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break;
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}
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}
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}
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/*-----------------------------------------------------------*/
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static void prvConfigurePHY( void )
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{
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unsigned short us;
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long x;
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/* Auto negotiate the configuration. */
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if( write_PHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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{
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vTaskDelay( emacSHORT_DELAY * 5 );
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for( x = 0; x < 10; x++ )
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{
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us = read_PHY( PHY_REG_BMSR, &us );
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if( us & PHY_AUTO_NEG_COMPLETE )
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{
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break;
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}
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vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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}
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}
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}
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/*-----------------------------------------------------------*/
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static long prvSetupLinkStatus( void )
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{
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long lReturn = pdFAIL, x;
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unsigned short usLinkStatus;
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for( x = 0; x < 10; x++ )
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{
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usLinkStatus = read_PHY( PHY_REG_STS, &lReturn );
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if( usLinkStatus & emacLINK_ESTABLISHED )
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{
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/* Link is established. */
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lReturn = pdPASS;
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break;
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}
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vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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}
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if( lReturn == pdPASS )
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{
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/* Configure Full/Half Duplex mode. */
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if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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{
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/* Full duplex is enabled. */
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MAC_MAC2 |= MAC2_FULL_DUP;
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MAC_COMMAND |= CR_FULL_DUP;
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MAC_IPGT = IPGT_FULL_DUP;
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}
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else
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{
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/* Half duplex mode. */
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MAC_IPGT = IPGT_HALF_DUP;
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}
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/* Configure 100MBit/10MBit mode. */
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if( usLinkStatus & emac10BASE_T_MODE )
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{
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/* 10MBit mode. */
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MAC_SUPP = 0;
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}
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else
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{
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/* 100MBit mode. */
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MAC_SUPP = SUPP_SPEED;
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}
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}
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE Init_EMAC( void )
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{
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portBASE_TYPE xReturn = pdPASS;
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volatile unsigned long regv, tout;
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unsigned long ulID1, ulID2;
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/* Reset peripherals, configure port pins and registers. */
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prvSetupEMACHardware();
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/* Check if connected to a DP83848C PHY. */
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ulID1 = read_PHY( PHY_REG_IDR1, &xReturn );
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ulID2 = read_PHY( PHY_REG_IDR2, &xReturn );
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if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
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{
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/* Set the Ethernet MAC Address registers */
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MAC_SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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MAC_SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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MAC_SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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/* Initialize Tx and Rx DMA Descriptors */
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prvInitDescriptors();
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/* Receive Broadcast and Perfect Match Packets */
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MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Create the semaphore used to wake the uIP task. */
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vSemaphoreCreateBinary( xEMACSemaphore );
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/* Setup the PHY. */
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prvConfigurePHY();
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}
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else
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{
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xReturn = pdFAIL;
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}
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/* Check the link status. */
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if( xReturn == pdPASS )
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{
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xReturn = prvSetupLinkStatus();
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}
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if( xReturn == pdPASS )
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{
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/* Reset all interrupts */
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MAC_INTCLEAR = 0xFFFF;
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/* Enable receive and transmit mode of MAC Ethernet core */
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MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
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MAC_MAC1 |= MAC1_REC_EN;
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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// reads a word in little-endian byte order from RX_BUFFER
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unsigned short ReadFrame_EMAC( void )
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{
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return( *rptr++ );
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}
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// copies bytes from frame port to MCU-memory
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// NOTES: * an odd number of byte may only be transfered
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// if the frame is read to the end!
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// * MCU-memory MUST start at word-boundary
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void CopyFromFrame_EMAC( void *Dest, unsigned short Size )
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{
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unsigned short *piDest; // Keil: Pointer added to correct expression
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piDest = Dest; // Keil: Line added
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while( Size > 1 )
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{
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*piDest++ = ReadFrame_EMAC();
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Size -= 2;
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}
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if( Size )
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{ // check for leftover byte...
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*( unsigned char * ) piDest = ( char ) ReadFrame_EMAC(); // the LAN-Controller will return 0
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} // for the highbyte
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}
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// Reads the length of the received ethernet frame and checks if the
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// destination address is a broadcast message or not
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// returns the frame length
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unsigned short StartReadFrame( void )
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{
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unsigned short RxLen;
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unsigned int idx;
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idx = MAC_RXCONSUMEINDEX;
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RxLen = ( RX_STAT_INFO(idx) & RINFO_SIZE ) - 3;
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rptr = ( unsigned short * ) RX_DESC_PACKET( idx );
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return( RxLen );
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}
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void EndReadFrame( void )
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{
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unsigned int idx;
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/* DMA free packet. */
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idx = MAC_RXCONSUMEINDEX;
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if( ++idx == NUM_RX_FRAG )
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{
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idx = 0;
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}
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MAC_RXCONSUMEINDEX = idx;
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}
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unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
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{
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unsigned int uiLen = 0;
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if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
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{
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uiLen = StartReadFrame();
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CopyFromFrame_EMAC( ucBuffer, uiLen );
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EndReadFrame();
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}
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return uiLen;
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}
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// requests space in EMAC memory for storing an outgoing frame
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void RequestSend( void )
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{
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unsigned int idx;
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idx = MAC_TXPRODUCEINDEX;
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tptr = ( unsigned short * ) TX_DESC_PACKET( idx );
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}
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// writes a word in little-endian byte order to TX_BUFFER
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void WriteFrame_EMAC( unsigned short Data )
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{
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*tptr++ = Data;
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}
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// copies bytes from MCU-memory to frame port
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// NOTES: * an odd number of byte may only be transfered
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// if the frame is written to the end!
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// * MCU-memory MUST start at word-boundary
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void CopyToFrame_EMAC( void *Source, unsigned int Size )
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{
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unsigned short *piSource;
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piSource = Source;
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Size = ( Size + 1 ) & 0xFFFE; // round Size up to next even number
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while( Size > 0 )
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{
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WriteFrame_EMAC( *piSource++ );
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Size -= 2;
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}
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}
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void DoSend_EMAC( unsigned short FrameSize )
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{
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unsigned int idx;
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idx = MAC_TXPRODUCEINDEX;
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TX_DESC_CTRL( idx ) = FrameSize | TCTRL_LAST;
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if( ++idx == NUM_TX_FRAG )
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{
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idx = 0;
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}
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MAC_TXPRODUCEINDEX = idx;
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}
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void vEMAC_ISR( void )
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{
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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/* Clear the interrupt. */
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MAC_INTCLEAR = 0xffff;
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/* Ensure the uIP task is not blocked as data has arrived. */
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xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
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portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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}
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