Add register test tasks to QEMU project (#765)
* Add register test tasks to the CORTEX_MPS2_QEMU_IAR GCC and IAR builds. * Update header comment in the two added files. * Fix header checks * Fix build issue * update IAR version --------- Co-authored-by: none <> Co-authored-by: Rahul Kar <karahulx@amazon.com> Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>pull/1039/head^2
RichardBarry
12 months ago
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GitHub
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/*
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* FreeRTOS V202212.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* "Reg test" tasks - These fill the registers with known values, then check
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* that each register maintains its expected value for the lifetime of the
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* task. Each task uses a different set of values. The reg test tasks execute
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* with a very low priority, so get preempted very frequently. A register
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* containing an unexpected value is indicative of an error in the context
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* switching mechanism.
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*/
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void vRegTest1Implementation( void ) __attribute__ ((naked));
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void vRegTest2Implementation( void ) __attribute__ ((naked));
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void vRegTest1Implementation( void )
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{
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__asm volatile
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(
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".extern ulRegTest1LoopCounter \n"
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/* Fill the core registers with known values. */
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"mov r0, #100 \n"
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"mov r1, #101 \n"
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"mov r2, #102 \n"
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"mov r3, #103 \n"
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"mov r4, #104 \n"
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"mov r5, #105 \n"
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"mov r6, #106 \n"
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"mov r7, #107 \n"
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"mov r8, #108 \n"
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"mov r9, #109 \n"
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"mov r10, #110 \n"
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"mov r11, #111 \n"
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"mov r12, #112 \n"
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"reg1_loop: \n"
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"cmp r0, #100 \n"
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"bne reg1_error_loop \n"
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"cmp r1, #101 \n"
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"bne reg1_error_loop \n"
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"cmp r2, #102 \n"
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"bne reg1_error_loop \n"
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"cmp r3, #103 \n"
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"bne reg1_error_loop \n"
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"cmp r4, #104 \n"
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"bne reg1_error_loop \n"
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"cmp r5, #105 \n"
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"bne reg1_error_loop \n"
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"cmp r6, #106 \n"
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"bne reg1_error_loop \n"
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"cmp r7, #107 \n"
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"bne reg1_error_loop \n"
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"cmp r8, #108 \n"
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"bne reg1_error_loop \n"
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"cmp r9, #109 \n"
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"bne reg1_error_loop \n"
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"cmp r10, #110 \n"
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"bne reg1_error_loop \n"
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"cmp r11, #111 \n"
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"bne reg1_error_loop \n"
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"cmp r12, #112 \n"
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"bne reg1_error_loop \n"
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/* Everything passed, increment the loop counter. */
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"push { r0-r1 } \n"
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"ldr r0, =ulRegTest1LoopCounter \n"
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"ldr r1, [r0] \n"
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"adds r1, r1, #1 \n"
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"str r1, [r0] \n"
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"pop { r0-r1 } \n"
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/* Start again. */
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"b reg1_loop \n"
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"reg1_error_loop: \n"
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/* If this line is hit then there was an error in a core register value.
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The loop ensures the loop counter stops incrementing. */
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"b reg1_error_loop \n"
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"nop \n"
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); /* __asm volatile. */
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}
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/*-----------------------------------------------------------*/
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void vRegTest2Implementation( void )
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{
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__asm volatile
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(
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".extern ulRegTest2LoopCounter \n"
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/* Set all the core registers to known values. */
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"mov r0, #-1 \n"
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"mov r1, #1 \n"
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"mov r2, #2 \n"
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"mov r3, #3 \n"
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"mov r4, #4 \n"
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"mov r5, #5 \n"
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"mov r6, #6 \n"
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"mov r7, #7 \n"
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"mov r8, #8 \n"
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"mov r9, #9 \n"
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"mov r10, #10 \n"
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"mov r11, #11 \n"
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"mov r12, #12 \n"
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"reg2_loop : \n"
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"cmp r0, #-1 \n"
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"bne reg2_error_loop \n"
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"cmp r1, #1 \n"
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"bne reg2_error_loop \n"
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"cmp r2, #2 \n"
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"bne reg2_error_loop \n"
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"cmp r3, #3 \n"
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"bne reg2_error_loop \n"
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"cmp r4, #4 \n"
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"bne reg2_error_loop \n"
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"cmp r5, #5 \n"
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"bne reg2_error_loop \n"
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"cmp r6, #6 \n"
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"bne reg2_error_loop \n"
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"cmp r7, #7 \n"
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"bne reg2_error_loop \n"
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"cmp r8, #8 \n"
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"bne reg2_error_loop \n"
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"cmp r9, #9 \n"
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"bne reg2_error_loop \n"
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"cmp r10, #10 \n"
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"bne reg2_error_loop \n"
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"cmp r11, #11 \n"
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"bne reg2_error_loop \n"
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"cmp r12, #12 \n"
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"bne reg2_error_loop \n"
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/* Increment the loop counter to indicate this test is still functioning
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correctly. */
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"push { r0-r1 } \n"
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"ldr r0, =ulRegTest2LoopCounter \n"
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"ldr r1, [r0] \n"
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"adds r1, r1, #1 \n"
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"str r1, [r0] \n"
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/* Yield to increase test coverage. */
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"movs r0, #0x01 \n"
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"ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */
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"lsl r0, r0, #28 \n" /* Shift to PendSV bit */
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"str r0, [r1] \n"
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"dsb \n"
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"pop { r0-r1 } \n"
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/* Start again. */
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"b reg2_loop \n"
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"reg2_error_loop: \n"
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/* If this line is hit then there was an error in a core register value.
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This loop ensures the loop counter variable stops incrementing. */
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"b reg2_error_loop \n"
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); /* __asm volatile */
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}
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/*-----------------------------------------------------------*/
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@ -0,0 +1,181 @@
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/*
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* FreeRTOS V202212.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
|
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#include <FreeRTOSConfig.h>
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RSEG CODE:CODE(2)
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thumb
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EXTERN ulRegTest1LoopCounter
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EXTERN ulRegTest2LoopCounter
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PUBLIC vRegTest1Implementation
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PUBLIC vRegTest2Implementation
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/*-----------------------------------------------------------*/
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vRegTest1Implementation
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/* Fill the core registers with known values. */
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mov r0, #100
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mov r1, #101
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mov r2, #102
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mov r3, #103
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mov r4, #104
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mov r5, #105
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mov r6, #106
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mov r7, #107
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mov r8, #108
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mov r9, #109
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mov r10, #110
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mov r11, #111
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mov r12, #112
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reg1_loop:
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cmp r0, #100
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bne reg1_error_loop
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cmp r1, #101
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bne reg1_error_loop
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cmp r2, #102
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bne reg1_error_loop
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cmp r3, #103
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bne reg1_error_loop
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cmp r4, #104
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bne reg1_error_loop
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cmp r5, #105
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bne reg1_error_loop
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cmp r6, #106
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bne reg1_error_loop
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cmp r7, #107
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bne reg1_error_loop
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cmp r8, #108
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bne reg1_error_loop
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cmp r9, #109
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bne reg1_error_loop
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cmp r10, #110
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bne reg1_error_loop
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cmp r11, #111
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bne reg1_error_loop
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cmp r12, #112
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bne reg1_error_loop
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/* Everything passed, increment the loop counter. */
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push { r0-r1 }
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ldr r0, =ulRegTest1LoopCounter
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ldr r1, [r0]
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adds r1, r1, #1
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str r1, [r0]
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pop { r0-r1 }
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/* Start again. */
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b reg1_loop
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reg1_error_loop:
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/* If this line is hit then there was an error in a core register value.
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The loop ensures the loop counter stops incrementing. */
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b reg1_error_loop
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/*-----------------------------------------------------------*/
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vRegTest2Implementation
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/* Set all the core registers to known values. */
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mov r0, #-1
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mov r1, #1
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mov r2, #2
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mov r3, #3
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mov r4, #4
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mov r5, #5
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mov r6, #6
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mov r7, #7
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mov r8, #8
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mov r9, #9
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mov r10, #10
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mov r11, #11
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mov r12, #12
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reg2_loop:
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cmp r0, #-1
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bne reg2_error_loop
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cmp r1, #1
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bne reg2_error_loop
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cmp r2, #2
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bne reg2_error_loop
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cmp r3, #3
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bne reg2_error_loop
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cmp r4, #4
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bne reg2_error_loop
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cmp r5, #5
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bne reg2_error_loop
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cmp r6, #6
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bne reg2_error_loop
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cmp r7, #7
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bne reg2_error_loop
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cmp r8, #8
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bne reg2_error_loop
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cmp r9, #9
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bne reg2_error_loop
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cmp r10, #10
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bne reg2_error_loop
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cmp r11, #11
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bne reg2_error_loop
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cmp r12, #12
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bne reg2_error_loop
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/* Increment the loop counter to indicate this test is still functioning
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correctly. */
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push { r0-r1 }
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ldr r0, =ulRegTest2LoopCounter
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ldr r1, [r0]
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adds r1, r1, #1
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str r1, [r0]
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/* Yield to increase test coverage. */
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movs r0, #0x01
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ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
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lsl r0, r0, #28 /* Shift to PendSV bit */
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str r0, [r1]
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dsb
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pop { r0-r1 }
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/* Start again. */
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b reg2_loop
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reg2_error_loop:
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/* If this line is hit then there was an error in a core register value.
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This loop ensures the loop counter variable stops incrementing. */
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b reg2_error_loop
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/*-----------------------------------------------------------*/
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END
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