diff --git a/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h b/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h new file mode 100644 index 0000000000..7d6cf4cc86 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h @@ -0,0 +1,110 @@ +/* + FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS books - available as PDF or paperback * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( 32000000UL ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255 +(lowest) to 0 (1?) (highest). */ +#define configKERNEL_INTERRUPT_PRIORITY 255 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */ + + +/* This is the value being used as per the ST library which permits 16 +priority values, 0 to 15. This must correspond to the +configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest +NVIC value of 255. */ +#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/Demo/Cortex_STM32L152_IAR/ParTest.c b/Demo/Cortex_STM32L152_IAR/ParTest.c new file mode 100644 index 0000000000..3009d685e0 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/ParTest.c @@ -0,0 +1,147 @@ +/* + FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS books - available as PDF or paperback * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* ST library functions. */ +#include "stm32l152_eval.h" + +#define partstMAX_OUTPUT_LED 4 + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + STM_EVAL_LEDInit( LED1 ); + STM_EVAL_LEDInit( LED2 ); + STM_EVAL_LEDInit( LED3 ); + STM_EVAL_LEDInit( LED4 ); + STM_EVAL_LEDOff( LED1 ); + STM_EVAL_LEDOff( LED2 ); + STM_EVAL_LEDOff( LED3 ); + STM_EVAL_LEDOff( LED4 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + vTaskSuspendAll(); + { + if( xValue != pdFALSE ) + { + switch( uxLED ) + { + case 0: STM_EVAL_LEDOn( LED1 ); + break; + + case 1: STM_EVAL_LEDOn( LED2 ); + break; + + case 2: STM_EVAL_LEDOn( LED3 ); + break; + + case 3: STM_EVAL_LEDOn( LED4 ); + break; + } + } + else + { + switch( uxLED ) + { + case 0: STM_EVAL_LEDOff( LED1 ); + break; + + case 1: STM_EVAL_LEDOff( LED2 ); + break; + + case 2: STM_EVAL_LEDOff( LED3 ); + break; + + case 3: STM_EVAL_LEDOff( LED4 ); + break; + } + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 0: STM_EVAL_LEDToggle( LED1 ); + break; + + case 1: STM_EVAL_LEDToggle( LED2 ); + break; + + case 2: STM_EVAL_LEDToggle( LED3 ); + break; + + case 3: STM_EVAL_LEDToggle( LED4 ); + break; + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd new file mode 100644 index 0000000000..8745728d26 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd @@ -0,0 +1,1683 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 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+ + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp new file mode 100644 index 0000000000..3da15ae98f --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp @@ -0,0 +1,1807 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + 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$PROJ_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.c + + + + Peripheral_Library + + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\misc.c + + + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c + + + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c + + + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c + + + $PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c + + + + $PROJ_DIR$\system_and_ST_code\startup_stm32l1xx_md.s + + + $PROJ_DIR$\system_and_ST_code\stm32l1xx_it.c + + + $PROJ_DIR$\system_and_ST_code\system_stm32l1xx.c + + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest.c + + + + diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.eww b/Demo/Cortex_STM32L152_IAR/RTOSDemo.eww new file mode 100644 index 0000000000..239a9381ec --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/Demo/Cortex_STM32L152_IAR/main.c b/Demo/Cortex_STM32L152_IAR/main.c new file mode 100644 index 0000000000..06476f6485 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/main.c @@ -0,0 +1,220 @@ +/* + FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS books - available as PDF or paperback * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" + +/* ST driver includes. */ +#include "stm32l1xx_usart.h" + +/* Eval board includes. */ +#include "stm32_eval.h" +#include "stm32l152_eval_lcd.h" + +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +#define mainLCD_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) + +#define mainQUEUE_LENGTH ( 5 ) + +#define mainMESSAGE_BUTTON_UP ( 1 ) +#define mainMESSAGE_BUTTON_DOWN ( 2 ) +#define mainMESSAGE_BUTTON_LEFT ( 3 ) +#define mainMESSAGE_BUTTON_RIGHT ( 4 ) +#define mainMESSAGE_BUTTON_SEL ( 5 ) + +/* + * System configuration is performed prior to main() being called, this function + * configures the peripherals used by the demo application. + */ +static void prvSetupHardware( void ); +static void prvLCDTask( void *pvParameters ); +static void vTempTask( void *pv ); + +static xQueueHandle xLCDQueue = NULL; + +typedef struct +{ + char cMessageID; + long lMessageValue; +} xQueueMessage; + +void main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by tasks and interrupts to send strings to the LCD + task. */ + xLCDQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( xQueueMessage ) ); + + if( xLCDQueue != NULL ) + { + xTaskCreate( prvLCDTask, ( signed char * ) "LCD", mainLCD_TASK_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vTempTask, ( signed char * ) "Temp", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + } + + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + + vTaskStartScheduler(); + + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDTask( void *pvParameters ) +{ +xQueueMessage xReceivedMessage; +long lLine = Line1; +const long lFontHeight = (((sFONT *)LCD_GetFont())->Height); +static char cBuffer[ 32 ]; + + for( ;; ) + { + xQueueReceive( xLCDQueue, &xReceivedMessage, portMAX_DELAY ); + + if( lLine >= Line9 ) + { + LCD_Clear( Blue ); + lLine = 0; + } + + switch( xReceivedMessage.cMessageID ) + { + case mainMESSAGE_BUTTON_UP : sprintf( cBuffer, "Button up = %d", xReceivedMessage.lMessageValue ); + break; + case mainMESSAGE_BUTTON_DOWN : + break; + case mainMESSAGE_BUTTON_LEFT : + break; + case mainMESSAGE_BUTTON_RIGHT : + break; + case mainMESSAGE_BUTTON_SEL : + break; + default : sprintf( cBuffer, "Unknown message" ); + break; + } + + LCD_DisplayStringLine( lLine, ( uint8_t * ) cBuffer ); + lLine += lFontHeight; + } +} +/*-----------------------------------------------------------*/ + +static void vTempTask( void *pv ) +{ +long lLastState = pdFALSE; +long lState; +xQueueMessage xMessage; + + for( ;; ) + { + lState = STM_EVAL_PBGetState( BUTTON_UP ); + if( lState != lLastState ) + { + xMessage.cMessageID = mainMESSAGE_BUTTON_UP; + xMessage.lMessageValue = lState; + lLastState = lState; + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); + vTaskDelay( 10 ); + } + } + +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Initialise the LEDs. */ + vParTestInitialise(); + + //BUTTON_MODE_EXTI + /* Initialise the joystick inputs. */ + STM_EVAL_PBInit( BUTTON_UP, BUTTON_MODE_GPIO ); + STM_EVAL_PBInit( BUTTON_DOWN, BUTTON_MODE_GPIO ); + STM_EVAL_PBInit( BUTTON_LEFT, BUTTON_MODE_GPIO ); + STM_EVAL_PBInit( BUTTON_RIGHT, BUTTON_MODE_GPIO ); + STM_EVAL_PBInit( BUTTON_SEL, BUTTON_MODE_GPIO ); + +#if 0 +USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit( COM1, &USART_InitStructure ); +#endif + + /* Initialize the LCD */ + STM32L152_LCD_Init(); + + LCD_Clear(Blue); + LCD_SetBackColor(Blue); + LCD_SetTextColor(White); + LCD_DisplayStringLine(Line0, " www.FreeRTOS.org"); +} +/*-----------------------------------------------------------*/ + diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat new file mode 100644 index 0000000000..1f8369b138 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat @@ -0,0 +1,15 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM + + +"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32l152xx.ddf" "--semihosting" "--device=STM32L152xB" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" + + diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 0000000000..8d1124e4ec --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,84 @@ + + + + + + + + + 201622 + + 20 + 1216 + 324 + 81 + + + + + + + + 295272727 + + + + 2 + 0 + 0 + + + 1 + 1 + 1 + + 200100100100100200208100100100 + + + + + + + TabID-4782-21358 + Debug Log + Debug-Log + + + + TabID-4259-21368 + Build + Build + + + + + 0 + + + TabID-15530-21362 + Workspace + Workspace + + + RTOSDemoRTOSDemo/System_and_ST_Code + + + + 0 + + + + + + TextEditor$WS_DIR$\main.c029114711470TextEditor$WS_DIR$\FreeRTOSConfig.h04836633663TextEditor$WS_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval.c03031157911579TextEditor$WS_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.c05151720817208TextEditor$WS_DIR$\system_and_ST_code\stm32_eval.h02891082210832TextEditor$WS_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.h026086418651TextEditor$WS_DIR$\system_and_ST_code\Common\fonts.h050161716510100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1armjlink.enu1-2-2716369-2-2200200119048203666220833731161-2-21981682-2-216842001002381203666119048203666 + + + + diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni new file mode 100644 index 0000000000..241c15162d --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni @@ -0,0 +1,64 @@ +[DebugChecksum] +Checksum=1807629591 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[InstructionProfiling] +Enabled=_ 0 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[Exceptions] +StopOnUncaught=_ 0 +StopOnThrow=_ 0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[InterruptLog] +LogEnabled=0 +SumEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +ShowTimeSum=1 +SumSortOrder=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[TraceHelper] +Enabled=0 +ShowSource=1 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[CallStackLog] +Enabled=0 +[DriverProfiling] +Enabled=0 +Mode=995247177 +Graph=0 +Symbiont=0 +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 0000000000..af878919cf --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,49 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 211272727 + + 20121632481201622 + + + + + + TabID-27630-4718 + Workspace + Workspace + + + RTOSDemoRTOSDemo/System_and_ST_CodeRTOSDemo/System_and_ST_Code/Eval_Board_LibraryRTOSDemo/System_and_ST_Code/Peripheral_Library + + + + 0TabID-10002-7709BuildBuildTabID-18437-21512Debug LogDebug-Log0 + + + + + + TextEditor$WS_DIR$\main.c0113083308300100000010000001 + + + + + + + iaridepm.enu1-2-2740285-2-2200200119048203666170833755601-2-21981682-2-216842001002381203666119048203666 + + + + diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink new file mode 100644 index 0000000000..228ff82244 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink @@ -0,0 +1,23 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ADUC7020X62" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +[SWO] +SWOLogFile="" diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c new file mode 100644 index 0000000000..d45111bedd --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c @@ -0,0 +1,996 @@ +/** + ****************************************************************************** + * @file fonts.c + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief This file provides text fonts for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file includes the Fonts driver of STM32-EVAL boards. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +const uint16_t ASCII16x24_Table [] = { +/** + * @brief Space ' ' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '!' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '"' + */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '#' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, +/** + * @brief '$' + */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '%' + */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, +/** + * @brief '&' + */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '(' + */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, +/** + * @brief ')' + */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, +/** + * @brief '*' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '+' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ',' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, +/** + * @brief '-' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '.' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '/' + */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '0' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '1' + */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '2' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '3' + */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '4' + */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '5' + */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '6' + */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '7' + */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '8' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '9' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ':' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ';' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '<' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '=' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '>' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '?' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '@' + */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'A' + */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'B' + */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'C' + */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'D' + */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'E' + */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'F' + */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'G' + */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'H' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'I' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'J' + */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'K' + */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'L' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'M' + */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'N' + */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'O' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'P' + */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Q' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'R' + */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'S' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'T' + */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'U' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'V' + */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'W' + */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'X' + */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Y' + */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Z' + */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '[' + */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '\' + */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ']' + */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '^' + */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '_' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'a' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'b' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'c' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'd' + */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'e' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'f' + */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'g' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, +/** + * @brief 'h' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'i' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'j' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, +/** + * @brief 'k' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'l' + */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'm' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'n' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'o' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'p' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, +/** + * @brief 'q' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, +/** + * @brief 'r' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 's' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 't' + */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'u' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'v' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'w' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'x' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'y' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, +/** + * @brief 'z' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '{' + */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, +/** + * @brief '|' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, +/** + * @brief '}' + */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, +/** + * @brief '~' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; + +const uint16_t ASCII12x12_Table [] = { + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000, + 0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000, + 0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000, + 0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000, + 0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000, + 0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000, + 0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000, + 0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000, + 0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000, + 0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000, + 0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000, + 0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000, + 0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000, + 0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000, + 0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040, + 0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000, + 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000, + 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000, + 0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000, + 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000, + 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000, + 0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000, + 0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000, + 0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000, + 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000, + 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000, + 0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000, + 0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000, + 0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000, + 0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000, + 0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000, + 0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000, + 0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000, + 0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000, + 0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000, + 0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000, + 0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00, + 0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000, + 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000, + 0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400, + 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000, + 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000, + 0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000, + 0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000, + 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400, + 0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000, + 0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000, + 0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000}; + +const uint16_t ASCII8x12_Table [] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00, + 0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00, + 0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10, + 0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00, + 0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, + 0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00, + 0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00, + 0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00, + 0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00, + 0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00, + 0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00, + 0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00, + 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40, + 0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00, + 0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00, + 0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41, + 0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00, + 0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00, + 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00, + 0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00, + 0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00, + 0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00, + 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00, + 0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00, + 0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00, + 0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00, + 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00, + 0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04, + 0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00, + 0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00, + 0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00, + 0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00, + 0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00, + 0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00, + 0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00, + 0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00, + 0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00, + 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00, + 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, + 0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8, + 0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00, + 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00, + 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00, + 0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00, + 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00, + 0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10, + 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00, + 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00, + 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00, + 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80, + 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10, + 0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00, + 0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00, + 0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00, + 0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00, + 0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00, + 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00, + 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20, + 0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00, + 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40, + 0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00}; + +const uint16_t ASCII8x8_Table [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, + 0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48, + 0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38, + 0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24, + 0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30, + 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, + 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, + 0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00, + 0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, + 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20, + 0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18, + 0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c, + 0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18, + 0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04, + 0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18, + 0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18, + 0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, + 0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18, + 0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18, + 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00, + 0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00, + 0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10, + 0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38, + 0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, + 0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78, + 0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c, + 0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70, + 0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c, + 0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20, + 0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c, + 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18, + 0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, + 0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92, + 0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42, + 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, + 0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40, + 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a, + 0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42, + 0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38, + 0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, + 0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10, + 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44, + 0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42, + 0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c, + 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c, + 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, + 0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c, + 0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c, + 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28, + 0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18, + 0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14, + 0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18, + 0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10, + 0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18, + 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24, + 0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10, + 0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92, + 0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24, + 0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18, + 0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20, + 0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04, + 0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20, + 0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18, + 0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18, + 0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14, + 0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10, + 0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44, + 0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44, + 0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, + 0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c, + 0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10, + 0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + +sFONT Font16x24 = { + ASCII16x24_Table, + 16, /* Width */ + 24, /* Height */ +}; + +sFONT Font12x12 = { + ASCII12x12_Table, + 12, /* Width */ + 12, /* Height */ +}; + +sFONT Font8x12 = { + ASCII8x12_Table, + 8, /* Width */ + 12, /* Height */ +}; + + +sFONT Font8x8 = { + ASCII8x8_Table, + 8, /* Width */ + 8, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h new file mode 100644 index 0000000000..00fa116b97 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file fonts.h + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief Header for fonts.c + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FONTS_H +#define __FONTS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @{ + */ + +/** @defgroup FONTS_Exported_Types + * @{ + */ +typedef struct _tFont +{ + const uint16_t *table; + uint16_t Width; + uint16_t Height; + +} sFONT; + +extern sFONT Font16x24; +extern sFONT Font12x12; +extern sFONT Font8x12; +extern sFONT Font8x8; + +/** + * @} + */ + +/** @defgroup FONTS_Exported_Constants + * @{ + */ +#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height)) + +/** + * @} + */ + +/** @defgroup FONTS_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup FONTS_Exported_Functions + * @{ + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FONTS_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c new file mode 100644 index 0000000000..1f087a7c6e --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c @@ -0,0 +1,584 @@ +/** + ****************************************************************************** + * @file stm32l152_eval.c + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief This file provides + * - set of firmware functions to manage Leds, push-button and COM ports + * - low level initialization functions for SD card (on SPI) and + * temperature sensor (LM75) + * available on STM32L152-EVAL evaluation board from STMicroelectronics. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l152_eval.h" +#include "stm32l1xx_spi.h" +#include "stm32l1xx_i2c.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM32L152_EVAL + * @{ + */ + +/** @defgroup STM32L152_EVAL_LOW_LEVEL + * @brief This file provides firmware functions to manage Leds, push-buttons, + * COM ports, SD card on SPI and temperature sensor (LM75) available on + * STM32L152-EVAL evaluation board from STMicroelectronics. + * @{ + */ + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables + * @{ + */ +GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, + LED4_GPIO_PORT}; +const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, + LED4_PIN}; +const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, + LED4_GPIO_CLK}; + +GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, + KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT, + LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, + DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; + +const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, + KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, + LEFT_BUTTON_PIN, UP_BUTTON_PIN, + DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; + +const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, + KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK, + LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, + DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}; + +const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, + TAMPER_BUTTON_EXTI_LINE, + KEY_BUTTON_EXTI_LINE, + RIGHT_BUTTON_EXTI_LINE, + LEFT_BUTTON_EXTI_LINE, + UP_BUTTON_EXTI_LINE, + DOWN_BUTTON_EXTI_LINE, + SEL_BUTTON_EXTI_LINE}; + +const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, + TAMPER_BUTTON_EXTI_PORT_SOURCE, + KEY_BUTTON_EXTI_PORT_SOURCE, + RIGHT_BUTTON_EXTI_PORT_SOURCE, + LEFT_BUTTON_EXTI_PORT_SOURCE, + UP_BUTTON_EXTI_PORT_SOURCE, + DOWN_BUTTON_EXTI_PORT_SOURCE, + SEL_BUTTON_EXTI_PORT_SOURCE}; + +const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, + TAMPER_BUTTON_EXTI_PIN_SOURCE, + KEY_BUTTON_EXTI_PIN_SOURCE, + RIGHT_BUTTON_EXTI_PIN_SOURCE, + LEFT_BUTTON_EXTI_PIN_SOURCE, + UP_BUTTON_EXTI_PIN_SOURCE, + DOWN_BUTTON_EXTI_PIN_SOURCE, + SEL_BUTTON_EXTI_PIN_SOURCE}; + +const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, + KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn, + LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn, + DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}; + +USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; + +GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}; + +GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}; + +const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; + +const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}; + +const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}; + +const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; + +const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; + +const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE}; + +const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE}; + +const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF}; + +const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF}; + +/** + * @} + */ + + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions + * @{ + */ + +/** + * @brief Configures LED GPIO. + * @param Led: Specifies the Led to be configured. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDInit(Led_TypeDef Led) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable the GPIO_LED Clock */ + RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE); + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); + GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; +} + +/** + * @brief Turns selected LED On. + * @param Led: Specifies the Led to be set on. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDOn(Led_TypeDef Led) +{ + GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; +} + +/** + * @brief Turns selected LED Off. + * @param Led: Specifies the Led to be set off. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDOff(Led_TypeDef Led) +{ + GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; +} + +/** + * @brief Toggles the selected LED. + * @param Led: Specifies the Led to be toggled. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDToggle(Led_TypeDef Led) +{ + GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; +} + +/** + * @brief Configures Button GPIO and EXTI Line. + * @param Button: Specifies the Button to be configured. + * This parameter can be one of following parameters: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @arg BUTTON_RIGHT: Joystick Right Push Button + * @arg BUTTON_LEFT: Joystick Left Push Button + * @arg BUTTON_UP: Joystick Up Push Button + * @arg BUTTON_DOWN: Joystick Down Push Button + * @arg BUTTON_SEL: Joystick Sel Push Button + * @param Button_Mode: Specifies Button mode. + * This parameter can be one of following parameters: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt + * generation capability + * @retval None + */ +void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) +{ + GPIO_InitTypeDef GPIO_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable the BUTTON Clock */ + RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure Button pin as input */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; + GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); + + + if (Button_Mode == BUTTON_MODE_EXTI) + { + /* Connect Button EXTI Line to Button GPIO Pin */ + SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); + + /* Configure Button EXTI line */ + EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + + if((Button != BUTTON_WAKEUP) && (Button != BUTTON_KEY) && (Button != BUTTON_TAMPER)) + { + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + } + else + { + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + } + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + + NVIC_Init(&NVIC_InitStructure); + } +} + +/** + * @brief Returns the selected Button state. + * @param Button: Specifies the Button to be checked. + * This parameter can be one of following parameters: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @arg BUTTON_RIGHT: Joystick Right Push Button + * @arg BUTTON_LEFT: Joystick Left Push Button + * @arg BUTTON_UP: Joystick Up Push Button + * @arg BUTTON_DOWN: Joystick Down Push Button + * @arg BUTTON_SEL: Joystick Sel Push Button + * @retval The Button GPIO pin value. + */ +uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) +{ + return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + + +/** + * @brief Configures COM port. + * @param COM: Specifies the COM port to be configured. + * This parameter can be one of following parameters: + * @arg COM1 + * @arg COM2 + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that + * contains the configuration information for the specified USART peripheral. + * @retval None + */ +void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIO clock */ + RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE); + + /* Enable UART clock */ + RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); + + /* Connect PXx to USARTx_Tx*/ + GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]); + + /* Connect PXx to USARTx_Rx*/ + GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]); + + /* Configure USART Tx as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); + + /* Configure USART Rx as input floating */ + GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; + GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); + + /* USART configuration */ + USART_Init(COM_USART[COM], USART_InitStruct); + + /* Enable USART */ + USART_Cmd(COM_USART[COM], ENABLE); +} + +/** + * @brief DeInitializes the SPI interface. + * @param None + * @retval None + */ +void SD_LowLevel_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */ + SPI_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */ + + /*!< SD_SPI Periph clock disable */ + RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); + + /*!< Configure SD_SPI pins: SCK */ + GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI pins: MISO */ + GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; + GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI pins: MOSI */ + GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; + GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ + GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; + GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ + GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; + GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief Initializes the SD Card and put it into StandBy State (Ready for + * data transfer). + * @param None + * @retval None + */ +void SD_LowLevel_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + SPI_InitTypeDef SPI_InitStructure; + + /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO + and SD_SPI_SCK_GPIO Periph clock enable */ + RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK | + SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE); + + /*!< SD_SPI Periph clock enable */ + RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); + + /*!< Configure SD_SPI pins: SCK */ + GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI pins: MISO */ + GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; + GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI pins: MOSI */ + GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; + GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ + GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ + GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PXx to SD_SPI_SCK */ + GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF); + + /* Connect PXx to SD_SPI_MISO */ + GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); + + /* Connect PXx to SD_SPI_MOSI */ + GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF); + + /*!< SD_SPI Config */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(SD_SPI, &SPI_InitStructure); + + SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ +} + +/** + * @brief DeInitializes the LM75_I2C. + * @param None + * @retval None + */ +void LM75_LowLevel_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< Disable LM75_I2C */ + I2C_Cmd(LM75_I2C, DISABLE); + + /*!< DeInitializes the LM75_I2C */ + I2C_DeInit(LM75_I2C); + + /*!< LM75_I2C Periph clock disable */ + RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE); + + /*!< Configure LM75_I2C pins: SCL */ + GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure LM75_I2C pins: SDA */ + GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; + GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure LM75_I2C pin: SMBUS ALERT */ + GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; + GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief Initializes the LM75_I2C. + * @param None + * @retval None + */ +void LM75_LowLevel_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< LM75_I2C Periph clock enable */ + RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE); + + /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK + and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */ + RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK | + LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE); + + /*!< Configure LM75_I2C pins: SCL */ + GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure LM75_I2C pins: SDA */ + GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; + GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure LM75_I2C pin: SMBUS ALERT */ + GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; + GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); + + + /* Connect PXx to I2C_SCL */ + GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF); + + /* Connect PXx to I2C_SDA */ + GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); + + /* Connect PXx to I2C_SMBUSALER */ + GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h new file mode 100644 index 0000000000..56df0fb136 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h @@ -0,0 +1,337 @@ +/** + ****************************************************************************** + * @file stm32l152_eval.h + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief This file contains definitions for STM32L152_EVAL's Leds, push-buttons + * and COM ports hardware resources. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L152_EVAL_H +#define __STM32L152_EVAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM32L152_EVAL + * @{ + */ + +/** @addtogroup STM32L152_EVAL_LOW_LEVEL + * @{ + */ + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants + * @{ + */ + +/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED + * @{ + */ +#define LEDn 4 + +#define LED1_PIN GPIO_Pin_0 +#define LED1_GPIO_PORT GPIOD +#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOD + +#define LED2_PIN GPIO_Pin_1 +#define LED2_GPIO_PORT GPIOD +#define LED2_GPIO_CLK RCC_AHBPeriph_GPIOD + +#define LED3_PIN GPIO_Pin_4 +#define LED3_GPIO_PORT GPIOD +#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOD + +#define LED4_PIN GPIO_Pin_5 +#define LED4_GPIO_PORT GPIOD +#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOD + +/** + * @} + */ + +/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON + * @{ + */ +#define BUTTONn 8 + +/** + * @brief Wakeup push-button + */ +#define WAKEUP_BUTTON_PIN GPIO_Pin_13 +#define WAKEUP_BUTTON_GPIO_PORT GPIOC +#define WAKEUP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC +#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line13 +#define WAKEUP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC +#define WAKEUP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13 +#define WAKEUP_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Tamper push-button + */ +#define TAMPER_BUTTON_PIN GPIO_Pin_13 +#define TAMPER_BUTTON_GPIO_PORT GPIOC +#define TAMPER_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC +#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 +#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC +#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13 +#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Key push-button + */ +#define KEY_BUTTON_PIN GPIO_Pin_13 +#define KEY_BUTTON_GPIO_PORT GPIOC +#define KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC +#define KEY_BUTTON_EXTI_LINE EXTI_Line13 +#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC +#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13 +#define KEY_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Joystick Right push-button + */ +#define RIGHT_BUTTON_PIN GPIO_Pin_11 +#define RIGHT_BUTTON_GPIO_PORT GPIOE +#define RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE +#define RIGHT_BUTTON_EXTI_LINE EXTI_Line11 +#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE +#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11 +#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Joystick Left push-button + */ +#define LEFT_BUTTON_PIN GPIO_Pin_12 +#define LEFT_BUTTON_GPIO_PORT GPIOE +#define LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE +#define LEFT_BUTTON_EXTI_LINE EXTI_Line12 +#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE +#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource12 +#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Joystick Up push-button + */ +#define UP_BUTTON_PIN GPIO_Pin_9 +#define UP_BUTTON_GPIO_PORT GPIOE +#define UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE +#define UP_BUTTON_EXTI_LINE EXTI_Line9 +#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE +#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9 +#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn + +/** + * @brief Joystick Down push-button + */ +#define DOWN_BUTTON_PIN GPIO_Pin_10 +#define DOWN_BUTTON_GPIO_PORT GPIOE +#define DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE +#define DOWN_BUTTON_EXTI_LINE EXTI_Line10 +#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE +#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource10 +#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Joystick Sel push-button + */ +#define SEL_BUTTON_PIN GPIO_Pin_8 +#define SEL_BUTTON_GPIO_PORT GPIOE +#define SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE +#define SEL_BUTTON_EXTI_LINE EXTI_Line8 +#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE +#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8 +#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn + +/** + * @} + */ + +/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM + * @{ + */ +#define COMn 2 + +/** + * @brief Definition for COM port1, connected to USART2 + */ +#define EVAL_COM1 USART2 +#define EVAL_COM1_CLK RCC_APB1Periph_USART2 +#define EVAL_COM1_TX_PIN GPIO_Pin_5 +#define EVAL_COM1_TX_GPIO_PORT GPIOD +#define EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOD +#define EVAL_COM1_TX_SOURCE GPIO_PinSource5 +#define EVAL_COM1_TX_AF GPIO_AF_USART2 +#define EVAL_COM1_RX_PIN GPIO_Pin_6 +#define EVAL_COM1_RX_GPIO_PORT GPIOD +#define EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOD +#define EVAL_COM1_RX_SOURCE GPIO_PinSource6 +#define EVAL_COM1_RX_AF GPIO_AF_USART2 +#define EVAL_COM1_IRQn USART2_IRQn + +/** + * @brief Definition for COM port2, connected to USART3 + */ +#define EVAL_COM2 USART3 +#define EVAL_COM2_CLK RCC_APB1Periph_USART3 + +#define EVAL_COM2_TX_PIN GPIO_Pin_10 +#define EVAL_COM2_TX_GPIO_PORT GPIOC +#define EVAL_COM2_TX_GPIO_CLK RCC_AHBPeriph_GPIOC +#define EVAL_COM2_TX_SOURCE GPIO_PinSource10 +#define EVAL_COM2_TX_AF GPIO_AF_USART3 + +#define EVAL_COM2_RX_PIN GPIO_Pin_11 +#define EVAL_COM2_RX_GPIO_PORT GPIOC +#define EVAL_COM2_RX_GPIO_CLK RCC_AHBPeriph_GPIOC +#define EVAL_COM2_RX_SOURCE GPIO_PinSource11 +#define EVAL_COM2_RX_AF GPIO_AF_USART3 +#define EVAL_COM2_IRQn USART3_IRQn + +/** + * @} + */ + +/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH + * @{ + */ +/** + * @brief SD Card SPI Interface + */ +#define SD_SPI SPI2 +#define SD_SPI_CLK RCC_APB1Periph_SPI2 +#define SD_SPI_SCK_PIN GPIO_Pin_13 /* PB.13 */ +#define SD_SPI_SCK_GPIO_PORT GPIOB /* GPIOB */ +#define SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB +#define SD_SPI_SCK_SOURCE GPIO_PinSource13 +#define SD_SPI_SCK_AF GPIO_AF_SPI2 +#define SD_SPI_MISO_PIN GPIO_Pin_14 /* PB.14 */ +#define SD_SPI_MISO_GPIO_PORT GPIOB /* GPIOB */ +#define SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB +#define SD_SPI_MISO_SOURCE GPIO_PinSource14 +#define SD_SPI_MISO_AF GPIO_AF_SPI2 +#define SD_SPI_MOSI_PIN GPIO_Pin_15 /* PB.15 */ +#define SD_SPI_MOSI_GPIO_PORT GPIOB /* GPIOB */ +#define SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB +#define SD_SPI_MOSI_SOURCE GPIO_PinSource15 +#define SD_SPI_MOSI_AF GPIO_AF_SPI2 +#define SD_CS_PIN GPIO_Pin_7 /* PD.07 */ +#define SD_CS_GPIO_PORT GPIOD /* GPIOD */ +#define SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOD +#define SD_DETECT_PIN GPIO_Pin_7 /* PE.07 */ +#define SD_DETECT_GPIO_PORT GPIOE /* GPIOE */ +#define SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOE +/** + * @} + */ + +/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C + * @{ + */ +/** + * @brief LM75 Temperature Sensor I2C Interface pins + */ +#define LM75_I2C I2C1 +#define LM75_I2C_CLK RCC_APB1Periph_I2C1 +#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ +#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ +#define LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB +#define LM75_I2C_SCL_SOURCE GPIO_PinSource6 +#define LM75_I2C_SCL_AF GPIO_AF_I2C1 +#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ +#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ +#define LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB +#define LM75_I2C_SDA_SOURCE GPIO_PinSource7 +#define LM75_I2C_SDA_AF GPIO_AF_I2C1 +#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */ +#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */ +#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB +#define LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5 +#define LM75_I2C_SMBUSALERT_AF GPIO_AF_I2C1 +/** + * @} + */ +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions + * @{ + */ +void STM_EVAL_LEDInit(Led_TypeDef Led); +void STM_EVAL_LEDOn(Led_TypeDef Led); +void STM_EVAL_LEDOff(Led_TypeDef Led); +void STM_EVAL_LEDToggle(Led_TypeDef Led); +void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); +uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); +void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); +void SD_LowLevel_DeInit(void); +void SD_LowLevel_Init(void); +void LM75_LowLevel_DeInit(void); +void LM75_LowLevel_Init(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L152_EVAL_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c new file mode 100644 index 0000000000..8c3f05a823 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c @@ -0,0 +1,1528 @@ +/** + ****************************************************************************** + * @file stm32l152_eval_lcd.c + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), + * AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module + * of STM32L152-EVAL board. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l152_eval_lcd.h" +#include "../Common/fonts.c" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM32L152_EVAL + * @{ + */ + +/** @defgroup STM32L152_EVAL_LCD + * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), + * AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module + * of STM32L152-EVAL board. + * @{ + */ + +/** @defgroup STM32L152_EVAL_LCD_Private_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Private_Defines + * @{ + */ +#define LCD_ILI9320 0x9320 +#define LCD_SPFD5408 0x5408 +#define START_BYTE 0x70 +#define SET_INDEX 0x00 +#define READ_STATUS 0x01 +#define LCD_WRITE_REG 0x02 +#define LCD_READ_REG 0x03 +#define MAX_POLY_CORNERS 200 +#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) +#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Private_Macros + * @{ + */ +#define ABS(X) ((X) > 0 ? (X) : -(X)) +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Private_Variables + * @{ + */ +static sFONT *LCD_Currentfonts; +/* Global variables to set the written text color */ +static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; +static __IO uint32_t LCDType = LCD_SPFD5408; +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes + * @{ + */ +#ifndef USE_Delay +static void delay(__IO uint32_t nCount); +#endif /* USE_Delay*/ + +static void PutPixel(int16_t x, int16_t y); +static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); + +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Private_Functions + * @{ + */ + +/** + * @brief DeInitializes the LCD. + * @param None + * @retval None + */ +void STM32L152_LCD_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< LCD Display Off */ + LCD_DisplayOff(); + + /*!< LCD_SPI disable */ + SPI_Cmd(LCD_SPI, DISABLE); + + /*!< LCD_SPI DeInit */ + SPI_DeInit(LCD_SPI); + + /*!< Disable SPI clock */ + RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE); + + /* Configure NCS in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); + + /* Configure SPI pins: SCK, MISO and MOSI */ + GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; + GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; + GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; + GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief Setups the LCD. + * @param None + * @retval None + */ +void LCD_Setup(void) +{ +/* Configure the LCD Control pins --------------------------------------------*/ + LCD_CtrlLinesConfig(); + +/* Configure the LCD_SPI interface ----------------------------------------------*/ + LCD_SPIConfig(); + + if(LCDType == LCD_SPFD5408) + { + /* Start Initial Sequence --------------------------------------------------*/ + LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */ + LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */ + LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */ + LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ + LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ + LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ + LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ + LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + /* Power On sequence -------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ + LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ + LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */ + /* Adjust the Gamma Curve --------------------------------------------------*/ + LCD_WriteReg(LCD_REG_48, 0x0007); + LCD_WriteReg(LCD_REG_49, 0x0302); + LCD_WriteReg(LCD_REG_50, 0x0105); + LCD_WriteReg(LCD_REG_53, 0x0206); + LCD_WriteReg(LCD_REG_54, 0x0808); + LCD_WriteReg(LCD_REG_55, 0x0206); + LCD_WriteReg(LCD_REG_56, 0x0504); + LCD_WriteReg(LCD_REG_57, 0x0007); + LCD_WriteReg(LCD_REG_60, 0x0105); + LCD_WriteReg(LCD_REG_61, 0x0808); + /* Set GRAM area -----------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ + LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ + LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */ + LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */ + /* Partial Display Control -------------------------------------------------*/ + LCD_WriteReg(LCD_REG_128, 0x0000); + LCD_WriteReg(LCD_REG_129, 0x0000); + LCD_WriteReg(LCD_REG_130, 0x0000); + LCD_WriteReg(LCD_REG_131, 0x0000); + LCD_WriteReg(LCD_REG_132, 0x0000); + LCD_WriteReg(LCD_REG_133, 0x0000); + /* Panel Control -----------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_144, 0x0010); + LCD_WriteReg(LCD_REG_146, 0x0000); + LCD_WriteReg(LCD_REG_147, 0x0003); + LCD_WriteReg(LCD_REG_149, 0x0110); + LCD_WriteReg(LCD_REG_151, 0x0000); + LCD_WriteReg(LCD_REG_152, 0x0000); + /* Set GRAM write direction and BGR = 1 + I/D=01 (Horizontal : increment, Vertical : decrement) + AM=1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1018); + LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */ + } + else if(LCDType == LCD_ILI9320) + { + _delay_(5); /* Delay 50 ms */ + /* Start Initial Sequence ------------------------------------------------*/ + LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ + LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ + LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ + LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ + LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ + LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ + LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ + LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ + LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ + LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + /* Power On sequence -----------------------------------------------------*/ + LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ + LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + /* Adjust the Gamma Curve ------------------------------------------------*/ + LCD_WriteReg(LCD_REG_48, 0x0006); + LCD_WriteReg(LCD_REG_49, 0x0101); + LCD_WriteReg(LCD_REG_50, 0x0003); + LCD_WriteReg(LCD_REG_53, 0x0106); + LCD_WriteReg(LCD_REG_54, 0x0b02); + LCD_WriteReg(LCD_REG_55, 0x0302); + LCD_WriteReg(LCD_REG_56, 0x0707); + LCD_WriteReg(LCD_REG_57, 0x0007); + LCD_WriteReg(LCD_REG_60, 0x0600); + LCD_WriteReg(LCD_REG_61, 0x020b); + + /* Set GRAM area ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ + LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ + LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ + /* Partial Display Control -----------------------------------------------*/ + LCD_WriteReg(LCD_REG_128, 0x0000); + LCD_WriteReg(LCD_REG_129, 0x0000); + LCD_WriteReg(LCD_REG_130, 0x0000); + LCD_WriteReg(LCD_REG_131, 0x0000); + LCD_WriteReg(LCD_REG_132, 0x0000); + LCD_WriteReg(LCD_REG_133, 0x0000); + /* Panel Control ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_144, 0x0010); + LCD_WriteReg(LCD_REG_146, 0x0000); + LCD_WriteReg(LCD_REG_147, 0x0003); + LCD_WriteReg(LCD_REG_149, 0x0110); + LCD_WriteReg(LCD_REG_151, 0x0000); + LCD_WriteReg(LCD_REG_152, 0x0000); + /* Set GRAM write direction and BGR = 1 */ + /* I/D=01 (Horizontal : increment, Vertical : decrement) */ + /* AM=1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1018); + LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ + } +} + + +/** + * @brief Initializes the LCD. + * @param None + * @retval None + */ +void STM32L152_LCD_Init(void) +{ + /* Setups the LCD */ + LCD_Setup(); + + /* Try to read new LCD controller ID 0x5408 */ + if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408) + { + LCDType = LCD_SPFD5408; + } + else + { + LCDType = LCD_ILI9320; + /* Setups the LCD */ + LCD_Setup(); + } + + LCD_SetFont(&LCD_DEFAULT_FONT); +} + +/** + * @brief Sets the LCD Text and Background colors. + * @param _TextColor: specifies the Text Color. + * @param _BackColor: specifies the Background Color. + * @retval None + */ +void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) +{ + TextColor = _TextColor; + BackColor = _BackColor; +} + +/** + * @brief Gets the LCD Text and Background colors. + * @param _TextColor: pointer to the variable that will contain the Text + Color. + * @param _BackColor: pointer to the variable that will contain the Background + Color. + * @retval None + */ +void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) +{ + *_TextColor = TextColor; *_BackColor = BackColor; +} + +/** + * @brief Sets the Text color. + * @param Color: specifies the Text color code RGB(5-6-5). + * @retval None + */ +void LCD_SetTextColor(__IO uint16_t Color) +{ + TextColor = Color; +} + + +/** + * @brief Sets the Background color. + * @param Color: specifies the Background color code RGB(5-6-5). + * @retval None + */ +void LCD_SetBackColor(__IO uint16_t Color) +{ + BackColor = Color; +} + +/** + * @brief Sets the Text Font. + * @param fonts: specifies the font to be used. + * @retval None + */ +void LCD_SetFont(sFONT *fonts) +{ + LCD_Currentfonts = fonts; +} + +/** + * @brief Gets the Text Font. + * @param None. + * @retval the used font. + */ +sFONT *LCD_GetFont(void) +{ + return LCD_Currentfonts; +} + +/** + * @brief Clears the selected line. + * @param Line: the Line to be cleared. + * This parameter can be one of the following values: + * @arg Linex: where x can be 0..n + * @retval None + */ +void LCD_ClearLine(uint8_t Line) +{ + uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; + + /* Send the string character by character on lCD */ + while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, ' '); + /* Decrement the column position by 16 */ + refcolumn -= LCD_Currentfonts->Width; + } +} + + +/** + * @brief Clears the hole LCD. + * @param Color: the color of the background. + * @retval None + */ +void LCD_Clear(uint16_t Color) +{ + uint32_t index = 0; + + LCD_SetCursor(0x00, 0x013F); + + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + + for(index = 0; index < 76800; index++) + { + LCD_WriteRAM(Color); + } + + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); + +} + + +/** + * @brief Sets the cursor position. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @retval None + */ +void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) +{ + LCD_WriteReg(LCD_REG_32, Xpos); + LCD_WriteReg(LCD_REG_33, Ypos); +} + + +/** + * @brief Draws a character on LCD. + * @param Xpos: the Line where to display the character shape. + * @param Ypos: start column address. + * @param c: pointer to the character data. + * @retval None + */ +void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) +{ + uint32_t index = 0, i = 0; + uint8_t Xaddress = 0; + + Xaddress = Xpos; + + LCD_SetCursor(Xaddress, Ypos); + + for(index = 0; index < LCD_Currentfonts->Height; index++) + { + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + + for(i = 0; i < LCD_Currentfonts->Width; i++) + { + if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| + (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) + + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); + Xaddress++; + LCD_SetCursor(Xaddress, Ypos); + } +} + + +/** + * @brief Displays one character (16dots width, 24dots height). + * @param Line: the Line where to display the character shape . + * This parameter can be one of the following values: + * @arg Linex: where x can be 0..9 + * @param Column: start column address. + * @param Ascii: character ascii code, must be between 0x20 and 0x7E. + * @retval None + */ +void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) +{ + Ascii -= 32; + LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); +} + + +/** + * @brief Displays a maximum of 20 char on the LCD. + * @param Line: the Line where to display the character shape . + * This parameter can be one of the following values: + * @arg Linex: where x can be 0..9 + * @param *ptr: pointer to string to display on LCD. + * @retval None + */ +void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) +{ + uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; + + /* Send the string character by character on lCD */ + while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + /* Decrement the column position by 16 */ + refcolumn -= LCD_Currentfonts->Width; + /* Point on the next character */ + ptr++; + } +} + + +/** + * @brief Sets a display window + * @param Xpos: specifies the X buttom left position. + * @param Ypos: specifies the Y buttom left position. + * @param Height: display window height. + * @param Width: display window width. + * @retval None + */ +void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) +{ + /* Horizontal GRAM Start Address */ + if(Xpos >= Height) + { + LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); + } + else + { + LCD_WriteReg(LCD_REG_80, 0); + } + /* Horizontal GRAM End Address */ + LCD_WriteReg(LCD_REG_81, Xpos); + /* Vertical GRAM Start Address */ + if(Ypos >= Width) + { + LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); + } + else + { + LCD_WriteReg(LCD_REG_82, 0); + } + /* Vertical GRAM End Address */ + LCD_WriteReg(LCD_REG_83, Ypos); + + LCD_SetCursor(Xpos, Ypos); +} + + +/** + * @brief Disables LCD Window mode. + * @param None + * @retval None + */ +void LCD_WindowModeDisable(void) +{ + LCD_SetDisplayWindow(239, 0x13F, 240, 320); + LCD_WriteReg(LCD_REG_3, 0x1018); +} + +/** + * @brief Displays a line. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Length: line length. + * @param Direction: line direction. + * This parameter can be one of the following values: Vertical or Horizontal. + * @retval None + */ +void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) +{ + uint32_t i = 0; + + LCD_SetCursor(Xpos, Ypos); + + if(Direction == LCD_DIR_HORIZONTAL) + { + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + + for(i = 0; i < Length; i++) + { + LCD_WriteRAM(TextColor); + } + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); + } + else + { + for(i = 0; i < Length; i++) + { + LCD_WriteRAMWord(TextColor); + Xpos++; + LCD_SetCursor(Xpos, Ypos); + } + } +} + + +/** + * @brief Displays a rectangle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Height: display rectangle height. + * @param Width: display rectangle width. + * @retval None + */ +void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) +{ + LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); + LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); + + LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); + LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); +} + + +/** + * @brief Displays a circle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Radius + * @retval None + */ +void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + int32_t D;/* Decision Variable */ + uint32_t CurX;/* Current X Value */ + uint32_t CurY;/* Current Y Value */ + + D = 3 - (Radius << 1); + CurX = 0; + CurY = Radius; + + while (CurX <= CurY) + { + LCD_SetCursor(Xpos + CurX, Ypos + CurY); + LCD_WriteRAMWord(TextColor); + LCD_SetCursor(Xpos + CurX, Ypos - CurY); + LCD_WriteRAMWord(TextColor); + + LCD_SetCursor(Xpos - CurX, Ypos + CurY); + LCD_WriteRAMWord(TextColor); + + LCD_SetCursor(Xpos - CurX, Ypos - CurY); + LCD_WriteRAMWord(TextColor); + + LCD_SetCursor(Xpos + CurY, Ypos + CurX); + LCD_WriteRAMWord(TextColor); + + LCD_SetCursor(Xpos + CurY, Ypos - CurX); + LCD_WriteRAMWord(TextColor); + + LCD_SetCursor(Xpos - CurY, Ypos + CurX); + LCD_WriteRAMWord(TextColor); + + LCD_SetCursor(Xpos - CurY, Ypos - CurX); + LCD_WriteRAMWord(TextColor); + + if (D < 0) + { + D += (CurX << 2) + 6; + } + else + { + D += ((CurX - CurY) << 2) + 10; + CurY--; + } + CurX++; + } +} + + +/** + * @brief Displays a monocolor picture. + * @param Pict: pointer to the picture array. + * @retval None + */ +void LCD_DrawMonoPict(const uint32_t *Pict) +{ + uint32_t index = 0, i = 0; + LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); + + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + + for(index = 0; index < 2400; index++) + { + for(i = 0; i < 32; i++) + { + if((Pict[index] & (1 << i)) == 0x00) + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + } + + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); +} + +#ifdef USE_LCD_DrawBMP +/** + * @brief Displays a bitmap picture loaded in the SPI Flash. + * @param BmpAddress: Bmp picture address in the SPI Flash. + * @retval None + */ +void LCD_DrawBMP(uint32_t BmpAddress) +{ + uint32_t i = 0, size = 0; + /* Read bitmap size */ + SPI_FLASH_BufferRead((uint8_t*)&size, BmpAddress + 2, 4); + /* get bitmap data address offset */ + SPI_FLASH_BufferRead((uint8_t*)&i, BmpAddress + 10, 4); + + size = (size - i)/2; + SPI_FLASH_StartReadSequence(BmpAddress + i); + /* Disable SPI1 */ + SPI_Cmd(SPI1, DISABLE); + /* SPI in 16-bit mode */ + SPI_DataSizeConfig(SPI1, SPI_DataSize_16b); + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); + + if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) + { + /* Set GRAM write direction and BGR = 1 */ + /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ + /* AM=1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1008); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + } + + /* Read bitmap data from SPI Flash and send them to LCD */ + for(i = 0; i < size; i++) + { + LCD_WriteRAM(__REV16(SPI_FLASH_SendHalfWord(0xA5A5))); + } + if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) + { + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); + } + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_CS_HIGH(); + /* Disable SPI1 */ + SPI_Cmd(SPI1, DISABLE); + /* SPI in 8-bit mode */ + SPI_DataSizeConfig(SPI1, SPI_DataSize_8b); + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); + + if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) + { + /* Set GRAM write direction and BGR = 1 */ + /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ + /* AM = 1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1018); + } +} +#endif /* USE_LCD_DrawBMP */ + +/** + * @brief Displays a full rectangle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Height: rectangle height. + * @param Width: rectangle width. + * @retval None + */ +void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) +{ + LCD_SetTextColor(TextColor); + + LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); + LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); + + LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); + LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); + + Width -= 2; + Height--; + Ypos--; + + LCD_SetTextColor(BackColor); + + while(Height--) + { + LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); + } + + LCD_SetTextColor(TextColor); +} + +/** + * @brief Displays a full circle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Radius + * @retval None + */ +void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + int32_t D; /* Decision Variable */ + uint32_t CurX;/* Current X Value */ + uint32_t CurY;/* Current Y Value */ + + D = 3 - (Radius << 1); + + CurX = 0; + CurY = Radius; + + LCD_SetTextColor(BackColor); + + while (CurX <= CurY) + { + if(CurY > 0) + { + LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); + LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); + } + + if(CurX > 0) + { + LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); + LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); + } + if (D < 0) + { + D += (CurX << 2) + 6; + } + else + { + D += ((CurX - CurY) << 2) + 10; + CurY--; + } + CurX++; + } + + LCD_SetTextColor(TextColor); + LCD_DrawCircle(Xpos, Ypos, Radius); +} + +/** + * @brief Displays an uni line (between two points). + * @param x1: specifies the point 1 x position. + * @param y1: specifies the point 1 y position. + * @param x2: specifies the point 2 x position. + * @param y2: specifies the point 2 y position. + * @retval None + */ +void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) +{ + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, + curpixel = 0; + + deltax = ABS(x2 - x1); /* The difference between the x's */ + deltay = ABS(y2 - y1); /* The difference between the y's */ + x = x1; /* Start x off at the first pixel */ + y = y1; /* Start y off at the first pixel */ + + if (x2 >= x1) /* The x-values are increasing */ + { + xinc1 = 1; + xinc2 = 1; + } + else /* The x-values are decreasing */ + { + xinc1 = -1; + xinc2 = -1; + } + + if (y2 >= y1) /* The y-values are increasing */ + { + yinc1 = 1; + yinc2 = 1; + } + else /* The y-values are decreasing */ + { + yinc1 = -1; + yinc2 = -1; + } + + if (deltax >= deltay) /* There is at least one x-value for every y-value */ + { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + yinc2 = 0; /* Don't change the y for every iteration */ + den = deltax; + num = deltax / 2; + numadd = deltay; + numpixels = deltax; /* There are more x-values than y-values */ + } + else /* There is at least one y-value for every x-value */ + { + xinc2 = 0; /* Don't change the x for every iteration */ + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + den = deltay; + num = deltay / 2; + numadd = deltax; + numpixels = deltay; /* There are more y-values than x-values */ + } + + for (curpixel = 0; curpixel <= numpixels; curpixel++) + { + PutPixel(x, y); /* Draw the current pixel */ + num += numadd; /* Increase the numerator by the top of the fraction */ + if (num >= den) /* Check if numerator >= denominator */ + { + num -= den; /* Calculate the new numerator value */ + x += xinc1; /* Change the x as appropriate */ + y += yinc1; /* Change the y as appropriate */ + } + x += xinc2; /* Change the x as appropriate */ + y += yinc2; /* Change the y as appropriate */ + } +} + +/** + * @brief Displays an polyline (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_PolyLine(pPoint Points, uint16_t PointCount) +{ + int16_t X = 0, Y = 0; + + if(PointCount < 2) + { + return; + } + + while(--PointCount) + { + X = Points->X; + Y = Points->Y; + Points++; + LCD_DrawUniLine(X, Y, Points->X, Points->Y); + } +} + +/** + * @brief Displays an relative polyline (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @param Closed: specifies if the draw is closed or not. + * 1: closed, 0 : not closed. + * @retval None + */ +static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) +{ + int16_t X = 0, Y = 0; + pPoint First = Points; + + if(PointCount < 2) + { + return; + } + X = Points->X; + Y = Points->Y; + while(--PointCount) + { + Points++; + LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); + X = X + Points->X; + Y = Y + Points->Y; + } + if(Closed) + { + LCD_DrawUniLine(First->X, First->Y, X, Y); + } +} + +/** + * @brief Displays a closed polyline (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) +{ + LCD_PolyLine(Points, PointCount); + LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); +} + +/** + * @brief Displays a relative polyline (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) +{ + LCD_PolyLineRelativeClosed(Points, PointCount, 0); +} + +/** + * @brief Displays a closed relative polyline (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) +{ + LCD_PolyLineRelativeClosed(Points, PointCount, 1); +} + + +/** + * @brief Displays a full polyline (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) +{ + /* public-domain code by Darel Rex Finley, 2007 */ + uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, + j = 0, swap = 0; + uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; + + IMAGE_LEFT = IMAGE_RIGHT = Points->X; + IMAGE_TOP= IMAGE_BOTTOM = Points->Y; + + for(i = 1; i < PointCount; i++) + { + pixelX = POLY_X(i); + if(pixelX < IMAGE_LEFT) + { + IMAGE_LEFT = pixelX; + } + if(pixelX > IMAGE_RIGHT) + { + IMAGE_RIGHT = pixelX; + } + + pixelY = POLY_Y(i); + if(pixelY < IMAGE_TOP) + { + IMAGE_TOP = pixelY; + } + if(pixelY > IMAGE_BOTTOM) + { + IMAGE_BOTTOM = pixelY; + } + } + + LCD_SetTextColor(BackColor); + + /* Loop through the rows of the image. */ + for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) + { + /* Build a list of nodes. */ + nodes = 0; j = PointCount-1; + + for (i = 0; i < PointCount; i++) + { + if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) + { + nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); + } + j = i; + } + + /* Sort the nodes, via a simple “Bubble” sort. */ + i = 0; + while (i < nodes-1) + { + if (nodeX[i]>nodeX[i+1]) + { + swap = nodeX[i]; + nodeX[i] = nodeX[i+1]; + nodeX[i+1] = swap; + if(i) + { + i--; + } + } + else + { + i++; + } + } + + /* Fill the pixels between node pairs. */ + for (i = 0; i < nodes; i+=2) + { + if(nodeX[i] >= IMAGE_RIGHT) + { + break; + } + if(nodeX[i+1] > IMAGE_LEFT) + { + if (nodeX[i] < IMAGE_LEFT) + { + nodeX[i]=IMAGE_LEFT; + } + if(nodeX[i+1] > IMAGE_RIGHT) + { + nodeX[i+1] = IMAGE_RIGHT; + } + LCD_SetTextColor(BackColor); + LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); + LCD_SetTextColor(TextColor); + PutPixel(pixelY, nodeX[i+1]); + PutPixel(pixelY, nodeX[i]); + /* for (j=nodeX[i]; j> 8); + + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } + + SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF)); + + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } + + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); +} + + +/** + * @brief Reads the selected LCD Register. + * @param LCD_Reg: address of the selected register. + * @retval LCD Register Value. + */ +uint16_t LCD_ReadReg(uint8_t LCD_Reg) +{ + uint16_t tmp = 0; + uint8_t i = 0; + + /* LCD_SPI prescaler: 4 */ + LCD_SPI->CR1 &= 0xFFC7; + LCD_SPI->CR1 |= 0x0008; + /* Write 16-bit Index (then Read Reg) */ + LCD_WriteRegIndex(LCD_Reg); + /* Read 16-bit Reg */ + /* Reset LCD control line(/CS) and Send Start-Byte */ + LCD_nCS_StartByte(START_BYTE | LCD_READ_REG); + + for(i = 0; i < 5; i++) + { + SPI_SendData(LCD_SPI, 0xFF); + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } + /* One byte of invalid dummy data read after the start byte */ + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET) + { + } + SPI_ReceiveData(LCD_SPI); + } + + SPI_SendData(LCD_SPI, 0xFF); + + /* Read upper byte */ + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } + + /* Read lower byte */ + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET) + { + } + tmp = SPI_ReceiveData(LCD_SPI); + + + SPI_SendData(LCD_SPI, 0xFF); + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } + + /* Read lower byte */ + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET) + { + } + + tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI); + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); + + /* LCD_SPI prescaler: 2 */ + LCD_SPI->CR1 &= 0xFFC7; + + return tmp; +} + + +/** + * @brief Prepare to write to the LCD RAM. + * @param None + * @retval None + */ +void LCD_WriteRAM_Prepare(void) +{ + LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */ + + /* Reset LCD control line(/CS) and Send Start-Byte */ + LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG); +} + + +/** + * @brief Writes 1 word to the LCD RAM. + * @param RGB_Code: the pixel color in RGB mode (5-6-5). + * @retval None + */ +void LCD_WriteRAMWord(uint16_t RGB_Code) +{ + LCD_WriteRAM_Prepare(); + + LCD_WriteRAM(RGB_Code); + + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); +} + +/** + * @brief Writes to the LCD RAM. + * @param RGB_Code: the pixel color in RGB mode (5-6-5). + * @retval None + */ +void LCD_WriteRAM(uint16_t RGB_Code) +{ + SPI_SendData(LCD_SPI, RGB_Code >> 8); + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } + SPI_SendData(LCD_SPI, RGB_Code & 0xFF); + while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) + { + } +} + + +/** + * @brief Power on the LCD. + * @param None + * @retval None + */ +void LCD_PowerOn(void) +{ + /* Power On sequence ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ + LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + _delay_(5); /* delay 50 ms */ + LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + _delay_(5); /* delay 50 ms */ + LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ +} + + +/** + * @brief Enables the Display. + * @param None + * @retval None + */ +void LCD_DisplayOn(void) +{ + /* Display On */ + LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ +} + + +/** + * @brief Disables the Display. + * @param None + * @retval None + */ +void LCD_DisplayOff(void) +{ + /* Display Off */ + LCD_WriteReg(LCD_REG_7, 0x0); +} + + +/** + * @brief Configures LCD control lines in Output Push-Pull mode. + * @param None + * @retval None + */ +void LCD_CtrlLinesConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE); + + /* Configure NCS (PF.02) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); + + LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); +} + + +/** + * @brief Sets or reset LCD control lines. + * @param GPIOx: where x can be B or D to select the GPIO peripheral. + * @param CtrlPins: the Control line. + * This parameter can be: + * @arg LCD_NCS_PIN: Chip Select pin + * @arg LCD_NWR_PIN: Read/Write Selection pin + * @arg LCD_RS_PIN: Register/RAM Selection pin + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal) +{ + /* Set or Reset the control line */ + GPIO_WriteBit(GPIOx, CtrlPins, BitVal); +} + + +/** + * @brief Configures the LCD_SPI interface. + * @param None + * @retval None + */ +void LCD_SPIConfig(void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */ + RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE); + + /* Enable LCD_SPI and SYSCFG clock */ + RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure LCD_SPI SCK pin */ + GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + /* Configure LCD_SPI MISO pin */ + GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; + GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + /* Configure LCD_SPI MOSI pin */ + GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; + GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PE.13 to SPI SCK */ + GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF); + + /* Connect PE.14 to SPI MISO */ + GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF); + + /* Connect PE.15 to SPI MOSI */ + GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF); + + SPI_DeInit(LCD_SPI); + + /* SPI Config */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(LCD_SPI, &SPI_InitStructure); + + /* SPI enable */ + SPI_Cmd(LCD_SPI, ENABLE); +} + +/** + * @brief Displays a pixel. + * @param x: pixel x. + * @param y: pixel y. + * @retval None + */ +static void PutPixel(int16_t x, int16_t y) +{ + if(x < 0 || x > 239 || y < 0 || y > 319) + { + return; + } + LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); +} + +#ifndef USE_Delay +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +static void delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (34000 * nCount); index != 0; index--) + { + } +} +#endif /* USE_Delay*/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h new file mode 100644 index 0000000000..e3c06a1f75 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file stm32l152_eval_lcd.h + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the stm32l152_eval_lcd + * firmware driver. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L152_EVAL_LCD_H +#define __STM32L152_EVAL_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" +#include "../Common/fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM32L152_EVAL + * @{ + */ + +/** @addtogroup STM32L152_EVAL_LCD + * @{ + */ + + +/** @defgroup STM32L152_EVAL_LCD_Exported_Types + * @{ + */ +typedef struct +{ + int16_t X; + int16_t Y; +} Point, * pPoint; +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Exported_Constants + * @{ + */ + +/** + * @brief Uncomment the line below if you want to use LCD_DrawBMP function to + * display a bitmap picture on the LCD. This function assumes that the bitmap + * file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however + * user can tailor it according to his application hardware requirement. + */ +/*#define USE_LCD_DrawBMP*/ + +/** + * @brief Uncomment the line below if you want to use user defined Delay function + * (for precise timing), otherwise default _delay_ function defined within + * this driver is used (less precise timing). + */ +/* #define USE_Delay */ + +#ifdef USE_Delay +#include "main.h" + + #define _delay_ Delay /* !< User can provide more timing precise _delay_ function + (with 10ms time base), using SysTick for example */ +#else + #define _delay_ delay /* !< Default _delay_ function with less precise timing */ +#endif + + +/** + * @brief LCD Control pins + */ +#define LCD_NCS_PIN GPIO_Pin_2 +#define LCD_NCS_GPIO_PORT GPIOH +#define LCD_NCS_GPIO_CLK RCC_AHBPeriph_GPIOH + +/** + * @brief LCD SPI Interface pins + */ +#define LCD_SPI_SCK_PIN GPIO_Pin_13 /* PE.13 */ +#define LCD_SPI_SCK_GPIO_PORT GPIOE /* GPIOE */ +#define LCD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOE +#define LCD_SPI_SCK_SOURCE GPIO_PinSource13 +#define LCD_SPI_SCK_AF GPIO_AF_SPI1 +#define LCD_SPI_MISO_PIN GPIO_Pin_14 /* PE.14 */ +#define LCD_SPI_MISO_GPIO_PORT GPIOE /* GPIOE */ +#define LCD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOE +#define LCD_SPI_MISO_SOURCE GPIO_PinSource14 +#define LCD_SPI_MISO_AF GPIO_AF_SPI1 +#define LCD_SPI_MOSI_PIN GPIO_Pin_15 /* PE.15 */ +#define LCD_SPI_MOSI_GPIO_PORT GPIOE /* GPIOE */ +#define LCD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOE +#define LCD_SPI_MOSI_SOURCE GPIO_PinSource15 +#define LCD_SPI_MOSI_AF GPIO_AF_SPI1 +#define LCD_SPI SPI1 +#define LCD_SPI_CLK RCC_APB2Periph_SPI1 + + +/** + * @brief LCD Registers + */ +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0A +#define LCD_REG_12 0x0C +#define LCD_REG_13 0x0D +#define LCD_REG_14 0x0E +#define LCD_REG_15 0x0F +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1A +#define LCD_REG_27 0x1B +#define LCD_REG_28 0x1C +#define LCD_REG_29 0x1D +#define LCD_REG_30 0x1E +#define LCD_REG_31 0x1F +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2B +#define LCD_REG_45 0x2D +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_59 0x3B +#define LCD_REG_60 0x3C +#define LCD_REG_61 0x3D +#define LCD_REG_62 0x3E +#define LCD_REG_63 0x3F +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4A +#define LCD_REG_75 0x4B +#define LCD_REG_76 0x4C +#define LCD_REG_77 0x4D +#define LCD_REG_78 0x4E +#define LCD_REG_79 0x4F +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6A +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8B +#define LCD_REG_140 0x8C +#define LCD_REG_141 0x8D +#define LCD_REG_143 0x8F +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9A +#define LCD_REG_157 0x9D +#define LCD_REG_192 0xC0 +#define LCD_REG_193 0xC1 +#define LCD_REG_227 0xE3 +#define LCD_REG_229 0xE5 +#define LCD_REG_231 0xE7 +#define LCD_REG_239 0xEF + + +/** + * @brief LCD color + */ +#define LCD_COLOR_WHITE 0xFFFF +#define LCD_COLOR_BLACK 0x0000 +#define LCD_COLOR_GREY 0xF7DE +#define LCD_COLOR_BLUE 0x001F +#define LCD_COLOR_BLUE2 0x051F +#define LCD_COLOR_RED 0xF800 +#define LCD_COLOR_MAGENTA 0xF81F +#define LCD_COLOR_GREEN 0x07E0 +#define LCD_COLOR_CYAN 0x7FFF +#define LCD_COLOR_YELLOW 0xFFE0 + +/** + * @brief LCD Lines depending on the chosen fonts. + */ +#define LCD_LINE_0 LINE(0) +#define LCD_LINE_1 LINE(1) +#define LCD_LINE_2 LINE(2) +#define LCD_LINE_3 LINE(3) +#define LCD_LINE_4 LINE(4) +#define LCD_LINE_5 LINE(5) +#define LCD_LINE_6 LINE(6) +#define LCD_LINE_7 LINE(7) +#define LCD_LINE_8 LINE(8) +#define LCD_LINE_9 LINE(9) +#define LCD_LINE_10 LINE(10) +#define LCD_LINE_11 LINE(11) +#define LCD_LINE_12 LINE(12) +#define LCD_LINE_13 LINE(13) +#define LCD_LINE_14 LINE(14) +#define LCD_LINE_15 LINE(15) +#define LCD_LINE_16 LINE(16) +#define LCD_LINE_17 LINE(17) +#define LCD_LINE_18 LINE(18) +#define LCD_LINE_19 LINE(19) +#define LCD_LINE_20 LINE(20) +#define LCD_LINE_21 LINE(21) +#define LCD_LINE_22 LINE(22) +#define LCD_LINE_23 LINE(23) +#define LCD_LINE_24 LINE(24) +#define LCD_LINE_25 LINE(25) +#define LCD_LINE_26 LINE(26) +#define LCD_LINE_27 LINE(27) +#define LCD_LINE_28 LINE(28) +#define LCD_LINE_29 LINE(29) + + +/** + * @brief LCD default font + */ +#define LCD_DEFAULT_FONT Font16x24 + +/** + * @brief LCD Direction + */ +#define LCD_DIR_HORIZONTAL 0x0000 +#define LCD_DIR_VERTICAL 0x0001 + +/** + * @brief LCD Size (Width and Height) + */ +#define LCD_PIXEL_WIDTH 0x0140 +#define LCD_PIXEL_HEIGHT 0x00F0 + +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Exported_Macros + * @{ + */ +#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) + +/** + * @} + */ + +/** @defgroup STM32L152_EVAL_LCD_Exported_Functions + * @{ + */ +void STM32L152_LCD_DeInit(void); +void LCD_Setup(void); +void STM32L152_LCD_Init(void); +void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); +void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); +void LCD_SetTextColor(__IO uint16_t Color); +void LCD_SetBackColor(__IO uint16_t Color); +void LCD_ClearLine(uint8_t Line); +void LCD_Clear(uint16_t Color); +void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); +void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); +void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); +void LCD_SetFont(sFONT *fonts); +sFONT *LCD_GetFont(void); +void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); +void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); +void LCD_WindowModeDisable(void); +void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); +void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); +void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); +void LCD_DrawMonoPict(const uint32_t *Pict); +void LCD_DrawBMP(uint32_t BmpAddress); +void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); +void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); +void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); +void LCD_PolyLine(pPoint Points, uint16_t PointCount); +void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); +void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); +void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); +void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); +void LCD_nCS_StartByte(uint8_t Start_Byte); +void LCD_WriteRegIndex(uint8_t LCD_Reg); +void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); +void LCD_WriteRAM_Prepare(void); +void LCD_WriteRAMWord(uint16_t RGB_Code); +uint16_t LCD_ReadReg(uint8_t LCD_Reg); +void LCD_WriteRAM(uint16_t RGB_Code); +void LCD_PowerOn(void); +void LCD_DisplayOn(void); +void LCD_DisplayOff(void); + +void LCD_CtrlLinesConfig(void); +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal); +void LCD_SPIConfig(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L152_EVAL_LCD_H */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h new file mode 100644 index 0000000000..6ae338d546 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32l1xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0001FFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h new file mode 100644 index 0000000000..769e4fc886 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file stm32l1xx_exti.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_EXTI_H +#define __STM32L1xx_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 + Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 + Connected to the RTC Alarm + event */ +#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 + Connected to the USB Device + FS Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 + Connected to the RTC Tamper + and Time Stamp events */ +#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 + Connected to the RTC Wakeup + event */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 + Connected to the Comparator 1 + event */ + +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 + Connected to the Comparator 2 + event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ + ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ + ((LINE) == EXTI_Line22)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h new file mode 100644 index 0000000000..189be5a53b --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file stm32l1xx_gpio.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_GPIO_H +#define __STM32L1xx_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOH)) + +/** @defgroup Configuration_Mode_enumeration + * @{ + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ +}GPIOMode_TypeDef; +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) +/** + * @} + */ + +/** @defgroup Output_type_enumeration + * @{ + */ +typedef enum +{ GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + +/** + * @} + */ + +/** @defgroup Output_Maximum_frequency_enumeration + * @{ + */ +typedef enum +{ + GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */ + GPIO_Speed_2MHz = 0x01, /*!< Low Speed */ + GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */ + GPIO_Speed_40MHz = 0x03 /*!< High Speed */ +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz)) +/** + * @} + */ + +/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration + * @{ + */ +typedef enum +{ GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) +/** + * @} + */ + +/** @defgroup Bit_SET_and_Bit_RESET_enumeration + * @{ + */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternat_function_selection_define + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */ +#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */ +#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */ +#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */ +#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +/** + * @brief AF 3 selection + */ +#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ +#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */ +#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ +/** + * @brief AF 5 selection + */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */ +/** + * @brief AF 14 selection + */ +#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \ + ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \ + ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \ + ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \ + ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \ + ((AF) == GPIO_AF_EVENTOUT)) + +/** + * @} + */ + +/** @defgroup GPIO_Legacy + * @{ + */ + +#define GPIO_Mode_AIN GPIO_Mode_AN + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32L1xx_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h new file mode 100644 index 0000000000..a9b949c99c --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h @@ -0,0 +1,471 @@ +/** + ****************************************************************************** + * @file stm32l1xx_rcc.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the RCC + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_RCC_H +#define __STM32L1xx_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup MSI_Clock_Range + * @{ + */ + +#define RCC_MSIRange_64KHz RCC_ICSCR_MSIRANGE_64KHz +#define RCC_MSIRange_128KHz RCC_ICSCR_MSIRANGE_128KHz +#define RCC_MSIRange_256KHz RCC_ICSCR_MSIRANGE_256KHz +#define RCC_MSIRange_512KHz RCC_ICSCR_MSIRANGE_512KHz +#define RCC_MSIRange_1MHz RCC_ICSCR_MSIRANGE_1MHz +#define RCC_MSIRange_2MHz RCC_ICSCR_MSIRANGE_2MHz +#define RCC_MSIRange_4MHz RCC_ICSCR_MSIRANGE_4MHz + +#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) || \ + ((RANGE) == RCC_MSIRange_128KHz) || \ + ((RANGE) == RCC_MSIRange_256KHz) || \ + ((RANGE) == RCC_MSIRange_512KHz) || \ + ((RANGE) == RCC_MSIRange_1MHz) || \ + ((RANGE) == RCC_MSIRange_2MHz) || \ + ((RANGE) == RCC_MSIRange_4MHz)) + +/** + * @} + */ + +/** @defgroup PLL_Clock_Source + * @{ + */ + +#define RCC_PLLSource_HSI ((uint8_t)0x00) +#define RCC_PLLSource_HSE ((uint8_t)0x01) + +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE)) +/** + * @} + */ + +/** @defgroup PLL_Multiplication_Factor + * @{ + */ + +#define RCC_PLLMul_3 ((uint8_t)0x00) +#define RCC_PLLMul_4 ((uint8_t)0x04) +#define RCC_PLLMul_6 ((uint8_t)0x08) +#define RCC_PLLMul_8 ((uint8_t)0x0C) +#define RCC_PLLMul_12 ((uint8_t)0x10) +#define RCC_PLLMul_16 ((uint8_t)0x14) +#define RCC_PLLMul_24 ((uint8_t)0x18) +#define RCC_PLLMul_32 ((uint8_t)0x1C) +#define RCC_PLLMul_48 ((uint8_t)0x20) + + +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \ + ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \ + ((MUL) == RCC_PLLMul_48)) +/** + * @} + */ + +/** @defgroup PLL_Divider_Factor + * @{ + */ + +#define RCC_PLLDiv_2 ((uint8_t)0x40) +#define RCC_PLLDiv_3 ((uint8_t)0x80) +#define RCC_PLLDiv_4 ((uint8_t)0xC0) + + +#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \ + ((DIV) == RCC_PLLDiv_4)) +/** + * @} + */ + +/** @defgroup System_Clock_Source + * @{ + */ + +#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI +#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_Clock_Source + * @{ + */ + +#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_Clock_Source + * @{ + */ + +#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16 +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + + +/** @defgroup RCC_Interrupt_Source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_MSIRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) + +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ + ((IT) == RCC_IT_CSS)) + +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup LSE_Configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x05) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_Clock_Source + * @{ + */ + +#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE +#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI +#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE +#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0) +#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1) +#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div16)) +/** + * @} + */ + +/** @defgroup AHB_Peripherals + * @{ + */ + +#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN +#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN +#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN +#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN +#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN +#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN +#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN +#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN +#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN +#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup APB2_Peripherals + * @{ + */ + +#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN +#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN +#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN +#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN +#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN +#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN +#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_Peripherals + * @{ + */ + +#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN +#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN +#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN +#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN +#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN +#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN +#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN +#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN +#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN +#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN +#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN +#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN +#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN +#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN +#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN +#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup MCO_Clock_Source + * @{ + */ + +#define RCC_MCOSource_NoClock ((uint8_t)0x00) +#define RCC_MCOSource_SYSCLK ((uint8_t)0x01) +#define RCC_MCOSource_HSI ((uint8_t)0x02) +#define RCC_MCOSource_MSI ((uint8_t)0x03) +#define RCC_MCOSource_HSE ((uint8_t)0x04) +#define RCC_MCOSource_PLLCLK ((uint8_t)0x05) +#define RCC_MCOSource_LSI ((uint8_t)0x06) +#define RCC_MCOSource_LSE ((uint8_t)0x07) + +#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \ + ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \ + ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \ + ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE)) +/** + * @} + */ + +/** @defgroup MCO_Output_Divider + * @{ + */ + +#define RCC_MCODiv_1 ((uint8_t)0x00) +#define RCC_MCODiv_2 ((uint8_t)0x10) +#define RCC_MCODiv_4 ((uint8_t)0x20) +#define RCC_MCODiv_8 ((uint8_t)0x30) +#define RCC_MCODiv_16 ((uint8_t)0x40) + +#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \ + ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \ + ((DIV) == RCC_MCODiv_16)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_MSIRDY ((uint8_t)0x29) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x49) +#define RCC_FLAG_LSIRDY ((uint8_t)0x41) +#define RCC_FLAG_OBLRST ((uint8_t)0x59) +#define RCC_FLAG_PINRST ((uint8_t)0x5A) +#define RCC_FLAG_PORRST ((uint8_t)0x5B) +#define RCC_FLAG_SFTRST ((uint8_t)0x5C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \ + ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue); +void RCC_MSIRangeConfig(uint32_t RCC_MSIRange); +void RCC_MSICmd(FunctionalState NewState); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_RTCResetCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h new file mode 100644 index 0000000000..cd51e92092 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h @@ -0,0 +1,381 @@ +/** + ****************************************************************************** + * @file stm32l1xx_syscfg.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains all the functions prototypes for the SYSCFG + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/*!< Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_SYSCFG_H +#define __STM32L1xx_SYSCFG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*!< Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SYSCFG + * @{ + */ + +/** @defgroup SYSCFG_Exported_Types + * @{ + */ + +/** @defgroup EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) +#define EXTI_PortSourceGPIOH ((uint8_t)0x05) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOH)) +/** + * @} + */ + +/** @defgroup EXTI_Pin_sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM)) + + +/** @defgroup RI_Resistor + * @{ + */ + +#define RI_Resistor_10KPU COMP_CSR_10KPU +#define RI_Resistor_400KPU COMP_CSR_400KPU +#define RI_Resistor_10KPD COMP_CSR_10KPD +#define RI_Resistor_400KPD COMP_CSR_400KPD + +#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \ + ((RESISTOR) == COMP_CSR_400KPU) || \ + ((RESISTOR) == COMP_CSR_10KPD) || \ + ((RESISTOR) == COMP_CSR_400KPD)) + +/** + * @} + */ + +/** @defgroup RI_InputCapture + * @{ + */ + +#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ +#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ +#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ +#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ + +#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup TIM_Select + * @{ + */ + +#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */ +#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */ +#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */ +#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */ + +#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \ + ((TIM) == TIM_Select_TIM2) || \ + ((TIM) == TIM_Select_TIM3) || \ + ((TIM) == TIM_Select_TIM4)) + +/** + * @} + */ + +/** @defgroup RI_InputCaptureRouting + * @{ + */ + /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ +#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */ +#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */ +#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */ +#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */ +#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */ +#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */ +#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */ +#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */ +#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */ +#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */ +#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */ +#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */ +#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */ +#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */ +#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */ +#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */ + +#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \ + ((ROUTING) == RI_InputCaptureRouting_1) || \ + ((ROUTING) == RI_InputCaptureRouting_2) || \ + ((ROUTING) == RI_InputCaptureRouting_3) || \ + ((ROUTING) == RI_InputCaptureRouting_4) || \ + ((ROUTING) == RI_InputCaptureRouting_5) || \ + ((ROUTING) == RI_InputCaptureRouting_6) || \ + ((ROUTING) == RI_InputCaptureRouting_7) || \ + ((ROUTING) == RI_InputCaptureRouting_8) || \ + ((ROUTING) == RI_InputCaptureRouting_9) || \ + ((ROUTING) == RI_InputCaptureRouting_10) || \ + ((ROUTING) == RI_InputCaptureRouting_11) || \ + ((ROUTING) == RI_InputCaptureRouting_12) || \ + ((ROUTING) == RI_InputCaptureRouting_13) || \ + ((ROUTING) == RI_InputCaptureRouting_14) || \ + ((ROUTING) == RI_InputCaptureRouting_15)) + +/** + * @} + */ + +/** @defgroup RI_IOSwitch + * @{ + */ + +/* ASCR1 I/O switch: bit 28 is set to '1' to indicate that the mask is in ASCR1 register */ +#define RI_IOSwitch_CH0 ((uint32_t)0x10000001) +#define RI_IOSwitch_CH1 ((uint32_t)0x10000002) +#define RI_IOSwitch_CH2 ((uint32_t)0x10000004) +#define RI_IOSwitch_CH3 ((uint32_t)0x10000008) +#define RI_IOSwitch_CH4 ((uint32_t)0x10000010) +#define RI_IOSwitch_CH5 ((uint32_t)0x10000020) +#define RI_IOSwitch_CH6 ((uint32_t)0x10000040) +#define RI_IOSwitch_CH7 ((uint32_t)0x10000080) +#define RI_IOSwitch_CH8 ((uint32_t)0x10000100) +#define RI_IOSwitch_CH9 ((uint32_t)0x10000200) +#define RI_IOSwitch_CH10 ((uint32_t)0x10000400) +#define RI_IOSwitch_CH11 ((uint32_t)0x10000800) +#define RI_IOSwitch_CH12 ((uint32_t)0x10001000) +#define RI_IOSwitch_CH13 ((uint32_t)0x10002000) +#define RI_IOSwitch_CH14 ((uint32_t)0x10004000) +#define RI_IOSwitch_CH15 ((uint32_t)0x10008000) +#define RI_IOSwitch_CH18 ((uint32_t)0x10040000) +#define RI_IOSwitch_CH19 ((uint32_t)0x10080000) +#define RI_IOSwitch_CH20 ((uint32_t)0x10100000) +#define RI_IOSwitch_CH21 ((uint32_t)0x10200000) +#define RI_IOSwitch_CH22 ((uint32_t)0x10400000) +#define RI_IOSwitch_CH23 ((uint32_t)0x10800000) +#define RI_IOSwitch_CH24 ((uint32_t)0x11000000) +#define RI_IOSwitch_CH25 ((uint32_t)0x12000000) +#define RI_IOSwitch_VCOMP ((uint32_t)0x14000000) /* VCOMP is an internal switch used to connect + selected channel to COMP1 non inverting input */ + +/* ASCR2 IO switch: : bit 28 is set to '0' to indicate that the mask is in ASCR2 register */ +#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001) +#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002) +#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004) +#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008) +#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010) +#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020) +#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040) +#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080) +#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100) +#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200) +#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400) +#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800) + +#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \ + ((IOSWITCH) == RI_IOSwitch_CH1) || \ + ((IOSWITCH) == RI_IOSwitch_CH2) || \ + ((IOSWITCH) == RI_IOSwitch_CH3) || \ + ((IOSWITCH) == RI_IOSwitch_CH4) || \ + ((IOSWITCH) == RI_IOSwitch_CH5) || \ + ((IOSWITCH) == RI_IOSwitch_CH6) || \ + ((IOSWITCH) == RI_IOSwitch_CH7) || \ + ((IOSWITCH) == RI_IOSwitch_CH8) || \ + ((IOSWITCH) == RI_IOSwitch_CH9) || \ + ((IOSWITCH) == RI_IOSwitch_CH10) || \ + ((IOSWITCH) == RI_IOSwitch_CH11) || \ + ((IOSWITCH) == RI_IOSwitch_CH12) || \ + ((IOSWITCH) == RI_IOSwitch_CH13) || \ + ((IOSWITCH) == RI_IOSwitch_CH14) || \ + ((IOSWITCH) == RI_IOSwitch_CH15) || \ + ((IOSWITCH) == RI_IOSwitch_CH18) || \ + ((IOSWITCH) == RI_IOSwitch_CH19) || \ + ((IOSWITCH) == RI_IOSwitch_CH20) || \ + ((IOSWITCH) == RI_IOSwitch_CH21) || \ + ((IOSWITCH) == RI_IOSwitch_CH22) || \ + ((IOSWITCH) == RI_IOSwitch_CH23) || \ + ((IOSWITCH) == RI_IOSwitch_CH24) || \ + ((IOSWITCH) == RI_IOSwitch_CH25) || \ + ((IOSWITCH) == RI_IOSwitch_VCOMP) || \ + ((IOSWITCH) == RI_IOSwitch_GR10_1) || \ + ((IOSWITCH) == RI_IOSwitch_GR10_2) || \ + ((IOSWITCH) == RI_IOSwitch_GR10_3) || \ + ((IOSWITCH) == RI_IOSwitch_GR10_4) || \ + ((IOSWITCH) == RI_IOSwitch_GR6_1) || \ + ((IOSWITCH) == RI_IOSwitch_GR6_2) || \ + ((IOSWITCH) == RI_IOSwitch_GR5_1) || \ + ((IOSWITCH) == RI_IOSwitch_GR5_2) || \ + ((IOSWITCH) == RI_IOSwitch_GR5_3) || \ + ((IOSWITCH) == RI_IOSwitch_GR4_1) || \ + ((IOSWITCH) == RI_IOSwitch_GR4_2) || \ + ((IOSWITCH) == RI_IOSwitch_GR4_3)) + +/** @defgroup RI_Port + * @{ + */ + +#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */ +#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */ +#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */ +#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */ +#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */ + +#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \ + ((PORT) == RI_PortB) || \ + ((PORT) == RI_PortC) || \ + ((PORT) == RI_PortD) || \ + ((PORT) == RI_PortE)) +/** + * @} + */ + +/** @defgroup RI_Pin define + * @{ + */ +#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Functions + * @{ + */ +void SYSCFG_DeInit(void); +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); +void SYSCFG_USBPuCmd(FunctionalState NewState); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_RIDeInit(void); +void SYSCFG_RITIMSelect(uint32_t TIM_Select); +void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting); +void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState); +void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState); +void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState); +void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, + FunctionalState NewState); +#ifdef __cplusplus +} +#endif + +#endif /*__STM32L1xx_SYSCFG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c new file mode 100644 index 0000000000..e7648ab199 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c new file mode 100644 index 0000000000..348f33c222 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32l1xx_exti.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_exti.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x007FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..22). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI’s line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI’s line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c new file mode 100644 index 0000000000..6c45f16514 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32l1xx_gpio.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_gpio.h" +#include "stm32l1xx_rcc.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset + * values. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if(GPIOx == GPIOA) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE); + } + else + { + if(GPIOx == GPIOH) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO + * peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /* -------------------------Configure the port pins---------------- */ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /*Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /*Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /*Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuartion*/ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + /*Pull-up Pull down resistor configuration*/ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRL = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRH = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRRL = GPIO_Pin; + } + else + { + GPIOx->BSRRH = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data + * register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AFSelection: selects the pin to used as Alternat function. + * This parameter can be one of the following values: + * @arg GPIO_AF_RTC_50Hz + * @arg GPIO_AF_MCO + * @arg GPIO_AF_TAMPER + * @arg GPIO_AF_WKUP + * @arg GPIO_AF_SWJ + * @arg GPIO_AF_TRACE + * @arg GPIO_AF_TIMESTAMP + * @arg GPIO_AF_CALIB + * @arg GPIO_AF_TIM2 + * @arg GPIO_AF_TIM3 + * @arg GPIO_AF_TIM4 + * @arg GPIO_AF_TIM9 + * @arg GPIO_AF_TIM10 + * @arg GPIO_AF_TIM11 + * @arg GPIO_AF_I2C1 + * @arg GPIO_AF_I2C2 + * @arg GPIO_AF_SPI1 + * @arg GPIO_AF_SPI2 + * @arg GPIO_AF_USART1 + * @arg GPIO_AF_USART2 + * @arg GPIO_AF_USART3 + * @arg GPIO_AF_USB + * @arg GPIO_AF_LCD + * @arg GPIO_AF_RI + * @arg GPIO_AF_EVENTOUT + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c new file mode 100644 index 0000000000..f7bdb4905f --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c @@ -0,0 +1,1225 @@ +/** + ****************************************************************************** + * @file stm32l1xx_rcc.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_rcc.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of MSION bit */ +#define MSION_BitNumber 0x08 +#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x1C +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x34) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* Alias word address of RTCEN bit */ +#define RTCEN_BitNumber 0x16 +#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of RTCRST bit */ +#define RTCRST_BitNumber 0x17 +#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4)) + + +/* ---------------------- RCC registers mask -------------------------------- */ +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) + +/* ICSCR register byte 4 (Bits[31:24]) base address */ +#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807) + +/* CFGR register byte 3 (Bits[23:16]) base address */ +#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E) + +/* CSR register byte 2 (Bits[15:8]) base address */ +#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835) + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + + /* Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /* Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; + +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->ICSCR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_ICSCR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 8; + + /* Store the new value */ + RCC->ICSCR = tmpreg; +} + +/** + * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value. + * @param MSICalibrationValue: specifies the MSI calibration trimming value. + * This parameter must be a number between 0 and 0xFF. + * @retval None + */ +void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue) +{ + + /* Check the parameters */ + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue)); + + *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; +} + +/** + * @brief Configures the Internal Multi Speed oscillator (MSI) clock range. + * @param RCC_MSIRange: specifies the MSI Clcok range. + * This parameter must be one of the following values: + * @arg RCC_MSIRange_64KHz: MSI clock is around 64 KHz + * @arg RCC_MSIRange_128KHz: MSI clock is around 128 KHz + * @arg RCC_MSIRange_256KHz: MSI clock is around 256 KHz + * @arg RCC_MSIRange_512KHz: MSI clock is around 512 KHz + * @arg RCC_MSIRange_1MHz: MSI clock is around 1 MHz + * @arg RCC_MSIRange_2MHz: MSI clock is around 2 MHz + * @arg RCC_MSIRange_4MHz: MSI clock is around 4 MHz + * @retval None + */ +void RCC_MSIRangeConfig(uint32_t RCC_MSIRange) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange)); + + tmpreg = RCC->ICSCR; + + /* Clear MSIRANGE[2:0] bits */ + tmpreg &= ~RCC_ICSCR_MSIRANGE; + + /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */ + tmpreg |= (uint32_t)RCC_MSIRange; + + /* Store the new value */ + RCC->ICSCR = tmpreg; +} + +/** + * @brief Enables or disables the Internal Multi Speed oscillator (MSI). + * @note MSI can not be stopped if it is used directly as system clock. + * @param NewState: new state of the MSI. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_MSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * This parameter can be: + * @arg RCC_PLLMul_3: PLL Clock entry multiplied by 3 + * @arg RCC_PLLMul_4: PLL Clock entry multiplied by 4 + * @arg RCC_PLLMul_6: PLL Clock entry multiplied by 6 + * @arg RCC_PLLMul_8: PLL Clock entry multiplied by 8 + * @arg RCC_PLLMul_12: PLL Clock entry multiplied by 12 + * @arg RCC_PLLMul_16: PLL Clock entry multiplied by 16 + * @arg RCC_PLLMul_24: PLL Clock entry multiplied by 24 + * @arg RCC_PLLMul_32: PLL Clock entry multiplied by 32 + * @arg RCC_PLLMul_48: PLL Clock entry multiplied by 48 + * @param RCC_PLLDiv: specifies the PLL division factor. + * This parameter can be: + * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 + * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 + * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 + * @retval None + */ +void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv)); + + *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv)))); +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following values: + * - 0x00: MSI used as system clock + * - 0x04: HSI used as system clock + * - 0x08: HSE used as system clock + * - 0x0C: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF; + + /* Set the new LSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK). + * @note + * - Once the RTC clock is selected it can't be changed unless the RTC is + * reset using RCC_RTCResetCmd function. + * - This RTC clock (RTCCLK) is used to clock the LCD (LCDCLK). + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) + { + /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ + tmpreg = RCC->CR; + + /* Clear RTCPRE[1:0] bits */ + tmpreg &= ~RCC_CR_RTCPRE; + + /* Configure HSE division factor for RTC clock */ + tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE); + + /* Store the new value */ + RCC->CR = tmpreg; + } + + RCC->CSR &= ~RCC_CSR_RTCSEL; + + /* Select the RTC clock source */ + RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the + * RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Forces or releases the RTC peripheral reset. + * @param NewState: new state of the RTC reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13; + RCC_Clocks->SYSCLK_Frequency = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000)); + break; + case 0x04: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA + * @arg RCC_AHBPeriph_GPIOB + * @arg RCC_AHBPeriph_GPIOC + * @arg RCC_AHBPeriph_GPIOD + * @arg RCC_AHBPeriph_GPIOE + * @arg RCC_AHBPeriph_GPIOH + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) + * @arg RCC_AHBPeriph_DMA1 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG + * @arg RCC_APB2Periph_TIM9 + * @arg RCC_APB2Periph_TIM10 + * @arg RCC_APB2Periph_TIM11 + * @arg RCC_APB2Periph_ADC1 + * @arg RCC_APB2Periph_SPI1 + * @arg RCC_APB2Periph_USART1 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2 + * @arg RCC_APB1Periph_TIM3 + * @arg RCC_APB1Periph_TIM4 + * @arg RCC_APB1Periph_TIM6 + * @arg RCC_APB1Periph_TIM7 + * @arg RCC_APB1Periph_LCD + * @arg RCC_APB1Periph_WWDG + * @arg RCC_APB1Periph_SPI2 + * @arg RCC_APB1Periph_USART2 + * @arg RCC_APB1Periph_USART3 + * @arg RCC_APB1Periph_I2C1 + * @arg RCC_APB1Periph_I2C2 + * @arg RCC_APB1Periph_USB + * @arg RCC_APB1Periph_PWR + * @arg RCC_APB1Periph_DAC + * @arg RCC_APB1Periph_COMP + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA + * @arg RCC_AHBPeriph_GPIOB + * @arg RCC_AHBPeriph_GPIOC + * @arg RCC_AHBPeriph_GPIOD + * @arg RCC_AHBPeriph_GPIOE + * @arg RCC_AHBPeriph_GPIOH + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) + * @arg RCC_AHBPeriph_DMA1 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG + * @arg RCC_APB2Periph_TIM9 + * @arg RCC_APB2Periph_TIM10 + * @arg RCC_APB2Periph_TIM11 + * @arg RCC_APB2Periph_ADC1 + * @arg RCC_APB2Periph_SPI1 + * @arg RCC_APB2Periph_USART1 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2 + * @arg RCC_APB1Periph_TIM3 + * @arg RCC_APB1Periph_TIM4 + * @arg RCC_APB1Periph_TIM6 + * @arg RCC_APB1Periph_TIM7 + * @arg RCC_APB1Periph_LCD + * @arg RCC_APB1Periph_WWDG + * @arg RCC_APB1Periph_SPI2 + * @arg RCC_APB1Periph_USART2 + * @arg RCC_APB1Periph_USART3 + * @arg RCC_APB1Periph_I2C1 + * @arg RCC_APB1Periph_I2C2 + * @arg RCC_APB1Periph_USB + * @arg RCC_APB1Periph_PWR + * @arg RCC_APB1Periph_DAC + * @arg RCC_APB1Periph_COMP + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the AHB peripheral clock during Low Power (SLEEP) mode. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA + * @arg RCC_AHBPeriph_GPIOB + * @arg RCC_AHBPeriph_GPIOC + * @arg RCC_AHBPeriph_GPIOD + * @arg RCC_AHBPeriph_GPIOE + * @arg RCC_AHBPeriph_GPIOH + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_DMA1 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBLPENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBLPENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the APB2 peripheral clock during Low Power (SLEEP) mode. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG + * @arg RCC_APB2Periph_TIM9 + * @arg RCC_APB2Periph_TIM10 + * @arg RCC_APB2Periph_TIM11 + * @arg RCC_APB2Periph_ADC1 + * @arg RCC_APB2Periph_SPI1 + * @arg RCC_APB2Periph_USART1 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2Periph; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the APB1 peripheral clock during Low Power (SLEEP) mode. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2 + * @arg RCC_APB1Periph_TIM3 + * @arg RCC_APB1Periph_TIM4 + * @arg RCC_APB1Periph_TIM6 + * @arg RCC_APB1Periph_TIM7 + * @arg RCC_APB1Periph_LCD + * @arg RCC_APB1Periph_WWDG + * @arg RCC_APB1Periph_SPI2 + * @arg RCC_APB1Periph_USART2 + * @arg RCC_APB1Periph_USART3 + * @arg RCC_APB1Periph_I2C1 + * @arg RCC_APB1Periph_I2C2 + * @arg RCC_APB1Periph_USB + * @arg RCC_APB1Periph_PWR + * @arg RCC_APB1Periph_DAC + * @arg RCC_APB1Periph_COMP + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1Periph; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCOSource_NoClock: No clock selected + * @arg RCC_MCOSource_SYSCLK: System clock selected + * @arg RCC_MCOSource_HSI: HSI oscillator clock selected + * @arg RCC_MCOSource_MSI: MSI oscillator clock selected + * @arg RCC_MCOSource_HSE: HSE oscillator clock selected + * @arg RCC_MCOSource_PLLCLK: PLL clock selected + * @arg RCC_MCOSource_LSI: LSI clock selected + * @arg RCC_MCOSource_LSE: LSE clock selected + * @param RCC_MCODiv: specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODiv_1: no division applied to MCO clock + * @arg RCC_MCODiv_2: division by 2 applied to MCO clock + * @arg RCC_MCODiv_4: division by 4 applied to MCO clock + * @arg RCC_MCODiv_8: division by 8 applied to MCO clock + * @arg RCC_MCODiv_16: division by 16 applied to MCO clock + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); + assert_param(IS_RCC_MCO_DIV(RCC_MCODiv)); + + /* Select MCO clock source and prescaler */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else /* The flag to check is in CSR register (tmp == 2) */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c new file mode 100644 index 0000000000..0d9bef1e20 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c @@ -0,0 +1,494 @@ +/** + ****************************************************************************** + * @file stm32l1xx_syscfg.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file provides all the SYSCFG and RI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_syscfg.h" +#include "stm32l1xx_rcc.h" + +/** @addtogroup STM32L1xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SYSCFG + * @brief SYSCFG driver modules + * @{ + */ + +/** @defgroup SYSCFG_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup SYSCFG_Private_Defines + * @{ + */ + +#define RI_ICR_RESET_VALUE ((uint32_t)0x00000000) /*!< ICR Reset value */ +#define RI_ASCR1_RESET_VALUE ((uint32_t)0x00000000) /*!< ASCR1 Reset value */ +#define RI_ASCR2_RESET_VALUE ((uint32_t)0x00000000) /*!< ASCR2 Reset value */ +#define RI_HYSCR1_RESET_VALUE ((uint32_t)0x00000000) /*!< HYSCR1 Reset value */ +#define RI_HYSCR2_RESET_VALUE ((uint32_t)0x00000000) /*!< HYSCR2 Reset value */ +#define RI_HYSCR3_RESET_VALUE ((uint32_t)0x00000000) /*!< HYSCR3 Reset value */ + +#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */ +#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup SYSCFG_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup SYSCFG_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup SYSCFG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the syscfg registers to their default reset values. + * @param None + * @retval None + * @ Note: MEMRMP bits are not reset by APB2 reset. + */ +void SYSCFG_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); +} + +/** + * @brief Changes the mapping of the specified pin. + * @param SYSCFG_Memory: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); + SYSCFG->MEMRMP = SYSCFG_MemoryRemap; +} + +/** + * @brief Control the internal pull-up on USB DP line. + * @param NewState: New state of the switch control mode. + * This parameter can be ENABLE: Connect internal pull-up on USB DP line. + * or DISABLE: Disconnect internal pull-up on USB DP line. + * @retval None + */ +void SYSCFG_USBPuCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Connect internal pull-up on USB DP line */ + SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU; + } + else + { + /* Disconnect internal pull-up on USB DP line */ + SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU); + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source + * for EXTI lines where x can be (A, B, C, D, E or H). + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * This parameter can be EXTI_PinSourcex where x can be (0..15) + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief Deinitializes the RI registers to their default reset values. + * @param None + * @retval None + */ +void SYSCFG_RIDeInit(void) +{ + RI->ICR = RI_ICR_RESET_VALUE; /*!< Set RI->ICR to reset value */ + RI->ASCR1 = RI_ASCR1_RESET_VALUE; /*!< Set RI->ASCR1 to reset value */ + RI->ASCR2 = RI_ASCR2_RESET_VALUE; /*!< Set RI->ASCR2 to reset value */ + RI->HYSCR1 = RI_HYSCR1_RESET_VALUE; /*!< Set RI->HYSCR1 to reset value */ + RI->HYSCR2 = RI_HYSCR2_RESET_VALUE; /*!< Set RI->HYSCR2 to reset value */ + RI->HYSCR3 = RI_HYSCR3_RESET_VALUE; /*!< Set RI->HYSCR3 to reset value */ +} + +/** + * @brief Configures the routing interface to select which Timer to be routed. + * @param TIM_Select: Timer select. + * This parameter can be one of the following values: + * @arg TIM_Select_None : No timer selected + * @arg TIM_Select_TIM2 : Timer 2 selected + * @arg TIM_Select_TIM3 : Timer 3 selected + * @arg TIM_Select_TIM4 : Timer 4 selected + * @retval None. + */ +void SYSCFG_RITIMSelect(uint32_t TIM_Select) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RI_TIM(TIM_Select)); + + /* Get the old register value */ + tmpreg = RI->ICR; + + /* Clear the TIMx select bits */ + tmpreg &= TIM_SELECT_MASK; + + /* Select the Timer */ + tmpreg |= (TIM_Select); + + /* Write to RI->ICR register */ + RI->ICR = tmpreg; +} + +/** + * @brief Configures the routing interface to select which Timer Input Capture + * to be routed to a selected pin. + * @param RI_InputCapture selects which input capture to be routed. + * This parameter can be one of the following values: + * @arg RI_InputCapture_IC1: Input capture 1 is slected. + * @arg RI_InputCapture_IC2: Input capture 2 is slected. + * @arg RI_InputCapture_IC3: Input capture 3 is slected. + * @arg RI_InputCapture_IC4: Input capture 4 is slected. + * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture. + * This parameter can be one of the following values: + * @arg RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15 + * @Note Input capture selection bits are not reset by this function. + * @retval None. + */ +void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture)); + assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting)); + + /* Get the old register value */ + tmpreg = RI->ICR; + + /* Select input captures to be routed */ + tmpreg |= (RI_InputCapture); + + if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1) + { + /* Clear the input capture select bits */ + tmpreg &= (uint32_t)(~IC_ROUTING_MASK); + + /* Set RI_InputCaptureRouting bits */ + tmpreg |= (uint32_t)( RI_InputCaptureRouting); + } + + if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2) + { + /* Clear the input capture select bits */ + tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4)); + + /* Set RI_InputCaptureRouting bits */ + tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); + } + + if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3) + { + /* Clear the input capture select bits */ + tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8)); + + /* Set RI_InputCaptureRouting bits */ + tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8)); + } + + if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4) + { + /* Clear the input capture select bits */ + tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12)); + + /* Set RI_InputCaptureRouting bits */ + tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12)); + } + + /* Write to RI->ICR register */ + RI->ICR = tmpreg; +} +/** + * @brief Configures the Pull-up and Pull-down Resistors + * @param RI_Resistor selects the resistor to connect. + * This parameter can be one of the following values: + * @arg RI_Resistor_10KPU : 10K pull-up resistor + * @arg RI_Resistor_400KPU : 400K pull-up resistor + * @arg RI_Resistor_10KPD : 10K pull-down resistor + * @arg RI_Resistor_400KPD : 400K pull-down resistor + * @param NewState: New state of the analog switch associated to the selected resistor. + * This parameter can be: + * ENABLE so the selected resistor is connected + * or DISABLE so the selected resistor is disconnected + * @retval None + */ +void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RI_RESISTOR(RI_Resistor)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the resistor */ + COMP->CSR |= (uint32_t) RI_Resistor; + } + else + { + /* Disable the Resistor */ + COMP->CSR &= (uint32_t) (~RI_Resistor); + } +} + +/** + * @brief Close or Open the routing interface Input Output switches. + * @param RI_IOSwitch: selects the I/O analog switch number. + * This parameter can be one of the following values: + * @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15 + * @argRI_IOSwitch_CH18 --> RI_IOSwitch_CH25 + * @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4 + * @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2 + * @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3 + * @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3 + * @arg RI_IOSwitch_VCOMP + * @param NewState: New state of the analog switch. + * This parameter can be + * ENABLE so the Input Output switch is closed + * or DISABLE so the Input Output switch is open + * @retval None + */ +void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState) +{ + uint32_t IOSwitchmask = 0; + + /* Check the parameters */ + assert_param(IS_RI_IOSWITCH(RI_IOSwitch)); + + /* Read Analog switch register index*/ + IOSwitchmask = RI_IOSwitch >> 28; + + /** Get Bits[27:0] of the IO switch */ + RI_IOSwitch &= 0x0FFFFFFF; + + + if (NewState != DISABLE) + { + if (IOSwitchmask != 0) + { + /* Close the analog switches */ + RI->ASCR1 |= RI_IOSwitch; + } + else + { + /* Open the analog switches */ + RI->ASCR2 |= RI_IOSwitch; + } + } + else + { + if (IOSwitchmask != 0) + { + /* Close the analog switches */ + RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch); + } + else + { + /* Open the analog switches */ + RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch); + } + } +} + +/** + * @brief Enable or disable the switch control mode. + * @param NewState: New state of the switch control mode. This parameter can + * be ENABLE: ADC analog switches closed if the corresponding + * I/O switch is also closed. + * or DISABLE: ADC analog switches open or controlled by the ADC interface. + * @retval None + */ +void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Switch control mode */ + RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM; + } + else + { + /* Disable the Switch control mode */ + RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM); + } +} + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E + * @param RI_Port: selects the GPIO Port. + * This parameter can be one of the following values: + * @arg RI_PortA : Port A is selected + * @arg RI_PortB : Port B is selected + * @arg RI_PortC : Port C is selected + * @arg RI_PortD : Port D is selected + * @arg RI_PortE : Port E is selected + * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All. + * @param NewState new state of the Hysteresis. + * This parameter can be: + * ENABLE so the Hysteresis is on + * or DISABLE so the Hysteresis is off + * @retval None + */ +void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, + FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RI_PORT(RI_Port)); + assert_param(IS_RI_PIN(RI_Pin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(RI_Port == RI_PortA) + { + if (NewState != DISABLE) + { + /* Hysteresis on */ + RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin); + } + else + { + /* Hysteresis off */ + RI->HYSCR1 |= (uint32_t) RI_Pin; + } + } + + else if(RI_Port == RI_PortB) + { + + if (NewState != DISABLE) + { + /* Hysteresis on */ + RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16); + } + else + { + /* Hysteresis off */ + RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16); + } + } + + else if(RI_Port == RI_PortC) + { + + if (NewState != DISABLE) + { + /* Hysteresis on */ + RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin)); + } + else + { + /* Hysteresis off */ + RI->HYSCR2 |= (uint32_t) (RI_Pin ); + } + } + else if(RI_Port == RI_PortD) + { + if (NewState != DISABLE) + { + /* Hysteresis on */ + RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16); + } + else + { + /* Hysteresis off */ + RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16); + + } + } + else /* RI_Port == RI_PortE */ + { + if (NewState != DISABLE) + { + /* Hysteresis on */ + RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin)); + } + else + { + /* Hysteresis off */ + RI->HYSCR3 |= (uint32_t) (RI_Pin ); + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s new file mode 100644 index 0000000000..8ede05b1a6 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s @@ -0,0 +1,459 @@ +;/******************** (C) COPYRIGHT 2010 STMicroelectronics ******************** +;* File Name : startup_stm32l15x_lp.s +;* Author : MCD Application Team +;* Version : V1.0.0RC1 +;* Date : 07/02/2010 +;* Description : STM32L15x Low Power Devices vector table for EWARM5.x toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN vPortSVCHandler + EXTERN xPortPendSVHandler + EXTERN xPortSysTickHandler + + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD vPortSVCHandler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD xPortPendSVHandler ; PendSV Handler + DCD xPortSysTickHandler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h new file mode 100644 index 0000000000..7d1cabdb00 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h @@ -0,0 +1,360 @@ +/** + ****************************************************************************** + * @file stm32_eval.h + * @author MCD Application Team + * @version V4.4.0RC1 + * @date 07/02/2010 + * @brief Header file for stm32_eval.c module. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_EVAL_H +#define __STM32_EVAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @defgroup STM32_EVAL_Abstraction_Layer + * @{ + */ + +/** @defgroup STM32_EVAL_HARDWARE_RESOURCES + * @{ + */ + +/** +@code + The table below gives an overview of the hardware resources supported by each + STM32 EVAL board. + - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI)) + - IOE: IO Expander on I2C + - sFLASH: serial SPI FLASH (M25Pxxx) + - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64) + - TSENSOR: Temperature Sensor (LM75) + - SD: SD Card memory (SPI and SDIO (SD Card MODE)) + =================================================================================================================+ + STM32 EVAL | LED | Buttons | Com Ports | LCD | IOE | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO) | + =================================================================================================================+ + STM3210B-EVAL | 4 | 8 | 2 | YES (SPI) | NO | YES | NO | YES | YES | NO | + -----------------------------------------------------------------------------------------------------------------+ + STM3210E-EVAL | 4 | 8 | 2 | YES (FSMC)| NO | YES | NO | YES | NO | YES | + -----------------------------------------------------------------------------------------------------------------+ + STM3210C-EVAL | 4 | 3 | 1 | YES (SPI) | YES | NO | YES | NO | YES | NO | + -----------------------------------------------------------------------------------------------------------------+ + STM32100B-EVAL | 4 | 8 | 2 | YES (SPI) | NO | YES | NO | YES | YES | NO | + -----------------------------------------------------------------------------------------------------------------+ + STM32L152-EVAL | 4 | 8 | 2 | YES (SPI) | NO | NO | NO | YES | YES | NO | + =================================================================================================================+ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup STM32_EVAL_Exported_Types + * @{ + */ +typedef enum +{ + LED1 = 0, + LED2 = 1, + LED3 = 2, + LED4 = 3 +} Led_TypeDef; + +typedef enum +{ + BUTTON_WAKEUP = 0, + BUTTON_TAMPER = 1, + BUTTON_KEY = 2, + BUTTON_RIGHT = 3, + BUTTON_LEFT = 4, + BUTTON_UP = 5, + BUTTON_DOWN = 6, + BUTTON_SEL = 7 +} Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +} ButtonMode_TypeDef; + +typedef enum +{ + JOY_NONE = 0, + JOY_SEL = 1, + JOY_DOWN = 2, + JOY_LEFT = 3, + JOY_RIGHT = 4, + JOY_UP = 5 +} JOYState_TypeDef +; + +typedef enum +{ + COM1 = 0, + COM2 = 1 +} COM_TypeDef; +/** + * @} + */ + +/** @defgroup STM32_EVAL_Exported_Constants + * @{ + */ + +/** + * @brief Uncomment the line corresponding to the STMicroelectronics evaluation + * board used in your application. + * + * Tip: To avoid modifying this file each time you need to switch between these + * boards, you can define the board in your toolchain compiler preprocessor. + */ +#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) && !defined (USE_STM3210E_EVAL)\ + && !defined (USE_STM3210C_EVAL) && !defined (USE_STM32L152_EVAL) + //#define USE_STM32100B_EVAL + //#define USE_STM3210B_EVAL + //#define USE_STM3210E_EVAL + //#define USE_STM3210C_EVAL + //#define USE_STM32L152_EVAL +#endif + +#ifdef USE_STM32100B_EVAL + #include "stm32f10x.h" + #include "stm32100b_eval/stm32100b_eval.h" +#elif defined USE_STM3210B_EVAL + #include "stm32f10x.h" + #include "stm3210b_eval/stm3210b_eval.h" +#elif defined USE_STM3210E_EVAL + #include "stm32f10x.h" + #include "stm3210e_eval/stm3210e_eval.h" +#elif defined USE_STM3210C_EVAL + #include "stm32f10x.h" + #include "stm3210c_eval/stm3210c_eval.h" +#elif defined USE_STM32L152_EVAL + #include "stm32l1xx.h" + #include "stm32l152_eval/stm32l152_eval.h" +#else + #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)" +#endif + + +/** + * @brief STM32 Button Defines Legacy + */ +#define Button_WAKEUP BUTTON_WAKEUP +#define Button_TAMPER BUTTON_TAMPER +#define Button_KEY BUTTON_KEY +#define Button_RIGHT BUTTON_RIGHT +#define Button_LEFT BUTTON_LEFT +#define Button_UP BUTTON_UP +#define Button_DOWN BUTTON_DOWN +#define Button_SEL BUTTON_SEL +#define Mode_GPIO BUTTON_MODE_GPIO +#define Mode_EXTI BUTTON_MODE_EXTI +#define Button_Mode_TypeDef ButtonMode_TypeDef +#define JOY_CENTER JOY_SEL +#define JOY_State_TypeDef JOYState_TypeDef + +/** + * @brief LCD Defines Legacy + */ +#define LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK +#define LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT +#define LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK +#define R0 LCD_REG_0 +#define R1 LCD_REG_1 +#define R2 LCD_REG_2 +#define R3 LCD_REG_3 +#define R4 LCD_REG_4 +#define R5 LCD_REG_5 +#define R6 LCD_REG_6 +#define R7 LCD_REG_7 +#define R8 LCD_REG_8 +#define R9 LCD_REG_9 +#define R10 LCD_REG_10 +#define R12 LCD_REG_12 +#define R13 LCD_REG_13 +#define R14 LCD_REG_14 +#define R15 LCD_REG_15 +#define R16 LCD_REG_16 +#define R17 LCD_REG_17 +#define R18 LCD_REG_18 +#define R19 LCD_REG_19 +#define R20 LCD_REG_20 +#define R21 LCD_REG_21 +#define R22 LCD_REG_22 +#define R23 LCD_REG_23 +#define R24 LCD_REG_24 +#define R25 LCD_REG_25 +#define R26 LCD_REG_26 +#define R27 LCD_REG_27 +#define R28 LCD_REG_28 +#define R29 LCD_REG_29 +#define R30 LCD_REG_30 +#define R31 LCD_REG_31 +#define R32 LCD_REG_32 +#define R33 LCD_REG_33 +#define R34 LCD_REG_34 +#define R36 LCD_REG_36 +#define R37 LCD_REG_37 +#define R40 LCD_REG_40 +#define R41 LCD_REG_41 +#define R43 LCD_REG_43 +#define R45 LCD_REG_45 +#define R48 LCD_REG_48 +#define R49 LCD_REG_49 +#define R50 LCD_REG_50 +#define R51 LCD_REG_51 +#define R52 LCD_REG_52 +#define R53 LCD_REG_53 +#define R54 LCD_REG_54 +#define R55 LCD_REG_55 +#define R56 LCD_REG_56 +#define R57 LCD_REG_57 +#define R59 LCD_REG_59 +#define R60 LCD_REG_60 +#define R61 LCD_REG_61 +#define R62 LCD_REG_62 +#define R63 LCD_REG_63 +#define R64 LCD_REG_64 +#define R65 LCD_REG_65 +#define R66 LCD_REG_66 +#define R67 LCD_REG_67 +#define R68 LCD_REG_68 +#define R69 LCD_REG_69 +#define R70 LCD_REG_70 +#define R71 LCD_REG_71 +#define R72 LCD_REG_72 +#define R73 LCD_REG_73 +#define R74 LCD_REG_74 +#define R75 LCD_REG_75 +#define R76 LCD_REG_76 +#define R77 LCD_REG_77 +#define R78 LCD_REG_78 +#define R79 LCD_REG_79 +#define R80 LCD_REG_80 +#define R81 LCD_REG_81 +#define R82 LCD_REG_82 +#define R83 LCD_REG_83 +#define R96 LCD_REG_96 +#define R97 LCD_REG_97 +#define R106 LCD_REG_106 +#define R118 LCD_REG_118 +#define R128 LCD_REG_128 +#define R129 LCD_REG_129 +#define R130 LCD_REG_130 +#define R131 LCD_REG_131 +#define R132 LCD_REG_132 +#define R133 LCD_REG_133 +#define R134 LCD_REG_134 +#define R135 LCD_REG_135 +#define R136 LCD_REG_136 +#define R137 LCD_REG_137 +#define R139 LCD_REG_139 +#define R140 LCD_REG_140 +#define R141 LCD_REG_141 +#define R143 LCD_REG_143 +#define R144 LCD_REG_144 +#define R145 LCD_REG_145 +#define R146 LCD_REG_146 +#define R147 LCD_REG_147 +#define R148 LCD_REG_148 +#define R149 LCD_REG_149 +#define R150 LCD_REG_150 +#define R151 LCD_REG_151 +#define R152 LCD_REG_152 +#define R153 LCD_REG_153 +#define R154 LCD_REG_154 +#define R157 LCD_REG_157 +#define R192 LCD_REG_192 +#define R193 LCD_REG_193 +#define R227 LCD_REG_227 +#define R229 LCD_REG_229 +#define R231 LCD_REG_231 +#define R239 LCD_REG_239 +#define White LCD_COLOR_WHITE +#define Black LCD_COLOR_BLACK +#define Grey LCD_COLOR_GREY +#define Blue LCD_COLOR_BLUE +#define Blue2 LCD_COLOR_BLUE2 +#define Red LCD_COLOR_RED +#define Magenta LCD_COLOR_MAGENTA +#define Green LCD_COLOR_GREEN +#define Cyan LCD_COLOR_CYAN +#define Yellow LCD_COLOR_YELLOW +#define Line0 LCD_LINE_0 +#define Line1 LCD_LINE_1 +#define Line2 LCD_LINE_2 +#define Line3 LCD_LINE_3 +#define Line4 LCD_LINE_4 +#define Line5 LCD_LINE_5 +#define Line6 LCD_LINE_6 +#define Line7 LCD_LINE_7 +#define Line8 LCD_LINE_8 +#define Line9 LCD_LINE_9 +#define Horizontal LCD_DIR_HORIZONTAL +#define Vertical LCD_DIR_VERTICAL + +/** + * @} + */ + +/** @defgroup STM32_EVAL_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32_EVAL_Exported_Functions + * @{ + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32_EVAL_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h new file mode 100644 index 0000000000..84dc2851b7 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_CONF_H +#define __STM32L1xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +/* #include "stm32l1xx_adc.h" */ +/* #include "stm32l1xx_crc.h" */ +/* #include "stm32l1xx_comp.h" */ +/* #include "stm32l1xx_dac.h" */ +/* #include "stm32l1xx_dbgmcu.h" */ +/* #include "stm32l1xx_dma.h" */ +#include "stm32l1xx_exti.h" +/* #include "stm32l1xx_flash.h" */ +#include "stm32l1xx_gpio.h" +#include "stm32l1xx_syscfg.h" +/* #include "stm32l1xx_i2c.h" */ +/* #include "stm32l1xx_iwdg.h" */ +/* #include "stm32l1xx_lcd.h" */ +/* #include "stm32l1xx_pwr.h" */ +#include "stm32l1xx_rcc.h" +/* #include "stm32l1xx_rtc.h" */ +#include "stm32l1xx_spi.h" +/* #include "stm32l1xx_tim.h" */ +#include "stm32l1xx_usart.h" +/* #include "stm32l1xx_wwdg.h" */ +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32L1xx_CONF_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf new file mode 100644 index 0000000000..ebca1e63ae --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c new file mode 100644 index 0000000000..5afcd2a10e --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_it.h" + + +/** @addtogroup Template_Project + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32L1xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32l1xx_md.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h new file mode 100644 index 0000000000..7eabc16b0f --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.h + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_IT_H +#define __STM32L1xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_IT_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c new file mode 100644 index 0000000000..e3881c1d58 --- /dev/null +++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c @@ -0,0 +1,934 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @version V1.0.0RC1 + * @date 07/02/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the MSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the MSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the MSI (2MHz default) is used as + System clock source. + + 4. The System clock configuration functions provided within this file assume that: + - For Ultra Low Power Medium Mensity devices an external 8MHz crystal is + used to drive the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +/* #define SYSCLK_FREQ_MSI */ + +#ifndef SYSCLK_FREQ_MSI +/* #define SYSCLK_FREQ_HSI HSI_VALUE */ +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_4MHz 4000000 */ +/* #define SYSCLK_FREQ_8MHz 8000000 */ +/* #define SYSCLK_FREQ_16MHz 16000000 */ +#define SYSCLK_FREQ_32MHz 32000000 +#else +/* #define SYSCLK_FREQ_MSI_64KHz 64000 */ +/* #define SYSCLK_FREQ_MSI_128KHz 128000 */ +/* #define SYSCLK_FREQ_MSI_256KHz 256000 */ +/* #define SYSCLK_FREQ_MSI_512KHz 512000 */ +/* #define SYSCLK_FREQ_MSI_1MHz 1000000 */ +/* #define SYSCLK_FREQ_MSI_2MHz 2000000 */ +/* #define SYSCLK_FREQ_MSI_4MHz 4000000 */ +#endif + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifndef SYSCLK_FREQ_MSI +#ifdef SYSCLK_FREQ_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_HSI; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_4MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_4MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_8MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_16MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_32MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_32MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< MSI Selected as System Clock source */ + uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif +#else +#ifdef SYSCLK_FREQ_MSI_64KHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_64KHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_MSI_128KHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_128KHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_MSI_256KHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_256KHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_MSI_512KHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_512KHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_MSI_1MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_1MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_MSI_2MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_2MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_MSI_4MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_4MHz; /*!< System Clock Frequency (Core Clock) */ +#else + uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif +#endif + +__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +__I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4}; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSI + static void SetSysClockToHSI(void); +#elif defined SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_4MHz + static void SetSysClockTo4(void); +#elif defined SYSCLK_FREQ_8MHz + static void SetSysClockTo8(void); +#elif defined SYSCLK_FREQ_16MHz + static void SetSysClockTo16(void); +#elif defined SYSCLK_FREQ_32MHz + static void SetSysClockTo32(void); +#else + static void SetSysClockToMSI(void); +#endif + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; + + /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /*!< Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note None + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000)); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: + SystemCoreClock = MSI_VALUE; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSI + SetSysClockToHSI(); +#elif defined SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_4MHz + SetSysClockTo4(); +#elif defined SYSCLK_FREQ_8MHz + SetSysClockTo8(); +#elif defined SYSCLK_FREQ_16MHz + SetSysClockTo16(); +#elif defined SYSCLK_FREQ_32MHz + SetSysClockTo32(); +#else + SetSysClockToMSI(); +#endif + + /* If none of the define above is enabled, the MSI (2MHz default) is used as + System clock source (default after reset) */ +} + +#ifdef SYSCLK_FREQ_HSI +/** + * @brief Selects HSI as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSI(void) +{ + __IO uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSI */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + StartUpCounter++; + } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != RESET) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + if (HSIStatus == (uint32_t)0x01) + { + /* Enable 64-bit access */ + FLASH->ACR |= FLASH_ACR_ACC64; + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 1 (1.8V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSI as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI; + + /* Wait till HSI is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSI fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + /* Disable Prefetch Buffer */ + FLASH->ACR &= ~FLASH_ACR_PRFTEN; + + /* Disable 64-bit access */ + FLASH->ACR &= ~FLASH_ACR_ACC64; + + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 2 (1.5V) */ + PWR->CR = PWR_CR_VOS_1; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_4MHz +/** + * @brief Sets System clock frequency to 4MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo4(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + /* Disable Prefetch Buffer */ + FLASH->ACR &= ~FLASH_ACR_PRFTEN; + + /* Disable 64-bit access */ + FLASH->ACR &= ~FLASH_ACR_ACC64; + + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 2 (1.5V) */ + PWR->CR = PWR_CR_VOS_1; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_8MHz +/** + * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo8(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + /* Disable Prefetch Buffer */ + FLASH->ACR &= ~FLASH_ACR_PRFTEN; + + /* Disable 64-bit access */ + FLASH->ACR &= ~FLASH_ACR_ACC64; + + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 2 (1.5V) */ + PWR->CR = PWR_CR_VOS_1; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_16MHz +/** + * @brief Sets System clock frequency to 16MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo16(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable 64-bit access */ + FLASH->ACR |= FLASH_ACR_ACC64; + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 2 (1.5V) */ + PWR->CR = PWR_CR_VOS_1; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | + RCC_CFGR_PLLDIV)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_32MHz +/** + * @brief Sets System clock frequency to 32MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo32(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable 64-bit access */ + FLASH->ACR |= FLASH_ACR_ACC64; + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 1 (1.8V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | + RCC_CFGR_PLLDIV)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#else +/** + * @brief Selects MSI as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToMSI(void) +{ + __IO uint32_t StartUpCounter = 0, MSIStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable MSI */ + RCC->CR |= ((uint32_t)RCC_CR_MSION); + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + MSIStatus = RCC->CR & RCC_CR_MSIRDY; + StartUpCounter++; + } while((MSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_MSIRDY) != RESET) + { + MSIStatus = (uint32_t)0x01; + } + else + { + MSIStatus = (uint32_t)0x00; + } + + if (MSIStatus == (uint32_t)0x01) + { +#ifdef SYSCLK_FREQ_MSI +#ifdef SYSCLK_FREQ_MSI_4MHz + /* Enable 64-bit access */ + FLASH->ACR |= FLASH_ACR_ACC64; + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; +#else + /* Flash 0 wait state */ + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + /* Disable Prefetch Buffer */ + FLASH->ACR &= ~FLASH_ACR_PRFTEN; + + /* Disable 64-bit access */ + FLASH->ACR &= ~FLASH_ACR_ACC64; +#endif +#endif + /* Enable the PWR APB1 Clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 3 (1.2V) */ + PWR->CR = PWR_CR_VOS; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef SYSCLK_FREQ_MSI + #ifdef SYSCLK_FREQ_MSI_64KHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_64KHz; + #elif defined SYSCLK_FREQ_MSI_128KHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_128KHz; + #elif defined SYSCLK_FREQ_MSI_256KHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_256KHz; + #elif defined SYSCLK_FREQ_MSI_512KHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_512KHz; + #elif defined SYSCLK_FREQ_MSI_1MHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_1MHz; + #elif defined SYSCLK_FREQ_MSI_2MHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_2MHz; + #elif defined SYSCLK_FREQ_MSI_4MHz + /* Set MSI clock range */ + RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE)); + RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_4MHz; + #endif +#endif + + /* Select MSI as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_MSI; + + /* Wait till MSI is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x00) + { + } + } + else + { + /* If MSI fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/