Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780)
Ming Yue
3 years ago
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GitHub
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# Emulating generic RISC-V 32bit machine on QEMU
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## Requirements
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1. GNU RISC-V toolchains (tested on pre-built Sifive GNU Embedded Toolchain — v2020.12.8)
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- https://www.sifive.com/software
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1. qemu-riscv32-system (tested on pre-built Sifive QEMU — v2020.08.1)
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- https://www.sifive.com/software
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1. Linux OS (tested on Ubuntu 20.04.3 LTS)
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## How to build
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Add path of toolchain that is described above section, such as:
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```
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$ export PATH="/YOUR_PATH/riscv64-unknown-elf/bin:${PATH}"
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```
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For release build:
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```
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$ make -C build/gcc/
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```
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For debug build:
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```
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$ make -C build/gcc/ DEBUG=1
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```
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To clean build artifacts:
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```
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$ make -C build/gcc/ clean
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```
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If the build was successful, the RTOSDemo.elf executable will be located in the build/gcc/output directory.
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## How to run
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```
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$ qemu-system-riscv32 -nographic -machine virt -net none \
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-chardev stdio,id=con,mux=on -serial chardev:con \
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-mon chardev=con,mode=readline -bios none \
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-smp 4 -kernel ./build/gcc/output/RTOSDemo.elf
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```
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## How to debug with gdb
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Append -s and -S options to the previous qemu command.
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- -s: enable to attach gdb to QEMU at port 1234
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- -S: start and halted CPU (wait for attach from gdb)
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It is recommended to use the 'debug build' so that gdb can automatically map symbols.
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Run these commands after starting the QEMU with above options:
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```
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$ riscv64-unknown-elf-gdb -x build/gcc/gdbinit
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```
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## Description
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This demo just prints Tx/Rx message of queue to serial port, use no
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other hardware and use only primary core (currently hart 0).
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Other cores are simply going to wfi state and execute nothing else.
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@ -0,0 +1,7 @@
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target remote localhost:1234
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set arch riscv:rv32
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set remotetimeout 250
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flushregs
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file ./output/RTOSDemo.elf
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load
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tb main
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@ -0,0 +1,62 @@
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/*
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* FreeRTOS V202112.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.balign 128, 0
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.option norvc
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.global freertos_vector_table
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freertos_vector_table:
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IRQ_0:
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j freertos_risc_v_exception_handler
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IRQ_1:
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j freertos_risc_v_interrupt_handler
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IRQ_2:
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j freertos_risc_v_interrupt_handler
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IRQ_3:
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j freertos_risc_v_interrupt_handler
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IRQ_4:
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j freertos_risc_v_interrupt_handler
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IRQ_5:
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j freertos_risc_v_interrupt_handler
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IRQ_6:
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j freertos_risc_v_interrupt_handler
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IRQ_7:
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j freertos_risc_v_mtimer_interrupt_handler
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IRQ_8:
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j freertos_risc_v_interrupt_handler
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IRQ_9:
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j freertos_risc_v_interrupt_handler
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IRQ_10:
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j freertos_risc_v_interrupt_handler
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IRQ_11:
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j freertos_risc_v_interrupt_handler
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IRQ_12:
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j freertos_risc_v_interrupt_handler
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IRQ_13:
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j freertos_risc_v_interrupt_handler
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IRQ_14:
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j freertos_risc_v_interrupt_handler
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IRQ_15:
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j freertos_risc_v_interrupt_handler
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@ -1 +1 @@
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Subproject commit 9efca75d1ebfc6c02f9e004c199dffa327267a09
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Subproject commit d5a10e45958148d437ae5096835a118be58e6df9
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