diff --git a/Demo/ARM7_STR75x_IAR/75x_init.s b/Demo/ARM7_STR75x_IAR/75x_init.s new file mode 100644 index 0000000000..a4b018b670 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/75x_init.s @@ -0,0 +1,249 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 75x_init.s +;* Author : MCD Application Team +;* Date First Issued : 03/10/2006 +;* Description : This module performs: +;* - Memory remapping (if required), +;* - Stack pointer initialisation for each mode , +;* - Interrupt Controller Initialisation +;* - Branches to ?main in the C library (which eventually +;* calls main()). +;* On reset, the ARM core starts up in Supervisor (SVC) mode, +;* in ARM state,with IRQ and FIQ disabled. +;******************************************************************************* +; History: +; 07/17/2006 : V1.0 +; 03/10/2006 : V0.1 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + + IMPORT WAKUP_Addr ; imported from 75x_vect.s + + + + + ; Depending on Your Application, Disable or Enable the following Defines + ; ---------------------------------------------------------------------------- + ; SMI Bank0 configuration + ; ---------------------------------------------------------------------------- + ; If you need to accees the SMI Bank0 + ; uncomment next line + ;#define SMI_Bank0_EN + + ; ---------------------------------------------------------------------------- + ; Memory remapping + ; ---------------------------------------------------------------------------- + ;#define Remap_SRAM ; remap SRAM at address 0x00 + + ; ---------------------------------------------------------------------------- + ; EIC initialization + ; ---------------------------------------------------------------------------- + #define EIC_INIT ; Configure and Initialize EIC + +; Standard definitions of mode bits and interrupt (I & F) flags in PSRs +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; MRCC Register +MRCC_PCLKEN_Addr EQU 0x60000030 ; Peripheral Clock Enable register base address + +; CFG Register +CFG_GLCONF_Addr EQU 0x60000010 ; Global Configuration register base address +SRAM_mask EQU 0x0002 ; to remap RAM at 0x0 + +; GPIO Register +GPIOREMAP0R_Addr EQU 0xFFFFE420 +SMI_EN_Mask EQU 0x00000001 + +; SMI Register +SMI_CR1_Addr EQU 0x90000000 + +; EIC Registers offsets +EIC_Base_addr EQU 0xFFFFF800 ; EIC base address +ICR_off_addr EQU 0x00 ; Interrupt Control register offset +CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset +IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset +FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset +IER_off_addr EQU 0x20 ; Interrupt Enable Register offset +IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset +SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0 + + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + RSEG IRQ_STACK:DATA(2) + RSEG FIQ_STACK:DATA(2) + RSEG UND_STACK:DATA(2) + RSEG ABT_STACK:DATA(2) + RSEG SVC_STACK:DATA(2) + RSEG CSTACK:DATA(2) + RSEG ICODE:CODE(2) + PUBLIC __program_start + EXTERN ?main + CODE32 + + +__program_start: + LDR pc, =NextInst + +NextInst +; Reset all Peripheral Clocks +; This is usefull only when using debugger to Reset\Run the application + + #ifdef SMI_Bank0_EN + LDR r0, =0x01000000 ; Disable peripherals clock (except GPIO) + #else + LDR r0, =0x00000000 ; Disable peripherals clock + #endif + LDR r1, =MRCC_PCLKEN_Addr + STR r0, [r1] + + #ifdef SMI_Bank0_EN + LDR r0, =0x1875623F ; Peripherals kept under reset (except GPIO) + #else + LDR r0, =0x1975623F ; Peripherals kept under reset + #endif + + STR r0, [r1,#4] + MOV r0, #0 + NOP ; Wait + NOP + NOP + NOP + STR r0, [r1,#4] ; Disable peripherals reset + +; Initialize stack pointer registers +; Enter each mode in turn and set up the stack pointer + + + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(FIQ_STACK) & 0xFFFFFFF8 ; End of FIQ_STACK + + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK + + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(ABT_STACK) & 0xFFFFFFF8 ; End of ABT_STACK + + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(UND_STACK) & 0xFFFFFFF8 ; End of UND_STACK + + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of SVC_STACK + +; ------------------------------------------------------------------------------ +; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register, +; enable SMI alternate function in GPIO_REMAP register and enable +; Bank0 in SMI_CR1 register. +; ------------------------------------------------------------------------------ + #ifdef SMI_Bank0_EN + MOV r0, #0x01000000 + LDR r1, =MRCC_PCLKEN_Addr + STR r0, [r1] ; Enable GPIOs clock + + LDR r1, =GPIOREMAP0R_Addr + MOV r0, #SMI_EN_Mask + LDR r2, [r1] + ORR r2, r2, r0 + STR r2, [r1] ; Enable SMI alternate function + + LDR r0, =0x251 ; SMI Bank0 enabled, Prescaler = 2, Deselect Time = 5 + LDR r1, =SMI_CR1_Addr + STR r0, [r1] ; Configure CR1 register + LDR r0, =0x00 + STR r0, [r1,#4] ; Reset CR2 register + #endif + +; ------------------------------------------------------------------------------ +; Description : Remapping SRAM at address 0x00 after the application has +; started executing. +; ------------------------------------------------------------------------------ + #ifdef Remap_SRAM + MOV r0, #SRAM_mask + LDR r1, =CFG_GLCONF_Addr + LDR r2, [r1] ; Read GLCONF Register + BIC r2, r2, #0x03 ; Reset the SW_BOOT bits + ORR r2, r2, r0 ; Change the SW_BOOT bits + STR r2, [r1] ; Write GLCONF Register + #endif + +;------------------------------------------------------------------------------- +;Description : Initialize the EIC as following : +; - IRQ disabled +; - FIQ disabled +; - IVR contains the load PC opcode +; - All channels are disabled +; - All channels priority equal to 0 +; - All SIR registers contains offset to the related IRQ table entry +;------------------------------------------------------------------------------- + #ifdef EIC_INIT + LDR r3, =EIC_Base_addr + LDR r4, =0x00000000 + STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ + STR r4, [r3, #IER_off_addr] ; Disable all interrupts channels + + LDR r4, =0xFFFFFFFF + STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits + + LDR r4, =0x18 + STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits + + LDR r4, =0x00000000 + STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register + + LDR r4, =0xE59F0000 ; Write the LDR pc,pc,#offset.. + STR r4, [r3, #IVR_off_addr] ; ..instruction code in IVR[31:16] + + + LDR r2,= 32 ; 32 Channel to initialize + LDR r0, =WAKUP_Addr ; Read the address of the IRQs address table + LDR r1, =0x00000FFF + AND r0,r0,r1 + LDR r5,=SIR0_off_addr ; Read SIR0 address + SUB r4,r0,#8 ; subtract 8 for prefetch + LDR r1, =0xF7E8 ; add the offset to the 0x00 address.. + ; ..(IVR address + 7E8 = 0x00) + ; 0xF7E8 used to complete the LDR pc,offset opcode + ADD r1,r4,r1 ; compute the jump offset +EIC_INI + MOV r4, r1, LSL #16 ; Left shift the result + STR r4, [r3, r5] ; Store the result in SIRx register + ADD r1, r1, #4 ; Next IRQ address + ADD r5, r5, #4 ; Next SIR + SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize + BNE EIC_INI ; If more then continue + + #endif + + +; --- Branch to C Library entry point + + IMPORT ?main + + B ?main ; use B not BL, because an application will never return this way + + + + + LTORG + + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE***** diff --git a/Demo/ARM7_STR75x_IAR/75x_vect.s b/Demo/ARM7_STR75x_IAR/75x_vect.s new file mode 100644 index 0000000000..991bda794f --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/75x_vect.s @@ -0,0 +1,882 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 75x_vect.c +;* Author : MCD Application Team +;* Date First Issued : 03/10/2006 +;* Description : This file used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions handlers. +;******************************************************************************* +; History: +; 07/17/2006 : V1.0 +; 03/10/2006 : V0.1 +;******************************************************************************* +;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + + PROGRAM ?RESET + COMMON INTVEC:CODE(2) + CODE32 + +EIC_base_addr EQU 0xFFFFF800 ; EIC base address +CICR_off_addr EQU 0x04 ; Current Interrupt Channel Register +IVR_off_addr EQU 0x18 ; Interrupt Vector Register +IPR_off_addr EQU 0x40 ; Interrupt Pending Register + + +;******************************************************************************* +; Import the __program_start address from 75x_init.s +;******************************************************************************* + + IMPORT __program_start + + + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT Undefined_Handler + IMPORT SWI_Handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT FIQ_Handler + +;******************************************************************************* +; Import IRQ handlers from 75x_it.c +;******************************************************************************* + + IMPORT WAKUP_IRQHandler + IMPORT TIM2_OC2_IRQHandler + IMPORT TIM2_OC1_IRQHandler + IMPORT TIM2_IC12_IRQHandler + IMPORT TIM2_UP_IRQHandler + IMPORT TIM1_OC2_IRQHandler + IMPORT TIM1_OC1_IRQHandler + IMPORT TIM1_IC12_IRQHandler + IMPORT TIM1_UP_IRQHandler + IMPORT TIM0_OC2_IRQHandler + IMPORT TIM0_OC1_IRQHandler + IMPORT TIM0_IC12_IRQHandler + IMPORT TIM0_UP_IRQHandler + IMPORT PWM_OC123_IRQHandler + IMPORT PWM_EM_IRQHandler + IMPORT PWM_UP_IRQHandler + IMPORT I2C_IRQHandler + IMPORT SSP1_IRQHandler + IMPORT SSP0_IRQHandler + IMPORT UART2_IRQHandler + IMPORT UART1_IRQHandler + IMPORT vSerialISR + IMPORT CAN_IRQHandler + IMPORT USB_LP_IRQHandler + IMPORT USB_HP_IRQHandler + IMPORT ADC_IRQHandler + IMPORT DMA_IRQHandler + IMPORT EXTIT_IRQHandler + IMPORT MRCC_IRQHandler + IMPORT FLASHSMI_IRQHandler + IMPORT RTC_IRQHandler + IMPORT TB_IRQHandler + IMPORT vPortPreemptiveTick + IMPORT vPortYieldProcessor + IMPORT UART0_IRQHandler + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + + EXPORT WAKUP_Addr + +;******************************************************************************* +; Exception vectors +;******************************************************************************* + + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD IRQHandler +FIQ_Addr DCD FIQHandler + +;******************************************************************************* +; Peripherals IRQ handlers address table +;******************************************************************************* + +WAKUP_Addr DCD WAKUPIRQHandler +TIM2_OC2_Addr DCD TIM2_OC2IRQHandler +TIM2_OC1_Addr DCD TIM2_OC1IRQHandler +TIM2_IC12_Addr DCD TIM2_IC12IRQHandler +TIM2_UP_Addr DCD TIM2_UPIRQHandler +TIM1_OC2_Addr DCD TIM1_OC2IRQHandler +TIM1_OC1_Addr DCD TIM1_OC1IRQHandler +TIM1_IC12_Addr DCD TIM1_IC12IRQHandler +TIM1_UP_Addr DCD TIM1_UPIRQHandler +TIM0_OC2_Addr DCD TIM0_OC2IRQHandler +TIM0_OC1_Addr DCD TIM0_OC1IRQHandler +TIM0_IC12_Addr DCD TIM0_IC12IRQHandler +TIM0_UP_Addr DCD TIM0_UPIRQHandler +PWM_OC123_Addr DCD PWM_OC123IRQHandler +PWM_EM_Addr DCD PWM_EMIRQHandler +PWM_UP_Addr DCD PWM_UPIRQHandler +I2C_Addr DCD I2CIRQHandler +SSP1_Addr DCD SSP1IRQHandler +SSP0_Addr DCD SSP0IRQHandler +UART2_Addr DCD UART2IRQHandler +UART1_Addr DCD UART1IRQHandler +UART0_Addr DCD vSerialISR +CAN_Addr DCD CANIRQHandler +USB_LP_Addr DCD USB_LPIRQHandler +USB_HP_Addr DCD USB_HPIRQHandler +ADC_Addr DCD ADCIRQHandler +DMA_Addr DCD DMAIRQHandler +EXTIT_Addr DCD EXTITIRQHandler +MRCC_Addr DCD MRCCIRQHandler +FLASHSMI_Addr DCD FLASHSMIIRQHandler +RTC_Addr DCD RTCIRQHandler +TB_Addr DCD vPortPreemptiveTick + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + +;******************************************************************************* +;* Macro Name : SaveContext +;* Description : This macro used to save the context before entering +;* an exception handler. +;* Input : The range of registers to store. +;* Output : none +;******************************************************************************* +SaveContext MACRO reg1,reg2 + STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return + ; address lr_ mode into the stack. + MRS r1,spsr ; Save the spsr_mode into r1. + STMFD sp!,{r1} ; Save spsr. + ENDM + +;******************************************************************************* +;* Macro Name : RestoreContext +;* Description : This macro used to restore the context to return from +;* an exception handler and continue the program execution. +;* Input : The range of registers to restore. +;* Output : none +;******************************************************************************* +RestoreContext MACRO reg1,reg2 + LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. + MSR spsr_cxsf,r1 ; Restore spsr_mode. + LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... + ; ...the exception interrupt. + ENDM + +;******************************************************************************* +;* Function Name : UndefinedHandler +;* Description : This function called when undefined instruction exception +;* is entered. +;* Input : none +;* Output : none +;******************************************************************************* +UndefinedHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ und and spsr_und. + ldr r0,=Undefined_Handler + ldr lr,=Undefined_Handler_end + bx r0 ;Branch to Undefined_Handler +Undefined_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the undefined instruction. + +;******************************************************************************* +;* Function Name : SWIHandler +;* Description : This function called when SWI instruction executed. +;* Input : none +;* Output : none +;******************************************************************************* +SWIHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ svc and spsr_svc. + ldr r0,= SWI_Handler + ldr lr,= SWI_Handler_end + bx r0 ;Branch to SWI_Handler +SWI_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the SWI instruction. + +;******************************************************************************* +;* Function Name : IRQHandler +;* Description : This function called when IRQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +IRQHandler + portSAVE_CONTEXT ; Save the context of the current task. + + LDR r0, =EIC_base_addr + LDR r1, =IVR_off_addr + LDR lr, =ReturnAddress ; Load the return address. + ADD pc,r0,r1 ; Branch to the IRQ handler. +ReturnAddress + LDR r0, =EIC_base_addr + LDR r2, [r0, #CICR_off_addr] ; Get the IRQ channel number + MOV r3,#1 + MOV r3,r3,LSL r2 + STR r3,[r0, #IPR_off_addr] ; Clear the corresponding IPR bit. + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + +;******************************************************************************* +;* Function Name : PrefetchAbortHandler +;* Description : This function called when Prefetch Abort exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +PrefetchAbortHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r7 ; Save the workspace plus the current + ; return address lr_abt and spsr_abt. + ldr r0,= Prefetch_Handler + ldr lr,= Prefetch_Handler_end + bx r0 ;Branch to Prefetch_Handler +Prefetch_Handler_end: + RestoreContext r0,r7 ; Return to the instruction following that... + ; ...has generated the prefetch abort exception. + +;******************************************************************************* +;* Function Name : DataAbortHandler +;* Description : This function is called when Data Abort exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +DataAbortHandler + SUB lr,lr,#8 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ abt and spsr_abt. + ldr r0,= Abort_Handler + ldr lr,= Abort_Handler_end + bx r0 ;Branch to Abort_Handler +Abort_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the data abort exception. + +;******************************************************************************* +;* Function Name : FIQHandler +;* Description : This function is called when FIQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +FIQHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r7 ; Save the workspace plus the current + ; return address lr_ fiq and spsr_fiq. + ldr r0,= FIQ_Handler + ldr lr,= FIQ_Handler_end + bx r0 ;Branch to FIQ_Handler +FIQ_Handler_end: + RestoreContext r0,r7 ; Restore the context and return to the... + ; ...program execution. + +;******************************************************************************* +;* Macro Name : IRQ_to_SYS +;* Description : This macro used to switch form IRQ mode to SYS mode. +;* Input : none. +;* Output : none +;******************************************************************************* +IRQ_to_SYS MACRO + MSR cpsr_c,#0x1F + STMFD sp!,{lr} + ENDM + +;******************************************************************************* +;* Macro Name : SYS_to_IRQ +;* Description : This macro used to switch from SYS mode to IRQ mode. +;* Input : none. +;* Output : none +;******************************************************************************* +SYS_to_IRQ MACRO + LDMFD sp!,{lr} + MSR cpsr_c,#0xD2 + MOV pc,lr + ENDM + +;******************************************************************************* +;* Function Name : WAKUPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the WAKUP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the WAKUP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +WAKUPIRQHandler + IRQ_to_SYS + ldr r0,=WAKUP_IRQHandler + ldr lr,=WAKUP_IRQHandler_end + bx r0 +WAKUP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_OC2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_OC2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_OC2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_OC2IRQHandler + IRQ_to_SYS + ldr r0,=TIM2_OC2_IRQHandler + ldr lr,=TIM2_OC2_IRQHandler_end + bx r0 +TIM2_OC2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_OC1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_OC1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_OC1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_OC1IRQHandler + IRQ_to_SYS + ldr r0,=TIM2_OC1_IRQHandler + ldr lr,=TIM2_OC1_IRQHandler_end + bx r0 +TIM2_OC1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_IC12IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_IC12_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_IC12_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_IC12IRQHandler + IRQ_to_SYS + ldr r0,=TIM2_IC12_IRQHandler + ldr lr,=TIM2_IC12_IRQHandler_end + bx r0 +TIM2_IC12_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_UPIRQHandler + IRQ_to_SYS + ldr r0,=TIM2_UP_IRQHandler + ldr lr,=TIM2_UP_IRQHandler_end + bx r0 +TIM2_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_OC2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_OC2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_OC2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_OC2IRQHandler + IRQ_to_SYS + ldr r0,=TIM1_OC2_IRQHandler + ldr lr,=TIM1_OC2_IRQHandler_end + bx r0 +TIM1_OC2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_OC1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_OC1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_OC1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_OC1IRQHandler + IRQ_to_SYS + ldr r0,=TIM1_OC1_IRQHandler + ldr lr,=TIM1_OC1_IRQHandler_end + bx r0 +TIM1_OC1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_IC12IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_IC12_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_IC12_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_IC12IRQHandler + IRQ_to_SYS + ldr r0,=TIM1_IC12_IRQHandler + ldr lr,=TIM1_IC12_IRQHandler_end + bx r0 +TIM1_IC12_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_UPIRQHandler + IRQ_to_SYS + ldr r0,=TIM1_UP_IRQHandler + ldr lr,=TIM1_UP_IRQHandler_end + bx r0 +TIM1_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_OC2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_OC2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_OC2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_OC2IRQHandler + IRQ_to_SYS + ldr r0,=TIM0_OC2_IRQHandler + ldr lr,=TIM0_OC2_IRQHandler_end + bx r0 +TIM0_OC2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_OC1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_OC1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_OC1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_OC1IRQHandler + IRQ_to_SYS + ldr r0,=TIM0_OC1_IRQHandler + ldr lr,=TIM0_OC1_IRQHandler_end + bx r0 +TIM0_OC1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_IC12IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_IC12_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_IC12_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_IC12IRQHandler + IRQ_to_SYS + ldr r0,=TIM0_IC12_IRQHandler + ldr lr,=TIM0_IC12_IRQHandler_end + bx r0 +TIM0_IC12_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_UPIRQHandler + IRQ_to_SYS + ldr r0,=TIM0_UP_IRQHandler + ldr lr,=TIM0_UP_IRQHandler_end + bx r0 +TIM0_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : PWM_OC123IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the PWM_OC123_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the PWM_OC123_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +PWM_OC123IRQHandler + IRQ_to_SYS + ldr r0,=PWM_OC123_IRQHandler + ldr lr,=PWM_OC123_IRQHandler_end + bx r0 +PWM_OC123_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : PWM_EMIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the PWM_EM_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the PWM_EM_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +PWM_EMIRQHandler + IRQ_to_SYS + ldr r0,=PWM_EM_IRQHandler + ldr lr,=PWM_EM_IRQHandler_end + bx r0 +PWM_EM_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : PWM_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the PWM_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the PWM_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +PWM_UPIRQHandler + IRQ_to_SYS + ldr r0,=PWM_UP_IRQHandler + ldr lr,=PWM_UP_IRQHandler_end + bx r0 +PWM_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : I2CIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the I2C_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the I2C_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +I2CIRQHandler + IRQ_to_SYS + ldr r0,=I2C_IRQHandler + ldr lr,=I2C_IRQHandler_end + bx r0 +I2C_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : SSP1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the SSP1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the SSP1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +SSP1IRQHandler + IRQ_to_SYS + ldr r0,=SSP1_IRQHandler + ldr lr,=SSP1_IRQHandler_end + bx r0 +SSP1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : SSP0IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the SSP0_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the SSP0_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +SSP0IRQHandler + IRQ_to_SYS + ldr r0,=SSP0_IRQHandler + ldr lr,=SSP0_IRQHandler_end + bx r0 +SSP0_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : UART2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the UART2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the UART2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +UART2IRQHandler + IRQ_to_SYS + ldr r0,=UART2_IRQHandler + ldr lr,=UART2_IRQHandler_end + bx r0 +UART2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : UART1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the UART1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the UART1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +UART1IRQHandler + IRQ_to_SYS + ldr r0,=UART1_IRQHandler + ldr lr,=UART1_IRQHandler_end + bx r0 +UART1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : UART0IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the UART0_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the UART0_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +UART0IRQHandler + IRQ_to_SYS + ldr r0,=UART0_IRQHandler + ldr lr,=UART0_IRQHandler_end + bx r0 +UART0_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : CANIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the CAN_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the CAN_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +CANIRQHandler + IRQ_to_SYS + ldr r0,=CAN_IRQHandler + ldr lr,=CAN_IRQHandler_end + bx r0 +CAN_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : USB_LPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the USB_LP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the USB_LP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +USB_LPIRQHandler + IRQ_to_SYS + ldr r0,=USB_LP_IRQHandler + ldr lr,=USB_LP_IRQHandler_end + bx r0 +USB_LP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : USB_HPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the USB_HP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the USB_HP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +USB_HPIRQHandler + IRQ_to_SYS + ldr r0,=USB_HP_IRQHandler + ldr lr,=USB_HP_IRQHandler_end + bx r0 +USB_HP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : ADCIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the ADC_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the ADC_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +ADCIRQHandler + IRQ_to_SYS + ldr r0,=ADC_IRQHandler + ldr lr,=ADC_IRQHandler_end + bx r0 +ADC_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : DMAIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the DMA_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the DMA_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +DMAIRQHandler + IRQ_to_SYS + ldr r0,=DMA_IRQHandler + ldr lr,=DMA_IRQHandler_end + bx r0 +DMA_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : EXTITIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the EXTIT_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the EXTIT_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +EXTITIRQHandler + IRQ_to_SYS + ldr r0,=EXTIT_IRQHandler + ldr lr,=EXTIT_IRQHandler_end + bx r0 +EXTIT_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : MRCCIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the MRCC_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the MRCC_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +MRCCIRQHandler + IRQ_to_SYS + ldr r0,=MRCC_IRQHandler + ldr lr,=MRCC_IRQHandler_end + bx r0 +MRCC_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : FLASHSMIIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the FLASHSMI_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the FLASHSMI_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +FLASHSMIIRQHandler + IRQ_to_SYS + ldr r0,=FLASHSMI_IRQHandler + ldr lr,=FLASHSMI_IRQHandler_end + bx r0 +FLASHSMI_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : RTCIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the RTC_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the RTC_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +RTCIRQHandler + IRQ_to_SYS + ldr r0,=RTC_IRQHandler + ldr lr,=RTC_IRQHandler_end + bx r0 +RTC_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TBIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TB_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TB_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +TBIRQHandler + IRQ_to_SYS + ldr r0,=TB_IRQHandler + ldr lr,=TB_IRQHandler_end + bx r0 +TB_IRQHandler_end: + SYS_to_IRQ + + LTORG + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE***** + + + + + + + + + + + diff --git a/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h b/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h new file mode 100644 index 0000000000..e0ee52dcb3 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h @@ -0,0 +1,75 @@ +/* + FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* Timer clock. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 12800 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c b/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c new file mode 100644 index 0000000000..eaf16a1e7d --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c @@ -0,0 +1,147 @@ +/* + FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Library includes. */ +#include "75x_GPIO.h" +#include "75x_map.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's - which are + * connected to the second nibble of GPIO port 1. + *-----------------------------------------------------------*/ + +#define partstLED_3 0x0080 +#define partstLED_2 0x0040 +#define partstLED_1 0x0020 +#define partstLED_0 0x0010 +#define partstON_BOARD 0x0100 /* The LED built onto the KickStart board. */ + +#define partstALL_LEDs ( partstLED_0 | partstLED_1 | partstLED_2 | partstLED_3 | partstON_BOARD ) + +#define partstFIRST_LED_BIT 4 + +/* This demo application uses files that are common to all port demo +applications. These files assume 6 LED's are available, whereas I have +only 5 (including the LED built onto the development board). To prevent +two tasks trying to use the same LED a bit of remapping is performed. +The ComTest tasks will try and use LED's 6 and 7. LED 6 is ignored and +has no effect, LED 7 is mapped to LED3. The LED usage is described in +the port documentation available from the FreeRTOS.org WEB site. */ +#define partstCOM_TEST_LED 7 +#define partstRX_CHAR_LED 3 + +#define partstNUM_LEDS 4 + +typedef struct GPIOMAP +{ + GPIO_TypeDef *pxPort; + unsigned portLONG ulPin; + unsigned portLONG ulValue; +} GPIO_MAP; + +static GPIO_MAP xLEDMap[ partstNUM_LEDS ] = +{ + { ( GPIO_TypeDef * )GPIO1_BASE, GPIO_Pin_1, 0UL }, + { ( GPIO_TypeDef * )GPIO0_BASE, GPIO_Pin_16, 0UL }, + { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_18, 0UL }, + { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_19, 0UL } + +}; + +/*-----------------------------------------------------------*/ +GPIO_InitTypeDef GPIO_InitStructure ; + +void vParTestInitialise( void ) +{ + /* Configure the bits used to flash LED's on port 1 as output. */ + /* Configure LED3 */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16; + GPIO_Init(GPIO0,&GPIO_InitStructure); + /* Configure LED2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIO1, &GPIO_InitStructure); + /* Configure LED4 and LED5 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_18 | GPIO_Pin_19; + GPIO_Init(GPIO2, &GPIO_InitStructure); + + vParTestSetLED( 0, 0 ); + vParTestSetLED( 1, 0 ); + vParTestSetLED( 2, 0 ); + vParTestSetLED( 3, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED < partstNUM_LEDS ) + { + if( xValue ) + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); + xLEDMap[ uxLED ].ulValue = 0; + } + else + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); + xLEDMap[ uxLED ].ulValue = 1; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < partstNUM_LEDS ) + { + if( xLEDMap[ uxLED ].ulValue == 1 ) + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); + xLEDMap[ uxLED ].ulValue = 0; + } + else + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); + xLEDMap[ uxLED ].ulValue = 1; + } + } +} + + + + diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd new file mode 100644 index 0000000000..77da49bb25 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd @@ -0,0 +1,1043 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\stack.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + + + Release + + ARM + + 1 + + C-SPY + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 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+1,1741 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 1 + + General + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\Demo\source\75x_it.c + + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\Demo\source\lcd.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\serial\serial.c + + + + Library Source + + $PROJ_DIR$\STLibrary\src\75x_cfg.c + + + $PROJ_DIR$\STLibrary\src\75x_eic.c + + + $PROJ_DIR$\STLibrary\src\75x_gpio.c + + + $PROJ_DIR$\STLibrary\src\75x_lib.c + + + $PROJ_DIR$\STLibrary\src\75x_mrcc.c + + + $PROJ_DIR$\STLibrary\src\75x_tb.c + + + $PROJ_DIR$\STLibrary\src\75x_uart.c + + + + RTOS Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR75x\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR75x\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + startup + + $PROJ_DIR$\75x_init.s + + + $PROJ_DIR$\75x_vect.s + + + + + diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.eww b/Demo/ARM7_STR75x_IAR/RTOSDemo.eww new file mode 100644 index 0000000000..239a9381ec --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h new file mode 100644 index 0000000000..bce23f731d --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_adc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* ADC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_ADC_H +#define __75x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ADC Init structure definition */ +typedef struct +{ + u16 ADC_ConversionMode; + u16 ADC_ExtTrigger; + u16 ADC_AutoClockOff; + u8 ADC_SamplingPrescaler; + u8 ADC_ConversionPrescaler; + u8 ADC_FirstChannel; + u8 ADC_ChannelNumber; + }ADC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* ADC control status flags */ +#define ADC_FLAG_ECH 0x0001 +#define ADC_FLAG_EOC 0x0002 +#define ADC_FLAG_JECH 0x0004 +#define ADC_FLAG_JEOC 0x0008 +#define ADC_FLAG_AnalogWatchdog0_LowThreshold 0x0010 +#define ADC_FLAG_AnalogWatchdog0_HighThreshold 0x0020 +#define ADC_FLAG_AnalogWatchdog1_LowThreshold 0x0040 +#define ADC_FLAG_AnalogWatchdog1_HighThreshold 0x0080 +#define ADC_FLAG_AnalogWatchdog2_LowThreshold 0x0100 +#define ADC_FLAG_AnalogWatchdog2_HighThreshold 0x0200 +#define ADC_FLAG_AnalogWatchdog3_LowThreshold 0x0400 +#define ADC_FLAG_AnalogWatchdog3_HighThreshold 0x0800 + +/* ADC Interrupt sources */ +#define ADC_IT_ECH 0x0001 +#define ADC_IT_EOC 0x0002 +#define ADC_IT_JECH 0x0004 +#define ADC_IT_JEOC 0x0008 +#define ADC_IT_AnalogWatchdog0_LowThreshold 0x0010 +#define ADC_IT_AnalogWatchdog0_HighThreshold 0x0020 +#define ADC_IT_AnalogWatchdog1_LowThreshold 0x0040 +#define ADC_IT_AnalogWatchdog1_HighThreshold 0x0080 +#define ADC_IT_AnalogWatchdog2_LowThreshold 0x0100 +#define ADC_IT_AnalogWatchdog2_HighThreshold 0x0200 +#define ADC_IT_AnalogWatchdog3_LowThreshold 0x0400 +#define ADC_IT_AnalogWatchdog3_HighThreshold 0x0800 +#define ADC_IT_ALL 0x0FFF + +/* ADC Watchdogs Thresholds */ +#define ADC_AnalogWatchdog0 0x0030 +#define ADC_AnalogWatchdog1 0x00C0 +#define ADC_AnalogWatchdog2 0x0300 +#define ADC_AnalogWatchdog3 0x0C00 + +/* ADC Channels */ +#define ADC_CHANNEL0 0x0 +#define ADC_CHANNEL1 0x1 +#define ADC_CHANNEL2 0x2 +#define ADC_CHANNEL3 0x3 +#define ADC_CHANNEL4 0x4 +#define ADC_CHANNEL5 0x5 +#define ADC_CHANNEL6 0x6 +#define ADC_CHANNEL7 0x7 +#define ADC_CHANNEL8 0x8 +#define ADC_CHANNEL9 0x9 +#define ADC_CHANNEL10 0xA +#define ADC_CHANNEL11 0xB +#define ADC_CHANNEL12 0xC +#define ADC_CHANNEL13 0xD +#define ADC_CHANNEL14 0xE +#define ADC_CHANNEL15 0xF + +/* ADC DMA Channels */ +#define ADC_DMA_CHANNEL0 0x0001 +#define ADC_DMA_CHANNEL1 0x0002 +#define ADC_DMA_CHANNEL2 0x0004 +#define ADC_DMA_CHANNEL3 0x0008 +#define ADC_DMA_CHANNEL4 0x0010 +#define ADC_DMA_CHANNEL5 0x0020 +#define ADC_DMA_CHANNEL6 0x0040 +#define ADC_DMA_CHANNEL7 0x0080 +#define ADC_DMA_CHANNEL8 0x0100 +#define ADC_DMA_CHANNEL9 0x0200 +#define ADC_DMA_CHANNEL10 0x0400 +#define ADC_DMA_CHANNEL11 0x0800 +#define ADC_DMA_CHANNEL12 0x1000 +#define ADC_DMA_CHANNEL13 0x2000 +#define ADC_DMA_CHANNEL14 0x4000 +#define ADC_DMA_CHANNEL15 0x8000 + +/* Trigger conversion detection */ +#define ADC_ExtTrigger_LowLevel 0x4FFF +#define ADC_ExtTrigger_HighLevel 0x5000 +#define ADC_ExtTrigger_FallingEdge 0x6000 +#define ADC_ExtTrigger_RisingEdge 0x7000 +#define ADC_ExtTrigger_Disable 0x8FFF + +/* DMA enable config */ +#define ADC_DMA_ExtTrigger_HighLevel 0x6000 +#define ADC_DMA_ExtTrigger_LowLevel 0x4FFF +#define ADC_DMA_Enable 0x8000 +#define ADC_DMA_Disable 0x3FFF + +/* Injected Trigger conversion detection */ +#define ADC_Injec_ExtTrigger_RisingEdge 0x6000 +#define ADC_Injec_ExtTrigger_FallingEdge 0xDFFF +#define ADC_Injec_ExtTrigger_Disable 0x3FFF + +/* Start Conversion */ +#define ADC_Conversion_Start 0x0001 +#define ADC_Conversion_Stop 0xFFFE + +/* ADC Conversion Modes */ +#define ADC_ConversionMode_Scan 0x8000 +#define ADC_ConversionMode_OneShot 0x7FFF + +/* Auto Clock Off */ +#define ADC_AutoClockOff_Enable 0x4000 +#define ADC_AutoClockOff_Disable 0xBFFF + +/* Calibration */ +#define ADC_Calibration_ON 0x0002 +#define ADC_CalibAverage_Disable 0x0020 +#define ADC_CalibAverage_Enable 0xFFDF + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void ADC_DeInit(void); +void ADC_Init(ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(FunctionalState NewState); +void ADC_StartCalibration(u16 ADC_CalibAverage); +FlagStatus ADC_GetCalibrationStatus(void); +void ADC_ConversionCmd(u16 ADC_Conversion); +FlagStatus ADC_GetSTARTBitStatus(void); +void ADC_AutoClockOffConfig(FunctionalState NewState); +u16 ADC_GetConversionValue(u8 ADC_CHANNEL); +void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState); +void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, + u16 LowThreshold, u16 HighThreshold); +void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState); +u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog); +void ADC_StartInjectedConversion(void); +void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber); +void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState); +void ADC_DMACmd(u16 ADC_DMA); +u16 ADC_GetDMAFirstEnabledChannel(void); +FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG); +void ADC_ClearFlag(u16 ADC_FLAG); +ITStatus ADC_GetITStatus(u16 ADC_IT); +void ADC_ClearITPendingBit(u16 ADC_IT); + +#endif /*__75x_ADC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h new file mode 100644 index 0000000000..9b630ee0c2 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h @@ -0,0 +1,165 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_can.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* CAN bus software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CAN_H +#define __75x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* CAN Init structure define */ +typedef struct +{ + u8 CAN_ConfigParameters; + u32 CAN_Bitrate; +}CAN_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Standard bitrates available*/ +enum +{ + CAN_BITRATE_100K, + CAN_BITRATE_125K, + CAN_BITRATE_250K, + CAN_BITRATE_500K, + CAN_BITRATE_1M +}; + +/* Control register*/ +#define CAN_CR_TEST 0x0080 +#define CAN_CR_CCE 0x0040 +#define CAN_CR_DAR 0x0020 +#define CAN_CR_EIE 0x0008 +#define CAN_CR_SIE 0x0004 +#define CAN_CR_IE 0x0002 +#define CAN_CR_INIT 0x0001 + +/* Status register */ +#define CAN_SR_BOFF 0x0080 +#define CAN_SR_EWARN 0x0040 +#define CAN_SR_EPASS 0x0020 +#define CAN_SR_RXOK 0x0010 +#define CAN_SR_TXOK 0x0008 +#define CAN_SR_LEC 0x0007 + +/* Test register*/ +#define CAN_TESTR_RX 0x0080 +#define CAN_TESTR_TX1 0x0040 +#define CAN_TESTR_TX0 0x0020 +#define CAN_TESTR_LBACK 0x0010 +#define CAN_TESTR_SILENT 0x0008 +#define CAN_TESTR_BASIC 0x0004 + +/* IFn / Command Request register*/ +#define CAN_CRR_BUSY 0x8000 + +/* IFn / Command Mask register*/ +#define CAN_CMR_WRRD 0x0080 +#define CAN_CMR_MASK 0x0040 +#define CAN_CMR_ARB 0x0020 +#define CAN_CMR_CONTROL 0x0010 +#define CAN_CMR_CLRINTPND 0x0008 +#define CAN_CMR_TXRQSTNEWDAT 0x0004 +#define CAN_CMR_DATAA 0x0002 +#define CAN_CMR_DATAB 0x0001 + +/* IFn / Mask 2 register*/ +#define CAN_M2R_MXTD 0x8000 +#define CAN_M2R_MDIR 0x4000 + +/* IFn / Arbitration 2 register*/ +#define CAN_A2R_MSGVAL 0x8000 +#define CAN_A2R_XTD 0x4000 +#define CAN_A2R_DIR 0x2000 + +/* IFn / Message Control register*/ +#define CAN_MCR_NEWDAT 0x8000 +#define CAN_MCR_MSGLST 0x4000 +#define CAN_MCR_INTPND 0x2000 +#define CAN_MCR_UMASK 0x1000 +#define CAN_MCR_TXIE 0x0800 +#define CAN_MCR_RXIE 0x0400 +#define CAN_MCR_RMTEN 0x0200 +#define CAN_MCR_TXRQST 0x0100 +#define CAN_MCR_EOB 0x0080 + + +/* Wake-up modes*/ +enum +{ + CAN_WAKEUP_ON_EXT, + CAN_WAKEUP_ON_CAN +}; + + +/* CAN message structure*/ +typedef struct +{ + u32 IdType; + u32 Id; + u8 Dlc; + u8 Data[8]; +} canmsg; + +/* Message ID types*/ +enum +{ + CAN_STD_ID, + CAN_EXT_ID +}; + +/* Message ID limits*/ + +#define CAN_LAST_STD_ID ((1<<11) - 1) +#define CAN_LAST_EXT_ID ((1L<<29) - 1) + +/* Exported functions ------------------------------------------------------- */ + +void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); +void CAN_DeInit (void); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SetBitrate(u32 bitrate); +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); +void CAN_InvalidateAllMsgObj(void); +ErrorStatus CAN_ReleaseMessage(u32 msgobj); +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); +ErrorStatus CAN_WaitEndOfTx(void); +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); +void CAN_EnterTestMode(u8 TestMask); +void CAN_EnterInitMode(u8 InitMask); +void CAN_LeaveInitMode(void); +void CAN_LeaveTestMode(void); +void CAN_ReleaseTxMessage(u32 msgobj); +void CAN_ReleaseRxMessage(u32 msgobj); +u32 CAN_IsMessageWaiting(u32 msgobj); +u32 CAN_IsTransmitRequested(u32 msgobj); +u32 CAN_IsInterruptPending(u32 msgobj); +u32 CAN_IsObjectValid(u32 msgobj); + +#endif /* __75x_CAN_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h new file mode 100644 index 0000000000..e1042a2463 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h @@ -0,0 +1,48 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_cfg.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* CFG software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CFG_H +#define __75x_CFG_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define CFG_BootSpace_FLASH 0x00000000 +#define CFG_BootSpace_SRAM 0x00000002 +#define CFG_BootSpace_ExtSMI 0x00000003 + +#define CFG_FLASHBurst_Disable 0xFFFFFEFF +#define CFG_FLASHBurst_Enable 0x00000100 + +#define CFG_USBFilter_Disable 0xFFFFFDFF +#define CFG_USBFilter_Enable 0x00000200 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void CFG_BootSpaceConfig(u32 CFG_BootSpace); +void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst); +void CFG_USBFilterConfig(u32 CFG_USBFilter); +FlagStatus CFG_GetFlagStatus(void); + +#endif /* __75x_CFG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h new file mode 100644 index 0000000000..f71b1cad4d --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h @@ -0,0 +1,140 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_dma.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* DMA software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __75x_DMA_H +#define __75x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_SRCBaseAddr; + u32 DMA_DSTBaseAddr; + u16 DMA_BufferSize; + u16 DMA_SRC; + u16 DMA_DST; + u16 DMA_SRCSize; + u16 DMA_SRCBurst; + u16 DMA_DSTSize; + u16 DMA_Mode; + u16 DMA_M2M; + u16 DMA_DIR; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DMA interrupt Mask */ +#define DMA_IT_SI0 0x0001 +#define DMA_IT_SI1 0x0002 +#define DMA_IT_SI2 0x0004 +#define DMA_IT_SI3 0x0008 +#define DMA_IT_SE0 0x0010 +#define DMA_IT_SE1 0x0020 +#define DMA_IT_SE2 0x0040 +#define DMA_IT_SE3 0x0080 +#define DMA_IT_ALL 0x00FF + +/* DMA Flags */ +#define DMA_FLAG_SI0 0x0001 +#define DMA_FLAG_SI1 0x0002 +#define DMA_FLAG_SI2 0x0004 +#define DMA_FLAG_SI3 0x0008 +#define DMA_FLAG_SE0 0x0010 +#define DMA_FLAG_SE1 0x0020 +#define DMA_FLAG_SE2 0x0040 +#define DMA_FLAG_SE3 0x0080 +#define DMA_FLAG_ACT0 0x0100 +#define DMA_FLAG_ACT1 0x0200 +#define DMA_FLAG_ACT2 0x0400 +#define DMA_FLAG_ACT3 0x0800 + +/* DMA Increment Current Source Register */ +#define DMA_SRC_INCR 0x0002 +#define DMA_SRC_NOT_INCR 0xFFFD + +/* DMA Increment Current Destination Register */ +#define DMA_DST_INCR 0x0004 +#define DMA_DST_NOT_INCR 0xFFFB + +/* Source to DMA data width */ +#define DMA_SRCSize_Byte 0x0000 +#define DMA_SRCSize_HalfWord 0x0008 +#define DMA_SRCSize_Word 0x0010 + +/* DMA source burst size */ +#define DMA_SRCBurst_1Data 0x0000 +#define DMA_SRCBurst_4Data 0x0020 +#define DMA_SRCBurst_8Data 0x0040 +#define DMA_SRCBurst_16Data 0x0060 + +/* DMA destination data width */ +#define DMA_DSTSize_Byte 0x0000 +#define DMA_DSTSize_HalfWord 0x0080 +#define DMA_DSTSize_Word 0x0100 + +/* DMA mode */ +#define DMA_Mode_Circular 0x0200 +#define DMA_Mode_Normal 0xFDFF + +/* Memory to Memory Transfer */ +#define DMA_M2M_Enable 0x0800 +#define DMA_M2M_Disable 0xF7FF + +/* Direction Transfer */ +#define DMA_DIR_PeriphDST 0x2000 +#define DMA_DIR_PeriphSRC 0xDFFF + +/* DMA streamx Registers */ +#define DMA_SOURCEL 0x00000000 /* source base address low register */ +#define DMA_SOURCEH 0x00000004 /* source base address high register */ +#define DMA_DESTL 0x00000008 /* destination base address low register */ +#define DMA_DESTH 0x0000000C /* destination base address high register */ +#define DMA_MAX 0x00000010 /* Maximum count register */ +#define DMA_CTRL 0x00000014 /* Control register */ +#define DMA_SOCURRH 0x00000018 /* Current Source address high register */ +#define DMA_SOCURRL 0x0000001C /* Current Source address low register */ +#define DMA_DECURRH 0x00000020 /* Current Destination address high register */ +#define DMA_DECURRL 0x00000024 /* Current Destination address low register */ +#define DMA_TCNT 0x00000028 /* Terminal Counter Register */ +#define DMA_LUBUFF 0x0000002C /* Last Used Buffer location */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx); +void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); +void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState); +u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx); +u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx); +u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx); +void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); +void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr); +FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG); +void DMA_ClearFlag(u16 DMA_FLAG); +ITStatus DMA_GetITStatus(u16 DMA_IT); +void DMA_ClearITPendingBit(u16 DMA_IT); + +#endif /* __75x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h new file mode 100644 index 0000000000..c7e6a07cf3 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h @@ -0,0 +1,97 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_eic.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* EIC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_EIC_H +#define __75x_EIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 EIC_IRQChannel; + u8 EIC_IRQChannelPriority; + FunctionalState EIC_IRQChannelCmd; +}EIC_IRQInitTypeDef; + +typedef struct +{ + u8 EIC_FIQChannel; + FunctionalState EIC_FIQChannelCmd; +}EIC_FIQInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ channels */ +#define WAKUP_IRQChannel 0 +#define TIM2_OC2_IRQChannel 1 +#define TIM2_OC1_IRQChannel 2 +#define TIM2_IC12_IRQChannel 3 +#define TIM2_UP_IRQChannel 4 +#define TIM1_OC2_IRQChannel 5 +#define TIM1_OC1_IRQChannel 6 +#define TIM1_IC12_IRQChannel 7 +#define TIM1_UP_IRQChannel 8 +#define TIM0_OC2_IRQChannel 9 +#define TIM0_OC1_IRQChannel 10 +#define TIM0_IC12_IRQChannel 11 +#define TIM0_UP_IRQChannel 12 +#define PWM_OC123_IRQChannel 13 +#define PWM_EM_IRQChannel 14 +#define PWM_UP_IRQChannel 15 +#define I2C_IRQChannel 16 +#define SSP1_IRQChannel 17 +#define SSP0_IRQChannel 18 +#define UART2_IRQChannel 19 +#define UART1_IRQChannel 20 +#define UART0_IRQChannel 21 +#define CAN_IRQChannel 22 +#define USB_LP_IRQChannel 23 +#define USB_HP_IRQChannel 24 +#define ADC_IRQChannel 25 +#define DMA_IRQChannel 26 +#define EXTIT_IRQChannel 27 +#define MRCC_IRQChannel 28 +#define FLASHSMI_IRQChannel 29 +#define RTC_IRQChannel 30 +#define TB_IRQChannel 31 + +/* FIQ channels */ +#define EXTIT_Line0_FIQChannel 0x00000001 +#define WATCHDOG_FIQChannel 0x00000002 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void EIC_DeInit(void); +void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); +void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); +void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); +void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); +void EIC_IRQCmd(FunctionalState NewState); +void EIC_FIQCmd(FunctionalState NewState); +u8 EIC_GetCurrentIRQChannel(void); +u8 EIC_GetCurrentIRQChannelPriority(void); +void EIC_CurrentIRQPriorityConfig(u8 NewPriority); +u8 EIC_GetCurrentFIQChannel(void); +void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel); + +#endif /* __75x_EIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h new file mode 100644 index 0000000000..5dbbc3a093 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h @@ -0,0 +1,77 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_extit.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* EXTIT software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_EXTIT_H +#define __75x_EXTIT_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* EXTIT Trigger enumeration */ +typedef enum +{ + EXTIT_ITTrigger_Falling = 1, + EXTIT_ITTrigger_Rising +}EXTITTrigger_TypeDef; + +/* EXTIT Init Structure definition */ +typedef struct +{ + u32 EXTIT_ITLine; + EXTITTrigger_TypeDef EXTIT_ITTrigger; + FunctionalState EXTIT_ITLineCmd; +}EXTIT_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* EXTIT Lines */ +#define EXTIT_ITLineNone 0x0000 /* No interrupt selected */ +#define EXTIT_ITLine0 0x0001 /* External interrupt line 0 */ +#define EXTIT_ITLine1 0x0002 /* External interrupt line 1 */ +#define EXTIT_ITLine2 0x0004 /* External interrupt line 2 */ +#define EXTIT_ITLine3 0x0008 /* External interrupt line 3 */ +#define EXTIT_ITLine4 0x0010 /* External interrupt line 4 */ +#define EXTIT_ITLine5 0x0020 /* External interrupt line 5 */ +#define EXTIT_ITLine6 0x0040 /* External interrupt line 6 */ +#define EXTIT_ITLine7 0x0080 /* External interrupt line 7 */ +#define EXTIT_ITLine8 0x0100 /* External interrupt line 8 */ +#define EXTIT_ITLine9 0x0200 /* External interrupt line 9 */ +#define EXTIT_ITLine10 0x0400 /* External interrupt line 10 */ +#define EXTIT_ITLine11 0x0800 /* External interrupt line 11 */ +#define EXTIT_ITLine12 0x1000 /* External interrupt line 12 */ +#define EXTIT_ITLine13 0x2000 /* External interrupt line 13 */ +#define EXTIT_ITLine14 0x4000 /* External interrupt line 14 */ +#define EXTIT_ITLine15 0x8000 /* External interrupt line 15 */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void EXTIT_DeInit(void); +void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct); +void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct); +void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine); +FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine); +void EXTIT_ClearFlag(u16 EXTIT_ITLine); +ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine); +void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine); + +#endif /* __75x_EXTIT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h new file mode 100644 index 0000000000..53aad69ca0 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h @@ -0,0 +1,120 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_gpio.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_GPIO_H +#define __75x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 1, + GPIO_Mode_IN_FLOATING, + GPIO_Mode_IPD, + GPIO_Mode_IPU, + GPIO_Mode_Out_OD, + GPIO_Mode_Out_PP, + GPIO_Mode_AF_OD, + GPIO_Mode_AF_PP +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + u32 GPIO_Pin; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define */ +#define GPIO_Pin_None 0x00000000 /* No pin selected */ +#define GPIO_Pin_0 0x00000001 /* Pin 0 selected */ +#define GPIO_Pin_1 0x00000002 /* Pin 1 selected */ +#define GPIO_Pin_2 0x00000004 /* Pin 2 selected */ +#define GPIO_Pin_3 0x00000008 /* Pin 3 selected */ +#define GPIO_Pin_4 0x00000010 /* Pin 4 selected */ +#define GPIO_Pin_5 0x00000020 /* Pin 5 selected */ +#define GPIO_Pin_6 0x00000040 /* Pin 6 selected */ +#define GPIO_Pin_7 0x00000080 /* Pin 7 selected */ +#define GPIO_Pin_8 0x00000100 /* Pin 8 selected */ +#define GPIO_Pin_9 0x00000200 /* Pin 9 selected */ +#define GPIO_Pin_10 0x00000400 /* Pin 10 selected */ +#define GPIO_Pin_11 0x00000800 /* Pin 11 selected */ +#define GPIO_Pin_12 0x00001000 /* Pin 12 selected */ +#define GPIO_Pin_13 0x00002000 /* Pin 13 selected */ +#define GPIO_Pin_14 0x00004000 /* Pin 14 selected */ +#define GPIO_Pin_15 0x00008000 /* Pin 15 selected */ +#define GPIO_Pin_16 0x00010000 /* Pin 16 selected */ +#define GPIO_Pin_17 0x00020000 /* Pin 17 selected */ +#define GPIO_Pin_18 0x00040000 /* Pin 18 selected */ +#define GPIO_Pin_19 0x00080000 /* Pin 19 selected */ +#define GPIO_Pin_20 0x00100000 /* Pin 20 selected */ +#define GPIO_Pin_21 0x00200000 /* Pin 21 selected */ +#define GPIO_Pin_22 0x00400000 /* Pin 22 selected */ +#define GPIO_Pin_23 0x00800000 /* Pin 23 selected */ +#define GPIO_Pin_24 0x01000000 /* Pin 24 selected */ +#define GPIO_Pin_25 0x02000000 /* Pin 25 selected */ +#define GPIO_Pin_26 0x04000000 /* Pin 26 selected */ +#define GPIO_Pin_27 0x08000000 /* Pin 27 selected */ +#define GPIO_Pin_28 0x10000000 /* Pin 28 selected */ +#define GPIO_Pin_29 0x20000000 /* Pin 29 selected */ +#define GPIO_Pin_30 0x40000000 /* Pin 30 selected */ +#define GPIO_Pin_31 0x80000000 /* Pin 31 selected */ +#define GPIO_Pin_All 0xFFFFFFFF /* All pins selected */ + +/* GPIO Remap define */ +#define GPIO_Remap_SMI_CS3_EN 0x23 /* SMI CS3 Enable */ +#define GPIO_Remap_SMI_CS2_EN 0x22 /* SMI CS2 Enable */ +#define GPIO_Remap_SMI_CS1_EN 0x21 /* SMI CS1 Enable */ +#define GPIO_Remap_SMI_EN 0x20 /* SMI Enable */ +#define GPIO_Remap_DBGOFF 0x45 /* JTAG Disable */ +#define GPIO_Remap_UART1 0x44 /* UART1 Alternate Function mapping */ +#define GPIO_Remap_UART2 0x43 /* UART2 Alternate Function mapping */ +#define GPIO_Remap_SSP1 0x42 /* SSP1 Alternate Function mapping */ +#define GPIO_Remap_TIM2 0x41 /* TIM2 Alternate Function mapping */ +#define GPIO_Remap_TIM0 0x40 /* TIM0 Alternate Function mapping */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u32 GPIO_Read(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin); +void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx,u32 GPIO_Pin, BitAction BitVal); +void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState); +u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx); +void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState); + +#endif /* __75x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h new file mode 100644 index 0000000000..0e3a8c511c --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h @@ -0,0 +1,115 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_i2c.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* I2C software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __75x_I2C_H +#define __75x_I2C_H + +/* Includes ----------------------------------------------------------------- */ +#include "75x_map.h" + +/* Exported types ----------------------------------------------------------- */ +/* I2C Init structure definition */ +typedef struct +{ + u32 I2C_CLKSpeed; + u16 I2C_OwnAddress; + u8 I2C_GeneralCall; + u8 I2C_Ack; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* General Call */ +#define I2C_GeneralCall_Enable 0x10 +#define I2C_GeneralCall_Disable 0xEF + +/* Acknowledgement */ +#define I2C_Ack_Enable 0x04 +#define I2C_Ack_Disable 0xFB + +/* I2C Flags */ +#define I2C_FLAG_SB 0x0001 +#define I2C_FLAG_M_SL 0x0002 +#define I2C_FLAG_ADSL 0x0004 +#define I2C_FLAG_BTF 0x0008 +#define I2C_FLAG_BUSY 0x0010 +#define I2C_FLAG_TRA 0x0020 +#define I2C_FLAG_ADD10 0x0040 +#define I2C_FLAG_EVF 0x0080 +#define I2C_FLAG_GCAL 0x0100 +#define I2C_FLAG_BERR 0x0200 +#define I2C_FLAG_ARLO 0x0400 +#define I2C_FLAG_STOPF 0x0800 +#define I2C_FLAG_AF 0x1000 +#define I2C_FLAG_ENDAD 0x2000 +#define I2C_FLAG_ACK 0x4000 + +/* I2C Events */ +#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_ADSL) +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) +#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) +#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) +#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF +#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) + +#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR +#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO +#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) + +/* Master/Receiver Mode */ +#define I2C_MODE_TRANSMITTER 0x00 +#define I2C_MODE_RECEIVER 0x01 + +/* I2C Registers offset */ +#define I2C_CR 0x00 +#define I2C_SR1 0x04 +#define I2C_SR2 0x08 +#define I2C_CCR 0x0C +#define I2C_OAR1 0x10 +#define I2C_OAR2 0x14 +#define I2C_DR 0x18 +#define I2C_ECCR 0x1C + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void I2C_DeInit(void); +void I2C_Init(I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(FunctionalState NewState); +void I2C_GenerateSTART(FunctionalState NewState); +void I2C_GenerateSTOP(FunctionalState NewState); +void I2C_AcknowledgeConfig(FunctionalState NewState); +void I2C_ITConfig(FunctionalState NewState); +u16 I2C_GetLastEvent(void); +ErrorStatus I2C_CheckEvent(u16 I2C_EVENT); +void I2C_SendData(u8 Data); +u8 I2C_ReceiveData(void); +void I2C_Send7bitAddress(u8 Address, u8 Direction); +u8 I2C_ReadRegister(u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG); +void I2C_ClearFlag(u16 I2C_FLAG, ...); + +#endif /* __75x_I2C_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h new file mode 100644 index 0000000000..8048ffcc3b --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h @@ -0,0 +1,103 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_lib.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_LIB_H +#define __75x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +#ifdef _SMI + #include "75x_smi.h" +#endif /*_SMI */ + +#ifdef _CFG + #include "75x_cfg.h" +#endif /*_CFG*/ + +#ifdef _MRCC + #include "75x_mrcc.h" +#endif /*_MRCC */ + +#ifdef _ADC + #include "75x_adc.h" +#endif /*_ADC */ + +#ifdef _TB + #include "75x_tb.h" +#endif /*_TB */ + +#ifdef _TIM + #include "75x_tim.h" +#endif /*_TIM */ + +#ifdef _PWM + #include "75x_pwm.h" +#endif /*_PWM */ + +#ifdef _WDG + #include "75x_wdg.h" +#endif /*_WDG */ + +#ifdef _SSP + #include "75x_ssp.h" +#endif /*_SSP */ + +#ifdef _CAN + #include "75x_can.h" +#endif /*_CAN */ + +#ifdef _I2C + #include "75x_i2c.h" +#endif /*_I2C */ + +#ifdef _UART + #include "75x_uart.h" +#endif /*_UART */ + +#ifdef _GPIO + #include "75x_gpio.h" +#endif /*_GPIO */ + +#ifdef _DMA + #include "75x_dma.h" +#endif /*_DMA */ + +#ifdef _RTC + #include "75x_rtc.h" +#endif /*_RTC */ + +#ifdef _EXTIT + #include "75x_extit.h" +#endif /*_EXTIT */ + +#ifdef _EIC + #include "75x_eic.h" +#endif /*_EIC */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __75x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h new file mode 100644 index 0000000000..d000f1b452 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h @@ -0,0 +1,697 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_map.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the peripheral register's definitions +* and memory mapping. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_MAP_H +#define __75x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_conf.h" +#include "75x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu16 CLR0; + u16 EMPTY1; + vu16 CLR1; + u16 EMPTY2; + vu16 CLR2; + u16 EMPTY3; + vu16 CLR3; + u16 EMPTY4; + vu16 CLR4; + u16 EMPTY5; + vu16 TRA0; + u16 EMPTY6; + vu16 TRA1; + u16 EMPTY7; + vu16 TRA2; + u16 EMPTY8; + vu16 TRA3; + u16 EMPTY9; + vu16 TRB0; + u16 EMPTY10; + vu16 TRB1; + u16 EMPTY11; + vu16 TRB2; + u16 EMPTY12; + vu16 TRB3; + u16 EMPTY13; + vu16 DMAR; + u16 EMPTY14[7]; + vu16 DMAE; + u16 EMPTY15 ; + vu16 PBR; + u16 EMPTY16; + vu16 IMR; + u16 EMPTY17; + vu16 D0; + u16 EMPTY18; + vu16 D1; + u16 EMPTY19; + vu16 D2; + u16 EMPTY20; + vu16 D3; + u16 EMPTY21; + vu16 D4; + u16 EMPTY22; + vu16 D5; + u16 EMPTY23; + vu16 D6; + u16 EMPTY24; + vu16 D7; + u16 EMPTY25; + vu16 D8; + u16 EMPTY26; + vu16 D9; + u16 EMPTY27; + vu16 D10; + u16 EMPTY28; + vu16 D11; + u16 EMPTY29; + vu16 D12; + u16 EMPTY30; + vu16 D13; + u16 EMPTY31; + vu16 D14; + u16 EMPTY32; + vu16 D15; + u16 EMPTY33; +} ADC_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu16 CRR; + u16 EMPTY1; + vu16 CMR; + u16 EMPTY2; + vu16 M1R; + u16 EMPTY3; + vu16 M2R; + u16 EMPTY4; + vu16 A1R; + u16 EMPTY5; + vu16 A2R; + u16 EMPTY6; + vu16 MCR; + u16 EMPTY7; + vu16 DA1R; + u16 EMPTY8; + vu16 DA2R; + u16 EMPTY9; + vu16 DB1R; + u16 EMPTY10; + vu16 DB2R; + u16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SR; + u16 EMPTY2; + vu16 ERR; + u16 EMPTY3; + vu16 BTR; + u16 EMPTY4; + vu16 IDR; + u16 EMPTY5; + vu16 TESTR; + u16 EMPTY6; + vu16 BRPR; + u16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + u16 EMPTY8[16]; + vu16 TXR1R; + u16 EMPTY9; + vu16 TXR2R; + u16 EMPTY10[13]; + vu16 ND1R; + u16 EMPTY11; + vu16 ND2R; + u16 EMPTY12[13]; + vu16 IP1R; + u16 EMPTY13; + vu16 IP2R; + u16 EMPTY14[13]; + vu16 MV1R; + u16 EMPTY15; + vu16 MV2R; + u16 EMPTY16; +} CAN_TypeDef; + +/*--------------------------- Configuration Register -------------------------*/ +typedef struct +{ + vu32 GLCONF; +} CFG_TypeDef; + +/*-------------------------------- DMA Controller ----------------------------*/ +typedef struct +{ + vu16 SOURCEL; + u16 EMPTY1; + vu16 SOURCEH; + u16 EMPTY2; + vu16 DESTL; + u16 EMPTY3; + vu16 DESTH; + u16 EMPTY4; + vu16 MAX; + u16 EMPTY5; + vu16 CTRL; + u16 EMPTY6; + vuc16 SOCURRH; + u16 EMPTY7; + vuc16 SOCURRL; + u16 EMPTY8; + vuc16 DECURRH; + u16 EMPTY9; + vuc16 DECURRL; + u16 EMPTY10; + vuc16 TCNT; + u16 EMPTY11; + vu16 LUBUFF; + u16 EMPTY12; +} DMA_Stream_TypeDef; + +typedef struct +{ + vu16 MASK; + u16 EMPTY4; + vu16 CLR; + u16 EMPTY5; + vuc16 STATUS; + u16 EMPTY6; + vu16 LAST; + u16 EMPTY7; +} DMA_TypeDef; + +/*----------------------- Enhanced Interrupt Controller ----------------------*/ +typedef struct +{ + vu32 ICR; + vuc32 CICR; + vu32 CIPR; + u32 EMPTY1; + vu32 FIER; + vu32 FIPR; + vu32 IVR; + vu32 FIR; + vu32 IER; + u32 EMPTY2[7]; + vu32 IPR; + u32 EMPTY3[7]; + vu32 SIRn[32]; +} EIC_TypeDef; + +/*------------------------- External Interrupt Controller --------------------*/ +typedef struct +{ + vu32 MR; + vu32 TSR; + vu32 SWIR; + vu32 PR; +} EXTIT_TypeDef; + +/*-------------------------- General Purpose IO ports ------------------------*/ +typedef struct +{ + vu32 PC0; + vu32 PC1; + vu32 PC2; + vu32 PD; + vu32 PM; +} GPIO_TypeDef; + +typedef struct +{ + vu32 REMAP0R; + vu32 REMAP1R; +} GPIOREMAP_TypeDef; + +/*--------------------------------- I2C interface ----------------------------*/ +typedef struct +{ + vu8 CR; + u8 EMPTY1[3]; + vu8 SR1; + u8 EMPTY2[3]; + vu8 SR2; + u8 EMPTY3[3]; + vu8 CCR; + u8 EMPTY4[3]; + vu8 OAR1; + u8 EMPTY5[3]; + vu8 OAR2; + u8 EMPTY6[3]; + vu8 DR; + u8 EMPTY7[3]; + vu8 ECCR; + u8 EMPTY8[3]; +} I2C_TypeDef; + +/*---------------------------- Power, Reset and Clocks -----------------------*/ +typedef struct +{ + vu32 CLKCTL; + vu32 RFSR; + vu32 PWRCTRL; + u32 EMPTY1; + vu32 PCLKEN; + vu32 PSWRES; + u32 EMPTY2[2]; + vu32 BKP0; + vu32 BKP1; +} MRCC_TypeDef; + +/*-------------------------------- Real Time Clock ---------------------------*/ +typedef struct +{ + vu16 CRH; + u16 EMPTY; + vu16 CRL; + u16 EMPTY1; + vu16 PRLH; + u16 EMPTY2; + vu16 PRLL; + u16 EMPTY3; + vu16 DIVH; + u16 EMPTY4; + vu16 DIVL; + u16 EMPTY5; + vu16 CNTH; + u16 EMPTY6; + vu16 CNTL; + u16 EMPTY7; + vu16 ALRH; + u16 EMPTY8; + vu16 ALRL; + u16 EMPTY9; +} RTC_TypeDef; + +/*---------------------------- Serial Memory Interface -----------------------*/ +typedef struct +{ + vu32 CR1; + vu32 CR2; + vu32 SR; + vu32 TR; + vuc32 RR; +} SMI_TypeDef; + +/*--------------------------------- Timer Base -------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2; + vu16 IMCR; + u16 EMPTY3[7]; + vu16 RSR; + u16 EMPTY4; + vu16 RER; + u16 EMPTY5; + vu16 ISR; + u16 EMPTY6; + vu16 CNT; + u16 EMPTY7; + vu16 PSC; + u16 EMPTY8[3]; + vu16 ARR; + u16 EMPTY9[13]; + vu16 ICR1; + u16 EMPTY10; +} TB_TypeDef; + +/*------------------------------------ TIM -----------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2; + vu16 IMCR; + u16 EMPTY3; + vu16 OMR1; + u16 EMPTY4[5]; + vu16 RSR; + u16 EMPTY5; + vu16 RER; + u16 EMPTY6; + vu16 ISR; + u16 EMPTY7; + vu16 CNT; + u16 EMPTY8; + vu16 PSC; + u16 EMPTY9[3]; + vu16 ARR; + u16 EMPTY10; + vu16 OCR1; + u16 EMPTY11; + vu16 OCR2; + u16 EMPTY12[9]; + vu16 ICR1; + u16 EMPTY13; + vu16 ICR2; + u16 EMPTY14[9]; + vu16 DMAB; + u16 EMPTY15; +} TIM_TypeDef; + +/*------------------------------------ PWM -----------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2[3]; + vu16 OMR1; + u16 EMPTY3; + vu16 OMR2; + u16 EMPTY4[3]; + vu16 RSR; + u16 EMPTY5; + vu16 RER; + u16 EMPTY6; + vu16 ISR; + u16 EMPTY7; + vu16 CNT; + u16 EMPTY8; + vu16 PSC; + u16 EMPTY9; + vu16 RCR; + u16 EMPTY10; + vu16 ARR; + u16 EMPTY11; + vu16 OCR1; + u16 EMPTY12; + vu16 OCR2; + u16 EMPTY13; + vu16 OCR3; + u16 EMPTY14[15]; + vu16 DTR; + u16 EMPTY15; + vu16 DMAB; + u16 EMPTY16; +} PWM_TypeDef; + +/*----------------------- Synchronous Serial Peripheral ----------------------*/ +typedef struct +{ + vu32 CR0; + vu32 CR1; + vu32 DR; + vu32 SR; + vu32 PR; + vu32 IMSCR; + vu32 RISR; + vu32 MISR; + vu32 ICR; + vu32 DMACR; +} SSP_TypeDef; + +/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/ +typedef struct +{ + vu16 DR; + u16 EMPTY; + vu16 RSR; + u16 EMPTY1[9]; + vu16 FR; + u16 EMPTY2; + vu16 BKR; + u16 EMPTY3[3]; + vu16 IBRD; + u16 EMPTY4; + vu16 FBRD; + u16 EMPTY5; + vu16 LCR; + u16 EMPTY6; + vu16 CR; + u16 EMPTY7; + vu16 IFLS; + u16 EMPTY8; + vu16 IMSC; + u16 EMPTY9; + vu16 RIS; + u16 EMPTY10; + vu16 MIS; + u16 EMPTY11; + vu16 ICR; + u16 EMPTY12; + vu16 DMACR; + u16 EMPTY13; +} UART_TypeDef; + +/*---------------------------------- WATCHDOG --------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 PR; + u16 EMPTY2; + vu16 VR; + u16 EMPTY3; + vu16 CNT; + u16 EMPTY4; + vu16 SR; + u16 EMPTY5; + vu16 MR; + u16 EMPTY6; + vu16 KR; + u16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Peripherals' Base addresses +*******************************************************************************/ + +#define SRAM_BASE 0x40000000 + +#define CONFIG_BASE 0x60000000 + +#define SMIR_BASE 0x90000000 + +#define PERIPH_BASE 0xFFFF0000 + +#define CFG_BASE (CONFIG_BASE + 0x0010) +#define MRCC_BASE (CONFIG_BASE + 0x0020) +#define ADC_BASE (PERIPH_BASE + 0x8400) +#define TB_BASE (PERIPH_BASE + 0x8800) +#define TIM0_BASE (PERIPH_BASE + 0x8C00) +#define TIM1_BASE (PERIPH_BASE + 0x9000) +#define TIM2_BASE (PERIPH_BASE + 0x9400) +#define PWM_BASE (PERIPH_BASE + 0x9800) +#define WDG_BASE (PERIPH_BASE + 0xB000) +#define SSP0_BASE (PERIPH_BASE + 0xB800) +#define SSP1_BASE (PERIPH_BASE + 0xBC00) +#define CAN_BASE (PERIPH_BASE + 0xC400) +#define I2C_BASE (PERIPH_BASE + 0xCC00) +#define UART0_BASE (PERIPH_BASE + 0xD400) +#define UART1_BASE (PERIPH_BASE + 0xD800) +#define UART2_BASE (PERIPH_BASE + 0xDC00) +#define GPIO0_BASE (PERIPH_BASE + 0xE400) +#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420) +#define GPIO1_BASE (PERIPH_BASE + 0xE440) +#define GPIO2_BASE (PERIPH_BASE + 0xE480) +#define DMA_BASE (PERIPH_BASE + 0xECF0) +#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00) +#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40) +#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80) +#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0) +#define RTC_BASE (PERIPH_BASE + 0xF000) +#define EXTIT_BASE (PERIPH_BASE + 0xF400) +#define EIC_BASE (PERIPH_BASE + 0xF800) + +/******************************************************************************* + IPs' declaration +*******************************************************************************/ + +/*------------------- Non Debug Mode -----------------------------------------*/ + +#ifndef DEBUG + #define SMI ((SMI_TypeDef *) SMIR_BASE) + #define CFG ((CFG_TypeDef *) CFG_BASE) + #define MRCC ((MRCC_TypeDef *) MRCC_BASE) + #define ADC ((ADC_TypeDef *) ADC_BASE) + #define TB ((TB_TypeDef *) TB_BASE) + #define TIM0 ((TIM_TypeDef *) TIM0_BASE) + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) + #define PWM ((PWM_TypeDef *) PWM_BASE) + #define WDG ((WDG_TypeDef *) WDG_BASE) + #define SSP0 ((SSP_TypeDef *) SSP0_BASE) + #define SSP1 ((SSP_TypeDef *) SSP1_BASE) + #define CAN ((CAN_TypeDef *) CAN_BASE) + #define I2C ((I2C_TypeDef *) I2C_BASE) + #define UART0 ((UART_TypeDef *) UART0_BASE) + #define UART1 ((UART_TypeDef *) UART1_BASE) + #define UART2 ((UART_TypeDef *) UART2_BASE) + #define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE) + #define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE) + #define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE) + #define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE) + #define DMA ((DMA_TypeDef *) DMA_BASE) + #define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE) + #define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE) + #define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE) + #define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE) + #define RTC ((RTC_TypeDef *) RTC_BASE) + #define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE) + #define EIC ((EIC_TypeDef *) EIC_BASE) +#else /* DEBUG */ + #ifdef _SMI + EXT SMI_TypeDef *SMI; + #endif /*_SMI */ + + #ifdef _CFG + EXT CFG_TypeDef *CFG; + #endif /*_CFG */ + + #ifdef _MRCC + EXT MRCC_TypeDef *MRCC; + #endif /*_MRCC */ + + #ifdef _ADC + EXT ADC_TypeDef *ADC; + #endif /*_ADC */ + + #ifdef _TB + EXT TB_TypeDef *TB; + #endif /*_TB */ + + #ifdef _TIM0 + EXT TIM_TypeDef *TIM0; + #endif /*_TIM0 */ + + #ifdef _TIM1 + EXT TIM_TypeDef *TIM1; + #endif /*_TIM1 */ + + #ifdef _TIM2 + EXT TIM_TypeDef *TIM2; + #endif /*_TIM2 */ + + #ifdef _PWM + EXT PWM_TypeDef *PWM; + #endif /*_PWM */ + + #ifdef _WDG + EXT WDG_TypeDef *WDG; + #endif /*_WDG */ + + #ifdef _SSP0 + EXT SSP_TypeDef *SSP0; + #endif /*_SSP0 */ + + #ifdef _SSP1 + EXT SSP_TypeDef *SSP1; + #endif /*_SSP1 */ + + #ifdef _CAN + EXT CAN_TypeDef *CAN; + #endif /*_CAN */ + + #ifdef _I2C + EXT I2C_TypeDef *I2C; + #endif /*_I2C */ + + #ifdef _UART0 + EXT UART_TypeDef *UART0; + #endif /*_UART0 */ + + #ifdef _UART1 + EXT UART_TypeDef *UART1; + #endif /*_UART1 */ + + #ifdef _UART2 + EXT UART_TypeDef *UART2; + #endif /*_UART2 */ + + #ifdef _GPIO0 + EXT GPIO_TypeDef *GPIO0; + #endif /*_GPIO0 */ + + #ifdef _GPIOREMAP + EXT GPIOREMAP_TypeDef *GPIOREMAP; + #endif /*_GPIOREMAP */ + + #ifdef _GPIO1 + EXT GPIO_TypeDef *GPIO1; + #endif /*_GPIO1 */ + + #ifdef _GPIO2 + EXT GPIO_TypeDef *GPIO2; + #endif /*_GPIO2 */ + + #ifdef _DMA + EXT DMA_TypeDef *DMA; + #endif /*_DMA */ + + #ifdef _DMA_Stream0 + EXT DMA_Stream_TypeDef *DMA_Stream0; + #endif /*_DMA_Stream0 */ + + #ifdef _DMA_Stream1 + EXT DMA_Stream_TypeDef *DMA_Stream1; + #endif /*_DMA_Stream1 */ + + #ifdef _DMA_Stream2 + EXT DMA_Stream_TypeDef *DMA_Stream2; + #endif /*_DMA_Stream2 */ + + #ifdef _DMA_Stream3 + EXT DMA_Stream_TypeDef *DMA_Stream3; + #endif /*_DMA_Stream3 */ + + #ifdef _RTC + EXT RTC_TypeDef *RTC; + #endif /*_RTC */ + + #ifdef _EXTIT + EXT EXTIT_TypeDef *EXTIT; + #endif /*_EXTIT */ + + #ifdef _EIC + EXT EIC_TypeDef *EIC; + #endif /*_EIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_MAP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h new file mode 100644 index 0000000000..91c178429b --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h @@ -0,0 +1,241 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_mrcc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* MRCC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_MRCC_H +#define __75x_MRCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* MRCC Buck-up registers */ +typedef enum +{ + MRCC_BKP0, + MRCC_BKP1 +}MRCC_BKPReg; + +typedef enum +{ + FREEOSC, + OSC4MPLL, + OSC4M, + CKRTC, + Disabled, + OSC4M_Div128, + LPOSC, + OSC32K, + Internal, + External, + ON, + OFF +}CLKSourceTypeDef; + + +typedef struct +{ + CLKSourceTypeDef CKSYS_Source; /* FREEOSC, OSC4MPLL, OSC4M, CKRTC */ + CLKSourceTypeDef CKRTC_Source; /* Disabled, OSC4M_Div128, OSC32K, LPOSC */ + CLKSourceTypeDef CKUSB_Source; /* Disabled, Internal, External */ + CLKSourceTypeDef PLL_Status; /* ON, OFF */ + CLKSourceTypeDef OSC4M_Status; /* ON, OFF */ + CLKSourceTypeDef LPOSC_Status; /* ON, OFF */ + CLKSourceTypeDef OSC32K_Status; /* ON, OFF */ + u32 CKSYS_Frequency; + u32 HCLK_Frequency; + u32 CKTIM_Frequency; + u32 PCLK_Frequency; +}MRCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Oscillator divider by 2 */ +#define MRCC_XTDIV2_Disable 0xFFFF7FFF +#define MRCC_XTDIV2_Enable 0x00008000 + +/* System clock source */ +#define MRCC_CKSYS_FREEOSC 0x01 +#define MRCC_CKSYS_OSC4M 0x02 +#define MRCC_CKSYS_OSC4MPLL 0x03 +#define MRCC_CKSYS_RTC 0x04 + +/* PLL multiplication factors */ +#define MRCC_PLL_Disabled 0xFEFFFFFF +#define MRCC_PLL_NoChange 0x00000001 +#define MRCC_PLL_Mul_12 0x18000000 +#define MRCC_PLL_Mul_14 0x10000000 +#define MRCC_PLL_Mul_15 0x08000000 +#define MRCC_PLL_Mul_16 0x00000000 + +/* AHB clock source */ +#define MRCC_CKSYS_Div1 0x00000000 +#define MRCC_CKSYS_Div2 0x00000008 +#define MRCC_CKSYS_Div4 0x00000010 +#define MRCC_CKSYS_Div8 0x00000018 + +/* TIM clock source */ +#define MRCC_HCLK_Div1 0x00000000 +#define MRCC_HCLK_Div2 0x00000001 +#define MRCC_HCLK_Div4 0x00000002 +#define MRCC_HCLK_Div8 0x00000003 + +/* APB clock source */ +#define MRCC_CKTIM_Div1 0xFFFFFFFB +#define MRCC_CKTIM_Div2 0x00000004 + +/* RTC clock sources */ +#define MRCC_CKRTC_OSC4M_Div128 0x01000000 +#define MRCC_CKRTC_OSC32K 0x02000000 +#define MRCC_CKRTC_LPOSC 0x03000000 + +/* USB clock sources */ +#define MRCC_CKUSB_Internal 0xFFBFFFFF +#define MRCC_CKUSB_External 0x00400000 + +/* MRCC Interrupts */ +#define MRCC_IT_LOCK 0x40000000 +#define MRCC_IT_NCKD 0x00080000 + +/* Peripheral Clock */ +#define MRCC_Peripheral_ALL 0x1975623F +#define MRCC_Peripheral_EXTIT 0x10000000 +#define MRCC_Peripheral_RTC 0x08000000 +#define MRCC_Peripheral_GPIO 0x01000000 +#define MRCC_Peripheral_UART2 0x00400000 +#define MRCC_Peripheral_UART1 0x00200000 +#define MRCC_Peripheral_UART0 0x00100000 +#define MRCC_Peripheral_I2C 0x00040000 +#define MRCC_Peripheral_CAN 0x00010000 +#define MRCC_Peripheral_SSP1 0x00004000 +#define MRCC_Peripheral_SSP0 0x00002000 +#define MRCC_Peripheral_USB 0x00000200 +#define MRCC_Peripheral_PWM 0x00000020 +#define MRCC_Peripheral_TIM2 0x00000010 +#define MRCC_Peripheral_TIM1 0x00000008 +#define MRCC_Peripheral_TIM0 0x00000004 +#define MRCC_Peripheral_TB 0x00000002 +#define MRCC_Peripheral_ADC 0x00000001 + +/* Clock sources to measure theire frequency */ +#define MRCC_ClockSource_CKSYS 0x01 +#define MRCC_ClockSource_HCLK 0x02 +#define MRCC_ClockSource_PCLK 0x03 +#define MRCC_ClockSource_CKTIM 0x04 + +/* Low Power Debug Mode */ +#define MRCC_LPDM_Disable 0xFFFFFFF7 +#define MRCC_LPDM_Enable 0x00000008 + +/* WFI Mode parameters */ +#define MRCC_WFIParam_FLASHPowerDown 0x00000000 +#define MRCC_WFIParam_FLASHOn 0x00000010 +#define MRCC_WFIParam_FLASHOff 0x00004000 + +/* STOP Mode parameters */ +#define MRCC_STOPParam_Default 0x00000000 +#define MRCC_STOPParam_OSC4MOff 0x00008000 +#define MRCC_STOPParam_FLASHOff 0x00004000 +#define MRCC_STOPParam_MVREGOff 0x00002000 + +/* I/O Pins voltage range */ +#define MRCC_IOVoltageRange_5V 0xFFFEFFFF +#define MRCC_IOVoltageRange_3V3 0x00010000 + +/* Clock sources to output on MCO pin */ +#define MRCC_MCO_HCLK 0x00000000 +#define MRCC_MCO_PCLK 0x00000040 +#define MRCC_MCO_OSC4M 0x00000080 +#define MRCC_MCO_CKPLL2 0x000000C0 +#define MRCC_MCOPrescaler_1 0xFFFFFFDF +#define MRCC_MCOPrescaler_2 0x00000020 + +/* 4MHz main oscillator configuration */ +#define MRCC_OSC4M_Default 0xFFFCFFFF +#define MRCC_OSC4M_Disable 0x00020000 +#define MRCC_OSC4M_Bypass 0x00010000 + +/* OSC32K oscillator configuration */ +#define MRCC_OSC32K_Disable 0xDFFFFFFF +#define MRCC_OSC32K_Enable 0x20000000 +#define MRCC_OSC32KBypass_Disable 0xBFFFFFFF +#define MRCC_OSC32KBypass_Enable 0x40000000 + +/* LPOSC oscillator configuration */ +#define MRCC_LPOSC_Disable 0xEFFFFFFF +#define MRCC_LPOSC_Enable 0x10000000 + +/* RTC measurement configuration */ +#define MRCC_RTCM_Disable 0xFBFFFFFF +#define MRCC_RTCM_Enable 0x04000000 + +/* MRCC Flags */ +#define MRCC_FLAG_LOCK 0x3F +#define MRCC_FLAG_LOCKIF 0x3D +#define MRCC_FLAG_CKSEL 0x37 +#define MRCC_FLAG_CKOSCSEL 0x35 +#define MRCC_FLAG_NCKD 0x32 +#define MRCC_FLAG_SWR 0x5D +#define MRCC_FLAG_WDGR 0x5C +#define MRCC_FLAG_EXTR 0x5B +#define MRCC_FLAG_WKP 0x5A +#define MRCC_FLAG_STDB 0x59 +#define MRCC_FLAG_BCOUNT 0x58 +#define MRCC_FLAG_OSC32KRDY 0x7F +#define MRCC_FLAG_CKRTCOK 0x7B +#define MRCC_FLAG_LPDONE 0x67 +#define MRCC_FLAG_LP 0x60 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void MRCC_DeInit(void); +void MRCC_XTDIV2Config(u32 MRCC_XTDIV2); +ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL); +void MRCC_HCLKConfig(u32 MRCC_HCLK); +void MRCC_CKTIMConfig(u32 MRCC_CKTIM); +void MRCC_PCLKConfig(u32 MRCC_PCLK); +ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC); +ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB); +void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState); +void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState); +void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState); +void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus); +void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM); +void MRCC_EnterWFIMode(u32 MRCC_WFIParam); +void MRCC_EnterSTOPMode(u32 MRCC_STOPParam); +void MRCC_EnterSTANDBYMode(void); +void MRCC_GenerateSWReset(void); +void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data); +u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP); +void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange); +void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler); +ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M); +ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass); +ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC); +void MRCC_RTCMConfig(u32 MRCC_RTCM); +void MRCC_SetBuilderCounter(u8 BuilderCounter); +u16 MRCC_GetCKSYSCounter(void); +FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG); +void MRCC_ClearFlag(u8 MRCC_FLAG); +ITStatus MRCC_GetITStatus(u32 MRCC_IT); +void MRCC_ClearITPendingBit(u32 MRCC_IT); +ErrorStatus MRCC_WaitForOSC4MStartUp(void); + +#endif /* __75x_MRCC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h new file mode 100644 index 0000000000..28edba9e8b --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h @@ -0,0 +1,215 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_pwm.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* PWM software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_PWM_H +#define __75x_PWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u16 PWM_Mode; /* PWM Mode */ + u16 PWM_Prescaler; /* Prescaler value */ + u16 PWM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ + u16 PWM_Period; /* Period value */ + u16 PWM_Complementary; /* Complementary PWM selection */ + u16 PWM_OCState; /* Output compare off-state in Run mode */ + u16 PWM_OCNState; /* Complementary Output compare off-state in Run mode */ + u16 PWM_Channel; /* PWM Channel: 1, 2 or 3 */ + u16 PWM_Pulse1; /* PWM or OCM Channel 1 pulse length */ + u16 PWM_Pulse2; /* PWM or OCM Channel 2 pulse length */ + u16 PWM_Pulse3; /* PWM or OCM Channel 3 pulse length */ + u16 PWM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ + u16 PWM_Polarity2; /* PWM or OCM Channel 2 polarity */ + u16 PWM_Polarity3; /* PWM or OCM Channel 3 polarity */ + u16 PWM_Polarity1N; /* PWM or OCM Channel 1N polarity */ + u16 PWM_Polarity2N; /* PWM or OCM Channel 2N polarity */ + u16 PWM_Polarity3N; /* PWM or OCM Channel 3N polarity */ + u16 PWM_DTRAccess; /* Enable or disable the configuration of DTR register parameters: + DeadTime, Emergency, LOCKLevel, OSSIState, OCState and OCNState */ + u16 PWM_DeadTime; /* Dead Time value */ + u16 PWM_Emergency; /* Emergency selection: Enable / Disable */ + u16 PWM_LOCKLevel; /* LOCK level */ + u16 PWM_OSSIState; /* Off-State Selection for Idle state */ + u8 PWM_RepetitionCounter; /* Repetition counter value */ +} PWM_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* PWM modes */ +#define PWM_Mode_OCTiming 0x0001 +#define PWM_Mode_OCActive 0x0002 +#define PWM_Mode_OCInactive 0x0003 +#define PWM_Mode_OCToggle 0x0004 +#define PWM_Mode_PWM 0x0005 + +/* PWM Counter Mode */ +#define PWM_CounterMode_Up 0x0000 +#define PWM_CounterMode_Down 0x0010 +#define PWM_CounterMode_CenterAligned1 0x0020 +#define PWM_CounterMode_CenterAligned2 0x0040 +#define PWM_CounterMode_CenterAligned3 0x0060 + +/* PWM Channel */ +#define PWM_Channel_1 0x0001 +#define PWM_Channel_2 0x0002 +#define PWM_Channel_3 0x0004 +#define PWM_Channel_ALL 0x0007 + +/* PWM Polarity channel 1 */ +#define PWM_Polarity1_High 0x0001 +#define PWM_Polarity1_Low 0x0002 + +/* PWM Polarity channel 2 */ +#define PWM_Polarity2_High 0x0001 +#define PWM_Polarity2_Low 0x0002 + +/* PWM Polarity channel 3 */ +#define PWM_Polarity3_High 0x0001 +#define PWM_Polarity3_Low 0x0002 + +/* PWM Polarity channel 1N */ +#define PWM_Polarity1N_High 0x0001 +#define PWM_Polarity1N_Low 0x0002 + +/* PWM Polarity channel 2N */ +#define PWM_Polarity2N_High 0x0001 +#define PWM_Polarity2N_Low 0x0002 + +/* PWM Polarity channel 3N */ +#define PWM_Polarity3N_High 0x0001 +#define PWM_Polarity3N_Low 0x0002 + +/* PWM interrupt sources */ +#define PWM_IT_OC1 0x0100 +#define PWM_IT_OC2 0x0200 +#define PWM_IT_OC3 0x0400 +#define PWM_IT_Update 0x0001 +#define PWM_IT_GlobalUpdate 0x1001 +#define PWM_IT_Emergency 0x8000 + +/* PWM DMA sources */ +#define PWM_DMASource_OC1 0x0100 +#define PWM_DMASource_OC2 0x0200 +#define PWM_DMASource_OC3 0x0400 +#define PWM_DMASource_Update 0x0001 + +/* PWM DMA Base address */ +#define PWM_DMABase_CR 0x0000 +#define PWM_DMABase_SCR 0x0800 +#define PWM_DMABase_OMR1 0x1800 +#define PWM_DMABase_OMR2 0x2000 +#define PWM_DMABase_RSR 0x3000 +#define PWM_DMABase_RER 0x3800 +#define PWM_DMABase_ISR 0x4000 +#define PWM_DMABase_CNT 0x4800 +#define PWM_DMABase_PSC 0x5000 +#define PWM_DMABase_RCR 0x5800 +#define PWM_DMABase_ARR 0x6000 +#define PWM_DMABase_OCR1 0x6800 +#define PWM_DMABase_OCR2 0x7000 +#define PWM_DMABase_OCR3 0x7800 +#define PWM_DMABase_DTR 0xB800 + +/* PWM OCM state */ +#define PWM_OCRMState_Enable 0x0005 +#define PWM_OCRMState_Disable 0x0006 + +/* PWM Flags */ +#define PWM_FLAG_OC1 0x0100 +#define PWM_FLAG_OC2 0x0200 +#define PWM_FLAG_OC3 0x0400 +#define PWM_FLAG_Update 0x0001 +#define PWM_FLAG_Emergency 0x8000 + +/* PWM_ForcedAction */ +#define PWM_ForcedAction_Active 0x000A +#define PWM_ForcedAction_InActive 0x0008 + +/* PWM TRGO Mode */ +#define PWM_TRGOMode_Enable 0x0100 +#define PWM_TRGOMode_Update 0x0200 +#define PWM_TRGOMode_Reset 0x0000 +#define PWM_TRGOMode_OC 0x0300 + +/* PWM Complementary outputs Enable/Disable */ +#define PWM_Complementary_Disable 0x0001 +#define PWM_Complementary_Enable 0x0002 + +/* PWM DTR Access Enable/Disable */ +#define PWM_DTRAccess_Enable 0x0001 +#define PWM_DTRAccess_Disable 0x0002 + +/* PWM Emergency input Enable/Disable */ +#define PWM_Emergency_Disable 0x0000 +#define PWM_Emergency_Enable 0x1000 + +/* OC states */ +#define PWM_OCNState_Disable 0x0001 +#define PWM_OCNState_Enable 0x0002 +#define PWM_OCNState_OffState 0x0003 + +/* OCN states */ +#define PWM_OCState_Disable 0x0004 +#define PWM_OCState_Enable 0x0005 +#define PWM_OCState_OffState 0x0006 + +/* PWM LOCK level */ +#define PWM_LOCKLevel_1 0x0400 +#define PWM_LOCKLevel_2 0x0800 +#define PWM_LOCKLevel_3 0x0C00 +#define PWM_LOCKLevel_OFF 0x0000 + +/* Off State selection for Idle state */ +#define PWM_OSSIState_Disable 0x0000 +#define PWM_OSSIState_Enable 0x2000 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void PWM_DeInit(void); +void PWM_Init(PWM_InitTypeDef* PWM_InitStruct); +void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct); +void PWM_Cmd(FunctionalState Newstate); +void PWM_CtrlPWMOutputs(FunctionalState Newstate); +void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate); +void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase); +void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate); +void PWM_SetPrescaler(u16 Prescaler); +void PWM_SetPeriod(u16 Period); +void PWM_SetPulse(u16 PWM_Channel, u16 Pulse); +void PWM_SetPulse1(u16 Pulse); +void PWM_SetPulse2(u16 Pulse); +void PWM_SetPulse3(u16 Pulse); +void PWM_DebugCmd(FunctionalState Newstate); +void PWM_CounterModeConfig(u16 PWM_CounterMode); +void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction); +void PWM_SetDeadTime(u16 DeadTime); +void PWM_ResetCounter(void); +void PWM_TRGOSelection(u16 PWM_TRGOMode); +FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG); +void PWM_ClearFlag(u16 PWM_FLAG); +ITStatus PWM_GetITStatus(u16 PWM_IT); +void PWM_ClearITPendingBit(u16 PWM_IT); + +#endif /* __75x_PWM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h new file mode 100644 index 0000000000..a54dee9588 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h @@ -0,0 +1,63 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_rtc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* RTC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_RTC_H +#define __75x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* RTC interrupts define */ +#define RTC_IT_Overflow 0x0004 /* Overflow interrupt */ +#define RTC_IT_Alarm 0x0002 /* Alarm interrupt */ +#define RTC_IT_Second 0x0001 /* Second interrupt */ + +/* RTC interrupts flags */ +#define RTC_FLAG_RTOFF 0x0020 /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF 0x0008 /* Registers Synchronized flag */ +#define RTC_FLAG_Overflow 0x0004 /* Overflow interrupt flag */ +#define RTC_FLAG_Alarm 0x0002 /* Alarm interrupt flag */ +#define RTC_FLAG_Second 0x0001 /* Second interrupt flag */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void RTC_DeInit(void); +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +u32 RTC_GetCounter(void); +void RTC_SetCounter(u32 CounterValue); +void RTC_SetPrescaler(u32 PrescalerValue); +u32 RTC_GetPrescaler(void); +void RTC_SetAlarm(u32 AlarmValue); +u32 RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); +void RTC_ClearFlag(u16 RTC_FLAG); +ITStatus RTC_GetITStatus(u16 RTC_IT); +void RTC_ClearITPendingBit(u16 RTC_IT); + +#endif /* __75x_RTC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h new file mode 100644 index 0000000000..1e4a71bd24 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h @@ -0,0 +1,111 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_smi.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* SMI software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_SMI_H +#define __75x_SMI_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 SMI_ClockHold; + u8 SMI_Prescaler; + u8 SMI_DeselectTime; +} SMI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SMI mode */ +#define SMI_Mode_HW 0xEFFFFFFF +#define SMI_Mode_SW 0x10000000 + +/* Reception Length */ +#define SMI_RxLength_0Bytes 0x00000000 +#define SMI_RxLength_1Byte 0x00000010 +#define SMI_RxLength_2Bytes 0x00000020 +#define SMI_RxLength_3Bytes 0x00000030 +#define SMI_RxLength_4Bytes 0x00000040 + +/* Transmission Length */ +#define SMI_TxLength_0Bytes 0x00000000 +#define SMI_TxLength_1Byte 0x00000001 +#define SMI_TxLength_2Bytes 0x00000002 +#define SMI_TxLength_3Bytes 0x00000003 +#define SMI_TxLength_4Bytes 0x00000004 + +/* SMI memory Banks */ +#define SMI_Bank_0 0x00000001 +#define SMI_Bank_1 0x00000002 +#define SMI_Bank_2 0x00000004 +#define SMI_Bank_3 0x00000008 + +/* SMI Interrupts */ +#define SMI_IT_WC 0x00000200 +#define SMI_IT_TF 0x00000100 + +/* Fast Read Mode */ +#define SMI_FastRead_Disable 0xFFFF7FFF +#define SMI_FastRead_Enable 0x00008000 + +/* Write Burst Mode */ +#define SMI_WriteBurst_Disable 0xDFFFFFFF +#define SMI_WriteBurst_Enable 0x20000000 + +/* SMI Flags */ +#define SMI_FLAG_Bank3_WM 0x00008000 +#define SMI_FLAG_Bank2_WM 0x00004000 +#define SMI_FLAG_Bank1_WM 0x00002000 +#define SMI_FLAG_Bank0_WM 0x00001000 +#define SMI_FLAG_ERF2 0x00000800 +#define SMI_FLAG_ERF1 0x00000400 +#define SMI_FLAG_WC 0x00000200 +#define SMI_FLAG_TF 0x00000100 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SMI_DeInit(void); +void SMI_Init(SMI_InitTypeDef* SMI_InitStruct); +void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct); +void SMI_ModeConfig(u32 SMI_Mode); +void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength); +void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState); +void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState); +void SMI_SelectBank(u32 SMI_Bank); +void SMI_SendWENCmd(void); +void SMI_SendRSRCmd(void); +void SMI_SendCmd(u32 Command); +void SMI_FastReadConfig(u32 SMI_FastRead); +void SMI_WriteBurstConfig(u32 SMI_WriteBurst); +void SMI_WriteByte(u32 WriteAddr, u8 Data); +void SMI_WriteHalfWord(u32 WriteAddr, u16 Data); +void SMI_WriteWord(u32 WriteAddr, u32 Data); +u8 SMI_ReadByte(u32 ReadAddr); +u16 SMI_ReadHalfWord(u32 ReadAddr); +u32 SMI_ReadWord(u32 ReadAddr); +u8 SMI_ReadMemoryStatusRegister(void); +FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG); +void SMI_ClearFlag(u32 SMI_FLAG); +ITStatus SMI_GetITStatus(u32 SMI_IT); +void SMI_ClearITPendingBit(u32 SMI_IT); + +#endif /* __75x_SMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h new file mode 100644 index 0000000000..96dec886ac --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h @@ -0,0 +1,135 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_SSP.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* SSP software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_SSP_H +#define __75x_SSP_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SSP Init structure definition */ +typedef struct +{ + u16 SSP_FrameFormat; + u16 SSP_Mode; + u16 SSP_CPOL; + u16 SSP_CPHA; + u16 SSP_DataSize; + u16 SSP_NSS; + u16 SSP_SlaveOutput; + u8 SSP_ClockRate; + u8 SSP_ClockPrescaler; +}SSP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SSP Frame Format Select */ +#define SSP_FrameFormat_TI 0x0010 +#define SSP_FrameFormat_Motorola 0xFFCF + +/* SSP Master/Slave Select */ +#define SSP_Mode_Master 0xFFFB +#define SSP_Mode_Slave 0x0004 + +/* SSP Clock Polarity */ +#define SSP_CPOL_Low 0xFFBF +#define SSP_CPOL_High 0x0040 + +/* SSP Clock Phase */ +#define SSP_CPHA_1Edge 0xFF7F +#define SSP_CPHA_2Edge 0x0080 + +/* SSP Data Size */ +#define SSP_DataSize_16b 0x000F +#define SSP_DataSize_15b 0x000E +#define SSP_DataSize_14b 0x000D +#define SSP_DataSize_13b 0x000C +#define SSP_DataSize_12b 0x000B +#define SSP_DataSize_11b 0x000A +#define SSP_DataSize_10b 0x0009 +#define SSP_DataSize_9b 0x0008 +#define SSP_DataSize_8b 0x0007 +#define SSP_DataSize_7b 0x0006 +#define SSP_DataSize_6b 0x0005 +#define SSP_DataSize_5b 0x0004 +#define SSP_DataSize_4b 0x0003 + +/* SSP Slave Select management config */ +#define SSP_NSS_Hard 0xFFEF +#define SSP_NSS_Soft 0x0010 + +/* SSP NSS internal config */ +#define SSP_NSSInternal_Set 0x0020 +#define SSP_NSSInternal_Reset 0xFFDF + +/* SSP Slave output config */ +#define SSP_SlaveOutput_Enable 0xFFF7 +#define SSP_SlaveOutput_Disable 0x0008 + +/* SSP Interrupts */ +#define SSP_IT_TxFifo 0x0008 +#define SSP_IT_RxFifo 0x0004 +#define SSP_IT_RxTimeOut 0x0002 +#define SSP_IT_RxOverrun 0x0001 + +/* SSP Flags */ +#define SSP_FLAG_Busy 0x0024 +#define SSP_FLAG_RxFifoFull 0x0023 +#define SSP_FLAG_RxFifoNotEmpty 0x0022 +#define SSP_FLAG_TxFifoNotFull 0x0021 +#define SSP_FLAG_TxFifoEmpty 0x0020 +#define SSP_FLAG_TxFifo 0x0043 +#define SSP_FLAG_RxFifo 0x0042 +#define SSP_FLAG_RxTimeOut 0x0041 +#define SSP_FLAG_RxOverrun 0x0040 + +/* SSP DMA Requests */ +#define SSP0_DMA_Transmit 0x0002 +#define SSP0_DMA_Receive 0x0001 + +#define SSP0_DMATxReq_Single 0xFFF7 +#define SSP0_DMATxReq_Burst 0x0008 + +#define SSP0_DMARxReq_Single 0xFFFB +#define SSP0_DMARxReq_Burst 0x0004 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SSP_DeInit(SSP_TypeDef* SSPx); +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); +void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState); +void SSP_DMATxConfig(u16 SSP0_DMATxReq); +void SSP_DMARxConfig(u16 SSP0_DMARxReq); +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); +u16 SSP_ReceiveData(SSP_TypeDef* SSPx); +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState); +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); + +#endif /* __75x_SSP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h new file mode 100644 index 0000000000..e5054935d8 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tb.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* TB software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TB_H +#define __75x_TB_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 TB_Mode; /* TB mode */ + u16 TB_ClockSource; /* TB clock source: CK_TIM or CK_RTC */ + u16 TB_CounterMode; /* TB counter mode */ + u16 TB_ICAPolarity; /* TB Input Capture signal Polarity */ + u16 TB_Prescaler; /* TB Prescaler factor */ + u16 TB_AutoReload; /* TB AutoReload factor */ +} TB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TB modes */ +#define TB_Mode_IC 0x0002 +#define TB_Mode_Timing 0x0001 + +/* TB clock source */ +#define TB_ClockSource_CKTIM 0x0001 +#define TB_ClockSource_CKRTC 0x0002 + +/* TB Input capture polarity */ +#define TB_ICAPolarity_Rising 0x7000 +#define TB_ICAPolarity_Falling 0x8000 + +/* TB counter modes */ +#define TB_CounterMode_Up 0x0000 +#define TB_CounterMode_Down 0x0010 +#define TB_CounterMode_CenterAligned 0x0060 + +/* TB interrupt sources */ +#define TB_IT_Update 0x0001 +#define TB_IT_IC 0x0004 +#define TB_IT_GlobalUpdate 0x8001 + +/* TB Flags */ +#define TB_FLAG_IC 0x0004 +#define TB_FLAG_Update 0x0001 + +/* TB Slave Mode Selection */ +#define TB_SMSMode_Trigger 0x0018 +#define TB_SMSMode_Gated 0x0010 +#define TB_SMSMode_External 0x0008 +#define TB_SMSMode_Reset 0x0000 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TB_DeInit(void); +void TB_Init(TB_InitTypeDef* TB_InitStruct); +void TB_StructInit(TB_InitTypeDef *TB_InitStruct); +void TB_Cmd(FunctionalState Newstate ); +void TB_ITConfig(u16 TB_IT, FunctionalState Newstate); +void TB_SetPrescaler(u16 Prescaler); +void TB_ResetCounter(void); +void TB_DebugCmd(FunctionalState Newstate); +void TB_CounterModeConfig(u16 TB_CounterMode); +void TB_SLaveModeConfig(u16 TB_SMSMode); +u16 TB_GetCounter(void); +u16 TB_GetICAP1(void); +void TB_SetCounter(u16 Counter); +FlagStatus TB_GetFlagStatus(u16 TB_FLAG); +void TB_ClearFlag(u16 TB_FLAG); +ITStatus TB_GetITStatus(u16 TB_IT); +void TB_ClearITPendingBit(u16 TB_IT); + +#endif /* __75x_TB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h new file mode 100644 index 0000000000..02b51321bb --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h @@ -0,0 +1,232 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tim.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TIM_H +#define __75x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 TIM_Mode; /* Timer Mode */ + u16 TIM_Prescaler; /* Prescaler value */ + u16 TIM_ClockSource; /* Timer clock source */ + u16 TIM_ExtCLKEdge; /* External clock edge */ + u16 TIM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ + u16 TIM_Period; /* Period value */ + u16 TIM_Channel; /* Timer Channel: 1, 2 or All */ + u16 TIM_Pulse1; /* PWM or OCM Channel 1 pulse length */ + u16 TIM_Pulse2; /* PWM or OCM Channel 2 pulse length */ + u16 TIM_RepetitivePulse; /* OPM Repetitive pulse state: enable or disable */ + u16 TIM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ + u16 TIM_Polarity2; /* PWM or OCM Channel 2 polarity */ + u16 TIM_IC1Selection; /* Input Capture 1 selection: TI1 or TI2 */ + u16 TIM_IC2Selection; /* Input Capture 2 selection: TI1 or TI2 */ + u16 TIM_IC1Polarity; /* Input Capture 1 polarity */ + u16 TIM_IC2Polarity; /* Input Capture 2 polarity */ + u16 TIM_PWMI_ICSelection; /* PWM Input Capture selection: TI1 or TI2 */ + u16 TIM_PWMI_ICPolarity; /* PWM Input Capture Polarity */ +} TIM_InitTypeDef; + +/* Master and slave synchronized Timer peripherals */ +typedef enum +{ + PWM_Master = 0x01, + TIM0_Master, + TIM1_Master, + TIM2_Master +}Master_TypeDef; + +typedef enum +{ + PWM_Slave = 0x05, + TIM0_Slave, + TIM1_Slave, + TIM2_Slave +}Slave_TypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TIM modes */ +#define TIM_Mode_OCTiming 0x0001 +#define TIM_Mode_OCActive 0x0002 +#define TIM_Mode_OCInactive 0x0003 +#define TIM_Mode_OCToggle 0x0004 +#define TIM_Mode_PWM 0x0005 +#define TIM_Mode_PWMI 0x0006 +#define TIM_Mode_IC 0x0007 +#define TIM_Mode_Encoder1 0x0008 +#define TIM_Mode_Encoder2 0x0009 +#define TIM_Mode_Encoder3 0x000A +#define TIM_Mode_OPM_PWM 0x000B +#define TIM_Mode_OPM_Toggle 0x000C +#define TIM_Mode_OPM_Active 0x000D + +/* TIM Clock Source */ +#define TIM_ClockSource_Internal 0x0001 +#define TIM_ClockSource_TI11 0x0002 +#define TIM_ClockSource_TI12 0x0003 +#define TIM_ClockSource_TI22 0x0004 +#define TIM_ClockSource_TI21 0x0005 + +/* TIM External Clock Edge */ +#define TIM_ExtCLKEdge_Falling 0x0001 +#define TIM_ExtCLKEdge_Rising 0x0002 + +/* TIM Counter Mode */ +#define TIM_CounterMode_Up 0x0000 +#define TIM_CounterMode_Down 0x0010 +#define TIM_CounterMode_CenterAligned1 0x0020 +#define TIM_CounterMode_CenterAligned2 0x0040 +#define TIM_CounterMode_CenterAligned3 0x0060 + +/* TIM Channel */ +#define TIM_Channel_1 0x0001 +#define TIM_Channel_2 0x0002 +#define TIM_Channel_ALL 0x0003 + +/* TIM Polarity channel 1 */ +#define TIM_Polarity1_High 0x0001 +#define TIM_Polarity1_Low 0x0002 + +/* TIM Polarity channel 2 */ +#define TIM_Polarity2_High 0x0001 +#define TIM_Polarity2_Low 0x0002 + +#define TIM_RepetitivePulse_Disable 0x0005 +#define TIM_RepetitivePulse_Enable 0x0006 + +/* TIM Input Capture channel 1 Selection */ +#define TIM_IC1Selection_TI1 0x0001 +#define TIM_IC1Selection_TI2 0x0002 + +/* TIM Input Capture channel 2 Selection */ +#define TIM_IC2Selection_TI1 0x0001 +#define TIM_IC2Selection_TI2 0x0002 + +/* TIM Input Capture channel 1 Polarity */ +#define TIM_IC1Polarity_Falling 0x0001 +#define TIM_IC1Polarity_Rising 0x0002 + +/* TIM Input Capture channel 2 Polarity */ +#define TIM_IC2Polarity_Falling 0x0001 +#define TIM_IC2Polarity_Rising 0x0002 + +/* TIM PWM Input IC Selection */ +#define TIM_PWMI_ICSelection_TI1 0x0001 +#define TIM_PWMI_ICSelection_TI2 0x0002 + +/* TIM PWM Input IC Polarity */ +#define TIM_PWMI_ICPolarity_Falling 0x0003 +#define TIM_PWMI_ICPolarity_Rising 0x0004 + +/* TIM interrupt sources */ +#define TIM_IT_IC1 0x0004 +#define TIM_IT_IC2 0x0008 +#define TIM_IT_OC1 0x0100 +#define TIM_IT_OC2 0x0200 +#define TIM_IT_Update 0x0001 +#define TIM_IT_GlobalUpdate 0x1001 + +/* TIM DMA sources */ +#define TIM_DMASource_IC1 0x0004 +#define TIM_DMASource_IC2 0x0008 +#define TIM_DMASource_OC1 0x0100 +#define TIM_DMASource_OC2 0x0200 +#define TIM_DMASource_Update 0x0001 + +/* TIM DMA Base address */ +#define TIM_DMABase_CR 0x0000 +#define TIM_DMABase_SCR 0x0800 +#define TIM_DMABase_IMCR 0x1000 +#define TIM_DMABase_OMR1 0x1800 +#define TIM_DMABase_RSR 0x3000 +#define TIM_DMABase_RER 0x3800 +#define TIM_DMABase_ISR 0x4000 +#define TIM_DMABase_CNT 0x4800 +#define TIM_DMABase_PSC 0x5000 +#define TIM_DMABase_ARR 0x6000 +#define TIM_DMABase_OCR1 0x6800 +#define TIM_DMABase_OCR2 0x7000 +#define TIM_DMABase_ICR1 0x9800 +#define TIM_DMABase_ICR2 0xA000 + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x0004 +#define TIM_FLAG_IC2 0x0008 +#define TIM_FLAG_OC1 0x0100 +#define TIM_FLAG_OC2 0x0200 +#define TIM_FLAG_Update 0x0001 + +/* TIM_ForcedAction */ +#define TIM_ForcedAction_Active 0x000A +#define TIM_ForcedAction_InActive 0x0008 + +/* TIM synchronization action */ +#define TIM_SynchroAction_Enable 0x0100 +#define TIM_SynchroAction_Update 0x0200 +#define TIM_SynchroAction_Reset 0x0000 +#define TIM_SynchroAction_OC 0x0300 + +/* TIM synchronization mode */ +#define TIM_SynchroMode_Gated 0x0010 +#define TIM_SynchroMode_Trigger 0x0018 +#define TIM_SynchroMode_External 0x0008 +#define TIM_SynchroMode_Reset 0x0000 + +/* OCRM bit states */ +#define TIM_OCRMState_Enable 0x0005 +#define TIM_OCRMState_Disable 0x0006 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate); +void TIM_PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, FunctionalState Newstate); +void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase); +void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate); +void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, + u16 TIM_ExtCLKEdge); +void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler); +void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period); +void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse); +u16 TIM_GetICAP1(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); +void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, + u16 TIM_ForcedAction); +void TIM_ResetCounter(TIM_TypeDef* TIMx); +void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, + u16 TIM_SynchroAction, u16 TIM_SynchroMode); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); + +#endif /* __75x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h new file mode 100644 index 0000000000..6f8842700b --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h @@ -0,0 +1,71 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_type.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the common data types used for the +* STR75x software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TYPE_H +#define __75x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_TYPE_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h new file mode 100644 index 0000000000..6fc5033ab1 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h @@ -0,0 +1,178 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_uart.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_UART_H +#define __75x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + RTSRESET = 1, + RTSSET +}UART_RTSTypeDef; + + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* One stop bit is transmitted at + the end of frame */ +#define UART_StopBits_2 0x0008 /* Tow stop bits are transmitted + at the end of frame */ + +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000/* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000/* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000/* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000/* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt */ +#define UART_IT_Receive 0x0010 /* Receive interrupt */ +#define UART_IT_CTS 0x0002 /* CTS interrupt */ + +/* UART0 DMA transfer */ +#define UART0_DMATransfer_Single 0xFFF7 /* Single DMA transfer */ +#define UART0_DMATransfer_Burst 0x0008 /* Burst DMA transfer */ + +/* UART0 DMA On Error */ +#define UART0_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART0 error interrupt + is asserted. */ +#define UART0_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART0 error interrupt + is asserted. */ + +/* UART0 DMA Request */ +#define UART0_DMAReq_Tx 0x0002 /* Transmit DMA Enable */ +#define UART0_DMAReq_Rx 0x0001 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Masked IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Masked IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Masked IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Masked IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Masked IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Masked IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Masked IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Masked IT flag */ + +/* UART LIN break length */ +#define UART_LINBreakLength_10 0x0000 /* 10 low bits */ +#define UART_LINBreakLength_11 0x0200 /* 11 low bits */ +#define UART_LINBreakLength_12 0x0400 /* 12 low bits */ +#define UART_LINBreakLength_13 0x0600 /* 13 low bits */ +#define UART_LINBreakLength_14 0x0800 /* 14 low bits */ +#define UART_LINBreakLength_15 0x0A00 /* 15 low bits */ +#define UART_LINBreakLength_16 0x0C00 /* 16 low bits */ +#define UART_LINBreakLength_17 0x0E00 /* 17 low bits */ +#define UART_LINBreakLength_18 0x1000 /* 18 low bits */ +#define UART_LINBreakLength_19 0x1200 /* 19 low bits */ +#define UART_LINBreakLength_20 0x1400 /* 20 low bits */ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError); +void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength); +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __75x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h new file mode 100644 index 0000000000..3390b63f32 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h @@ -0,0 +1,62 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_wdg.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_WDG_H +#define __75x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + typedef struct +{ + u16 WDG_Mode; /* Watchdog or Timer mode */ + u16 WDG_Preload; /* Preload register */ + u8 WDG_Prescaler; /* Prescaler register */ +}WDG_InitTypeDef; +/* Exported constants --------------------------------------------------------*/ + +/* WDG/Timer Select */ +#define WDG_Mode_WDG 0x0001 +#define WDG_Mode_Timer 0xFFFE + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + +/* WDG end of count Flag */ +#define WDG_FLAG_EC 0x0001 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c new file mode 100644 index 0000000000..93905cb6c7 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c @@ -0,0 +1,869 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_adc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the ADC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_adc.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Mask for Power Down Mode */ +#define ADC_PowerDown_Enable 0x8000 +#define ADC_PowerDown_Disable 0x7FFF + +/* Mask for Watchdog Thresholds Enable */ +#define ADC_AnalogWatchdog_Enable 0x8000 +#define ADC_AnalogWatchdog_Disable 0x7FFF + +/* Mask for Injected conversion start */ +#define ADC_Injec_ConversionStart 0x8000 + +/* DMA enable */ +#define ADC_DMA_ExtEnable_Mask 0x4000 + +/* Injected start trigger enable */ +#define ADC_Injec_ExtTrigger_Enable 0x4000 + +/* ADC Masks */ +#define ADC_DMAFirstEnabledChannel_Mask 0x000F +#define ADC_DataRegisterOffset 0x0050 +#define ADC_FirstChannel_Mask 0xFFF0 +#define ADC_ChannelNumber_Mask 0xFC3F +#define ADC_Threshold_Mask 0xFC00 +#define ADC_AnalogWatchdogChannel_Mask 0xC3FF +#define ADC_Prescalers_Mask 0x7F18 +#define ADC_SPEN_Mask 0x8000 +#define ADC_FallingEdge_Mask 0xEFFF +#define ADC_LowLevel_Mask 0x4000 +#define ADC_HighLevel_Mask 0xDFFF +#define ADC_Calibration_Mask 0x0002 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitializes the ADC peripheral registers to their default +* reset values. +* Input : None. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_DeInit(void) +{ + /* Reset the ADC registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,DISABLE); +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes the ADC peripheral according to the specified +* parameters in the ADC_InitStruct. +* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that + contains the configuration information for the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Configure the conversion mode */ + if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Scan) + { + /* Set the scan conversion mode */ + ADC->CLR2 |= ADC_ConversionMode_Scan; + } + else + { + /* Set the one-shot conversion mode */ + ADC->CLR2 &= ADC_ConversionMode_OneShot; + } + + /* Configure the external start conversion trigger */ + switch(ADC_InitStruct->ADC_ExtTrigger) + { + case ADC_ExtTrigger_HighLevel: + /* Start conversion on High level of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_HighLevel_Mask; + ADC->CLR0 |= ADC_ExtTrigger_HighLevel; + break; + + case ADC_ExtTrigger_LowLevel: + /* Start conversion on low level of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_ExtTrigger_LowLevel; + ADC->CLR0 |= ADC_LowLevel_Mask; + break; + + case ADC_ExtTrigger_RisingEdge: + /* Start conversion on rising edge of the external trigger (TIM0) */ + ADC->CLR0 |= ADC_ExtTrigger_RisingEdge; + break; + + case ADC_ExtTrigger_FallingEdge: + /* Start conversion on falling edge of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_FallingEdge_Mask; + ADC->CLR0 |= ADC_ExtTrigger_FallingEdge; + break; + + case ADC_ExtTrigger_Disable: + /* Disable the external trigger and start the conversion by software */ + ADC->CLR0 &= ADC_ExtTrigger_Disable; + break; + + default: + break; + } + + /* Configure the auto clock off feature */ + if (ADC_InitStruct->ADC_AutoClockOff == ADC_AutoClockOff_Enable) + { + /* Enable the auto clock off feature */ + ADC->CLR4 |= ADC_AutoClockOff_Enable; + } + else + { + /* Disable the auto clock off feature */ + ADC->CLR4 &= ADC_AutoClockOff_Disable; + } + + /* Clear conversion prescaler CNVP[2:0], sampling prescaler SMPP[2:0] bits + and Sample prescaler enable SPEN bit */ + ADC->CLR1 &= ADC_Prescalers_Mask; + /* Set conversion prescaler value (sampling and conversion prescalers are equal + while SPEN bit is reset */ + ADC->CLR1 |= (ADC_InitStruct->ADC_ConversionPrescaler<<5); + + /* In case ADC_SamplingPrescaler member is different from the conversion one */ + if(ADC_InitStruct->ADC_SamplingPrescaler != ADC_InitStruct->ADC_ConversionPrescaler) + { + /* Set the sampling prescaler value */ + ADC->CLR1 |= ADC_InitStruct->ADC_SamplingPrescaler; + /* Set SPEN bit (sampling and conversion prescalers are different */ + ADC->CLR1 = (ADC->CLR1 | ADC_SPEN_Mask); + } + + /* Clear first channel to be converted FCH[3:0] bits */ + ADC->CLR2 &= ADC_FirstChannel_Mask; + /* Set the first channel to be converted */ + ADC->CLR2 |= ADC_InitStruct->ADC_FirstChannel; + /* Clear number of channels to be converted NCH[3:0] bits */ + ADC->CLR2 &= ADC_ChannelNumber_Mask; + /* Set the number of channels to be converted */ + ADC->CLR2 |= ((ADC_InitStruct->ADC_ChannelNumber)-1<<6); +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its default value. +* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_ConversionMode member */ + ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_OneShot; + + /* Initialize the ADC_ExtTrigger member */ + ADC_InitStruct->ADC_ExtTrigger = ADC_ExtTrigger_Disable; + + /* Initialize the ADC_AutoClockOff member */ + ADC_InitStruct->ADC_AutoClockOff = ADC_AutoClockOff_Disable; + + /* Initialize the ADC_SamplingPrescaler member */ + ADC_InitStruct->ADC_SamplingPrescaler = 0; + + /* Initialize the ADC_ConversionPrescaler member */ + ADC_InitStruct->ADC_ConversionPrescaler = 0; + + /* Initialize the ADC_FirstChannel member */ + ADC_InitStruct->ADC_FirstChannel = ADC_CHANNEL0; + + /* Initialize the ADC_ChannelNumber member */ + ADC_InitStruct->ADC_ChannelNumber = 1; + } + +/******************************************************************************* +* Function Name : ADC_StartCalibration +* Description : Starts the ADC Calibration. Calibration average enabled/disabled. +* Input : - ADC_CalibAverage: Enables or disables ADC calibration average. +* This parameter can be one of the following values: +* - ADC_CalibAverage_Enable: enable calibration average +* - ADC_CalibAverage_Disable: disable calibration average +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartCalibration(u16 ADC_CalibAverage) +{ + if (ADC_CalibAverage == ADC_CalibAverage_Enable) + { + /* Enable ADC Calibration Average */ + ADC->CLR4 &= ADC_CalibAverage_Enable; + } + else + { + /* Disable ADC Calibration Average */ + ADC->CLR4 |= ADC_CalibAverage_Disable; + } + + /* Start Calibration */ + ADC->CLR0 |= ADC_Calibration_ON; +} + +/******************************************************************************* +* Function Name : ADC_GetCalibrationStatus +* Description : Get the ADC Calibration Status. +* Input : None +* Output : None +* Return : The NewState of the ADC calibration (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetCalibrationStatus(void) +{ + /* Check the status of the ADC calibration */ + if((ADC->CLR0 & ADC_Calibration_Mask) != RESET) + { + /* Return SET if ADC Calibration is on going */ + return SET; + } + else + { + /* Return RESET if ADC Calibration is finished */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ConversionCmd +* Description : Starts or stops the ADC conversion. +* Input : - ADC_Conversion: specifies the ADC command to apply. +* This parameter can be one of the following values: +* - ADC_Conversion_Start: start conversion +* - ADC_Conversion_Stop: stop conversion +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ConversionCmd (u16 ADC_Conversion) +{ + if (ADC_Conversion == ADC_Conversion_Start) + { + /* Start the ADC Conversion */ + ADC->CLR0 |= ADC_Conversion_Start; + } + else + { + /* Stop the ADC Conversion */ + ADC->CLR0 &= ADC_Conversion_Stop; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSTARTBitStatus +* Description : Gets the ADC START/STOP bit Status. +* Input : None +* Output : None +* Return : The NewState of the ADC START/STOP bit (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSTARTBitStatus(void) +{ + /* Check the status of the ADC START/STOP bit */ + if((ADC->CLR0 & ADC_Conversion_Start) != RESET) + { + /* Return SET if ADC Conversion is started */ + return SET; + } + else + { + /* Return RESET if ADC Conversion is stopped */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Enables the ADC peripheral or puts it in power down mode. +* - NewState: new state of the ADC peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_Cmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + /* Enable ADC Power Down Mode */ + ADC->CLR4 |= ADC_PowerDown_Enable; + } + else + { + /* Disable ADC Power Down Mode */ + ADC->CLR4 &= ADC_PowerDown_Disable; + } +} + +/******************************************************************************* +* Function Name : ADC_AutoClockOffConfig +* Description : Enables or disables the Auto clock off feature. +* - NewState: new state of the Auto clock off feature. This +* parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_AutoClockOffConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable ADC Auto Clock Off */ + ADC->CLR4 |= ADC_AutoClockOff_Enable; + } + else + { + /* Disable ADC Auto Clock Off */ + ADC->CLR4 &= ADC_AutoClockOff_Disable; + } +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogConfig +* Description : Configures the analog input channel to be used for the selected +* Analog Watchdog and defines its corresponding High and Low +* threshold values. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog which will +* be affected to the desired converted channel. This parameter +* can be one of the following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* - ADC_CHANNEL: specifies the channel linked to the selected +* analog watchdog. This parameter can be ADC_CHANNELx where x +* can be (0..15) +* - LowThreshold: Low Threshold for the selected Analog watchdog +* - HighThreshold: High Threshold for the selected Analog watchdog +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, + u16 LowThreshold, u16 HighThreshold) +{ + switch (ADC_AnalogWatchdog) + { + /* Set the selected channel and their corresponding High and Low thresholds */ + case ADC_AnalogWatchdog0 : + ADC->TRA0 = (ADC->TRA0 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA0 = (ADC->TRA0 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB0 = (ADC->TRB0 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRA1 = (ADC->TRA1 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA1 = (ADC->TRA1 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB1 = (ADC->TRB1 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRA2 = (ADC->TRA2 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA2 = (ADC->TRA2 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB2 = (ADC->TRB2 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRA3 = (ADC->TRA3 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA3 = (ADC->TRA3 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB3 = (ADC->TRB3 & ADC_Threshold_Mask) | LowThreshold; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogCmd +* Description : Enables or disables the selected analog Watchdog. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog to be +* enabled or disabled. This parameter can be one of the +* following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* - NewState: new state of the specified analog watchdog. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected ADC AnalogWatchdogx */ + switch (ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + ADC->TRB0 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRB1 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRB2 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRB3 |= ADC_AnalogWatchdog_Enable; + break; + + default: + break; + } + } + else + { + /* Disable the selected ADC AnalogWatchdogx */ + switch (ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + ADC->TRB0 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRB1 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRB2 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRB3 &= ADC_AnalogWatchdog_Disable; + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name : ADC_GetAnalogWatchdogResult +* Description : Returns the comparison result of the selected analog watchdog. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog channel +* which its comparison result will be returned. This parameter +* can be one of the following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* Output : None +* Return : The analog watchdog comparaison result value +*******************************************************************************/ +u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog) +{ + /* Return the selected ADC AnalogWatchdogx comparaison result */ + switch(ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>4); + + case ADC_AnalogWatchdog1 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>6); + + case ADC_AnalogWatchdog2 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>8); + + case ADC_AnalogWatchdog3 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>10); + + default : return (0xFF); /* if a wrong value of ADC_AnalogWatchdog is selected */ + } +} + +/******************************************************************************* +* Function Name : ADC_InjectedConversionConfig +* Description : Configures the start trigger level for the injected channels +* and the injected analog input channels to be converted. +* Input : - ADC_Injec_ExtTrigger: specifies the start trigger level. +* This parameter can be one of the following values: +* - ADC_Injec_ExtTrigger_Disable : external trigger disabled +* - ADC_Injec_ExtTrigger_RisingEdge: external trigger +* configured as rising edge of PWM Timer TRGO signal +* - ADC_Injec_ExtTrigger_FallingEdge: external trigger +* configured as falling edge of PWM Timer TRGO signal +* - FirstChannel: specifies the first injected channel to be +* converted. +* This parameter can be ADC_CHANNELx where x can be (0..15). +* - ChannelNumber: specifies the Number of the injected channels +* to be converted. This parameter can be a value from 1 to 16. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber) +{ + /* Configure the external start injected conversion trigger */ + switch (ADC_Injec_ExtTrigger) + { + case ADC_Injec_ExtTrigger_Disable : + /* Disable the external trigger and start the injected conversion by software */ + ADC->CLR3 &= ADC_Injec_ExtTrigger_Disable ; + break; + case ADC_Injec_ExtTrigger_RisingEdge : + /* Start injected conversion on rising edge of the external trigger (PWM) */ + ADC->CLR3 |= ADC_Injec_ExtTrigger_RisingEdge; + break; + case ADC_Injec_ExtTrigger_FallingEdge : + /* Start injected conversion on falling edge of the external trigger (PWM) */ + ADC->CLR3 |= ADC_Injec_ExtTrigger_Enable; + ADC->CLR3 &= ADC_Injec_ExtTrigger_FallingEdge; + break; + + default: + break; + } + + /* Clear first injected channel to be converted JFCH[3:0] bits */ + ADC->CLR3 &= ADC_FirstChannel_Mask; + /* Set the first injected channel to be converted */ + ADC->CLR3 |= FirstChannel; + /* Clear number of injected channels to be converted JNCH[3:0] bits */ + ADC->CLR3 &= ADC_ChannelNumber_Mask; + /* Set the number of injected channels to be converted */ + ADC->CLR3 |= ((ChannelNumber-1)<<6); +} + +/******************************************************************************* +* Function Name : ADC_StartInjectedConversion +* Description : Starts by software the conversion of the injected input channels. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartInjectedConversion(void) +{ + /* Start the injected ADC Conversion */ + ADC->CLR3 |= ADC_Injec_ConversionStart; +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Reads the conversion result from the appropriate data register. +* Input : - ADC_CHANNEL :specifies the ADC channel which its conversion +* value have to be returned. This parameter can be ADC_CHANNELx +* where x can be (0..15) to select channelx +* Output : None +* Return : The returned value holds the conversion result of the selected +* channel. +*******************************************************************************/ +u16 ADC_GetConversionValue(u8 ADC_CHANNEL) +{ + /* Return the conversion result of the selected channel */ + return *((u16 *)(ADC_BASE + ((ADC_CHANNEL<<2) + ADC_DataRegisterOffset))); +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADC_IT: specifies the ADC interrupts to be enabled or disabled. +* This parameter can be any combination of the following values: +* - ADC_IT_ECH: End of chain conversion interrupt +* - ADC_IT_EOC: End of channel conversion interrupt +* - ADC_IT_JECH: Injected end of chain conversion interrupt +* - ADC_IT_JEOC: Injected end of channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 5 HighThreshold interrupt +* - ADC_IT_ALL: All interrupts +* - NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected ADC interrupts */ + ADC->IMR |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADC->IMR &= ~ADC_IT; + } +} + +/******************************************************************************* +* Function Name : ADC_DMAConfig +* Description : Configures the ADC’s DMA interface. +* Input : - ADC_DMA_CHANNEL: specifies the channels to be enabled or +* disabled for DMA transfer. This parameter can be any +* combination of ADC_DMA_CHANNELx where x can be (0..15). +* - NewState: new state of the specified ADC DMA channels. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable DMA for the selected channels */ + ADC->DMAR |= ADC_DMA_CHANNEL ; + } + else + { + /* Disable DMA for the selected channels */ + ADC->DMAR &= ~ADC_DMA_CHANNEL; + } +} + +/******************************************************************************* +* Function Name : ADC_DMACmd +* Description : Enable or disable the DMA transfer for the ADC. +* Input : - ADC_DMA: specifies the DMA command. This parameter can be +* one of the following values: +* - ADC_DMA_Disable: disable the DMA capability +* - ADC_DMA_Enable: enabled by setting the global +* enable bit +* - ADC_DMA_ExtTrigger_HighLevel: enabled by detection of +* high level of TIM2 OC2 signal +* - ADC_DMA_ExtTrigger_LowLevel: enabled by detection of +* low level of TIM2 OC2 signal +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMACmd(u16 ADC_DMA) +{ + /* Configure the DMA external trigger enable */ + switch (ADC_DMA) + { + case ADC_DMA_Disable : + /* Disable DMA transfer */ + ADC->DMAE &= ADC_DMA_Disable; + break; + + case ADC_DMA_Enable : + /* Enable DMA transfer */ + ADC->DMAE |= ADC_DMA_Enable; + break; + + case ADC_DMA_ExtTrigger_HighLevel : + /* Enable DMA transfer on high level of the external trigger (TIM2) */ + ADC->DMAE &= ADC_DMA_Disable; + ADC->DMAE |= ADC_DMA_ExtTrigger_HighLevel; + break; + + case ADC_DMA_ExtTrigger_LowLevel : + /* Enable DMA transfer on low level of the external trigger (TIM2) */ + ADC->DMAE |= ADC_DMA_ExtEnable_Mask; + ADC->DMAE &= ADC_DMA_ExtTrigger_LowLevel; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_GetDMAFirstEnabledChannel +* Description : Gets the first DMA-enabled channel configured at the time that +* DMA was last globally enabled. +* Input : None +* Output : None +* Return : The first DMA enabled channel +*******************************************************************************/ +u16 ADC_GetDMAFirstEnabledChannel(void) +{ + /* Return the DMA first enabled channel */ + return (ADC->DMAE & ADC_DMAFirstEnabledChannel_Mask); +} + +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : - ADC_FLAG: specifies the ADC flag to check. This parameter +* can be one of the following values: +* - ADC_FLAG_ECH: End of chain conversion Flag +* - ADC_FLAG_EOC: End of channel conversion Flag +* - ADC_FLAG_JECH: End of injected chain conversion Flag +* - ADC_FLAG_JEOC: End of injected channel conversion Flag +* - ADC_FLAG_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold Flag +* Output : None +* Return : The new state of the ADC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG) +{ + /* Check the status of the specified ADC flag */ + if((ADC->PBR & ADC_FLAG) != RESET) + { + /* Return SET if ADC_FLAG is set */ + return SET; + } + else + { + /* Return RESET if ADC_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ClearFlag +* Description : Clears the ADC’s pending flags. +* Input : - ADC_FLAG: specifies the flag to clear. This parameter can +* be any combination of the following values: +* - ADC_FLAG_ECH: End of chain conversion flag +* - ADC_FLAG_EOC: End of channel conversion flag +* - ADC_FLAG_JECH: Injected end of chain conversion flag +* - ADC_FLAG_JEOC: Injected end of channel conversion flag +* - ADC_FLAG_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold flag +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearFlag(u16 ADC_FLAG) +{ + /* Clear the selected ADC flag */ + ADC->PBR = ADC_FLAG; +} + +/******************************************************************************* +* Function Name : ADC_GetITStatus +* Description : Checks whether the specified ADC interrupt has occured or not. +* Input : - ADC_IT: specifies the ADC interrupt source to check. This +* parameter can be one of the following values: +* - ADC_IT_ECH :End of chain conversion interrupt +* - ADC_IT_EOC :End of channel conversion interrupt +* - ADC_IT_JECH :End of injected chain conversion interrupt +* - ADC_IT_JEOC :End of injected channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold interrupt +* Output : None +* Return : The new state of the ADC_IT (SET or RESET). +*******************************************************************************/ +ITStatus ADC_GetITStatus(u16 ADC_IT) +{ + /* Check the status of the specified ADC interrupt */ + if((ADC->PBR & ADC_IT) != RESET) + { + /* Return SET if the ADC interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if the ADC interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ClearITPendingBit +* Description : Clears the ADC’s interrupt pending bits. +* Input : - ADC_IT: specifies the interrupt pending bit to clear. This +* parameter can be can be any combination of the following +* values: +* - ADC_IT_ECH: End of chain conversion interrupt +* - ADC_IT_EOC: End of channel conversion interrupt +* - ADC_IT_JECH: Injected end of chain conversion interrupt +* - ADC_IT_JEOC: Injected end of channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 5 HighThreshold interrupt +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearITPendingBit(u16 ADC_IT) +{ + /* Clear the selected ADC interrupts pending bits */ + ADC->PBR = ADC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c new file mode 100644 index 0000000000..0472200baf --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c @@ -0,0 +1,765 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_can.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_can.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates*/ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ + CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ + CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,DISABLE); +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ + CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c new file mode 100644 index 0000000000..593e8b84d3 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c @@ -0,0 +1,122 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_cfg.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the CFG software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_cfg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CFG_SWBOOT_Mask 0xFFFFFFFC +#define CFG_FLASHBusy_Mask 0x00000080 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CFG_BootSpaceConfig +* Description : Selects which memory space will be remapped at address 0x00. +* Input : - CFG_BootSpace: specifies the memory space to be remapped +* at address 0x00. +* This parameter can be one of the following values: +* - CFG_BootSpace_FLASH +* - CFG_BootSpace_SRAM +* - CFG_BootSpace_ExtSMI +* Output : None +* Return : None +*******************************************************************************/ +void CFG_BootSpaceConfig(u32 CFG_BootSpace) +{ + u32 Temp = 0; + + /* Clear SW_BOOT[1:0] bits */ + Temp = CFG->GLCONF & CFG_SWBOOT_Mask; + + /* Set SW_BOOT[1:0] bits according to CFG_BootSpace parameter value */ + Temp |= CFG_BootSpace; + + /* Store the new value */ + CFG->GLCONF = Temp; +} + +/******************************************************************************* +* Function Name : CFG_FLASHBurstConfig +* Description : Enables or disables the FLASH Burst mode. +* Input : - CCFG_FLASHBurst: specifies the new state of the FLASH Burst +* mode. +* This parameter can be one of the following values: +* - CFG_FLASHBurst_Disable +* - CFG_FLASHBurst_Enable +* Output : None +* Return : None +*******************************************************************************/ +void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst) +{ + if(CFG_FLASHBurst == CFG_FLASHBurst_Enable) + { + CFG->GLCONF |= CFG_FLASHBurst_Enable; + } + else + { + CFG->GLCONF &= CFG_FLASHBurst_Disable; + } +} + +/******************************************************************************* +* Function Name : CFG_USBFilterConfig +* Description : Enables or disables the USB Filter. +* Input : - CFG_USBFilter: specifies the new state of the USB Filter. +* This parameter can be one of the following values: +* - CFG_USBFilter_Disable +* - CFG_USBFilter_Enable +* Output : None +* Return : None +*******************************************************************************/ +void CFG_USBFilterConfig(u32 CFG_USBFilter) +{ + if(CFG_USBFilter == CFG_USBFilter_Enable) + { + CFG->GLCONF |= CFG_USBFilter_Enable; + } + else + { + CFG->GLCONF &= CFG_USBFilter_Disable; + } +} + +/******************************************************************************* +* Function Name : CFG_GetFlagStatus +* Description : Checks whether the FLASH Busy flag is set or not. +* Input : None +* Output : None +* Return : The new state of FLASH Busy flag (SET or RESET). +*******************************************************************************/ +FlagStatus CFG_GetFlagStatus(void) +{ + if((CFG->GLCONF & CFG_FLASHBusy_Mask) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c new file mode 100644 index 0000000000..7bc09466d2 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c @@ -0,0 +1,596 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_dma.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the DMA software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_dma.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* DMA enable */ +#define DMA_Enable 0x0001 +#define DMA_Disable 0xFFFE + +/* DMA Last Buffer Sweep */ +#define DMA_Last0_Enable_Mask 0x0001 +#define DMA_Last0_Disable_Mask 0xFFFE +#define DMA_Last1_Enable_Mask 0x0002 +#define DMA_Last1_Disable_Mask 0xFFFD +#define DMA_Last2_Enable_Mask 0x0004 +#define DMA_Last2_Disable_Mask 0xFFFB +#define DMA_Last3_Enable_Mask 0x0008 +#define DMA_Last3_Disable_Mask 0xFFF7 + +/* DMA Masks */ +#define DMA_Stream0_MASK_Mask 0xFFEE +#define DMA_Stream0_CLR_Mask 0x0011 +#define DMA_Stream0_LAST_Mask 0xFFFE + +#define DMA_Stream1_MASK_Mask 0xFFDD +#define DMA_Stream1_CLR_Mask 0x0022 +#define DMA_Stream1_LAST_Mask 0xFFFD + +#define DMA_Stream2_MASK_Mask 0xFFBB +#define DMA_Stream2_CLR_Mask 0x0044 +#define DMA_Stream2_LAST_Mask 0xFFFB + +#define DMA_Stream3_MASK_Mask 0xFF77 +#define DMA_Stream3_CLR_Mask 0x0088 +#define DMA_Stream3_LAST_Mask 0xFFF7 + +#define DMA_SRCSize_Mask 0xFFE7 +#define DMA_SRCBurst_Mask 0xFF9F +#define DMA_DSTSize_Mask 0xFE7F + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : DMA_DeInit +* Description : Deinitializes the DMA streamx registers to their default reset +* values. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx) +{ + /* Reset streamx source base address register */ + DMA_Streamx->SOURCEL = 0; + DMA_Streamx->SOURCEH = 0; + + /* Reset streamx destination base address register */ + DMA_Streamx->DESTL = 0; + DMA_Streamx->DESTH = 0; + + /* Reset streamx maximum count register */ + DMA_Streamx->MAX = 0; + /* Reset streamx control register */ + DMA_Streamx->CTRL = 0; + /* Reset streamx last used buffer location register */ + DMA_Streamx->LUBUFF = 0; + + switch(*(u32*)&DMA_Streamx) + { + case DMA_Stream0_BASE: + /* Reset interrupt mask, clear and flag bits for stream0 */ + DMA->MASK &= DMA_Stream0_MASK_Mask; + DMA->CLR |= DMA_Stream0_CLR_Mask; + DMA->LAST &= DMA_Stream0_LAST_Mask; + break; + + case DMA_Stream1_BASE: + /* Reset interrupt mask, clear and flag bits for stream1 */ + DMA->MASK &= DMA_Stream1_MASK_Mask; + DMA->CLR |= DMA_Stream1_CLR_Mask; + DMA->LAST &= DMA_Stream1_LAST_Mask; + break; + + case DMA_Stream2_BASE: + /* Reset interrupt mask, clear and flag bits for stream2 */ + DMA->MASK &= DMA_Stream2_MASK_Mask; + DMA->CLR |= DMA_Stream2_CLR_Mask; + DMA->LAST &= DMA_Stream2_LAST_Mask; + break; + + case DMA_Stream3_BASE: + /* Reset interrupt mask, clear and flag bits for stream3 */ + DMA->MASK &= DMA_Stream3_MASK_Mask; + DMA->CLR |= DMA_Stream3_CLR_Mask; + DMA->LAST &= DMA_Stream3_LAST_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_Init +* Description : Initializes the DMAx stream according to the specified +* parameters in the DMA_InitStruct. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA stream. +* Output : None +* Return : None +******************************************************************************/ +void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct) +{ + /* set the buffer Size */ + DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ; + + /* Configure the incrementation of the current source Register */ + if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR) + { + /* Increment current source register */ + DMA_Streamx->CTRL |= DMA_SRC_INCR; + } + else + { + /* Current source register unchanged */ + DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR; + } + + /* Configure the incrementation of the current destination Register */ + if(DMA_InitStruct->DMA_DST == DMA_DST_INCR) + { + /* Increment current source register */ + DMA_Streamx->CTRL |= DMA_DST_INCR; + } + else + { + /* Current source register unchanged */ + DMA_Streamx->CTRL &= DMA_DST_NOT_INCR; + } + + /* Clear source to DMA data width SOSIZE[1:0] bits */ + DMA_Streamx->CTRL &= DMA_SRCSize_Mask; + /* Set the source to DMA data width */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize; + + /* Clear the DMA peripheral burst size SOBURST[1:0] bits */ + DMA_Streamx->CTRL &= DMA_SRCBurst_Mask; + /* Set the DMA peripheral burst size */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst; + + /* Clear destination to DMA dat width DESIZE[1:0] bits */ + DMA_Streamx->CTRL &= DMA_DSTSize_Mask; + /* Set the destination to DMA data width */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize; + + /* Configure the circular mode */ + if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular) + { + /* Set circular mode */ + DMA_Streamx->CTRL |= DMA_Mode_Circular; + } + else + { + /* Set normal mode */ + DMA_Streamx->CTRL &= DMA_Mode_Normal; + } + + /* Configure the direction transfer */ + if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST) + { + /* Set peripheral as destination */ + DMA_Streamx->CTRL |= DMA_DIR_PeriphDST; + } + else + { + /* Set peripheral as source */ + DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC; + } + + /* Configure the memory to memory transfer only for stream3 */ + if(DMA_Streamx == DMA_Stream3) + { + if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable) + { + /* Enable memory to memory transfer for stream3 */ + DMA_Streamx->CTRL |= DMA_M2M_Enable; + } + else + { + /* Disable memory to memory transfer for stream3 */ + DMA_Streamx->CTRL &= DMA_M2M_Disable; + } + } + + /* Configure the source base address */ + DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr; + DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16; + + /* Configure the destination base address */ + DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr; + DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16; +} + +/******************************************************************************* +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its default value. +* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* initialize the DMA_SRCBaseAddr member */ + DMA_InitStruct->DMA_SRCBaseAddr = 0; + + /* Initialize the DMA_DSTBaseAddr member */ + DMA_InitStruct ->DMA_DSTBaseAddr = 0; + + /* Initialize the DMA_SRC member */ + DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR; + + /* Initialize the DMA_DST member */ + DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR; + + /* Initialize the DMA_SRCSize member */ + DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte; + + /* Initialize the DMA_SRCBurst member */ + DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data; + + /* Initialize the DMA_DSTSize member */ + DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC; +} + +/******************************************************************************* +* Function Name : DMA_Cmd +* Description : Enables or disables the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - NewState: new state of the DMAx stream. This parameter can +* be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected DMA streamx */ + DMA_Streamx->CTRL |= DMA_Enable; + } + else + { + /* Disable the selected DMA streamx */ + DMA_Streamx->CTRL &= DMA_Disable; + } +} + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the specified DMA interrupts. +* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt mask +* - DMA_IT_SI1: Stream1 transfer end interrupt mask +* - DMA_IT_SI2: Stream2 transfer end interrupt mask +* - DMA_IT_SI3: Stream3 transfer end interrupt mask +* - DMA_IT_SE0: Stream0 transfer error interrupt mask +* - DMA_IT_SE1: Stream1 transfer error interrupt mask +* - DMA_IT_SE2: Stream2 transfer error interrupt mask +* - DMA_IT_SE3: Stream3 transfer error interrupt mask +* - DMA_IT_ALL: ALL DMA interrupts mask +* - NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected DMA interrupts */ + DMA->MASK |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA->MASK &= ~DMA_IT; + } +} + +/******************************************************************************* +* Function Name : DMA_GetCurrDSTAddr +* Description : Returns the current value of the destination address pointer +* related to the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The current value of the destination address pointer related +* to the specified DMA stream. +*******************************************************************************/ +u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx) +{ + u32 Tmp = 0; + + /* Get high current destination address */ + Tmp = (DMA_Streamx->DECURRH)<<16; + /* Get low current destination address */ + Tmp |= DMA_Streamx->DECURRL; + + /* Return the current destination address value for streamx */ + return Tmp; +} + +/******************************************************************************* +* Function Name : DMA_GetCurrSRCAddr +* Description : Returns the current value of the source address pointer +* related to the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The current value of the source address pointer related to +* the specified DMA stream. +*******************************************************************************/ +u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx) +{ + u32 Tmp = 0; + + /* Get high current source address */ + Tmp = (DMA_Streamx->SOCURRH)<<16; + /* Get slow current source address */ + Tmp |= DMA_Streamx->SOCURRL; + + /* Return the current source address value for streamx */ + return Tmp; +} + +/******************************************************************************* +* Function Name : DMA_GetTerminalCounter +* Description : Returns the number of data units remaining in the current +* DMA stream transfer. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The number of data units remaining in the current DMA stream +* transfer. +*******************************************************************************/ +u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx) +{ + /* Return the terminal counter value for streamx */ + return(DMA_Streamx->TCNT); +} + +/******************************************************************************* +* Function Name : DMA_LastBufferSweepConfig +* Description : Activates or disactivates the last buffer sweep mode for the +* DMA streamx configured in circular buffer mode. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - NewState: new state of the Last buffer sweep DMA_Streamx. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) +{ + switch(*(u32*)&DMA_Streamx) + { + case DMA_Stream0_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream0 */ + DMA->LAST |= DMA_Last0_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream0 */ + DMA->LAST &= DMA_Last0_Disable_Mask; + } + break; + + case DMA_Stream1_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream1 */ + DMA->LAST |= DMA_Last1_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream1 */ + DMA->LAST &= DMA_Last1_Disable_Mask; + } + break; + + case DMA_Stream2_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream2 */ + DMA->LAST |= DMA_Last2_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream2 */ + DMA->LAST &= DMA_Last2_Disable_Mask; + } + break; + + case DMA_Stream3_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream3 */ + DMA->LAST |= DMA_Last3_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream3 */ + DMA->LAST &= DMA_Last3_Disable_Mask; + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_LastBufferAddrConfig +* Description : Configures the circular buffer position where the last data +* to be used by the specified DMA stream is located. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - DMA_LastBufferAddr: specifies the circular buffer position +* where the last data to be used by the specified DMA stream +* is located. +* This member must be a number between 0 and the stream BufferSize-1. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr) +{ + /* Set the streamx last data circular buffer location */ + DMA_Streamx->LUBUFF = DMA_LastBufferAddr; +} + +/******************************************************************************* +* Function Name : DMA_GetFlagStatus +* Description : Checks whether the specified DMA flag is set or not. +* Input : - DMA_FLAG: specifies the flag to check. This parameter can +* be one of the following values: +* - DMA_FLAG_SI0: Stream0 transfer end flag. +* - DMA_FLAG_SI1: Stream1 transfer end flag. +* - DMA_FLAG_SI2: Stream2 transfer end flag. +* - DMA_FLAG_SI3: Stream3 transfer end flag. +* - DMA_FLAG_SE0: Stream0 transfer error flag. +* - DMA_FLAG_SE1: Stream1 transfer error flag. +* - DMA_FLAG_SE2: Stream2 transfer error flag. +* - DMA_FLAG_SE3: Stream3 transfer error flag. +* - DMA_FLAG_ACT0: Stream0 status. +* - DMA_FLAG_ACT1: Stream1 status. +* - DMA_FLAG_ACT2: Stream2 status. +* - DMA_FLAG_ACT3: Stream3 status. +* Output : None +* Return : The new state of DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG) +{ + /* Check the status of the specified DMA flag */ + if((DMA->STATUS & DMA_FLAG) != RESET) + { + /* Return SET if DMA_FLAG is set */ + return SET; + } + else + { + /* Return RESET if DMA_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : DMA_ClearFlag +* Description : Clears the DMA’s pending flags. +* Input : - DMA_FLAG: specifies the flag to clear. This parameter can +* be any combination of the following values: +* - DMA_FLAG_SI0: Stream0 transfer end flag. +* - DMA_FLAG_SI1: Stream1 transfer end flag. +* - DMA_FLAG_SI2: Stream2 transfer end flag. +* - DMA_FLAG_SI3: Stream3 transfer end flag. +* - DMA_FLAG_SE0: Stream0 transfer error flag. +* - DMA_FLAG_SE1: Stream1 transfer error flag. +* - DMA_FLAG_SE2: Stream2 transfer error flag. +* - DMA_FLAG_SE3: Stream3 transfer error flag. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearFlag(u16 DMA_FLAG) +{ + /* Clear the selected DMA flags */ + DMA->CLR = DMA_FLAG ; +} + +/******************************************************************************* +* Function Name : DMA_GetITStatus +* Description : Checks whether the specified DMA interrupt has occured or not. +* Input : - DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt +* - DMA_IT_SI1: Stream1 transfer end interrupt +* - DMA_IT_SI2: Stream2 transfer end interrupt +* - DMA_IT_SI3: Stream3 transfer end interrupt +* - DMA_IT_SE0: Stream0 transfer error interrupt +* - DMA_IT_SE1: Stream1 transfer error interrupt +* - DMA_IT_SE2: Stream2 transfer error interrupt +* - DMA_IT_SE3: Stream3 transfer error interrupt +* Output : None +* Return : The new state of DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus DMA_GetITStatus(u16 DMA_IT) +{ + /* Check the status of the specified DMA interrupt */ + if((DMA->STATUS & DMA_IT) != RESET) + { + /* Return SET if the DMA interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if the DMA interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : DMA_ClearITPendingBit +* Description : Clears the DMA’s interrupt pending bits. +* Input : - DMA_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt. +* - DMA_IT_SI1: Stream1 transfer end interrupt. +* - DMA_IT_SI2: Stream2 transfer end interrupt. +* - DMA_IT_SI3: Stream3 transfer end interrupt. +* - DMA_IT_SE0: Stream0 transfer error interrupt. +* - DMA_IT_SE1: Stream1 transfer error interrupt. +* - DMA_IT_SE2: Stream2 transfer error interrupt. +* - DMA_IT_SE3: Stream3 transfer error interrupt. +* - DMA_IT_ALL: All DMA interrupts. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearITPendingBit(u16 DMA_IT) +{ + /* Clear the selected DMA interrupts pending bits */ + DMA->CLR = DMA_IT ; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c new file mode 100644 index 0000000000..ca9ead80f6 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c @@ -0,0 +1,258 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_eic.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the EIC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_eic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EIC_IRQEnable_Mask 0x00000001 +#define EIC_IRQDisable_Mask 0xFFFFFFFE + +#define EIC_FIQEnable_Mask 0x00000002 +#define EIC_FIQDisable_Mask 0xFFFFFFFD + +#define EIC_SIPL_Mask 0x0000000F +#define EIC_SIPL_Reset_Mask 0xFFFFFFF0 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EIC_DeInit +* Description : Deinitializes the EIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EIC_DeInit(void) +{ + EIC->ICR = 0x00; + EIC->CIPR = 0x00; + EIC->FIR = 0x0C; + EIC->IER = 0x00; + EIC->IPR = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : EIC_IRQInit +* Description : Configures the IRQ channels according to the specified +* parameters in the EIC_IRQInitStruct. +* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) +{ + u32 Tmp = 0; + + if(EIC_IRQInitStruct->EIC_IRQChannelCmd == ENABLE) + { + /* Enable the selected IRQ channel */ + EIC->IER |= 1 << EIC_IRQInitStruct->EIC_IRQChannel; + + /* Configure the selected IRQ channel priority ***************************/ + /* Clear SIPL[3:0] bits */ + EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] &= EIC_SIPL_Reset_Mask; + + /* Configure SIPL[3:0] bits according to EIC_IRQChannelPriority parameter */ + Tmp = EIC_IRQInitStruct->EIC_IRQChannelPriority & EIC_SIPL_Mask; + EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] |= Tmp; + } + else + { + /* Disable the select IRQ channel */ + EIC->IER &=~ (1 << EIC_IRQInitStruct->EIC_IRQChannel); + } +} + +/******************************************************************************* +* Function Name : EIC_FIQInit +* Description : Configures the FIQ channels according to the specified +* parameters in the EIC_FIQInitStruct. +* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) +{ + if(EIC_FIQInitStruct->EIC_FIQChannelCmd == ENABLE) + { + /* Enable the selected FIQ channel */ + EIC->FIER |= EIC_FIQInitStruct->EIC_FIQChannel ; + } + else + { + /* Disable the selected FIQ channel */ + EIC->FIER &= ~EIC_FIQInitStruct->EIC_FIQChannel; + } +} + +/******************************************************************************* +* Function Name : EIC_IRQStructInit +* Description : Fills each EIC_IRQInitStruct member with its default value. +* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) +{ + EIC_IRQInitStruct->EIC_IRQChannel = 0x1F; + EIC_IRQInitStruct->EIC_IRQChannelPriority = 0; + EIC_IRQInitStruct->EIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EIC_FIQStructInit +* Description : Fills each EIC_FIQInitStruct member with its default value. +* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) +{ + EIC_FIQInitStruct->EIC_FIQChannel = 0x03; + EIC_FIQInitStruct->EIC_FIQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EIC_IRQCmd +* Description : Enables or disables EIC IRQ output request to CPU. +* Input : NewState: new state of the EIC IRQ output request to CPU. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable EIC IRQ output request to CPU */ + EIC->ICR |= EIC_IRQEnable_Mask; + } + else + { + /* Disable EIC IRQ output request to CPU */ + EIC->ICR &= EIC_IRQDisable_Mask; + } +} + +/******************************************************************************* +* Function Name : EIC_FIQCmd +* Description : Enables or disables EIC FIQ output request to CPU. +* Input : NewState: new state of the EIC FIQ output request to CPU. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable EIC FIQ output request to CPU */ + EIC->ICR |= EIC_FIQEnable_Mask; + } + else + { + /* Disable EIC FIQ output request to CPU */ + EIC->ICR &= EIC_FIQDisable_Mask; + } +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentIRQChannel +* Description : Returns the current served IRQ channel identifier. +* Input : None +* Output : None +* Return : The current served IRQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentIRQChannel(void) +{ + /* Read and return the CIC[4:0] bits of CICR register */ + return ((u8) (EIC->CICR)); +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentIRQChannelPriority +* Description : Returns the priority level of the current served IRQ channel. +* Input : None +* Output : None +* Return : The priority level of the current served IRQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentIRQChannelPriority(void) +{ + /* Read and return the CIP[3:0] bits of CIPR register */ + return ((u8) (EIC->CIPR)); +} + +/******************************************************************************* +* Function Name : EIC_CurrentIRQPriorityConfig +* Description : Changes the priority of the current served IRQ channel. +* The new priority value must be higher, or equal, than the +* priority value associated to the interrupt channel currently +* serviced. +* Input : NewPriority: new priority value of the IRQ interrupt routine +* currently serviced. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_CurrentIRQPriorityConfig(u8 NewPriority) +{ + /* Disable EIC IRQ output request to CPU */ + EIC->ICR &= EIC_IRQDisable_Mask; + + /* Change the current priority */ + EIC->CIPR = NewPriority; + + /* Enable EIC IRQ output request to CPU */ + EIC->ICR |= EIC_IRQEnable_Mask; +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentFIQChannel +* Description : Returns the current served FIQ channel identifier. +* Input : None +* Output : None +* Return : The current served FIQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentFIQChannel(void) +{ + /* Read and return the FIP[1:0] bits of FIPR register */ + return ((u8) (EIC->FIPR)); +} + +/******************************************************************************* +* Function Name : EIC_ClearFIQPendingBit +* Description : Clears the pending bit of the selected FIQ Channel. +* Input : EIC_FIQChannel: specifies the FIQ channel to clear its +* pending bit. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel) +{ + /* Clear the correspondent FIQ pending bit */ + EIC->FIPR = EIC_FIQChannel ; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c new file mode 100644 index 0000000000..997cb24f20 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c @@ -0,0 +1,179 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_extit.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the EXTIT software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_extit.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EXTIT_DeInit +* Description : Deinitializes the EXTIT peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_DeInit(void) +{ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,DISABLE); +} + +/******************************************************************************* +* Function Name : EXTIT_Init +* Description : Initializes the EXTIT peripheral according to the specified +* parameters in the EXTIT_InitStruct . +* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure +* that contains the configuration information for the EXTIT +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct) +{ + if(EXTIT_InitStruct->EXTIT_ITLineCmd == ENABLE) + { + /* Enable the selected external interrupts */ + EXTIT->MR |= EXTIT_InitStruct->EXTIT_ITLine; + + /* Select the trigger for the selected external interrupts */ + if(EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Falling) + { + /* Falling edge */ + EXTIT->TSR &= ~EXTIT_InitStruct->EXTIT_ITLine; + } + else if (EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Rising) + { + /* Rising edge */ + EXTIT->TSR |= EXTIT_InitStruct->EXTIT_ITLine; + } + } + else if(EXTIT_InitStruct->EXTIT_ITLineCmd == DISABLE) + { + /* Disable the selected external interrupts */ + EXTIT->MR &= ~EXTIT_InitStruct->EXTIT_ITLine; + } +} + +/******************************************************************************* +* Function Name : EXTIT_StructInit +* Description : Fills each EXTIT_InitStruct member with its reset value. +* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct) +{ + EXTIT_InitStruct->EXTIT_ITLine = EXTIT_ITLineNone; + EXTIT_InitStruct->EXTIT_ITTrigger = EXTIT_ITTrigger_Falling; + EXTIT_InitStruct->EXTIT_ITLineCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EXTIT_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to be enabled or +* disabled. This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine) +{ + EXTIT->SWIR |= EXTIT_ITLine; +} + +/******************************************************************************* +* Function Name : EXTIT_GetFlagStatus +* Description : Checks whether the specified EXTIT line flag is set or not. +* Input : - EXTIT_ITLine: specifies the EXTIT lines flag to check. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : The new state of EXTIT_ITLine (SET or RESET). +*******************************************************************************/ +FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine) +{ + if((EXTIT->PR & EXTIT_ITLine) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : EXTIT_ClearFlag +* Description : Clears the EXTIT’s line pending flags. +* Input : - EXTIT_ITLine: specifies the EXTIT lines flags to clear. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_ClearFlag(u16 EXTIT_ITLine) +{ + EXTIT->PR = EXTIT_ITLine; +} + +/******************************************************************************* +* Function Name : EXTIT_GetITStatus +* Description : Checks whether the specified EXTIT line is asserted or not. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to check. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : The new state of EXTIT_ITLine (SET or RESET). +*******************************************************************************/ +ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine) +{ + if(((EXTIT->PR & EXTIT_ITLine) != RESET)&& ((EXTIT->MR & EXTIT_ITLine) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : EXTIT_ClearITPendingBit +* Description : Clears the EXTIT’s line pending bits. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to clear. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine) +{ + EXTIT->PR = EXTIT_ITLine; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c new file mode 100644 index 0000000000..dcc7d79209 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c @@ -0,0 +1,320 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_gpio.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_gpio.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define GPIO_Remap_Mask 0x1F /* GPIO remapping mask */ +#define GPIO_Pin_Mask 0x000FFFFF /* GPIO1 and GPIO2 all pins mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* The I/O remapping register 0 and 1 are not reset by this function. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Reset the GPIOx registers values */ + GPIOx->PC0 = 0xFFFFFFFF; + GPIOx->PC1 = 0x0; + GPIOx->PC2 = 0x0; + GPIOx->PM = 0x0; +} + +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. This function will not +* change the configuration for a pin if the corresponding mask +* bit is set, except pins configured as input pull-up or pull-down. +* These pins are automatically masked after each configuration. +* Input :- GPIOx: where x can be (0..2) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* GPIOx Mode and Pins Set */ + if((GPIOx != GPIO0) && (GPIO_InitStruct->GPIO_Pin == GPIO_Pin_All)) + { + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_Mask; + } + + switch(GPIO_InitStruct->GPIO_Mode) + { + case GPIO_Mode_AIN: + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IN_FLOATING: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IPD: + GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PD &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IPU: + GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_Out_OD: + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_Out_PP: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_AF_OD: + GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_AF_PP: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + default : + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Fills each GPIO_InitStruct member with its default value. +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u32 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return GPIOx->PD; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified data port bit. +* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin) +{ + if ((GPIOx->PD & GPIO_Pin) != Bit_RESET) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes data to the specified GPIO data port. +* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - PortVal: specifies the value to be written to the data port +* register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal) +{ + GPIOx->PD = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* - BitVal: specifies the value to be written to the selected bit. +* This parameter must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->PD |= GPIO_Pin; + } + else + { + GPIOx->PD &= ~GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_PinMaskConfig +* Description : Enables or disables write protection to the selected bits in +* the I/O port registers (PxC2, PxC1, PxC0 and PxD). +* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be protected. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + GPIOx->PM |= GPIO_Pin; + } + else + { + GPIOx->PM &= ~GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetPortMask +* Description : Gets the GPIOx port mask value. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : GPIO port mask value. +*******************************************************************************/ +u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx) +{ + return GPIOx->PM; +} + +/******************************************************************************* +* Function Name : GPIO_PinRemapConfig +* Description : Changes the mapping of the specified pin. +* Input :- GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* - GPIO_Remap_SMI_CS3_EN: Enable SMI CS3 +* - GPIO_Remap_SMI_CS2_EN: Enable SMI CS2 +* - GPIO_Remap_SMI_CS1_EN: Enable SMI CS1 +* - GPIO_Remap_SMI_EN: Enable SMI Alternate Functions: +* SMI_CS0, SMI_CK, SMI_DIN and SMI_DOUT +* - GPIO_Remap_DBGOFF: JTAG Disable +* - GPIO_Remap_UART1: UART1 Alternate Function mapping +* - GPIO_Remap_UART2: UART2 Alternate Function mapping +* - GPIO_Remap_SSP1: SSP1 Alternate Function mapping +* - GPIO_Remap_TIM2: TIM2 Alternate Function mapping +* - GPIO_Remap_TIM0: TIM0 Alternate Function mapping +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState) +{ + u32 GPIOReg = 0; + u32 PinPos = 0; + + /* Get the GPIO register index */ + GPIOReg = GPIO_Remap >> 5; + + /* Get the pin position */ + PinPos = GPIO_Remap & GPIO_Remap_Mask; + + if(GPIOReg == 1) /* The pin to remap is in REMAP0R register */ + { + if(NewState == ENABLE) + { + GPIOREMAP->REMAP0R |= (1 << PinPos); + } + else + { + GPIOREMAP->REMAP0R &= ~(1 << PinPos); + } + } + else if(GPIOReg == 2) /* The pin to remap is in REMAP1R register */ + { + if(NewState == ENABLE) + { + GPIOREMAP->REMAP1R |= (1 << PinPos); + } + else + { + GPIOREMAP->REMAP1R &= ~(1 << PinPos); + } + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c new file mode 100644 index 0000000000..e5e5d001c6 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c @@ -0,0 +1,568 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_i2c.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the I2C software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_i2c.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* I2C IT enable */ +#define I2C_IT_Enable 0x01 +#define I2C_IT_Disable 0xFE + +/* I2C Peripheral Enable/Disable */ +#define I2C_PE_Set 0x20 +#define I2C_PE_Reset 0xDF + +/* I2C START Enable/Disable */ +#define I2C_Start_Enable 0x08 +#define I2C_Start_Disable 0xF7 + +/* I2C STOP Enable/Disable */ +#define I2C_Stop_Enable 0x02 +#define I2C_Stop_Disable 0xFD + +/* Address direction bit */ +#define I2C_ADD0_Set 0x01 +#define I2C_ADD0_Reset 0xFE + +/* I2C Masks */ +#define I2C_Frequency_Mask 0x1F +#define I2C_AddressHigh_Mask 0xF9 +#define I2C_OwnAddress_Mask 0x0300 +#define I2C_StandardMode_Mask 0x7f +#define I2C_FastMode_Mask 0x80 +#define I2C_Event_Mask 0x3FFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2C peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(void) +{ + /* Reset the I2C registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,DISABLE); +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2C peripheral according to the specified +* parameters in the I2C_Initstruct. +* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified I2C +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Init(I2C_InitTypeDef* I2C_InitStruct) +{ + u8 ITEState = 0; + u16 Result = 0x0F; + u32 APBClock = 8000000; + MRCC_ClocksTypeDef MRCC_ClocksStatus; + + /* Get APBClock frequency value */ + MRCC_GetClocksStatus(&MRCC_ClocksStatus); + APBClock = MRCC_ClocksStatus.PCLK_Frequency; + /* Save ITE bit state */ + ITEState = I2C->CR & 0xFE; + /* Disable I2C peripheral to set FR[2:0] bits */ + I2C_Cmd(DISABLE); + /* Clear frequency FR[2:0] bits */ + I2C->OAR2 &= I2C_Frequency_Mask; + + /* Set frequency bits depending on APBClock value */ + if (APBClock < 10000000) + I2C->OAR2 &= 0x1F; + else if (APBClock < 16670000) + I2C->OAR2 |= 0x20; + else if (APBClock < 26670000) + I2C->OAR2 |= 0x40; + else if (APBClock < 40000000) + I2C->OAR2 |= 0x60; + else if (APBClock < 53330000) + I2C->OAR2 |= 0x80; + else if (APBClock < 66000000) + I2C->OAR2 |= 0xA0; + else if (APBClock < 80000000) + I2C->OAR2 |= 0xC0; + else if (APBClock < 100000000) + I2C->OAR2 |= 0xE0; + I2C_Cmd(ENABLE); + + /* Restore the ITE bit state */ + I2C->CR |= ITEState; + + /* Configure general call */ + if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) + { + /* Enable general call */ + I2C->CR |= I2C_GeneralCall_Enable; + } + else + { + /* Disable general call */ + I2C->CR &= I2C_GeneralCall_Disable; + } + + /* Configure acknowledgement */ + if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) + { + /* Enable acknowledgement */ + I2C->CR |= I2C_Ack_Enable; + } + else + { + /* Disable acknowledgement */ + I2C->CR &= I2C_Ack_Disable; + } + + /* Configure LSB own address */ + I2C->OAR1 = I2C_InitStruct->I2C_OwnAddress; + /* Clear MSB own address ADD[9:8] bits */ + I2C->OAR2 &= I2C_AddressHigh_Mask; + /* Set MSB own address value */ + I2C->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_CLKSpeed <= 100000) + { + /* Standard mode speed calculate */ + Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-7)/2; + /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ + I2C->CCR = Result & I2C_StandardMode_Mask; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) + { + /* Fast mode speed calculate */ + Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-9)/3; + /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ + I2C->CCR = Result | I2C_FastMode_Mask; + } + /* Set speed in MSB clock divider */ + I2C->ECCR = Result >>7; +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Fills each I2C_InitStruct member with its default value. +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /* Initialize the I2C_CLKSpeed member */ + I2C_InitStruct->I2C_CLKSpeed = 5000; + + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0x0; + + /* Initialize the I2C_GeneralCall member */ + I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the I2C peripheral. +* Input : - NewState: new state of the I2C peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Cmd(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ + I2C->CR |= I2C_PE_Set; + I2C->CR |= I2C_PE_Set; + } + else + { + /* Disable the I2C peripheral */ + I2C->CR &= I2C_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2C communication START condition. +* Input : - NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTART(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a START condition */ + I2C->CR |= I2C_Start_Enable; + } + else + { + /* Disable the START condition generation */ + I2C->CR &= I2C_Start_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2C communication STOP condition. +* Input : - NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a SIOP condition */ + I2C->CR |= I2C_Stop_Enable; + } + else + { + /* Disable the STOP condition generation */ + I2C->CR &= I2C_Stop_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables I2C acknowledge feature. +* Input : - NewState: new state of the I2C Acknowledgement. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the acknowledgement */ + I2C->CR |= I2C_Ack_Enable; + } + else + { + /* Disable the acknowledgement */ + I2C->CR &= I2C_Ack_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables the I2C interrupt. +* Input : - NewState: new state of the I2C interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ITConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C interrupt */ + I2C->CR |= I2C_IT_Enable; + } + else + { + /* Disable the I2C interrupt */ + I2C->CR &= I2C_IT_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Gets the last I2C event that has occurred. +* Input : None +* Output : None +* Return : The Last happened Event. +*******************************************************************************/ +u16 I2C_GetLastEvent(void) +{ + u16 Flag1 = 0, Flag2 = 0, LastEvent = 0; + + Flag1 = I2C->SR1; + Flag2 = I2C->SR2; + Flag2 = Flag2<<8; + /* Get the last event value from I2C status register */ + LastEvent = (((Flag1 | (Flag2)) & I2C_Event_Mask)); + /* Return the last event */ + return LastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input : - I2C_EVENT: specifies the event to be checked. This parameter +* can be one of the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED +* - I2C_EVENT_SLAVE_BYTE_RECEIVED +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED +* - I2C_EVENT_SLAVE_ACK_FAILURE +* - I2C_EVENT_MASTER_MODE_SELECT +* - I2C_EVENT_MASTER_MODE_SELECTED +* - I2C_EVENT_MASTER_BYTE_RECEIVED +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_ADDRESS10 +* - I2C_EVENT_SLAVE_STOP_DETECTED +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(u16 I2C_EVENT) +{ + u16 LastEvent = I2C_GetLastEvent(); + + /* Check whether the last event is equal to I2C_EVENT */ + if (LastEvent == I2C_EVENT) + { + /* Return SUCCESS when last event is equal to I2C_EVENT */ + return SUCCESS; + } + else + { + /* Return ERROR when last event is different from I2C_EVENT */ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Sends a data byte. +* Input : - Data: indicates the byte to be transmitted. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_SendData(u8 Data) +{ + /* Write in the DR register the byte to be sent */ + I2C->DR = Data; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Reads the received byte. +* Input : None +* Output : None +* Return : The received byte +*******************************************************************************/ +u8 I2C_ReceiveData(void) +{ + /* Return from the DR register the received byte */ + return I2C->DR; +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input : - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. This parameter can be one of the +* following values +* - I2C_MODE_TRANSMITTER: Transmitter mode +* - I2C_MODE_RECEIVER: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(u8 Address, u8 Direction) +{ + /* Test on the direction to define the read/write bit */ + if (Direction == I2C_MODE_RECEIVER) + { + /* Set the address bit0 for read */ + Address |= I2C_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= I2C_ADD0_Reset; + } + /* Send the address */ + I2C->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads the specified I2C register and returns its value. +* Input1 : - I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* - I2C_CR: CR register. +* - I2C_SR1: SR1 register. +* - I2C_SR2: SR2 register. +* - I2C_CCR: CCR register. +* - I2C_OAR1: OAR1 register. +* - I2C_OAR2: OAR2 register. +* - I2C_DR: DR register. +* - I2C_ECCR: ECCR register. +* Output : None +* Return : The value of the read register. +*******************************************************************************/ +u8 I2C_ReadRegister(u8 I2C_Register) +{ + /* Return the selected register value */ + return (*(u8 *)(I2C_BASE + I2C_Register)); +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input : - I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - I2C_FLAG_SB: Start bit flag (Master mode) +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Address matched flag (Slave mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag (slave mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag (slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* Output : None +* Return : The NewState of the I2C_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG) +{ + u16 Flag1 = 0, Flag2 = 0, Flag3 = 0, Tmp = 0; + + Flag1 = I2C->SR1; + Flag2 = I2C->SR2; + Flag2 = Flag2<<8; + Flag3 = I2C->CR & 0x04; + + /* Get all the I2C flags in a unique register*/ + Tmp = (((Flag1 | (Flag2)) & I2C_Event_Mask) | (Flag3<<12)); + + /* Check the status of the specified I2C flag */ + if((Tmp & I2C_FLAG) != RESET) + { + /* Return SET if I2C_FLAG is set */ + return SET; + } + else + { + /* Return RESET if I2C_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2C’s pending flags +* Input : - I2C_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* - parameter needed in the case that the flag to be cleared +* need a write in one register +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearFlag(u16 I2C_FLAG, ...) +{ + u8 Tmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); + + /* flags that need a read of the SR2 register to be cleared */ + if ((I2C_FLAG == I2C_FLAG_ADD10) || (I2C_FLAG == I2C_FLAG_EVF) || + (I2C_FLAG == I2C_FLAG_STOPF) || (I2C_FLAG == I2C_FLAG_AF) || + (I2C_FLAG == I2C_FLAG_BERR) || (I2C_FLAG == I2C_FLAG_ARLO) || + (I2C_FLAG == I2C_FLAG_ENDAD)) + { + /* Read the SR2 register */ + (void)I2C->SR2; + + /* Two flags need a second step to be cleared */ + switch (I2C_FLAG) + { + case I2C_FLAG_ADD10: + /* Send the MSB 10bit address passed as second parameter */ + I2C->DR = Tmp; + break; + case I2C_FLAG_ENDAD: + /* Write to the I2C_CR register by setting PE bit */ + I2C->CR |= I2C_PE_Set; + break; + } + } + /* flags that need a read of the SR1 register to be cleared */ + else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* Read the SR1 register */ + (void)I2C->SR1; + + /* three flags need a second step to be cleared */ + if (I2C_FLAG == I2C_FLAG_SB) + { + /* Send the address byte passed as second parameter */ + I2C->DR=Tmp; + } + else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* return the received byte in the variable passed as second parameter */ + Tmp=I2C->DR; + } + } + /* flags that need to disable the I2C interface */ + else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) + { + I2C_Cmd(DISABLE); + I2C_Cmd(ENABLE); + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c new file mode 100644 index 0000000000..16c87f0643 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c @@ -0,0 +1,178 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_lib.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT + +/* Includes ------------------------------------------------------------------*/ +#include "75x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void debug(void) +{ +/************************************* SMI ************************************/ +#ifdef _SMI + SMI = (SMI_TypeDef *) SMIR_BASE; +#endif /*_SMI */ + +/************************************* CFG ************************************/ +#ifdef _CFG + CFG = (CFG_TypeDef *) CFG_BASE; +#endif /*_CFG */ + +/************************************* MRCC ***********************************/ +#ifdef _MRCC + MRCC = (MRCC_TypeDef *) MRCC_BASE; +#endif /*_MRCC */ + +/************************************* ADC ************************************/ +#ifdef _ADC + ADC = (ADC_TypeDef *) ADC_BASE; +#endif /*_ADC */ + +/************************************* TB *************************************/ +#ifdef _TB + TB = (TB_TypeDef *) TB_BASE; +#endif /*_TB */ + +/************************************* TIM ************************************/ +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *) TIM0_BASE; +#endif /*_TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *) TIM1_BASE; +#endif /*_TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *) TIM2_BASE; +#endif /*_TIM2 */ + +/************************************* PWM ************************************/ +#ifdef _PWM + PWM = (PWM_TypeDef *) PWM_BASE; +#endif /*_PWM */ + +/************************************* WDG ************************************/ +#ifdef _WDG + WDG = (WDG_TypeDef *) WDG_BASE; +#endif /*_WDG */ + +/************************************* SSP ************************************/ +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *) SSP0_BASE; +#endif /*_SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *) SSP1_BASE; +#endif /*_SSP1 */ + +/************************************* CAN ************************************/ +#ifdef _CAN + CAN = (CAN_TypeDef *) CAN_BASE; +#endif /*_CAN */ + +/************************************* I2C ************************************/ +#ifdef _I2C + I2C = (I2C_TypeDef *) I2C_BASE; +#endif /*_I2C */ + +/************************************* UART ***********************************/ +#ifdef _UART0 + UART0 = (UART_TypeDef *) UART0_BASE; +#endif /*_UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *) UART1_BASE; +#endif /*_UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *) UART2_BASE; +#endif /*_UART2 */ + +/************************************* GPIO ***********************************/ +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *) GPIO0_BASE; +#endif /*_GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *) GPIO1_BASE; +#endif /*_GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *) GPIO2_BASE; +#endif /*_GPIO2 */ + +#ifdef _GPIOREMAP + GPIOREMAP = (GPIOREMAP_TypeDef *) GPIOREMAP_BASE; +#endif /*_GPIOREMAP */ + +/************************************* DMA ************************************/ +#ifdef _DMA + DMA = (DMA_TypeDef *) DMA_BASE; +#endif /*_DMA */ + +#ifdef _DMA_Stream0 + DMA_Stream0 = (DMA_Stream_TypeDef *) DMA_Stream0_BASE; +#endif /*_DMA_Stream0 */ + +#ifdef _DMA_Stream1 + DMA_Stream1 = (DMA_Stream_TypeDef *) DMA_Stream1_BASE; +#endif /*_DMA_Stream1 */ + +#ifdef _DMA_Stream2 + DMA_Stream2 = (DMA_Stream_TypeDef *) DMA_Stream2_BASE; +#endif /*_DMA_Stream2 */ + +#ifdef _DMA_Stream3 + DMA_Stream3 = (DMA_Stream_TypeDef *) DMA_Stream3_BASE; +#endif /*_DMA_Stream3 */ + +/************************************* RTC ************************************/ +#ifdef _RTC + RTC = (RTC_TypeDef *) RTC_BASE; +#endif /*_RTC */ + +/************************************* EXTIT **********************************/ +#ifdef _EXTIT + EXTIT = (EXTIT_TypeDef *) EXTIT_BASE; +#endif /*_EXTIT */ + +/************************************* EIC ************************************/ +#ifdef _EIC + EIC = (EIC_TypeDef *) EIC_BASE; +#endif /*_EIC */ + +} + +#endif + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c new file mode 100644 index 0000000000..fadfb73c7c --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c @@ -0,0 +1,1673 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_mrcc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the MRCC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */ + +/* MRCC_PWRCTRL mask bits */ +#define MRCC_LP_Set_Mask 0x00000001 +#define MRCC_LP_Reset_Mask 0xFFFFFFFE +#define MRCC_SWRESET_Mask 0x00000002 +#define MRCC_WFI_Mask 0x00000004 +#define MRCC_STANDBY_Mask 0x00000006 +#define MRCC_LPMC_Reset_Mask 0xFFFFFFF9 +#define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F +#define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF +#define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF +#define MRCC_CKRTCSEL_Set_Mask 0x03000000 +#define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF +#define MRCC_CKRTCOK_Mask 0x08000000 +#define MRCC_LPOSCEN_Mask 0x10000000 +#define MRCC_OSC32KEN_Mask 0x20000000 + +/* MRCC_CLKCTL mask bits */ +#define MRCC_PPRESC_Set_Mask 0x00000003 +#define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC +#define MRCC_PPRESC2_Mask 0x00000004 +#define MRCC_HPRESC_Set_Mask 0x00000018 +#define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7 +#define MRCC_MCOS_Reset_Mask 0xFFFFFF3F +#define MRCC_XTDIV2_Set_Mask 0x00008000 +#define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF +#define MRCC_OSC4MBYP_Set_Mask 0x00010000 +#define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF +#define MRCC_OSC4MOFF_Set_Mask 0x00020000 +#define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF +#define MRCC_NCKDF_Set_Mask 0x00040000 +#define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF +#define MRCC_CKOSCSEL_Set_Mask 0x00200000 +#define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF +#define MRCC_CKUSBSEL_Mask 0x00400000 +#define MRCC_CKSEL_Set_Mask 0x00800000 +#define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF +#define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000 +#define MRCC_PLLEN_Set_Mask 0x01000000 +#define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF +#define MRCC_PLL2EN_Set_Mask 0x02000000 +#define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF +#define MRCC_MX_Set_Mask 0x18000000 +#define MRCC_MX_Reset_Mask 0xE7FFFFFF +#define MRCC_LOCK_Mask 0x80000000 +#define MRCC_PLLEN_LOCK_Mask 0x81000000 + +/* Typical Value of the OSC4M in Hz */ +#define OSC4M_Value 4000000 + +/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */ +#define OSC4M_Div128_Value 31250 + +/* Typical Value of the OS32K Oscillator Frequency in Hz */ +#define OSC32K_Value 32768 + +/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */ +#define LPOSC_Value 245000 + +/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */ +#define FREEOSC_Value 5000000 + +/* Time out for OSC4M start up */ +#define OSC4MStartUp_TimeOut 0xFE + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static ErrorStatus SetCKSYS_FREEOSC(void); +static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State); +static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul); +static ErrorStatus SetCKSYS_RTC(u32 PLL_State); +static void WriteLPBit(void); +static void WriteCKOSCSELBit(void); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : MRCC_DeInit +* Description : Deinitializes the MRCC peripheral registers to their default +* reset values. +* - Depending on the system clock state, some bits in MRCC_CLKCTL +* register can’t be reset. +* - The OSC32K, LPOSC and RTC clock selection configuration +* bits in MRCC_PWRCTRL register are not cleared by this +* function. To reset those bits, use the dedicated functions +* available within this driver. +* - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not +* reset by this function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_DeInit(void) +{ + /* Try to clear NCKDF bit */ + MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) + {/* No clock detected on OSC4M */ + + /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0], + MCOP, HPRESC[1:0], PPRES[2:0] bits */ + MRCC->CLKCTL &= 0x9FB40000; + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + /* Clear CKOSCSEL bit --------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + } + } + else + {/* Clock present on OSC4M */ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + /* Reset CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Clear CKOSCSEL bit --------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + } + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + /* Set CKSEL bit */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + } + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + + /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP, + HPRESC[1:0], PPRES[2:0] bits */ + MRCC->CLKCTL &= 0x87B70000; + + /* Reset CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Reset OSC4MOFF and OSC4MBYP bits */ + MRCC->CLKCTL &= 0xFFFCFFFF; + } + + /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */ + MRCC->PWRCTRL &= 0xFBFE1FE1; + + /* Reset PCLKEN register bits */ + MRCC->PCLKEN = 0x00; + + /* Reset PSWRES register bits */ + MRCC->PSWRES = 0x00; + + /* Clear NCKDF bit */ + MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; +} + +/******************************************************************************* +* Function Name : MRCC_XTDIV2Config +* Description : Enables or disables the oscillator divider by 2. This function +* must not be used when the PLL is enabled. +* Input : - MRCC_XTDIV2: specifies the new state of the oscillator +* divider by 2. +* This parameter can be one of the following values: +* - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled +* - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_XTDIV2Config(u32 MRCC_XTDIV2) +{ + if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable) + { + MRCC->CLKCTL |= MRCC_XTDIV2_Enable; + } + else + { + MRCC->CLKCTL &= MRCC_XTDIV2_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_CKSYSConfig +* Description : Configures the system clock (CK_SYS). +* Input : - MRCC_CKSYS: specifies the clock source used as system clock. +* This parameter can be one of the following values: +* - MRCC_CKSYS_FREEOSC +* - MRCC_CKSYS_OSC4M +* - MRCC_CKSYS_OSC4MPLL +* - MRCC_CKSYS_RTC (RTC clock source must be previously +* configured using MRCC_CKRTCConfig() function) +* : - MRCC_PLL: specifies the PLL configuration. +* This parameter can be one of the following values: +* - MRCC_PLL_Disabled: PLL disabled +* - MRCC_PLL_NoChange: No change on PLL configuration +* - MRCC_PLL_Mul_12: Multiplication by 12 +* - MRCC_PLL_Mul_14: Multiplication by 14 +* - MRCC_PLL_Mul_15: Multiplication by 15 +* - MRCC_PLL_Mul_16: Multiplication by 16 +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL) +{ + ErrorStatus Status = ERROR; + + switch(MRCC_CKSYS) + { + case MRCC_CKSYS_FREEOSC: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_FREEOSC(); + } + break; + + case MRCC_CKSYS_OSC4M: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_OSC4M(MRCC_PLL); + } + break; + + case MRCC_CKSYS_OSC4MPLL: + if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) || + (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16)) + { + Status = SetCKSYS_OSC4MPLL(MRCC_PLL); + } + break; + + case MRCC_CKSYS_RTC: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_RTC(MRCC_PLL); + } + break; + + default: + Status = ERROR; + break; + } + return Status; +} + +/******************************************************************************* +* Function Name : MRCC_HCLKConfig +* Description : Configures the AHB clock (HCLK). +* Input : - MRCC_HCLK: defines the AHB clock. This clock is derived +* from the system clock(CK_SYS). +* This parameter can be one of the following values: +* - MRCC_CKSYS_Div1: AHB clock = CK_SYS +* - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2 +* - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4 +* - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_HCLKConfig(u32 MRCC_HCLK) +{ + u32 Temp = 0; + + /* Clear HPRESC[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask; + + /* Set HPRESC[1:0] bits according to MRCC_HCLK value */ + Temp |= MRCC_HCLK; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_CKTIMConfig +* Description : Configures the TIM clock (CK_TIM). +* Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived +* from the AHB clock(HCLK). +* This parameter can be one of the following values: +* - MRCC_HCLK_Div1: TIM clock = HCLK +* - MRCC_HCLK_Div2: TIM clock = HCLK/2 +* - MRCC_HCLK_Div4: TIM clock = HCLK/4 +* - MRCC_HCLK_Div8: TIM clock = HCLK/8 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_CKTIMConfig(u32 MRCC_CKTIM) +{ + u32 Temp = 0; + + /* Clear PPRESC[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask; + + /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */ + Temp |= MRCC_CKTIM; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_PCLKConfig +* Description : Configures the APB clock (PCLK). +* Input : - MRCC_PCLK: defines the APB clock. This clock is derived +* from the TIM clock(CK_TIM). +* This parameter can be one of the following values: +* - MRCC_CKTIM_Div1: APB clock = CKTIM +* - MRCC_CKTIM_Div2: APB clock = CKTIM/2 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PCLKConfig(u32 MRCC_PCLK) +{ + if(MRCC_PCLK == MRCC_CKTIM_Div2) + { + MRCC->CLKCTL |= MRCC_CKTIM_Div2; + } + else + { + MRCC->CLKCTL &= MRCC_CKTIM_Div1; + } +} + +/******************************************************************************* +* Function Name : MRCC_CKRTCConfig +* Description : Configures the RTC clock (CK_RTC). +* Input : - MRCC_CKRTC: specifies the clock source to be used as RTC +* clock. +* This parameter can be one of the following values: +* - MRCC_CKRTC_OSC4M_Div128 +* - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled +* using MRCC_OSC32KConfig() function) +* - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled +* using MRCC_LPOSCConfig() function) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC) +{ + u32 Tmp = 0; + + if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)) + { + /* CK_RTC used as CK_SYS clock source */ + return ERROR; + } + else + { + /* Clear CKRTCSEL[1:0] bits */ + Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask; + + /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */ + Tmp |= MRCC_CKRTC; + + /* Store the new value */ + MRCC->PWRCTRL = Tmp; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : MRCC_CKUSBConfig +* Description : Configures the USB clock(CK_USB). +* Input : - MRCC_CKUSB: specifies the clock source to be used as USB +* clock. +* This parameter can be one of the following values: +* - MRCC_CKUSB_Internal(CK_PLL2 enabled) +* - MRCC_CKUSB_External(CK_PLL2 disabled) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB) +{ + if(MRCC_CKUSB == MRCC_CKUSB_External) + { + /* Disable CK_PLL2 */ + MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask; + + /* External USB clock selected */ + MRCC->CLKCTL |= MRCC_CKUSB_External; + } + else + { + if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET) + { /* PLL enabled and locked */ + + /* Enable CK_PLL2 */ + MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask; + + /* Internal USB clock selected */ + MRCC->CLKCTL &= MRCC_CKUSB_Internal; + } + else + { + /* PLL not enabled */ + return ERROR; + } + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : MRCC_ITConfig +* Description : Enables or disables the specified MRCC interrupts. +* Input : - MRCC_IT: specifies the MRCC interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* - NewState: new state of the MRCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->CLKCTL |= MRCC_IT; + } + else + { + MRCC->CLKCTL &= ~MRCC_IT; + } +} + +/******************************************************************************* +* Function Name : MRCC_PeripheralClockConfig +* Description : Enables or disables the specified peripheral clock. +* Input : - MRCC_Peripheral: specifies the peripheral to gates its +* clock. More than one peripheral can be selected using +* the “|” operator. +* - NewState: new state of the specified peripheral clock. +* This parameter can be one of the following values: +* - ENABLE: the selected peripheral clock is enabled +* - DISABLE: the selected peripheral clock is disabled +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->PCLKEN |= MRCC_Peripheral; + } + else + { + MRCC->PCLKEN &= ~MRCC_Peripheral; + } +} + +/******************************************************************************* +* Function Name : MRCC_PeripheralSWResetConfig +* Description : Forces or releases peripheral software reset. +* Input : - MRCC_Peripheral: specifies the peripheral to reset. More +* than one peripheral can be selected using the “|” operator. +* - NewState: new state of the specified peripheral software +* reset. This parameter can be one of the following values: +* - ENABLE: the selected peripheral is kept under reset +* - DISABLE: the selected peripheral exits from reset +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->PSWRES |= MRCC_Peripheral; + } + else + { + MRCC->PSWRES &= ~MRCC_Peripheral; + } +} + +/******************************************************************************* +* Function Name : MRCC_GetClocksStatus +* Description : Returns the status and frequencies of different on chip clocks. +* Don’t use this function when CK_SYS is clocked by an external +* clock source (OSC4M bypassed). +* Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure +* which will hold the clocks information. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus) +{ + u32 PLLMul = 0; + u32 Temp = 0; + u32 Presc = 0; + + /* Get the Status of PLL */ + if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET) + { + MRCC_ClocksStatus->PLL_Status = OFF; + } + else + { + MRCC_ClocksStatus->PLL_Status = ON; + } + + /* Get the Status of OSC4M */ + if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET) + { + MRCC_ClocksStatus->OSC4M_Status = ON; + } + else + { + MRCC_ClocksStatus->OSC4M_Status = OFF; + } + + /* Get the Status of LPOSC */ + if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET) + { + MRCC_ClocksStatus->LPOSC_Status = OFF; + } + else + { + MRCC_ClocksStatus->LPOSC_Status = ON; + } + + /* Get the Status of OSC32K */ + if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET) + { + MRCC_ClocksStatus->OSC32K_Status = OFF; + } + else + { + MRCC_ClocksStatus->OSC32K_Status = ON; + } + +/* Get CKU_SB source ---------------------------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET) + { + MRCC_ClocksStatus->CKUSB_Source = External; + } + else + { + if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET) + { + MRCC_ClocksStatus->CKUSB_Source = Internal; + + } + else + { + MRCC_ClocksStatus->CKUSB_Source = Disabled; + } + } + +/* Get CK_RTC source ---------------------------------------------------------*/ + Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask; + Temp = Temp >> 24; + + switch(Temp) + { + case 0x00: + MRCC_ClocksStatus->CKRTC_Source = Disabled; + break; + + case 0x01: + MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128; + break; + + case 0x02: + MRCC_ClocksStatus->CKRTC_Source = OSC32K; + break; + + case 0x03: + MRCC_ClocksStatus->CKRTC_Source = LPOSC; + break; + + default: + MRCC_ClocksStatus->CKRTC_Source = Disabled; + break; + } + +/* Get CK_SYS source ---------------------------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + {/* CK_OSC used as CK_SYS clock source */ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { /* CK_RTC used as CK_OSC clock source */ + MRCC_ClocksStatus->CKSYS_Source = CKRTC; + + if(MRCC_ClocksStatus->CKRTC_Source == OSC32K) + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value; + } + else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC) + + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value; + } + else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128) + + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value; + } + } + else + { /* OSC4M used as CK_OSC clock source */ + MRCC_ClocksStatus->CKSYS_Source = OSC4M; + + if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET) + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1; + } + else + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator; + } + } + } + else + {/* CK_PLL1 used as CK_SYS clock */ + + if(MRCC_ClocksStatus->PLL_Status == OFF) + { /* FREEOSC used as CK_PLL1 clock source */ + MRCC_ClocksStatus->CKSYS_Source = FREEOSC; + + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value; + } + else + { /* OSC4M followed by PLL used as CK_PLL1 clock source */ + MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL; + + /* Get PLL factor ------------------------------------------------------*/ + Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask; + Temp = Temp >> 27; + + switch(Temp) + { + case 0x00: + PLLMul = 16; + break; + + case 0x01: + PLLMul = 15; + break; + + case 0x02: + PLLMul = 14; + break; + + case 0x03: + PLLMul = 12; + break; + + default: + PLLMul = 16; + break; + } + + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul; + } + } + +/* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/ + /* Get HCLK prescaler */ + Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask; + Presc = Presc >> 3; + /* HCLK clock frequency */ + MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc; + + /* Get CK_TIM prescaler */ + Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask; + /* CK_TIM clock frequency */ + MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc; + + /* Get PCLK prescaler */ + Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask; + Presc = Presc >> 2; + /* PCLK clock frequency */ + MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc; +} + +/******************************************************************************* +* Function Name : MRCC_LPMC_DBGonfig +* Description : Enables or disables the Low Power Debug Mode. +* Input : - MRCC_LPDM: specifies the LPDM new state value. +* This parameter can be one of the following values: +* - MRCC_LPDM_Disable +* - MRCC_LPDM_Enable +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM) +{ + if(MRCC_LPDM == MRCC_LPDM_Enable) + { + MRCC->PWRCTRL |= MRCC_LPDM_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_LPDM_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_EnterWFIMode +* Description : Enters WFI mode. +* If the Flash is used in Burst mode, it must be kept enabled +* in WFI mode(use MRCC_WFIParam_FLASHOn as parameter) +* Input : - MRCC_WFIParam: specifies the WFI mode control parameters. +* This parameter can be one of the following values: +* - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI) +* - MRCC_WFIParam_FLASHOn(DMA allowed during WFI) +* - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI) +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterWFIMode(u32 MRCC_WFIParam) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select WFI mode */ + MRCC->PWRCTRL |= MRCC_WFI_Mask; + +/* Low Power mode control parameters configuration ---------------------------*/ + /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */ + MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask; + + if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown) + { + /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */ + MRCC->PWRCTRL |= MRCC_WFIParam; + } + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_EnterSTOPMode +* Description : Enters STOP mode. +* Input : - MRCC_STOPParam: specifies the STOP mode control parameters. +* This parameter can be one of the following values: +* - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On) +* - MRCC_STOPParam_OSC4MOff +* - MRCC_STOPParam_FLASHOff +* - MRCC_STOPParam_MVREGOff +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterSTOPMode(u32 MRCC_STOPParam) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits (STOP mode is selected) */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + +/* Low Power mode control parameters configuration ---------------------------*/ + /* Clear LP_PARAM[15:13] bits */ + MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask; + + if(MRCC_STOPParam != MRCC_STOPParam_Default) + { + /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */ + MRCC->PWRCTRL |= MRCC_STOPParam; + } + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_EnterSTANDBYMode +* Description : Enters STANDBY mode. +* Make sure that WKPF flag is cleared before using this function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterSTANDBYMode(void) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select STANDBY mode */ + MRCC->PWRCTRL |= MRCC_STANDBY_Mask; + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_GenerateSWReset +* Description : Generates a system software reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_GenerateSWReset(void) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select software reset */ + MRCC->PWRCTRL |= MRCC_SWRESET_Mask; + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_WriteBackupRegister +* Description : Writes user data to the specified backup register. +* Input : - MRCC_BKP: specifies the backup register. +* This parameter can be one of the following values: +* - MRCC_BKP0 +* - MRCC_BKP1 +* - Data: data to write. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data) +{ + if(MRCC_BKP == MRCC_BKP0) + { + MRCC->BKP0 = Data; + } + else + { + MRCC->BKP1 = Data; + } +} + +/******************************************************************************* +* Function Name : MRCC_ReadBackupRegister +* Description : Reads data from the specified backup register. +* Input : - MRCC_BKP: specifies the backup register. +* This parameter can be one of the following values: +* - MRCC_BKP0 +* - MRCC_BKP1 +* Output : None +* Return : The content of the specified backup register. +*******************************************************************************/ +u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP) +{ + if(MRCC_BKP == MRCC_BKP0) + { + return(MRCC->BKP0); + } + else + { + return(MRCC->BKP1); + } +} + +/******************************************************************************* +* Function Name : MRCC_IOVoltageRangeConfig +* Description : Configures the I/O pins voltage range. +* Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range. +* This parameter can be one of the following values: +* - MRCC_IOVoltageRange_5V +* - MRCC_IOVoltageRange_3V3 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange) +{ + if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3) + { + MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3; + } + else + { + MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V; + } +} + +/******************************************************************************* +* Function Name : MRCC_MCOConfig +* Description : Selects the clock source to output on MCO pin (P0.1). +* To output the clock, the associated alternate function must +* be enabled in the I/O port controller. +* Input : - MRCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* - MRCC_MCO_HCLK +* - MRCC_MCO_PCLK +* - MRCC_MCO_OSC4M +* - MRCC_MCO_CKPLL2 +* - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2, +* is applied to this clock before outputting it to MCO pin. +* This parameter can be one of the following values: +* - MRCC_MCOPrescaler_1 +* - MRCC_MCOPrescaler_2 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler) +{ + u32 Temp = 0; +/* MCO prescaler configuration -----------------------------------------------*/ + if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2) + { + MRCC->CLKCTL |= MRCC_MCOPrescaler_2; + } + else + { + MRCC->CLKCTL &= MRCC_MCOPrescaler_1; + } + +/* MCO selection configuration -----------------------------------------------*/ + + /* Clear MCOS[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask; + + /* Set MCOS[1:0] bits according to MRCC_MCO value */ + Temp |= MRCC_MCO; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_OSC4MConfig +* Description : Configures the 4MHz main oscillator (OSC4M). +* This function must be used when the CK_SYS is not clocked +* by the OSC4M and the PLL is not enabled. +* Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator. +* This parameter can be one of the following values: +* - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled +* - MRCC_OSC4M_Disable: OSC4M disabled +* - MRCC_OSC4M_Bypass: OSC4M bypassed +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M) +{ + ErrorStatus Status = SUCCESS; + +/* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/ + if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) || + (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) && + ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))|| + ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)) + { + Status = ERROR; + } +/* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/ + else + { + switch(MRCC_OSC4M) + { + case MRCC_OSC4M_Default: + MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask; + break; + + case MRCC_OSC4M_Disable: + MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask; + MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask; + break; + + case MRCC_OSC4M_Bypass: + MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask; + MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask; + break; + + default: + Status = ERROR; + break; + } + } + + return Status; +} + +/******************************************************************************* +* Function Name : MRCC_OSC32KConfig +* Description : Configures the OSC32K oscillator. +* This function must be used when the CK_SYS is not clocked by +* the CK_RTC. +* Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator. +* This parameter can be one of the following values: +* - MRCC_OSC32K_Disable: OSC32K disabled +* - MRCC_OSC32K_Enable: OSC32K enabled +* - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is +* bypassed or not. +* This parameter can be one of the following values: +* - MRCC_OSC32KBypass_Disable: OSC32K selected +* - MRCC_OSC32KBypass_Enable: OSC32K bypassed +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass) +{ +/* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/ + if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) + { + return ERROR; + } +/* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/ + else + { + /* Configure OSC32KEN bit */ + if(MRCC_OSC32K == MRCC_OSC32K_Enable) + { + MRCC->PWRCTRL |= MRCC_OSC32K_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_OSC32K_Disable; + } + + /* Configure OSC32KBYP bit */ + if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable) + { + MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable; + } + + return SUCCESS; + } +} + +/******************************************************************************* +* Function Name : MRCC_LPOSCConfig +* Description : Enables or disables the LPOSC oscillator. +* This function must be used when the CK_SYS is not clocked by +* the CK_RTC. +* Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator. +* This parameter can be one of the following values: +* - MRCC_LPOSC_Disable: LPOSC disabled +* - MRCC_LPOSC_Enable: LPOSC enabled +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC) +{ +/* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/ + if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) || + ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC)) + { + return ERROR; + } +/* Else configure the LPOSCEN bit --------------------------------------------*/ + else + { + if(MRCC_LPOSC == MRCC_LPOSC_Enable) + { + MRCC->PWRCTRL |= MRCC_LPOSC_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_LPOSC_Disable; + } + + return SUCCESS; + } +} + +/******************************************************************************* +* Function Name : MRCC_RTCMConfig +* Description : Enables or disables RTC clock measurement. +* Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB +* timer IC1 or not. +* This parameter can be one of the following values: +* - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1 +* - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_RTCMConfig(u32 MRCC_RTCM) +{ + if(MRCC_RTCM == MRCC_RTCM_Enable) + { + MRCC->PWRCTRL |= MRCC_RTCM_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_RTCM_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_SetBuilderCounter +* Description : Sets the builder counter value which defines the delay for +* the 4MHz main oscillator (OSC4M) clock to be stabilized. +* Input : - BuilderCounter: defines the delay for the OSC4M oscillator +* clock to be stabilized. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_SetBuilderCounter(u8 BuilderCounter) +{ + *(u8 *) 0x60000026 = BuilderCounter; +} + +/******************************************************************************* +* Function Name : MRCC_GetCKSYSCounter +* Description : Gets the result of the delay applied to CK_SYS before +* starting the CPU. +* Input : None +* Output : None +* Return : SCOUNT value. +*******************************************************************************/ +u16 MRCC_GetCKSYSCounter(void) +{ + return((u16)(MRCC->RFSR & 0x0FFF)); +} + +/******************************************************************************* +* Function Name : MRCC_GetFlagStatus +* Description : Checks whether the specified MRCC flag is set or not. +* Input : - MRCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - MRCC_FLAG_LOCK: PLL Locked flag +* - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag +* - MRCC_FLAG_CKSEL: CK_SYS source staus flag +* - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag +* - MRCC_FLAG_NCKD: No Clock Detected flag +* - MRCC_FLAG_SWR: Software Reset flag +* - MRCC_FLAG_WDGR: Watchdog Reset flag +* - MRCC_FLAG_EXTR: External Reset flag +* - MRCC_FLAG_WKP: Wake-Up flag +* - MRCC_FLAG_STDB: STANDBY flag +* - MRCC_FLAG_BCOUNT: Builder Counter Flag +* - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready +* - MRCC_FLAG_CKRTCOK: CK_RTC OK +* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed +* - MRCC_FLAG_LP: Low Power Mode Entry +* Output : None +* Return : The new state of MRCC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG) +{ + u32 MRCCReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the MRCC register index */ + MRCCReg = MRCC_FLAG >> 5; + + /* Get the flag position */ + FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; + + if(MRCCReg == 1) /* The flag to check is in CLKCTL register */ + { + StatusReg = MRCC->CLKCTL; + } + else if (MRCCReg == 2) /* The flag to check is in RFSR register */ + { + StatusReg = MRCC->RFSR; + } + else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */ + { + StatusReg = MRCC->PWRCTRL; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MRCC_ClearFlag +* Description : Clears the MRCC’s pending flags. +* Input : - MRCC_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - MRCC_FLAG_NCKD: No Clock Detected flag +* - MRCC_FLAG_SWR: Software Reset flag +* - MRCC_FLAG_WDGR: Watchdog Reset flag +* - MRCC_FLAG_EXTR: External Reset flag +* - MRCC_FLAG_WKP: Wake-Up flag +* - MRCC_FLAG_STDB: STANDBY flag +* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ClearFlag(u8 MRCC_FLAG) +{ + u32 MRCCReg = 0, FlagPos = 0; + + /* Get the MRCC register index */ + MRCCReg = MRCC_FLAG >> 5; + + /* Get the flag position */ + FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; + + if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */ + { + MRCC->CLKCTL &= ~(1 << FlagPos); + } + else if (MRCCReg == 2) /* The flag to clear is in RFSR register */ + { + MRCC->RFSR &= ~(1 << FlagPos); + } + else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */ + { + MRCC->PWRCTRL &= ~(1 << FlagPos); + } +} + +/******************************************************************************* +* Function Name : MRCC_GetITStatus +* Description : Checks whether the specified MRCC interrupt has occurred or not. +* Input : - MRCC_IT: specifies the MRCC interrupt source to check. +* This parameter can be one of the following values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* Output : None +* Return : The new state of MRCC_IT (SET or RESET). +*******************************************************************************/ +ITStatus MRCC_GetITStatus(u32 MRCC_IT) +{ + /* Check the specified interrupt pending bit */ + if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MRCC_ClearITPendingBit +* Description : Clears the MRCC’s interrupt pending bits. +* Input : - MRCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following +* values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ClearITPendingBit(u32 MRCC_IT) +{ + /* Clear the specified interrupt pending bit */ + MRCC->CLKCTL &= ~(MRCC_IT >> 1); +} + +/******************************************************************************* +* Function Name : MRCC_WaitForOSC4MStartUp +* Description : Waits for OSC4M start-up. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: OSC4M oscillator is stable and ready to use +* - ERROR: no clock is detected on OSC4M +*******************************************************************************/ +ErrorStatus MRCC_WaitForOSC4MStartUp(void) +{ + u32 StartUpCounter = 0; + + do + { + /* Clear No Clock Detected flag */ + if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET) + { + MRCC_ClearFlag(MRCC_FLAG_NCKD); + } + + StartUpCounter++; + + }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&& + (StartUpCounter != OSC4MStartUp_TimeOut)); + + if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_FREEOSC +* Description : Selects FREEOSC as CK_SYS clock source. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_FREEOSC(void) +{ + /* Check if the PLL is enabled */ + if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) + { + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { /* CK_PLL1 used as Ck_SYS clock source*/ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + {/* Check if CK_RTC source clock is present*/ + if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET) + { + /* CK_RTC disabled*/ + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + } + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_OSC4M +* Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source. +* Input : PLL_State: specifies the PLL state. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State) +{ +/* If OSC4M is not present, exit ---------------------------------------------*/ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || + ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) ) + { + /* OSC4M disabled or OSC4M clock is not present*/ + return ERROR; + } + +/* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { /* CK_RTC used as CK_OSC clock */ + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + } + + /* Clear CKOSCSEL bit ----------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 0 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + if(PLL_State == MRCC_PLL_Disabled) + { + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_OSC4MPLL +* Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as +* CK_SYS clock source. +* Input : PLL_Mul: specifies the PLL factor. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul) +{ + /* Check if 4MHz main oscillator clock is present */ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) && + ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)) + { + if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul)) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + /* If CK_RTC is selected as CK_OSC clock source */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + /* Clear CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + } + + /* Clear CKOSCSEL bit ------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 0 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + + /* Configure PLL factor */ + if(PLL_Mul == MRCC_PLL_Mul_16) + { + MRCC->CLKCTL &= MRCC_MX_Reset_Mask; + } + else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) || + (PLL_Mul == MRCC_PLL_Mul_12)) + { + /* Clear MX[1:0] bits */ + MRCC->CLKCTL &= MRCC_MX_Reset_Mask; + /* Set MX[1:0] bits according to PLL_Mul value */ + MRCC->CLKCTL |= PLL_Mul; + } + + if(Main_Oscillator == 4000000) + {/* 4 MHz external Quartz oscillator used as main oscillator */ + /* Disable Oscillator Divider by 2 */ + MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask; + } + else if(Main_Oscillator == 8000000) + {/* 8 MHz external Quartz oscillator used as main oscillator */ + /* Enable Oscillator Divider by 2 */ + MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask; + } + + /* Enable PLL */ + MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask; + + /* Wait until the PLL is locked */ + while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET) + { + /* If OSC4M clock disapear or the PLL is disabled, exit */ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || + ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)) + { + return ERROR; + } + } + + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + } + else + { + /* OSC4M disabled or OSC4M clock is not present*/ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_RTC +* Description : Selects RTC clock (CK_RTC) as CK_SYS clock source. +* Input : PLL_State: specifies the PLL state. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_RTC(u32 PLL_State) +{ + /* Check if CK_RTC clock is enabled and ready to use */ + if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)|| + ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET)) + { +/* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Set CKOSCSEL bit ----------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 1 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + if(PLL_State == MRCC_PLL_Disabled) + { + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + /* CK_RTC disabled */ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : WriteLPBit +* Description : Executes the Low Power bit writing sequence. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void WriteLPBit(void) +{ + u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; + + /* Clear LP_DONE flag */ + MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask; + + Tmp = MRCC->PWRCTRL; + Tmp1 = Tmp | MRCC_LP_Set_Mask; + Tmp2 = Tmp & MRCC_LP_Reset_Mask; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Reset LP bit */ + MRCC->PWRCTRL = Tmp2; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Read LP bit*/ + Tmp = MRCC->PWRCTRL; +} + +/******************************************************************************* +* Function Name : WriteCKOSCSELBit +* Description : Executes the CKOSCSEL bit writing sequence. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void WriteCKOSCSELBit(void) +{ + u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; + + Tmp = MRCC->CLKCTL; + Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask; + Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Reset CKOSCSEL bit */ + MRCC->CLKCTL = Tmp2; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Read CKOSCSEL bit */ + Tmp = MRCC->CLKCTL; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c new file mode 100644 index 0000000000..79c15aa5b5 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c @@ -0,0 +1,1153 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_pwm.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the PWM software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_pwm.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* PWM interrupt masks */ +#define PWM_IT_Clear_Mask 0x7FFF +#define PWM_IT_Enable_Mask 0xEFFF + +/* PWM_CR Masks bit */ +#define PWM_CounterMode_Mask 0xFF8F +#define PWM_DBASE_Mask 0x077F +#define PWM_MasterModeSelection_Mask 0xFC7F + +/* PWM Update flag selection Set/Reset value */ +#define PWM_UFS_Reset 0xFFFE +#define PWM_UFS_Set 0x0001 + +/* PWM Counter value */ +#define PWM_COUNTER_Reset 0x0002 +#define PWM_COUNTER_Start 0x0004 +#define PWM_COUNTER_Stop 0xFFFB + +/* PWM Debug Mode Set/Reset value */ +#define PWM_DBGC_Set 0x0400 +#define PWM_DBGC_Reset 0xFBFF + +/* PWM Output Compare Polarity Set/Reset value */ +#define PWM_OC1P_Set 0x0020 +#define PWM_OC1P_Reset 0xFFDF + +#define PWM_OC1NP_Set 0x0080 +#define PWM_OC1NP_Reset 0xFF7F + +#define PWM_OC2P_Set 0x2000 +#define PWM_OC2P_Reset 0xDFFF + +#define PWM_OC2NP_Set 0x8000 +#define PWM_OC2NP_Reset 0x7FFF + +#define PWM_OC3P_Set 0x0020 +#define PWM_OC3P_Reset 0xFFDF + +#define PWM_OC3NP_Set 0x0080 +#define PWM_OC3NP_Reset 0xFF7F + +/* PWM Output Compare control mode constant */ +#define PWM_OCControl_PWM 0x000C +#define PWM_OCControl_OCToggle 0x0006 +#define PWM_OCControl_OCInactive 0x0004 +#define PWM_OCControl_OCActive 0x0002 +#define PWM_OCControl_OCTiming 0x0000 + +/* PWM Output Compare mode Enable value */ +#define PWM_OC1_Enable 0x0010 +#define PWM_OC2_Enable 0x1000 +#define PWM_OC3_Enable 0x0010 + +#define PWM_OC1_Disable 0xFFEF +#define PWM_OC2_Disable 0xEFFF +#define PWM_OC3_Disable 0xFFEF + +#define PWM_OC1N_Enable 0x0040 +#define PWM_OC2N_Enable 0x4000 +#define PWM_OC3N_Enable 0x0040 + +#define PWM_OC1N_Disable 0xFFBF +#define PWM_OC2N_Disable 0xBFFF +#define PWM_OC3N_Disable 0xFFBF + +/* PWM Output Compare mode Mask value */ +#define PWM_OC1C_Mask 0xFFF1 +#define PWM_OC2C_Mask 0xF1FF +#define PWM_OC3C_Mask 0xFFF1 + +/* PWM Preload bit Set/Reset value */ +#define PWM_PLD1_Set 0x0001 +#define PWM_PLD2_Set 0x0100 +#define PWM_PLD3_Set 0x0001 + +/* PWM OCRM Set/Reset value */ +#define PWM_OCMR_Set 0x0080 +#define PWM_OCMR_Reset 0xFF7F + +/* PWM_DTR bit Masks value */ +#define PWM_DTR_Mask 0xFC00 +#define PWM_LOCK_Mask 0xF3FF + +/* PWM MOE Set value */ +#define PWM_MOE_Set 0x8000 +#define PWM_MOE_Reset 0x7FFF + +/* PWM OSSR bit Set/Reset value */ +#define PWM_OSSR_Set 0x4000 +#define PWM_OSSR_Reset 0xBFFF + +/* Reset Register Masks */ +#define PWM_Prescaler_Reset_Mask 0x0000 +#define PWM_Pulse1_Reset_Mask 0x0000 +#define PWM_Pulse2_Reset_Mask 0x0000 +#define PWM_Pulse3_Reset_Mask 0x0000 +#define PWM_Period_Reset_Mask 0xFFFF +#define PWM_RepetitionCounter_Reset_Mask 0x0000 +#define PWM_DeadTime_Reset_Mask 0x0000 + +/* Private function prototypes -----------------------------------------------*/ +static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct); + +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : PWM_DeInit +* Description : Deinitializes PWM peripheral registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DeInit(void) +{ + /* Enters and exits the PWM peripheral to and from reset */ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE); +} + +/******************************************************************************* +* Function Name : PWM_Init +* Description : Initializes the PWM peripheral according to the specified +* parameters in the PWM_InitStruct . +* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that +* contains the configuration information for the PWM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_Init(PWM_InitTypeDef* PWM_InitStruct) +{ + /* Sets the prescaler value */ + PWM->PSC = PWM_InitStruct->PWM_Prescaler; + + /* Selects the counter mode */ + PWM->CR &= PWM_CounterMode_Mask; + PWM->CR |= PWM_InitStruct->PWM_CounterMode; + + /* Sets the period value */ + PWM->ARR = PWM_InitStruct->PWM_Period; + + /* Sets the repetition counter */ + PWM->RCR &= PWM_RepetitionCounter_Reset_Mask; + PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter; + + /* Configures the PWM according to the PWM_InitTypeDef structure parameters */ + OCM_ModuleConfig(PWM_InitStruct); +} + +/******************************************************************************* +* Function Name : PWM_StructInit +* Description : Fills each PWM_InitStruct member with its default value. +* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct) +{ + /* Sets the default configuration */ + PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming; + PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask; + PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up; + PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask; + PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable; + PWM_InitStruct->PWM_OCState = PWM_OCState_Disable; + PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable; + PWM_InitStruct->PWM_Channel = PWM_Channel_1; + PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask; + PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask; + PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask; + PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High; + PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High; + PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High; + PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High; + PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High; + PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High; + PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable; + PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask; + PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable; + PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF; + PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable; + PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask; +} + +/******************************************************************************* +* Function Name : PWM_Cmd +* Description : Enables or disables the PWM peripheral. +* Input : Newstate: new state of the PWM peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_Cmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->CR |= PWM_COUNTER_Start; + } + else + { + PWM->CR &= PWM_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : PWM_CtrlPWMOutputs +* Description : Enables or disables PWM peripheral Main Outputs. +* Input : Newstate: new state of the PWM peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_CtrlPWMOutputs(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->DTR |= PWM_MOE_Set; + } + else + { + PWM->DTR &= PWM_MOE_Reset; + } +} + +/******************************************************************************* +* Function Name : PWM_ITConfig +* Description : Enables or disables the PWM interrupts. +* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* - Newstate: new state of PWM interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate) +{ + u16 PWM_IT_Enable = 0; + + PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate) + { + PWM->CR &= PWM_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update) + { + PWM->CR |= PWM_UFS_Set; + } + /* Select and enable the interrupts requests */ + PWM->RSR |= PWM_IT_Enable; + PWM->RER |= PWM_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + PWM->RSR &= ~PWM_IT_Enable; + PWM->RER &= ~PWM_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : PWM_DMAConfig +* Description : Configures the PWM’s DMA interface. +* Input : - PWM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source +* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source +* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source +* - PWM_DMASource_Update: PWM Update DMA source +* - PWM_OCRMState: the state of output compare request mode. +* This parameter can be one of the following values: +* - PWM_OCRMState_Enable +* - PWM_OCRMState_Disable +* - PWM_DMABase:DMA Base address. +* This parameter can be one of the following values: +* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1, +* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER, +* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC, +* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1, +* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase) +{ + /* Select the DMA requests */ + PWM->RSR &= ~PWM_DMASources; + + /* Sets the OCRM state */ + if(PWM_OCRMState == PWM_OCRMState_Enable) + { + PWM->RSR |= PWM_OCMR_Set; + } + else + { + PWM->RSR &= PWM_OCMR_Reset; + } + + /* Sets the DMA Base address */ + PWM->CR &= PWM_DBASE_Mask; + PWM->CR |= PWM_DMABase; +} + +/******************************************************************************* +* Function Name : PWM_DMACmd +* Description : Enables or disables the PWM’s DMA interface. +* Input : - PWM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source +* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source +* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source +* - PWM_DMASource_Update: PWM Update DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->RER |= PWM_DMASources; + } + else + { + PWM->RER &= ~PWM_DMASources; + } +} + +/******************************************************************************* +* Function Name : PWM_SetPrescaler +* Description : Sets the PWM prescaler value. +* Input : Prescaler: PWM prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPrescaler(u16 Prescaler) +{ + PWM->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : PWM_SetPeriod +* Description : Sets the PWM period value. +* Input : Period: PWM period new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPeriod(u16 Period) +{ + PWM->ARR = Period; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse +* Description : Sets the PWM pulse value. +* Input : - PWM_Channel: specifies the PWM channel to be used. +* This parameter can be one of the following values: +* - PWM_Channel_1: PWM Channel 1 is used +* - PWM_Channel_2: PWM Channel 2 is used +* - PWM_Channel_3: PWM Channel 3 is used +* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used +* - Pulse: PWM pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse(u16 PWM_Channel, u16 Pulse) +{ + /* Sets Channel 1 pulse value */ + if(PWM_Channel == PWM_Channel_1) + { + PWM->OCR1 = Pulse; + } + /* Sets Channel 2 pulse value */ + else if(PWM_Channel == PWM_Channel_2) + { + PWM->OCR2 = Pulse; + } + /* Sets Channel 3 pulse value */ + else if(PWM_Channel == PWM_Channel_3) + { + PWM->OCR3 = Pulse; + } + /* Sets Channel 1, Channel 2 and Channel 3 pulse values */ + else if(PWM_Channel == PWM_Channel_ALL) + { + PWM->OCR1 = Pulse; + PWM->OCR2 = Pulse; + PWM->OCR3 = Pulse; + } +} + +/******************************************************************************* +* Function Name : PWM_SetPulse1 +* Description : Sets the PWM Channel 1 pulse value. +* Input : - Pulse: PWM Channel 1 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse1(u16 Pulse) +{ + PWM->OCR1 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse2 +* Description : Sets the PWM Channel 2 pulse value. +* Input : - Pulse: PWM Channel 2 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse2(u16 Pulse) +{ + PWM->OCR2 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse3 +* Description : Sets the PWM Channel 3 pulse value. +* Input : - Pulse: PWM Channel 3 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse3(u16 Pulse) +{ + PWM->OCR3 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_DebugCmd +* Description : Enables or disables PWM peripheral Debug control. +* Input : Newstate: new state of the PWM Debug control. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DebugCmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->CR |= PWM_DBGC_Set; + } + else + { + PWM->CR &= PWM_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : PWM_CounterModeConfig +* Description : Specifies the Counter Mode to be used. +* Input : PWM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - PWM_CounterMode_Up: PWM Up Counting Mode +* - PWM_CounterMode_Down: PWM Down Counting Mode +* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode +* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode +* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode +* Output : None +* Return : None +*******************************************************************************/ +void PWM_CounterModeConfig(u16 PWM_CounterMode) +{ + /* Counter mode configuration */ + PWM->CR &= PWM_CounterMode_Mask; + PWM->CR |= PWM_CounterMode; +} + +/******************************************************************************* +* Function Name : PWM_ForcedOCConfig +* Description : Forces the PWM output waveform to active or inactive level. +* Input : - PWM_Channel: specifies the PWM channel to be used. +* This parameter can be one of the following values: +* - PWM_Channel_1: PWM Channel 1 is used +* - PWM_Channel_2: PWM Channel 2 is used +* - PWM_Channel_3: PWM Channel 3 is used +* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used +* - PWM_ForcedAction: specifies the forced Action to be set to the +* output waveform. +* This parameter can be one of the following values: +* - PWM_ForcedAction_Active: Force active level on OCxREF +* - PWM_ForcedAction_InActive: Force inactive level on +* OCxREF +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction) +{ + /* Channel 1 Forced Output Compare mode configuration */ + if(PWM_Channel == PWM_Channel_1) + { + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_ForcedAction; + } + /* Channel 2 Forced Output Compare mode configuration */ + else + { + if(PWM_Channel == PWM_Channel_2) + { + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_ForcedAction<<8); + } + else + { + /* Channel 3 Forced Output Compare mode configuration */ + if(PWM_Channel == PWM_Channel_3) + { + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_ForcedAction; + } + /* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode + configuration */ + else + { + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_ForcedAction; + + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_ForcedAction<<8); + + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_ForcedAction; + } + } + } +} + +/******************************************************************************* +* Function Name : PWM_SetDeadTime +* Description : Inserts dead time between the OCx and OCNx. +* Input : DeadTime: PWM Dead Time value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetDeadTime(u16 DeadTime) +{ + /* Sets the dead time value */ + PWM->DTR &= PWM_DTR_Mask; + PWM->DTR |= DeadTime; +} + +/******************************************************************************* +* Function Name : PWM_ResetCounter +* Description : Re-intializes the PWM counter and generates an update of the +* registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ResetCounter(void) +{ + /* Resets the PWM counter */ + PWM->CR |= PWM_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : PWM_TRGOSelection +* Description : Sets the PWM Master Mode selection bits. +* Input : PWM_TRGOMode: specifies the TRGO source. +* This parameter can be one of the following values: +* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO +* - PWM_TRGOMode_Update: The Update event is used as TRGO +* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO +* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO +* Output : None +* Return : None +*******************************************************************************/ +void PWM_TRGOSelection(u16 PWM_TRGOMode) +{ + /* Sets the synchronization action */ + PWM->CR &= PWM_MasterModeSelection_Mask; + PWM->CR |= PWM_TRGOMode; +} + +/******************************************************************************* +* Function Name : PWM_GetFlagStatus +* Description : Checks whether the specified PWM flag is set or not. +* Input : PWM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - PWM_FLAG_OC1: Output Compare 1 Flag +* - PWM_FLAG_OC2: Output Compare 2 Flag +* - PWM_FLAG_OC3: Output Compare 3 Flag +* - PWM_FLAG_Update: PWM update Flag +* - PWM_FLAG_Emergency: PWM Emergency Flag +* Output : None +* Return : The new state of the PWM_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG) +{ + if((PWM->ISR & PWM_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : PWM_ClearFlag +* Description : Clears the PWM’s pending flags. +* Input : PWM_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - PWM_FLAG_OC1: Output Compare 1 flag +* - PWM_FLAG_OC2: Output Compare 2 flag +* - PWM_FLAG_OC3: Output Compare 3 flag +* - PWM_FLAG_Update: PWM update flag +* - PWM_FLAG_Emergency: PWM Emergency flag +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ClearFlag(u16 PWM_FLAG) +{ + /* Clears the flags */ + PWM->ISR &= ~PWM_FLAG; +} + +/******************************************************************************* +* Function Name : PWM_GetITStatus +* Description : Checks whether the PWM interrupt has occurred or not. +* Input : PWM_IT: specifies the PWM interrupt source to check. +* This parameter can be one of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* Output : None +* Return : The new state of the PWM_IT(SET or RESET). +*******************************************************************************/ +ITStatus PWM_GetITStatus(u16 PWM_IT) +{ + u16 PWM_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask; + + if((PWM->ISR & PWM_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : PWM_ClearITPendingBit +* Description : Clears the PWM's interrupt pending bits. +* Input : PWM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ClearITPendingBit(u16 PWM_IT) +{ + u16 PWM_IT_Clear = 0; + + /* Calculates the pending bits to be cleared */ + PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask; + + /* Clears the pending bits */ + PWM->ISR &= ~PWM_IT_Clear; + +} + +/******************************************************************************* +* Function Name : OCM_ModuleConfig +* Description : Output Compare Module configuration. +* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that +* contains the configuration information for the PWM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct) +{ + u16 PWM_OCControl = 0x0000; + u16 DTR_REG = 0x0000; + + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming) + { + PWM_OCControl = PWM_OCControl_OCTiming; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive) + { + PWM_OCControl = PWM_OCControl_OCActive; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive) + { + PWM_OCControl = PWM_OCControl_OCInactive; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle) + { + PWM_OCControl = PWM_OCControl_OCToggle; + } + else + { + PWM_OCControl = PWM_OCControl_PWM; + + } + } + } + } + + /* Read DTR register */ + DTR_REG = PWM->DTR & 0x8000; + +/*Channel 1 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_1) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 1 on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + + /* Sets the OC1N wave polarity */ + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + }/* End complementary case */ + /* Single PWM Output configuratuion */ + else + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 1 on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable; + PWM->OMR1 |= PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC1E = 0 and OSSR = 0 sets the polarity */ + PWM->OMR1 &= PWM_OC1_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC1E = 0 and OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC1_Disable; + DTR_REG |= PWM_OSSR_Set; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + } + break; + } + + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 1N on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1N wave polarity */ + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC1N = 0 OSSR = 0 */ + PWM->OMR1 &= PWM_OC1N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC1N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC1N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 1 */ + +/*Channel 2 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_2) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 2 on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Set the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + + /* Sets the OC2N wave polarity */ + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + + }/* End complentary case */ + else + /* Single PWM Output configuratuion */ + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 2 on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC2E = 0 and OSSR = 0 */ + PWM->OMR1 &= PWM_OC2_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC2E = 0 and OSSR = 1 sets the polarity */ + PWM->OMR1 &= PWM_OC2_Disable; + DTR_REG |= PWM_OSSR_Set; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + } + break; + } + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 2N on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC2N = 0 OSSR = 0 */ + PWM->OMR1 &= PWM_OC2N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC2N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC2N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 2 */ + +/*Channel 3 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_3) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 3 on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OC3 wave polarity */ + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + + /* Sets the OC3N wave polarity */ + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + }/* End complementary case */ + else + /* Single PWM Output configuratuion */ + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 3 on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OCC wave polarity */ + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC3E = 0 and OSSR = 0 */ + PWM->OMR2 &= PWM_OC3_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC3E = 0 and OSSR = 1 sets the polarity */ + PWM->OMR2 &= PWM_OC3_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + } + break; + } + + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 3N on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OC3 wave polarity */ + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC3N = 0 OSSR = 0 */ + PWM->OMR2 &= PWM_OC3N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC3N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR2 &= PWM_OC3N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 3 */ + + if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable) + { + DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency | + PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState; + PWM->DTR = DTR_REG; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c new file mode 100644 index 0000000000..ab6da500bb --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c @@ -0,0 +1,326 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_rtc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the RTC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_rtc.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define RTC_CNF_Enable_Mask 0x0010 /* Configuration Flag Enable Mask */ +#define RTC_CNF_Disable_Mask 0xFFEF /* Configuration Flag Disable Mask */ +#define RTC_LSB_Mask 0x0000FFFF /* RTC LSB Mask */ +#define RTC_MSB_Mask 0xFFFF0000 /* RTC MSB Mask */ +#define RTC_Prescaler_MSB_Mask 0x000F0000 /* RTC Prescaler MSB Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : RTC_DeInit +* Description : Deinitializes the RTC peripheral registers to their +* default reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_DeInit(void) +{ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,DISABLE); +} + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enables or disables the specified RTC interrupts. +* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled +* or disabled. +* This parameter can be a combination of one or more of the +* following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* - NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= ~RTC_IT; + } +} + +/******************************************************************************* +* Function Name : RTC_EnterConfigMode +* Description : Enters the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CNF_Enable_Mask; +} + +/******************************************************************************* +* Function Name : RTC_ExitConfigMode +* Description : Exits from the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= RTC_CNF_Disable_Mask; +} + +/******************************************************************************* +* Function Name : RTC_GetCounter +* Description : Gets the RTC counter value. +* Input : None +* Output : None +* Return : RTC counter value. +*******************************************************************************/ +u32 RTC_GetCounter(void) +{ + u16 Tmp = 0; + Tmp = RTC->CNTL; + + return (((u32)RTC->CNTH << 16 ) |Tmp) ; +} + +/******************************************************************************* +* Function Name : RTC_SetCounter +* Description : Sets the RTC counter value. +* Input : RTC counter new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetCounter(u32 CounterValue) +{ + RTC_EnterConfigMode(); + +/* COUNTER Config ------------------------------------------------------------*/ + /* Set RTC COUNTER MSB word */ + RTC->CNTH =(CounterValue & RTC_MSB_Mask) >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL =(CounterValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetPrescaler +* Description : Sets the RTC prescaler value. +* Input : RTC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetPrescaler(u32 PrescalerValue) +{ + RTC_EnterConfigMode(); + +/* PRESCALER Config ----------------------------------------------------------*/ + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & RTC_Prescaler_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetPrescaler +* Description : Gets the RTC prescaler value. +* Input : None +* Output : None +* Return : RTC prescaler value. +*******************************************************************************/ +u32 RTC_GetPrescaler(void) +{ + u16 Tmp = 0; + Tmp = RTC->PRLL; + + return (((u32)(RTC->PRLH & 0x000F) << 16 ) | Tmp); +} + +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the RTC alarm value. +* Input : RTC alarm new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(u32 AlarmValue) +{ + RTC_EnterConfigMode(); + +/* ALARM Config --------------------------------------------------------------*/ + /* Set the ALARM MSB word */ + RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetDivider +* Description : Gets the RTC divider value. +* Input : None +* Output : None +* Return : RTC Divider value. +*******************************************************************************/ +u32 RTC_GetDivider(void) +{ + u16 Tmp = 0; + Tmp = RTC->DIVL ; + return (((u32)(RTC->DIVH & 0x000F) << 16 ) | Tmp); +} + +/******************************************************************************* +* Function Name : RTC_WaitForLastTask +* Description : Waits until last write operation on RTC registers has finished. +* This function must be called before any write to RTC registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == RESET); +} + +/******************************************************************************* +* Function Name : RTC_WaitForSynchro +* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* This function must be called before any read operation after +* an APB reset or an APB clock stop. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= ~RTC_FLAG_RSF; + + /* Loop until RSF flag is set */ + while((RTC->CRL & RTC_FLAG_RSF)== RESET); +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Checks whether the specified RTC flag is set or not. +* Input : RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* - RTC_FLAG_RTOFF: RTC Operation OFF flag +* - RTC_FLAG_RSF: Registers Synchronized flag +* - RTC_FLAG_Overflow: Overflow interrupt flag +* - RTC_FLAG_Alarm: Alarm interrupt flag +* - RTC_FLAG_Second: Second interrupt flag +* Output : None +* Return : The new state of RTC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) +{ + if((RTC->CRL & RTC_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears the RTC’s pending flags. +* Input : RTC_FLAG: specifies the flag to clear. +* This parameter can be a combination of one or more of +* the following values: +* - RTC_FLAG_RSF: Registers Synchronized flag. This flag +* is cleared only after an APB reset or an APB Clock stop. +* - RTC_FLAG_Overflow: Overflow interrupt flag +* - RTC_FLAG_Alarm: Alarm interrupt flag +* - RTC_FLAG_Second: Second interrupt flag +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearFlag(u16 RTC_FLAG) +{ + /* Clear the coressponding RTC flag */ + RTC->CRL &= ~RTC_FLAG; +} + +/******************************************************************************* +* Function Name : RTC_GetITStatus +* Description : Checks whether the specified RTC interrupt has occured or not. +* Input : RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be a combination of one or more of +* the following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* Output : None +* Return : The new state of the RTC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RTC_GetITStatus(u16 RTC_IT) +{ + if(((RTC->CRH & RTC_IT) != RESET)&& ((RTC->CRL & RTC_IT) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : RTC_ClearITPendingBit +* Description : Clears the RTC’s interrupt pending bits. +* Input : RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of one or more of +* the following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearITPendingBit(u16 RTC_IT) +{ + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= ~RTC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c new file mode 100644 index 0000000000..9af53a9e8b --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c @@ -0,0 +1,551 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_smi.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the SMI software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_smi.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SMI_CR1 mask bits */ +#define SMI_HOLDPRESCTCS_RESET_Mask 0xFF00800F +#define SMI_Prescaler_MaxValue 0x7F +#define SMI_DeselectTime_MaxValue 0x0F +#define SMI_ClockHold_Mask 0x00 +#define SMI_Prescaler_Mask 0x02 +#define SMI_DeselectTime_Mask 0x5 + +/* SMI_CR2 mask bits */ +#define SMI_BS_RESET_Mask 0xFFFFCFFF +#define SMI_BS_Bank1_Mask 0x00001000 +#define SMI_BS_Bank2_Mask 0x00002000 +#define SMI_BS_Bank3_Mask 0x00003000 +#define SMI_WEN_Mask 0x00000800 +#define SMI_RSR_Mask 0x00000400 +#define SMI_SEND_Mask 0x00000080 +#define SMI_TRARECLENGTH_RESET_Mask 0xFFFFFF88 + +/* SMI_SR mask bits */ +#define SMI_STATUSREGISTER_Mask 0xFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SMI_DeInit +* Description : Deinitializes the SMI peripheral registers to their default +* reset values. This function must not be used when booting +* from the SMI external memory. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_DeInit(void) +{ + SMI->CR1 = 0x00000250; + SMI->CR2 = 0x00; + SMI->SR &= 0xFFFFF0FF; + SMI->TR = 0x00; +} + +/******************************************************************************* +* Function Name : SMI_Init +* Description : Initializes the SMI peripheral according to the specified +* parameters in the SMI_InitStruct. +* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure that +* contains the configuration information for the specified +* SMI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_Init(SMI_InitTypeDef* SMI_InitStruct) +{ + u32 Temp = 0; + + /* Clear HOLD[7:0], PRESC[6:0] and TCS[3:0] bits */ + Temp = SMI->CR1 & SMI_HOLDPRESCTCS_RESET_Mask; + + /* Set HOLD[7:0] bits according to SMI_ClockHold value */ + Temp |= SMI_InitStruct->SMI_ClockHold << 16; + + if(SMI_InitStruct->SMI_Prescaler <= SMI_Prescaler_MaxValue) + { + /* Set PRESC[6:0] bits according to SMI_Prescaler value */ + Temp |= SMI_InitStruct->SMI_Prescaler << 8; + } + + if(SMI_InitStruct->SMI_DeselectTime <= SMI_DeselectTime_MaxValue) + { + /* Set TCS[3:0] bits according to SMI_DeselectTime value */ + Temp |= SMI_InitStruct->SMI_DeselectTime << 4; + } + + /* Store the new value */ + SMI->CR1 = Temp; +} + +/******************************************************************************* +* Function Name : SMI_StructInit +* Description : Fills each SMI_InitStruct member with its reset value. +* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct) +{ + /* SMI_CK is sent continuously */ + SMI_InitStruct->SMI_ClockHold = SMI_ClockHold_Mask; + + /* SMI_CK = HCLK/2 */ + SMI_InitStruct->SMI_Prescaler = SMI_Prescaler_Mask; + + /* Deselect Time set to 6*SMI_CK periods */ + SMI_InitStruct->SMI_DeselectTime = SMI_DeselectTime_Mask; +} + +/******************************************************************************* +* Function Name : SMI_ModeConfig +* Description : Selects the SMI mode: hardware or software. +* Input : - SMI_Mode: specifies the SMI mode. +* This parameter can be one of the following values: +* - SMI_Mode_HW: SMI in hardware mode +* - SMI_Mode_SW: SMI in software mode +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ModeConfig(u32 SMI_Mode) +{ + if(SMI_Mode == SMI_Mode_SW) + { + SMI->CR1 |= SMI_Mode_SW; + } + else + { + SMI->CR1 &= SMI_Mode_HW; + } +} + +/******************************************************************************* +* Function Name : SMI_TxRxLengthConfig +* Description : Configures the number of bytes to be transmitted and received +* to/from external memory. This function is used in Software +* mode only. +* Input : - SMI_TxLength: specifies the number of bytes to be transmitted +* to external memory. +* This parameter can be one of the following values: +* - SMI_TxLength_0Bytes: No bytes transmitted +* - SMI_TxLength_1Byte: 1 byte transmitted +* - SMI_TxLength_2Bytes: 2 bytes transmitted +* - SMI_TxLength_3Bytes: 3 bytes transmitted +* - SMI_TxLength_4Bytes: 4 bytes transmitted +* - SMI_RxLength: specifies the number of bytes to be received +* from external memory. +* This parameter can be one of the following values: +* - SMI_RxLength_0Bytes: No bytes received +* - SMI_RxLength_1Byte: 1 byte received +* - SMI_RxLength_2Bytes: 2 bytes received +* - SMI_RxLength_3Bytes: 3 bytes received +* - SMI_RxLength_4Bytes: 4 bytes received +* Output : None +* Return : None +*******************************************************************************/ +void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength) +{ + u32 Temp = 0; + + /* Clear TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits */ + Temp = SMI->CR2 & SMI_TRARECLENGTH_RESET_Mask; + + /* Set TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits according to function parameters */ + Temp |= SMI_TxLength | SMI_RxLength; + + /* Store the new value */ + SMI->CR2 = Temp; +} + +/******************************************************************************* +* Function Name : SMI_BankCmd +* Description : Enables or disables the specified memory Bank. +* Input : - SMI_Bank: specifies the memory Bank to be enabled or disabled. +* This parameter can be any combination of the following values: +* - SMI_Bank_0 +* - SMI_Bank_1 +* - SMI_Bank_2 +* - SMI_Bank_3 +* - NewState: new state of the specified memory Bank. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SMI->CR1 |= SMI_Bank; + } + else + { + SMI->CR1 &= ~SMI_Bank; + } +} + +/******************************************************************************* +* Function Name : SMI_ITConfig +* Description : Enables or disables the specified SMI interrupts. +* Input : - SMI_IT: specifies the SMI interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* - NewState: new state of the specified SMI interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SMI->CR2 |= SMI_IT; + } + else + { + SMI->CR2 &= ~SMI_IT; + } +} + +/******************************************************************************* +* Function Name : SMI_SelectBank +* Description : Selects the memory Bank to be accessed. Only one Bank can be +* selected at a time. +* Input : - SMI_Bank: specifies the memory Bank to be selected. +* This parameter can be one of the following values: +* - SMI_Bank_0 +* - SMI_Bank_1 +* - SMI_Bank_2 +* - SMI_Bank_3 +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SelectBank(u32 SMI_Bank) +{ + /* Clear BS[1:0] bits (Bank0 is selected)*/ + SMI->CR2 &= SMI_BS_RESET_Mask; + + switch(SMI_Bank) + { + case SMI_Bank_1: + /* Select Bank1 */ + SMI->CR2 |= SMI_BS_Bank1_Mask; + break; + + case SMI_Bank_2: + /* Select Bank2 */ + SMI->CR2 |= SMI_BS_Bank2_Mask; + break; + + case SMI_Bank_3: + /* Select Bank3 */ + SMI->CR2 |= SMI_BS_Bank3_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : SMI_SendWENCmd +* Description : Sends a Write Enable command to the selected memory Bank. +* This function is used in Hardware mode only. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendWENCmd(void) +{ + SMI->CR2 |= SMI_WEN_Mask; +} + +/******************************************************************************* +* Function Name : SMI_SendRSRCmd +* Description : Sends a Read Status Register Command to the selected memory +* Bank. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendRSRCmd(void) +{ + SMI->CR2 |= SMI_RSR_Mask; +} + +/******************************************************************************* +* Function Name : SMI_SendCmd +* Description : Sends command to the selected memory Bank. This function is +* used in Software mode only. +* Input : - Command: specifies the command to send to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendCmd(u32 Command) +{ + /* Load the command in the Transmit Register */ + SMI->TR = Command; + + /* Start transfer */ + SMI->CR2 |= SMI_SEND_Mask; +} + +/******************************************************************************* +* Function Name : SMI_FastReadConfig +* Description : Enables or disables the Fast Read Mode. +* Input : - SMI_FastRead: specifies whether the Fast Read Mode is +* enabled or disabled. +* This parameter can be one of the following values: +* - SMI_FastRead_Disable : Fast Read Mode disabled +* - SMI_FastRead_Enable : Fast Read Mode enabled +* Output : None +* Return : None +*******************************************************************************/ +void SMI_FastReadConfig(u32 SMI_FastRead) +{ + if(SMI_FastRead == SMI_FastRead_Enable) + { + SMI->CR1 |= SMI_FastRead_Enable; + } + else + { + SMI->CR1 &= SMI_FastRead_Disable; + } +} + +/******************************************************************************* +* Function Name : SMI_WriteBurstConfig +* Description : Enables or disables the Write Burst Mode. +* Input : - SMI_WriteBurst: specifies whether the Write Burst Mode is +* enabled or disabled. +* This parameter can be one of the following values: +* - SMI_WriteBurst_Disable : Write Burst Mode disabled +* - SMI_WriteBurst_Enable : Write Burst Mode enabled +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteBurstConfig(u32 SMI_WriteBurst) +{ + if(SMI_WriteBurst == SMI_WriteBurst_Enable) + { + SMI->CR1 |= SMI_WriteBurst_Enable; + } + else + { + SMI->CR1 &= SMI_WriteBurst_Disable; + } +} + +/******************************************************************************* +* Function Name : SMI_WriteByte +* Description : Writes a Byte to the selected memory Bank. This function is +* used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteByte(u32 WriteAddr, u8 Data) +{ + /* Transfer data to the memory */ + *(u8 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_WriteHalfWord +* Description : Writes a Half Word to the selected memory Bank. This function +* is used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteHalfWord(u32 WriteAddr, u16 Data) +{ + /* Transfer data to the memory */ + *(u16 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_WriteWord +* Description : Writes a Word to the selected memory Bank. This function is +* used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteWord(u32 WriteAddr, u32 Data) +{ + /* Transfer data to the memory */ + *(u32 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_ReadByte +* Description : Reads a Byte from the selected memory Bank. This function is +* used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u8 SMI_ReadByte(u32 ReadAddr) +{ + return(*(u8 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadHalfWord +* Description : Reads a Half Word from the selected memory Bank. This function +* is used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u16 SMI_ReadHalfWord(u32 ReadAddr) +{ + return(*(u16 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadWord +* Description : Reads a Word from the selected memory Bank. This function is +* used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u32 SMI_ReadWord(u32 ReadAddr) +{ + return(*(u32 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadMemoryStatusRegister +* Description : Reads the status register of the memory connected to the +* selected Bank. +* Input : None +* Output : None +* Return : External memory status register value. +*******************************************************************************/ +u8 SMI_ReadMemoryStatusRegister(void) +{ + return((u8) (SMI->SR & SMI_STATUSREGISTER_Mask)); +} + +/******************************************************************************* +* Function Name : SMI_GetFlagStatus +* Description : Checks whether the specified SMI flag is set or not. +* Input : - SMI_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SMI_FLAG_Bank3_WM : Memory Bank3 Write Mode flag +* - SMI_FLAG_Bank2_WM : Memory Bank2 Write Mode flag +* - SMI_FLAG_Bank1_WM : Memory Bank1 Write Mode flag +* - SMI_FLAG_Bank0_WM : Memory Bank0 Write Mode flag +* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request +* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access +* - SMI_FLAG_WC : Write Complete flag +* - SMI_FLAG_TF : Transfer Finished flag +* Output : None +* Return : The new state of SMI_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG) +{ + if((SMI->SR & SMI_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : SMI_ClearFlag +* Description : Clears the SMI’s pending flags. +* Input : - SMI_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request +* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access +* - SMI_FLAG_WC : Write Complete flag +* - SMI_FLAG_TF : Transfer Finished flag +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ClearFlag(u32 SMI_FLAG) +{ + SMI->SR &= ~SMI_FLAG; +} + +/******************************************************************************* +* Function Name : SMI_GetITStatus +* Description : Checks whether the specified SMI interrupt has occurred or not. +* Input : - SMI_FLAG: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* Output : None +* Return : The new state of SMI_IT (SET or RESET). +*******************************************************************************/ +ITStatus SMI_GetITStatus(u32 SMI_IT) +{ + if(((SMI->CR2 & SMI_IT) != RESET) && ((SMI->SR & SMI_IT) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : SMI_ClearITPendingBit +* Description : Clears the SMI’s interrupt pending bits. +* Input : - SMI_FLAG: specifies the interrupts sources to clear. +* This parameter can be any combination of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ClearITPendingBit(u32 SMI_IT) +{ + SMI->SR &= ~SMI_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c new file mode 100644 index 0000000000..b4ccd215e6 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c @@ -0,0 +1,588 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_ssp.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the SSP software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_ssp.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* SSP peripheral Enable */ +#define SSP_Enable 0x0002 +#define SSP_Disable 0xFFFD + +/* SSP Loop Back Mode Enable */ +#define SSP_LoopBackMode_Enable 0x0001 +#define SSP_LoopBackMode_Disable 0xFFFE + +/* SSP Flag Mask */ +#define SSP_Flag_Mask 0x001F + +/* SSP DMA transmit/ receive enable/disable Masks */ +#define SSP0_DMA_TransmitEnable 0x0002 +#define SSP0_DMA_TransmitDisable 0xFFFD +#define SSP0_DMA_ReceiveEnable 0x0001 +#define SSP0_DMA_ReceiveDisable 0xFFFE + +/* SSP Masks */ +#define SSP_FrameFormat_Mask 0xFFCF +#define SSP_DataSize_Mask 0xFFF0 +#define SSP_ClockRate_Mask 0x00FF +#define SSP_ClockPrescaler_Mask 0xFF00 +#define SSP_SSI_Set_Mask 0x0020 +#define SSP_SSI_Reset_Mask 0xFFDF + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SSP_DeInit +* Description : Deinitializes the SSPx peripheral registers to their default +* reset values. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DeInit(SSP_TypeDef* SSPx) +{ + if(SSPx == SSP0) + { + /* Reset the SSP0 registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,DISABLE); + } + else if (SSPx == SSP1) + { + /* Reset the SSP1 registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,DISABLE); + } +} + +/******************************************************************************* +* Function Name : SSP_Init +* Description : Initializes the SSPx peripheral according to the specified +* parameters in the SSP_InitTypeDef structure. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that +* contains the configuration information for the specified SSP +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) +{ + /* Configure the Frame format */ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) + { + /* Clear the FRF[1:0] bits */ + SSPx->CR0 &= SSP_FrameFormat_Mask; + /* Set the TI frame format */ + SSPx->CR0 |= SSP_FrameFormat_TI; + } + else + { + /* Set the Motorola frame format */ + SSPx->CR0 &= SSP_FrameFormat_Motorola; + /* Configure the Clock polarity */ + if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) + { + /* SCK is held high when no data is being transfered */ + SSPx->CR0 |= SSP_CPOL_High; + } + else + { + /* SCK is held low when no data is being transfered */ + SSPx->CR0 &= SSP_CPOL_Low; + } + /* Configure the Clock Phase */ + if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) + { + /* Data captured on second clock edge */ + SSPx->CR0 |= SSP_CPHA_2Edge; + } + else + { + /* Data captured on first clock edge */ + SSPx->CR0 &= SSP_CPHA_1Edge; + } + } + + /* Configure the Mode */ + if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) + { + /* Set the slave mode */ + SSPx->CR1 |= SSP_Mode_Slave; + /* Configure the Slave output */ + if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) + { + /* Slave output disabled */ + SSPx->CR1 |= SSP_SlaveOutput_Disable; + } + else + { + /* Slave output enabled */ + SSPx->CR1 &= SSP_SlaveOutput_Enable; + } + /* Configure the NSS pin */ + if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) + { + /* Slave selected by software through SSI bit */ + SSPx->CR1 |= SSP_NSS_Soft; + SSPx->CR1 &= SSP_SSI_Reset_Mask; + } + else + { + /* Slave selected by hardware through external SSpin */ + SSPx->CR1 &= SSP_NSS_Hard; + } + /* Configure the Clock rate and prescaler in TI slave mode */ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) + { + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + } + else + { + /* Set the master mode */ + SSPx->CR1 &= SSP_Mode_Master; + /* Configure the NSS pin */ + if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) + { + /* Master selected by software through SSI bit */ + SSPx->CR1 |= SSP_NSS_Soft; + SSPx->CR1 |= SSP_SSI_Set_Mask; + } + else + { + /* Master selected by hardware through external SSpin */ + SSPx->CR1 &= SSP_NSS_Hard; + } + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + + /* Clear data size DSS[3:0] bits */ + SSPx->CR0 &= SSP_DataSize_Mask; + /* Set the data size */ + SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; +} + +/******************************************************************************* +* Function Name : SSP_StructInit +* Description : Fills each SSP_InitStruct member with its default value. +* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) +{ + /* Initialize the SSP_FrameFormat member */ + SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; + + /* Initialize the SSP_Mode member */ + SSP_InitStruct->SSP_Mode = SSP_Mode_Master; + + /* Initialize the SSP_CPOL member */ + SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; + + /* Initialize the SSP_CPHA member */ + SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; + + /* Initialize the SSP_DataSize member */ + SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; + + /* Initialize the SSP_NSS member */ + SSP_InitStruct->SSP_NSS = SSP_NSS_Hard; + + /* Initialize the SSP_SlaveOutput member */ + SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; + + /* Initialize the SSP_ClockRate member */ + SSP_InitStruct->SSP_ClockRate = 0; + + /* Initialize the SSP_ClockPrescaler member */ + SSP_InitStruct->SSP_ClockPrescaler = 0; +} + +/******************************************************************************* +* Function Name : SSP_Cmd +* Description : Enables or disables the specified SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the SSPx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the SSP peripheral */ + SSPx->CR1 |= SSP_Enable; + } + else + { + /* Disable the SSP peripheral */ + SSPx->CR1 &= SSP_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_ITConfig +* Description : Enables or disables the specified SSP interrupts. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the SSP interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* - NewState: new state of the specified SSP interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected SSP interrupts */ + SSPx->IMSCR |= SSP_IT; + } + else + { + /* Disable the selected SSP interrupts */ + SSPx->IMSCR &= ~SSP_IT; + } +} + +/******************************************************************************* +* Function Name : SSP_DMACmd +* Description : Configures the SSP0 DMA interface. +* Input : - SSP0_DMAtransfer : specifies the DMA transfer to be +* enabled or disabled. This parameter can be one of the +* following values: +* - SSP0_DMA_Transmit: transmit Fifo DMA transfer +* - SSP0_DMA_Receive: receive Fifo DMA transfer +* - NewState: new state of SSP0 DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + if(SSP0_DMAtransfer == SSP0_DMA_Transmit) + { + /* Enable DMA for the transmit FIFO */ + SSP0->DMACR |= SSP0_DMA_TransmitEnable; + } + else + { + /* Enable DMA for the receive FIFO */ + SSP0->DMACR |= SSP0_DMA_ReceiveEnable; + } + } + else + { + if(SSP0_DMAtransfer == SSP0_DMA_Transmit) + { + /* Disable DMA for the transmit FIFO */ + SSP0->DMACR &= SSP0_DMA_TransmitDisable; + } + else + { + /* Disable DMA for the receive FIFO */ + SSP0->DMACR &= SSP0_DMA_ReceiveDisable; + } + } +} + +/******************************************************************************* +* Function Name : SSP_DMATxConfig +* Description : Configures the SSP0 DMA transmit transfer. +* Input : - SSP0_DMATxReq : specifies the SSP0 DMA transmit request to +* be enabled. This parameter can be one of the following +* values: +* - SSP0_DMATxReq_Single: Transmit FIFO DMA single +* request enabled +* - SSP0_DMATxReq_Burst: Transmit FIFO DMA burst request +* enabled +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMATxConfig(u16 SSP0_DMATxReq) +{ + if(SSP0_DMATxReq == SSP0_DMATxReq_Burst) + { + /* Enable DMA transmit burst request */ + SSP0->DMACR |= SSP0_DMATxReq_Burst; + } + else + { + /* Enable DMA transmit single request */ + SSP0->DMACR &= SSP0_DMATxReq_Single; + } +} + +/******************************************************************************* +* Function Name : SSP_DMARxConfig +* Description : Configures the SSP0 DMA receive transfer. +* Input : - SSP0_DMARxReq : specifies the SSP0 DMA receive request to +* be enabled. This parameter can be one of the following +* values: +* - SSP0_DMARxReq_Single: Receive FIFO DMA burst request +* enabled +* - SSP0_DMARxReq_Burst: Receive FIFO DMA single request +* enabled +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMARxConfig(u16 SSP0_DMARxReq) +{ + if(SSP0_DMARxReq == SSP0_DMARxReq_Burst) + { + /* Enable DMA receive burst request */ + SSP0->DMACR |= SSP0_DMARxReq_Burst; + } + else + { + /* Enable DMA receive single request */ + SSP0->DMACR &= SSP0_DMARxReq_Single; + } +} + +/******************************************************************************* +* Function Name : SSP_SendData +* Description : Transmits a Data through the SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - Data : Data to be transmitted. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SSPx->DR = Data; +} + +/******************************************************************************* +* Function Name : SSP_ReceiveData +* Description : Returns the most recent received data by the SSP peripheral. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SSP_ReceiveData(SSP_TypeDef* SSPx) +{ + /* Return the data in the DR register */ + return SSPx->DR; +} + +/******************************************************************************* +* Function Name : SSP_LoopBackConfig +* Description : Enables or disables the Loop back mode for the selected SSP +* peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the Loop Back mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable loop back mode */ + SSPx->CR1 |= SSP_LoopBackMode_Enable; + } + else + { + /* Disable loop back mode */ + SSPx->CR1 &= SSP_LoopBackMode_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_NSSInternalConfig +* Description : Configures by software the NSS pin. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_NSSState: NSS internal state.This parameter can be one +* of the following values: +* - SSP_NSSInternal_Set: Set NSS pin internally +* - SSP_NSSInternal_Reset: Reset NSS pin internally +* Output : None +* Return : None +*******************************************************************************/ +void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState) +{ + if(SSP_NSSState == SSP_NSSInternal_Set) + { + /* Set NSS pin internally */ + SSPx->CR1 |= SSP_NSSInternal_Set; + } + else + { + /* Reset NSS pin internally */ + SSPx->CR1 &= SSP_NSSInternal_Reset; + } +} + +/******************************************************************************* +* Function Name : SSP_GetFlagStatus +* Description : Checks whether the specified SSP flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: specifies the flag to check. This parameter can +* be one of the following values: +* - SSP_FLAG_Busy: busy flag +* - SSP_FLAG_RxFifoFull: Receive FIFO full flag +* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag +* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag +* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag +* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag +* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : The new state of SSP_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u32 SSPReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the SSP register index */ + SSPReg = SSP_FLAG >> 5; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Find the register of the flag to check */ + if(SSPReg == 1) + { + /* The flag to check is in SR register */ + StatusReg = SSPx->SR; + } + else if (SSPReg == 2) + { + /* The flag to check is in RISR register */ + StatusReg = SSPx->RISR; + } + + /* Check the status of the specified SSP flag */ + if((StatusReg & (1 << FlagPos)) != RESET) + { + /* Return SET if the SSP flag is set */ + return SET; + } + else + { + /* Return RESET if the SSP flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearFlag +* Description : Clears the SSPx’s pending flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: specifies the flag to clear. This parameter can +* be one of the following values: +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Clear the selected SSP flag */ + SSPx->ICR = (1 << FlagPos); +} + +/******************************************************************************* +* Function Name : SSP_GetITStatus +* Description : Checks whether the specified SSP interrupt has occurred or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : The new state of SSP_IT(SET or RESET). +*******************************************************************************/ +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Check the status of the specified interrupt flag */ + if((SSPx->MISR & SSP_IT) != RESET) + { + /* Return SET if the SSP interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if SSP interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearITPendingBit +* Description : Clears the SSPx’s interrupt pending bits. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Clear the selected SSP interrupts pending bits */ + SSPx->ICR = SSP_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c new file mode 100644 index 0000000000..4f461f997b --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c @@ -0,0 +1,425 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tb.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the TB software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_tb.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#define TB_IT_Enable_Mask 0x7FFF +#define TB_IT_Clear_Mask 0x7FFF +#define TB_IC_Enable 0x0004 +#define TB_ICPolarity_Set 0x0008 +#define TB_ICPolarity_Reset 0xFFF7 +#define TB_UFS_Reset 0xFFFE +#define TB_UFS_Set 0x0001 + +/* TB debug state */ +#define TB_DBGC_Set 0x0400 +#define TB_DBGC_Reset 0xFB7F + +/* TB counter state */ +#define TB_COUNTER_Reset 0x0002 +#define TB_COUNTER_Start 0x0004 +#define TB_COUNTER_Stop 0xFFFB + +#define TB_SMS_EXTCLK_Set 0x0008 +#define TB_SMS_RESETCLK_Set 0x0000 + +/* TB Slave Mode Enable Set/Reset value */ +#define TB_SME_Reset 0x731B +#define TB_SME_Set 0x0004 + +/* TB Trigger Selection value */ +#define TB_TS_IC1_Set 0x0200 + +/* TB SCR Masks bit */ +#define TB_SlaveModeSelection_Mask 0x7307 +#define TB_TriggerSelection_Mask 0x701F + +/* Reset Register Masks */ +#define TB_Prescaler_Reset_Mask 0x0000 +#define TB_CounterMode_Mask 0xFF8F +#define TB_AutoReload_Reset_Mask 0xFFFF + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /****************************************************************************** +* Function Name : TB_DeInit +* Description : Deinitializes the TB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_DeInit(void) +{ + /* Enters and exits the TB peripheral to and from reset */ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,DISABLE); +} + +/******************************************************************************* +* Function Name : TB_Init +* Description : Initializes TB peripheral according to the specified +* parameters in the TB_InitStruct. +* Input : TB_InitStruct: pointer to a TB_InitTypeDef structure that +* contains the configuration information for the TB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TB_Init(TB_InitTypeDef* TB_InitStruct) +{ + /* Set the TB prescaler value */ + TB->PSC = TB_InitStruct->TB_Prescaler; + + /* Set the TB period value */ + TB->ARR = TB_InitStruct->TB_AutoReload; + + /* Set the corresponding counter mode */ + TB->CR = (TB->CR & TB_CounterMode_Mask) | TB_InitStruct->TB_CounterMode; + + /* Set the corresponding clock source */ + if(TB_InitStruct->TB_ClockSource == TB_ClockSource_CKRTC) + { + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SMS_EXTCLK_Set | TB_SME_Set | TB_TS_IC1_Set; + } + else + { + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + } + + if(TB_InitStruct->TB_Mode == TB_Mode_IC) + { + /* Set the corresponding value in TB SCR register */ + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SMS_RESETCLK_Set | TB_SME_Set | TB_TS_IC1_Set; + + /* Set the IC1 enable bit */ + TB->IMCR |= TB_IC_Enable; + + /* Set the input signal polarity */ + if (TB_InitStruct->TB_ICAPolarity == TB_ICAPolarity_Falling) + { + TB->IMCR |= TB_ICPolarity_Set; + } + else + { + TB->IMCR &= TB_ICPolarity_Reset; + } + } +} + +/******************************************************************************* +* Function Name : TB_StructInit +* Description : Fills each TB_InitStruct member with its default value +* Input : TB_InitStruct : pointer to a TB_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TB_StructInit(TB_InitTypeDef *TB_InitStruct) +{ + TB_InitStruct->TB_Mode = TB_Mode_Timing; + TB_InitStruct->TB_ClockSource = TB_ClockSource_CKTIM; + TB_InitStruct->TB_CounterMode = TB_CounterMode_Up; + TB_InitStruct->TB_ICAPolarity = TB_ICAPolarity_Rising; + TB_InitStruct->TB_Prescaler = TB_Prescaler_Reset_Mask; + TB_InitStruct->TB_AutoReload = TB_AutoReload_Reset_Mask; +} + +/******************************************************************************* +* Function Name : TB_Cmd +* Description : Enables or disables the TB peripheral. +* Input : Newstate: new state of the TB peripheral. This parameter can +* be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_Cmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TB->CR |= TB_COUNTER_Start; + } + else + { + TB->CR &= TB_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : TB_ITConfig +* Description : Enables or disables the specified TB interrupt. +* Input : - TB_IT: specifies the TB interrupt sources to be enabled or +* disabled. +* This parameter can be any combination of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* - Newstate: new state of the specified TB interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_ITConfig(u16 TB_IT, FunctionalState Newstate) +{ + u16 TB_IT_Enable = 0; + + TB_IT_Enable = TB_IT & TB_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if ((TB_IT & TB_IT_GlobalUpdate) == TB_IT_GlobalUpdate) + { + TB->CR &= TB_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if ((TB_IT & TB_IT_Update) == TB_IT_Update) + { + TB->CR |= TB_UFS_Set; + } + /* Select and enable the interrupts requests */ + TB->RSR |= TB_IT_Enable; + TB->RER |= TB_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + TB->RSR &= ~TB_IT_Enable; + TB->RER &= ~TB_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : TB_SetPrescaler +* Description : Sets the TB Prescaler value. +* Input : Prescaler: specifies the TB Prescaler value. +* Output : None +* Return : None +*******************************************************************************/ +void TB_SetPrescaler(u16 Prescaler) +{ + /* Sets the prescaler value */ + TB->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : TB_ResetCounter +* Description : Re-intializes the counter and generates an update of the +* registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_ResetCounter(void) +{ + /* Re-intializes TB counter */ + TB->CR |= TB_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : TB_DebugCmd +* Description : Enables or disables TB peripheral Debug control. +* Input : Newstate: new state of the TB Debug control. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_DebugCmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TB->CR |= TB_DBGC_Set; + } + else + { + TB->CR &= TB_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : TB_CounterModeConfig +* Description : Configures the TB Counter Mode. +* Input : TB_CounterMode: specifies the TB counter mode to be used. +* This parameter can be one of the following values: +* - TB_CounterMode_Up: TB Up Counting Mode +* - TB_CounterMode_Down: TB Down Counting Mode +* - TB_CounterMode_CenterAligned: TB Center Aligned Mode +* Output : None +* Return : None +*******************************************************************************/ +void TB_CounterModeConfig(u16 TB_CounterMode) +{ + /* Counter mode configuration */ + TB->CR &= TB_CounterMode_Mask; + TB->CR |= TB_CounterMode; +} + +/******************************************************************************* +* Function Name : TB_SLaveModeConfig +* Description : Configures the TB slave Mode. +* Input : TB_SMSMode: specifies the TB slave mode to be used. +* This parameter can be one of the following values: +* - TB_SMSMode_Trigger: The counter starts at a rising +* edge of the trigger +* - TB_SMSMode_Gated: The counter clock is enabled when +* trigger signal is high +* - TB_SMSMode_External: The rising edge of selected trigger +* clocks the counter +* - TB_SMSMode_Reset: The rising edge of the selected +* trigger signal resets the counter +* Output : None +* Return : None +*******************************************************************************/ +void TB_SLaveModeConfig(u16 TB_SMSMode) +{ + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SME_Set | TB_SMSMode | TB_TS_IC1_Set; +} +/******************************************************************************* +* Function Name : TB_GetCounter +* Description : Gets the TB Counter value. +* Input : None +* Output : None +* Return : The TB counter register value. +*******************************************************************************/ +u16 TB_GetCounter(void) +{ + return TB->CNT; +} + +/******************************************************************************* +* Function Name : TB_GetICAP1 +* Description : Gets the TB Input capture value. +* Input : None +* Output : None +* Return : The TB ICR1 register value. +*******************************************************************************/ +u16 TB_GetICAP1(void) +{ + return TB->ICR1; +} + +/******************************************************************************* +* Function Name : TB_SetCounter +* Description : Sets the TB Counter value. +* Input : Counter: specifies the TB Counter value. +* Output : None +* Return : None +*******************************************************************************/ +void TB_SetCounter(u16 Counter) +{ + TB->CNT = Counter; +} + +/******************************************************************************* +* Function Name : TB_GetFlagStatus +* Description : Checks whether the specified TB flag is set or not. +* Input : TB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TB_FLAG_IC: TB Input Capture flag +* - TB_FLAG_Update: TB update flag +* Output : None +* Return : The new state of the TB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TB_GetFlagStatus(u16 TB_FLAG) +{ + if((TB->ISR & TB_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TB_ClearFlag +* Description : Clears the TB’s pending flags. +* Input : TB_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - TB_FLAG_IC: TB Input Capture flag +* - TB_FLAG_Update: TB update flag +* Output : None +* Return : None +*******************************************************************************/ +void TB_ClearFlag(u16 TB_FLAG) +{ + /* Clears the flags */ + TB->ISR &= ~TB_FLAG; +} + +/******************************************************************************* +* Function Name : TB_GetITStatus +* Description : Checks whether the specified TB interrupt has occurred or not. +* Input : TB_IT: specifies the interrupt to check. +* This parameter can be one of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* Output : None +* Return : The new state of the TB_IT (SET or RESET). +*******************************************************************************/ +ITStatus TB_GetITStatus(u16 TB_IT) +{ + u16 TB_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + TB_IT_Check = TB_IT & TB_IT_Clear_Mask; + + if((TB->ISR & TB_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TB_ClearITPendingBit +* Description : Clears the TB's interrupt pending bits. +* Input : TB_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* Output : None +* Return : None +*******************************************************************************/ +void TB_ClearITPendingBit(u16 TB_IT) +{ + u16 TB_IT_Clear = 0; + + /* Calculates the pending bits to be cleared */ + TB_IT_Clear = TB_IT & TB_IT_Clear_Mask; + + /* Clears the pending bits */ + TB->ISR &= ~TB_IT_Clear; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c new file mode 100644 index 0000000000..d23d97965a --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c @@ -0,0 +1,1360 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tim.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_tim.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* TIM interrupt masks */ +#define TIM_IT_Clear_Mask 0x7FFF +#define TIM_IT_Enable_Mask 0x7FFF + +/* TIM Input Capture Selection Set/Reset */ +#define TIM_IC1S_Set 0x0001 +#define TIM_IC1S_Reset 0x003E + +/* TIM Input Capture Selection Set/Reset */ +#define TIM_IC2S_Set 0x0002 +#define TIM_IC2S_Reset 0x003D + +/* TIM_SCR Masks bit */ +#define TIM_Encoder_Mask 0x731C +#define TIM_SlaveModeSelection_Mask 0x7307 +#define TIM_TriggerSelection_Mask 0x701F +#define TIM_InternalTriggerSelection_Mask 0x031F + +/* TIM Encoder mode Set value */ +#define TIM_Encoder1_Set 0x0001 +#define TIM_Encoder2_Set 0x0002 +#define TIM_Encoder3_Set 0x0003 + +/* TIM Slave Mode Enable Set/Reset value */ +#define TIM_SME_Reset 0x731B +#define TIM_SME_Set 0x0004 + +/* TIM Internal Trigger Selection value */ +#define TIM_ITS_TIM0 0x1000 +#define TIM_ITS_TIM1 0x2000 +#define TIM_ITS_TIM2 0x3000 +#define TIM_ITS_PWM 0x4000 + +/* TIM Trigger Selection value */ +#define TIM_TS_IC1_Set 0x0200 +#define TIM_TS_IC2_Set 0x0300 + +/* TIM Slave Mode selction external clock Set value */ +#define TIM_SMS_EXTCLK_Set 0x0008 +#define TIM_SMS_RESETCLK_Set 0x0000 + +/* TIM_CR Masks bit */ +#define TIM_DBASE_Mask 0x077F +#define TIM_MasterModeSelection_Mask 0xFC7F +#define TIM_CounterMode_Mask 0xFF8F + +/* TIM Update flag selection Set/Reset value */ +#define TIM_UFS_Reset 0xFFFE +#define TIM_UFS_Set 0x0001 + +/* TIM Counter value */ +#define TIM_COUNTER_Reset 0x0002 +#define TIM_COUNTER_Start 0x0004 +#define TIM_COUNTER_Stop 0xFFFB + +/* TIM One pulse Mode set value */ +#define TIM_OPM_Set 0x0008 +#define TIM_OPM_Reset 0xFFF7 + +/* TIM Debug Mode Set/Reset value */ +#define TIM_DBGC_Set 0x0400 +#define TIM_DBGC_Reset 0xFB7F + +/* TIM Input Capture Enable/Disable value */ +#define TIM_IC1_Enable 0x0004 +#define TIM_IC2_Enable 0x0010 + +/* TIM Input Capture Polarity Set/Reset value */ +#define TIM_IC1P_Set 0x0008 +#define TIM_IC2P_Set 0x0020 +#define TIM_IC1P_Reset 0x0037 +#define TIM_IC2P_Reset 0x001F + +/* TIM Output Compare Polarity Set/Reset value */ +#define TIM_OC1P_Set 0x0020 +#define TIM_OC2P_Set 0x2000 +#define TIM_OC1P_Reset 0x3F1F +#define TIM_OC2P_Reset 0x1F3F + +/* TIM Output Compare control mode constant */ +#define TIM_OCControl_PWM 0x000C +#define TIM_OCControl_OCToggle 0x0006 +#define TIM_OCControl_OCInactive 0x0004 +#define TIM_OCControl_OCActive 0x0002 +#define TIM_OCControl_OCTiming 0x0000 + +/* TIM Output Compare mode Enable value */ +#define TIM_OC1_Enable 0x0010 +#define TIM_OC2_Enable 0x1000 + +/* TIM Output Compare mode Mask value */ +#define TIM_OC1C_Mask 0x3F31 +#define TIM_OC2C_Mask 0x313F + +/* TIM Preload bit Set/Reset value */ +#define TIM_PLD1_Set 0x0001 +#define TIM_PLD1_Reset 0xFFFE + +#define TIM_PLD2_Set 0x0100 +#define TIM_PLD2_Reset 0xFEFF + +/* TIM OCRM Set/Reset value */ +#define TIM_OCRM_Set 0x0080 +#define TIM_OCRM_Reset 0x030D + +/* Reset Register Masks */ +#define TIM_Pulse2_Reset_Mask 0x0000 +#define TIM_Prescaler_Reset_Mask 0x0000 +#define TIM_Pulse1_Reset_Mask 0x0000 +#define TIM_Period_Reset_Mask 0xFFFF +#define TIM_Counter_Reset 0x0002 + +/* Private function prototypes -----------------------------------------------*/ +static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); + +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : TIM_DeInit +* Description : Deinitializes TIM peripheral registers to their default reset +* values. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM0) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE); + } + else if(TIMx == TIM1) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE); + } + else if(TIMx == TIM2) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_InitStruct . +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + /* Set the prescaler value */ + TIMx->PSC = TIM_InitStruct->TIM_Prescaler; + + /* Select the clock source */ + TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource, + TIM_InitStruct->TIM_ExtCLKEdge); + + /* Select the counter mode */ + TIMx->CR &= TIM_CounterMode_Mask; + TIMx->CR |= TIM_InitStruct->TIM_CounterMode; + + /* Set the period value */ + TIMx->ARR = TIM_InitStruct->TIM_Period; + + switch(TIM_InitStruct->TIM_Mode) + { + case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive: + case TIM_Mode_OCToggle: case TIM_Mode_PWM: + OCM_ModuleConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_PWMI: case TIM_Mode_IC: + ICAP_ModuleConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3: + Encoder_ModeConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active: + + /* Output module configuration */ + OCM_ModuleConfig(TIMx, TIM_InitStruct); + + /* Input module configuration */ + ICAP_ModuleConfig(TIMx, TIM_InitStruct); + + /* Set the slave mode to trigger Mode */ + TIMx->SCR |= TIM_SynchroMode_Trigger; + + /* Repetitive pulse state selection */ + if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable) + { + TIMx->CR |= TIM_OPM_Set; + } + else + { + TIMx->CR &= TIM_OPM_Reset; + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills each TIM_InitStruct member with its default value. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming; + TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; + TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal; + TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising; + TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask; + TIM_InitStruct->TIM_Channel = TIM_Channel_ALL; + TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask; + TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask; + TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable; + TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low; + TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low; + TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1; + TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1; + TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising; + TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising; + TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1; + TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIMx->CR |= TIM_COUNTER_Start; + } + else + { + TIMx->CR &= TIM_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the TIM interrupts. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt +* - TIM_IT_OC1: Output Compare 1 Interrupt +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_GlobalUpdate: Timer global update Interrupt +* - TIM_IT_IC2: Input Capture 2 Interrupt +* - TIM_IT_OC2: Output Compare 2 Interrupt +* - Newstate: new state of the specified TIMx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate) +{ + u16 TIM_IT_Enable = 0; + + TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate) + { + TIMx->CR &= TIM_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update) + { + TIMx->CR |= TIM_UFS_Set; + } + /* Select and enable the interrupts requests */ + TIMx->RSR |= TIM_IT_Enable; + TIMx->RER |= TIM_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + TIMx->RSR &= ~TIM_IT_Enable; + TIMx->RER &= ~TIM_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : TIM_PreloadConfig +* Description : Enables or disables TIM peripheral Preload register on OCRx. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 is used +* - TIM_Channel_2: TIM Channel 2 is used +* - TIM_Channel_ALL: TIM Channel 1and 2 are used +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + switch (TIM_Channel) + { + case TIM_Channel_1: + TIMx->OMR1 |= TIM_PLD1_Set; + break; + + case TIM_Channel_2: + TIMx->OMR1 |= TIM_PLD2_Set; + break; + + case TIM_Channel_ALL: + TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set; + break; + + default: + break; + } + } + else + { + switch (TIM_Channel) + { + case TIM_Channel_1: + TIMx->OMR1 &= TIM_PLD1_Reset; + break; + + case TIM_Channel_2: + TIMx->OMR1 &= TIM_PLD2_Reset; + break; + + case TIM_Channel_ALL: + TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset; + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIM0’s DMA interface. +* Input : - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMASource_OC1: Output Compare 1 DMA source +* - TIM_DMASource_OC2: Output Compare 2 DMA source +* - TIM_DMASource_IC1: Input Capture 1 DMA source +* - TIM_DMASource_IC2: Input Capture 2 DMA source +* - TIM_DMASource_Update: Timer Update DMA source +* - TIM_OCRMState: the state of output compare request mode. +* This parameter can be one of the following values: +* - TIM_OCRMState_Enable +* - TIM_OCRMState_Disable +* - TIM_DMABase:DMA Base address. +* This parameter can be one of the following values: +* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR, +* TIM_DMABase_OMR1, TIM_DMABase_RSR, +* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT, +* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1, +* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase) +{ + /* Select the DMA requests */ + TIM0->RSR &= TIM_DMASources; + + /* Set the OCRM state */ + if(TIM_OCRMState == TIM_OCRMState_Enable) + { + TIM0->RSR |= TIM_OCRM_Set; + } + else + { + TIM0->RSR &= TIM_OCRM_Reset; + } + + /* Set the DMA Base address */ + TIM0->CR &= TIM_DBASE_Mask; + TIM0->CR |= TIM_DMABase; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIM0’s DMA interface. +* Input : - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMASource_OC1: Output Compare 1 DMA source +* - TIM_DMASource_OC2: Output Compare 2 DMA source +* - TIM_DMASource_IC1: Input Capture 1 DMA source +* - TIM_DMASource_IC2: Input Capture 2 DMA source +* - TIM_DMASource_Update: Timer Update DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIM0->RER |= TIM_DMASources; + } + else + { + TIM0->RER &= ~TIM_DMASources; + } +} + +/******************************************************************************* +* Function Name : TIM_ClockSourceConfig +* Description : Configures the TIM clock source. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_ClockSource: specifies the TIM clock source to be +* selected. +* This parameter can be one of the following values: +* - TIM_ClockSource_Internal: CK_TIM internal clock +* - TIM_ClockSource_TI11: External input pin TI1 +* connected to IC1 channel. +* - TIM_ClockSource_TI12: External input pin TI1 +* connected to IC2 channel. +* - TIM_ClockSource_TI22: External input pin TI2 +* connected to IC2 channel. +* - TIM_ClockSource_TI21: External input pin TI2 +* connected to IC1 channel. +* - TIM_ExtCLKEdge: specifies the External input signal edge. +* This parameter can be one of the following values: +* - TIM_ExtCLKEdge_Falling : Falling edge selected. +* - TIM_ExtCLKEdge_Rising : Rising edge selected. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, + u16 TIM_ExtCLKEdge) +{ + if(TIM_ClockSource == TIM_ClockSource_Internal) + { + /* CK_TIM is used as clock source */ + TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; + } + else + /* Input Captures are used as TIM external clock */ + { + TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; + TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set; + + if((TIM_ClockSource == TIM_ClockSource_TI11) || + (TIM_ClockSource == TIM_ClockSource_TI21)) + /* Input Capture 1 is selected */ + { + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable; + TIMx->SCR |= TIM_TS_IC1_Set; + + if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) + /* Set the corresponding polarity */ + { + TIMx->IMCR |= TIM_IC1P_Set; + } + else + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + if(TIM_ClockSource == TIM_ClockSource_TI11) + { + /* External signal TI1 connected to IC1 channel */ + TIMx->IMCR &= TIM_IC1S_Reset; + } + else + { + /* External signal TI2 connected to IC1 channel */ + TIMx->IMCR |= TIM_IC1S_Set; + } + } + else + /* Input Capture 2 is selected */ + { + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC2_Enable; + TIMx->SCR |= TIM_TS_IC2_Set; + + if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) + /* Set the corresponding polarity */ + { + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR &= TIM_IC2P_Reset; + } + if(TIM_ClockSource == TIM_ClockSource_TI22) + { + /* External signal TI2 connected to IC2 channel */ + TIMx->IMCR &= TIM_IC2S_Reset; + } + else + { + /* External signal TI1 connected to IC2 channel */ + TIMx->IMCR |= TIM_IC2S_Set; + } + } + } +} + +/******************************************************************************* +* Function Name : TIM_SetPrescaler +* Description : Sets the TIM prescaler value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Prescaler: TIM prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler) +{ + TIMx->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : TIM_SetPeriod +* Description : Sets the TIM period value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Period: TIM period new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period) +{ + TIMx->ARR = Period; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : Sets the TIM pulse value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 is used +* - TIM_Channel_2: TIM Channel 2 is used +* - TIM_Channel_ALL: TIM Channel 1and 2 are used +* - Pulse: TIM pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse) +{ + /* Set Channel 1 pulse value */ + if(TIM_Channel == TIM_Channel_1) + { + TIMx->OCR1 = Pulse; + } + /* Set Channel 2 pulse value */ + else if(TIM_Channel == TIM_Channel_2) + { + TIMx->OCR2 = Pulse; + } + /* Set Channel 1 and Channel 2 pulse values */ + else if(TIM_Channel == TIM_Channel_ALL) + { + TIMx->OCR1 = Pulse; + TIMx->OCR2 = Pulse; + } +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1 +* Description : Gets the Input Capture 1 value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 1 Register value. +*******************************************************************************/ +u16 TIM_GetICAP1(TIM_TypeDef *TIMx) +{ + return TIMx->ICR1; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2 +* Description : Gets the Input Capture 2 value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 2 Register value +*******************************************************************************/ +u16 TIM_GetICAP2(TIM_TypeDef *TIMx) +{ + return TIMx->ICR2; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : Gets the PWM Input pulse value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 2 Register value +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->ICR2; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : Gets the PWM Input period value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 1 Register value +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->ICR1; +} + +/******************************************************************************* +* Function Name : TIM_DebugCmd +* Description : Enables or disables the specified TIM peripheral Debug control. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Newstate: new state of the TIMx Debug control. + This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIMx->CR |= TIM_DBGC_Set; + } + else + { + TIMx->CR &= TIM_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the Counter Mode to be used. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + /* Counter mode configuration */ + TIMx->CR &= TIM_CounterMode_Mask; + TIMx->CR |= TIM_CounterMode; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOCConfig +* Description : Forces the TIM output waveform to active or inactive level. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: Timer Channel 1 is used +* - TIM_Channel_2: Timer Channel 2 is used +* - TIM_Channel_ALL: Timer Channel 1 and 2 are used +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OCxREF +* - TIM_ForcedAction_InActive: Force inactive level on +* OCxREF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction) +{ + /* Channel 1 Forced Output Compare mode configuration */ + if(TIM_Channel == TIM_Channel_1) + { + TIMx->OMR1 &= TIM_OC1C_Mask; + TIMx->OMR1 |= TIM_ForcedAction; + } + /* Channel 2 Forced Output Compare mode configuration */ + else + { + if(TIM_Channel == TIM_Channel_2) + { + TIMx->OMR1 &= TIM_OC2C_Mask; + TIMx->OMR1 |= (TIM_ForcedAction<<8); + } + /* Channel 1 and Channel 2 Forced Output Compare mode configuration */ + else + { + TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8); + } + } +} + +/******************************************************************************* +* Function Name : TIM_ResetCounter +* Description : Re-intializes the TIM counter and generates an update of the +* registers. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ResetCounter(TIM_TypeDef* TIMx) +{ + /* Re-intialize the TIM counter */ + TIMx->CR |= TIM_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : TIM_SynchroConfig +* Description : Synchronizes two Timers in a specified mode. +* Input : - Master: specifies the peripheral master. +* This parameter can be one of the following values: +* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master. +* - Slave: specifies the peripheral slave. +* This parameter can be one of the following values: +* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave. +* - TIM_SynchroAction: specifies the synchronization Action to +* be used. +* This parameter can be one of the following values: +* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO +* - TIM_SynchroAction_Update: The Update event is used as TRGO +* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO +* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO +* - TIM_SynchroMode: specifies the synchronization Mode to be used. +* This parameter can be one of the following values: +* - TIM_SynchroMode_Gated: Both start and stop of the +* counter is controlled. +* - TIM_SynchroMode_Trigger: Only the start of the +* counter is controlled. +* - TIM_SynchroMode_External: The rising edge of selected trigger +* clocks the counter. +* - TIM_SynchroMode_Reset: The rising edge of the selected trigger +* signal resets the counter and generates an update of the registers. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, + u16 TIM_SynchroAction, u16 TIM_SynchroMode) +{ + switch (Slave) + { + case PWM_Slave: + { + PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + PWM->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == TIM1_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM0_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM0_Slave: + { + TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + + else if(Master == TIM1_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM1_Slave: + { + + TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + else if(Master == TIM0_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM2_Slave: + { + + TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + + else if(Master == TIM1_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM0_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIM flag is set or not. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture 1 Flag +* - TIM_FLAG_OC1: Output Compare 1 Flag +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_IC2: Input Capture 2 Flag +* - TIM_FLAG_OC2: Output Compare 2 Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + if((TIMx->ISR & TIM_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_IC1: Timer Input Capture 1 flag +* - TIM_FLAG_OC1: Timer Output Compare 1 flag +* - TIM_FLAG_Update: Timer update flag +* - TIM_FLAG_IC2: Timer Input Capture 2 flag +* - TIM_FLAG_OC2: Timer Output Compare 2 flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Clear the flags */ + TIMx->ISR &= ~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the specified TIM interrupt has occurred or not. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 interrupt +* - TIM_IT_OC1: Output Compare 1 interrupt +* - TIM_IT_Update: Timer update interrupt +* - TIM_IT_GlobalUpdate: Timer global update interrupt +* - TIM_IT_IC2: Input Capture 2 interrupt +* - TIM_IT_OC2: Output Compare 2 interrupt +* Output : None +* Return : The new state of TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + u16 TIM_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask; + + if((TIMx->ISR & TIM_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIM's interrupt pending bits. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt +* - TIM_IT_OC1: Output Compare 1 Interrupt +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_GlobalUpdate: Timer global update Interrupt +* - TIM_IT_IC2: Input Capture 2 Interrupt +* - TIM_IT_OC2: Output Compare 2 Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + u16 TIM_IT_Clear = 0; + + /* Calculate the pending bits to be cleared */ + TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask; + + /* Clear the pending bits */ + TIMx->ISR &= ~TIM_IT_Clear; +} + +/******************************************************************************* +* Function Name : OCM_ModuleConfig +* Description : Output Compare Module configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + u16 TIM_OCControl = 0x0000; + + if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming) + { + TIM_OCControl = TIM_OCControl_OCTiming; + } + else + { + if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) || + (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active)) + { + TIM_OCControl = TIM_OCControl_OCActive; + } + else + { + if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive) + { + TIM_OCControl = TIM_OCControl_OCInactive; + } + else + { + if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) || + (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle)) + { + TIM_OCControl = TIM_OCControl_OCToggle; + } + else + { + TIM_OCControl = TIM_OCControl_PWM; + + } + } + } + } + + if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) + { + /* Configure Channel 1 on Output Compare mode */ + TIMx->OMR1 &= TIM_OC1C_Mask; + TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable; + TIMx->OMR1 |= TIM_PLD1_Set; + TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; + + /* Set the OC1 wave polarity */ + if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) + { + TIMx->OMR1 |= TIM_OC1P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC1P_Reset; + } + } + else + { + if(TIM_InitStruct->TIM_Channel == TIM_Channel_2) + { + /* Configure Channel 2 on Output Compare mode */ + TIMx->OMR1 &= TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable; + TIMx->OMR1 |= TIM_PLD2_Set; + TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; + + /* Set the OCB wave polarity */ + if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) + { + TIMx->OMR1 |= TIM_OC2P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC2P_Reset; + } + } + /* Configure Channel 1 and Channel 2 on Output Compare mode */ + else + { + TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable| + TIM_PLD1_Set|TIM_PLD2_Set; + + TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; + TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; + + /* Set the OC1 wave polarity */ + if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) + { + TIMx->OMR1 |= TIM_OC1P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC1P_Reset; + } + + /* Set the OC2 wave polarity */ + if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) + { + TIMx->OMR1 |= TIM_OC2P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC2P_Reset; + } + } + } +} + +/******************************************************************************* +* Function Name : ICAP_ModuleConfig +* Description : Input Capture Module configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI) + { /* PWM input mode configuration */ + TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 1 and channel 2 input selection */ + if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1) + { + TIMx->IMCR &= TIM_IC1S_Reset; + TIMx->IMCR |= TIM_IC2S_Set; + } + else + { + TIMx->IMCR |= TIM_IC1S_Set; + TIMx->IMCR &= TIM_IC2S_Reset; + } + + /* Channel polarity */ + if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising) + { + TIMx->IMCR &= TIM_IC1P_Reset; + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR |= TIM_IC1P_Set; + TIMx->IMCR &= TIM_IC2P_Reset; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable; + } + else + { + if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) + { + /* Input Capture 1 mode configuration */ + TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask; + TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 1 input selection */ + if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1) + { + TIMx->IMCR &= TIM_IC1S_Reset; + } + else + { + TIMx->IMCR |= TIM_IC1S_Set; + } + /* Channel 1 polarity */ + if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising) + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + else + { + TIMx->IMCR |= TIM_IC1P_Set; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable; + } + else + { + /* Input Capture 2 mode configuration */ + TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask); + TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 2 input selection */ + if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2) + { + TIMx->IMCR &= TIM_IC2S_Reset; + } + else + { + TIMx->IMCR |= TIM_IC2S_Set; + } + + /* Channel 2 polarity */ + if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising) + { + TIMx->IMCR &= TIM_IC2P_Reset; + } + else + { + TIMx->IMCR |= TIM_IC2P_Set; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC2_Enable; + } + } +} + +/******************************************************************************* +* Function Name : Encoder_ModeConfig +* Description : Encoder Mode configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + /* Set Encoder mode */ + TIMx->SCR &= TIM_Encoder_Mask; + + if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1) + { + TIMx->SCR |= TIM_Encoder1_Set; + } + else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2) + { + TIMx->SCR |= TIM_Encoder2_Set; + } + else + { + TIMx->SCR |= TIM_Encoder3_Set; + } + + /* Channel 1 input selection */ + if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2) + { + TIMx->IMCR |= TIM_IC1S_Set; + } + else + { + TIMx->IMCR &= TIM_IC1S_Reset; + } + + /* Channel 2 input selection */ + if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1) + { + TIMx->IMCR |= TIM_IC2S_Set; + } + else + { + TIMx->IMCR &= TIM_IC2S_Reset; + } + + /* Channel 1 polarity */ + if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling) + { + TIMx->IMCR |= TIM_IC1P_Set; + } + else + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + + /* Channel 2 polarity */ + if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling) + { + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR &= TIM_IC2P_Reset; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c new file mode 100644 index 0000000000..5494ff3356 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c @@ -0,0 +1,599 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_uart.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_uart.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART LIN Mask */ +#define UART_LIN_Disable_Mask 0xFEFF /* LIN Disable Mask */ +#define UART_LIN_Enable_Mask 0x0100 /* LIN Enable Mask */ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F/* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080/* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_LINBreakLength_Mask 0xE1FF /* UART LIN Break Length Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask */ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTSSET_Mask 0xF7FF /* RTS signal is high */ +#define UART_RTSRESET_Mask 0x0800 /* RTS signal is low */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers to their default +* reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,DISABLE); + } + else if(UARTx == UART1) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,DISABLE); + } + else if(UARTx == UART2) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u32 APBClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + MRCC_ClocksTypeDef MRCC_ClocksStatus; + + /* Clear the WLEN bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the WLEN bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_1) + { + /* One Stop Bit */ + UARTx->LCR &= UART_StopBits_1; + } + else + { + /* Two Stop Bits */ + UARTx->LCR |= UART_StopBits_2; + } + + /* Clear SPS, EPS and PEN bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set PS, EPS and PEN bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate --------------------------------------------------*/ + /* Get the APB frequency */ + MRCC_GetClocksStatus(&MRCC_ClocksStatus); + APBClock = MRCC_ClocksStatus.PCLK_Frequency; + + /* Determine the integer part */ + IntegerDivider = ((100) * (APBClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear RTSEn and CTSEn bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set RTSEn and CTSEn bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear TXE and RXE bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set TXE and RXE bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its default value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UART0 DMA interface. +* Input : - UART0_DMAtransfer : specifies the configuration of DMA request. +* This parameter can be: +* - UART0_DMATransfer_Single: Single DMA transfer +* - UART0_DMATransfer_Burst: Burst DMA transfer +* - UART0_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART0_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART0_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError) +{ + if(UART0_DMATransfer == UART0_DMATransfer_Single) + { + /* Configure the DMA request from the UART0 as single transfer */ + UART0->DMACR &= UART0_DMATransfer_Single; + } + else + { + UART0->DMACR |= UART0_DMATransfer_Burst; + } + + if(UART0_DMAOnError == UART0_DMAOnError_Enable) + { + UART0->DMACR &= UART0_DMAOnError_Enable; + } + else + { + UART0->DMACR |= UART0_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UART0’s DMA interface. +* Input : - UART0_DMAReq: specifies the DMA request. +* This parameter can be: +* - UART0_DMAReq_Tx: Transmit DMA request +* - UART0_DMAReq_Rx: Receive DMA request +* - NewState: new state of the UART0’s DMA request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState) +{ + if(UART0_DMAReq == UART0_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UART0->DMACR |= UART0_DMAReq_Tx; + } + else + { + UART0->DMACR &= ~UART0_DMAReq_Tx; + } + } + else + { + if(NewState == ENABLE) + { + UART0->DMACR |= UART0_DMAReq_Rx; + } + else + { + UART0->DMACR &= ~UART0_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables LoopBack mode in UARTx. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx’s LoopBack mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_LINConfig +* Description : Sets the LIN break length. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - UART_LINBreakLength: Break length value. +* This parameter can be: +* - UART_LINBreakLength_10: 10 low bits +* - UART_LINBreakLength_11: 11 low bits +* - UART_LINBreakLength_12: 12 low bits +* - UART_LINBreakLength_13: 13 low bits +* - UART_LINBreakLength_14: 14 low bits +* - UART_LINBreakLength_15: 15 low bits +* - UART_LINBreakLength_16: 16 low bits +* - UART_LINBreakLength_17: 17 low bits +* - UART_LINBreakLength_18: 18 low bits +* - UART_LINBreakLength_19: 19 low bits +* - UART_LINBreakLength_20: 20 low bits +* Output : None +* Return : None +*******************************************************************************/ +void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength) +{ + /* Clear LBKLEN bits */ + UARTx->LCR &= UART_LINBreakLength_Mask; + + /* Set LBKLEN bits according to UART_LINBreakLength value */ + UARTx->LCR |= UART_LINBreakLength; +} + +/******************************************************************************* +* Function Name : UART_LINCmd +* Description : Enables or disables LIN master mode in UARTx. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx’s LIN interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the LIN mode of the specified UART */ + UARTx->LCR |= UART_LIN_Enable_Mask; + } + else + { + /* Disable the LIN mode of the specified UART */ + UARTx->LCR &= UART_LIN_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits a signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->BKR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - RTSState: new state of the RTS signal. +* This parameter can be: RTSSET or RTSRESET +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_TypeDef* UARTx, UART_RTSTypeDef RTSState) +{ + if(RTSState == RTSRESET) + { + UARTx->CR |= UART_RTSRESET_Mask; + } + else if(RTSState == RTSSET) + { + UARTx->CR &= UART_RTSSET_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s pending flags. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + /* Clear the sepecified flag */ + UARTx->RSR &= ~(1 << FlagPos); +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occurred or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR = UART_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c new file mode 100644 index 0000000000..812d627a96 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c @@ -0,0 +1,244 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_wdg.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_wdg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +#define WDG_Preload_Mask 0xFFFF +#define WDG_Prescaler_Mask 0xFF + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start_Mask 0x0002 +#define WDG_Counter_Stop_Mask 0xFFFD + +/* WDG Sequence */ +#define WDG_KeyValue1_Mask 0xA55A +#define WDG_KeyValue2_Mask 0x5AA5 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + /* Reset all the WDG registers */ + WDG->CR = 0x0000; + WDG->PR = 0x00FF; + WDG->VR = 0xFFFF; + WDG->CNT = 0xFFFF; + WDG->SR = 0x0000; + WDG->MR = 0x0000; + WDG->KR = 0x0000; +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_WDG) + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_WDG ; + } + else + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills each WDG_InitStruct member with its default value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Initialize mode */ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload = WDG_Preload_Mask ; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler = WDG_Prescaler_Mask; +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState) +{ + if((WDG->CR & WDG_Mode_WDG) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start_Mask; + } + else + { + /* Stop timer by clearing SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop_Mask; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1_Mask; + WDG->KR = WDG_KeyValue2_Mask; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the WDG End of Count(EC) interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of WDG End of Count(EC) flag (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG’s End of Count(EC) pending flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_FLAG_EC; +} + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt has +* occurred or not. +* Input : None +* Output : None +* Return : The new state of WDG End of Count(EC) interrupt (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/lnkarm_flash.xcl b/Demo/ARM7_STR75x_IAR/lnkarm_flash.xcl new file mode 100644 index 0000000000..054d9627b1 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/lnkarm_flash.xcl @@ -0,0 +1,215 @@ +/*;******************** (C) COPYRIGHT 2005 STMicroelectronics ****************** +;* File Name : lnkarm_flash.xcl +;* Author : MCD Application Team +;* Date First Issued : 03/10/2006 +;* Description : XLINK command file for EWARM/ICCARM +;* : Usage: xlink -f lnkarm +;* : -s +;******************************************************************************* +; History: +; 07/17/2006 : V1.0 +; 03/10/2006 : V0.1 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +// Embedded Flash (256/128/64Kbytes) +// The user has to change the flash memory length depending STR75xFxx devices + +// Code memory in flash +-DROMSTART=0x20000000 +-DROMEND=0x2003FFFF //0x2001FFFF;0x200FFFF + +// Data memory +-DRAMSTART=0x40000000 +-DRAMEND=0x40003FFF + + +//************************************************************************* +// ------------- +// Code segments - may be placed anywhere in memory. +// ------------- +// +// INTVEC -- Exception vector table. +// SWITAB -- Software interrupt vector table. +// ICODE -- Startup (cstartup) and exception code. +// DIFUNCT -- Dynamic initialization vectors used by C++. +// CODE -- Compiler generated code. +// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) +// CODE_ID -- Initializer for CODE_I (ROM). +// +// ------------- +// Data segments - may be placed anywhere in memory. +// ------------- +// +// CSTACK -- The stack used by C/C++ programs (system and user mode). +// IRQ_STACK -- The stack used by IRQ service routines. +// SVC_STACK -- The stack used in supervisor mode +// UND_STACK -- The stack used in Und mode +// ABT_STACK -- The stack used in Abort mode +// FIQ_STACK -- The stack used by FIQ service routines +// HEAP -- The heap used by malloc and free in C and new and +// delete in C++. +// INITTAB -- Table containing addresses and sizes of segments that +// need to be initialized at startup (by cstartup). +// CHECKSUM -- The linker places checksum byte(s) in this segment, +// when the -J linker command line option is used. +// DATA_y -- Data objects. +// +// Where _y can be one of: +// +// _AN -- Holds uninitialized located objects, i.e. objects with +// an absolute location given by the @ operator or the +// #pragma location directive. Since these segments +// contain objects which already have a fixed address, +// they should not be mentioned in this linker command +// file. +// _C -- Constants (ROM). +// _I -- Initialized data (RAM). +// _ID -- The original content of _I (copied to _I by cstartup) (ROM). +// _N -- Uninitialized data (RAM). +// _Z -- Zero initialized data (RAM). +// +// Note: Be sure to use end values for the defined address ranges. +// Otherwise, the linker may allocate space outside the +// intended memory range. +//************************************************************************* + + +//************************************************ +// Inform the linker about the CPU family used. +//************************************************ + +-carm + +//************************************************************************* +// Segment placement - General information +// +// All numbers in the segment placement command lines below are interpreted +// as hexadecimal unless they are immediately preceded by a '.', which +// denotes decimal notation. +// +// When specifying the segment placement using the -P instead of the -Z +// option, the linker is free to split each segment into its segment parts +// and randomly place these parts within the given ranges in order to +// achieve a more efficient memory usage. One disadvantage, however, is +// that it is not possible to find the start or end address (using +// the assembler operators .sfb./.sfe.) of a segment which has been split +// and reformed. +// +// When generating an output file which is to be used for programming +// external ROM/Flash devices, the -M linker option is very useful +// (see xlink.pdf for details). +//************************************************************************* + + +//************************************************************************* +// Read-only segments mapped to ROM. +//************************************************************************* + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +//************************************************ + +-Z(CODE)INTVEC=ROMSTART-ROMEND + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ + +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ + +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Original ROM location for __ramfunc code copied +// to and executed from RAM. +//************************************************ + +-Z(CONST)CODE_ID=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ + +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + + +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* + +//************************************************ +// Data segments. +//************************************************ + +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ + +-Z(DATA)CODE_I=RAMSTART-RAMEND + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// CODE_ID segment instead, but to keep symbol and +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +-QCODE_I=CODE_ID + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* + +// Add size >0 for ABT_Stack, UND_Stack if you need them. +// size must be 8 byte aligned. + +-D_CSTACK_SIZE=0x100 +-D_SVC_STACK_SIZE=0x400 +-D_IRQ_STACK_SIZE=0x400 +-D_FIQ_STACK_SIZE=0x40 +-D_ABT_STACK_SIZE=0x0 +-D_UND_STACK_SIZE=0x0 +-D_HEAP_SIZE=0x10 + +-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND +-Z(DATA)ABT_STACK+_ABT_STACK_SIZE=RAMSTART-RAMEND +-Z(DATA)UND_STACK+_UND_STACK_SIZE=RAMSTART-RAMEND +-Z(DATA)FIQ_STACK+_FIQ_STACK_SIZE=RAMSTART-RAMEND +-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND +-Z(DATA)HEAP+_HEAP_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/Demo/ARM7_STR75x_IAR/main.c b/Demo/ARM7_STR75x_IAR/main.c new file mode 100644 index 0000000000..286d0464ca --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/main.c @@ -0,0 +1,315 @@ +/* + FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * In addition to the standard demo tasks there are two tasks defined within + * this file: + * + * 1 - The check task + * The 'check' task is responsible for ensuring that all the standard demo + * tasks are executing as expected. It only executes every three seconds, but + * has the highest priority within the system so is guaranteed to get execution + * time. Any errors discovered by the check task are latched until the + * processor is reset. At the end of each cycle the check task sends either + * a pass or fail message to the 'print' task for display on the LCD. + * + * 2 - The print task + * The print task is the LCD 'gatekeeper'. That is, it is the only task that + * should access the LCD directly so is always guaranteed exclusive (and + * therefore consistent) access. The print task simply blocks on a queue + * to wait for messages from other tasks wishing to display text on the LCD. + * When a message arrives it displays its contents on the LCD then blocks to + * wait again. + */ + +/* ST includes. */ +#include "lcd.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "Queue.h" + +/* Demo application includes. */ +#include "ParTest.h" +#include "flash.h" +#include "integer.h" +#include "blocktim.h" +#include "BlockQ.h" +#include "comtest2.h" +#include "dynamic.h" + +/* Demo application task priorities. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* How often should we check the other tasks? */ +#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) + +/* The maximum offset into the pass and fail strings sent to the LCD. An +offset is used a simple method of using a different column each time a message +is written to the LCD. */ +#define mainMAX_WRITE_COLUMN ( 14 ) + +/* Baud rate used by the comtest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( 19200 ) + +/* The LED used by the comtest tasks. See the comtest.c file for more +information. */ +#define mainCOM_TEST_LED ( 3 ) + +/* The number of messages that can be queued for display on the LCD at any one +time. */ +#define mainLCD_QUEUE_LENGTH ( 2 ) + +/* The time to wait when sending to mainLCD_QUEUE_LENGTH. */ +#define mainNO_DELAY ( 0 ) + +/*-----------------------------------------------------------*/ + +/* The type that is posted to the LCD queue. */ +typedef struct LCD_MESSAGE +{ + unsigned portCHAR *pucString; /* Points to the string to be displayed. */ + unsigned portCHAR ucLine; /* The line of the LCD that should be used. */ +} LCDMessage; + +/*-----------------------------------------------------------*/ + +/* + * The task that executes at the highest priority and checks the operation of + * all the other tasks in the system. See the description at the top of the + * file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * ST provided routine to configure the processor. + */ +static void prvSetupHardware(void); + +/* + * The only task that should access the LCD. Other tasks wanting to write + * to the LCD should send a message of type LCDMessage containing the + * information to display to the print task. The print task simply blocks + * waiting for the arrival of such messages, displays the message, then blocks + * again. + */ +static void vPrintTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to communicate with the LCD print task. */ +static xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +/* Create all the demo application tasks, then start the scheduler. */ +void main( void ) +{ + /* Perform any hardware setup necessary. */ + prvSetupHardware(); + vParTestInitialise(); + + /* Create the queue used to communicate with the LCD print task. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); + + /* Create the standard demo application tasks. See the WEB documentation + for more information on these tasks. */ + vCreateBlockTimeTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartDynamicPriorityTasks(); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Create the tasks defined within this file. */ + xTaskCreate( vPrintTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + vTaskStartScheduler(); + + /* Execution will only reach here if there was insufficient heap to + start the scheduler. */ +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +static unsigned portLONG ulErrorDetected = pdFALSE; +portTickType xLastExecutionTime; +unsigned portCHAR *cErrorMessage = " FAIL"; +unsigned portCHAR *cSuccessMessage = " PASS"; +unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; +LCDMessage xMessage; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Wait until it is time for the next cycle. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); + + /* Has an error been found in any of the standard demo tasks? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + /* Calculate the LCD line on which we would like the message to + be displayed. The column variable is used for convenience as + it is incremented each cycle anyway. */ + xMessage.ucLine = ( unsigned portCHAR ) ( uxColumn & 0x01 ); + + /* The message displayed depends on whether an error was found or + not. Any discovered error is latched. Here the column variable + is used as an index into the text string as a simple way of moving + the text from column to column. */ + if( ulErrorDetected == pdFALSE ) + { + xMessage.pucString = cSuccessMessage + uxColumn; + } + else + { + xMessage.pucString = cErrorMessage + uxColumn; + } + + /* Send the message to the print task for display. */ + xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); + + /* Make sure the message is printed in a different column the next + time around. */ + uxColumn--; + if( uxColumn == 0 ) + { + uxColumn = mainMAX_WRITE_COLUMN; + } + } +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +LCDMessage xMessage; + + for( ;; ) + { + /* Wait until a message arrives. */ + while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ); + + /* The message contains the text to display, and the line on which the + text should be displayed. */ + LCD_Clear(); + LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware(void) +{ +ErrorStatus OSC4MStartUpStatus01; + + /* ST provided routine. */ + + /* MRCC system reset */ + MRCC_DeInit(); + + /* Wait for OSC4M start-up */ + OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); + + if(OSC4MStartUpStatus01 == SUCCESS) + { + /* Set HCLK to 60MHz */ + MRCC_HCLKConfig(MRCC_CKSYS_Div1); + + /* Set CKTIM to 60MHz */ + MRCC_CKTIMConfig(MRCC_HCLK_Div1); + + /* Set PCLK to 30MHz */ + MRCC_PCLKConfig(MRCC_CKTIM_Div2); + + /* Enable Flash Burst mode */ + CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable); + + /* Set CK_SYS to 60 MHz */ + MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15); + } + + /* GPIO pins optimized for 3V3 operation */ + MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3); + + /* GPIO clock source enable */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); + + /* EXTIT clock source enable */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE); + /* TB clock source enable */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE); + + /* Initialize the demonstration menu */ + LCD_Init(); + + LCD_DisplayString(Line1, "www.FreeRTOS.org", BlackText); + LCD_DisplayString(Line2, " STR750 Demo ", BlackText); + + EIC_IRQCmd(ENABLE); +} +/*-----------------------------------------------------------*/ diff --git a/Demo/ARM7_STR75x_IAR/serial/serial.c b/Demo/ARM7_STR75x_IAR/serial/serial.c new file mode 100644 index 0000000000..ab3e031f84 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/serial/serial.c @@ -0,0 +1,263 @@ +/* + FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Library includes. */ +#include "75x_uart.h" +#include "75x_gpio.h" +#include "75x_eic.h" +#include "75x_mrcc.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo application includes. */ +#include "serial.h" + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +static volatile portBASE_TYPE xQueueEmpty = pdTRUE; + +/*-----------------------------------------------------------*/ + +/* The interrupt service routine - called from the assembly entry point. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn; +UART_InitTypeDef UART_InitStructure; +GPIO_InitTypeDef GPIO_InitStructure; +EIC_IRQInitTypeDef EIC_IRQInitStructure; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + portENTER_CRITICAL(); + { + /* Enable the UART0 Clock. */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_UART0, ENABLE ); + + /* Configure the UART0_Tx as alternate function */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIO0, &GPIO_InitStructure); + + /* Configure the UART0_Rx as input floating */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIO0, &GPIO_InitStructure); + + /* Configure UART0. */ + UART_InitStructure.UART_WordLength = UART_WordLength_8D; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No; + UART_InitStructure.UART_BaudRate = ulWantedBaud; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx; + UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_Init(UART0, &UART_InitStructure); + + /* Enable the UART0 */ + UART_Cmd(UART0, ENABLE); + + /* Configure the IEC for the UART interrupts. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = UART0_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + xQueueEmpty = pdTRUE; + UART_ITConfig( UART0, UART_IT_Transmit | UART_IT_Receive, ENABLE ); + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn; + + /* Place the character in the queue of characters to be transmitted. */ + portENTER_CRITICAL(); + { + if( xQueueEmpty == pdTRUE ) + { + UART0->DR = cOutChar; + xReturn = pdPASS; + } + else + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + } + + xQueueEmpty = pdFALSE; + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +__arm void vSerialISR( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + do + { + if( UART0->MIS & UART_IT_Transmit ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + UART0->DR = cChar; + } + else + { + xQueueEmpty = pdTRUE; + } + + UART_ClearITPendingBit( UART0, UART_IT_Transmit ); + } + + if( UART0->MIS & UART_IT_Receive ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue of received + characters. */ + cChar = UART0->DR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + UART_ClearITPendingBit( UART0, UART_IT_Receive ); + } + } while( UART0->MIS ); + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); +} + + + + + + diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 0000000000..1c29a21aa5 --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,88 @@ + + + + + + + + + + + + + 158272727 + + + + + + + + 200 + + + + 100 + + 20 + 1004 + 267 + 66 + + + {W}Watch-0:TB->CR4200143100100100200 + + + + + + + TabID-22366-21915 + Debug Log + Debug-Log + + + + TabID-21843-21924 + Build + Build + + + + TabID-21385-32577 + Breakpoints + Breakpoints + + + + + 0 + + + TabID-346-21918 + Workspace + Workspace + + + RTOSDemo + + + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c01195333533300100000010000001 + + + + + + + iaridepm1debuggergui1-2-2796232-2-20000167143820988-2-21301402-2-21404132100285713580200 + + + + diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni new file mode 100644 index 0000000000..6b1ac8cf7d --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni @@ -0,0 +1,40 @@ +[JLinkDriver] +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 0000000000..775c9e17dc --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,64 @@ + + + + + + RTOSDemo/Release + + + + + + + + + 224272727 + + + + + + + 300Find-in-FilesDebug-LogBreakpoints20100426766 + + + + + 48268826300BuildDebug-LogBreakpoints + 300BuildFind-in-FilesBreakpoints + + + 100300BuildFind-in-FilesDebug-Log + + + + + + + TabID-5322-15070 + Workspace + Workspace + + + RTOSDemoRTOSDemo/sourceRTOSDemo/startup + + + + 0TabID-10308-14988BuildBuildTabID-11884-28246BreakpointsBreakpointsTabID-30248-21129Debug LogDebug-Log0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c01195333533300100000010000001 + + + + + + + iaridepm1-2-2705298-2-20000214286727366-2-22211402-2-214042231002857229424142857205761 + + + + diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par new file mode 100644 index 0000000000..88b582c54a --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par @@ -0,0 +1,17 @@ +// IAR XLINK Setup +// Autogenerated file - do not edit +% +setrangelist($evec_ADR,[0-3F]); +setrangelist($internal_ROM,[8000-FFFFF]); +setrangelist($external_ROM,[]); +setrangelist($internal_RAM,[100000-7FFFFF]); +setrangelist($external_RAM,[]); +$CSTACK_SIZE=2000; +$IRQSTACK_SIZE=400; +$HEAP_SIZE=8000; +$COMMANDS=""; +$STACK_LOCATION="Internal RAM"; +$IRQSTACK_LOCATION="Internal RAM"; +$HEAP_LOCATION="Internal RAM"; +$iar_saved_xclfilename="C:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\RTOSDemo_lnk.xcl"; +% \ No newline at end of file diff --git a/Source/include/portable.h b/Source/include/portable.h index fdf075b7d0..8b815353c9 100644 --- a/Source/include/portable.h +++ b/Source/include/portable.h @@ -109,6 +109,10 @@ #include "..\..\Source\portable\IAR\STR71x\portmacro.h" #endif +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + #ifdef STR91X_IAR #include "..\..\Source\portable\IAR\STR91x\portmacro.h" #endif diff --git a/Source/portable/IAR/STR75x/ISR_Support.h b/Source/portable/IAR/STR75x/ISR_Support.h new file mode 100644 index 0000000000..47e4c87c1e --- /dev/null +++ b/Source/portable/IAR/STR75x/ISR_Support.h @@ -0,0 +1,108 @@ +; FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. +; +; This file is part of the FreeRTOS.org distribution. +; +; FreeRTOS.org is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; FreeRTOS.org is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with FreeRTOS.org; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +; +; A special exception to the GPL can be applied should you wish to distribute +; a combined work that includes FreeRTOS.org, without being obliged to provide +; the source code for any proprietary components. See the licensing section +; of http://www.FreeRTOS.org for full details of how and when the exception +; can be applied. +; +; *************************************************************************** +; See http://www.FreeRTOS.org for documentation, latest information, license +; and contact details. Please ensure to read the configuration and relevant +; port sections of the online documentation. +; *************************************************************************** + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/Source/portable/IAR/STR75x/port.c b/Source/portable/IAR/STR75x/port.c new file mode 100644 index 0000000000..c1332df585 --- /dev/null +++ b/Source/portable/IAR/STR75x/port.c @@ -0,0 +1,241 @@ +/* + FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR75x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/* Tick interrupt routines for preemptive operation. */ +__arm void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +__arm void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + vTaskIncrementTick(); + + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + #if configUSE_PREEMPTION == 1 + vTaskSwitchContext(); + #endif + + TB_ClearITPendingBit( TB_IT_Update ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +EIC_IRQInitTypeDef EIC_IRQInitStructure; +TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1; + TB_Init(&TB_InitStructure); + + /* Enable TB Update interrupt */ + TB_ITConfig(TB_IT_Update, ENABLE); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit(TB_IT_Update); + + /* Enable TB */ + TB_Cmd(ENABLE); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/Source/portable/IAR/STR75x/portasm.s79 b/Source/portable/IAR/STR75x/portasm.s79 new file mode 100644 index 0000000000..2fefd3c665 --- /dev/null +++ b/Source/portable/IAR/STR75x/portasm.s79 @@ -0,0 +1,66 @@ +; FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. +; +; This file is part of the FreeRTOS.org distribution. +; +; FreeRTOS.org is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; FreeRTOS.org is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with FreeRTOS.org; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +; +; A special exception to the GPL can be applied should you wish to distribute +; a combined work that includes FreeRTOS.org, without being obliged to provide +; the source code for any proprietary components. See the licensing section +; of http://www.FreeRTOS.org for full details of how and when the exception +; can be applied. +; +; *************************************************************************** +; See http://www.FreeRTOS.org for documentation, latest information, license +; and contact details. Please ensure to read the configuration and relevant +; port sections of the online documentation. +; *************************************************************************** + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + + END + diff --git a/Source/portable/IAR/STR75x/portmacro.h b/Source/portable/IAR/STR75x/portmacro.h new file mode 100644 index 0000000000..c3a7422132 --- /dev/null +++ b/Source/portable/IAR/STR75x/portmacro.h @@ -0,0 +1,106 @@ +/* + FreeRTOS.org V4.1.2 - Copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics */ +#define inline + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#endif /* PORTMACRO_H */ + +