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@ -73,10 +73,6 @@ static void prvSetupRLT0Interrupt( void );
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typedef void tskTCB;
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extern volatile tskTCB * volatile pxCurrentTCB;
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING ( ( unsigned portBASE_TYPE ) 0 )
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volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
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/*-----------------------------------------------------------*/
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/*
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@ -116,11 +112,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
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__asm(" AND CCR,#H'DF "); \
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__asm(" PUSHW A "); \
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__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
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\
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/* Save the critical nesting count to the stack. */ \
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__asm(" MOVW RW0, _uxCriticalNesting "); \
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__asm(" PUSHW (RW0) "); \
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\
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__asm(" MOVW A, _pxCurrentTCB "); \
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__asm(" MOVW A, SP "); \
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__asm(" SWAPW "); \
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@ -143,13 +134,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
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__asm(" MOVW A, @A "); \
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__asm(" AND CCR,#H'DF "); \
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__asm(" MOVW SP, A "); \
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\
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/* Load the saved uxCriticalNesting value into RW0. */ \
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__asm(" POPW (RW0) "); \
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\
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/* Save the loaded value into the uxCriticalNesting variable. */ \
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__asm(" MOVW _uxCriticalNesting, RW0 "); \
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\
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__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
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__asm(" POPW A "); \
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__asm(" OR CCR,#H'20 "); \
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@ -203,11 +187,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
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__asm(" AND CCR,#H'DF "); \
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__asm(" PUSHW A "); \
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__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
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\
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/* Save the critical nesting count to the stack. */ \
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__asm(" MOVW RW0, _uxCriticalNesting "); \
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__asm(" PUSHW (RW0) "); \
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\
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__asm(" MOVL A, _pxCurrentTCB "); \
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__asm(" MOVL RL2, A "); \
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__asm(" MOVW A, SP "); \
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@ -224,13 +203,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
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__asm(" MOVW SP, A "); \
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__asm(" MOV A, @RL2+2 "); \
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__asm(" MOV USB, A "); \
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\
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/* Load the saved uxCriticalNesting value into RW0. */ \
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__asm(" POPW (RW0) "); \
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\
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/* Save the loaded value into the uxCriticalNesting variable. */ \
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__asm(" MOVW _uxCriticalNesting, RW0 "); \
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\
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__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
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__asm(" POPW A "); \
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__asm(" OR CCR,#H'20 "); \
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@ -398,11 +370,6 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1111; /* RW1 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x8888; /* RW0 */
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pxTopOfStack--;
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/* The task starts with its uxCriticalNesting variable set to 0, interrupts
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being enabled. */
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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return pxTopOfStack;
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}
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@ -554,28 +521,3 @@ __nosavereg __interrupt void vPortYieldDelayed( void )
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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/* Disable interrupts */
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portDISABLE_INTERRUPTS();
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/* Now interrupts are disabled uxCriticalNesting can be accessed
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directly. Increment uxCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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uxCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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if( uxCriticalNesting > portNO_CRITICAL_NESTING )
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{
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uxCriticalNesting--;
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if( uxCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable all interrupt/exception. */
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portENABLE_INTERRUPTS();
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}
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}
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}
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/*-----------------------------------------------------------*/
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