Update MSP430X IAR port to ensure the power settings are correct for the clock speed.
Richard Barry
13 years ago
parent
f16af5d27e
commit
3b4771e1a9
@ -0,0 +1,248 @@
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/*******************************************************************************
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*
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* HAL_PMM.c
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* Power Management Module Library for MSP430F5xx/6xx family
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*
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#include "msp430.h"
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#include "HAL_PMM.h"
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/*******************************************************************************
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* \brief Increase Vcore by one level
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*
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* \param level Level to which Vcore needs to be increased
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* \return status Success/failure
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******************************************************************************/
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static uint16_t SetVCoreUp(uint8_t level)
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{
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uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
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// The code flow for increasing the Vcore has been altered to work around
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// the erratum FLASH37.
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// Please refer to the Errata sheet to know if a specific device is affected
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// DO NOT ALTER THIS FUNCTION
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// Open PMM registers for write access
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PMMCTL0_H = 0xA5;
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// Disable dedicated Interrupts
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// Backup all registers
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PMMRIE_backup = PMMRIE;
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PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |
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SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE);
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SVSMHCTL_backup = SVSMHCTL;
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SVSMLCTL_backup = SVSMLCTL;
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// Clear flags
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PMMIFG = 0;
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// Set SVM highside to new level and check if a VCore increase is possible
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SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level);
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// Wait until SVM highside is settled
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while ((PMMIFG & SVSMHDLYIFG) == 0) ;
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// Clear flag
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PMMIFG &= ~SVSMHDLYIFG;
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// Check if a VCore increase is possible
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if ((PMMIFG & SVMHIFG) == SVMHIFG){ // -> Vcc is too low for a Vcore increase
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// recover the previous settings
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PMMIFG &= ~SVSMHDLYIFG;
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SVSMHCTL = SVSMHCTL_backup;
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// Wait until SVM highside is settled
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while ((PMMIFG & SVSMHDLYIFG) == 0) ;
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// Clear all Flags
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PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
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PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register
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PMMCTL0_H = 0x00; // Lock PMM registers for write access
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return PMM_STATUS_ERROR; // return: voltage not set
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}
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// Set also SVS highside to new level
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// Vcc is high enough for a Vcore increase
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SVSMHCTL |= (SVSHRVL0 * level);
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// Wait until SVM highside is settled
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while ((PMMIFG & SVSMHDLYIFG) == 0) ;
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// Clear flag
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PMMIFG &= ~SVSMHDLYIFG;
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// Set VCore to new level
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PMMCTL0_L = PMMCOREV0 * level;
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// Set SVM, SVS low side to new level
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SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);
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// Wait until SVM, SVS low side is settled
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while ((PMMIFG & SVSMLDLYIFG) == 0) ;
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// Clear flag
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PMMIFG &= ~SVSMLDLYIFG;
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// SVS, SVM core and high side are now set to protect for the new core level
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// Restore Low side settings
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// Clear all other bits _except_ level settings
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SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
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// Clear level settings in the backup register,keep all other bits
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SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
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// Restore low-side SVS monitor settings
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SVSMLCTL |= SVSMLCTL_backup;
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// Restore High side settings
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// Clear all other bits except level settings
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SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
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// Clear level settings in the backup register,keep all other bits
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SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
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// Restore backup
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SVSMHCTL |= SVSMHCTL_backup;
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// Wait until high side, low side settled
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while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)) ;
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// Clear all Flags
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PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
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PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register
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PMMCTL0_H = 0x00; // Lock PMM registers for write access
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return PMM_STATUS_OK;
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}
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/*******************************************************************************
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* \brief Decrease Vcore by one level
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*
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* \param level Level to which Vcore needs to be decreased
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* \return status Success/failure
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******************************************************************************/
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static uint16_t SetVCoreDown(uint8_t level)
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{
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uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
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// The code flow for decreasing the Vcore has been altered to work around
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// the erratum FLASH37.
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// Please refer to the Errata sheet to know if a specific device is affected
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// DO NOT ALTER THIS FUNCTION
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// Open PMM registers for write access
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PMMCTL0_H = 0xA5;
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// Disable dedicated Interrupts
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// Backup all registers
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PMMRIE_backup = PMMRIE;
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PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |
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SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE);
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SVSMHCTL_backup = SVSMHCTL;
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SVSMLCTL_backup = SVSMLCTL;
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// Clear flags
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PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG);
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// Set SVM, SVS high & low side to new settings in normal mode
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SVSMHCTL = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level);
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SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);
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// Wait until SVM high side and SVM low side is settled
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while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0) ;
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// Clear flags
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PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG);
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// SVS, SVM core and high side are now set to protect for the new core level
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// Set VCore to new level
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PMMCTL0_L = PMMCOREV0 * level;
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// Restore Low side settings
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// Clear all other bits _except_ level settings
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SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
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// Clear level settings in the backup register,keep all other bits
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SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
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// Restore low-side SVS monitor settings
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SVSMLCTL |= SVSMLCTL_backup;
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// Restore High side settings
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// Clear all other bits except level settings
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SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
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// Clear level settings in the backup register, keep all other bits
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SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
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// Restore backup
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SVSMHCTL |= SVSMHCTL_backup;
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// Wait until high side, low side settled
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while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)) ;
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// Clear all Flags
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PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
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PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register
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PMMCTL0_H = 0x00; // Lock PMM registers for write access
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return PMM_STATUS_OK; // Return: OK
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}
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uint16_t SetVCore(uint8_t level)
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{
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uint16_t actlevel;
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uint16_t status = 0;
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level &= PMMCOREV_3; // Set Mask for Max. level
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actlevel = (PMMCTL0 & PMMCOREV_3); // Get actual VCore
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// step by step increase or decrease
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while ((level != actlevel) && (status == 0)) {
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if (level > actlevel){
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status = SetVCoreUp(++actlevel);
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}
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else {
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status = SetVCoreDown(--actlevel);
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}
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}
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return status;
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}
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@ -0,0 +1,113 @@
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/*******************************************************************************
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*
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* HAL_PMM.h
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* Power Management Module Library for MSP430F5xx/6xx family
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*
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef HAL_PMM_H
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#define HAL_PMM_H
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#include <stdint.h>
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#include "HAL_MACROS.h"
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/*******************************************************************************
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* Macros
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******************************************************************************/
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#define ENABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00; )
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#define DISABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00; )
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#define ENABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00; )
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#define DISABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00; )
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#define ENABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00; )
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#define ENABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00; )
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#define DISABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00; )
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#define CLEAR_PMM_IFGS() st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00; )
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// These settings use SVSH/LACE = 0
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#define SVSL_ENABLED_IN_LPM_FAST_WAKE() st( \
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PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP + SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00; )
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#define SVSL_ENABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= \
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~(SVSLFP + SVSMLACE); PMMCTL0_H = 0x00; )
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#define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= \
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~(SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )
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#define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= \
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~(SVSLFP + SVSMLACE + SVSLMD); PMMCTL0_H = 0x00; )
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#define SVSH_ENABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= \
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~(SVSMHACE + SVSHFP); PMMCTL0_H = 0x00; )
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#define SVSH_ENABLED_IN_LPM_FULL_PERF() st( \
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PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD + SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00; )
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#define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= \
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~(SVSMHACE + SVSHFP + SVSHMD); PMMCTL0_H = 0x00; )
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#define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= \
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~(SVSMHACE + SVSHMD); PMMCTL0_H = 0x00; )
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// These setting use SVSH/LACE = 1
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#define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= \
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(SVSLFP + SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )
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#define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= \
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(SVSHMD + SVSHFP + SVSMHACE); PMMCTL0_H = 0x00; )
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/*******************************************************************************
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* Defines
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******************************************************************************/
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#define PMM_STATUS_OK 0
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#define PMM_STATUS_ERROR 1
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/*******************************************************************************
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* \brief Set Vcore to expected level
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*
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* \param level Level to which Vcore needs to be increased/decreased
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* \return status Success/failure
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******************************************************************************/
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extern uint16_t SetVCore(uint8_t level);
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#endif /* HAL_PMM_H */
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