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Beginnings of a project to build the GCC Cortex-A port targeting a Zynq.

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Richard Barry 11 years ago
parent 86023aa5a6
commit 33351b02c9
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FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.cproject
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<value>$%7BPARENT-4-PROJECT_LOC%7D</value>
</variable>
</variableList>
</projectDescription>

201
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h
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/*
FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/*
* The FreeRTOS Cortex-A port implements a full interrupt nesting model.
*
* Interrupts that are assigned a priority at or below
* configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM
* generic interrupt controller [GIC] means a priority that has a numerical
* value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API
* functions and will nest.
*
* Interrupts that are assigned a priority above
* configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical
* value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS
* API functions, will nest, and will not be masked by FreeRTOS critical
* sections (although it is necessary for interrupts to be globally disabled
* extremely briefly as the interrupt mask is updated in the GIC).
*
* FreeRTOS functions that can be called from an interrupt are those that end in
* "FromISR". FreeRTOS maintains a separate interrupt safe API to enable
* interrupt entry to be shorter, faster, simpler and smaller.
*
* The Zynq implements 32 unique interrupt priorities. For the purpose of
* setting configMAX_API_CALL_INTERRUPT_PRIORITY 31 represents the lowest
* priority.
*/
#define configMAX_API_CALL_INTERRUPT_PRIORITY 25
#define configCPU_CLOCK_HZ 100000000UL
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_TICKLESS_IDLE 0
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configPERIPHERAL_CLOCK_HZ ( 33333000UL )
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 160 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38912 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_QUEUE_SETS 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCallFromISR 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* The following constants describe the hardware, and are correct for the
Zynq MPU. */
#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0xE8201000
#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000
#define configUNIQUE_INTERRUPT_PRIORITIES 32
/* Run time stats gathering definitions. */
unsigned long ulGetRunTimeCounterValue( void );
void vInitialiseRunTimeStats( void );
#define configGENERATE_RUN_TIME_STATS 0
//#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats()
//#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
/* The size of the global output buffer that is available for use when there
are multiple command interpreters running at once (for example, one on a UART
and one on TCP/IP). This is done to prevent an output buffer being defined by
each implementation - which would waste RAM. In this case, there is only one
command interpreter running. */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
void vAssertCalled( const char * pcFile, unsigned long ulLine );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );
/****** Hardware specific settings. *******************************************/
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must
* be installed as the peripheral's interrupt handler.
*/
void vConfigureTickInterrupt( void );
#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
#endif /* FREERTOS_CONFIG_H */

96
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c
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/*
FreeRTOS V8.0.0:rc2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
* Simple IO routines to control the LEDs.
* This file is called ParTest.c for historic reasons. Originally it stood for
* PARallel port TEST.
*-----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo includes. */
#include "partest.h"
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
}

210
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/asm_vectors.S
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/******************************************************************************
*
* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex A9 processor
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Save lr when profiling is enabled
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#if 0
#include "xil_errata.h"
#define __ARM_NEON__ 1
.org 0
.text
.globl _boot
.globl _vector_table
.globl FIQInterrupt
.globl IRQInterrupt
.globl SWInterrupt
.globl DataAbortInterrupt
.globl PrefetchAbortInterrupt
.globl IRQHandler
.globl prof_pc
.section .vectors
_vector_table:
B _boot
B Undefined
B SVCHandler
B PrefetchAbortHandler
B DataAbortHandler
NOP /* Placeholder for address exception vector*/
B IRQHandler
B FIQHandler
IRQHandler: /* IRQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
#ifdef __ARM_NEON__
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
#ifdef PROFILING
ldr r2, =prof_pc
subs r3, lr, #0
str r3, [r2]
#endif
bl IRQInterrupt /* IRQ vector */
#ifdef __ARM_NEON__
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
FIQHandler: /* FIQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
#ifdef __ARM_NEON__
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
FIQLoop:
bl FIQInterrupt /* FIQ vector */
#ifdef __ARM_NEON__
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
Undefined: /* Undefined handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
b _prestart
movs pc, lr
SVCHandler: /* SWI handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
tst r0, #0x20 /* check the T bit */
ldrneh r0, [lr,#-2] /* Thumb mode */
bicne r0, r0, #0xff00 /* Thumb mode */
ldreq r0, [lr,#-4] /* ARM mode */
biceq r0, r0, #0xff000000 /* ARM mode */
bl SWInterrupt /* SWInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
DataAbortHandler: /* Data Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
PrefetchAbortHandler: /* Prefetch Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
.end
#endif

285
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 2013.4 EDK_2013.4.20131205 */
/* */
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x3FF00000
ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
*(.vectors)
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_0_S_AXI_BASEADDR
.init : {
KEEP (*(.init))
} > ps7_ddr_0_S_AXI_BASEADDR
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0_S_AXI_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.got : {
*(.got)
} > ps7_ddr_0_S_AXI_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0_S_AXI_BASEADDR
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0_S_AXI_BASEADDR
_end = .;
}

172
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c
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/*
FreeRTOS V8.0.0:rc2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
*
*/
/* Standard includes. */
#include <stdio.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Standard demo includes. */
#include "partest.h"
#include "TimerDemo.h"
#include "QueueOverwrite.h"
/* Xilinx includes. */
#include "platform.h"
#include "xparameters.h"
#include "xscutimer.h"
#include "xscugic.h"
#include "xil_exception.h"
int main()
{
init_platform();
print("Hello World\n\r");
return 0;
}
void vAssertCalled( const char * pcFile, unsigned long ulLine )
{
( void ) pcFile;
( void ) ulLine;
}
void vConfigureTickInterrupt( void )
{
}
static void prvSetupHardware( void )
{
Xil_ExceptionInit();
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the ARM processor.
*/
#if 0
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
(Xil_ExceptionHandler)FreeRTOS_ExHandler,
(void *)4);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
(Xil_ExceptionHandler)FreeRTOS_ExHandler,
(void *)4);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
(Xil_ExceptionHandler)FreeRTOS_ExHandler,
(void *)8);
#endif
}
void vApplicationIdleHook( void )
{
}
void vApplicationStackOverflowHook( TaskHandle_t xTask, const char * pcTaskName )
{
}
void vApplicationTickHook( void )
{
}
void vApplicationIRQHandler( uint32_t ulICCIAR )
{
uint32_t ulInterruptID;
/* Re-enable interrupts. */
__asm ( "cpsie i" );
/* The ID of the interrupt can be obtained by bitwise anding the ICCIAR value
with 0x3FF. */
ulInterruptID = ulICCIAR & 0x3FFUL;
/* Call the function installed in the array of installed handler functions. */
// intc_func_table[ ulInterruptID ]( 0 );
}

112
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/******************************************************************************
*
* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
#include "xparameters.h"
#include "xil_cache.h"
#include "platform_config.h"
/*
* Uncomment the following line if ps7 init source files are added in the
* source directory for compiling example outside of SDK.
*/
/*#include "ps7_init.h"*/
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#define UART_BAUD 9600
#endif
void
enable_caches()
{
#ifdef __PPC__
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheEnable();
#endif
#endif
}
void
disable_caches()
{
Xil_DCacheDisable();
Xil_ICacheDisable();
}
void
init_uart()
{
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
#ifdef STDOUT_IS_PS7_UART
/* Bootrom/BSP configures PS7 UART to 115200 bps */
#endif
}
void
init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment the following line and also #include "ps7_init.h" at the top.
* Make sure that the ps7_init.c and ps7_init.h files are included
* along with this example source files for compilation.
*/
/* ps7_init();*/
enable_caches();
init_uart();
}
void
cleanup_platform()
{
disable_caches();
}

27
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.h
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/*
* Copyright (c) 2008 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
*/
#ifndef __PLATFORM_H_
#define __PLATFORM_H_
#include "platform_config.h"
void init_platform();
void cleanup_platform();
#endif

10
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform_config.h
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#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define STDOUT_IS_PS7_UART
#define UART_DEVICE_ID 0
#ifdef __PPC__
#define CACHEABLE_REGION_MASK 0xff000001
#endif
#endif

120
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/*
FreeRTOS V8.0.0:rc2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART2.
***Note*** This example uses queues to send each character into an interrupt
service routine and out of an interrupt service routine individually. This
is done to demonstrate queues being used in an interrupt, and to deliberately
load the system to test the FreeRTOS port. It is *NOT* meant to be an
example of an efficient implementation. An efficient implementation should
use the DMA, and only use FreeRTOS API functions when enough has been
received to warrant a task being unblocked to process the data.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
#include "comtest2.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
return NULL;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
return 0;
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
return 0;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/

19
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?>
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1844486228">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1844486228" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.core.pathentry">
<pathentry excluding="ps7_cortexa9_0/libsrc/standalone_v3_12_a/src/asm_vectors.S" kind="src" path=""/>
<pathentry kind="out" path=""/>
</storageModule>
</cproject>

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo_bsp</name>
<comment></comment>
<projects>
<project>ZC702_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>

3
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.sdkproject
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THIRPARTY=false
PROCESSOR=ps7_cortexa9_0
MSS_FILE=system.mss

21
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile
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# Makefile generated by Xilinx SDK.
-include libgen.options
LIBRARIES = ${PROCESSOR}/lib/libxil.a
MSS = system.mss
all: libs
@echo 'Finished building libraries'
libs: $(LIBRARIES)
$(LIBRARIES): $(MSS)
libgen -hw ${HWSPEC}\
${REPOSITORIES}\
-pe ${PROCESSOR} \
-log libgen.log \
$(MSS)
clean:
rm -rf ${PROCESSOR}

20
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/libgen.log
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Release 2013.4 - libgen Xilinx EDK 2013.4 Build EDK_2013.4.20131205
(nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: libgen -hw ../ZC702_hw_platform/system.xml -pe ps7_cortexa9_0 -log
libgen.log system.mss
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=arm-xilinx-eabi-gcc"
"ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc"
"ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Running execs_generate.

3
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/libgen.options
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PROCESSOR=ps7_cortexa9_0
REPOSITORIES=
HWSPEC=../ZC702_hw_platform/system.xml

225
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss
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PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 3.12.a
PARAMETER PROC_INSTANCE = ps7_cortexa9_0
PARAMETER STDIN = ps7_uart_1
PARAMETER STDOUT = ps7_uart_1
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa9
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = ps7_cortexa9_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_afi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_afi_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_afi_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_afi_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = canps
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = ps7_can_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_coresight_comp_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_ddr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_ddrc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = devcfg
PARAMETER DRIVER_VER = 2.04.a
PARAMETER HW_INSTANCE = ps7_dev_cfg_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmaps
PARAMETER DRIVER_VER = 1.07.a
PARAMETER HW_INSTANCE = ps7_dma_ns
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmaps
PARAMETER DRIVER_VER = 1.07.a
PARAMETER HW_INSTANCE = ps7_dma_s
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emacps
PARAMETER DRIVER_VER = 1.06.a
PARAMETER HW_INSTANCE = ps7_ethernet_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_globaltimer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpiops
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = ps7_gpio_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_gpv_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
PARAMETER DRIVER_VER = 1.04.a
PARAMETER HW_INSTANCE = ps7_i2c_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_intc_dist_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_l2cachec_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_ocmc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspips
PARAMETER DRIVER_VER = 2.03.a
PARAMETER HW_INSTANCE = ps7_qspi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_qspi_linear_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_ram_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_ram_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_scuc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
PARAMETER DRIVER_VER = 1.06.a
PARAMETER HW_INSTANCE = ps7_scugic_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scutimer
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = ps7_scutimer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scuwdt
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = ps7_scuwdt_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdps
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_sd_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ps7_slcr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = ps7_ttc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
PARAMETER DRIVER_VER = 1.05.a
PARAMETER HW_INSTANCE = ps7_uart_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = usbps
PARAMETER DRIVER_VER = 1.06.a
PARAMETER HW_INSTANCE = ps7_usb_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = xadcps
PARAMETER DRIVER_VER = 1.03.a
PARAMETER HW_INSTANCE = ps7_xadc_0
END

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ZC702_hw_platform</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.hw.HwProject</nature>
</natures>
</projectDescription>

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/******************************************************************************
*
* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666666
#define DDR_FREQ 533333333
#define DCI_FREQ 10159000
#define QSPI_FREQ 200000000
#define SMC_FREQ 100000000
#define ENET0_FREQ 25000000
#define ENET1_FREQ 125000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 50000000
#define SPI_FREQ 166666666
#define I2C_FREQ 111111115
#define WDT_FREQ 133333333
#define TTC_FREQ 50000000
#define CAN_FREQ 23809500
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 50000000
#define FPGA2_FREQ 50000000
#define FPGA3_FREQ 50000000
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
char* getPS7MessageInfo(unsigned key);
#ifdef __cplusplus
}
#endif

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proc ps7_pll_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00302301
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00500801
mask_write 0XF800014C 0x00003F31 0x00000501
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00001402
mask_write 0XF800015C 0x03F03F33 0x00300E01
mask_write 0XF8000160 0x007F007F 0x00000000
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00101400
mask_write 0XF8000180 0x03F03F30 0x00101400
mask_write 0XF8000190 0x03F03F30 0x00101400
mask_write 0XF80001A0 0x03F03F30 0x00101400
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001081
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004159B
mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
mask_write 0XF8006020 0x7FDFFFFC 0x27087290
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
mask_write 0XF8006034 0x13FF3FFF 0x00011054
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F000 0x0003C000
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000003
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x0003C81D
mask_write 0XF8006130 0x000FFFFF 0x00036012
mask_write 0XF8006134 0x000FFFFF 0x0003780C
mask_write 0XF8006138 0x000FFFFF 0x0003B821
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x0000009D
mask_write 0XF8006158 0x000FFFFF 0x00000092
mask_write 0XF800615C 0x000FFFFF 0x0000008C
mask_write 0XF8006160 0x000FFFFF 0x000000A1
mask_write 0XF8006168 0x001FFFFF 0x00000147
mask_write 0XF800616C 0x001FFFFF 0x0000012D
mask_write 0XF8006170 0x001FFFFF 0x00000133
mask_write 0XF8006174 0x001FFFFF 0x00000143
mask_write 0XF800617C 0x000FFFFF 0x000000DD
mask_write 0XF8006180 0x000FFFFF 0x000000D2
mask_write 0XF8006184 0x000FFFFF 0x000000CC
mask_write 0XF8006188 0x000FFFFF 0x000000E1
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B00 0x00000071 0x00000001
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000E09
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000700 0x00003F01 0x00001201
mask_write 0XF8000704 0x00003FFF 0x00001202
mask_write 0XF8000708 0x00003FFF 0x00000202
mask_write 0XF800070C 0x00003FFF 0x00000202
mask_write 0XF8000710 0x00003FFF 0x00000202
mask_write 0XF8000714 0x00003FFF 0x00000202
mask_write 0XF8000718 0x00003FFF 0x00000202
mask_write 0XF800071C 0x00003FFF 0x00000200
mask_write 0XF8000720 0x00003FFF 0x00000202
mask_write 0XF8000724 0x00003FFF 0x00001200
mask_write 0XF8000728 0x00003FFF 0x00001200
mask_write 0XF800072C 0x00003FFF 0x00001200
mask_write 0XF8000730 0x00003FFF 0x00001200
mask_write 0XF8000734 0x00003FFF 0x00001200
mask_write 0XF8000738 0x00003FFF 0x00001200
mask_write 0XF800073C 0x00003F01 0x00001201
mask_write 0XF8000740 0x00003FFF 0x00002802
mask_write 0XF8000744 0x00003FFF 0x00002802
mask_write 0XF8000748 0x00003FFF 0x00002802
mask_write 0XF800074C 0x00003FFF 0x00002802
mask_write 0XF8000750 0x00003FFF 0x00002802
mask_write 0XF8000754 0x00003FFF 0x00002802
mask_write 0XF8000758 0x00003FFF 0x00000803
mask_write 0XF800075C 0x00003FFF 0x00000803
mask_write 0XF8000760 0x00003FFF 0x00000803
mask_write 0XF8000764 0x00003FFF 0x00000803
mask_write 0XF8000768 0x00003FFF 0x00000803
mask_write 0XF800076C 0x00003FFF 0x00000803
mask_write 0XF8000770 0x00003FFF 0x00000204
mask_write 0XF8000774 0x00003FFF 0x00000205
mask_write 0XF8000778 0x00003FFF 0x00000204
mask_write 0XF800077C 0x00003FFF 0x00000205
mask_write 0XF8000780 0x00003FFF 0x00000204
mask_write 0XF8000784 0x00003FFF 0x00000204
mask_write 0XF8000788 0x00003FFF 0x00000204
mask_write 0XF800078C 0x00003FFF 0x00000204
mask_write 0XF8000790 0x00003FFF 0x00000205
mask_write 0XF8000794 0x00003FFF 0x00000204
mask_write 0XF8000798 0x00003FFF 0x00000204
mask_write 0XF800079C 0x00003FFF 0x00000204
mask_write 0XF80007A0 0x00003FFF 0x00000280
mask_write 0XF80007A4 0x00003FFF 0x00000280
mask_write 0XF80007A8 0x00003FFF 0x00000280
mask_write 0XF80007AC 0x00003FFF 0x00000280
mask_write 0XF80007B0 0x00003FFF 0x00000280
mask_write 0XF80007B4 0x00003FFF 0x00000280
mask_write 0XF80007B8 0x00003FFF 0x00001221
mask_write 0XF80007BC 0x00003FFF 0x00001220
mask_write 0XF80007C0 0x00003FFF 0x000002E0
mask_write 0XF80007C4 0x00003FFF 0x000002E1
mask_write 0XF80007C8 0x00003FFF 0x00001240
mask_write 0XF80007CC 0x00003FFF 0x00001240
mask_write 0XF80007D0 0x00003FFF 0x00000280
mask_write 0XF80007D4 0x00003FFF 0x00000280
mask_write 0XF8000830 0x003F003F 0x0000000F
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mask_write 0XF8000004 0x0000FFFF 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000003E
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
}
proc ps7_post_config_3_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_pll_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00302301
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00500801
mask_write 0XF800014C 0x00003F31 0x00000501
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00001402
mask_write 0XF800015C 0x03F03F33 0x00300E01
mask_write 0XF8000160 0x007F007F 0x00000000
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00101400
mask_write 0XF8000180 0x03F03F30 0x00101400
mask_write 0XF8000190 0x03F03F30 0x00101400
mask_write 0XF80001A0 0x03F03F30 0x00101400
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004159B
mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
mask_write 0XF8006034 0x13FF3FFF 0x00011054
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000003
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x0003C81D
mask_write 0XF8006130 0x000FFFFF 0x00036012
mask_write 0XF8006134 0x000FFFFF 0x0003780C
mask_write 0XF8006138 0x000FFFFF 0x0003B821
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x0000009D
mask_write 0XF8006158 0x000FFFFF 0x00000092
mask_write 0XF800615C 0x000FFFFF 0x0000008C
mask_write 0XF8006160 0x000FFFFF 0x000000A1
mask_write 0XF8006168 0x001FFFFF 0x00000147
mask_write 0XF800616C 0x001FFFFF 0x0000012D
mask_write 0XF8006170 0x001FFFFF 0x00000133
mask_write 0XF8006174 0x001FFFFF 0x00000143
mask_write 0XF800617C 0x000FFFFF 0x000000DD
mask_write 0XF8006180 0x000FFFFF 0x000000D2
mask_write 0XF8006184 0x000FFFFF 0x000000CC
mask_write 0XF8006188 0x000FFFFF 0x000000E1
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B00 0x00000303 0x00000001
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000E09
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003F01 0x00001201
mask_write 0XF8000704 0x00003FFF 0x00001202
mask_write 0XF8000708 0x00003FFF 0x00000202
mask_write 0XF800070C 0x00003FFF 0x00000202
mask_write 0XF8000710 0x00003FFF 0x00000202
mask_write 0XF8000714 0x00003FFF 0x00000202
mask_write 0XF8000718 0x00003FFF 0x00000202
mask_write 0XF800071C 0x00003FFF 0x00000200
mask_write 0XF8000720 0x00003FFF 0x00000202
mask_write 0XF8000724 0x00003FFF 0x00001200
mask_write 0XF8000728 0x00003FFF 0x00001200
mask_write 0XF800072C 0x00003FFF 0x00001200
mask_write 0XF8000730 0x00003FFF 0x00001200
mask_write 0XF8000734 0x00003FFF 0x00001200
mask_write 0XF8000738 0x00003FFF 0x00001200
mask_write 0XF800073C 0x00003F01 0x00001201
mask_write 0XF8000740 0x00003FFF 0x00002802
mask_write 0XF8000744 0x00003FFF 0x00002802
mask_write 0XF8000748 0x00003FFF 0x00002802
mask_write 0XF800074C 0x00003FFF 0x00002802
mask_write 0XF8000750 0x00003FFF 0x00002802
mask_write 0XF8000754 0x00003FFF 0x00002802
mask_write 0XF8000758 0x00003FFF 0x00000803
mask_write 0XF800075C 0x00003FFF 0x00000803
mask_write 0XF8000760 0x00003FFF 0x00000803
mask_write 0XF8000764 0x00003FFF 0x00000803
mask_write 0XF8000768 0x00003FFF 0x00000803
mask_write 0XF800076C 0x00003FFF 0x00000803
mask_write 0XF8000770 0x00003FFF 0x00000204
mask_write 0XF8000774 0x00003FFF 0x00000205
mask_write 0XF8000778 0x00003FFF 0x00000204
mask_write 0XF800077C 0x00003FFF 0x00000205
mask_write 0XF8000780 0x00003FFF 0x00000204
mask_write 0XF8000784 0x00003FFF 0x00000204
mask_write 0XF8000788 0x00003FFF 0x00000204
mask_write 0XF800078C 0x00003FFF 0x00000204
mask_write 0XF8000790 0x00003FFF 0x00000205
mask_write 0XF8000794 0x00003FFF 0x00000204
mask_write 0XF8000798 0x00003FFF 0x00000204
mask_write 0XF800079C 0x00003FFF 0x00000204
mask_write 0XF80007A0 0x00003FFF 0x00000280
mask_write 0XF80007A4 0x00003FFF 0x00000280
mask_write 0XF80007A8 0x00003FFF 0x00000280
mask_write 0XF80007AC 0x00003FFF 0x00000280
mask_write 0XF80007B0 0x00003FFF 0x00000280
mask_write 0XF80007B4 0x00003FFF 0x00000280
mask_write 0XF80007B8 0x00003FFF 0x00001221
mask_write 0XF80007BC 0x00003FFF 0x00001220
mask_write 0XF80007C0 0x00003FFF 0x000002E0
mask_write 0XF80007C4 0x00003FFF 0x000002E1
mask_write 0XF80007C8 0x00003FFF 0x00001240
mask_write 0XF80007CC 0x00003FFF 0x00001240
mask_write 0XF80007D0 0x00003FFF 0x00000280
mask_write 0XF80007D4 0x00003FFF 0x00000280
mask_write 0XF8000830 0x003F003F 0x0000000F
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mask_write 0XF8000004 0x0000FFFF 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000003E
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
}
proc ps7_post_config_2_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_pll_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00302301
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00500801
mask_write 0XF800014C 0x00003F31 0x00000501
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00001402
mask_write 0XF800015C 0x03F03F33 0x00300E01
mask_write 0XF8000160 0x007F007F 0x00000000
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00101400
mask_write 0XF8000180 0x03F03F30 0x00101400
mask_write 0XF8000190 0x03F03F30 0x00101400
mask_write 0XF80001A0 0x03F03F30 0x00101400
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004159B
mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
mask_write 0XF8006020 0xFFFFFFFC 0x27287290
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
mask_write 0XF8006034 0x13FF3FFF 0x00011054
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000003
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x0003C81D
mask_write 0XF8006130 0x000FFFFF 0x00036012
mask_write 0XF8006134 0x000FFFFF 0x0003780C
mask_write 0XF8006138 0x000FFFFF 0x0003B821
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x0000009D
mask_write 0XF8006158 0x000FFFFF 0x00000092
mask_write 0XF800615C 0x000FFFFF 0x0000008C
mask_write 0XF8006160 0x000FFFFF 0x000000A1
mask_write 0XF8006168 0x001FFFFF 0x00000147
mask_write 0XF800616C 0x001FFFFF 0x0000012D
mask_write 0XF8006170 0x001FFFFF 0x00000133
mask_write 0XF8006174 0x001FFFFF 0x00000143
mask_write 0XF800617C 0x000FFFFF 0x000000DD
mask_write 0XF8006180 0x000FFFFF 0x000000D2
mask_write 0XF8006184 0x000FFFFF 0x000000CC
mask_write 0XF8006188 0x000FFFFF 0x000000E1
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B00 0x00000303 0x00000001
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000209
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000700 0x00003F01 0x00001201
mask_write 0XF8000704 0x00003FFF 0x00001202
mask_write 0XF8000708 0x00003FFF 0x00000202
mask_write 0XF800070C 0x00003FFF 0x00000202
mask_write 0XF8000710 0x00003FFF 0x00000202
mask_write 0XF8000714 0x00003FFF 0x00000202
mask_write 0XF8000718 0x00003FFF 0x00000202
mask_write 0XF800071C 0x00003FFF 0x00000200
mask_write 0XF8000720 0x00003FFF 0x00000202
mask_write 0XF8000724 0x00003FFF 0x00001200
mask_write 0XF8000728 0x00003FFF 0x00001200
mask_write 0XF800072C 0x00003FFF 0x00001200
mask_write 0XF8000730 0x00003FFF 0x00001200
mask_write 0XF8000734 0x00003FFF 0x00001200
mask_write 0XF8000738 0x00003FFF 0x00001200
mask_write 0XF800073C 0x00003F01 0x00001201
mask_write 0XF8000740 0x00003FFF 0x00002802
mask_write 0XF8000744 0x00003FFF 0x00002802
mask_write 0XF8000748 0x00003FFF 0x00002802
mask_write 0XF800074C 0x00003FFF 0x00002802
mask_write 0XF8000750 0x00003FFF 0x00002802
mask_write 0XF8000754 0x00003FFF 0x00002802
mask_write 0XF8000758 0x00003FFF 0x00000803
mask_write 0XF800075C 0x00003FFF 0x00000803
mask_write 0XF8000760 0x00003FFF 0x00000803
mask_write 0XF8000764 0x00003FFF 0x00000803
mask_write 0XF8000768 0x00003FFF 0x00000803
mask_write 0XF800076C 0x00003FFF 0x00000803
mask_write 0XF8000770 0x00003FFF 0x00000204
mask_write 0XF8000774 0x00003FFF 0x00000205
mask_write 0XF8000778 0x00003FFF 0x00000204
mask_write 0XF800077C 0x00003FFF 0x00000205
mask_write 0XF8000780 0x00003FFF 0x00000204
mask_write 0XF8000784 0x00003FFF 0x00000204
mask_write 0XF8000788 0x00003FFF 0x00000204
mask_write 0XF800078C 0x00003FFF 0x00000204
mask_write 0XF8000790 0x00003FFF 0x00000205
mask_write 0XF8000794 0x00003FFF 0x00000204
mask_write 0XF8000798 0x00003FFF 0x00000204
mask_write 0XF800079C 0x00003FFF 0x00000204
mask_write 0XF80007A0 0x00003FFF 0x00000280
mask_write 0XF80007A4 0x00003FFF 0x00000280
mask_write 0XF80007A8 0x00003FFF 0x00000280
mask_write 0XF80007AC 0x00003FFF 0x00000280
mask_write 0XF80007B0 0x00003FFF 0x00000280
mask_write 0XF80007B4 0x00003FFF 0x00000280
mask_write 0XF80007B8 0x00003FFF 0x00001221
mask_write 0XF80007BC 0x00003FFF 0x00001220
mask_write 0XF80007C0 0x00003FFF 0x000002E0
mask_write 0XF80007C4 0x00003FFF 0x000002E1
mask_write 0XF80007C8 0x00003FFF 0x00001240
mask_write 0XF80007CC 0x00003FFF 0x00001240
mask_write 0XF80007D0 0x00003FFF 0x00000280
mask_write 0XF80007D4 0x00003FFF 0x00000280
mask_write 0XF8000830 0x003F003F 0x0000000F
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mask_write 0XF8000004 0x0000FFFF 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000003E
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000
mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
mask_write 0XE000A204 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
mask_write 0XE000A208 0xFFFFFFFF 0x00002880
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000
mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
}
proc ps7_post_config_1_0 {} {
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}

6164
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml
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