@ -83,6 +83,7 @@
descriptor is then used to re - send in order to speed up the uIP Tx process . */
# define emacTX_DESC_INDEX ( 0 )
# define PCONP_PCENET 0x40000000
/*-----------------------------------------------------------*/
/*
@ -162,15 +163,15 @@ unsigned long ulID1, ulID2;
if ( ( ( ulID1 < < 16UL ) | ( ulID2 & 0xFFF0UL ) ) = = DP83848C_ID )
{
/* Set the Ethernet MAC Address registers */
EMAC- > SA0 = ( configMAC_ADDR0 < < 8 ) | configMAC_ADDR1 ;
EMAC- > SA1 = ( configMAC_ADDR2 < < 8 ) | configMAC_ADDR3 ;
EMAC- > SA2 = ( configMAC_ADDR4 < < 8 ) | configMAC_ADDR5 ;
LPC_ EMAC- > SA0 = ( configMAC_ADDR0 < < 8 ) | configMAC_ADDR1 ;
LPC_ EMAC- > SA1 = ( configMAC_ADDR2 < < 8 ) | configMAC_ADDR3 ;
LPC_ EMAC- > SA2 = ( configMAC_ADDR4 < < 8 ) | configMAC_ADDR5 ;
/* Initialize Tx and Rx DMA Descriptors */
prvInitDescriptors ( ) ;
/* Receive broadcast and perfect match packets */
EMAC- > RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN ;
LPC_ EMAC- > RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN ;
/* Setup the PHY. */
prvConfigurePHY ( ) ;
@ -192,11 +193,11 @@ unsigned long ulID1, ulID2;
uip_buf = prvGetNextBuffer ( ) ;
/* Reset all interrupts */
EMAC- > IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP ) ;
LPC_ EMAC- > IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP ) ;
/* Enable receive and transmit mode of MAC Ethernet core */
EMAC- > Command | = ( CR_RX_EN | CR_TX_EN ) ;
EMAC- > MAC1 | = MAC1_REC_EN ;
LPC_ EMAC- > Command | = ( CR_RX_EN | CR_TX_EN ) ;
LPC_ EMAC- > MAC1 | = MAC1_REC_EN ;
}
return lReturn ;
@ -260,12 +261,12 @@ long x, lNextBuffer = 0;
}
/* Set EMAC Receive Descriptor Registers. */
EMAC- > RxDescriptor = RX_DESC_BASE ;
EMAC- > RxStatus = RX_STAT_BASE ;
EMAC- > RxDescriptorNumber = NUM_RX_FRAG - 1 ;
LPC_ EMAC- > RxDescriptor = RX_DESC_BASE ;
LPC_ EMAC- > RxStatus = RX_STAT_BASE ;
LPC_ EMAC- > RxDescriptorNumber = NUM_RX_FRAG - 1 ;
/* Rx Descriptors Point to 0 */
EMAC- > RxConsumeIndex = 0 ;
LPC_ EMAC- > RxConsumeIndex = 0 ;
/* A buffer is not allocated to the Tx descriptors until they are actually
used . */
@ -277,12 +278,12 @@ long x, lNextBuffer = 0;
}
/* Set EMAC Transmit Descriptor Registers. */
EMAC- > TxDescriptor = TX_DESC_BASE ;
EMAC- > TxStatus = TX_STAT_BASE ;
EMAC- > TxDescriptorNumber = NUM_TX_FRAG - 1 ;
LPC_ EMAC- > TxDescriptor = TX_DESC_BASE ;
LPC_ EMAC- > TxStatus = TX_STAT_BASE ;
LPC_ EMAC- > TxDescriptorNumber = NUM_TX_FRAG - 1 ;
/* Tx Descriptors Point to 0 */
EMAC- > TxProduceIndex = 0 ;
LPC_ EMAC- > TxProduceIndex = 0 ;
}
/*-----------------------------------------------------------*/
@ -292,34 +293,34 @@ unsigned short us;
long x , lDummy ;
/* Enable P1 Ethernet Pins. */
PINCON- > PINSEL2 = emacPINSEL2_VALUE ;
PINCON- > PINSEL3 = ( PINCON- > PINSEL3 & ~ 0x0000000F ) | 0x00000005 ;
LPC_ PINCON- > PINSEL2 = emacPINSEL2_VALUE ;
LPC_ PINCON- > PINSEL3 = ( LPC_ PINCON- > PINSEL3 & ~ 0x0000000F ) | 0x00000005 ;
/* Power Up the EMAC controller. */
SC- > PCONP | = PCONP_PCENET ;
LPC_ SC- > PCONP | = PCONP_PCENET ;
vTaskDelay ( emacSHORT_DELAY ) ;
/* Reset all EMAC internal modules. */
EMAC- > MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES ;
EMAC- > Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM ;
LPC_ EMAC- > MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES ;
LPC_ EMAC- > Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM ;
/* A short delay after reset. */
vTaskDelay ( emacSHORT_DELAY ) ;
/* Initialize MAC control registers. */
EMAC- > MAC1 = MAC1_PASS_ALL ;
EMAC- > MAC2 = MAC2_CRC_EN | MAC2_PAD_EN ;
EMAC- > MAXF = ETH_MAX_FLEN ;
EMAC- > CLRT = CLRT_DEF ;
EMAC- > IPGR = IPGR_DEF ;
LPC_ EMAC- > MAC1 = MAC1_PASS_ALL ;
LPC_ EMAC- > MAC2 = MAC2_CRC_EN | MAC2_PAD_EN ;
LPC_ EMAC- > MAXF = ETH_MAX_FLEN ;
LPC_ EMAC- > CLRT = CLRT_DEF ;
LPC_ EMAC- > IPGR = IPGR_DEF ;
/* Enable Reduced MII interface. */
EMAC- > Command = CR_RMII | CR_PASS_RUNT_FRM ;
LPC_ EMAC- > Command = CR_RMII | CR_PASS_RUNT_FRM ;
/* Reset Reduced MII Logic. */
EMAC- > SUPP = SUPP_RES_RMII ;
LPC_ EMAC- > SUPP = SUPP_RES_RMII ;
vTaskDelay ( emacSHORT_DELAY ) ;
EMAC- > SUPP = 0 ;
LPC_ EMAC- > SUPP = 0 ;
/* Put the PHY in reset mode */
prvWritePHY ( PHY_REG_BMCR , MCFG_RES_MII ) ;
@ -389,26 +390,26 @@ unsigned short usLinkStatus;
if ( usLinkStatus & emacFULL_DUPLEX_ENABLED )
{
/* Full duplex is enabled. */
EMAC- > MAC2 | = MAC2_FULL_DUP ;
EMAC- > Command | = CR_FULL_DUP ;
EMAC- > IPGT = IPGT_FULL_DUP ;
LPC_ EMAC- > MAC2 | = MAC2_FULL_DUP ;
LPC_ EMAC- > Command | = CR_FULL_DUP ;
LPC_ EMAC- > IPGT = IPGT_FULL_DUP ;
}
else
{
/* Half duplex mode. */
EMAC- > IPGT = IPGT_HALF_DUP ;
LPC_ EMAC- > IPGT = IPGT_HALF_DUP ;
}
/* Configure 100MBit/10MBit mode. */
if ( usLinkStatus & emac10BASE_T_MODE )
{
/* 10MBit mode. */
EMAC- > SUPP = 0 ;
LPC_ EMAC- > SUPP = 0 ;
}
else
{
/* 100MBit mode. */
EMAC- > SUPP = SUPP_SPEED ;
LPC_ EMAC- > SUPP = SUPP_SPEED ;
}
}
@ -437,21 +438,21 @@ unsigned long ulGetEMACRxData( void )
unsigned long ulLen = 0 ;
long lIndex ;
if ( EMAC- > RxProduceIndex ! = EMAC- > RxConsumeIndex )
if ( LPC_ EMAC- > RxProduceIndex ! = LPC_ EMAC- > RxConsumeIndex )
{
/* Mark the current buffer as free as uip_buf is going to be set to
the buffer that contains the received data . */
prvReturnBuffer ( uip_buf ) ;
ulLen = ( RX_STAT_INFO ( EMAC- > RxConsumeIndex ) & RINFO_SIZE ) - 3 ;
uip_buf = ( unsigned char * ) RX_DESC_PACKET ( EMAC- > RxConsumeIndex ) ;
ulLen = ( RX_STAT_INFO ( LPC_ EMAC- > RxConsumeIndex ) & RINFO_SIZE ) - 3 ;
uip_buf = ( unsigned char * ) RX_DESC_PACKET ( LPC_ EMAC- > RxConsumeIndex ) ;
/* Allocate a new buffer to the descriptor. */
RX_DESC_PACKET ( EMAC- > RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer ( ) ;
RX_DESC_PACKET ( LPC_ EMAC- > RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer ( ) ;
/* Move the consume index onto the next position, ensuring it wraps to
the beginning at the appropriate place . */
lIndex = EMAC- > RxConsumeIndex ;
lIndex = LPC_ EMAC- > RxConsumeIndex ;
lIndex + + ;
if ( lIndex > = NUM_RX_FRAG )
@ -459,7 +460,7 @@ long lIndex;
lIndex = 0 ;
}
EMAC- > RxConsumeIndex = lIndex ;
LPC_ EMAC- > RxConsumeIndex = lIndex ;
}
return ulLen ;
@ -494,7 +495,7 @@ unsigned long ulAttempts = 0UL;
usSendLen = usTxDataLen ;
TX_DESC_PACKET ( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf ;
TX_DESC_CTRL ( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT ) ;
EMAC- > TxProduceIndex = ( emacTX_DESC_INDEX + 1 ) ;
LPC_ EMAC- > TxProduceIndex = ( emacTX_DESC_INDEX + 1 ) ;
/* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
uip_buf = prvGetNextBuffer ( ) ;
@ -506,13 +507,13 @@ static long prvWritePHY( long lPhyReg, long lValue )
const long lMaxTime = 10 ;
long x ;
EMAC- > MADR = DP83848C_DEF_ADR | lPhyReg ;
EMAC- > MWTD = lValue ;
LPC_ EMAC- > MADR = DP83848C_DEF_ADR | lPhyReg ;
LPC_ EMAC- > MWTD = lValue ;
x = 0 ;
for ( x = 0 ; x < lMaxTime ; x + + )
{
if ( ( EMAC- > MIND & MIND_BUSY ) = = 0 )
if ( ( LPC_ EMAC- > MIND & MIND_BUSY ) = = 0 )
{
/* Operation has finished. */
break ;
@ -537,13 +538,13 @@ static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
long x ;
const long lMaxTime = 10 ;
EMAC- > MADR = DP83848C_DEF_ADR | ucPhyReg ;
EMAC- > MCMD = MCMD_READ ;
LPC_ EMAC- > MADR = DP83848C_DEF_ADR | ucPhyReg ;
LPC_ EMAC- > MCMD = MCMD_READ ;
for ( x = 0 ; x < lMaxTime ; x + + )
{
/* Operation has finished. */
if ( ( EMAC- > MIND & MIND_BUSY ) = = 0 )
if ( ( LPC_ EMAC- > MIND & MIND_BUSY ) = = 0 )
{
break ;
}
@ -551,14 +552,14 @@ const long lMaxTime = 10;
vTaskDelay ( emacSHORT_DELAY ) ;
}
EMAC- > MCMD = 0 ;
LPC_ EMAC- > MCMD = 0 ;
if ( x > = lMaxTime )
{
* plStatus = pdFAIL ;
}
return ( EMAC- > MRDD ) ;
return ( LPC_ EMAC- > MRDD ) ;
}
/*-----------------------------------------------------------*/
@ -567,10 +568,10 @@ void vEMAC_ISR( void )
unsigned long ulStatus ;
long lHigherPriorityTaskWoken = pdFALSE ;
ulStatus = EMAC- > IntStatus ;
ulStatus = LPC_ EMAC- > IntStatus ;
/* Clear the interrupt. */
EMAC- > IntClear = ulStatus ;
LPC_ EMAC- > IntClear = ulStatus ;
if ( ulStatus & INT_RX_DONE )
{
@ -586,7 +587,7 @@ long lHigherPriorityTaskWoken = pdFALSE;
only two descriptors the index is set back to 0. */
TX_DESC_PACKET ( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET ( emacTX_DESC_INDEX ) ;
TX_DESC_CTRL ( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT ) ;
EMAC- > TxProduceIndex = ( emacTX_DESC_INDEX ) ;
LPC_ EMAC- > TxProduceIndex = ( emacTX_DESC_INDEX ) ;
/* This is the second Tx so set usSendLen to 0 to indicate that the
Tx descriptors will be free again . */