Add a hardware definition project for the MicroZed board (#607)
Add a hardware definition project for the MicroZed board to the existing Zynq ZC702 project. Add a text file that describes how to switch the Zynq project form the ZC702 hardware to the MicroZed hardware.pull/806/head
RichardBarry
3 years ago
committed by
GitHub
parent
92b26dbf99
commit
1509e4f742
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>MicroZed_hw_platform</name>
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<comment>Created by SDK v2014.3</comment>
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<projects>
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</projects>
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<buildSpec>
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</buildSpec>
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<natures>
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<nature>com.xilinx.sdk.hw.HwProject</nature>
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</natures>
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</projectDescription>
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/******************************************************************************
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*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this
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* software and associated documentation files (the "Software"), to deal in the Software
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* without restriction, including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
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* persons to whom the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
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* otherwise to promote the sale, use or other dealings in this Software without prior written
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* authorization from Xilinx.
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*
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*******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file ps7_init.h
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*
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* This file can be included in FSBL code
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* to get prototype of ps7_init() function
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* and error codes
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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//typedef unsigned int u32;
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/** do we need to make this name more unique ? **/
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//extern u32 ps7_init_data[];
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extern unsigned long * ps7_ddr_init_data;
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extern unsigned long * ps7_mio_init_data;
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extern unsigned long * ps7_pll_init_data;
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extern unsigned long * ps7_clock_init_data;
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extern unsigned long * ps7_peripherals_init_data;
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#define OPCODE_EXIT 0U
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#define OPCODE_CLEAR 1U
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#define OPCODE_WRITE 2U
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#define OPCODE_MASKWRITE 3U
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#define OPCODE_MASKPOLL 4U
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#define OPCODE_MASKDELAY 5U
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#define NEW_PS7_ERR_CODE 1
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/* Encode number of arguments in last nibble */
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#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
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#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
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#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
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#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
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#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
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#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
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/* Returns codes of PS7_Init */
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#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
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#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
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#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
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#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
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#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
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#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
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/* Silicon Versions */
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#define PCW_SILICON_VERSION_1 0
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#define PCW_SILICON_VERSION_2 1
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#define PCW_SILICON_VERSION_3 2
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/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
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#define PS7_POST_CONFIG
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/* Freq of all peripherals */
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#define APU_FREQ 666666687
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#define DDR_FREQ 533333374
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#define DCI_FREQ 10158731
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#define QSPI_FREQ 200000000
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#define SMC_FREQ 10000000
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#define ENET0_FREQ 125000000
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#define ENET1_FREQ 10000000
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#define USB0_FREQ 60000000
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#define USB1_FREQ 60000000
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#define SDIO_FREQ 50000000
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#define UART_FREQ 50000000
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#define SPI_FREQ 10000000
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#define I2C_FREQ 111111115
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#define WDT_FREQ 111111115
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#define TTC_FREQ 50000000
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#define CAN_FREQ 10000000
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#define PCAP_FREQ 200000000
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#define TPIU_FREQ 200000000
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#define FPGA0_FREQ 100000000
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#define FPGA1_FREQ 100000000
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#define FPGA2_FREQ 33333336
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#define FPGA3_FREQ 50000000
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/* For delay calculation using global registers*/
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#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
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#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
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int ps7_config( unsigned long*);
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int ps7_init();
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int ps7_post_config();
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int ps7_debug();
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char* getPS7MessageInfo(unsigned key);
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void perf_start_clock(void);
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void perf_disable_clock(void);
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void perf_reset_clock(void);
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void perf_reset_and_start_timer();
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int get_number_of_cycles_for_delay(unsigned int delay);
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#ifdef __cplusplus
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}
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#endif
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File diff suppressed because it is too large
Load Diff
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proc ps7_pll_init_data_3_0 {} {
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mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
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mask_write 0XF8000110 0x003FFFF0 0x000FA220
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mask_write 0XF8000100 0x0007F000 0x00028000
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mask_write 0XF8000100 0x00000010 0x00000010
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mask_write 0XF8000100 0x00000001 0x00000001
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mask_write 0XF8000100 0x00000001 0x00000000
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mask_poll 0XF800010C 0x00000001
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mask_write 0XF8000100 0x00000010 0x00000000
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mask_write 0XF8000120 0x1F003F30 0x1F000200
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mask_write 0XF8000114 0x003FFFF0 0x0012C220
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mask_write 0XF8000104 0x0007F000 0x00020000
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mask_write 0XF8000104 0x00000010 0x00000010
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mask_write 0XF8000104 0x00000001 0x00000001
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mask_write 0XF8000104 0x00000001 0x00000000
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mask_poll 0XF800010C 0x00000002
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mask_write 0XF8000104 0x00000010 0x00000000
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mask_write 0XF8000124 0xFFF00003 0x0C200003
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mask_write 0XF8000118 0x003FFFF0 0x001452C0
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mask_write 0XF8000108 0x0007F000 0x0001E000
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mask_write 0XF8000108 0x00000010 0x00000010
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mask_write 0XF8000108 0x00000001 0x00000001
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mask_write 0XF8000108 0x00000001 0x00000000
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mask_poll 0XF800010C 0x00000004
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mask_write 0XF8000108 0x00000010 0x00000000
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mask_write 0XF8000004 0x0000FFFF 0x0000767B
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}
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proc ps7_clock_init_data_3_0 {} {
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mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
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mask_write 0XF8000128 0x03F03F01 0x00302301
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mask_write 0XF8000138 0x00000011 0x00000001
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mask_write 0XF8000140 0x03F03F71 0x00100801
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mask_write 0XF800014C 0x00003F31 0x00000501
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mask_write 0XF8000150 0x00003F33 0x00001401
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mask_write 0XF8000154 0x00003F33 0x00001402
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mask_write 0XF8000168 0x00003F31 0x00000501
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mask_write 0XF8000170 0x03F03F30 0x00100A00
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mask_write 0XF8000180 0x03F03F30 0x00100A00
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mask_write 0XF8000190 0x03F03F30 0x00101E00
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mask_write 0XF80001A0 0x03F03F30 0x00101400
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mask_write 0XF80001C4 0x00000001 0x00000001
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mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
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mask_write 0XF8000004 0x0000FFFF 0x0000767B
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}
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proc ps7_ddr_init_data_3_0 {} {
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mask_write 0XF8006000 0x0001FFFF 0x00000080
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mask_write 0XF8006004 0x0007FFFF 0x00001081
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mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
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mask_write 0XF800600C 0x03FFFFFF 0x02001001
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mask_write 0XF8006010 0x03FFFFFF 0x00014001
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mask_write 0XF8006014 0x001FFFFF 0x0004281A
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mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
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mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
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mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
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mask_write 0XF8006024 0x0FFFFFC3 0x00000000
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mask_write 0XF8006028 0x00003FFF 0x00002007
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mask_write 0XF800602C 0xFFFFFFFF 0x00000008
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mask_write 0XF8006030 0xFFFFFFFF 0x00040930
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mask_write 0XF8006034 0x13FF3FFF 0x00011054
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mask_write 0XF8006038 0x00000003 0x00000000
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mask_write 0XF800603C 0x000FFFFF 0x00000777
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mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
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mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
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mask_write 0XF8006048 0x0003F000 0x0003C000
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mask_write 0XF8006050 0xFF0F8FFF 0x77010800
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mask_write 0XF8006058 0x00010000 0x00000000
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mask_write 0XF800605C 0x0000FFFF 0x00005003
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mask_write 0XF8006060 0x000017FF 0x0000003E
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mask_write 0XF8006064 0x00021FE0 0x00020000
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mask_write 0XF8006068 0x03FFFFFF 0x00284141
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mask_write 0XF800606C 0x0000FFFF 0x00001610
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mask_write 0XF8006078 0x03FFFFFF 0x00466111
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mask_write 0XF800607C 0x000FFFFF 0x00032222
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mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
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mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
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mask_write 0XF80060AC 0x000001FF 0x000001FE
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mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
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mask_write 0XF80060B4 0x00000200 0x00000200
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mask_write 0XF80060B8 0x01FFFFFF 0x00200066
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mask_write 0XF80060C4 0x00000003 0x00000003
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mask_write 0XF80060C4 0x00000003 0x00000000
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mask_write 0XF80060C8 0x000000FF 0x00000000
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mask_write 0XF80060DC 0x00000001 0x00000000
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mask_write 0XF80060F0 0x0000FFFF 0x00000000
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mask_write 0XF80060F4 0x0000000F 0x00000008
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mask_write 0XF8006114 0x000000FF 0x00000000
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mask_write 0XF8006118 0x7FFFFFCF 0x40000001
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mask_write 0XF800611C 0x7FFFFFCF 0x40000001
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mask_write 0XF8006120 0x7FFFFFCF 0x40000001
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mask_write 0XF8006124 0x7FFFFFCF 0x40000001
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mask_write 0XF800612C 0x000FFFFF 0x0002C000
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mask_write 0XF8006130 0x000FFFFF 0x0002C400
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mask_write 0XF8006134 0x000FFFFF 0x0002F003
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mask_write 0XF8006138 0x000FFFFF 0x0002EC03
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mask_write 0XF8006140 0x000FFFFF 0x00000035
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mask_write 0XF8006144 0x000FFFFF 0x00000035
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mask_write 0XF8006148 0x000FFFFF 0x00000035
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mask_write 0XF800614C 0x000FFFFF 0x00000035
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mask_write 0XF8006154 0x000FFFFF 0x00000077
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mask_write 0XF8006158 0x000FFFFF 0x00000077
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mask_write 0XF800615C 0x000FFFFF 0x00000083
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mask_write 0XF8006160 0x000FFFFF 0x00000083
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mask_write 0XF8006168 0x001FFFFF 0x00000105
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mask_write 0XF800616C 0x001FFFFF 0x00000106
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mask_write 0XF8006170 0x001FFFFF 0x00000111
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mask_write 0XF8006174 0x001FFFFF 0x00000110
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mask_write 0XF800617C 0x000FFFFF 0x000000B7
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mask_write 0XF8006180 0x000FFFFF 0x000000B7
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mask_write 0XF8006184 0x000FFFFF 0x000000C3
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mask_write 0XF8006188 0x000FFFFF 0x000000C3
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mask_write 0XF8006190 0x6FFFFEFE 0x00040080
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mask_write 0XF8006194 0x000FFFFF 0x0001FC82
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mask_write 0XF8006204 0xFFFFFFFF 0x00000000
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mask_write 0XF8006208 0x000703FF 0x000003FF
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mask_write 0XF800620C 0x000703FF 0x000003FF
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mask_write 0XF8006210 0x000703FF 0x000003FF
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mask_write 0XF8006214 0x000703FF 0x000003FF
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mask_write 0XF8006218 0x000F03FF 0x000003FF
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mask_write 0XF800621C 0x000F03FF 0x000003FF
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mask_write 0XF8006220 0x000F03FF 0x000003FF
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mask_write 0XF8006224 0x000F03FF 0x000003FF
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mask_write 0XF80062A8 0x00000FF5 0x00000000
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mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
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mask_write 0XF80062B0 0x003FFFFF 0x00005125
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mask_write 0XF80062B4 0x0003FFFF 0x000012A8
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mask_poll 0XF8000B74 0x00002000
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mask_write 0XF8006000 0x0001FFFF 0x00000081
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mask_poll 0XF8006054 0x00000007
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}
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proc ps7_mio_init_data_3_0 {} {
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mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
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mask_write 0XF8000B40 0x00000FFF 0x00000600
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mask_write 0XF8000B44 0x00000FFF 0x00000600
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mask_write 0XF8000B48 0x00000FFF 0x00000672
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mask_write 0XF8000B4C 0x00000FFF 0x00000672
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mask_write 0XF8000B50 0x00000FFF 0x00000674
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mask_write 0XF8000B54 0x00000FFF 0x00000674
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mask_write 0XF8000B58 0x00000FFF 0x00000600
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mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
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mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
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mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
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mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
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mask_write 0XF8000B6C 0x00007FFF 0x00000E09
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mask_write 0XF8000B70 0x00000001 0x00000001
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mask_write 0XF8000B70 0x00000021 0x00000020
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mask_write 0XF8000B70 0x07FEFFFF 0x00000823
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mask_write 0XF8000700 0x00003FFF 0x00000600
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mask_write 0XF8000704 0x00003FFF 0x00000602
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mask_write 0XF8000708 0x00003FFF 0x00000602
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mask_write 0XF800070C 0x00003FFF 0x00000602
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mask_write 0XF8000710 0x00003FFF 0x00000602
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mask_write 0XF8000714 0x00003FFF 0x00000602
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mask_write 0XF8000718 0x00003FFF 0x00000602
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mask_write 0XF800071C 0x00003FFF 0x00000600
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mask_write 0XF8000720 0x00003FFF 0x00000602
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mask_write 0XF8000724 0x00003FFF 0x00000600
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mask_write 0XF8000728 0x00003FFF 0x00000600
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mask_write 0XF800072C 0x00003FFF 0x00000600
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mask_write 0XF8000730 0x00003FFF 0x00000600
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mask_write 0XF8000734 0x00003FFF 0x00000600
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mask_write 0XF8000738 0x00003FFF 0x00000600
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mask_write 0XF800073C 0x00003FFF 0x00000600
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mask_write 0XF8000740 0x00003FFF 0x00000202
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mask_write 0XF8000744 0x00003FFF 0x00000202
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mask_write 0XF8000748 0x00003FFF 0x00000202
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mask_write 0XF800074C 0x00003FFF 0x00000202
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mask_write 0XF8000750 0x00003FFF 0x00000202
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mask_write 0XF8000754 0x00003FFF 0x00000202
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mask_write 0XF8000758 0x00003FFF 0x00000203
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mask_write 0XF800075C 0x00003FFF 0x00000203
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mask_write 0XF8000760 0x00003FFF 0x00000203
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mask_write 0XF8000764 0x00003FFF 0x00000203
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mask_write 0XF8000768 0x00003FFF 0x00000203
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mask_write 0XF800076C 0x00003FFF 0x00000203
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mask_write 0XF8000770 0x00003FFF 0x00000204
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mask_write 0XF8000774 0x00003FFF 0x00000205
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mask_write 0XF8000778 0x00003FFF 0x00000204
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mask_write 0XF800077C 0x00003FFF 0x00000205
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mask_write 0XF8000780 0x00003FFF 0x00000204
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mask_write 0XF8000784 0x00003FFF 0x00000204
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mask_write 0XF8000788 0x00003FFF 0x00000204
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mask_write 0XF800078C 0x00003FFF 0x00000204
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mask_write 0XF8000790 0x00003FFF 0x00000205
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mask_write 0XF8000794 0x00003FFF 0x00000204
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mask_write 0XF8000798 0x00003FFF 0x00000204
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mask_write 0XF800079C 0x00003FFF 0x00000204
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mask_write 0XF80007A0 0x00003FFF 0x00000280
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mask_write 0XF80007A4 0x00003FFF 0x00000280
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mask_write 0XF80007A8 0x00003FFF 0x00000280
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mask_write 0XF80007AC 0x00003FFF 0x00000280
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mask_write 0XF80007B0 0x00003FFF 0x00000280
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mask_write 0XF80007B4 0x00003FFF 0x00000280
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mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||
mask_write 0XF80007C8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||
mask_write 0XF8000830 0x003F003F 0x002E0032
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A204 0xFFFFFFFF 0x00000080
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
|
||||
mask_write 0XE000A208 0xFFFFFFFF 0x00000080
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00302301
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00100A00
|
||||
mask_write 0XF8000180 0x03F03F30 0x00100A00
|
||||
mask_write 0XF8000190 0x03F03F30 0x00101E00
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00101400
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004281A
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x00011054
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000003
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x0002C000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x0002C400
|
||||
mask_write 0XF8006134 0x000FFFFF 0x0002F003
|
||||
mask_write 0XF8006138 0x000FFFFF 0x0002EC03
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000077
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000077
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006168 0x001FFFFF 0x00000105
|
||||
mask_write 0XF800616C 0x001FFFFF 0x00000106
|
||||
mask_write 0XF8006170 0x001FFFFF 0x00000111
|
||||
mask_write 0XF8006174 0x001FFFFF 0x00000110
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000B7
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000B7
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000E09
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00000202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00000203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00000203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000205
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000204
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000205
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000204
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000205
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000204
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000204
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||
mask_write 0XF80007C8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||
mask_write 0XF8000830 0x003F003F 0x002E0032
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A204 0xFFFFFFFF 0x00000080
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
|
||||
mask_write 0XE000A208 0xFFFFFFFF 0x00000080
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00302301
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00100A00
|
||||
mask_write 0XF8000180 0x03F03F30 0x00100A00
|
||||
mask_write 0XF8000190 0x03F03F30 0x00101E00
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00101400
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004281A
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x00011054
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000003
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x0002C000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x0002C400
|
||||
mask_write 0XF8006134 0x000FFFFF 0x0002F003
|
||||
mask_write 0XF8006138 0x000FFFFF 0x0002EC03
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000077
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000077
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006168 0x001FFFFF 0x00000105
|
||||
mask_write 0XF800616C 0x001FFFFF 0x00000106
|
||||
mask_write 0XF8006170 0x001FFFFF 0x00000111
|
||||
mask_write 0XF8006174 0x001FFFFF 0x00000110
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000B7
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000B7
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000209
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00000202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00000203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00000203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00000203
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000205
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000204
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000205
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000204
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000205
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000204
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000204
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000204
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||
mask_write 0XF80007C8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||
mask_write 0XF8000830 0x003F003F 0x002E0032
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A204 0xFFFFFFFF 0x00000080
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
|
||||
mask_write 0XE000A208 0xFFFFFFFF 0x00000080
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_delay 0XF8F00200 1
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8000004 0x0000FFFF 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,130 @@
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
*******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158731
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 50000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 100000000
|
||||
#define FPGA2_FREQ 33333336
|
||||
#define FPGA3_FREQ 50000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,31 @@
|
||||
The Zynq project is provided pre-configured to run on the ZC702 hardware. This
|
||||
file describes how to run the project on the MicroZed.
|
||||
|
||||
1) Import the projects as described on the documentation page linked to by
|
||||
the Instructions_Readme file, but importing all four projects rather than the
|
||||
three described in the instructions. The forth project is MicroZed_hw_platform.
|
||||
|
||||
2) Select "File->New-Board Support Package" XSDK (Eclipse) IDE's File menu. In
|
||||
the pop up window, call the BSP project MicroZed_bsp, save the bsp in a convenient
|
||||
location, IMPORTANTLY ensure MicroZed_hw_platform is selected as the hardware
|
||||
platform and standalone is selected as the bsp type. Then click Finish to close
|
||||
the pop up window. The board support package settings window can then also be
|
||||
closed without any changes from the default values.
|
||||
|
||||
3) Right click the RTOSDemo project in the XSDK's project explorer window and
|
||||
select "Change referenced BSP" from the pop up window. Select MicroZed_bsp as
|
||||
the referenced BSP.
|
||||
|
||||
4) Change the definition of partstLED_OUTPUT from 10 to 47 in
|
||||
RTOSDemo/src/ParTest.c - that changes the output used to toggle the LED to be
|
||||
correct for the MicroZed hardware.
|
||||
|
||||
5) Select Clean and then from the XSDK's project menu.
|
||||
|
||||
6) Right click the RTOSDemo project again, and select Refresh from the pop up
|
||||
menu, before finally right clicking the project one final time and clicking
|
||||
Build.
|
||||
|
||||
7) Select MicroZed_hw_platform as the hardware platform in the "Target Setup"
|
||||
tab of the debug configuration.
|
||||
|
||||
Loading…
Reference in New Issue