pull/1/head
Richard Barry
19 years ago
parent
946da76519
commit
05023971cb
@ -0,0 +1,76 @@
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||||
/*
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FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
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||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
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||||
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||||
***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*----------------------------------------------------------*/
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 1
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#define configUSE_TICK_HOOK 0
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#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )
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#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) )
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#define configMAX_TASK_NAME_LEN ( 3 )
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#define configUSE_TRACE_FACILITY 0
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 0
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#define configUSE_CO_ROUTINES 1
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 0
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#define INCLUDE_uxTaskPriorityGet 0
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#define INCLUDE_vTaskDelete 0
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#define INCLUDE_vTaskCleanUpResources 0
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#define INCLUDE_vTaskSuspend 0
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#define INCLUDE_vTaskDelayUntil 0
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#define INCLUDE_vTaskDelay 1
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#endif /* FREERTOS_CONFIG_H */
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@ -0,0 +1,112 @@
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/*
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FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
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***************************************************************************
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*/
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/*-----------------------------------------------------------
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* Simple parallel port IO routines.
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*-----------------------------------------------------------*/
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/*
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*/
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#include "FreeRTOS.h"
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#include "Task.h"
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#include "partest.h"
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#include "pdc.h"
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#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
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#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )
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#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 )
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static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF;
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void vParTestInitialise( void )
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{
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PDCInit();
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PDCWrite( PDC_LED, ucOutputValue );
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}
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/*-----------------------------------------------------------*/
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void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
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{
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unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;
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vTaskSuspendAll();
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{
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if( uxLED < partstMAX_OUTPUT_LED )
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{
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ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;
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if( xValue == pdFALSE )
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{
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ucBit ^= ( unsigned portCHAR ) 0xff;
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ucOutputValue &= ucBit;
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}
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else
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{
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ucOutputValue |= ucBit;
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}
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PDCWrite( PDC_LED, ucOutputValue );
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}
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}
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xTaskResumeAll();
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}
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/*-----------------------------------------------------------*/
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void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
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{
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unsigned portCHAR ucBit;
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vTaskSuspendAll();
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{
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if( uxLED < partstMAX_OUTPUT_LED )
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{
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ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;
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if( ucOutputValue & ucBit )
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{
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ucOutputValue &= ~ucBit;
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}
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else
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{
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ucOutputValue |= ucBit;
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}
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PDCWrite( PDC_LED, ucOutputValue );
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}
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}
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xTaskResumeAll();
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}
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@ -0,0 +1,535 @@
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<?xml version="1.0" encoding="iso-8859-1"?>
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<project>
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<fileVersion>2</fileVersion>
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<configuration>
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<name>Debug</name>
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<outputs>
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<file>$PROJ_DIR$\..\..\Source\croutine.c</file>
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<file>$PROJ_DIR$\ewarm\Obj\cspy.pbi</file>
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<file>$PROJ_DIR$\ewarm\Exe\RTOSDemo.sim</file>
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<file>$PROJ_DIR$\ewarm\Obj\commstest.r79</file>
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<file>$PROJ_DIR$\ewarm\Obj\pdc.r79</file>
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<file>$PROJ_DIR$\ewarm\Obj\list.r79</file>
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<file>$PROJ_DIR$\hw_include\hw_ssi.h</file>
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<file>$PROJ_DIR$\ewarm\List\RTOSDemo.map</file>
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<file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>
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<file>$TOOLKIT_DIR$\inc\stddef.h</file>
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<file>$PROJ_DIR$\hw_include\hw_uart.h</file>
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<file>$PROJ_DIR$\standalone.xcl</file>
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<file>$PROJ_DIR$\hw_include\debug.h</file>
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<file>$PROJ_DIR$\hw_include\hw_adc.h</file>
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<file>$PROJ_DIR$\hw_include\hw_i2c.h</file>
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<file>$PROJ_DIR$\ewarm\Obj\registertest.r79</file>
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<file>$PROJ_DIR$\ewarm\Obj\commstest.pbi</file>
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<file>$PROJ_DIR$\ewarm\Obj\crhook.pbi</file>
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<file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>
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<file>$PROJ_DIR$\hw_include\interrupt.h</file>
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<file>$PROJ_DIR$\..\Common\include\crhook.h</file>
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<file>$PROJ_DIR$\ewarm\Obj\ParTest.pbi</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\tasks.pbi</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\startup.pbi</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\crflash.pbi</file>
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||||
<file>$PROJ_DIR$\..\Common\Minimal\crflash.c</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\startup.r79</file>
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<file>$PROJ_DIR$\..\..\Source\include\task.h</file>
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<file>$TOOLKIT_DIR$\inc\stdio.h</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\croutine.pbi</file>
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<file>$PROJ_DIR$\hw_include\i2c.h</file>
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||||
<file>$TOOLKIT_DIR$\inc\ysizet.h</file>
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||||
<file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.r79</file>
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||||
<file>$PROJ_DIR$\hw_include\gpio.h</file>
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<file>$PROJ_DIR$\hw_include\adc.h</file>
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||||
<file>$PROJ_DIR$\..\..\Source\include\queue.h</file>
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<file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\portasm.r79</file>
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||||
<file>$PROJ_DIR$\ewarm\Obj\tasks.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\cspy.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\port.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\queue.r79</file>
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||||
<file>$PROJ_DIR$\hw_include\hw_ints.h</file>
|
||||
<file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\crhook.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\qs_dk-lm3s316.pbi</file>
|
||||
<file>$PROJ_DIR$\ewarm\Exe\RTOSDemo.d79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\crflash.r79</file>
|
||||
<file>$PROJ_DIR$\FreeRTOSConfig.h</file>
|
||||
<file>$PROJ_DIR$\..\Common\include\partest.h</file>
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||||
<file>$PROJ_DIR$\hw_include\sysctl.h</file>
|
||||
<file>$PROJ_DIR$\hw_include\pdc.h</file>
|
||||
<file>$PROJ_DIR$\hw_include\DriverLib.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\ParTest.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd</file>
|
||||
<file>$PROJ_DIR$\qs_dk-lm3s316.c</file>
|
||||
<file>$TOOLKIT_DIR$\inc\yvals.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\main.r79</file>
|
||||
<file>$PROJ_DIR$\hw_include\hw_types.h</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\include\portable.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\list.pbi</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>
|
||||
<file>$PROJ_DIR$\hw_include\ssi.h</file>
|
||||
<file>$TOOLKIT_DIR$\inc\stdlib.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\queue.pbi</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\pdc.pbi</file>
|
||||
<file>$TOOLKIT_DIR$\inc\string.h</file>
|
||||
<file>$PROJ_DIR$\startup.c</file>
|
||||
<file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>
|
||||
<file>$PROJ_DIR$\..\..\utils\cspy.c</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\heap_1.r79</file>
|
||||
<file>$PROJ_DIR$\..\Common\Minimal\crhook.c</file>
|
||||
<file>$PROJ_DIR$\commstest.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\heap_1.pbi</file>
|
||||
<file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
|
||||
<file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\croutine.r79</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\include\list.h</file>
|
||||
<file>$PROJ_DIR$\..\Common\include\crflash.h</file>
|
||||
<file>$PROJ_DIR$\hw_include\diag.h</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\qs_dk-lm3s316.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\main.pbi</file>
|
||||
<file>$PROJ_DIR$\hw_include\hw_memmap.h</file>
|
||||
<file>$PROJ_DIR$\hw_include\uart.h</file>
|
||||
<file>$PROJ_DIR$\..\..\utils\pdc.c</file>
|
||||
<file>$PROJ_DIR$\hw_include\hw_nvic.h</file>
|
||||
<file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.h</file>
|
||||
<file>$PROJ_DIR$\commstest.c</file>
|
||||
<file>$PROJ_DIR$\main.c</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</file>
|
||||
<file>$PROJ_DIR$\ParTest\ParTest.c</file>
|
||||
<file>$PROJ_DIR$\registertest.s</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\list.c</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\queue.c</file>
|
||||
<file>$PROJ_DIR$\..\..\Source\tasks.c</file>
|
||||
<file>$PROJ_DIR$\hw_include\driverlib.r79</file>
|
||||
<file>$PROJ_DIR$\ewarm\Obj\port.pbi</file>
|
||||
<file>$PROJ_DIR$\hw_include\cspy.c</file>
|
||||
<file>$PROJ_DIR$\hw_include\pdc.c</file>
|
||||
<file>$PROJ_DIR$\hw_include\startup.c</file>
|
||||
</outputs>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\croutine.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 76</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 29</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 61</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77 61</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\Common\Minimal\crflash.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 47</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 24</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 18 9 56 74 86 75 43 68 31 8 48 59 36 61 77 35 49 78</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 18 9 56 74 75 43 68 31 8 48 59 36 61 77 35 49 78</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\ewarm\Exe\RTOSDemo.d79</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>XLINK</name>
|
||||
<file> 7 2</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>XLINK</name>
|
||||
<file> 11 53 3 47 76 39 70 5 57 4 40 37 41 15 26 38 97 32</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd</name>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>BILINK</name>
|
||||
<file> 21 16 24 29 1 73 60 81 65 98 64 23 22</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\qs_dk-lm3s316.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 80</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 45</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\startup.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 26</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 23</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\utils\cspy.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 39</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 1</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\Common\Minimal\crhook.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 44</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 17</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 18 9 56 74 86 75 43 68 31 8 48 59 36 61 77 35 20</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 18 9 56 74 75 43 68 31 8 48 59 36 61 77 35 20</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\utils\pdc.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 4</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 65</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>[ROOT_NODE]</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>XLINK</name>
|
||||
<file> 46 7 2</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\commstest.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 3</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 16</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 35 61 49 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77 35 61 49 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\main.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 57</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 81</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 28 56 74 86 75 43 68 31 18 9 8 48 59 36 27 77 35 61 49 78 72 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 28 56 74 75 43 68 31 18 9 8 48 59 36 27 77 35 61 49 78 72 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 70</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 73</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 63 56 74 86 75 43 68 31 18 9 8 48 59 36 27 77</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 63 56 74 75 43 68 31 18 9 8 48 59 36 27 77</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\ParTest\ParTest.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 53</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 21</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 49 51</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77 49 51</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\registertest.s</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>AARM</name>
|
||||
<file> 15</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\list.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 5</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 60</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 63 56 74 86 75 43 68 31 18 9 8 48 59 36 77</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 63 56 74 75 43 68 31 18 9 8 48 59 36 77</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 40</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 98</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>AARM</name>
|
||||
<file> 37</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>AARM</name>
|
||||
<file> 48</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\queue.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 41</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 64</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 63 56 74 86 75 43 68 31 66 18 9 8 48 59 36 27 77 61</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 63 56 74 75 43 68 31 66 18 9 8 48 59 36 27 77 61</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\tasks.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 38</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 22</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 28 56 74 86 75 43 68 31 63 66 18 9 8 48 59 36 27 77</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 28 56 74 75 43 68 31 63 66 18 9 8 48 59 36 27 77</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\cspy.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 39</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 1</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 79</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 79</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\pdc.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 4</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 65</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
<inputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 82 58 12 33 62 50 51</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 82 58 12 33 62 50 51</file>
|
||||
</tool>
|
||||
</inputs>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\startup.c</name>
|
||||
<outputs>
|
||||
<tool>
|
||||
<name>ICCARM</name>
|
||||
<file> 26</file>
|
||||
</tool>
|
||||
<tool>
|
||||
<name>BICOMP</name>
|
||||
<file> 23</file>
|
||||
</tool>
|
||||
</outputs>
|
||||
</file>
|
||||
</configuration>
|
||||
</project>
|
||||
|
||||
|
||||
@ -0,0 +1,509 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<project>
|
||||
<fileVersion>1</fileVersion>
|
||||
<configuration>
|
||||
<name>Debug</name>
|
||||
<toolchain>
|
||||
<name>ARM</name>
|
||||
</toolchain>
|
||||
<debug>1</debug>
|
||||
<settings>
|
||||
<name>C-SPY</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>13</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CInput</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CEndian</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCVariant</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacFile</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MemOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MemFile</name>
|
||||
<state>$TOOLKIT_DIR$\CONFIG\iolm3s101.ddf</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToEnable</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RunToName</name>
|
||||
<state>main</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CExtraOptionsCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CExtraOptions</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CFpuProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDDFArgumentProducer</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDownloadSuppressDownload</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDownloadVerifyAll</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCProductVersion</name>
|
||||
<state>4.39B</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDynDriverList</name>
|
||||
<state>JLINK_ID</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCLastSavedByProductVersion</name>
|
||||
<state>4.39B</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDownloadAttachToProgram</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>FlashLoaders</name>
|
||||
<state>,,,,(default),</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UseFlashLoader</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>ARMSIM_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>OCSimDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>ANGEL_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CCAngelHeartbeat</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CAngelCommunication</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CAngelCommBaud</name>
|
||||
<version>0</version>
|
||||
<state>3</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CAngelCommPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ANGELTCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoAngelLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AngelLogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>IARROM_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CRomLogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomLogFileEditB</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomCommunication</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomCommPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRomCommBaud</name>
|
||||
<version>0</version>
|
||||
<state>7</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>JLINK_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>6</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>JLinkSpeed</name>
|
||||
<state>32</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkDoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkLogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkHWResetDelay</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>JLinkInitialSpeed</name>
|
||||
<state>32</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDoJlinkMultiTarget</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCScanChainNonARMDevices</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkMultiTarget</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkIRLength</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkCommRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkTCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkResetRadio</name>
|
||||
<state>2</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkResetInitSeq</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkSpeedRadioV2</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCUSBDevice</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchUndef</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchSWI</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchData</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchPrefetch</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchIRQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchFIQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkBreakpointRadio</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkDoUpdateBreakpoints</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCJLinkUpdateBreakpoints</name>
|
||||
<state>main</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>MACRAIGOR_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>1</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>jtag</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>EmuSpeed</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>TCPIP</name>
|
||||
<state>aaa.bbb.ccc.ddd</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoLogfile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>LogFile</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoEmuMultiTarget</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>EmuMultiTarget</name>
|
||||
<state>0@ARM7TDMI</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>EmuHWReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CEmuCommBaud</name>
|
||||
<version>0</version>
|
||||
<state>4</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CEmuCommPort</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>jtago</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>UnusedAddr</name>
|
||||
<state>0x00800000</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCMacraigorHWResetDelay</name>
|
||||
<state></state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>RDI_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>1</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CRDIDriverDll</name>
|
||||
<state>Browse to your RDI driver</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRDILogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CRDILogFileEdit</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDIHWReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchReset</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchUndef</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchSWI</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchData</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchPrefetch</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchIRQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDICatchFIQ</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRDIUseETM</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>THIRDPARTY_ID</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CThirdPartyDriverDll</name>
|
||||
<state>Browse to your third-party driver</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CThirdPartyLogFileCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CThirdPartyLogFileEditB</name>
|
||||
<state>$TOOLKIT_DIR$\cspycomm.log</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OCDriverInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<debuggerPlugins>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
|
||||
<loadFlag>1</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
|
||||
<loadFlag>1</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$EW_DIR$\common\plugins\Stack\stack.ewplugin</file>
|
||||
<loadFlag>1</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
|
||||
<loadFlag>0</loadFlag>
|
||||
</plugin>
|
||||
</debuggerPlugins>
|
||||
</configuration>
|
||||
</project>
|
||||
|
||||
|
||||
@ -0,0 +1,891 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<project>
|
||||
<fileVersion>1</fileVersion>
|
||||
<configuration>
|
||||
<name>Debug</name>
|
||||
<toolchain>
|
||||
<name>ARM</name>
|
||||
</toolchain>
|
||||
<debug>1</debug>
|
||||
<settings>
|
||||
<name>General</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>9</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>GProcessorMode</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ExePath</name>
|
||||
<state>ewarm\Exe</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ObjPath</name>
|
||||
<state>ewarm\Obj</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ListPath</name>
|
||||
<state>ewarm\List</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>Variant</name>
|
||||
<version>5</version>
|
||||
<state>25</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GEndianMode</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GInterwork</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GStackAlign</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>Input variant</name>
|
||||
<version>1</version>
|
||||
<state>3</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>Input description</name>
|
||||
<state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>Output variant</name>
|
||||
<version>0</version>
|
||||
<state>3</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>Output description</name>
|
||||
<state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GOutputBinary</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>FPU</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGCoreOrChip</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GRuntimeLibSelect</name>
|
||||
<version>0</version>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GRuntimeLibSelectSlave</name>
|
||||
<version>0</version>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RTDescription</name>
|
||||
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RTConfigPath</name>
|
||||
<state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.h</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RTLibraryPath</name>
|
||||
<state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.r79</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGProductVersion</name>
|
||||
<state>4.39B</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGLastSavedByProductVersion</name>
|
||||
<state>4.40A</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraRules</name>
|
||||
<version>0</version>
|
||||
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralEnableMisra</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraVerbose</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGChipSelectEditMenu</name>
|
||||
<state>LM3S316 Luminary LM3S316</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>ICCARM</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>13</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>CCDefines</name>
|
||||
<state>BUILD_ALL</state>
|
||||
<state>ewarm</state>
|
||||
<state>IAR_ARMCM3_LM</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPreprocFile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPreprocComments</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPreprocLine</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCListCFile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCListCMnemonics</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCListCMessages</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCListAssFile</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCListAssSource</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCEnableRemarks</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagSuppress</name>
|
||||
<state>Pa050, Pa082</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagRemark</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagWarning</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagError</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCObjPrefix</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCOptSizeSpeed</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCOptimization</name>
|
||||
<version>0</version>
|
||||
<state>2</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCAllowList</name>
|
||||
<version>1</version>
|
||||
<state>1001010</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCObjUseModuleName</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCObjModuleName</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDebugInfo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IProcessorMode</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IEndianMode</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IStackAlign</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IInterwork</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IExtraOptionsCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IExtraOptions</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLangConformance</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCSignedPlainChar</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCRequirePrototypes</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCMultibyteSupport</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagWarnAreErr</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCompilerRuntimeInfo</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IFpuProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OutputFile</name>
|
||||
<state>$FILE_BNAME$.r79</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLangSelect</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCLibConfigHeader</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCOptSizeSpeedSlave</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCOptimizationSlave</name>
|
||||
<version>0</version>
|
||||
<state>2</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCCodeFunctions</name>
|
||||
<state>CODE</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCData</name>
|
||||
<state>DATA</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>PreInclude</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CompilerMisraRules</name>
|
||||
<version>0</version>
|
||||
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CompilerMisraOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCModuleTypeOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCModuleType</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCModuleTypeCmdlineProducer</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state>$PROJ_DIR$\</state>
|
||||
<state>$PROJ_DIR$\hw_include</state>
|
||||
<state>$PROJ_DIR$\..\common\include</state>
|
||||
<state>$PROJ_DIR$\..\..\source\include</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncludePath</name>
|
||||
<state>$TOOLKIT_DIR$\INC\</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>AARM</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>7</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>AObjPrefix</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AEndian</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ACaseSensitivity</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacroChars</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AWarnEnable</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AWarnWhat</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AWarnOne</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AWarnRange1</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AWarnRange2</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ADebug</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AltRegisterNames</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ADefines</name>
|
||||
<state>BUILD_ALL</state>
|
||||
<state>ewarm</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AList</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AListHeader</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AListing</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>Includes</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacDefs</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacExps</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MacExec</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OnlyAssed</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>MultiLine</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>PageLengthCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>PageLength</name>
|
||||
<state>80</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>TabSpacing</name>
|
||||
<state>8</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AXRef</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AXRefDefines</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AXRefInternal</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AXRefDual</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AFpuProcessor</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AOutputFile</name>
|
||||
<state>$FILE_BNAME$.r79</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AMultibyteSupport</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ALimitErrorsCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ALimitErrorsEdit</name>
|
||||
<state>100</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AIgnoreStdInclude</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AStdIncludes</name>
|
||||
<state>$TOOLKIT_DIR$\INC\</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AUserIncludes</name>
|
||||
<state>$PROJ_DIR$\</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AExtraOptionsCheckV2</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AExtraOptionsV2</name>
|
||||
<state></state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>CUSTOM</name>
|
||||
<archiveVersion>3</archiveVersion>
|
||||
<data>
|
||||
<extensions></extensions>
|
||||
<cmdline></cmdline>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>BICOMP</name>
|
||||
<archiveVersion>0</archiveVersion>
|
||||
<data/>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>BUILDACTION</name>
|
||||
<archiveVersion>1</archiveVersion>
|
||||
<data>
|
||||
<prebuild></prebuild>
|
||||
<postbuild></postbuild>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>XLINK</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>18</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>XOutOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OutputFile</name>
|
||||
<state>RTOSDemo.d79</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OutputFormat</name>
|
||||
<version>11</version>
|
||||
<state>16</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>FormatVariant</name>
|
||||
<version>7</version>
|
||||
<state>16</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>SecondaryOutputFile</name>
|
||||
<state>(None for the selected format)</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XDefines</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AlwaysOutput</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OverlapWarnings</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>NoGlobalCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XList</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>SegmentMap</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ListSymbols</name>
|
||||
<state>2</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>PageLengthCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>PageLength</name>
|
||||
<state>80</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XIncludes</name>
|
||||
<state>$TOOLKIT_DIR$\LIB\</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ModuleStatus</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XclOverride</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XclFile</name>
|
||||
<state>$PROJ_DIR$\standalone.xcl</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XclFileSlave</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoFill</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>FillerByte</name>
|
||||
<state>0xFF</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DoCrc</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcSize</name>
|
||||
<version>0</version>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcAlgo</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcPoly</name>
|
||||
<state>0x11021</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcCompl</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RangeCheckAlternatives</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>SuppressAllWarn</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>SuppressDiags</name>
|
||||
<state>w6</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>TreatAsWarn</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>TreatAsErr</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ModuleLocalSym</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcBitOrder</name>
|
||||
<version>0</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XExtraOptionsCheck</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XExtraOptions</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IncludeSuppressed</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OXLibIOConfig</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ModuleSummary</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>xcProgramEntryLabel</name>
|
||||
<state>ResetISR</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>DebugInformation</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RuntimeControl</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IoEmulation</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XcRTLibraryFile</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>AllowExtraOutput</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GenerateExtraOutput</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XExtraOutOverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ExtraOutputFile</name>
|
||||
<state>RTOSDemo.sim</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ExtraOutputFormat</name>
|
||||
<version>11</version>
|
||||
<state>60</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ExtraFormatVariant</name>
|
||||
<version>7</version>
|
||||
<state>2</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>xcOverrideProgramEntryLabel</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>xcProgramEntryLabelSelect</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ListOutputFormat</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>BufferedTermOutput</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OverlaySystemMap</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RawBinaryFile</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RawBinarySymbol</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RawBinarySegment</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>RawBinaryAlign</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XLinkMisraHandler</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcAlign</name>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CrcInitialValue</name>
|
||||
<state>0x0</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>XAR</name>
|
||||
<archiveVersion>2</archiveVersion>
|
||||
<data>
|
||||
<version>0</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>XARInputs</name>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XAROverride</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>XAROutput</name>
|
||||
<state>###Unitialized###</state>
|
||||
</option>
|
||||
</data>
|
||||
</settings>
|
||||
<settings>
|
||||
<name>BILINK</name>
|
||||
<archiveVersion>0</archiveVersion>
|
||||
<data/>
|
||||
</settings>
|
||||
</configuration>
|
||||
<group>
|
||||
<name>Demo Source</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\commstest.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\Common\Minimal\crflash.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\main.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\ParTest\ParTest.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\registertest.s</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>FreeRTOS Source</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\croutine.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\list.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\queue.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\Source\tasks.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Libraries</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\driverlib.r79</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Luminary Code</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\cspy.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\pdc.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\hw_include\startup.c</name>
|
||||
</file>
|
||||
</group>
|
||||
</project>
|
||||
|
||||
|
||||
@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\RTOSDemo.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@ -0,0 +1,294 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* The comms test Rx and Tx task and co-routine. See the comments at the top
|
||||
* of main.c for full information.
|
||||
*/
|
||||
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "queue.h"
|
||||
#include "croutine.h"
|
||||
|
||||
/* Demo application include files. */
|
||||
#include "partest.h"
|
||||
|
||||
/* Library include files. */
|
||||
#include "DriverLib.h"
|
||||
|
||||
/* The LED's toggled by the various tasks. */
|
||||
#define commsFAIL_LED ( 7 )
|
||||
#define commsRX_LED ( 6 )
|
||||
#define commsTX_LED ( 5 )
|
||||
|
||||
/* The length of the queue used to pass received characters to the Comms Rx
|
||||
task. */
|
||||
#define commsRX_QUEUE_LEN ( 5 )
|
||||
|
||||
/* The baud rate used by the UART comms tasks/co-routine. */
|
||||
#define commsBAUD_RATE ( 57600 )
|
||||
|
||||
/* FIFO setting for the UART. The FIFO is not used to create a better test. */
|
||||
#define commsFIFO_SET ( 0x10 )
|
||||
|
||||
/* The string that is transmitted on the UART contains sequentially the
|
||||
characters from commsFIRST_TX_CHAR to commsLAST_TX_CHAR. */
|
||||
#define commsFIRST_TX_CHAR '0'
|
||||
#define commsLAST_TX_CHAR 'z'
|
||||
|
||||
/* Just used to walk through the program memory in order that some random data
|
||||
can be generated. */
|
||||
#define commsTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )
|
||||
#define commsFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )
|
||||
|
||||
/* The time between transmissions of the string on UART 0. This is pseudo
|
||||
random in order to generate a bit or randomness to when the interrupts occur.*/
|
||||
#define commsMIN_TX_DELAY ( 40 / portTICK_RATE_MS )
|
||||
#define commsMAX_TX_DELAY ( ( portTickType ) 0x7f )
|
||||
#define commsOFFSET_TIME ( ( portTickType ) 3 )
|
||||
|
||||
/* The time the Comms Rx task should wait to receive a character. This should
|
||||
be slightly longer than the time between transmissions. If we do not receive
|
||||
a character after this time then there must be an error in the transmission or
|
||||
the timing of the transmission. */
|
||||
#define commsRX_DELAY ( commsMAX_TX_DELAY + 20 )
|
||||
|
||||
|
||||
static unsigned portBASE_TYPE uxCommsErrorStatus = pdPASS;
|
||||
|
||||
/* The queue used to pass characters out of the ISR. */
|
||||
static xQueueHandle xCommsQueue;
|
||||
|
||||
/* The next character to transmit. */
|
||||
static portCHAR cNextChar;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vSerialInit( void )
|
||||
{
|
||||
/* Create the queue used to communicate between the UART ISR and the Comms
|
||||
Rx task. */
|
||||
xCommsQueue = xQueueCreate( commsRX_QUEUE_LEN, sizeof( portCHAR ) );
|
||||
|
||||
/* Enable the UART. GPIOA has already been initialised. */
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
|
||||
|
||||
/* Set GPIO A0 and A1 as peripheral function. They are used to output the
|
||||
UART signals. */
|
||||
GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );
|
||||
|
||||
/* Configure the UART for 8-N-1 operation. */
|
||||
UARTConfigSet( UART0_BASE, commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );
|
||||
|
||||
/* We dont want to use the fifo. This is for test purposes to generate
|
||||
as many interrupts as possible. */
|
||||
HWREG( UART0_BASE + UART_O_LCR_H ) &= ~commsFIFO_SET;
|
||||
|
||||
/* Enable both Rx and Tx interrupts. */
|
||||
HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );
|
||||
IntEnable( INT_UART0 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
|
||||
{
|
||||
portTickType xDelayPeriod;
|
||||
static unsigned portLONG *pulRandomBytes = commsFIRST_PROGRAM_BYTES;
|
||||
|
||||
/* Co-routine MUST start with a call to crSTART. */
|
||||
crSTART( xHandle );
|
||||
|
||||
for(;;)
|
||||
{
|
||||
/* Was the previously transmitted string received correctly? */
|
||||
if( uxCommsErrorStatus != pdPASS )
|
||||
{
|
||||
/* An error was encountered so set the error LED. */
|
||||
vParTestSetLED( commsFAIL_LED, pdTRUE );
|
||||
}
|
||||
|
||||
/* The next character to Tx is the first in the string. */
|
||||
cNextChar = commsFIRST_TX_CHAR;
|
||||
|
||||
UARTIntDisable( UART0_BASE, UART_INT_TX );
|
||||
{
|
||||
/* Send the first character. */
|
||||
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
|
||||
{
|
||||
HWREG( UART0_BASE + UART_O_DR ) = cNextChar;
|
||||
}
|
||||
|
||||
/* Move the variable to the char to Tx on so the ISR transmits
|
||||
the next character in the string once this one has completed. */
|
||||
cNextChar++;
|
||||
}
|
||||
UARTIntEnable(UART0_BASE, UART_INT_TX);
|
||||
|
||||
/* Toggle the LED to show a new string is being transmitted. */
|
||||
vParTestToggleLED( commsTX_LED );
|
||||
|
||||
/* Delay before we start the string off again. A pseudo-random delay
|
||||
is used as this will provide a better test. */
|
||||
xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );
|
||||
|
||||
pulRandomBytes++;
|
||||
if( pulRandomBytes > commsTOTAL_PROGRAM_MEMORY )
|
||||
{
|
||||
pulRandomBytes = commsFIRST_PROGRAM_BYTES;
|
||||
}
|
||||
|
||||
/* Make sure we don't wait too long... */
|
||||
xDelayPeriod &= commsMAX_TX_DELAY;
|
||||
|
||||
/* ...but we do want to wait. */
|
||||
if( xDelayPeriod < commsMIN_TX_DELAY )
|
||||
{
|
||||
xDelayPeriod = commsMIN_TX_DELAY;
|
||||
}
|
||||
|
||||
/* Block for the random(ish) time. */
|
||||
crDELAY( xHandle, xDelayPeriod );
|
||||
}
|
||||
|
||||
/* Co-routine MUST end with a call to crEND. */
|
||||
crEND();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vUART_ISR( void )
|
||||
{
|
||||
unsigned portLONG ulStatus;
|
||||
portCHAR cRxedChar;
|
||||
portBASE_TYPE xTaskWokenByPost = pdFALSE;
|
||||
|
||||
/* What caused the interrupt. */
|
||||
ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );
|
||||
|
||||
/* Clear the interrupt. */
|
||||
UARTIntClear( UART0_BASE, ulStatus );
|
||||
|
||||
/* Was an Rx interrpt pending? */
|
||||
if( ulStatus & UART_INT_RX )
|
||||
{
|
||||
if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )
|
||||
{
|
||||
/* Get the char from the buffer and post it onto the queue of
|
||||
Rxed chars. Posting the character should wake the task that is
|
||||
blocked on the queue waiting for characters. */
|
||||
cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );
|
||||
xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );
|
||||
}
|
||||
}
|
||||
|
||||
/* Was a Tx interrupt pending? */
|
||||
if( ulStatus & UART_INT_TX )
|
||||
{
|
||||
/* Send the next character in the string. We are not using the FIFO. */
|
||||
if( cNextChar <= commsLAST_TX_CHAR )
|
||||
{
|
||||
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
|
||||
{
|
||||
HWREG( UART0_BASE + UART_O_DR ) = cNextChar;
|
||||
}
|
||||
cNextChar++;
|
||||
}
|
||||
}
|
||||
|
||||
if( xTaskWokenByPost )
|
||||
{
|
||||
/* If a task was woken by the character being received then we force
|
||||
a context switch to occur in case the task is of higher priority than
|
||||
the currently executing task (i.e. the task that this interrupt
|
||||
interrupted.) */
|
||||
portEND_SWITCHING_ISR( xTaskWokenByPost );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vCommsRxTask( void * pvParameters )
|
||||
{
|
||||
static portCHAR cRxedChar, cExpectedChar;
|
||||
|
||||
/* Set the char we expect to receive to the start of the string. */
|
||||
cExpectedChar = commsFIRST_TX_CHAR;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait for a character to be received. */
|
||||
xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, commsRX_DELAY );
|
||||
|
||||
/* Was the character recived (if any) the expected character. */
|
||||
if( cRxedChar != cExpectedChar )
|
||||
{
|
||||
/* Got an unexpected character. This can sometimes occur when
|
||||
reseting the system using the debugger leaving characters already
|
||||
in the UART regsters. */
|
||||
uxCommsErrorStatus = pdFAIL;
|
||||
|
||||
/* Resync by waiting for the end of the current string. */
|
||||
while( cRxedChar != commsLAST_TX_CHAR )
|
||||
{
|
||||
while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );
|
||||
}
|
||||
|
||||
/* The next expected character is the start of the string again. */
|
||||
cExpectedChar = commsFIRST_TX_CHAR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if( cExpectedChar == commsLAST_TX_CHAR )
|
||||
{
|
||||
/* We have reached the end of the string - we now expect to
|
||||
receive the first character in the string again. The LED is
|
||||
toggled to indicate that the entire string was received without
|
||||
error. */
|
||||
vParTestToggleLED( commsRX_LED );
|
||||
cExpectedChar = commsFIRST_TX_CHAR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We got the expected character, we now expect to receive the
|
||||
next character in the string. */
|
||||
cExpectedChar++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
unsigned portBASE_TYPE uxGetCommsStatus( void )
|
||||
{
|
||||
return uxCommsErrorStatus;
|
||||
}
|
||||
@ -0,0 +1,54 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef COMMS_TEST_H
|
||||
#define COMMS_TEST_H
|
||||
|
||||
/*
|
||||
* Initialisation routine for the UART.
|
||||
*/
|
||||
void vSerialInit( void );
|
||||
|
||||
/*
|
||||
* The task that receives the characters from UART 0.
|
||||
*/
|
||||
void vCommsRxTask( void * pvParameters );
|
||||
|
||||
/*
|
||||
* The co-routine that periodically initiates the transmission of the string on
|
||||
* the UART.
|
||||
*/
|
||||
void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
|
||||
|
||||
unsigned portBASE_TYPE uxGetCommsStatus( void );
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,22 @@
|
||||
#ifndef INCLUDE_DRIVER_LIB_H
|
||||
#define INCLUDE_DRIVER_LIB_H
|
||||
|
||||
#include "hw_ints.h"
|
||||
#include "hw_uart.h"
|
||||
#include "hw_memmap.h"
|
||||
#include "hw_types.h"
|
||||
#include "hw_nvic.h"
|
||||
#include "hw_ssi.h"
|
||||
#include "hw_i2c.h"
|
||||
#include "hw_adc.h"
|
||||
|
||||
#include "gpio.h"
|
||||
#include "interrupt.h"
|
||||
#include "sysctl.h"
|
||||
#include "uart.h"
|
||||
#include "ssi.h"
|
||||
#include "pdc.h"
|
||||
#include "i2c.h"
|
||||
#include "adc.h"
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,192 @@
|
||||
// Generated : 06/01/06 20:29:52
|
||||
//**********************************************************************
|
||||
// XLINK template command file to be used with the ICCARM C/C++ Compiler
|
||||
//
|
||||
// Usage: xlink -f lnkarm <your_object_file(s)>
|
||||
// -s <program start label> <C/C++ runtime library>
|
||||
//
|
||||
// $Revision: 1.3 $
|
||||
//
|
||||
//**********************************************************************
|
||||
|
||||
//*************************************************************************
|
||||
// In this file it is assumed that the system has the following
|
||||
// memory layout:
|
||||
//
|
||||
// Exception vectors [0x000000--0x00001F] RAM or ROM
|
||||
// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory)
|
||||
// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory)
|
||||
//
|
||||
// -------------
|
||||
// Code segments - may be placed anywhere in memory.
|
||||
// -------------
|
||||
//
|
||||
// INTVEC -- Exception vector table.
|
||||
// SWITAB -- Software interrupt vector table.
|
||||
// ICODE -- Startup (cstartup) and exception code.
|
||||
// DIFUNCT -- Dynamic initialization vectors used by C++.
|
||||
// CODE -- Compiler generated code.
|
||||
// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM)
|
||||
// CODE_ID -- Initializer for CODE_I (ROM).
|
||||
//
|
||||
// -------------
|
||||
// Data segments - may be placed anywhere in memory.
|
||||
// -------------
|
||||
//
|
||||
// CSTACK -- The stack used by C/C++ programs (system and user mode).
|
||||
// IRQ_STACK -- The stack used by IRQ service routines.
|
||||
// SVC_STACK -- The stack used in supervisor mode
|
||||
// (Define other exception stacks as needed for
|
||||
// FIQ, ABT, UND).
|
||||
// HEAP -- The heap used by malloc and free in C and new and
|
||||
// delete in C++.
|
||||
// INITTAB -- Table containing addresses and sizes of segments that
|
||||
// need to be initialized at startup (by cstartup).
|
||||
// CHECKSUM -- The linker places checksum byte(s) in this segment,
|
||||
// when the -J linker command line option is used.
|
||||
// DATA_y -- Data objects.
|
||||
//
|
||||
// Where _y can be one of:
|
||||
//
|
||||
// _AN -- Holds uninitialized located objects, i.e. objects with
|
||||
// an absolute location given by the @ operator or the
|
||||
// #pragma location directive. Since these segments
|
||||
// contain objects which already have a fixed address,
|
||||
// they should not be mentioned in this linker command
|
||||
// file.
|
||||
// _C -- Constants (ROM).
|
||||
// _I -- Initialized data (RAM).
|
||||
// _ID -- The original content of _I (copied to _I by cstartup) (ROM).
|
||||
// _N -- Uninitialized data (RAM).
|
||||
// _Z -- Zero initialized data (RAM).
|
||||
//
|
||||
// Note: Be sure to use end values for the defined address ranges.
|
||||
// Otherwise, the linker may allocate space outside the
|
||||
// intended memory range.
|
||||
//*************************************************************************
|
||||
|
||||
//************************************************
|
||||
// Inform the linker about the CPU family used.
|
||||
//************************************************
|
||||
|
||||
-carm
|
||||
|
||||
//*************************************************************************
|
||||
// Segment placement - General information
|
||||
//
|
||||
// All numbers in the segment placement command lines below are interpreted
|
||||
// as hexadecimal unless they are immediately preceded by a '.', which
|
||||
// denotes decimal notation.
|
||||
//
|
||||
// When specifying the segment placement using the -P instead of the -Z
|
||||
// option, the linker is free to split each segment into its segment parts
|
||||
// and randomly place these parts within the given ranges in order to
|
||||
// achieve a more efficient memory usage. One disadvantage, however, is
|
||||
// that it is not possible to find the start or end address (using
|
||||
// the assembler operators .sfb./.sfe.) of a segment which has been split
|
||||
// and reformed.
|
||||
//
|
||||
// When generating an output file which is to be used for programming
|
||||
// external ROM/Flash devices, the -M linker option is very useful
|
||||
// (see xlink.pdf for details).
|
||||
//*************************************************************************
|
||||
|
||||
|
||||
//*************************************************************************
|
||||
// Read-only segments mapped to ROM.
|
||||
//*************************************************************************
|
||||
|
||||
//************************************************
|
||||
// Address range for reset and exception
|
||||
// vectors (INTVEC).
|
||||
// The vector area is 32 bytes,
|
||||
// an additional 32 bytes is allocated for the
|
||||
// constant table used by ldr PC in cstartup.s79.
|
||||
//************************************************
|
||||
|
||||
-Z(CODE)INTVEC=0-3F
|
||||
|
||||
//************************************************
|
||||
// Startup code and exception routines (ICODE).
|
||||
//************************************************
|
||||
|
||||
-Z(CODE)ICODE,DIFUNCT=8000-FFFFF
|
||||
-Z(CODE)SWITAB=8000-FFFFF
|
||||
|
||||
//************************************************
|
||||
// Code segments may be placed anywhere.
|
||||
//************************************************
|
||||
|
||||
-Z(CODE)CODE=8000-FFFFF
|
||||
|
||||
//************************************************
|
||||
// Original ROM location for __ramfunc code copied
|
||||
// to and executed from RAM.
|
||||
//************************************************
|
||||
|
||||
-Z(CONST)CODE_ID=8000-FFFFF
|
||||
|
||||
//************************************************
|
||||
// Various constants and initializers.
|
||||
//************************************************
|
||||
|
||||
-Z(CONST)INITTAB,DATA_ID,DATA_C=8000-FFFFF
|
||||
-Z(CONST)CHECKSUM=8000-FFFFF
|
||||
|
||||
//*************************************************************************
|
||||
// Read/write segments mapped to RAM.
|
||||
//*************************************************************************
|
||||
|
||||
//************************************************
|
||||
// Data segments.
|
||||
//************************************************
|
||||
|
||||
-Z(DATA)DATA_I,DATA_Z,DATA_N=100000-7FFFFF
|
||||
|
||||
//************************************************
|
||||
// __ramfunc code copied to and executed from RAM.
|
||||
//************************************************
|
||||
|
||||
-Z(DATA)CODE_I=100000-7FFFFF
|
||||
|
||||
//************************************************
|
||||
// ICCARM produces code for __ramfunc functions in
|
||||
// CODE_I segments. The -Q XLINK command line
|
||||
// option redirects XLINK to emit the code in the
|
||||
// CODE_ID segment instead, but to keep symbol and
|
||||
// debug information associated with the CODE_I
|
||||
// segment, where the code will execute.
|
||||
//************************************************
|
||||
|
||||
-QCODE_I=CODE_ID
|
||||
|
||||
//*************************************************************************
|
||||
// Stack and heap segments.
|
||||
//*************************************************************************
|
||||
|
||||
-Z(DATA)CSTACK+200=100000-7FFFFF
|
||||
-Z(DATA)IRQ_STACK+100=100000-7FFFFF
|
||||
-Z(DATA)HEAP+8000=100000-7FFFFF
|
||||
|
||||
//**********************************************************************
|
||||
// Output user defined segments
|
||||
//**********************************************************************
|
||||
|
||||
|
||||
|
||||
//*************************************************************************
|
||||
// ELF/DWARF support.
|
||||
//
|
||||
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
|
||||
// Available format specifiers are:
|
||||
//
|
||||
// "-yn": Suppress DWARF debug output
|
||||
// "-yp": Multiple ELF program sections
|
||||
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
|
||||
//
|
||||
// "-Felf" and the format specifiers can also be supplied directly as
|
||||
// command line options, or selected from the Xlink Output tab in the
|
||||
// IAR Embedded Workbench.
|
||||
//*************************************************************************
|
||||
|
||||
// -Felf
|
||||
@ -0,0 +1,120 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// adc.h - ADC headers for using the ADC driver functions.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __ADC_H__
|
||||
#define __ADC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
|
||||
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
|
||||
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
|
||||
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
|
||||
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
|
||||
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
|
||||
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
|
||||
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
|
||||
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
|
||||
#define ADC_CTL_IE 0x00000040 // Interrupt enable
|
||||
#define ADC_CTL_END 0x00000020 // Sequence end select
|
||||
#define ADC_CTL_D 0x00000010 // Differential select
|
||||
#define ADC_CTL_CH0 0x00000000 // Input channel 0
|
||||
#define ADC_CTL_CH1 0x00000001 // Input channel 1
|
||||
#define ADC_CTL_CH2 0x00000002 // Input channel 2
|
||||
#define ADC_CTL_CH3 0x00000003 // Input channel 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ADCIntUnregister(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern unsigned long ADCIntStatus(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
tBoolean bMasked);
|
||||
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceEnable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceDisable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulTrigger,
|
||||
unsigned long ulPriority);
|
||||
extern void ADCSequenceStepConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulStep,
|
||||
unsigned long ulConfig);
|
||||
extern long ADCSequenceOverflow(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern long ADCSequenceUnderflow(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern long ADCSequenceDataGet(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long *pulBuffer);
|
||||
extern void ADCProcessorTrigger(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulFactor);
|
||||
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulStep,
|
||||
unsigned long ulConfig);
|
||||
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long *pulBuffer,
|
||||
unsigned long ulCount);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __ADC_H__
|
||||
@ -0,0 +1,130 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __ASMDEFS_H__
|
||||
#define __ASMDEFS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for EW-ARM.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef ewarm
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __TEXT__ rseg CODE:CODE(2)
|
||||
#define __DATA__ rseg DATA:DATA(2)
|
||||
#define __BSS__ rseg DATA:DATA(2)
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ alignrom 4
|
||||
#define __END__ end
|
||||
#define __EXPORT__ export
|
||||
#define __IMPORT__ import
|
||||
#define __LABEL__
|
||||
#define __STR__ dcb
|
||||
#define __THUMB_LABEL__
|
||||
#define __WORD__ dcd
|
||||
|
||||
#endif // ewarm
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for GCC.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef gcc
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
|
||||
#endif // gcc
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for RV-MDK.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef rvmdk
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
thumb
|
||||
require8
|
||||
preserve8
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __TEXT__ area ||.text||, code, readonly, align=2
|
||||
#define __DATA__ area ||.data||, data, align=2
|
||||
#define __BSS__ area ||.bss||, noinit, align=2
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ align 4
|
||||
#define __END__ end
|
||||
#define __EXPORT__ export
|
||||
#define __IMPORT__ import
|
||||
#define __LABEL__
|
||||
#define __STR__ dcb
|
||||
#define __THUMB_LABEL__
|
||||
#define __WORD__ dcd
|
||||
|
||||
#endif // rvmdk
|
||||
|
||||
#endif // __ASMDEF_H__
|
||||
@ -0,0 +1,120 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// comp.h - Prototypes for the analog comparator driver.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __COMP_H__
|
||||
#define __COMP_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorConfigure() as the ulConfig
|
||||
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
|
||||
// the values may be selected and ORed together will values from the other
|
||||
// groups.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
|
||||
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
|
||||
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
|
||||
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
|
||||
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
|
||||
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
|
||||
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
|
||||
#define COMP_INT_LOW 0x00000000 // Interrupt when low
|
||||
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
|
||||
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
|
||||
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
|
||||
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
|
||||
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
|
||||
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
|
||||
#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal
|
||||
#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
|
||||
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
|
||||
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
|
||||
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
|
||||
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
|
||||
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
|
||||
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
|
||||
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
|
||||
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
|
||||
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
|
||||
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
|
||||
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
|
||||
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
|
||||
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
|
||||
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
|
||||
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
|
||||
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
|
||||
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
|
||||
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
|
||||
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
|
||||
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
|
||||
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
|
||||
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
|
||||
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
|
||||
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
|
||||
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
|
||||
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
|
||||
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
|
||||
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulConfig);
|
||||
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
|
||||
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
|
||||
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ComparatorIntUnregister(unsigned long ulBase,
|
||||
unsigned long ulComp);
|
||||
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
|
||||
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
|
||||
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
|
||||
tBoolean bMasked);
|
||||
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __COMP_H__
|
||||
@ -0,0 +1,40 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// cpu.h - Prototypes for the CPU instruction wrapper functions.
|
||||
//
|
||||
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __CPU_H__
|
||||
#define __CPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void CPUcpsid(void);
|
||||
extern void CPUcpsie(void);
|
||||
extern void CPUwfi(void);
|
||||
|
||||
#endif // __CPU_H__
|
||||
@ -0,0 +1,119 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// cspy.c - Routines for simply ignoring the debugger communciation APIs in
|
||||
// C-Spy for now.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include "diag.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Open a handle for stdio functions (both stdin and stdout).
|
||||
//
|
||||
//*****************************************************************************
|
||||
int
|
||||
DiagOpenStdio(void)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Open a host file system file.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int
|
||||
DiagOpen(const char *pcName, int iMode)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close a host file system file.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int
|
||||
DiagClose(int iHandle)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Write data to a host file system file.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int
|
||||
DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, int iMode)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Read data from a host file system file.
|
||||
//
|
||||
//*****************************************************************************
|
||||
int
|
||||
DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Get the length of a host file system file.
|
||||
//
|
||||
//*****************************************************************************
|
||||
long
|
||||
DiagFlen(int iHandle)
|
||||
{
|
||||
return(-1);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Terminate the application.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
DiagExit(int iRet)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Get the command line arguments from the debugger.
|
||||
//
|
||||
//*****************************************************************************
|
||||
char *
|
||||
DiagCommandString(char *pcBuf, unsigned long ulLen)
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
@ -0,0 +1,56 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// debug.h - Macros for assisting debug of the driver library.
|
||||
//
|
||||
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototype for the function that is called when an invalid argument is passed
|
||||
// to an API. This is only used when doing a DEBUG build.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(char *pcFilename, unsigned long ulLine);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The ASSERT macro, which does the actual assertion checking. Typically, this
|
||||
// will be for procedure arguments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
#define ASSERT(expr) { \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#endif // __DEBUG_H__
|
||||
@ -0,0 +1,67 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// diag.h - Prototypes for the diagnostic functions.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DIAG_H__
|
||||
#define __DIAG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed as the iMode parater to DiagOpen, DiagRead, and
|
||||
// DiagWrite.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define OPEN_R 0 // read access
|
||||
#define OPEN_W 4 // write access
|
||||
#define OPEN_A 8 // append to file
|
||||
#define OPEN_B 1 // binary access
|
||||
#define OPEN_PLUS 2 // read and write access
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern int DiagOpenStdio(void);
|
||||
extern int DiagOpen(const char *pcName, int iMode);
|
||||
extern int DiagClose(int iHandle);
|
||||
extern int DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen,
|
||||
int iMode);
|
||||
extern int DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode);
|
||||
extern long DiagFlen(int iHandle);
|
||||
extern void DiagExit(int iRet);
|
||||
extern char *DiagCommandString(char *pcBuf, unsigned long ulLen);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DIAG_H__
|
||||
Binary file not shown.
@ -0,0 +1,75 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// flash.h - Prototypes for the flash driver.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __FLASH_H__
|
||||
#define __FLASH_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FlashProtectSet(), and returned by
|
||||
// FlashProtectGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef enum
|
||||
{
|
||||
FlashReadWrite, // Flash can be read and written
|
||||
FlashReadOnly, // Flash can only be read
|
||||
FlashExecuteOnly // Flash can only be executed
|
||||
}
|
||||
tFlashProtection;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern unsigned long FlashUsecGet(void);
|
||||
extern void FlashUsecSet(unsigned long ulClocks);
|
||||
extern long FlashErase(unsigned long ulAddress);
|
||||
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
|
||||
unsigned long ulCount);
|
||||
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
|
||||
extern long FlashProtectSet(unsigned long ulAddress,
|
||||
tFlashProtection eProtect);
|
||||
extern long FlashProtectSave(void);
|
||||
extern void FlashIntRegister(void (*pfnHandler)(void));
|
||||
extern void FlashIntUnregister(void);
|
||||
extern void FlashIntEnable(unsigned long ulIntFlags);
|
||||
extern void FlashIntDisable(unsigned long ulIntFlags);
|
||||
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
|
||||
extern void FlashIntClear(unsigned long ulIntFlags);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __FLASH_H__
|
||||
@ -0,0 +1,136 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// gpio.h - Defines and Macros for GPIO API.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following values define the bit field for the ucPins argument to several
|
||||
// of the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
|
||||
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
|
||||
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
|
||||
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
|
||||
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
|
||||
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
|
||||
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
|
||||
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
|
||||
// returned from GPIODirModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
|
||||
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
|
||||
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
|
||||
// returned from GPIOIntTypeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
|
||||
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
|
||||
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
|
||||
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
|
||||
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
|
||||
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
|
||||
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
|
||||
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
|
||||
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
|
||||
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
|
||||
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
|
||||
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
|
||||
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
|
||||
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulPinIO);
|
||||
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulIntType);
|
||||
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulStrength,
|
||||
unsigned long ulPadType);
|
||||
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
|
||||
unsigned long *pulStrength,
|
||||
unsigned long *pulPadType);
|
||||
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
|
||||
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPortIntRegister(unsigned long ulPort,
|
||||
void (*pfIntHandler)(void));
|
||||
extern void GPIOPortIntUnregister(unsigned long ulPort);
|
||||
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned char ucVal);
|
||||
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __GPIO_H__
|
||||
@ -0,0 +1,329 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_adc.h - Macros used when accessing the ADC hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_ADC_H__
|
||||
#define __HW_ADC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the ADC registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_O_ACTSS 0x00000000 // Active sample register
|
||||
#define ADC_O_RIS 0x00000004 // Raw interrupt status register
|
||||
#define ADC_O_IM 0x00000008 // Interrupt mask register
|
||||
#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
|
||||
#define ADC_O_OSTAT 0x00000010 // Overflow status register
|
||||
#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
|
||||
#define ADC_O_USTAT 0x00000018 // Underflow status register
|
||||
#define ADC_O_SSPRI 0x00000020 // Channel priority register
|
||||
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
|
||||
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
|
||||
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
|
||||
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
|
||||
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
|
||||
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
|
||||
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
|
||||
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
|
||||
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
|
||||
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
|
||||
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
|
||||
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
|
||||
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
|
||||
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
|
||||
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
|
||||
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
|
||||
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
|
||||
#define ADC_O_TMLB 0x00000100 // Test mode loopback register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the ADC sequence registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
|
||||
#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
|
||||
#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
|
||||
#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
|
||||
#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
|
||||
#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_ACTSS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
|
||||
#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
|
||||
#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
|
||||
#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
|
||||
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
|
||||
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
|
||||
#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
|
||||
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
|
||||
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
|
||||
#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_ISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
|
||||
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
|
||||
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
|
||||
#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_OSTAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
|
||||
#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
|
||||
#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
|
||||
#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_EMUX register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
|
||||
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
|
||||
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
|
||||
#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
|
||||
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
|
||||
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
|
||||
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
|
||||
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
|
||||
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
|
||||
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
|
||||
#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
|
||||
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
|
||||
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
|
||||
#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
|
||||
#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
|
||||
#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
|
||||
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
|
||||
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
|
||||
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
|
||||
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
|
||||
#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
|
||||
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
|
||||
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
|
||||
#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
|
||||
#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
|
||||
#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
|
||||
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
|
||||
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
|
||||
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
|
||||
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
|
||||
#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
|
||||
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
|
||||
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
|
||||
#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
|
||||
#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
|
||||
#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
|
||||
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
|
||||
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
|
||||
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
|
||||
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
|
||||
#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
|
||||
#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
|
||||
#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
|
||||
#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_USTAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
|
||||
#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
|
||||
#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
|
||||
#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_SSPRI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
|
||||
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
|
||||
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
|
||||
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
|
||||
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
|
||||
#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
|
||||
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
|
||||
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
|
||||
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
|
||||
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
|
||||
#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
|
||||
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
|
||||
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
|
||||
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
|
||||
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
|
||||
#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
|
||||
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
|
||||
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
|
||||
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
|
||||
#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_PSSI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
|
||||
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
|
||||
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
|
||||
#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,
|
||||
// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_SSMUX_MUX7_MASK 0x30000000 // 8th mux select mask
|
||||
#define ADC_SSMUX_MUX6_MASK 0x03000000 // 7th mux select mask
|
||||
#define ADC_SSMUX_MUX5_MASK 0x00300000 // 6th mux select mask
|
||||
#define ADC_SSMUX_MUX4_MASK 0x00030000 // 5th mux select mask
|
||||
#define ADC_SSMUX_MUX3_MASK 0x00003000 // 4th mux select mask
|
||||
#define ADC_SSMUX_MUX2_MASK 0x00000300 // 3rd mux select mask
|
||||
#define ADC_SSMUX_MUX1_MASK 0x00000030 // 2nd mux select mask
|
||||
#define ADC_SSMUX_MUX0_MASK 0x00000003 // 1st mux select mask
|
||||
#define ADC_SSMUX_MUX7_SHIFT 28
|
||||
#define ADC_SSMUX_MUX6_SHIFT 24
|
||||
#define ADC_SSMUX_MUX5_SHIFT 20
|
||||
#define ADC_SSMUX_MUX4_SHIFT 16
|
||||
#define ADC_SSMUX_MUX3_SHIFT 12
|
||||
#define ADC_SSMUX_MUX2_SHIFT 8
|
||||
#define ADC_SSMUX_MUX1_SHIFT 4
|
||||
#define ADC_SSMUX_MUX0_SHIFT 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,
|
||||
// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
|
||||
#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
|
||||
#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
|
||||
#define ADC_SSCTL_D7 0x10000000 // 8th differential select
|
||||
#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
|
||||
#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
|
||||
#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
|
||||
#define ADC_SSCTL_D6 0x01000000 // 7th differential select
|
||||
#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
|
||||
#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
|
||||
#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
|
||||
#define ADC_SSCTL_D5 0x00100000 // 6th differential select
|
||||
#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
|
||||
#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
|
||||
#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
|
||||
#define ADC_SSCTL_D4 0x00010000 // 5th differential select
|
||||
#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
|
||||
#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
|
||||
#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
|
||||
#define ADC_SSCTL_D3 0x00001000 // 4th differential select
|
||||
#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
|
||||
#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
|
||||
#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
|
||||
#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
|
||||
#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
|
||||
#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
|
||||
#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
|
||||
#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
|
||||
#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
|
||||
#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
|
||||
#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
|
||||
#define ADC_SSCTL_D0 0x00000001 // 1st differential select
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,
|
||||
// ADC_SSFIFO2, and ADC_SSFIFO3 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
|
||||
#define ADC_SSFIFO_DATA_SHIFT 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,
|
||||
// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
|
||||
#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
|
||||
#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
|
||||
#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the ADC_TMLB register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TMLB_LB 0x00000001 // Loopback control signals
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the loopback ADC data.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
|
||||
#define ADC_LB_CONT 0x00000020 // Continuation sample
|
||||
#define ADC_LB_DIFF 0x00000010 // Differential sample
|
||||
#define ADC_LB_TS 0x00000008 // Temperature sensor sample
|
||||
#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
|
||||
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
|
||||
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
|
||||
|
||||
#endif // __HW_ADC_H__
|
||||
@ -0,0 +1,118 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_comp.h - Macros used when accessing the comparator hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_COMP_H__
|
||||
#define __HW_COMP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the comparator registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_O_MIS 0x00000000 // Interrupt status register
|
||||
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
|
||||
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
|
||||
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
|
||||
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
|
||||
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
|
||||
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
|
||||
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
|
||||
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
|
||||
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the COMP_MIS, COMP_RIS, and
|
||||
// COMP_INTEN registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_INT_2 0x00000004 // Comp2 interrupt
|
||||
#define COMP_INT_1 0x00000002 // Comp1 interrupt
|
||||
#define COMP_INT_0 0x00000001 // Comp0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the COMP_REFCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
|
||||
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
|
||||
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
|
||||
#define COMP_REFCTL_VREF_SHIFT 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and
|
||||
// COMP_ACSTAT2 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and
|
||||
// COMP_ACCTL2 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
|
||||
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
|
||||
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
|
||||
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
|
||||
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
|
||||
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
|
||||
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
|
||||
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
|
||||
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
|
||||
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
|
||||
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
|
||||
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
|
||||
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
|
||||
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
|
||||
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
|
||||
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
|
||||
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
|
||||
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
|
||||
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the reset values for the comparator registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_RV_MIS 0x00000000 // Interrupt status register
|
||||
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
|
||||
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
|
||||
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
|
||||
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
|
||||
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
|
||||
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
|
||||
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
|
||||
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
|
||||
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
|
||||
|
||||
#endif // __HW_COMP_H__
|
||||
@ -0,0 +1,139 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_flash.h - Macros used when accessing the flash controller.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_FLASH_H__
|
||||
#define __HW_FLASH_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the FLASH registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMA 0x400FD000 // Memory address register
|
||||
#define FLASH_FMD 0x400FD004 // Memory data register
|
||||
#define FLASH_FMC 0x400FD008 // Memory control register
|
||||
#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register
|
||||
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
|
||||
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
|
||||
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
|
||||
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
|
||||
#define FLASH_USECRL 0x400FE140 // uSec reload register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the FLASH_FMC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
|
||||
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
|
||||
#define FLASH_FMC_COMT 0x00000008 // Commit user register
|
||||
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
|
||||
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
|
||||
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the FLASH_FCRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
|
||||
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the FLASH_FCIM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
|
||||
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the FLASH_FMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
|
||||
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
|
||||
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
|
||||
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
|
||||
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
|
||||
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
|
||||
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
|
||||
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
|
||||
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
|
||||
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
|
||||
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
|
||||
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
|
||||
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
|
||||
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
|
||||
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
|
||||
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
|
||||
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
|
||||
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
|
||||
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
|
||||
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
|
||||
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
|
||||
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
|
||||
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
|
||||
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
|
||||
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
|
||||
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
|
||||
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
|
||||
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
|
||||
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
|
||||
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
|
||||
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
|
||||
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
|
||||
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the FLASH_USECRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
|
||||
#define FLASH_USECRL_SHIFT 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The erase size is the size of the FLASH block that is erased by an erase
|
||||
// operation, and the protect size is the size of the FLASH block that is
|
||||
// protected by each protection register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_ERASE_SIZE 0x00000400
|
||||
#define FLASH_PROTECT_SIZE 0x00000800
|
||||
|
||||
#endif // __HW_FLASH_H__
|
||||
@ -0,0 +1,103 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_gpio.h - Defines and Macros for GPIO hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_GPIO_H__
|
||||
#define __HW_GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO Register Offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_DATA 0x00000000 // Data register.
|
||||
#define GPIO_O_DIR 0x00000400 // Data direction register.
|
||||
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
|
||||
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
|
||||
#define GPIO_O_IEV 0x0000040C // Intterupt event register.
|
||||
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
|
||||
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
|
||||
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
|
||||
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
|
||||
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
|
||||
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
|
||||
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
|
||||
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
|
||||
#define GPIO_O_ODR 0x0000050C // Open drain select register.
|
||||
#define GPIO_O_PUR 0x00000510 // Pull up select register.
|
||||
#define GPIO_O_PDR 0x00000514 // Pull down select register.
|
||||
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
|
||||
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
|
||||
#define GPIO_O_PeriphID4 0x00000FD0 //
|
||||
#define GPIO_O_PeriphID5 0x00000FD4 //
|
||||
#define GPIO_O_PeriphID6 0x00000FD8 //
|
||||
#define GPIO_O_PeriphID7 0x00000FDC //
|
||||
#define GPIO_O_PeriphID0 0x00000FE0 //
|
||||
#define GPIO_O_PeriphID1 0x00000FE4 //
|
||||
#define GPIO_O_PeriphID2 0x00000FE8 //
|
||||
#define GPIO_O_PeriphID3 0x00000FEC //
|
||||
#define GPIO_O_PCellID0 0x00000FF0 //
|
||||
#define GPIO_O_PCellID1 0x00000FF4 //
|
||||
#define GPIO_O_PCellID2 0x00000FF8 //
|
||||
#define GPIO_O_PCellID3 0x00000FFC //
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO Register reset values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
|
||||
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
|
||||
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
|
||||
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
|
||||
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
|
||||
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
|
||||
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
|
||||
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
|
||||
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
|
||||
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
|
||||
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
|
||||
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
|
||||
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
|
||||
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
|
||||
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
|
||||
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
|
||||
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
|
||||
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
|
||||
#define GPIO_RV_PeriphID4 0x00000000 //
|
||||
#define GPIO_RV_PeriphID5 0x00000000 //
|
||||
#define GPIO_RV_PeriphID6 0x00000000 //
|
||||
#define GPIO_RV_PeriphID7 0x00000000 //
|
||||
#define GPIO_RV_PeriphID0 0x00000061 //
|
||||
#define GPIO_RV_PeriphID1 0x00000010 //
|
||||
#define GPIO_RV_PeriphID2 0x00000004 //
|
||||
#define GPIO_RV_PeriphID3 0x00000000 //
|
||||
#define GPIO_RV_PCellID0 0x0000000D //
|
||||
#define GPIO_RV_PCellID1 0x000000F0 //
|
||||
#define GPIO_RV_PCellID2 0x00000005 //
|
||||
#define GPIO_RV_PCellID3 0x000000B1 //
|
||||
|
||||
#endif // __HW_GPIO_H__
|
||||
@ -0,0 +1,189 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_I2C_H__
|
||||
#define __HW_I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the I2C master registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
|
||||
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
|
||||
#define I2C_MASTER_O_DR 0x00000008 // Data register
|
||||
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
|
||||
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
|
||||
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
|
||||
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
|
||||
#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register
|
||||
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the I2C slave registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
|
||||
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
|
||||
#define I2C_SLAVE_O_DR 0x00000008 // Data register
|
||||
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
|
||||
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
|
||||
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
|
||||
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The followng define the bit fields in the I2C master slave address register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
|
||||
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
|
||||
#define I2C_MASTER_SA_SA_SHIFT 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Master Control and Status
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
|
||||
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
|
||||
#define I2C_MASTER_CS_START 0x00000002 // Start
|
||||
#define I2C_MASTER_CS_RUN 0x00000001 // Run
|
||||
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
|
||||
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
|
||||
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
|
||||
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
|
||||
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
|
||||
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
|
||||
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
|
||||
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define values used in determining the contents of the I2C
|
||||
// Master Timer Period register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
|
||||
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
|
||||
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
|
||||
#define I2C_SCL_FAST 400000 // SCL fast frequency
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Master Interrupt Mask
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Master Raw Interrupt Status
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Master Masked Interrupt
|
||||
// Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Master Interrupt Clear
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Master Configuration
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
|
||||
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
|
||||
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Slave Own Address register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Slave Control/Status
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
|
||||
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
|
||||
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Slave Interrupt Mask
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Slave Raw Interrupt Status
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Slave Masked Interrupt
|
||||
// Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the I2C Slave Interrupt Clear
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
|
||||
|
||||
#endif // __HW_I2C_H__
|
||||
@ -0,0 +1,96 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_INTS_H__
|
||||
#define __HW_INTS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the fault assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FAULT_NMI 2 // NMI fault
|
||||
#define FAULT_HARD 3 // Hard fault
|
||||
#define FAULT_MPU 4 // MPU fault
|
||||
#define FAULT_BUS 5 // Bus fault
|
||||
#define FAULT_USAGE 6 // Usage fault
|
||||
#define FAULT_SVCALL 11 // SVCall
|
||||
#define FAULT_DEBUG 12 // Debug monitor
|
||||
#define FAULT_PENDSV 14 // PendSV
|
||||
#define FAULT_SYSTICK 15 // System Tick
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA 16 // GPIO Port A
|
||||
#define INT_GPIOB 17 // GPIO Port B
|
||||
#define INT_GPIOC 18 // GPIO Port C
|
||||
#define INT_GPIOD 19 // GPIO Port D
|
||||
#define INT_GPIOE 20 // GPIO Port E
|
||||
#define INT_UART0 21 // UART0 Rx and Tx
|
||||
#define INT_UART1 22 // UART1 Rx and Tx
|
||||
#define INT_SSI 23 // SSI Rx and Tx
|
||||
#define INT_I2C 24 // I2C Master and Slave
|
||||
#define INT_PWM_FAULT 25 // PWM Fault
|
||||
#define INT_PWM0 26 // PWM Generator 0
|
||||
#define INT_PWM1 27 // PWM Generator 1
|
||||
#define INT_PWM2 28 // PWM Generator 2
|
||||
#define INT_ADC0 30 // ADC Sequence 0
|
||||
#define INT_ADC1 31 // ADC Sequence 1
|
||||
#define INT_ADC2 32 // ADC Sequence 2
|
||||
#define INT_ADC3 33 // ADC Sequence 3
|
||||
#define INT_WATCHDOG 34 // Watchdog timer
|
||||
#define INT_TIMER0A 35 // Timer 0 subtimer A
|
||||
#define INT_TIMER0B 36 // Timer 0 subtimer B
|
||||
#define INT_TIMER1A 37 // Timer 1 subtimer A
|
||||
#define INT_TIMER1B 38 // Timer 1 subtimer B
|
||||
#define INT_TIMER2A 39 // Timer 2 subtimer A
|
||||
#define INT_TIMER2B 40 // Timer 2 subtimer B
|
||||
#define INT_COMP0 41 // Analog Comparator 0
|
||||
#define INT_COMP1 42 // Analog Comparator 1
|
||||
#define INT_COMP2 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
|
||||
#define INT_FLASH 45 // FLASH Control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The total number of interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_INTERRUPTS 46
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The total number of priority levels.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_PRIORITY 8
|
||||
#define NUM_PRIORITY_BITS 3
|
||||
|
||||
#endif // __HW_INTS_H__
|
||||
@ -0,0 +1,63 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_memmap.h - Macros defining the memory map of Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_MEMMAP_H__
|
||||
#define __HW_MEMMAP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the base address of the memories and peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BASE 0x00000000 // FLASH memory
|
||||
#define SRAM_BASE 0x20000000 // SRAM memory
|
||||
#define WATCHDOG_BASE 0x40000000 // Watchdog
|
||||
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
||||
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
||||
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
||||
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
||||
#define SSI_BASE 0x40008000 // SSI
|
||||
#define UART0_BASE 0x4000C000 // UART0
|
||||
#define UART1_BASE 0x4000D000 // UART1
|
||||
#define I2C_MASTER_BASE 0x40020000 // I2C Master
|
||||
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
|
||||
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
||||
#define PWM_BASE 0x40028000 // PWM
|
||||
#define TIMER0_BASE 0x40030000 // Timer0
|
||||
#define TIMER1_BASE 0x40031000 // Timer1
|
||||
#define TIMER2_BASE 0x40032000 // Timer2
|
||||
#define ADC_BASE 0x40038000 // ADC
|
||||
#define COMP_BASE 0x4003C000 // Analog comparators
|
||||
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
||||
#define SYSCTL_BASE 0x400FE000 // System Control
|
||||
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
|
||||
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
|
||||
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
||||
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
|
||||
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
||||
|
||||
#endif // __HW_MEMMAP_H__
|
||||
@ -0,0 +1,830 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_nvic.h - Macros used when accessing the NVIC hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_NVIC_H__
|
||||
#define __HW_NVIC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the addresses of the NVIC registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
|
||||
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
|
||||
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
|
||||
#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
|
||||
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
|
||||
#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
|
||||
#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
|
||||
#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
|
||||
#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
|
||||
#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
|
||||
#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
|
||||
#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
|
||||
#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
|
||||
#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
|
||||
#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
|
||||
#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
|
||||
#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
|
||||
#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
|
||||
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
|
||||
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
|
||||
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
|
||||
#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
|
||||
#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
|
||||
#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
|
||||
#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
|
||||
#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
|
||||
#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
|
||||
#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
|
||||
#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
|
||||
#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
|
||||
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
|
||||
#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
|
||||
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
|
||||
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
|
||||
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
|
||||
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
|
||||
#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
|
||||
#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
|
||||
#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
|
||||
#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
|
||||
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
|
||||
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
|
||||
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_INT_TYPE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
|
||||
#define NVIC_INT_TYPE_LINES_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_ST_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
|
||||
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
|
||||
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
|
||||
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_ST_RELOAD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
|
||||
#define NVIC_ST_RELOAD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_ST_CURRENT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
|
||||
#define NVIC_ST_CURRENT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_ST_CAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
|
||||
#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
|
||||
#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
|
||||
#define NVIC_ST_CAL_ONEMS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_EN0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
|
||||
#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
|
||||
#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
|
||||
#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
|
||||
#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
|
||||
#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
|
||||
#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
|
||||
#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
|
||||
#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
|
||||
#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
|
||||
#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
|
||||
#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
|
||||
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
|
||||
#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
|
||||
#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
|
||||
#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
|
||||
#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
|
||||
#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
|
||||
#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
|
||||
#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
|
||||
#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
|
||||
#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
|
||||
#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
|
||||
#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
|
||||
#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
|
||||
#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
|
||||
#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
|
||||
#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
|
||||
#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
|
||||
#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
|
||||
#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
|
||||
#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_DIS0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
|
||||
#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
|
||||
#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
|
||||
#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
|
||||
#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
|
||||
#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
|
||||
#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
|
||||
#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
|
||||
#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
|
||||
#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
|
||||
#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
|
||||
#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
|
||||
#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
|
||||
#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
|
||||
#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
|
||||
#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
|
||||
#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
|
||||
#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
|
||||
#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
|
||||
#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
|
||||
#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
|
||||
#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
|
||||
#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
|
||||
#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
|
||||
#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
|
||||
#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
|
||||
#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
|
||||
#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
|
||||
#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
|
||||
#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
|
||||
#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
|
||||
#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PEND0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
|
||||
#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
|
||||
#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
|
||||
#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
|
||||
#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
|
||||
#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
|
||||
#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
|
||||
#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
|
||||
#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
|
||||
#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
|
||||
#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
|
||||
#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
|
||||
#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
|
||||
#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
|
||||
#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
|
||||
#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
|
||||
#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
|
||||
#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
|
||||
#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
|
||||
#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
|
||||
#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
|
||||
#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
|
||||
#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
|
||||
#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
|
||||
#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
|
||||
#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
|
||||
#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
|
||||
#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
|
||||
#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
|
||||
#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
|
||||
#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
|
||||
#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_UNPEND0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
|
||||
#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
|
||||
#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
|
||||
#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
|
||||
#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
|
||||
#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
|
||||
#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
|
||||
#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
|
||||
#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
|
||||
#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
|
||||
#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
|
||||
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
|
||||
#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
|
||||
#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
|
||||
#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
|
||||
#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
|
||||
#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
|
||||
#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
|
||||
#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
|
||||
#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
|
||||
#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
|
||||
#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
|
||||
#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
|
||||
#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
|
||||
#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
|
||||
#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
|
||||
#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
|
||||
#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
|
||||
#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
|
||||
#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
|
||||
#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
|
||||
#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_ACTIVE0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
|
||||
#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
|
||||
#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
|
||||
#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
|
||||
#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
|
||||
#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
|
||||
#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
|
||||
#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
|
||||
#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
|
||||
#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
|
||||
#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
|
||||
#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
|
||||
#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
|
||||
#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
|
||||
#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
|
||||
#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
|
||||
#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
|
||||
#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
|
||||
#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
|
||||
#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
|
||||
#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
|
||||
#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
|
||||
#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
|
||||
#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
|
||||
#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
|
||||
#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
|
||||
#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
|
||||
#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
|
||||
#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
|
||||
#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
|
||||
#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
|
||||
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
|
||||
#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
|
||||
#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
|
||||
#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
|
||||
#define NVIC_PRI0_INT3_S 24
|
||||
#define NVIC_PRI0_INT2_S 16
|
||||
#define NVIC_PRI0_INT1_S 8
|
||||
#define NVIC_PRI0_INT0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
|
||||
#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
|
||||
#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
|
||||
#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
|
||||
#define NVIC_PRI1_INT7_S 24
|
||||
#define NVIC_PRI1_INT6_S 16
|
||||
#define NVIC_PRI1_INT5_S 8
|
||||
#define NVIC_PRI1_INT4_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
|
||||
#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
|
||||
#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
|
||||
#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
|
||||
#define NVIC_PRI2_INT11_S 24
|
||||
#define NVIC_PRI2_INT10_S 16
|
||||
#define NVIC_PRI2_INT9_S 8
|
||||
#define NVIC_PRI2_INT8_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
|
||||
#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
|
||||
#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
|
||||
#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
|
||||
#define NVIC_PRI3_INT15_S 24
|
||||
#define NVIC_PRI3_INT14_S 16
|
||||
#define NVIC_PRI3_INT13_S 8
|
||||
#define NVIC_PRI3_INT12_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
|
||||
#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
|
||||
#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
|
||||
#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
|
||||
#define NVIC_PRI4_INT19_S 24
|
||||
#define NVIC_PRI4_INT18_S 16
|
||||
#define NVIC_PRI4_INT17_S 8
|
||||
#define NVIC_PRI4_INT16_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI5 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
|
||||
#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
|
||||
#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
|
||||
#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
|
||||
#define NVIC_PRI5_INT23_S 24
|
||||
#define NVIC_PRI5_INT22_S 16
|
||||
#define NVIC_PRI5_INT21_S 8
|
||||
#define NVIC_PRI5_INT20_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI6 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
|
||||
#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
|
||||
#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
|
||||
#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
|
||||
#define NVIC_PRI6_INT27_S 24
|
||||
#define NVIC_PRI6_INT26_S 16
|
||||
#define NVIC_PRI6_INT25_S 8
|
||||
#define NVIC_PRI6_INT24_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_PRI7 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
|
||||
#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
|
||||
#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
|
||||
#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
|
||||
#define NVIC_PRI7_INT31_S 24
|
||||
#define NVIC_PRI7_INT30_S 16
|
||||
#define NVIC_PRI7_INT29_S 8
|
||||
#define NVIC_PRI7_INT28_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_CPUID register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
|
||||
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
|
||||
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
|
||||
#define NVIC_CPUID_REV_M 0x0000000F // Revision
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_INT_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
|
||||
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
|
||||
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
|
||||
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
|
||||
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
|
||||
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
|
||||
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
|
||||
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
|
||||
#define NVIC_INT_CTRL_VEC_PEN_S 12
|
||||
#define NVIC_INT_CTRL_VEC_ACT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_VTABLE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
|
||||
#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
|
||||
#define NVIC_VTABLE_OFFSET_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_APINT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
|
||||
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
|
||||
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
|
||||
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
|
||||
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
|
||||
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
|
||||
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
|
||||
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
|
||||
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
|
||||
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
|
||||
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
|
||||
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
|
||||
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
|
||||
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
|
||||
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_SYS_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
|
||||
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
|
||||
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_CFG_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
|
||||
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
|
||||
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
|
||||
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
|
||||
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
|
||||
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_SYS_PRI1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
|
||||
#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
|
||||
#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
|
||||
#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
|
||||
#define NVIC_SYS_PRI1_USAGE_S 16
|
||||
#define NVIC_SYS_PRI1_BUS_S 8
|
||||
#define NVIC_SYS_PRI1_MEM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_SYS_PRI2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
|
||||
#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
|
||||
#define NVIC_SYS_PRI2_SVC_S 24
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_SYS_PRI3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
|
||||
#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
|
||||
#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
|
||||
#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
|
||||
#define NVIC_SYS_PRI3_TICK_S 24
|
||||
#define NVIC_SYS_PRI3_PENDSV_S 16
|
||||
#define NVIC_SYS_PRI3_DEBUG_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_SYS_HND_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
|
||||
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
|
||||
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
|
||||
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
|
||||
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
|
||||
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
|
||||
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
|
||||
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
|
||||
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
|
||||
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
|
||||
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
|
||||
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_FAULT_STAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
|
||||
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
|
||||
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
|
||||
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
|
||||
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
|
||||
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
|
||||
#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
|
||||
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
|
||||
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
|
||||
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
|
||||
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
|
||||
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
|
||||
#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
|
||||
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
|
||||
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
|
||||
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
|
||||
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_HFAULT_STAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
|
||||
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
|
||||
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_DEBUG_STAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
|
||||
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
|
||||
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
|
||||
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
|
||||
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_MM_ADDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
|
||||
#define NVIC_MM_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_FAULT_ADDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
|
||||
#define NVIC_FAULT_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_EXC_STACK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_EXC_NUM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_EXC_NUM_M 0x000003FF // Exception number
|
||||
#define NVIC_EXC_NUM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_COPRO register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask
|
||||
#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied
|
||||
#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess
|
||||
#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access
|
||||
#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask
|
||||
#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied
|
||||
#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess
|
||||
#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access
|
||||
#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask
|
||||
#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied
|
||||
#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess
|
||||
#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access
|
||||
#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask
|
||||
#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied
|
||||
#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess
|
||||
#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access
|
||||
#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask
|
||||
#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied
|
||||
#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess
|
||||
#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access
|
||||
#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask
|
||||
#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied
|
||||
#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess
|
||||
#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access
|
||||
#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask
|
||||
#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied
|
||||
#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess
|
||||
#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access
|
||||
#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask
|
||||
#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied
|
||||
#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess
|
||||
#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access
|
||||
#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask
|
||||
#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied
|
||||
#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess
|
||||
#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access
|
||||
#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask
|
||||
#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied
|
||||
#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess
|
||||
#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access
|
||||
#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask
|
||||
#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied
|
||||
#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess
|
||||
#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access
|
||||
#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask
|
||||
#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied
|
||||
#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess
|
||||
#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access
|
||||
#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask
|
||||
#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied
|
||||
#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess
|
||||
#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access
|
||||
#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask
|
||||
#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied
|
||||
#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess
|
||||
#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access
|
||||
#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask
|
||||
#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied
|
||||
#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess
|
||||
#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access
|
||||
#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask
|
||||
#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied
|
||||
#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess
|
||||
#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_MPU_TYPE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
|
||||
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
|
||||
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
|
||||
#define NVIC_MPU_TYPE_IREGION_S 16
|
||||
#define NVIC_MPU_TYPE_DREGION_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_MPU_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
|
||||
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_MPU_NUMBER register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
|
||||
#define NVIC_MPU_NUMBER_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_MPU_BASE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address
|
||||
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
|
||||
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
|
||||
#define NVIC_MPU_BASE_ADDR_S 8
|
||||
#define NVIC_MPU_BASE_REGION_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_MPU_ATTR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes
|
||||
#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable
|
||||
#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_DBG_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
|
||||
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
|
||||
#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
|
||||
#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
|
||||
#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
|
||||
#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
|
||||
#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
|
||||
#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
|
||||
#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
|
||||
#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
|
||||
#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
|
||||
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
|
||||
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
|
||||
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
|
||||
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_DBG_XFER register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
|
||||
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
|
||||
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
|
||||
#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
|
||||
#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
|
||||
#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
|
||||
#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
|
||||
#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
|
||||
#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
|
||||
#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
|
||||
#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
|
||||
#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
|
||||
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
|
||||
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
|
||||
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
|
||||
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
|
||||
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
|
||||
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
|
||||
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
|
||||
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
|
||||
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
|
||||
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
|
||||
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_DBG_DATA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
|
||||
#define NVIC_DBG_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_DBG_INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
|
||||
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
|
||||
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
|
||||
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
|
||||
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
|
||||
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
|
||||
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
|
||||
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
|
||||
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
|
||||
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
|
||||
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the NVIC_SW_TRIG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
|
||||
#define NVIC_SW_TRIG_INTID_S 0
|
||||
|
||||
#endif // __HW_NVIC_H__
|
||||
@ -0,0 +1,260 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_PWM_H__
|
||||
#define __HW_PWM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM Module Register Offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_O_CTL 0x00000000 // PWM Master Control register
|
||||
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
|
||||
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
|
||||
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
|
||||
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
|
||||
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
|
||||
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
|
||||
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
|
||||
#define PWM_O_STATUS 0x00000020 // PWM Status register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the PWM Master Control register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
|
||||
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
|
||||
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the PWM Time Base Sync register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
|
||||
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
|
||||
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the PWM Output Enable register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
|
||||
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
|
||||
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
|
||||
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
|
||||
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
|
||||
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the PWM Inversion register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
|
||||
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
|
||||
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
|
||||
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
|
||||
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
|
||||
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the PWM Fault register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
|
||||
#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault
|
||||
#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault
|
||||
#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault
|
||||
#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault
|
||||
#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM Interrupt Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the PWM Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_STATUS_FAULT 0x00000001 // Fault status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM Generator standard offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
|
||||
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
|
||||
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
|
||||
|
||||
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
|
||||
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
|
||||
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
|
||||
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
|
||||
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
|
||||
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
|
||||
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
|
||||
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
|
||||
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
|
||||
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
|
||||
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
|
||||
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
|
||||
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Control Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
|
||||
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
|
||||
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
|
||||
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
|
||||
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
|
||||
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Interrupt/Trigger Enable Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
|
||||
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
|
||||
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
|
||||
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
|
||||
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Raw Interrupt Status Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
|
||||
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
|
||||
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
|
||||
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
|
||||
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
|
||||
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Interrupt Status Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
|
||||
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
|
||||
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
|
||||
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
|
||||
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
|
||||
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Generator A/B Control Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
|
||||
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
|
||||
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
|
||||
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
|
||||
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
|
||||
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Generator A/B Control Register action definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_ACT_NONE 0x0 // Do nothing
|
||||
#define PWM_GEN_ACT_INV 0x1 // Invert the output signal
|
||||
#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero
|
||||
#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one
|
||||
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
|
||||
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
|
||||
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
|
||||
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
|
||||
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
|
||||
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM_X Dead Band Control Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// PWM Register reset values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
|
||||
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
|
||||
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM
|
||||
// output pins
|
||||
#define PWM_RV_INVERT 0x00000000 // Inversion control for
|
||||
// PWM output pins
|
||||
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
|
||||
// output pins
|
||||
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
|
||||
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
|
||||
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
|
||||
#define PWM_RV_STATUS 0x00000000 // Status
|
||||
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
|
||||
// generator block
|
||||
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
|
||||
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
|
||||
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
|
||||
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
|
||||
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
|
||||
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
|
||||
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
|
||||
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
|
||||
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
|
||||
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
|
||||
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
|
||||
// count
|
||||
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
|
||||
// count
|
||||
|
||||
#endif // __HW_PWM_H__
|
||||
@ -0,0 +1,120 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_ssi.h - Macros used when accessing the SSI hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SSI_H__
|
||||
#define __HW_SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the SSI registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_O_CR0 0x00000000 // Control register 0
|
||||
#define SSI_O_CR1 0x00000004 // Control register 1
|
||||
#define SSI_O_DR 0x00000008 // Data register
|
||||
#define SSI_O_SR 0x0000000C // Status register
|
||||
#define SSI_O_CPSR 0x00000010 // Clock prescale register
|
||||
#define SSI_O_IM 0x00000014 // Int mask set and clear register
|
||||
#define SSI_O_RIS 0x00000018 // Raw interrupt register
|
||||
#define SSI_O_MIS 0x0000001C // Masked interrupt register
|
||||
#define SSI_O_ICR 0x00000020 // Interrupt clear register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SSI Control register 0.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
|
||||
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
|
||||
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
|
||||
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
|
||||
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
|
||||
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
|
||||
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
|
||||
#define SSI_CR0_DSS 0x0000000F // Data size select
|
||||
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
|
||||
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
|
||||
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
|
||||
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
|
||||
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
|
||||
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
|
||||
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
|
||||
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
|
||||
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
|
||||
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
|
||||
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
|
||||
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
|
||||
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SSI Control register 1.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
|
||||
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
|
||||
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
|
||||
#define SSI_CR1_LBM 0x00000001 // Loopback mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SSI Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_SR_BSY 0x00000010 // SSI busy
|
||||
#define SSI_SR_RFF 0x00000008 // RX FIFO full
|
||||
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
|
||||
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
|
||||
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SSI clock prescale register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define information concerning the SSI Data register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
|
||||
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the interrupt mask set and clear,
|
||||
// raw interrupt, masked interrupt, and interrupt clear registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
|
||||
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
|
||||
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
|
||||
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
|
||||
|
||||
#endif // __HW_SSI_H__
|
||||
@ -0,0 +1,380 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_sysctl.h - Macros used when accessing the system control hardware.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SYSCTL_H__
|
||||
#define __HW_SYSCTL_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the system control registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DID0 0x400fe000 // Device identification register 0
|
||||
#define SYSCTL_DID1 0x400fe004 // Device identification register 1
|
||||
#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
|
||||
#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
|
||||
#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
|
||||
#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
|
||||
#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
|
||||
#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
|
||||
#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
|
||||
#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
|
||||
#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
|
||||
#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
|
||||
#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
|
||||
#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
|
||||
#define SYSCTL_MISC 0x400fe058 // Interrupt status register
|
||||
#define SYSCTL_RESC 0x400fe05c // Reset cause register
|
||||
#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
|
||||
#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
|
||||
#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
|
||||
#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
|
||||
#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
|
||||
#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
|
||||
#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
|
||||
#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
|
||||
#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
|
||||
#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
|
||||
#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
|
||||
#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
|
||||
#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DID0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
|
||||
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
|
||||
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
|
||||
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
|
||||
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
|
||||
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
|
||||
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
|
||||
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DID1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
|
||||
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
|
||||
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
|
||||
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
|
||||
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
|
||||
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
|
||||
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
|
||||
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
|
||||
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
|
||||
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
|
||||
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
|
||||
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
|
||||
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
|
||||
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
|
||||
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
|
||||
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
|
||||
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
|
||||
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
|
||||
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
|
||||
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
|
||||
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
|
||||
#define SYSCTL_DID1_PRTNO_SHIFT 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DC0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
|
||||
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM
|
||||
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM
|
||||
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
|
||||
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash
|
||||
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DC1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
|
||||
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
|
||||
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
|
||||
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
|
||||
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
|
||||
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
|
||||
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
|
||||
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
|
||||
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
|
||||
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
|
||||
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
|
||||
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
|
||||
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DC2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
|
||||
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
|
||||
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
|
||||
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
|
||||
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
|
||||
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
|
||||
#define SYSCTL_DC2_I2C 0x00001000 // I2C present
|
||||
#define SYSCTL_DC2_SSI 0x00000010 // SSI present
|
||||
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
|
||||
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DC3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
|
||||
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
|
||||
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
|
||||
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
|
||||
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
|
||||
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
|
||||
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
|
||||
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
|
||||
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
|
||||
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
|
||||
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
|
||||
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
|
||||
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
|
||||
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
|
||||
#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
|
||||
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
|
||||
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
|
||||
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
|
||||
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
|
||||
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
|
||||
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
|
||||
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
|
||||
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
|
||||
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
|
||||
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
|
||||
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_DC4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
|
||||
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
|
||||
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
|
||||
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
|
||||
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_PBORCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
|
||||
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
|
||||
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
|
||||
#define SYSCTL_PBORCTL_BOR_SH 2
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_LDOPCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
|
||||
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
|
||||
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
|
||||
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
|
||||
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
|
||||
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
|
||||
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
|
||||
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
|
||||
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
|
||||
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
|
||||
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
|
||||
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
|
||||
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_SET0_PWM 0x00100000 // PWM module
|
||||
#define SYSCTL_SET0_ADC 0x00010000 // ADC module
|
||||
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
|
||||
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
|
||||
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
|
||||
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
|
||||
#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
|
||||
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
|
||||
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
|
||||
#define SYSCTL_SET1_I2C 0x00001000 // I2C module
|
||||
#define SYSCTL_SET1_SSI 0x00000010 // SSI module
|
||||
#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
|
||||
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
|
||||
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
|
||||
#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
|
||||
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
|
||||
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
|
||||
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
|
||||
// SYSCTL_IMS registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
|
||||
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
|
||||
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
|
||||
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
|
||||
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
|
||||
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
|
||||
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_RESC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
|
||||
#define SYSCTL_RESC_SW 0x00000010 // Software reset
|
||||
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
|
||||
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
|
||||
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
|
||||
#define SYSCTL_RESC_EXT 0x00000001 // External reset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_RCC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
|
||||
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
|
||||
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
|
||||
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
|
||||
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
|
||||
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
|
||||
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
|
||||
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
|
||||
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
|
||||
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
|
||||
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
|
||||
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
|
||||
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
|
||||
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
|
||||
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
|
||||
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
|
||||
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
|
||||
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
|
||||
#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
|
||||
#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
|
||||
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
|
||||
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
|
||||
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
|
||||
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
|
||||
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
|
||||
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
|
||||
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
|
||||
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
|
||||
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
|
||||
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
|
||||
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
|
||||
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
|
||||
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
|
||||
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
|
||||
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
|
||||
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
|
||||
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
|
||||
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
|
||||
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
|
||||
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
|
||||
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
|
||||
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
|
||||
#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
|
||||
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
|
||||
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_PLLCFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
|
||||
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
|
||||
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
|
||||
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
|
||||
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
|
||||
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
|
||||
#define SYSCTL_PLLCFG_F_SHIFT 5
|
||||
#define SYSCTL_PLLCFG_R_SHIFT 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_CLKVCLR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the SYSCTL_LDOARST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
|
||||
|
||||
#endif // __HW_SYSCTL_H__
|
||||
@ -0,0 +1,235 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_timer.h - Defines and macros used when accessing the timer.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TIMER_H__
|
||||
#define __HW_TIMER_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the offsets of the timer registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_O_CFG 0x00000000 // Configuration register
|
||||
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
|
||||
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
|
||||
#define TIMER_O_CTL 0x0000000C // Control register
|
||||
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
|
||||
#define TIMER_O_RIS 0x0000001C // Interrupt status register
|
||||
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
|
||||
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
|
||||
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
|
||||
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
|
||||
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
|
||||
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
|
||||
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
|
||||
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
|
||||
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
|
||||
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
|
||||
#define TIMER_O_TAR 0x00000048 // TimerA register
|
||||
#define TIMER_O_TBR 0x0000004C // TimerB register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the reset values of the timer registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
|
||||
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
|
||||
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
|
||||
#define TIMER_RV_CTL 0x00000000 // Control register RV
|
||||
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
|
||||
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
|
||||
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
|
||||
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
|
||||
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
|
||||
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
|
||||
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
|
||||
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
|
||||
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
|
||||
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
|
||||
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
|
||||
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
|
||||
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
|
||||
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_CFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
|
||||
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
|
||||
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
|
||||
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_TnMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
|
||||
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
|
||||
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
|
||||
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
|
||||
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
|
||||
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
|
||||
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
|
||||
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
|
||||
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
|
||||
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
|
||||
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
|
||||
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
|
||||
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
|
||||
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
|
||||
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
|
||||
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
|
||||
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
|
||||
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
|
||||
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
|
||||
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
|
||||
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
|
||||
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_IMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
|
||||
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
|
||||
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
|
||||
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
|
||||
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
|
||||
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
|
||||
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
|
||||
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
|
||||
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
|
||||
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
|
||||
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
|
||||
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
|
||||
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
|
||||
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
|
||||
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
|
||||
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
|
||||
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
|
||||
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
|
||||
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
|
||||
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
|
||||
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
|
||||
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
|
||||
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
|
||||
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
|
||||
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_TAILR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
|
||||
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines the bit fields in the TIMER_TBILR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_TAMATCHR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
|
||||
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines the bit fields in the TIMER_TBMATCHR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines the bit fields in the TIMER_TnPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines the bit fields in the TIMER_TnPMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the TIMER_TAR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
|
||||
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines the bit fields in the TIMER_TBR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
|
||||
|
||||
#endif // __HW_TIMER_H__
|
||||
@ -0,0 +1,67 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_types.h - Common types and macros.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TYPES_H__
|
||||
#define __HW_TYPES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Define a boolean type, and values for true and false.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef unsigned char tBoolean;
|
||||
|
||||
#ifndef true
|
||||
#define true 1
|
||||
#endif
|
||||
|
||||
#ifndef false
|
||||
#define false 0
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros for hardware access, both direct and via the bit-band region.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HWREG(x) \
|
||||
(*((volatile unsigned long *)(x)))
|
||||
#define HWREGH(x) \
|
||||
(*((volatile unsigned short *)(x)))
|
||||
#define HWREGB(x) \
|
||||
(*((volatile unsigned char *)(x)))
|
||||
#define HWREGBITW(x, b) \
|
||||
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITH(x, b) \
|
||||
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITB(x, b) \
|
||||
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
|
||||
#endif // __HW_TYPES_H__
|
||||
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Reference in New Issue