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96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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/* Demo includes. */
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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/* Library includes. */
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#include "hw_ints.h"
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#include "hw_memmap.h"
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#include "hw_types.h"
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#include "interrupt.h"
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#include "sysctl.h"
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#include "lmi_timer.h"
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#define tmrTIMER_2_FREQUENCY ( 2000UL )
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#define tmrTIMER_3_FREQUENCY ( 2001UL )
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void vInitialiseTimerForIntQueueTest( void )
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{
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unsigned long ulFrequency;
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/* Timer 2 and 3 are utilised for this test. */
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SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER2 );
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SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER3 );
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TimerConfigure( TIMER2_BASE, TIMER_CFG_32_BIT_PER );
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TimerConfigure( TIMER3_BASE, TIMER_CFG_32_BIT_PER );
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/* Set the timer interrupts to be above the kernel. The interrupts are
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assigned different priorities so they nest with each other. */
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IntPrioritySet( INT_TIMER2A, configMAX_SYSCALL_INTERRUPT_PRIORITY + ( 1 << 5 ) ); /* Shift left 5 as only the top 3 bits are implemented. */
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IntPrioritySet( INT_TIMER3A, configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* Ensure interrupts do not start until the scheduler is running. */
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portDISABLE_INTERRUPTS();
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/* The rate at which the timers will interrupt. */
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ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
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TimerLoadSet( TIMER2_BASE, TIMER_A, ulFrequency );
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IntEnable( INT_TIMER2A );
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TimerIntEnable( TIMER2_BASE, TIMER_TIMA_TIMEOUT );
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/* The rate at which the timers will interrupt. */
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ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_3_FREQUENCY;
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TimerLoadSet( TIMER3_BASE, TIMER_A, ulFrequency );
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IntEnable( INT_TIMER3A );
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TimerIntEnable( TIMER3_BASE, TIMER_TIMA_TIMEOUT );
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/* Enable both timers. */
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TimerEnable( TIMER2_BASE, TIMER_A );
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TimerEnable( TIMER3_BASE, TIMER_A );
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}
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/*-----------------------------------------------------------*/
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void vT2InterruptHandler( void )
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{
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TimerIntClear( TIMER2_BASE, TIMER_TIMA_TIMEOUT );
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portEND_SWITCHING_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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void vT3InterruptHandler( void )
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{
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TimerIntClear( TIMER3_BASE, TIMER_TIMA_TIMEOUT );
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portEND_SWITCHING_ISR( xSecondTimerHandler() );
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}
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