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560 lines
17 KiB
C
560 lines
17 KiB
C
/*
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FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/* Hardware specific includes. */
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#include <iorx62n.h>
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#include "typedefine.h"
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#include "r_ether.h"
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#include "phy.h"
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "semphr.h"
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/* uIP includes. */
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#include "net/uip.h"
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/* The time to wait between attempts to obtain a free buffer. */
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#define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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/* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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up on attempting to obtain a free buffer all together. */
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#define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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/* The number of Rx descriptors. */
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#define emacNUM_RX_DESCRIPTORS 8
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/* The number of Tx descriptors. When using uIP there is not point in having
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more than two. */
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#define emacNUM_TX_BUFFERS 2
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/* The total number of EMAC buffers to allocate. */
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#define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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/* The time to wait for the Tx descriptor to become free. */
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#define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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/* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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become free. */
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#define emacTX_WAIT_ATTEMPTS ( 50 )
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/* Only Rx end and Tx end interrupts are used by this driver. */
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#define emacTX_END_INTERRUPT ( 1UL << 21UL )
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#define emacRX_END_INTERRUPT ( 1UL << 18UL )
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/*-----------------------------------------------------------*/
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/* The buffers and descriptors themselves. */
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#pragma data_alignment=32
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volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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#pragma data_alignment=32
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volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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#pragma data_alignment=32
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char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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/* Used to indicate which buffers are free and which are in use. If an index
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contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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the buffer is in use or about to be used. */
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static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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/*-----------------------------------------------------------*/
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/*
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* Initialise both the Rx and Tx descriptors.
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*/
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static void prvInitialiseDescriptors( void );
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/*
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* Return a pointer to a free buffer within xEthernetBuffers.
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*/
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static unsigned char *prvGetNextBuffer( void );
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/*
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* Return a buffer to the list of free buffers.
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*/
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static void prvReturnBuffer( unsigned char *pucBuffer );
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/*
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* Examine the status of the next Rx FIFO to see if it contains new data.
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*/
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static unsigned long prvCheckRxFifoStatus( void );
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/*
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* Setup the microcontroller for communication with the PHY.
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*/
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static void prvResetMAC( void );
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/*
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* Configure the Ethernet interface peripherals.
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*/
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static void prvConfigureEtherCAndEDMAC( void );
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/*
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* Something has gone wrong with the descriptor usage. Reset all the buffers
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* and descriptors.
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*/
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static void prvResetEverything( void );
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/*-----------------------------------------------------------*/
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/* Points to the Rx descriptor currently in use. */
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static volatile ethfifo *pxCurrentRxDesc = NULL;
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/* The buffer used by the uIP stack to both receive and send. This points to
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one of the Ethernet buffers when its actually in use. */
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unsigned char *uip_buf = NULL;
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/*-----------------------------------------------------------*/
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void vInitEmac( void )
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{
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/* Software reset. */
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prvResetMAC();
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/* Set the Rx and Tx descriptors into their initial state. */
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prvInitialiseDescriptors();
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/* Set the MAC address into the ETHERC */
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ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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( unsigned long ) configMAC_ADDR3;
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ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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( unsigned long ) configMAC_ADDR5;
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/* Perform rest of interface hardware configuration. */
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prvConfigureEtherCAndEDMAC();
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/* Nothing received yet, so uip_buf points nowhere. */
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uip_buf = NULL;
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/* Initialize the PHY */
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phy_init();
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}
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/*-----------------------------------------------------------*/
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void vEMACWrite( void )
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{
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long x;
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/* Wait until the second transmission of the last packet has completed. */
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for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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{
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if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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{
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/* Descriptor is still active. */
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vTaskDelay( emacTX_WAIT_DELAY_ms );
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}
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else
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{
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break;
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}
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}
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/* Is the descriptor free after waiting for it? */
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if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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{
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/* Something has gone wrong. */
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prvResetEverything();
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}
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/* Setup both descriptors to transmit the frame. */
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xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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xTxDescriptors[ 0 ].bufsize = uip_len;
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xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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xTxDescriptors[ 1 ].bufsize = uip_len;
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/* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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for use by the stack. */
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uip_buf = prvGetNextBuffer();
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/* Clear previous settings and go. */
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xTxDescriptors[0].status &= ~( FP1 | FP0 );
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xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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xTxDescriptors[1].status &= ~( FP1 | FP0 );
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xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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EDMAC.EDTRR.LONG = 0x00000001;
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}
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/*-----------------------------------------------------------*/
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unsigned long ulEMACRead( void )
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{
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unsigned long ulBytesReceived;
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ulBytesReceived = prvCheckRxFifoStatus();
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if( ulBytesReceived > 0 )
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{
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/* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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the buffer that contains the received data. */
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prvReturnBuffer( uip_buf );
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/* Point uip_buf to the data about ot be processed. */
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uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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/* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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old descriptor. */
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pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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/* Prepare the descriptor to go again. */
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pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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pxCurrentRxDesc->status |= ACT;
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/* Move onto the next buffer in the ring. */
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pxCurrentRxDesc = pxCurrentRxDesc->next;
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if( EDMAC.EDRRR.LONG == 0x00000000L )
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{
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/* Restart Ethernet if it has stopped */
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EDMAC.EDRRR.LONG = 0x00000001L;
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}
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}
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return ulBytesReceived;
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}
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/*-----------------------------------------------------------*/
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long lEMACWaitForLink( void )
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{
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long lReturn;
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/* Set the link status. */
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switch( phy_set_autonegotiate() )
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{
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/* Half duplex link */
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case PHY_LINK_100H:
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ETHERC.ECMR.BIT.DM = 0;
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ETHERC.ECMR.BIT.RTM = 1;
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lReturn = pdPASS;
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break;
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case PHY_LINK_10H:
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ETHERC.ECMR.BIT.DM = 0;
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ETHERC.ECMR.BIT.RTM = 0;
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lReturn = pdPASS;
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break;
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/* Full duplex link */
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case PHY_LINK_100F:
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ETHERC.ECMR.BIT.DM = 1;
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ETHERC.ECMR.BIT.RTM = 1;
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lReturn = pdPASS;
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break;
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case PHY_LINK_10F:
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ETHERC.ECMR.BIT.DM = 1;
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ETHERC.ECMR.BIT.RTM = 0;
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lReturn = pdPASS;
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break;
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default:
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lReturn = pdFAIL;
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break;
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}
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if( lReturn == pdPASS )
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{
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/* Enable receive and transmit. */
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ETHERC.ECMR.BIT.RE = 1;
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ETHERC.ECMR.BIT.TE = 1;
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/* Enable EDMAC receive */
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EDMAC.EDRRR.LONG = 0x1;
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}
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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static void prvInitialiseDescriptors( void )
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{
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volatile ethfifo *pxDescriptor;
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long x;
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for( x = 0; x < emacNUM_BUFFERS; x++ )
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{
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/* Ensure none of the buffers are shown as in use at the start. */
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ucBufferInUse[ x ] = pdFALSE;
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}
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/* Initialise the Rx descriptors. */
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for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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{
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pxDescriptor = &( xRxDescriptors[ x ] );
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pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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pxDescriptor->bufsize = UIP_BUFSIZE;
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pxDescriptor->size = 0;
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pxDescriptor->status = ACT;
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pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ x + 1 ];
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/* Mark this buffer as in use. */
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ucBufferInUse[ x ] = pdTRUE;
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}
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/* The last descriptor points back to the start. */
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pxDescriptor->status |= DL;
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pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ 0 ];
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/* Initialise the Tx descriptors. */
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for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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{
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pxDescriptor = &( xTxDescriptors[ x ] );
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/* A buffer is not allocated to the Tx descriptor until a send is
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actually required. */
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pxDescriptor->buf_p = NULL;
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pxDescriptor->bufsize = UIP_BUFSIZE;
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pxDescriptor->size = 0;
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pxDescriptor->status = 0;
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pxDescriptor->next = ( ethfifo * ) &xTxDescriptors[ x + 1 ];
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}
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/* The last descriptor points back to the start. */
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pxDescriptor->status |= DL;
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pxDescriptor->next = ( ethfifo * ) &( xTxDescriptors[ 0 ] );
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/* Use the first Rx descriptor to start with. */
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pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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}
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/*-----------------------------------------------------------*/
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static unsigned char *prvGetNextBuffer( void )
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{
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long x;
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unsigned char *pucReturn = NULL;
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unsigned long ulAttempts = 0;
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while( pucReturn == NULL )
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{
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/* Look through the buffers to find one that is not in use by
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anything else. */
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for( x = 0; x < emacNUM_BUFFERS; x++ )
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{
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if( ucBufferInUse[ x ] == pdFALSE )
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{
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ucBufferInUse[ x ] = pdTRUE;
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pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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break;
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}
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}
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/* Was a buffer found? */
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if( pucReturn == NULL )
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{
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ulAttempts++;
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if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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{
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break;
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}
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/* Wait then look again. */
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vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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}
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}
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return pucReturn;
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}
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/*-----------------------------------------------------------*/
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static void prvReturnBuffer( unsigned char *pucBuffer )
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{
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unsigned long ul;
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/* Return a buffer to the pool of free buffers. */
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for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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{
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if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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{
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ucBufferInUse[ ul ] = pdFALSE;
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break;
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}
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}
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}
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/*-----------------------------------------------------------*/
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static void prvResetEverything( void )
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{
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/* Temporary code just to see if this gets called. This function has not
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been implemented. */
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portDISABLE_INTERRUPTS();
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for( ;; );
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}
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/*-----------------------------------------------------------*/
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static unsigned long prvCheckRxFifoStatus( void )
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{
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unsigned long ulReturn = 0;
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if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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{
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/* Current descriptor is still active. */
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}
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else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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{
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/* Frame error. Clear the error. */
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pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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pxCurrentRxDesc->status |= ACT;
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pxCurrentRxDesc = pxCurrentRxDesc->next;
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if( EDMAC.EDRRR.LONG == 0x00000000UL )
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{
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/* Restart Ethernet if it has stopped. */
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EDMAC.EDRRR.LONG = 0x00000001UL;
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}
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}
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else
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{
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/* The descriptor contains a frame. Because of the size of the buffers
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the frame should always be complete. */
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if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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{
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ulReturn = pxCurrentRxDesc->size;
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}
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else
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{
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/* Do not expect to get here. */
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prvResetEverything();
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}
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}
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return ulReturn;
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}
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/*-----------------------------------------------------------*/
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static void prvResetMAC( void )
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{
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/* Ensure the EtherC and EDMAC are enabled. */
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SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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vTaskDelay( 100 / portTICK_RATE_MS );
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EDMAC.EDMR.BIT.SWR = 1;
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/* Crude wait for reset to complete. */
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vTaskDelay( 500 / portTICK_RATE_MS );
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}
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/*-----------------------------------------------------------*/
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static void prvConfigureEtherCAndEDMAC( void )
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{
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/* Initialisation code taken from Renesas example project. */
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/* TODO: Check bit 5 */
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ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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/* Set the EDMAC interrupt priority. */
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_IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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/* TODO: Check bit 5 */
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/* Enable interrupts of interest only. */
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EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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/* EDMAC */
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EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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#if __LITTLE_ENDIAN__ == 1
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EDMAC.EDMR.BIT.DE = 1;
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#endif
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EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] );/* Initialaize Tx Descriptor List Address */
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EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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/* Enable the interrupt... */
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_IEN( _ETHER_EINT ) = 1;
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}
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/*-----------------------------------------------------------*/
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#pragma vector = VECT_ETHER_EINT
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__interrupt void vEMAC_ISR_Handler( void )
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{
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unsigned long ul = EDMAC.EESR.LONG;
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long lHigherPriorityTaskWoken = pdFALSE;
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extern xQueueHandle xEMACEventQueue;
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const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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__enable_interrupt();
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/* Has a Tx end occurred? */
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if( ul & emacTX_END_INTERRUPT )
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{
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/* Only return the buffer to the pool once both Txes have completed. */
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prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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}
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/* Has an Rx end occurred? */
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if( ul & emacRX_END_INTERRUPT )
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{
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/* Make sure the Ethernet task is not blocked waiting for a packet. */
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xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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}
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}
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