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903 lines
21 KiB
C
903 lines
21 KiB
C
/******************************************************************************
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* DISCLAIMER
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*
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* This software is supplied by Renesas Technology Corp. and is only
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* intended for use with Renesas products. No other uses are authorized.
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*
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* This software is owned by Renesas Technology Corp. and is protected under
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* all applicable laws, including copyright laws.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
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* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY
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* DISCLAIMED.
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*
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
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* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS
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* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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*
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* Renesas reserves the right, without notice, to make changes to this
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* software and to discontinue the availability of this software.
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* By using this software, you agree to the additional terms and
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* conditions found by accessing the following link:
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* http://www.renesas.com/disclaimer
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********************************************************************************
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* Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved.
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*""FILE COMMENT""*********** Technical reference data **************************
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* System Name : SH7216 Sample Program
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* File Name : vect.h
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* Abstract : Definition of Vector
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* Version : 0.02.00
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* Device : SH7216
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* Tool-Chain : High-performance Embedded Workshop (Ver.4.05.01).
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* : C/C++ compiler package for the SuperH RISC engine family
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* : (Ver.9.03 Release00).
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* OS : None
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* H/W Platform: R0K572167 (CPU board)
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* Description :
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********************************************************************************
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* History : Mar.30,2009 Ver.0.02.00
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*""FILE COMMENT END""**********************************************************/
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#ifndef VECT_H
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#define VECT_H
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//;<<VECTOR DATA START (POWER ON RESET)>>
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// 0 Power On Reset PC
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extern void PowerON_Reset_PC(void);
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//;<<VECTOR DATA END (POWER ON RESET)>>
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// 1 Power On Reset SP
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//;<<VECTOR DATA START (MANUAL RESET)>>
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// 2 Manual Reset PC
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extern void Manual_Reset_PC(void);
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//;<<VECTOR DATA END (MANUAL RESET)>>
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// 3 Manual Reset SP
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// 4 Illegal code
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#pragma interrupt INT_Illegal_code
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extern void INT_Illegal_code(void);
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// 5 Reserved
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// 6 Illegal slot
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#pragma interrupt INT_Illegal_slot
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extern void INT_Illegal_slot(void);
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// 7 Reserved
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// 8 Reserved
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// 9 CPU Address error
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#pragma interrupt INT_CPU_Address
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extern void INT_CPU_Address(void);
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// 10 DMAC Address error
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#pragma interrupt INT_DMAC_Address
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extern void INT_DMAC_Address(void);
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// 11 NMI
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#pragma interrupt INT_NMI
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extern void INT_NMI(void);
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// 12 User breakpoint trap
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#pragma interrupt INT_User_Break
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extern void INT_User_Break(void);
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// 13 Reserved
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// 14 H-UDI
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#pragma interrupt INT_HUDI
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extern void INT_HUDI(void);
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// 15 Register bank over
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#pragma interrupt INT_Bank_Overflow
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extern void INT_Bank_Overflow(void);
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// 16 Register bank under
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#pragma interrupt INT_Bank_Underflow
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extern void INT_Bank_Underflow(void);
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// 17 ZERO_DIV
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#pragma interrupt INT_Divide_by_Zero
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extern void INT_Divide_by_Zero(void);
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// 18 OVER_DIV
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#pragma interrupt INT_Divide_Overflow
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extern void INT_Divide_Overflow(void);
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// 19 Reserved
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// 20 Reserved
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// 21 Reserved
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// 22 Reserved
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// 23 Reserved
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// 24 Reserved
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// 25 Reserved
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// 26 Reserved
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// 27 Reserved
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// 28 Reserved
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// 29 Reserved
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// 30 Reserved
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// 31 Reserved
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// 32 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA32
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extern void INT_TRAPA32(void);
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// 33 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA33
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extern void INT_TRAPA33(void);
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// 34 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA34
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extern void INT_TRAPA34(void);
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// 35 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA35
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extern void INT_TRAPA35(void);
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// 36 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA36
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extern void INT_TRAPA36(void);
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// 37 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA37
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extern void INT_TRAPA37(void);
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// 38 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA38
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extern void INT_TRAPA38(void);
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// 39 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA39
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extern void INT_TRAPA39(void);
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// 40 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA40
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extern void INT_TRAPA40(void);
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// 41 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA41
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extern void INT_TRAPA41(void);
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// 42 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA42
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extern void INT_TRAPA42(void);
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// 43 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA43
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extern void INT_TRAPA43(void);
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// 44 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA44
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extern void INT_TRAPA44(void);
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// 45 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA45
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extern void INT_TRAPA45(void);
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// 46 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA46
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extern void INT_TRAPA46(void);
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// 47 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA47
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extern void INT_TRAPA47(void);
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// 48 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA48
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extern void INT_TRAPA48(void);
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// 49 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA49
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extern void INT_TRAPA49(void);
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// 50 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA50
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extern void INT_TRAPA50(void);
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// 51 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA51
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extern void INT_TRAPA51(void);
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// 52 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA52
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extern void INT_TRAPA52(void);
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// 53 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA53
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extern void INT_TRAPA53(void);
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// 54 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA54
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extern void INT_TRAPA54(void);
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// 55 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA55
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extern void INT_TRAPA55(void);
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// 56 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA56
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extern void INT_TRAPA56(void);
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// 57 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA57
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extern void INT_TRAPA57(void);
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// 58 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA58
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extern void INT_TRAPA58(void);
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// 59 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA59
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extern void INT_TRAPA59(void);
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// 60 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA60
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extern void INT_TRAPA60(void);
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// 61 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA61
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extern void INT_TRAPA61(void);
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// 62 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA62
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extern void INT_TRAPA62(void);
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// 63 TRAPA (User Vecter)
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#pragma interrupt INT_TRAPA63
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extern void INT_TRAPA63(void);
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// 64 Interrupt IRQ0
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#pragma interrupt INT_IRQ0(resbank)
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extern void INT_IRQ0(void);
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// 65 Interrupt IRQ1
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#pragma interrupt INT_IRQ1(resbank)
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extern void INT_IRQ1(void);
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// 66 Interrupt IRQ2
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#pragma interrupt INT_IRQ2(resbank)
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extern void INT_IRQ2(void);
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// 67 Interrupt IRQ3
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#pragma interrupt INT_IRQ3(resbank)
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extern void INT_IRQ3(void);
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// 68 Interrupt IRQ4
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#pragma interrupt INT_IRQ4(resbank)
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extern void INT_IRQ4(void);
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// 69 Interrupt IRQ5
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#pragma interrupt INT_IRQ5(resbank)
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extern void INT_IRQ5(void);
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// 70 Interrupt IRQ6
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#pragma interrupt INT_IRQ6(resbank)
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extern void INT_IRQ6(void);
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// 71 Interrupt IRQ7
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#pragma interrupt INT_IRQ7(resbank)
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extern void INT_IRQ7(void);
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// 72 Reserved
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// 73 Reserved
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// 74 Reserved
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// 75 Reserved
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// 76 Reserved
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// 77 Reserved
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// 78 Reserved
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// 79 Reserved
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// 80 Interrupt PINT0
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#pragma interrupt INT_PINT0(resbank)
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extern void INT_PINT0(void);
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// 81 Interrupt PINT1
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#pragma interrupt INT_PINT1(resbank)
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extern void INT_PINT1(void);
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// 82 Interrupt PINT2
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#pragma interrupt INT_PINT2(resbank)
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extern void INT_PINT2(void);
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// 83 Interrupt PINT3
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#pragma interrupt INT_PINT3(resbank)
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extern void INT_PINT3(void);
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// 84 Interrupt PINT4
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#pragma interrupt INT_PINT4(resbank)
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extern void INT_PINT4(void);
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// 85 Interrupt PINT5
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#pragma interrupt INT_PINT5(resbank)
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extern void INT_PINT5(void);
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// 86 Interrupt PINT6
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#pragma interrupt INT_PINT6(resbank)
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extern void INT_PINT6(void);
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// 87 Interrupt PINT7
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#pragma interrupt INT_PINT7(resbank)
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extern void INT_PINT7(void);
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// 88 Reserved
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// 89 Reserved
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// 90 Reserved
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// 91 ROM FIFE
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#pragma interrupt INT_ROM_FIFE(resbank)
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extern void INT_ROM_FIFE(void);
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// 92 A/D ADI0
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#pragma interrupt INT_AD_ADI0(resbank)
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extern void INT_AD_ADI0(void);
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// 93 Reserved
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// 94 Reserved
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// 95 Reserved
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// 96 A/D ADI1
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#pragma interrupt INT_AD_ADI1(resbank)
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extern void INT_AD_ADI1(void);
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// 97 Reserved
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// 98 Reserved
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// 99 Reserved
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// 100 Reserved
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// 101 Reserved
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// 102 Reserved
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// 103 Reserved
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// 104 RCANET0 ERS_0
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#pragma interrupt INT_RCANET0_ERS_0
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extern void INT_RCANET0_ERS_0(void);
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// 105 RCANET0 OVR_0
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#pragma interrupt INT_RCANET0_OVR_0
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extern void INT_RCANET0_OVR_0(void);
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// 106 RCANET0 RM01_0
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#pragma interrupt INT_RCANET0_RM01_0
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extern void INT_RCANET0_RM01_0(void);
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// 107 RCANET0 SLE_0
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#pragma interrupt INT_RCANET0_SLE_0
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extern void INT_RCANET0_SLE_0(void);
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// 108 DMAC0 DEI0
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#pragma interrupt INT_DMAC0_DEI0(resbank)
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extern void INT_DMAC0_DEI0(void);
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// 109 DMAC0 HEI0
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#pragma interrupt INT_DMAC0_HEI0(resbank)
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extern void INT_DMAC0_HEI0(void);
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// 110 Reserved
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// 111 Reserved
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// 112 DMAC1 DEI1
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#pragma interrupt INT_DMAC1_DEI1(resbank)
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extern void INT_DMAC1_DEI1(void);
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// 113 DMAC1 HEI1
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#pragma interrupt INT_DMAC1_HEI1(resbank)
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extern void INT_DMAC1_HEI1(void);
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// 114 Reserved
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// 115 Reserved
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// 116 DMAC2 DEI2
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#pragma interrupt INT_DMAC2_DEI2(resbank)
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extern void INT_DMAC2_DEI2(void);
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// 117 DMAC2 HEI2
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#pragma interrupt INT_DMAC2_HEI2(resbank)
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extern void INT_DMAC2_HEI2(void);
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// 118 Reserved
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// 119 Reserved
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// 120 DMAC3 DEI3
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#pragma interrupt INT_DMAC3_DEI3(resbank)
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extern void INT_DMAC3_DEI3(void);
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// 121 DMAC3 HEI3
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#pragma interrupt INT_DMAC3_HEI3(resbank)
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extern void INT_DMAC3_HEI3(void);
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// 122 Reserved
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// 123 Reserved
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// 124 DMAC4 DEI4
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#pragma interrupt INT_DMAC4_DEI4(resbank)
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extern void INT_DMAC4_DEI4(void);
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// 125 DMAC4 HEI4
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#pragma interrupt INT_DMAC4_HEI4(resbank)
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extern void INT_DMAC4_HEI4(void);
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// 126 Reserved
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// 127 Reserved
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// 128 DMAC5 DEI5
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#pragma interrupt INT_DMAC5_DEI5(resbank)
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extern void INT_DMAC5_DEI5(void);
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// 129 DMAC5 HEI5
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#pragma interrupt INT_DMAC5_HEI5(resbank)
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extern void INT_DMAC5_HEI5(void);
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// 130 Reserved
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// 131 Reserved
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// 132 DMAC6 DEI6
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#pragma interrupt INT_DMAC6_DEI6(resbank)
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extern void INT_DMAC6_DEI6(void);
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// 133 DMAC6 HEI6
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#pragma interrupt INT_DMAC6_HEI6(resbank)
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extern void INT_DMAC6_HEI6(void);
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// 134 Reserved
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// 135 Reserved
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// 136 DMAC7 DEI7
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#pragma interrupt INT_DMAC7_DEI7(resbank)
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extern void INT_DMAC7_DEI7(void);
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// 137 DMAC7 HEI7
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#pragma interrupt INT_DMAC7_HEI7(resbank)
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extern void INT_DMAC7_HEI7(void);
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// 138 Reserved
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// 139 Reserved
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// 140 CMT CMI0
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#pragma interrupt INT_CMT_CMI0(resbank)
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extern void INT_CMT_CMI0(void);
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// 141 Reserved
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// 142 Reserved
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// 143 Reserved
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// 144 CMT CMI1
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#pragma interrupt INT_CMT_CMI1(resbank)
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extern void INT_CMT_CMI1(void);
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// 145 Reserved
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// 146 Reserved
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// 147 Reserved
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// 148 BSC CMTI
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#pragma interrupt INT_BSC_CMTI(resbank)
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extern void INT_BSC_CMTI(void);
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// 149 Reserved
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// 150 USB EP4FULL
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#pragma interrupt INT_USB_EP4FULL(resbank)
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extern void INT_USB_EP4FULL(void);
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// 151 USB EP5EMPTY
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#pragma interrupt INT_USB_EP5EMPTY(resbank)
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extern void INT_USB_EP5EMPTY(void);
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// 152 WDT ITI
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#pragma interrupt INT_WDT_ITI(resbank)
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extern void INT_WDT_ITI(void);
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// 153 E-DMAC EINT0
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#pragma interrupt INT_EDMAC_EINT0(resbank)
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extern void INT_EDMAC_EINT0(void);
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// 154 USB EP1FULL
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#pragma interrupt INT_USB_EP1FULL(resbank)
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extern void INT_USB_EP1FULL(void);
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// 155 USB EP2EMPTY
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#pragma interrupt INT_USB_EP2EMPTY(resbank)
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extern void INT_USB_EP2EMPTY(void);
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// 156 MTU2 MTU0 TGI0A
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#pragma interrupt INT_MTU2_MTU0_TGI0A(resbank)
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extern void INT_MTU2_MTU0_TGI0A(void);
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// 157 MTU2 MTU0 TGI0B
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#pragma interrupt INT_MTU2_MTU0_TGI0B(resbank)
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extern void INT_MTU2_MTU0_TGI0B(void);
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// 158 MTU2 MTU0 TGI0C
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#pragma interrupt INT_MTU2_MTU0_TGI0C(resbank)
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extern void INT_MTU2_MTU0_TGI0C(void);
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// 159 MTU2 MTU0 TGI0D
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#pragma interrupt INT_MTU2_MTU0_TGI0D(resbank)
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extern void INT_MTU2_MTU0_TGI0D(void);
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// 160 MTU2 MTU0 TGI0V
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#pragma interrupt INT_MTU2_MTU0_TGI0V(resbank)
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extern void INT_MTU2_MTU0_TGI0V(void);
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// 161 MTU2 MTU0 TGI0E
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#pragma interrupt INT_MTU2_MTU0_TGI0E(resbank)
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extern void INT_MTU2_MTU0_TGI0E(void);
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// 162 MTU2 MTU0 TGI0F
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#pragma interrupt INT_MTU2_MTU0_TGI0F(resbank)
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extern void INT_MTU2_MTU0_TGI0F(void);
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// 163 Reserved
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// 164 MTU2 MTU1 TGI1A
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#pragma interrupt INT_MTU2_MTU1_TGI1A(resbank)
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extern void INT_MTU2_MTU1_TGI1A(void);
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// 165 MTU2 MTU1 TGI1B
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#pragma interrupt INT_MTU2_MTU1_TGI1B(resbank)
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extern void INT_MTU2_MTU1_TGI1B(void);
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// 166 Reserved
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// 167 Reserved
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// 168 MTU2 MTU1 TGI1V
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#pragma interrupt INT_MTU2_MTU1_TGI1V(resbank)
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extern void INT_MTU2_MTU1_TGI1V(void);
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// 169 MTU2 MTU1 TGI1U
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#pragma interrupt INT_MTU2_MTU1_TGI1U(resbank)
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extern void INT_MTU2_MTU1_TGI1U(void);
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// 170 Reserved
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// 171 Reserved
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// 172 MTU2 MTU2 TGI2A
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#pragma interrupt INT_MTU2_MTU2_TGI2A(resbank)
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extern void INT_MTU2_MTU2_TGI2A(void);
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// 173 MTU2 MTU2 TGI2B
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#pragma interrupt INT_MTU2_MTU2_TGI2B(resbank)
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extern void INT_MTU2_MTU2_TGI2B(void);
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// 174 Reserved
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// 175 Reserved
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// 176 MTU2 MTU2 TGI2V
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#pragma interrupt INT_MTU2_MTU2_TGI2V(resbank)
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extern void INT_MTU2_MTU2_TGI2V(void);
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// 177 MTU2 MTU2 TGI2U
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#pragma interrupt INT_MTU2_MTU2_TGI2U(resbank)
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extern void INT_MTU2_MTU2_TGI2U(void);
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// 178 Reserved
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// 179 Reserved
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// 180 MTU2 MTU3 TGI3A
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#pragma interrupt INT_MTU2_MTU3_TGI3A(resbank)
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extern void INT_MTU2_MTU3_TGI3A(void);
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// 181 MTU2 MTU3 TGI3B
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#pragma interrupt INT_MTU2_MTU3_TGI3B(resbank)
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extern void INT_MTU2_MTU3_TGI3B(void);
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// 182 MTU2 MTU3 TGI3C
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#pragma interrupt INT_MTU2_MTU3_TGI3C(resbank)
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extern void INT_MTU2_MTU3_TGI3C(void);
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// 183 MTU2 MTU3 TGI3D
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#pragma interrupt INT_MTU2_MTU3_TGI3D(resbank)
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extern void INT_MTU2_MTU3_TGI3D(void);
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// 184 MTU2 MTU3 TGI3V
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#pragma interrupt INT_MTU2_MTU3_TGI3V(resbank)
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extern void INT_MTU2_MTU3_TGI3V(void);
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// 185 Reserved
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// 186 Reserved
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// 187 Reserved
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// 188 MTU2 MTU4 TGI4A
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#pragma interrupt INT_MTU2_MTU4_TGI4A(resbank)
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extern void INT_MTU2_MTU4_TGI4A(void);
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// 189 MTU2 MTU4 TGI4B
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#pragma interrupt INT_MTU2_MTU4_TGI4B(resbank)
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extern void INT_MTU2_MTU4_TGI4B(void);
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// 190 MTU2 MTU4 TGI4C
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#pragma interrupt INT_MTU2_MTU4_TGI4C(resbank)
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extern void INT_MTU2_MTU4_TGI4C(void);
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// 191 MTU2 MTU4 TGI4D
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#pragma interrupt INT_MTU2_MTU4_TGI4D(resbank)
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extern void INT_MTU2_MTU4_TGI4D(void);
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// 192 MTU2 MTU4 TGI4V
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#pragma interrupt INT_MTU2_MTU4_TGI4V(resbank)
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extern void INT_MTU2_MTU4_TGI4V(void);
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// 193 Reserved
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// 194 Reserved
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// 195 Reserved
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// 196 MTU2 MTU5 TGI5U
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#pragma interrupt INT_MTU2_MTU5_TGI5U(resbank)
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extern void INT_MTU2_MTU5_TGI5U(void);
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// 197 MTU2 MTU5 TGI5V
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#pragma interrupt INT_MTU2_MTU5_TGI5V(resbank)
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extern void INT_MTU2_MTU5_TGI5V(void);
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// 198 MTU2 MTU5 TGI5W
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#pragma interrupt INT_MTU2_MTU5_TGI5W(resbank)
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extern void INT_MTU2_MTU5_TGI5W(void);
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// 199 Reserved
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// 200 POE2 OEI1
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|
#pragma interrupt INT_POE2_OEI1(resbank)
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|
extern void INT_POE2_OEI1(void);
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// 201 POE2 OEI2
|
|
#pragma interrupt INT_POE2_OEI2(resbank)
|
|
extern void INT_POE2_OEI2(void);
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// 202 Reserved
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// 203 Reserved
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// 204 MTU2S MTU3S TGI3A
|
|
#pragma interrupt INT_MTU2S_MTU3S_TGI3A(resbank)
|
|
extern void INT_MTU2S_MTU3S_TGI3A(void);
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|
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// 205 MTU2S MTU3S TGI3B
|
|
#pragma interrupt INT_MTU2S_MTU3S_TGI3B(resbank)
|
|
extern void INT_MTU2S_MTU3S_TGI3B(void);
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|
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// 206 MTU2S MTU3S TGI3C
|
|
#pragma interrupt INT_MTU2S_MTU3S_TGI3C(resbank)
|
|
extern void INT_MTU2S_MTU3S_TGI3C(void);
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|
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// 207 MTU2S MTU3S TGI3D
|
|
#pragma interrupt INT_MTU2S_MTU3S_TGI3D(resbank)
|
|
extern void INT_MTU2S_MTU3S_TGI3D(void);
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|
|
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// 208 MTU2S MTU3S TGI3V
|
|
#pragma interrupt INT_MTU2S_MTU3S_TGI3V(resbank)
|
|
extern void INT_MTU2S_MTU3S_TGI3V(void);
|
|
|
|
// 209 Reserved
|
|
|
|
// 210 Reserved
|
|
|
|
// 211 Reserved
|
|
|
|
// 212 MTU2S MTU4S TGI4A
|
|
#pragma interrupt INT_MTU2S_MTU4S_TGI4A(resbank)
|
|
extern void INT_MTU2S_MTU4S_TGI4A(void);
|
|
|
|
// 213 MTU2S MTU4S TGI4B
|
|
#pragma interrupt INT_MTU2S_MTU4S_TGI4B(resbank)
|
|
extern void INT_MTU2S_MTU4S_TGI4B(void);
|
|
|
|
// 214 MTU2S MTU4S TGI4C
|
|
#pragma interrupt INT_MTU2S_MTU4S_TGI4C(resbank)
|
|
extern void INT_MTU2S_MTU4S_TGI4C(void);
|
|
|
|
// 215 MTU2S MTU4S TGI4D
|
|
#pragma interrupt INT_MTU2S_MTU4S_TGI4D(resbank)
|
|
extern void INT_MTU2S_MTU4S_TGI4D(void);
|
|
|
|
// 216 MTU2S MTU4S TGI4V
|
|
#pragma interrupt INT_MTU2S_MTU4S_TGI4V(resbank)
|
|
extern void INT_MTU2S_MTU4S_TGI4V(void);
|
|
|
|
// 217 Reserved
|
|
|
|
// 218 Reserved
|
|
|
|
// 219 Reserved
|
|
|
|
// 220 MTU2S MTU5S TGI5U
|
|
#pragma interrupt INT_MTU2S_MTU5S_TGI5U(resbank)
|
|
extern void INT_MTU2S_MTU5S_TGI5U(void);
|
|
|
|
// 221 MTU2S MTU5S TGI5V
|
|
#pragma interrupt INT_MTU2S_MTU5S_TGI5V(resbank)
|
|
extern void INT_MTU2S_MTU5S_TGI5V(void);
|
|
|
|
// 222 MTU2S MTU5S TGI5W
|
|
#pragma interrupt INT_MTU2S_MTU5S_TGI5W(resbank)
|
|
extern void INT_MTU2S_MTU5S_TGI5W(void);
|
|
|
|
// 223 Reserved
|
|
|
|
// 224 POE2 OEI3
|
|
#pragma interrupt INT_POE2_OEI3(resbank)
|
|
extern void INT_POE2_OEI3(void);
|
|
|
|
// 225 Reserved
|
|
|
|
// 226 USB USI0
|
|
#pragma interrupt INT_USB_USI0(resbank)
|
|
extern void INT_USB_USI0(void);
|
|
|
|
// 227 USB USI1
|
|
#pragma interrupt INT_USB_USI1(resbank)
|
|
extern void INT_USB_USI1(void);
|
|
|
|
// 228 IIC3 STPI
|
|
#pragma interrupt INT_IIC3_STPI(resbank)
|
|
extern void INT_IIC3_STPI(void);
|
|
|
|
// 229 IIC3 NAKI
|
|
#pragma interrupt INT_IIC3_NAKI(resbank)
|
|
extern void INT_IIC3_NAKI(void);
|
|
|
|
// 230 IIC3 RXI
|
|
#pragma interrupt INT_IIC3_RXI(resbank)
|
|
extern void INT_IIC3_RXI(void);
|
|
|
|
// 231 IIC3 TXI
|
|
#pragma interrupt INT_IIC3_TXI(resbank)
|
|
extern void INT_IIC3_TXI(void);
|
|
|
|
// 232 IIC3 TEI
|
|
#pragma interrupt INT_IIC3_TEI(resbank)
|
|
extern void INT_IIC3_TEI(void);
|
|
|
|
// 233 RSPI SPERI
|
|
#pragma interrupt INT_RSPI_SPERI(resbank)
|
|
extern void INT_RSPI_SPERI(void);
|
|
|
|
// 234 RSPI SPRXI
|
|
#pragma interrupt INT_RSPI_SPRXI(resbank)
|
|
extern void INT_RSPI_SPRXI(void);
|
|
|
|
// 235 RSPI SPTXI
|
|
#pragma interrupt INT_RSPI_SPTXI(resbank)
|
|
extern void INT_RSPI_SPTXI(void);
|
|
|
|
// 236 SCI SCI4 ERI4
|
|
#pragma interrupt INT_SCI_SCI4_ERI4(resbank)
|
|
extern void INT_SCI_SCI4_ERI4(void);
|
|
|
|
// 237 SCI SCI4 RXI4
|
|
#pragma interrupt INT_SCI_SCI4_RXI4(resbank)
|
|
extern void INT_SCI_SCI4_RXI4(void);
|
|
|
|
// 238 SCI SCI4 TXI4
|
|
#pragma interrupt INT_SCI_SCI4_TXI4(resbank)
|
|
extern void INT_SCI_SCI4_TXI4(void);
|
|
|
|
// 239 SCI SCI4 TEI4
|
|
#pragma interrupt INT_SCI_SCI4_TEI4(resbank)
|
|
extern void INT_SCI_SCI4_TEI4(void);
|
|
|
|
// 240 SCI SCI0 ERI0
|
|
#pragma interrupt INT_SCI_SCI0_ERI0(resbank)
|
|
extern void INT_SCI_SCI0_ERI0(void);
|
|
|
|
// 241 SCI SCI0 RXI0
|
|
#pragma interrupt INT_SCI_SCI0_RXI0(resbank)
|
|
extern void INT_SCI_SCI0_RXI0(void);
|
|
|
|
// 242 SCI SCI0 TXI0
|
|
#pragma interrupt INT_SCI_SCI0_TXI0(resbank)
|
|
extern void INT_SCI_SCI0_TXI0(void);
|
|
|
|
// 243 SCI SCI0 TEI0
|
|
#pragma interrupt INT_SCI_SCI0_TEI0(resbank)
|
|
extern void INT_SCI_SCI0_TEI0(void);
|
|
|
|
// 244 SCI SCI1 ERI1
|
|
#pragma interrupt INT_SCI_SCI1_ERI1(resbank)
|
|
extern void INT_SCI_SCI1_ERI1(void);
|
|
|
|
// 245 SCI SCI1 RXI1
|
|
#pragma interrupt INT_SCI_SCI1_RXI1(resbank)
|
|
extern void INT_SCI_SCI1_RXI1(void);
|
|
|
|
// 246 SCI SCI1 TXI1
|
|
#pragma interrupt INT_SCI_SCI1_TXI1(resbank)
|
|
extern void INT_SCI_SCI1_TXI1(void);
|
|
|
|
// 247 SCI SCI1 TEI1
|
|
#pragma interrupt INT_SCI_SCI1_TEI1(resbank)
|
|
extern void INT_SCI_SCI1_TEI1(void);
|
|
|
|
// 248 SCI SCI2 ERI2
|
|
#pragma interrupt INT_SCI_SCI2_ERI2(resbank)
|
|
extern void INT_SCI_SCI2_ERI2(void);
|
|
|
|
// 249 SCI SCI2 RXI2
|
|
#pragma interrupt INT_SCI_SCI2_RXI2(resbank)
|
|
extern void INT_SCI_SCI2_RXI2(void);
|
|
|
|
// 250 SCI SCI2 TXI2
|
|
#pragma interrupt INT_SCI_SCI2_TXI2(resbank)
|
|
extern void INT_SCI_SCI2_TXI2(void);
|
|
|
|
// 251 SCI SCI2 TEI2
|
|
#pragma interrupt INT_SCI_SCI2_TEI2(resbank)
|
|
extern void INT_SCI_SCI2_TEI2(void);
|
|
|
|
// 252 SCIF SCIF3 BRI3
|
|
#pragma interrupt INT_SCIF_SCIF3_BRI3(resbank)
|
|
extern void INT_SCIF_SCIF3_BRI3(void);
|
|
|
|
// 253 SCIF SCIF3 ERI3
|
|
#pragma interrupt INT_SCIF_SCIF3_ERI3(resbank)
|
|
extern void INT_SCIF_SCIF3_ERI3(void);
|
|
|
|
// 254 SCIF SCIF3 RXI3
|
|
#pragma interrupt INT_SCIF_SCIF3_RXI3(resbank)
|
|
extern void INT_SCIF_SCIF3_RXI3(void);
|
|
|
|
// 255 SCIF SCIF3 TXI3
|
|
#pragma interrupt INT_SCIF_SCIF3_TXI3(resbank)
|
|
extern void INT_SCIF_SCIF3_TXI3(void);
|
|
|
|
// Dummy
|
|
#pragma interrupt Dummy(resbank)
|
|
extern void Dummy(void);
|
|
|
|
#endif /* VECT_H */
|
|
|
|
/* End of File */
|