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63 lines
2.4 KiB
C
63 lines
2.4 KiB
C
/*
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* FreeRTOS Kernel V10.1.0
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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#include "FreeRTOS.h"
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/*-----------------------------------------------------------*/
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/* Called by the startup code to initialise the run time system. */
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unsigned char __low_level_init( void );
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/*-----------------------------------------------------------*/
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unsigned char __low_level_init( void )
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{
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unsigned char resetflag = RESF;
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unsigned portBASE_TYPE i = 0;
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portDISABLE_INTERRUPTS(); /* disable global interrupts */
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PRCMD = 0x00; /* On-chip debug mode */
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PCC = 0x00; /* high speed mode fCPU */
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VSWC = 0x00;
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WDTM2 = 0xF; /* Stop watchdog Timer */
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PLLS = 0x03; /* Set PLL stabilisation time */
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PLLON = 1; /* activate PLL */
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for( i = 0; i <= 2000; i++ ) /* Wait for stabilisation */
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{
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portNOP();
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}
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while( LOCK ) /* Wait for PLL frequency stabiliasation */
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{
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portNOP();
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}
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SELPLL = 1; /* Set CPU operation to PLL mode */
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return pdTRUE;
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}
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/*-----------------------------------------------------------*/
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