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423 lines
16 KiB
C
423 lines
16 KiB
C
/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief MACB example driver for EVK1100 board.
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*
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* This file defines a useful set of functions for the MACB interface on
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* AVR32 devices.
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices with a MACB module can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of ATMEL may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef AVR32_MACB_H
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#define AVR32_MACB_H
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#include <avr32/io.h>
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#ifdef FREERTOS_USED
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#include <arch/sys_arch.h>
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#endif
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#include "conf_eth.h"
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/*! \name Rx Ring descriptor flags
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*/
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//! @{
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#define AVR32_MACB_RX_USED_OFFSET 0
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#define AVR32_MACB_RX_USED_SIZE 1
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#define AVR32_MACB_RX_WRAP_OFFSET 1
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#define AVR32_MACB_RX_WRAP_SIZE 1
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#define AVR32_MACB_RX_LEN_OFFSET 0
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#define AVR32_MACB_RX_LEN_SIZE 12
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#define AVR32_MACB_RX_OFFSET_OFFSET 12
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#define AVR32_MACB_RX_OFFSET_SIZE 2
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#define AVR32_MACB_RX_SOF_OFFSET 14
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#define AVR32_MACB_RX_SOF_SIZE 1
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#define AVR32_MACB_RX_EOF_OFFSET 15
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#define AVR32_MACB_RX_EOF_SIZE 1
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#define AVR32_MACB_RX_CFI_OFFSET 16
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#define AVR32_MACB_RX_CFI_SIZE 1
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//! @}
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/*! \name Tx Ring descriptor flags
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*/
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//! @{
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#define AVR32_MACB_TX_LEN_OFFSET 0
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#define AVR32_MACB_TX_LEN_SIZE 11
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#define AVR32_MACB_TX_EOF_OFFSET 15
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#define AVR32_MACB_TX_EOF_SIZE 1
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#define AVR32_MACB_TX_NOCRC_OFFSET 16
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#define AVR32_MACB_TX_NOCRC_SIZE 1
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#define AVR32_MACB_TX_EMF_OFFSET 27
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#define AVR32_MACB_TX_EMF_SIZE 1
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#define AVR32_MACB_TX_UNR_OFFSET 28
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#define AVR32_MACB_TX_UNR_SIZE 1
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#define AVR32_MACB_TX_MAXRETRY_OFFSET 29
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#define AVR32_MACB_TX_MAXRETRY_SIZE 1
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#define AVR32_MACB_TX_WRAP_OFFSET 30
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#define AVR32_MACB_TX_WRAP_SIZE 1
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#define AVR32_MACB_TX_USED_OFFSET 31
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#define AVR32_MACB_TX_USED_SIZE 1
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//! @}
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/*! \name Generic MII registers.
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*/
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//! @{
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#define PHY_BMCR 0x00 //!< Basic mode control register
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#define PHY_BMSR 0x01 //!< Basic mode status register
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#define PHY_PHYSID1 0x02 //!< PHYS ID 1
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#define PHY_PHYSID2 0x03 //!< PHYS ID 2
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#define PHY_ADVERTISE 0x04 //!< Advertisement control reg
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#define PHY_LPA 0x05 //!< Link partner ability reg
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//! @}
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#if BOARD == EVK1100
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/*! \name Extended registers for DP83848
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*/
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//! @{
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#define PHY_RBR 0x17 //!< RMII Bypass reg
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#define PHY_MICR 0x11 //!< Interrupt Control reg
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#define PHY_MISR 0x12 //!< Interrupt Status reg
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#define PHY_PHYCR 0x19 //!< Phy CTRL reg
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//! @}
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#endif
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/*! \name Basic mode control register.
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*/
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//! @{
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#define BMCR_RESV 0x007f //!< Unused...
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#define BMCR_CTST 0x0080 //!< Collision test
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#define BMCR_FULLDPLX 0x0100 //!< Full duplex
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#define BMCR_ANRESTART 0x0200 //!< Auto negotiation restart
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#define BMCR_ISOLATE 0x0400 //!< Disconnect PHY from MII
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#define BMCR_PDOWN 0x0800 //!< Powerdown the PHY
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#define BMCR_ANENABLE 0x1000 //!< Enable auto negotiation
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#define BMCR_SPEED100 0x2000 //!< Select 100Mbps
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#define BMCR_LOOPBACK 0x4000 //!< TXD loopback bits
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#define BMCR_RESET 0x8000 //!< Reset the PHY
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//! @}
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/*! \name Basic mode status register.
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*/
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//! @{
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#define BMSR_ERCAP 0x0001 //!< Ext-reg capability
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#define BMSR_JCD 0x0002 //!< Jabber detected
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#define BMSR_LSTATUS 0x0004 //!< Link status
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#define BMSR_ANEGCAPABLE 0x0008 //!< Able to do auto-negotiation
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#define BMSR_RFAULT 0x0010 //!< Remote fault detected
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#define BMSR_ANEGCOMPLETE 0x0020 //!< Auto-negotiation complete
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#define BMSR_RESV 0x00c0 //!< Unused...
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#define BMSR_ESTATEN 0x0100 //!< Extended Status in R15
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#define BMSR_100FULL2 0x0200 //!< Can do 100BASE-T2 HDX
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#define BMSR_100HALF2 0x0400 //!< Can do 100BASE-T2 FDX
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#define BMSR_10HALF 0x0800 //!< Can do 10mbps, half-duplex
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#define BMSR_10FULL 0x1000 //!< Can do 10mbps, full-duplex
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#define BMSR_100HALF 0x2000 //!< Can do 100mbps, half-duplex
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#define BMSR_100FULL 0x4000 //!< Can do 100mbps, full-duplex
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#define BMSR_100BASE4 0x8000 //!< Can do 100mbps, 4k packets
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//! @}
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/*! \name Advertisement control register.
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*/
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//! @{
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#define ADVERTISE_SLCT 0x001f //!< Selector bits
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#define ADVERTISE_CSMA 0x0001 //!< Only selector supported
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#define ADVERTISE_10HALF 0x0020 //!< Try for 10mbps half-duplex
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#define ADVERTISE_1000XFULL 0x0020 //!< Try for 1000BASE-X full-duplex
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#define ADVERTISE_10FULL 0x0040 //!< Try for 10mbps full-duplex
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#define ADVERTISE_1000XHALF 0x0040 //!< Try for 1000BASE-X half-duplex
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#define ADVERTISE_100HALF 0x0080 //!< Try for 100mbps half-duplex
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#define ADVERTISE_1000XPAUSE 0x0080 //!< Try for 1000BASE-X pause
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#define ADVERTISE_100FULL 0x0100 //!< Try for 100mbps full-duplex
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#define ADVERTISE_1000XPSE_ASYM 0x0100 //!< Try for 1000BASE-X asym pause
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#define ADVERTISE_100BASE4 0x0200 //!< Try for 100mbps 4k packets
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#define ADVERTISE_PAUSE_CAP 0x0400 //!< Try for pause
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#define ADVERTISE_PAUSE_ASYM 0x0800 //!< Try for asymetric pause
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#define ADVERTISE_RESV 0x1000 //!< Unused...
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#define ADVERTISE_RFAULT 0x2000 //!< Say we can detect faults
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#define ADVERTISE_LPACK 0x4000 //!< Ack link partners response
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#define ADVERTISE_NPAGE 0x8000 //!< Next page bit
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//! @}
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#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
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#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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ADVERTISE_100HALF | ADVERTISE_100FULL)
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/*! \name Link partner ability register.
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*/
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//! @{
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#define LPA_SLCT 0x001f //!< Same as advertise selector
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#define LPA_10HALF 0x0020 //!< Can do 10mbps half-duplex
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#define LPA_1000XFULL 0x0020 //!< Can do 1000BASE-X full-duplex
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#define LPA_10FULL 0x0040 //!< Can do 10mbps full-duplex
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#define LPA_1000XHALF 0x0040 //!< Can do 1000BASE-X half-duplex
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#define LPA_100HALF 0x0080 //!< Can do 100mbps half-duplex
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#define LPA_1000XPAUSE 0x0080 //!< Can do 1000BASE-X pause
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#define LPA_100FULL 0x0100 //!< Can do 100mbps full-duplex
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#define LPA_1000XPAUSE_ASYM 0x0100 //!< Can do 1000BASE-X pause asym
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#define LPA_100BASE4 0x0200 //!< Can do 100mbps 4k packets
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#define LPA_PAUSE_CAP 0x0400 //!< Can pause
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#define LPA_PAUSE_ASYM 0x0800 //!< Can pause asymetrically
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#define LPA_RESV 0x1000 //!< Unused...
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#define LPA_RFAULT 0x2000 //!< Link partner faulted
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#define LPA_LPACK 0x4000 //!< Link partner acked us
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#define LPA_NPAGE 0x8000 //!< Next page bit
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#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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//! @}
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#if BOARD == EVK1100
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/*! RMII Bypass Register */
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#define RBR_RMII 0x0020 //!< RMII Mode
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/*! \name Interrupt Ctrl Register.
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*/
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//! @{
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#define MICR_INTEN 0x0002 //!< Enable interrupts
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#define MICR_INTOE 0x0001 //!< Enable INT output
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//! @}
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/*! \name Interrupt Status Register.
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*/
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//! @{
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#define MISR_ED_INT_EN 0x0040 //!< Energy Detect enabled
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#define MISR_LINK_INT_EN 0x0020 //!< Link status change enabled
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#define MISR_SPD_INT_EN 0x0010 //!< Speed change enabled
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#define MISR_DP_INT_EN 0x0008 //!< Duplex mode change enabled
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#define MISR_ANC_INT_EN 0x0004 //!< Auto-Neg complete enabled
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#define MISR_FHF_INT_EN 0x0002 //!< False Carrier enabled
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#define MISR_RHF_INT_EN 0x0001 //!< Receive Error enabled
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#define MISR_ED_INT 0x4000 //!< Energy Detect
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#define MISR_LINK_INT 0x2000 //!< Link status change
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#define MISR_SPD_INT 0x1000 //!< Speed change
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#define MISR_DP_INT 0x0800 //!< Duplex mode change
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#define MISR_ANC_INT 0x0400 //!< Auto-Neg complete
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#define MISR_FHF_INT 0x0200 //!< False Carrier
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#define MISR_RHF_INT 0x0100 //!< Receive Error
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//! @}
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/*! \name Phy Ctrl Register.
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*/
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//! @{
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#define PHYCR_MDIX_EN 0x8000 //!< Enable Auto MDIX
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#define PHYCR_MDIX_FORCE 0x4000 //!< Force MDIX crossed
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//! @}
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#endif
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/*! Packet structure.
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*/
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//! @{
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typedef struct
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{
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char *data;
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unsigned int len;
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} macb_packet_t;
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//! @}
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/*! Receive Transfer descriptor structure.
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*/
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//! @{
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typedef struct _AVR32_RxTdDescriptor {
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unsigned int addr;
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union
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{
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unsigned int status;
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struct {
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unsigned int BroadCast:1;
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unsigned int MultiCast:1;
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unsigned int UniCast:1;
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unsigned int ExternalAdd:1;
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unsigned int Res1:1;
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unsigned int Sa1Match:1;
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unsigned int Sa2Match:1;
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unsigned int Sa3Match:1;
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unsigned int Sa4Match:1;
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unsigned int TypeID:1;
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unsigned int VlanTag:1;
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unsigned int PriorityTag:1;
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unsigned int VlanPriority:3;
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unsigned int Cfi:1;
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unsigned int EndOfFrame:1;
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unsigned int StartOfFrame:1;
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unsigned int Rxbuf_off:2;
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unsigned int Res0:1;
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unsigned int Length:11;
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}S_Status;
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}U_Status;
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}AVR32_RxTdDescriptor, *AVR32P_RxTdDescriptor;
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//! @}
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/*! Transmit Transfer descriptor structure.
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*/
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//! @{
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typedef struct _AVR32_TxTdDescriptor {
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unsigned int addr;
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union
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{
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unsigned int status;
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struct {
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unsigned int BuffUsed:1;
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unsigned int Wrap:1;
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unsigned int TransmitError:1;
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unsigned int TransmitUnderrun:1;
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unsigned int BufExhausted:1;
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unsigned int Res1:10;
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unsigned int NoCrc:1;
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unsigned int LastBuff:1;
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unsigned int Res0:4;
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unsigned int Length:11;
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}S_Status;
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}U_Status;
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}AVR32_TxTdDescriptor, *AVR32P_TxTdDescriptor;
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//! @}
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/*! Mask for frame used. */
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#define AVR32_OWNERSHIP_BIT 0x00000001
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/*! Receive status defintion.
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*/
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//! @{
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#define AVR32_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected
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#define AVR32_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match
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#define AVR32_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match
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#define AVR32_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match
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#define AVR32_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match
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#define AVR32_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match
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#define AVR32_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match
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#define AVR32_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match
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#define AVR32_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match
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#define AVR32_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected
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#define AVR32_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected
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#define AVR32_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask
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#define AVR32_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator
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#define AVR32_EOF ((unsigned int) (1 << 15)) //* EOF
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#define AVR32_SOF ((unsigned int) (1 << 14)) //* SOF
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#define AVR32_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask
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#define AVR32_LENGTH_FRAME ((unsigned int) 0x0FFF) //* Length of frame
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//! @}
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/* Transmit Status definition */
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//! @{
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#define AVR32_TRANSMIT_OK ((unsigned int) (1 << 31)) //*
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#define AVR32_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor
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#define AVR32_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error
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#define AVR32_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun
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#define AVR32_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame
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#define AVR32_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame
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#define AVR32_LAST_BUFFER ((unsigned int) (1 << 15)) //*
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//! @}
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/**
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* \brief Initialise the MACB driver.
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*
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* \param *macb Base address of the MACB
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*
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* \return TRUE if success, FALSE otherwise.
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*/
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Bool xMACBInit( volatile avr32_macb_t * macb );
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/**
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* \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the
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* MACB Tx buffers, then indicates to the MACB that the buffer is ready.
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* If lEndOfFrame is true then the data being copied is the end of the frame
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* and the frame can be transmitted.
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*
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* \param *macb Base address of the MACB
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* \param *pcFrom Address of the data buffer
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* \param ulLength Length of the frame
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* \param lEndOfFrame Flag for End Of Frame
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*
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* \return length sent.
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*/
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long lMACBSend(volatile avr32_macb_t * macb, char *pcFrom, unsigned long ulLength, long lEndOfFrame );
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/**
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* \brief Frames can be read from the MACB in multiple sections.
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* Read ulSectionLength bytes from the MACB receive buffers to pcTo.
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* ulTotalFrameLength is the size of the entire frame. Generally vMACBRead
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* will be repetedly called until the sum of all the ulSectionLenths totals
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* the value of ulTotalFrameLength.
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*
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* \param *pcTo Address of the buffer
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* \param ulSectionLength Length of the buffer
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* \param ulTotalFrameLength Length of the frame
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*/
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void vMACBRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength );
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/**
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* \brief Called by the Tx interrupt, this function traverses the buffers used to
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* hold the frame that has just completed transmission and marks each as
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* free again.
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*/
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void vClearMACBTxBuffer( void );
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/**
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* \brief Suspend on a semaphore waiting either for the semaphore to be obtained
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* or a timeout. The semaphore is used by the MACB ISR to indicate that
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* data has been received and is ready for processing.
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*
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* \param ulTimeOut time to wait for an input
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*
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*/
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void vMACBWaitForInput( unsigned long ulTimeOut );
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/**
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* \brief Function to get length of the next frame in the receive buffers
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*
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* \return the length of the next frame in the receive buffers.
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*/
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unsigned long ulMACBInputLength( void );
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/**
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* \brief Set the MACB Physical address (SA1B & SA1T registers).
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*
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* \param *MACAddress the MAC address to set.
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*/
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void vMACBSetMACAddress(const char * MACAddress);
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/**
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* \brief Disable MACB operations (Tx and Rx).
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*
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* \param *macb Base address of the MACB
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*/
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void vDisableMACBOperations(volatile avr32_macb_t * macb);
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#endif
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