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144 lines
5.7 KiB
C
144 lines
5.7 KiB
C
/*
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FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS books - available as PDF or paperback *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/*
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* This file contains the non-portable and therefore RX62N specific parts of
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* the IntQueue standard demo task - namely the configuration of the timers
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* that generate the interrupts and the interrupt entry points.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Demo includes. */
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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/* Hardware specifics. */
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#include "iodefine.h"
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#define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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#define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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void vInitialiseTimerForIntQueueTest( void )
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{
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/* Ensure interrupts do not start until full configuration is complete. */
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portENTER_CRITICAL();
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{
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/* Cascade two 8bit timer channels to generate the interrupts.
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8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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utilised for this test. */
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/* Enable the timers. */
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SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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/* Enable compare match A interrupt request. */
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TMR0.TCR.BIT.CMIEA = 1;
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TMR2.TCR.BIT.CMIEA = 1;
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/* Clear the timer on compare match A. */
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TMR0.TCR.BIT.CCLR = 1;
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TMR2.TCR.BIT.CCLR = 1;
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/* Set the compare match value. */
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TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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/* 16 bit operation ( count from timer 1,2 ). */
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TMR0.TCCR.BIT.CSS = 3;
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TMR2.TCCR.BIT.CSS = 3;
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/* Use PCLK as the input. */
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TMR1.TCCR.BIT.CSS = 1;
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TMR3.TCCR.BIT.CSS = 1;
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/* Divide PCLK by 8. */
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TMR1.TCCR.BIT.CKS = 2;
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TMR3.TCCR.BIT.CKS = 2;
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/* Enable TMR 0, 2 interrupts. */
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IEN( TMR0, CMIA0 ) = 1;
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IEN( TMR2, CMIA2 ) = 1;
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/* Set the timer interrupts to be above the kernel. The interrupts are
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assigned different priorities so they nest with each other. */
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IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );
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}
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portEXIT_CRITICAL();
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/* Ensure the interrupts are clear as they are edge detected. */
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IR( TMR0, CMIA0 ) = 0;
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IR( TMR2, CMIA2 ) = 0;
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}
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/*-----------------------------------------------------------*/
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#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )
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void vT0_1InterruptHandler( void )
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{
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portYIELD_FROM_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )
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void vT2_3InterruptHandler( void )
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{
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portYIELD_FROM_ISR( xSecondTimerHandler() );
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}
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