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184 lines
8.1 KiB
C
184 lines
8.1 KiB
C
/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
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* File Name : rccu.c
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* Author : MCD Application Team
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* Date First Issued : 07/28/2003
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* Description : This file provides all the RCCU software functions
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********************************************************************************
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* History:
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* 30/11/2004 : V2.0
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* 14/07/2004 : V1.3
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* 01/01/2004 : V1.2
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*******************************************************************************
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THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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#include "rccu.h"
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/*******************************************************************************
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* Function Name : RCCU_PLL1Config
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* Description : Configures the PLL1 div & mul factors.
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* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,
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* RCCU_PLL1_Mul_24 )
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* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
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* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
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* Return : None
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*******************************************************************************/
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void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )
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{
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u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
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RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;
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}
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/*******************************************************************************
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* Function Name : RCCU_PLL2Config
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* Description : Configures the PLL2 div & mul factors.
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* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20,
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* RCCU_Mul_PLL2_28 )
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* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
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* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
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* Return : None
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*******************************************************************************/
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void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div )
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{
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u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
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PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask );
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}
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/*******************************************************************************
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* Function Name : RCCU_RCLKSourceConfig
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* Description : Selects the RCLK source clock
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* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 )
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* Return : None
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*******************************************************************************/
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void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )
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{
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switch ( New_Clock )
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{
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case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag
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RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;
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// Set the CK2_16 Bit in the CFR
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RCCU->CFR |= RCCU_CK2_16_Mask;
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// Deselect The CKAF
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RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
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// switch off the PLL1
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RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
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|0x00000003) & ~RCCU_FREEN_Mask;
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break;}
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case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR
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RCCU->CFR &= ~RCCU_CK2_16_Mask;
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// Deselect The CKAF
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RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
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// switch off the PLL1
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RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
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|0x00000003) & ~RCCU_FREEN_Mask;
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break;}
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case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR
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RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask;
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// Waits the PLL1 to lock if DX bits are different from '111'
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// If all DX bit are set the PLL lock flag in meaningless
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if (( RCCU->PLL1CR & 0x0007 ) != 7)
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while(!(RCCU->CFR & RCCU_LOCK_Mask));
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// Deselect The CKAF
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RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
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// Select The CSU_CKSEL
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RCCU->CFR |= RCCU_CSU_CKSEL_Mask;
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break;}
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case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04;
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break;}
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}
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}
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/*******************************************************************************
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* Function Name : RCCU_RCLKClockSource
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* Description : Returns the current RCLK source clock
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* Input : None
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* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK
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*******************************************************************************/
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RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void )
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{
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if ((RCCU->CCR & 0x04)==0x04)
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return RCCU_RTC_CLOCK;
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else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0)
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return RCCU_CLOCK2_16;
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else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask)
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return RCCU_PLL1_Output;
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else
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return RCCU_CLOCK2;
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}
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/*******************************************************************************
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* Function Name : RCCU_USBClockSource
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* Description : Gets the RCLK source clock
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* Input : None
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* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK )
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*******************************************************************************/
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RCCU_USB_Clocks RCCU_USBClockSource ( void )
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{
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if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 )
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return RCCU_PLL2_Output;
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else return RCCU_USBCK;
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}
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/*******************************************************************************
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* Function Name : RCCU_FrequencyValue
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* Description : Calculates & Returns any internal RCCU clock frequency
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* passed in parametres
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* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK )
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* Return : u32
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*******************************************************************************/
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u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk )
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{
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u32 Tmp;
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u8 Div, Mul;
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RCCU_RCLK_Clocks CurrentRCLK;
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Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc;
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if ( Internal_Clk == RCCU_CLK2 )
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{
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Div = 1;
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Mul = 1;
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}
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else
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{ CurrentRCLK = RCCU_RCLKClockSource ();
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switch ( CurrentRCLK ){
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case RCCU_CLOCK2_16 : Div = 16;
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Mul = 1;
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break;
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case RCCU_CLOCK2 : Div = 1;
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Mul = 1;
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break;
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case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index;
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switch ( Mul )
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{case 0: Mul = 20; break;
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case 1: Mul = 12; break;
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case 2: Mul = 28; break;
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case 3: Mul = 16; break;
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}
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Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1;
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break;}
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case RCCU_RTC_CLOCK : Mul = 1;
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Div = 1;
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Tmp = RCCU_RTC_Osc;
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break;}}
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switch ( Internal_Clk ){
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case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask;
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break;}
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case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index;
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break;}
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case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3;
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break;}}
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return (Tmp * Mul) / Div;
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}
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/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/
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