You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
192 lines
6.7 KiB
C
192 lines
6.7 KiB
C
/*
|
|
FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
|
|
|
|
This file is part of the FreeRTOS.org distribution.
|
|
|
|
FreeRTOS.org is free software; you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation; either version 2 of the License, or
|
|
(at your option) any later version.
|
|
|
|
FreeRTOS.org is distributed in the hope that it will be useful,
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details.
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
along with FreeRTOS.org; if not, write to the Free Software
|
|
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
|
|
A special exception to the GPL can be applied should you wish to distribute
|
|
a combined work that includes FreeRTOS.org, without being obliged to provide
|
|
the source code for any proprietary components. See the licensing section
|
|
of http://www.FreeRTOS.org for full details of how and when the exception
|
|
can be applied.
|
|
|
|
***************************************************************************
|
|
See http://www.FreeRTOS.org for documentation, latest information, license
|
|
and contact details. Please ensure to read the configuration and relevant
|
|
port sections of the online documentation.
|
|
|
|
Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
|
|
with commercial development and support options.
|
|
***************************************************************************
|
|
*/
|
|
|
|
|
|
/*-----------------------------------------------------------
|
|
* Components that can be compiled to either ARM or THUMB mode are
|
|
* contained in port.c The ISR routines, which can only be compiled
|
|
* to ARM mode, are contained in this file.
|
|
*----------------------------------------------------------*/
|
|
|
|
/*
|
|
*/
|
|
|
|
/* Scheduler includes. */
|
|
#include "FreeRTOS.h"
|
|
#include "task.h"
|
|
|
|
/* Constants required to handle critical sections. */
|
|
#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
|
|
|
|
volatile unsigned portLONG ulCriticalNesting = 9999UL;
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* The scheduler can only be started from ARM mode, hence the inclusion of this
|
|
* function here.
|
|
*/
|
|
void vPortISRStartFirstTask( void );
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortISRStartFirstTask( void )
|
|
{
|
|
/* Simply start the scheduler. This is included here as it can only be
|
|
called from ARM mode. */
|
|
asm volatile ( \
|
|
"LDR R0, =pxCurrentTCB \n\t" \
|
|
"LDR R0, [R0] \n\t" \
|
|
"LDR LR, [R0] \n\t" \
|
|
\
|
|
/* The critical nesting depth is the first item on the stack. */ \
|
|
/* Load it into the ulCriticalNesting variable. */ \
|
|
"LDR R0, =ulCriticalNesting \n\t" \
|
|
"LDMFD LR!, {R1} \n\t" \
|
|
"STR R1, [R0] \n\t" \
|
|
\
|
|
/* Get the SPSR from the stack. */ \
|
|
"LDMFD LR!, {R0} \n\t" \
|
|
"MSR SPSR, R0 \n\t" \
|
|
\
|
|
/* Restore all system mode registers for the task. */ \
|
|
"LDMFD LR, {R0-R14}^ \n\t" \
|
|
"NOP \n\t" \
|
|
\
|
|
/* Restore the return address. */ \
|
|
"LDR LR, [LR, #+60] \n\t" \
|
|
\
|
|
/* And return - correcting the offset in the LR to obtain the */ \
|
|
/* correct address. */ \
|
|
"SUBS PC, LR, #4 \n\t" \
|
|
);
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortTickISR( void )
|
|
{
|
|
/* Increment the RTOS tick count, then look for the highest priority
|
|
task that is ready to run. */
|
|
vTaskIncrementTick();
|
|
|
|
#if configUSE_PREEMPTION == 1
|
|
vTaskSwitchContext();
|
|
#endif
|
|
|
|
/* Ready for the next interrupt. */
|
|
TB_ClearITPendingBit( TB_IT_Update );
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* The interrupt management utilities can only be called from ARM mode. When
|
|
* THUMB_INTERWORK is defined the utilities are defined as functions here to
|
|
* ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
|
|
* the utilities are defined as macros in portmacro.h - as per other ports.
|
|
*/
|
|
#ifdef THUMB_INTERWORK
|
|
|
|
void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
|
|
void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
|
|
|
|
void vPortDisableInterruptsFromThumb( void )
|
|
{
|
|
asm volatile (
|
|
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
|
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
|
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
|
|
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
|
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
|
|
"BX R14" ); /* Return back to thumb. */
|
|
}
|
|
|
|
void vPortEnableInterruptsFromThumb( void )
|
|
{
|
|
asm volatile (
|
|
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
|
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
|
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
|
|
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
|
"LDMIA SP!, {R0} \n\t" /* Pop R0. */
|
|
"BX R14" ); /* Return back to thumb. */
|
|
}
|
|
|
|
#endif /* THUMB_INTERWORK */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
|
|
asm volatile (
|
|
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
|
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
|
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
|
|
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
|
"LDMIA SP!, {R0}" ); /* Pop R0. */
|
|
|
|
/* Now interrupts are disabled ulCriticalNesting can be accessed
|
|
directly. Increment ulCriticalNesting to keep a count of how many times
|
|
portENTER_CRITICAL() has been called. */
|
|
ulCriticalNesting++;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
|
|
{
|
|
/* Decrement the nesting count as we are leaving a critical section. */
|
|
ulCriticalNesting--;
|
|
|
|
/* If the nesting level has reached zero then interrupts should be
|
|
re-enabled. */
|
|
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
|
{
|
|
/* Enable interrupts as per portEXIT_CRITICAL(). */
|
|
asm volatile (
|
|
"STMDB SP!, {R0} \n\t" /* Push R0. */
|
|
"MRS R0, CPSR \n\t" /* Get CPSR. */
|
|
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
|
|
"MSR CPSR, R0 \n\t" /* Write back modified value. */
|
|
"LDMIA SP!, {R0}" ); /* Pop R0. */
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|