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171 lines
6.9 KiB
C
171 lines
6.9 KiB
C
/*
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FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details. You should have received a copy of the GNU General Public License
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and the FreeRTOS license exception along with FreeRTOS; if not itcan be
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viewed here: http://www.freertos.org/a00114.html and also obtained by
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writing to Real Time Engineers Ltd., contact details for whom are available
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on the FreeRTOS WEB site.
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, and our new
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fully thread aware and reentrant UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems, who sell the code with commercial support,
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indemnification and middleware, under the OpenRTOS brand.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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*/
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/*
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* This file contains the non-portable and therefore RX62N specific parts of
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* the IntQueue standard demo task - namely the configuration of the timers
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* that generate the interrupts and the interrupt entry points.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Demo includes. */
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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/* Hardware specifics. */
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#include <iorx62n.h>
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#define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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#define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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/* Handlers for the two timers used. */
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__interrupt void vT0_1InterruptHandler( void );
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__interrupt void vT2_3InterruptHandler( void );
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void vInitialiseTimerForIntQueueTest( void )
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{
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/* Ensure interrupts do not start until full configuration is complete. */
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portENTER_CRITICAL();
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{
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/* Cascade two 8bit timer channels to generate the interrupts.
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8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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utilised for this test. */
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/* Enable the timers. */
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SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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/* Enable compare match A interrupt request. */
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TMR0.TCR.BIT.CMIEA = 1;
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TMR2.TCR.BIT.CMIEA = 1;
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/* Clear the timer on compare match A. */
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TMR0.TCR.BIT.CCLR = 1;
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TMR2.TCR.BIT.CCLR = 1;
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/* Set the compare match value. */
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TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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/* 16 bit operation ( count from timer 1,2 ). */
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TMR0.TCCR.BIT.CSS = 3;
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TMR2.TCCR.BIT.CSS = 3;
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/* Use PCLK as the input. */
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TMR1.TCCR.BIT.CSS = 1;
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TMR3.TCCR.BIT.CSS = 1;
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/* Divide PCLK by 8. */
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TMR1.TCCR.BIT.CKS = 2;
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TMR3.TCCR.BIT.CKS = 2;
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/* Enable TMR 0, 2 interrupts. */
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IEN( TMR0, CMIA0 ) = 1;
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IEN( TMR2, CMIA2 ) = 1;
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/* Set the timer interrupts to be above the kernel. The interrupts are
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assigned different priorities so they nest with each other. */
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IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );
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}
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portEXIT_CRITICAL();
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/* Ensure the interrupts are clear as they are edge detected. */
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IR( TMR0, CMIA0 ) = 0;
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IR( TMR2, CMIA2 ) = 0;
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}
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/*-----------------------------------------------------------*/
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#pragma vector = VECT_TMR0_CMIA0
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__interrupt void vT0_1InterruptHandler( void )
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{
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__enable_interrupt();
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portYIELD_FROM_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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#pragma vector = VECT_TMR2_CMIA2
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__interrupt void vT2_3InterruptHandler( void )
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{
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__enable_interrupt();
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portYIELD_FROM_ISR( xSecondTimerHandler() );
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}
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