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205 lines
12 KiB
C
205 lines
12 KiB
C
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*******************************************************************************/
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/*
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* cgc.h
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*
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* Created on: 01 Oct 2011
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* Author: RJW
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* Reneses Electronics Europe Ltd
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*/
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#ifndef CGC_H_
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#define CGC_H_
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/******************************************************************************
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Function Prototypes
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******************************************************************************/
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void InitCGC(void);
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/*****************************************************************************/
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/* */
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/* Set the CGC (Clock Generation Circuit of the RX630 using the */
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/* following 7 STEPS */
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/* */
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/*****************************************************************************/
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/*****************************************************************************/
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/* */
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/* STEP 1: System Clock Options */
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/* */
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/* Enter one of the CLK_SOURCE_ options into the */
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/* */
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/* #define CLK_SOURCE ( xxx ) */
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/* below. */
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/* This will be the clock source that the device will switch to as part of */
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/* HardwareSetup() */
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/* Extra clocks can be enabled in STEP 3. */
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/* */
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/* For example */
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/* #define CLK_SOURCE (CLK_SOURCE_MAIN) */
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/* */
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/*****************************************************************************/
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#define CLK_SOURCE_LOCO 0x0000
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#define CLK_SOURCE_HOCO 0x0100
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#define CLK_SOURCE_MAIN 0x0200
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#define CLK_SOURCE_SUB 0x0300
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#define CLK_SOURCE_PLL 0x0400
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#define CLK_SOURCE (CLK_SOURCE_PLL)
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/*****************************************************************************/
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/* */
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/* STEP 2: External XTAL values */
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/* */
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/* If using the CLK_SOURCE_MAIN, CLK_SOURCE_SUB, CLK_SOURCE_PLL */
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/* enter the MAIN XTAL and SUB XTAL values here. */
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/* */
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/* If using the PLL, enter the PLL multiplier and PLL frequency divder */
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/* Use the divider so that the input frequency into the PLL is in */
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/* the range of 4 MHz to 16 MHz. */
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/* */
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/* Use the multiplier so that the output frequency of the PLL is in */
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/* the range of 104MHz to 200Mhz */
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/* */
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/* The PLL frequency divider values are: */
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/* /1, /2, /4 */
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/* The PLL muliplier values are: */
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/* x8, x10, x12, x16, x20, x24, x25, x50 */
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/* */
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/* Example: */
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/* XTAL = 12MHz */
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/* PLL Divider = 1 */
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/* */
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/* Therefore, input into PLL = 12M / 1 */
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/* = 12M */
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/* PLL Multipler = 16 */
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/* */
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/* Therefore, ouput of PLL = 12M x 16 */
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/* = 192M */
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/* */
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/* NOTE: The maximum XTAL is 20MHz */
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/*****************************************************************************/
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#define XTAL_FREQUENCY (12000000L)
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#define PLL_MUL (16)
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#define PLL_INPUT_FREQ_DIV (1)
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#define SUB_FREQUENCY (32768L)
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/*****************************************************************************/
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/* */
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/* STEP 3: Enable the chosen clock source and any extra clock sources */
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/* Remeber to enable the clock source chosen in STEP 1. */
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/* Foe example, if CLK_SOURCE_PLL has been chosen, set */
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/* #define ENABLE_PLL (1) */
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/* */
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/*****************************************************************************/
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#define ENABLE_HOCO (1)
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#define ENABLE_SUB (0)
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#define ENABLE_MAIN (0)
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#define ENABLE_PLL (1)
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/*****************************************************************************/
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/* */
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/* STEP 4: */
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/* Enter the Clock Divders for */
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/* - FCLK_DIV, ICLK_DIV, BCLK_DIV, PCLKA_DIV, PCLKB_DIV */
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/* Valid values are 1, 2, 4, 8, 16, 32 and 64 */
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/* */
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/* The Clock Value being divided is: */
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/* If LOCO, 125kHz */
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/* If HOCO, 50MHz */
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/* If SUB, the value of SUB specified in STEP 2 */
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/* If MAIN, the value of XTAL specified in STEP 2 */
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/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */
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/*****************************************************************************/
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#define FCLK_DIV (4)
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#define ICLK_DIV (2)
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#define BCLK_DIV (4)
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#define PCLK1215_DIV (2) /* Do not change this */
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#define PCLKB_DIV (4)
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#define PCLK47_DIV (2) /* Do not change this */
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#define PCLK03_DIV (2) /* Do not change this */
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/*****************************************************************************/
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/* */
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/* STEP 5: */
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/* Enter the Clock Divder for */
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/* - IEBCK_DIV */
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/* Valid values are 2, 4, 6, 8, 16, 32 and 64 */
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/* */
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/* The Clock Value being divided is: */
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/* If LOCO, 125kHz */
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/* If HOCO, 50MHz */
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/* If SUB, the value of SUB specified in STEP 2 */
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/* If MAIN, the value of XTAL specified in STEP 2 */
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/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */
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/*****************************************************************************/
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#define IEBCK_DIV (2)
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/*****************************************************************************/
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/* */
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/* STEP 6: */
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/* Enter the Clock Divder for */
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/* - UCK_DIV */
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/* Valid values are 3, 4 */
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/* */
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/* The Clock Value being divided is: */
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/* If LOCO, 125kHz */
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/* If HOCO, 50MHz */
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/* If SUB, the value of SUB specified in STEP 2 */
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/* If MAIN, the value of XTAL specified in STEP 2 */
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/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */
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/*****************************************************************************/
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#define UCK_DIV (3)
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/*****************************************************************************/
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/* */
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/* STEP 7: */
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/* Specify the use of BCLK pin */
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/* To ENABLE, set to (0) */
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/* To DISABLE, set to (1) */
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/* */
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/*****************************************************************************/
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#define BCLK_PIN (1)
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/*****************************************************************************/
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/* Clock configuration is now complete. */
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/*****************************************************************************/
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#include "cgc_set.h"
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#include "cgc_error.h"
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#endif |